Index: CADR4/AMEM.v ================================================================== --- CADR4/AMEM.v +++ CADR4/AMEM.v @@ -35,12 +35,32 @@ localparam DATA_WIDTH = 32; localparam MEM_DEPTH = 1024; //////////////////////////////////////////////////////////////////////////////// -`ifdef SIMULATION - reg [31:0] ram [0:1023]; +`ifdef ISE + wire ena_a = arp | 1'b0; + wire ena_b = 1'b0 | awp; + + + ise_AMEM inst + ( + .clka(clk), + .ena(ena_a), + .wea(1'b0), + .addra(aadr), + .dina(32'b0), + .douta(amem), + .clkb(clk), + .enb(ena_b), + .web(awp), + .addrb(aadr), + .dinb(l), + .doutb() + /*AUTOINST*/); +`elsif SIMULATION + reg [31:0] ram [0:1023]; reg [31:0] out_a; reg [31:0] out_b; assign amem = out_a; @@ -63,32 +83,29 @@ out_b <= 0; else if (1'b0) begin out_b <= ram[aadr]; end `else - wire ena_a = arp | 1'b0; - wire ena_b = 1'b0 | awp; - - ise_AMEM inst - ( - .clka(clk), - .ena(ena_a), - .wea(1'b0), - .addra(aadr), - .dina(32'b0), - .douta(amem), - .clkb(clk), - .enb(ena_b), - .web(awp), - .addrb(aadr), - .dinb(l), - .doutb() - /*AUTOINST*/); + reg [31:0] ram [0:1023]; + reg [31:0] out_a; + + assign amem = out_a; + + always @(posedge clk) + if (awp) begin + ram[aadr] <= l; + end + + always @(posedge clk) begin + if (arp) begin + out_a <= ram[aadr]; + end + end `endif endmodule `default_nettype wire // Local Variables: // verilog-library-directories: (".." "../cores/xilinx") // End: Index: CADR4/DRAM.v ================================================================== --- CADR4/DRAM.v +++ CADR4/DRAM.v @@ -54,12 +54,31 @@ assign daddr0 = (ir[8] & vmo[18]) | (ir[9] & vmo[19]) | (dmask[0] & r[0]) | (ir[12]); assign dadr = {ir[22:13], daddr0} | ({4'b0000, dmask[6:1], 1'b0} & {4'b0000, r[6:1], 1'b0}); assign dwe = dispwr & state_write; -`ifdef SIMULATION - reg [16:0] ram [0:2047]; +`ifdef ISE + wire ena_a = ~state_prefetch && ~dwe | 1'b0; + wire ena_b = 1'b0 | dwe; + + ise_DRAM inst + ( + .clka(clk), + .ena(ena_a), + .wea(1'b0), + .addra(dadr), + .dina(17'b0), + .douta({dr, dp, dn, dpc}), + .clkb(clk), + .enb(ena_b), + .web(dwe), + .addrb(dadr), + .dinb(a[16:0]), + .doutb() + /*AUTOINST*/); +`elsif SIMULATION + reg [16:0] ram [0:2047]; reg [16:0] out_a; reg [16:0] out_b; assign {dr,dp,dn,dpc} = out_a; @@ -82,33 +101,33 @@ if (reset) out_b <= 0; else if (1'b0) begin out_b <= ram[dadr]; end -`else - wire ena_a = ~state_prefetch && ~dwe | 1'b0; - wire ena_b = 1'b0 | dwe; - - ise_DRAM inst - ( - .clka(clk), - .ena(ena_a), - .wea(1'b0), - .addra(dadr), - .dina(17'b0), - .douta({dr, dp, dn, dpc}), - .clkb(clk), - .enb(ena_b), - .web(dwe), - .addrb(dadr), - .dinb(a[16:0]), - .doutb() - /*AUTOINST*/); +`else // ALTERA + reg [16:0] ram [0:2047]; + reg [16:0] out_a; + reg [16:0] out_b; + + assign {dr,dp,dn,dpc} = out_a; + wire en_rd = ~state_prefetch && ~dwe; + + always @(posedge clk) begin + if (dwe) begin + ram[dadr] <= a[16:0]; + end + end + + always @(posedge clk) begin + if (en_rd) begin + out_a <= ram[dadr]; + end + end `endif endmodule `default_nettype wire // Local Variables: // verilog-library-directories: (".." "../cores/xilinx") // End: Index: CADR4/IRAML/IRAM.v ================================================================== --- CADR4/IRAML/IRAM.v +++ CADR4/IRAML/IRAM.v @@ -32,29 +32,65 @@ module IRAM(/*AUTOARG*/ // Outputs iram, // Inputs clk, reset, pc, iwr, iwe + `ifdef EXTERNAL_MCR + mcr_addr, mcr_data_in, mcr_data_out, mcr_ready, mcr_write + `endif ); - + input clk; input reset; input [13:0] pc; input [48:0] iwr; input iwe; output [48:0] iram; - //////////////////////////////////////////////////////////////////////////////// - + //////////////////////////////////////////////////////////////////////////////// localparam ADDR_WIDTH = 14; localparam DATA_WIDTH = 49; localparam MEM_DEPTH = 16384; - //////////////////////////////////////////////////////////////////////////////// -`ifdef SIMULATION + + /// +`ifdef EXTERNAL_MCR + // microcode address + output [13:0] mcr_addr; + // microcode data output: write to external memory + output [48:0] mcr_data_out; + // microcode data input: read from external memory + input [48:0] mcr_data_in; + // is microcode ready? + input mcr_ready; + // are we writing to microcode ram? + output mcr_write; + // ??? + input mcr_done; + + // holding register to hold IRAM output data in + reg [48:0] out_mcr; + + // IRAM data + assign iram = out_mcr; + + // read + always @(posedge clk) begin + out_mcr <= mcr_data_in; + mcr_addr <= pc; + end + // write + always @(posedge clk) begin + mcr_write <= iwe; + if (iwe) begin + mcr_data_out <= iwr; + end + end + +`elsif SIMULATION reg [48:0] ram [0:MEM_DEPTH-1]; reg [48:0] out_a; assign iram = out_a; @@ -65,12 +101,13 @@ ram[pc] <= iwr; end always @(posedge clk) if (1'b1) begin + out_a <= ram[pc]; end -`else +`elsif ISE wire ena_a = 1'b1 | iwe; ise_IRAM inst ( .clka(clk), @@ -78,14 +115,28 @@ .wea(iwe), .addra(pc), .dina(iwr), .douta(iram) /*AUTOINST*/); +`else + reg [48:0] ram [0:MEM_DEPTH-1]; + reg [48:0] out_a; + + assign iram = out_a; + + + /* synthesis syn_ramstyle="block_ram" */ + always @(posedge clk) begin + if (iwe) begin + ram[pc] <= iwr; + end + out_a <= ram[pc]; + end `endif endmodule `default_nettype wire // Local Variables: // verilog-library-directories: ("../.." "../../cores/xilinx") // End: Index: CADR4/MD.v ================================================================== --- CADR4/MD.v +++ CADR4/MD.v @@ -66,11 +66,11 @@ md[31:16] <= spy_in; else if (ldmdl) md[15:0] <= spy_in; assign mddrive = srcmd & (state_alu || state_write || state_mmu || state_fetch); - assign mdgetspar = ~destmdr & ~ignpar; + //assign mdgetspar = (~destmdr) & (~ignpar); assign ignpar = 1'b0; assign mdclk = loadmd | destmdr; endmodule Index: CADR4/MMEM.v ================================================================== --- CADR4/MMEM.v +++ CADR4/MMEM.v @@ -34,12 +34,32 @@ localparam DATA_WIDTH = 32; localparam MEM_DEPTH = 32; //////////////////////////////////////////////////////////////////////////////// -`ifdef SIMULATION - reg [31:0] ram [0:31]; +`ifdef ISE + wire ena_a = mrp | 1'b0; + wire ena_b = 1'b0 | mwp; + + ise_MMEM inst + ( + .clka(clk), + .ena(ena_a), + .wea(1'b0), + .addra(madr), + .dina(32'b0), + .douta(mmem), + .clkb(clk), + .enb(ena_b), + .web(mwp), + .addrb(madr), + .dinb(l), + .doutb() + /*AUTOINST*/); + +`elsif SIMULATION + reg [31:0] ram [0:31]; reg [31:0] out_a; reg [31:0] out_b; assign mmem = out_a; @@ -62,29 +82,29 @@ if (reset) out_b <= 0; else if (1'b0) begin out_b <= ram[madr]; end -`else - wire ena_a = mrp | 1'b0; - wire ena_b = 1'b0 | mwp; - - ise_MMEM inst - ( - .clka(clk), - .ena(ena_a), - .wea(1'b0), - .addra(madr), - .dina(32'b0), - .douta(mmem), - .clkb(clk), - .enb(ena_b), - .web(mwp), - .addrb(madr), - .dinb(l), - .doutb() - /*AUTOINST*/); +`else // ALTERA + + reg [31:0] ram [0:31]; + reg [31:0] out_a; + + assign mmem = out_a; + initial out_a = 0; + + always @(posedge clk) begin + if (mwp) begin + ram[madr] <= l; + end + end + + always @(posedge clk) begin + if (mrp) begin + out_a <= ram[madr]; + end + end `endif endmodule Index: CADR4/PDL.v ================================================================== --- CADR4/PDL.v +++ CADR4/PDL.v @@ -35,17 +35,55 @@ localparam DATA_WIDTH = 32; localparam MEM_DEPTH = 1024; //////////////////////////////////////////////////////////////////////////////// -`ifdef SIMULATION - reg [31:0] ram [0:1023]; +`ifdef ISE + wire ena_a = prp | 1'b0; + wire ena_b = 1'b0 | pwp; + + ise_PDL inst + ( + .clka(clk), + .ena(ena_a), + .wea(1'b0), + .addra(pdla), + .dina(32'b0), + .douta(pdlo), + .clkb(clk), + .enb(ena_b), + .web(pwp), + .addrb(pdla), + .dinb(l), + .doutb() + /*AUTOINST*/); +`else + reg [31:0] ram [0:1023]; + reg [31:0] out_a; + reg [31:0] out_b; + + initial out_a = 0; + assign pdlo = out_a; + + wire p_en = pwp | prp; + + always @(posedge clk) begin + if (p_en) begin + if (pwp) begin + ram[pdla] <= l; + end + out_a <= ram[pdla]; + end + end + + /* + reg [31:0] ram [0:1023]; reg [31:0] out_a; reg [31:0] out_b; assign pdlo = out_a; - + always @(posedge clk) if (1'b0) begin ram[pdla] <= 32'b0; end else if (pwp) begin ram[pdla] <= l; @@ -62,33 +100,15 @@ if (reset) out_b <= 0; else if (1'b0) begin out_b <= ram[pdla]; end -`else - wire ena_a = prp | 1'b0; - wire ena_b = 1'b0 | pwp; - - ise_PDL inst - ( - .clka(clk), - .ena(ena_a), - .wea(1'b0), - .addra(pdla), - .dina(32'b0), - .douta(pdlo), - .clkb(clk), - .enb(ena_b), - .web(pwp), - .addrb(pdla), - .dinb(l), - .doutb() - /*AUTOINST*/); + */ `endif endmodule `default_nettype wire // Local Variables: // verilog-library-directories: (".." "../cores/xilinx") // End: Index: CADR4/SPC.v ================================================================== --- CADR4/SPC.v +++ CADR4/SPC.v @@ -46,18 +46,37 @@ wire [4:0] spcptr_p1; assign spcptr_p1 = spcptr + 5'b00001; assign spcadr = (spcnt && spush) ? spcptr_p1 : spcptr; -`ifdef SIMULATION +`ifndef ISE reg [18:0] ram [0:31]; reg [18:0] out_a; reg [18:0] out_b; + + reg swp_cond; + + always @(posedge clk) begin + swp_cond <= (swp && spcadr == spcptr); + out_b <= spcw; + end + + assign spco = (swp_cond) ? out_a : out_b; - assign spco = out_a; + always @(posedge clk) begin + if (swp) begin + ram[spcadr] <= spcw; + end + end - + always @(posedge clk) begin + if (srp) begin + out_a <= ram[spcptr]; + end + end + + /* always @(posedge clk) if (1'b0) begin ram[spcptr] <= 19'b0; end else if (swp) begin ram[spcadr] <= spcw; @@ -65,25 +84,19 @@ always @(posedge clk) if (reset) out_a <= 0; else if (srp && ~swp) begin - /* WE NEED 'READ NEW DATA' ON SIMULTANEOUS WRITE/READ TO SAME ADDR */ + / * WE NEED 'READ NEW DATA' ON SIMULTANEOUS WRITE/READ TO SAME ADDR * / if (swp && spcadr == spcptr) begin out_a <= spcw; end else begin out_a <= ram[spcptr]; end end - - always @(posedge clk) - if (reset) - out_b <= 0; - else if (1'b0) - begin - out_b <= ram[spcadr]; - end + */ + `else wire ena_a = srp && ~swp | 1'b0; wire ena_b = 1'b0 | swp; ise_SPC inst Index: CADR4/VMEM0.v ================================================================== --- CADR4/VMEM0.v +++ CADR4/VMEM0.v @@ -41,39 +41,11 @@ //////////////////////////////////////////////////////////////////////////////// assign vmem0_adr = mapi[23:13]; -`ifdef SIMULATION - reg [4:0] ram [0:2047]; - reg [4:0] out_a; - reg [4:0] out_b; - - assign vmap = out_a; - - - always @(posedge clk) - if (1'b0) begin - ram[vmem0_adr] <= 5'b0; - end else if (vm0wp) begin - ram[vmem0_adr] <= vma[31:27]; - end - - always @(posedge clk) - if (reset) - out_a <= 0; - else if (vm0rp && ~vm0wp) begin - out_a <= ram[vmem0_adr]; - end - - always @(posedge clk) - if (reset) - out_b <= 0; - else if (1'b0) begin - out_b <= ram[vmem0_adr]; - end -`else +`ifdef ISE wire ena_a = vm0rp && ~vm0wp | 1'b0; wire ena_b = 1'b0 | vm0wp; ise_VMEM0 inst ( @@ -88,10 +60,31 @@ .web(vm0wp), .addrb(vmem0_adr), .dinb(vma[31:27]), .doutb() /*AUTOINST*/); + +`else + + reg [4:0] ram [0:2047]; + reg [4:0] out_a; + initial out_a = 0; + + assign vmap = out_a; + + wire [4:0] vma_in = vma[31:27]; + wire vma_en = vm0rp | vm0wp; + + always @(posedge clk) begin + if (vma_en) begin + if (vm0wp) begin + ram[vmem0_adr] <= vma_in; + end + out_a <= ram[vmem0_adr]; + end + end + `endif assign use_map = srcmap | memstart; endmodule Index: CADR4/VMEM1.v ================================================================== --- CADR4/VMEM1.v +++ CADR4/VMEM1.v @@ -41,40 +41,11 @@ //////////////////////////////////////////////////////////////////////////////// assign vmem1_adr = {vmap[4:0], mapi[12:8]}; -`ifdef SIMULATION - reg [23:0] ram [0:1023]; - reg [23:0] out_a; - reg [23:0] out_b; - - assign vmo = out_a; - - - always @(posedge clk) - if (1'b0) begin - ram[vmem1_adr] <= 24'b0; - end - else if (vm1wp) begin - ram[vmem1_adr] <= vma[23:0]; - end - - always @(posedge clk) - if (reset) - out_a <= 0; - else if (vm1rp && ~vm1wp) begin - out_a <= ram[vmem1_adr]; - end - - always @(posedge clk) - if (reset) - out_b <= 0; - else if (1'b0) begin - out_b <= ram[vmem1_adr]; - end -`else +`ifdef ISE wire ena_a = vm1rp && ~vm1wp | 1'b0; wire ena_b = 1'b0 | vm1wp; ise_VMEM1 inst ( @@ -89,14 +60,31 @@ .web(vm1wp), .addrb(vmem1_adr), .dinb(vma[23:0]), .doutb() /*AUTOINST*/); +`else + reg [23:0] ram [0:1023]; + reg [23:0] out_a; + + assign vmo = out_a; + wire vm1_en = vm1rp | vm1wp; + initial out_a = 0; + + always @(posedge clk) begin + if (vm1_en) begin + if (vm1wp) begin + ram[vmem1_adr] <= vma[23:0]; + end + out_a <= ram[vmem1_adr]; + end + end + `endif endmodule `default_nettype wire // Local Variables: // verilog-library-directories: (".." "../cores/xilinx") // End: ADDED block_dev_mister.sv Index: block_dev_mister.sv ================================================================== --- /dev/null +++ block_dev_mister.sv @@ -0,0 +1,748 @@ +/******************************************************************************* + * Engineer: Nicholas Nusgart + * Design Name: LM-3 CADR implementation + * Module Name: ram_controller_mister + * Project Name: LM-3 + * Description: This module is acts as the memory controller for the LM-3. It + acts as the interface from the LM-3 sdram bus to the MiSTer's + DDR3 and from the LM-3 vram bus to the VRAM (implemented as + block ram). + * Dependencies: alt_vram + * Revision: + * Revision 0.01 - File Created + * Additional Comments: +******************************************************************************/ + + +// block_dev_mmc.v --- ---!!! + +`timescale 1ns/1ps +`default_nettype none + +module block_dev_mister( + /// system + input wire clk, + input wire reset, + + /// block-device interface + // command + input [1:0] bd_cmd, + input bd_rd, + input bd_start, + input bd_wr, + // addr & data + input [23:0] bd_addr, + input [15:0] bd_data_in, + output [15:0] bd_data_out, + // status + output [11:0] bd_state, + output bd_bsy, + output bd_err, + output bd_iordy, + output bd_rdy, + + // MMC interface + input mmc_di, + input mmcclk, + output mmc_cs, + output mmc_do, + output mmc_sclk + ); + + + + //////////////////////////////////////////////////////////////////////////////// + + parameter + CMD01 = 48'h400000000095, + CMD02 = 48'h410000000001, + CMD16 = 48'h500000000001, + CMD17 = 48'h510000000001; + parameter [6:0] + s_idle = 0, + s_busy = 1, + s_init0 = 4, + s_init1 = 5, + s_init2 = 6, + s_init3 = 7, + s_init4 = 8, + s_init5 = 9, + s_read0 = 10, + s_read1 = 11, + s_read2 = 12, + s_read3 = 13, + s_read4 = 14, + s_read5 = 15, + s_read6 = 16, + s_write0 = 20, + s_write1 = 21, + s_write2 = 22, + s_write2aa = 19, + s_write2ab = 17, + s_write3 = 23, + s_write4 = 24, + s_write5 = 25, + s_write5a = 18, + s_write6 = 26, + s_write7 = 27, + s_done0 = 28, + s_reset = 29, + s_reset0 = 30, + s_reset1 = 31, + s_reset2 = 32, + s_reset3 = 33, + s_reset4 = 34, + s_reset5 = 35, + s_reset6 = 36, + s_reset7 = 37, + s_reset8 = 38, + s_reset9 = 39, + s_reset10 = 40, + s_reset11 = 41, + s_reset1a = 42, + s_reset2a = 43, + s_reset3a = 44, + s_reset4a = 45, + s_reset5a = 46, + s_reset6a = 47, + s_reset7a = 48, + s_reset8a = 49, + s_reset9a = 50, + s_reset10a = 51, + s_init0a = 52, + s_init1a = 53, + s_init2a = 54, + s_init4a = 55, + s_init5a = 56, + s_read0a = 57, + s_read1a = 58, + s_read3a = 59, + s_read4a = 60, + s_read5a = 61, + s_write1a = 62, + s_write2a = 63, + s_write3a = 64, + s_write4a = 65, + s_write5aa = 66, + s_write5b = 67, + s_write6a = 68; + + reg [15:0] data_hold; + reg [15:0] mmc_hold; + reg [1:0] bc; + reg [1:0] bd_cmd_hold; + reg [1:0] r_bd_cmd; + reg [31:0] lba32; + reg [47:0] mmc_cmd; + reg [6:0] state; + reg [6:0] state_next; + reg [7:0] mmc_in; + reg [7:0] wc; + reg clear_bc; + reg clear_err; + reg clear_wc; + reg err; + reg inc_bc; + reg inc_lba; + reg inc_wc; + reg inited; + reg mmc_hispeed; + reg mmc_init; + reg mmc_lospeed; + reg mmc_rd; + reg mmc_send; + reg mmc_speed; + reg mmc_stop; + reg mmc_wr; + reg r_bd_start; + reg set_err; + reg set_inited; + + wire [3:0] mmc_state; + wire [4:0] mmc_active; + wire [7:0] mmc_out; + wire mmc_done; + + /*AUTOWIRE*/ + /*AUTOREG*/ + + //////////////////////////////////////////////////////////////////////////////// + + mmc_wrapper mmc_wrapper + ( + .mmc_clk(mmcclk), + .speed(mmc_speed), + .wr(mmc_wr), + .rd(mmc_rd), + .init(mmc_init), + .send(mmc_send), + .stop(mmc_stop), + .cmd(mmc_cmd), + .data_in(mmc_in), + .data_out(mmc_out), + .done(mmc_done), + .state_out(mmc_state), + /*AUTOINST*/ + // Outputs + .mmc_cs (mmc_cs), + .mmc_do (mmc_do), + .mmc_sclk (mmc_sclk), + // Inputs + .clk (clk), + .mmc_di (mmc_di), + .reset (reset)); + + assign bd_iordy = (state == s_read2) || + (state == s_write2aa) || + (state == s_write2ab); + assign bd_rdy = + (state == s_idle) || + (state == s_read0) || (state == s_read1) || (state == s_read2) || + (state == s_write0) || (state == s_write1) || + (state == s_done0); + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + data_hold <= 16'h0; + // End of automatics + end else if (state == s_write0 && bd_wr) begin + data_hold <= bd_data_in; + end + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + mmc_hold <= 16'h0; + // End of automatics + end else if (mmc_done) begin + if (state == s_read0a) + mmc_hold[7:0] <= mmc_out; + else if (state == s_read1a) + mmc_hold[15:8] <= mmc_out; + else if (state == s_reset2 || state == s_reset4 || state == s_reset6 || + state == s_init2 || state == s_write5 || state == s_write5a) + mmc_hold[7:0] <= mmc_out; + end + + assign bd_data_out = mmc_hold; + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + wc <= 8'h0; + // End of automatics + end else if (clear_wc) + wc <= 8'b0; + else if (inc_wc) + wc <= wc + 8'b00000001; + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + bc <= 2'h0; + // End of automatics + end else if (clear_bc) + bc <= 2'b0; + else if (inc_bc) + bc <= bc + 2'b01; + + assign bd_bsy = state != s_idle ? 1'b1 : 1'b0; + assign bd_err = err; + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + lba32 <= 32'h0; + // End of automatics + end else begin + if (inc_lba) + lba32 <= lba32 + 32'd512; + else if (bd_start) + lba32 <= { bd_addr[22:0], 9'b0 }; + end + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + r_bd_cmd <= 2'h0; + r_bd_start <= 1'h0; + // End of automatics + end else begin + r_bd_cmd <= bd_cmd; + r_bd_start <= bd_start; + end + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + inited <= 1'h0; + // End of automatics + end else if (set_inited) + inited <= 1; + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + bd_cmd_hold <= 2'h0; + // End of automatics + end else if (bd_start) + bd_cmd_hold <= r_bd_cmd; + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + err <= 1'h0; + // End of automatics + end else if (clear_err) + err <= 1'b0; + else if (set_err) + err <= 1'b1; + + always @(posedge clk) + if (reset) + state <= s_idle; + else begin + state <= state_next; + end + + assign mmc_active = { mmc_speed, mmc_state }; + assign bd_state = { mmc_active, state }; + + always @(state or r_bd_cmd or bd_cmd_hold or r_bd_start or bd_rd or bd_wr or mmc_done or mmc_out or mmc_hold or bd_data_out) begin + state_next = state; + mmc_cmd = 0; + mmc_rd = 0; + mmc_wr = 0; + mmc_init = 0; + mmc_send = 0; + mmc_stop = 0; + mmc_in = 0; + mmc_hispeed = 0; + mmc_lospeed = 0; + clear_err = 0; + set_err = 0; + clear_wc = 0; + inc_wc = 0; + clear_bc = 0; + inc_bc = 0; + inc_lba = 0; + set_inited = 0; + case (state) + s_idle: begin + if (r_bd_start) begin + case (r_bd_cmd) + 2'b00: begin + state_next = s_reset; + end + 2'b01: begin + state_next = s_init0; + end + 2'b10: begin + state_next = s_init0; + end + 2'b11: + ; + endcase + end + end + s_busy: begin + state_next = s_idle; + end + s_reset: begin + mmc_lospeed = 1; + mmc_init = 1; + if (~mmc_done) + state_next = s_reset0; + end + s_reset0: begin + if (mmc_done) + state_next = s_reset1; + end + s_reset1: begin + mmc_send = 1; + mmc_cmd = CMD01; + if (~mmc_done) + state_next = s_reset1a; + end + s_reset1a: begin + if (mmc_done) + state_next = s_reset2; + end + s_reset2: begin + mmc_rd = 1; + if (~mmc_done) + state_next = s_reset2a; + end + s_reset2a: begin + if (mmc_done) begin + if (mmc_out == 8'h01) + state_next = s_reset3; + else if (mmc_out[7] == 1'b0) + state_next = s_reset; + else + state_next = s_reset2; + end + end + s_reset3: begin + mmc_stop = 1; + if (~mmc_done) + state_next = s_reset3a; + end + s_reset3a: begin + if (mmc_done) + state_next = s_reset4; + end + s_reset4: begin + mmc_send = 1; + mmc_cmd = CMD02; + if (~mmc_done) + state_next = s_reset4a; + end + s_reset4a: begin + if (mmc_done) + state_next = s_reset5; + end + s_reset5: begin + mmc_rd = 1; + if (~mmc_done) + state_next = s_reset5a; + end + s_reset5a: begin + if (mmc_done) begin + if (mmc_out == 8'h00) + state_next = s_reset7; + else if (mmc_out != 8'hff) + state_next = s_reset6; + else + state_next = s_reset5; + end + end + s_reset6: begin + mmc_stop = 1; + if (~mmc_done) + state_next = s_reset6a; + end + s_reset6a: begin + if (mmc_done) + state_next = s_reset4; + end + s_reset7: begin + mmc_stop = 1; + if (~mmc_done) + state_next = s_reset7a; + end + s_reset7a: begin + if (mmc_done) + state_next = s_reset8; + end + s_reset8: begin + mmc_hispeed = 1; + mmc_send = 1; + mmc_cmd = { 8'h50, 32'd512, 8'h01 }; + if (~mmc_done) + state_next = s_reset8a; + end + s_reset8a: begin + if (mmc_done) + state_next = s_reset9; + end + s_reset9: begin + mmc_rd = 1; + if (~mmc_done) + state_next = s_reset9a; + end + s_reset9a: begin + if (mmc_done) begin + if (mmc_out == 8'h00) + state_next = s_reset10; + else + state_next = s_reset9; + end + end + s_reset10: begin + mmc_stop = 1; + if (~mmc_done) + state_next = s_reset10a; + end + s_reset10a: begin + if (mmc_done) + state_next = s_reset11; + end + s_reset11: begin + set_inited = 1; + if (~inited && bd_cmd_hold != 2'b00) + state_next = s_init0; + else + state_next = s_busy; + end + s_init0: begin + if (~inited) + state_next = s_reset; + else + begin + mmc_send = 1; + mmc_cmd = { 8'hff, 8'hff, 8'hff, 8'hff, 8'hff, 8'hff }; + if (~mmc_done) + state_next = s_init0a; + end + end + s_init0a: begin + if (mmc_done) + state_next = s_init1; + end + s_init1: begin + mmc_send = 1; + mmc_cmd = bd_cmd_hold == 2'b10 ? { 8'h58, lba32, 8'h01 } : + bd_cmd_hold == 2'b01 ? { 8'h51, lba32, 8'h01 } : + 48'b0; + if (~mmc_done) + state_next = s_init1a; + end + s_init1a: begin + if (mmc_done) + state_next = s_init2; + end + s_init2: begin + mmc_rd = 1; + if (~mmc_done) + state_next = s_init2a; + end + s_init2a: begin + if (mmc_done) begin + if (mmc_out == 8'hff) + state_next = s_init2; + else if (mmc_out == 8'h00) + state_next = s_init3; + else begin + set_err = 1; + state_next = s_done0; + end + end + end + s_init3: begin + clear_wc = 1; + if (bd_cmd_hold == 2'b10) + state_next = s_init5; + else if (bd_cmd_hold == 2'b01) + state_next = s_init4; + end + s_init4: begin + mmc_rd = 1; + if (~mmc_done) + state_next = s_init4a; + end + s_init4a: begin + if (mmc_done) begin + if (mmc_out == 8'hff) + state_next = s_init4; + else if (mmc_out == 8'hfe) + state_next = s_read0; + end + end + s_init5: begin + mmc_wr = 1; + mmc_in = 8'hfe; + if (~mmc_done) + state_next = s_init5a; + end + s_init5a: begin + if (mmc_done) + state_next = s_write0; + end + s_read0: begin + mmc_rd = 1; + if (~mmc_done) + state_next = s_read0a; + end + s_read0a: begin + if (mmc_done) + state_next = s_read1; + end + s_read1: begin + mmc_rd = 1; + if (~mmc_done) + state_next = s_read1a; + end + s_read1a: begin + if (mmc_done) + state_next = s_read2; + end + s_read2: begin + if (bd_rd) begin + inc_wc = 1; + if (wc == 8'hff) + state_next = s_read3; + else + state_next = s_read0; + end + end + s_read3: begin + mmc_rd = 1; + if (~mmc_done) + state_next = s_read3a; + end + s_read3a: begin + if (mmc_done) + state_next = s_read4; + end + s_read4: begin + mmc_rd = 1; + if (~mmc_done) + state_next = s_read4a; + end + s_read4a: begin + if (mmc_done) + state_next = s_read5; + end + s_read5: begin + mmc_stop = 1; + if (~mmc_done) + state_next = s_read5a; + end + s_read5a: begin + if (mmc_done) + state_next = s_read6; + end + s_read6: begin + inc_bc = 1; + inc_lba = 1; + if (bc == 2'h01) + state_next = s_done0; + else + state_next = s_init0; + end + s_write0: begin + if (bd_wr) + state_next = s_write1; + end + s_write1: begin + mmc_wr = 1; + mmc_in = data_hold[7:0]; + if (~mmc_done) + state_next = s_write1a; + end + s_write1a: begin + if (mmc_done) + state_next = s_write2; + end + s_write2: begin + mmc_wr = 1; + mmc_in = data_hold[15:8]; + if (~mmc_done) + state_next = s_write2a; + end + s_write2a: begin + if (mmc_done) begin + inc_wc = 1; + if (wc == 8'hff) + state_next = s_write2ab; + else + state_next = s_write2aa; + end + end + s_write2aa: begin + if (~bd_wr) + state_next = s_write0; + end + s_write2ab: begin + if (~bd_wr) + state_next = s_write3; + end + s_write3: begin + mmc_wr = 1; + mmc_in = 8'h0; + if (~mmc_done) + state_next = s_write3a; + end + s_write3a: begin + if (mmc_done) + state_next = s_write4; + end + s_write4: begin + mmc_wr = 1; + mmc_in = 8'h0; + if (~mmc_done) + state_next = s_write4a; + end + s_write4a: begin + if (mmc_done) + state_next = s_write5; + end + s_write5: begin + mmc_rd = 1; + if (~mmc_done) + state_next = s_write5a; + end + s_write5a: begin + if (mmc_done) begin + if (mmc_out[4] == 1'b0 && mmc_out[0] == 1'b1) begin + if (mmc_out[3:1] != 3'b010) + set_err = 1; + end + state_next = s_write5aa; + end + end + s_write5aa: begin + mmc_rd = 1; + if (~mmc_done) + state_next = s_write5b; + end + s_write5b: begin + if (mmc_done) begin + if (mmc_out != 8'h00) + state_next = s_write6; + else + state_next = s_write5aa; + end + end + s_write6: begin + mmc_stop = 1; + if (~mmc_done) + state_next = s_write6a; + end + s_write6a: begin + if (mmc_done) + state_next = s_write7; + end + s_write7: begin + inc_bc = 1; + inc_lba = 1; + if (bc == 2'h01) + state_next = s_done0; + else + state_next = s_init0; + end + s_done0: begin + state_next = s_idle; + clear_err = 1; + clear_bc = 1; + end + default: begin + end + endcase + end + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + mmc_speed <= 1'h0; + // End of automatics + end else if (mmc_hispeed) + mmc_speed <= 1; + else if (mmc_lospeed) + mmc_speed <= 0; + +endmodule + +`default_nettype wire Index: block_dev_mmc.v ================================================================== --- block_dev_mmc.v +++ block_dev_mmc.v @@ -291,11 +291,11 @@ always @(posedge clk) if (reset) state <= s_idle; else begin - state <= state_next; + state <= state_next; end assign mmc_active = { mmc_speed, mmc_state }; assign bd_state = { mmc_active, state }; Index: busint.v ================================================================== --- busint.v +++ busint.v @@ -17,11 +17,11 @@ module busint(/*AUTOARG*/ // Outputs dataout, ack, load, interrupt, sdram_addr, sdram_data_out, sdram_req, sdram_write, bd_data_out, bd_cmd, bd_addr, bd_rd, bd_start, bd_wr, disk_state, vram_addr, vram_data_out, vram_req, - vram_write, promdisable, spyout, spyrd, spywr, spyreg, + vram_write, promdisable, spyout, spyrd, spywr, spyreg, o_audio, // Inputs clk, reset, addr, datain, req, write, sdram_data_in, sdram_done, sdram_ready, bd_state, bd_data_in, bd_bsy, bd_err, bd_iordy, bd_rdy, vram_data_in, vram_done, vram_ready, kb_data, kb_ready, ms_x, ms_y, ms_button, ms_ready, spyin @@ -36,10 +36,11 @@ input write; output [31:0] dataout; output ack; output load; output interrupt; + output [15:0] o_audio; // ---!!! ////////////////////////////////////////////////////////////////////// input [31:0] sdram_data_in; input sdram_done; @@ -248,10 +249,11 @@ .decode(decode_io), .interrupt(interrupt_io), /*AUTOINST*/ // Outputs .vector (vector[7:0]), + .o_audio (o_audio), // Inputs .clk (clk), .reset (reset), .addr (addr[21:0]), .write (write), Index: cadr.v ================================================================== --- cadr.v +++ cadr.v @@ -22,15 +22,21 @@ input [15:0] spy_in; output [15:0] spy_out; input dbread; input dbwrite; input [4:0] eadr; + // mcr address == pc output [13:0] mcr_addr; + // data to write to mcr if mcr_write is asserted output [48:0] mcr_data_out; + // data read from mcr input [48:0] mcr_data_in; + // is mcr ready for commands: input mcr_ready; + // write to mcr?? output mcr_write; + // is mcr done rd/wr?? input mcr_done; output [31:0] md; output memrq; output wrcyc; output [31:0] vma; @@ -40,10 +46,12 @@ input loadmd; input [31:0] busint_bus; input bus_int; input memack; input set_promdisable; + /// + wire [11:0] bd_state_in; //////////////////////////////////////////////////////////////////////////////// /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) @@ -371,15 +379,13 @@ .state_decode (state_decode), .state_write (state_write), .ir (ir[48:0]), .dest (dest), .destm (destm)); - ALATCH cadr_alatch(/*AUTOINST*/ - // Outputs - .a (a[31:0]), - // Inputs - .amem (amem[31:0])); + + assign a = amem; + ALU cadr_alu(/*AUTOINST*/ // Outputs .alu (alu[32:0]), .aeqm (aeqm), .xout3 (xout3), @@ -785,15 +791,13 @@ .reset (reset), .l (l[31:0]), .pdla (pdla[9:0]), .prp (prp), .pwp (pwp)); - PLATCH cadr_platch(/*AUTOINST*/ - // Outputs - .pdl (pdl[31:0]), - // Inputs - .pdlo (pdlo[31:0])); + + assign pdl = pdlo; + PDLCTL cadr_pdlctl(/*AUTOINST*/ // Outputs .pdla (pdla[9:0]), .pdlcnt (pdlcnt), .pdldrive (pdldrive), @@ -939,15 +943,13 @@ .spcw (spcw[18:0]), .spcnt (spcnt), .spush (spush), .srp (srp), .swp (swp)); - SPCLCH cadr_spclch(/*AUTOINST*/ - // Outputs - .spc (spc[18:0]), - // Inputs - .spco (spco[18:0])); + + assign spc = spco; + SPCW cadr_spcw(/*AUTOINST*/ // Outputs .spcw (spcw[18:0]), // Inputs .ipc (ipc[13:0]), @@ -1014,15 +1016,13 @@ .ssdone (ssdone), .stathalt (stathalt), .vmaok (vmaok), .waiting (waiting), .wmap (wmap)); - TRAP cadr_trap(/*AUTOINST*/ - // Outputs - .trap (trap), - // Inputs - .boot_trap (boot_trap)); + + assign trap = boot_trap; + VCTL1 cadr_vctl1(/*AUTOINST*/ // Outputs .memprepare (memprepare), .memrq (memrq), .memstart (memstart), @@ -1241,19 +1241,32 @@ // Outputs .iprom (iprom[48:0]), // Inputs .clk (clk), .promaddr (promaddr[8:0])); + + // IRAM IRAM cadr_iram(/*AUTOINST*/ // Outputs .iram (iram[48:0]), // Inputs .clk (clk), .reset (reset), .pc (pc[13:0]), .iwr (iwr[48:0]), - .iwe (iwe)); + .iwe (iwe) + `ifdef EXTERNAL_MCR + , + .mcr_addr (mcr_addr[13:0]), + .mcr_data_in (mcr_data_in[48:0]), + .mcr_data_out (mcr_data_out[48:0]), + .mcr_ready (mcr_ready), + .mcr_hold (mcr_hold), + .mcr_write (mcr_write), + .mcr_done (mcr_done) + `endif + ); SPY0 cadr_spy0(/*AUTOINST*/ // Outputs .ldclk (ldclk), .lddbirh (lddbirh), .lddbirl (lddbirl), Index: cadr.vh ================================================================== --- cadr.vh +++ cadr.vh @@ -1,1 +1,5 @@ // cadr.vh --- global definitions +`define enable_vga +`define enable_ps2 +`define enable_mmc +`define ISE ADDED cadr_core.sv Index: cadr_core.sv ================================================================== --- /dev/null +++ cadr_core.sv @@ -0,0 +1,320 @@ +/******************************************************************************* + * Engineer: Nicholas Nusgart + * Design Name: LM-3 CADR implementation + * Module Name: cadr_core + * Project Name: LM-3 + * Description: This module is the system-implementation of the LM-3. + TODO: possibly get rid of lm3.v + * Dependencies: support_cyc2, ram_controller_mister, lm3 + * Revision: + * Revision 0.01 - File Created + * Additional Comments: +******************************************************************************/ + +`default_nettype none +module cadr_core +( + input clk, + input cpu_clk, + input clk_vga, + input reset, + + input pal, + input scandouble, + + /// VGA video out + // pixel sampling strobe + output reg ce_pix, + // pixel colors + output wire vga_r, + output wire vga_g, + output wire vga_b, + // sync signals + output wire vga_hsync, + output wire vga_vsync, + // is the "beam" on-screen + output wire vga_blank, + + /// MMC interface + output wire mmc_cs, + input wire mmc_di, + output wire mmc_do, + output wire mmc_sclk, + + /// DDR memory interface + output DDRAM_CLK, + input DDRAM_BUSY, + output [7:0] DDRAM_BURSTCNT, + output [28:0] DDRAM_ADDR, + input [63:0] DDRAM_DOUT, + input DDRAM_DOUT_READY, + output DDRAM_RD, + output [63:0] DDRAM_DIN, + output [7:0] DDRAM_BE, + output DDRAM_WE, + + // Keyboard and Mouse + output wire ps2_kbd_clk_out, + output wire ps2_kbd_data_out, + input wire ps2_kbd_clk_in, + input wire ps2_kbd_data_in, + output [15:0] kbd_audio, + + // emulated ps2 mouse + output wire ps2_mouse_clk_out, + output wire ps2_mouse_data_out, + input wire ps2_mouse_clk_in, + input wire ps2_mouse_data_in +); + + reg [3:0] clkcnt; + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire boot; // From support of support_lx45.v + wire [15:0] busint_spyout; // From lm3 of lm3.v + wire dcm_reset; // From support of support_lx45.v + wire [4:0] disk_state; // From lm3 of lm3.v + wire halt; // From support of support_lx45.v + wire interrupt; // From support of support_lx45.v + wire lpddr_calib_done; // From rc of ram_controller_lx45.v + wire lpddr_reset; // From support of support_lx45.v + wire [13:0] mcr_addr; // From lm3 of lm3.v + wire [48:0] mcr_data_out; // From lm3 of lm3.v + wire [48:0] mcr_data_in; // From lm3 of lm3.v + wire mcr_done; // From rc of ram_controller_lx45.v + wire mcr_ready; // From rc of ram_controller_lx45.v + wire mcr_write; // From lm3 of lm3.v + wire [21:0] sdram_addr; // From lm3 of lm3.v + wire [31:0] sdram_data_cpu2rc; // From lm3 of lm3.v + wire [31:0] sdram_data_rc2cpu; // From lm3 of lm3.v + wire sdram_done; // From rc of ram_controller_lx45.v + wire sdram_ready; // From rc of ram_controller_lx45.v + wire sdram_req; // From lm3 of lm3.v + wire sdram_write; // From lm3 of lm3.v + wire spy_rd; // From lm3 of lm3.v + wire [3:0] spy_reg; // From lm3 of lm3.v + wire spy_wr; // From lm3 of lm3.v + wire [14:0] vram_cpu_addr; // From lm3 of lm3.v + wire [31:0] vram_cpu_data_out; // From lm3 of lm3.v + wire vram_cpu_done; // From rc of ram_controller_lx45.v + wire vram_cpu_ready; // From rc of ram_controller_lx45.v + wire vram_cpu_req; // From lm3 of lm3.v + wire vram_cpu_write; // From lm3 of lm3.v + wire [14:0] vram_vga_addr; // From lm3 of lm3.v + wire [31:0] vram_vga_data_out; // From rc of ram_controller_lx45.v + wire [31:0] vram_cpu_data_in; // From rc of ram_controller_lx45.v + wire vram_vga_ready; // From rc of ram_controller_lx45.v + wire vram_vga_req; // From lm3 of lm3.v + // End of automatics + + //////////////////////////////////////////////////////////////////////////////// + + wire clk50; + + wire rs232_txd, rs232_rxd; + assign clk50 = clk; + wire sup_reset; + + support_cyc2 support + ( + .sysclk(clk50), + .button_r(reset), + .button_b(1'b0), + .button_h(1'b0), + .button_c(1'b0), + /*AUTOINST*/ + // Outputs + .boot (boot), + .dcm_reset (dcm_reset), + .halt (halt), + .interrupt (interrupt), + .reset (sup_reset), + // Inputs + .cpu_clk (cpu_clk), + .lpddr_calib_done (~reset)); + + ram_controller_mister rc + ( + .clk(clk50), + .mcr_data_out(mcr_data_in), + .mcr_data_in(mcr_data_out), + .sdram_data_in(sdram_data_cpu2rc), + .sdram_data_out(sdram_data_rc2cpu), + .vram_cpu_data_in(vram_cpu_data_out), + .vram_cpu_data_out(vram_cpu_data_in), + + // + .DDRAM_CLK(DDRAM_CLK), + .DDRAM_ADDR(DDRAM_ADDR), + .DDRAM_BURSTCNT(DDRAM_BURSTCNT), + .DDRAM_BUSY(DDRAM_BUSY), + .DDRAM_DOUT(DDRAM_DOUT), + .DDRAM_DOUT_READY(DDRAM_DOUT_READY), + .DDRAM_RD(DDRAM_RD), + .DDRAM_DIN(DDRAM_DIN), + .DDRAM_BE(DDRAM_BE), + .DDRAM_WE(DDRAM_WE), + + // Outputs + .vram_vga_data_out (vram_vga_data_out[31:0]), + .mcr_done (mcr_done), + .mcr_ready (mcr_ready), + .sdram_done (sdram_done), + .sdram_ready (sdram_ready), + .vram_cpu_done (vram_cpu_done), + .vram_cpu_ready (vram_cpu_ready), + .vram_vga_ready (vram_vga_ready), + // Inouts + // Inputs + .mcr_addr (mcr_addr[13:0]), + .vram_cpu_addr (vram_cpu_addr[14:0]), + .vram_vga_addr (vram_vga_addr[14:0]), + .sdram_addr (sdram_addr[21:0]), + .cpu_clk (cpu_clk), + .mcr_write (mcr_write), + .reset (reset), + .sdram_req (sdram_req), + .sdram_write (sdram_write), + .vga_clk (clk_vga), + .vram_cpu_req (vram_cpu_req), + .vram_cpu_write (vram_cpu_write), + .vram_vga_req (vram_vga_req)); + + lm3 lm3(/*AUTOINST*/ + // Outputs + .sdram_addr (sdram_addr[21:0]), + .sdram_data_cpu2rc (sdram_data_cpu2rc[31:0]), + .sdram_req (sdram_req), + .sdram_write (sdram_write), + .vram_cpu_addr (vram_cpu_addr[14:0]), + .vram_cpu_data_out (vram_cpu_data_out[31:0]), + .vram_cpu_req (vram_cpu_req), + .vram_cpu_write (vram_cpu_write), + .spy_reg (spy_reg[3:0]), + .busint_spyout (busint_spyout[15:0]), + .spy_rd (spy_rd), + .spy_wr (spy_wr), + .disk_state (disk_state[4:0]), + .mcr_addr (mcr_addr[13:0]), + .mcr_data_out (mcr_data_out[48:0]), + .mcr_write (mcr_write), + .mmc_cs (mmc_cs), + .mmc_do (mmc_do), + .mmc_sclk (mmc_sclk), + .vram_vga_addr (vram_vga_addr[14:0]), + .vram_vga_req (vram_vga_req), + .vga_blank (vga_blank), + .vga_r (vga_r), + .vga_g (vga_g), + .vga_b (vga_b), + .vga_hsync (vga_hsync), + .vga_vsync (vga_vsync), + .rs232_txd (rs232_txd), + .o_audio(kbd_audio), + // Inouts + .ps2_mouse_clk_in (ps2_mouse_clk_in), + .ps2_mouse_data_in (ps2_mouse_data_in), + .ps2_mouse_clk_out (ps2_mouse_clk_out), + .ps2_mouse_data_out (ps2_mouse_data_out), + // Inputs + .clk50 (clk50), + .reset (reset), + .sdram_data_rc2cpu (sdram_data_rc2cpu[31:0]), + .sdram_done (sdram_done), + .sdram_ready (sdram_ready), + .vram_cpu_data_in (vram_cpu_data_in[31:0]), + .vram_cpu_done (vram_cpu_done), + .vram_cpu_ready (vram_cpu_ready), + .cpu_clk (cpu_clk), + .boot (boot), + .halt (halt), + .interrupt (interrupt), + .mcr_data_in (mcr_data_in[48:0]), + .mcr_ready (mcr_ready), + .mcr_done (mcr_done), + .mmc_di (mmc_di), + .vram_vga_data_out (vram_vga_data_out[31:0]), + .vram_vga_ready (vram_vga_ready), + .vga_clk (clk_vga), + .kb_ps2_clk (ps2_kbd_clk_in), + .kb_ps2_data (ps2_kbd_data_in), + .rs232_rxd (rs232_rxd)); + /* + assign led[3] = 1'b0; + assign led[2] = disk_state[1]; + assign led[1] = disk_state[2]; + assign led[0] = reset; +*/ + + +/* +/////////////////////////// ORIGINAL STUFF +reg [9:0] hc; +reg [9:0] vc; +reg [9:0] vvc; +reg [63:0] rnd_reg; + +wire [5:0] rnd_c = {rnd_reg[0],rnd_reg[1],rnd_reg[2],rnd_reg[2],rnd_reg[2],rnd_reg[2]}; +wire [63:0] rnd; + +lfsr random(rnd); + +always @(posedge clk) begin + if(scandouble) ce_pix <= 1; + else ce_pix <= ~ce_pix; + + if(reset) begin + hc <= 0; + vc <= 0; + end + else if(ce_pix) begin + if(hc == 637) begin + hc <= 0; + if(vc == (pal ? (scandouble ? 623 : 311) : (scandouble ? 523 : 261))) begin + vc <= 0; + vvc <= vvc + 9'd6; + end else begin + vc <= vc + 1'd1; + end + end else begin + hc <= hc + 1'd1; + end + + rnd_reg <= rnd; + end +end + +always @(posedge clk) begin + if (hc == 529) HBlank <= 1; + else if (hc == 0) HBlank <= 0; + + if (hc == 544) begin + HSync <= 1; + + if(pal) begin + if(vc == (scandouble ? 609 : 304)) VSync <= 1; + else if (vc == (scandouble ? 617 : 308)) VSync <= 0; + + if(vc == (scandouble ? 601 : 300)) VBlank <= 1; + else if (vc == 0) VBlank <= 0; + end + else begin + if(vc == (scandouble ? 490 : 245)) VSync <= 1; + else if (vc == (scandouble ? 496 : 248)) VSync <= 0; + + if(vc == (scandouble ? 480 : 240)) VBlank <= 1; + else if (vc == 0) VBlank <= 0; + end + end + + if (hc == 590) HSync <= 0; +end + +reg [7:0] cos_out; +wire [5:0] cos_g = cos_out[7:3]+6'd32; +cos cos(vvc + {vc>>scandouble, 2'b00}, cos_out); + +assign video = (cos_g >= rnd_c) ? {cos_g - rnd_c, 2'b00} : 8'd0; +*/ +endmodule +`default_nettype wire ADDED clkwiz.v Index: clkwiz.v ================================================================== --- /dev/null +++ clkwiz.v @@ -0,0 +1,321 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clkwiz.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clkwiz ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [5:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.clk0_divide_by = 12, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 13, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.gate_lock_signal = "NO", + altpll_component.inclk0_input_frequency = 10000, + altpll_component.intended_device_family = "Cyclone II", + altpll_component.invalid_lock_multiplier = 5, + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clkwiz", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.valid_lock_multiplier = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "12" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "108.333336" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "13" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "108.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkwiz.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "12" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "13" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON ADDED clkwiz_bb.v Index: clkwiz_bb.v ================================================================== --- /dev/null +++ clkwiz_bb.v @@ -0,0 +1,212 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clkwiz.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module clkwiz ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "12" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "108.333336" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "13" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "108.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkwiz.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "12" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "13" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkwiz_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON ADDED cores/alt_vram.qip Index: cores/alt_vram.qip ================================================================== --- /dev/null +++ cores/alt_vram.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "alt_vram.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "alt_vram_bb.v"] ADDED cores/alt_vram.v Index: cores/alt_vram.v ================================================================== --- /dev/null +++ cores/alt_vram.v @@ -0,0 +1,244 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: alt_vram.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.0 Build 625 09/12/2018 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module alt_vram ( + address_a, + address_b, + clock_a, + clock_b, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [14:0] address_a; + input [14:0] address_b; + input clock_a; + input clock_b; + input [31:0] data_a; + input [31:0] data_b; + input wren_a; + input wren_b; + output [31:0] q_a; + output [31:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock_a; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [31:0] sub_wire0; + wire [31:0] sub_wire1; + wire [31:0] q_a = sub_wire0[31:0]; + wire [31:0] q_b = sub_wire1[31:0]; + + altsyncram altsyncram_component ( + .address_a (address_a), + .address_b (address_b), + .clock0 (clock_a), + .clock1 (clock_b), + .data_a (data_a), + .data_b (data_b), + .wren_a (wren_a), + .wren_b (wren_b), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK1", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK1", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 21504, + altsyncram_component.numwords_b = 21504, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.outdata_reg_b = "CLOCK1", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 15, + altsyncram_component.widthad_b = 15, + altsyncram_component.width_a = 32, + altsyncram_component.width_b = 32, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "5" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "688128" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "21504" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "21504" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "15" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: USED_PORT: address_a 0 0 15 0 INPUT NODEFVAL "address_a[14..0]" +// Retrieval info: USED_PORT: address_b 0 0 15 0 INPUT NODEFVAL "address_b[14..0]" +// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" +// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" +// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]" +// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]" +// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]" +// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 15 0 address_a 0 0 15 0 +// Retrieval info: CONNECT: @address_b 0 0 15 0 address_b 0 0 15 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0 +// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0 +// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL alt_vram.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL alt_vram.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL alt_vram.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL alt_vram.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL alt_vram_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL alt_vram_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf ADDED cores/alt_vram_bb.v Index: cores/alt_vram_bb.v ================================================================== --- /dev/null +++ cores/alt_vram_bb.v @@ -0,0 +1,182 @@ +// megafunction wizard: %RAM: 2-PORT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: alt_vram.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.0 Build 625 09/12/2018 SJ Lite Edition +// ************************************************************ + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + +module alt_vram ( + address_a, + address_b, + clock_a, + clock_b, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [14:0] address_a; + input [14:0] address_b; + input clock_a; + input clock_b; + input [31:0] data_a; + input [31:0] data_b; + input wren_a; + input wren_b; + output [31:0] q_a; + output [31:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock_a; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "5" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "688128" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "21504" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "21504" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "15" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: USED_PORT: address_a 0 0 15 0 INPUT NODEFVAL "address_a[14..0]" +// Retrieval info: USED_PORT: address_b 0 0 15 0 INPUT NODEFVAL "address_b[14..0]" +// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" +// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" +// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]" +// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]" +// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]" +// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 15 0 address_a 0 0 15 0 +// Retrieval info: CONNECT: @address_b 0 0 15 0 address_b 0 0 15 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0 +// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0 +// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL alt_vram.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL alt_vram.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL alt_vram.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL alt_vram.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL alt_vram_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL alt_vram_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf ADDED cos.sv Index: cos.sv ================================================================== --- /dev/null +++ cos.sv @@ -0,0 +1,46 @@ + +module cos ( + input [9:0] x, + output [7:0] y +); + +wire [7:0] qcos[0:255] = '{ + 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, + 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, + 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, 8'b01111111, + 8'b01111110, 8'b01111110, 8'b01111110, 8'b01111110, 8'b01111110, 8'b01111110, 8'b01111110, 8'b01111110, + 8'b01111101, 8'b01111101, 8'b01111101, 8'b01111101, 8'b01111101, 8'b01111101, 8'b01111100, 8'b01111100, + 8'b01111100, 8'b01111100, 8'b01111100, 8'b01111011, 8'b01111011, 8'b01111011, 8'b01111011, 8'b01111010, + 8'b01111010, 8'b01111010, 8'b01111010, 8'b01111010, 8'b01111001, 8'b01111001, 8'b01111001, 8'b01111001, + 8'b01111000, 8'b01111000, 8'b01111000, 8'b01110111, 8'b01110111, 8'b01110111, 8'b01110111, 8'b01110110, + 8'b01110110, 8'b01110110, 8'b01110101, 8'b01110101, 8'b01110101, 8'b01110100, 8'b01110100, 8'b01110100, + 8'b01110011, 8'b01110011, 8'b01110011, 8'b01110010, 8'b01110010, 8'b01110010, 8'b01110001, 8'b01110001, + 8'b01110001, 8'b01110000, 8'b01110000, 8'b01101111, 8'b01101111, 8'b01101111, 8'b01101110, 8'b01101110, + 8'b01101101, 8'b01101101, 8'b01101101, 8'b01101100, 8'b01101100, 8'b01101011, 8'b01101011, 8'b01101010, + 8'b01101010, 8'b01101010, 8'b01101001, 8'b01101001, 8'b01101000, 8'b01101000, 8'b01100111, 8'b01100111, + 8'b01100110, 8'b01100110, 8'b01100101, 8'b01100101, 8'b01100100, 8'b01100100, 8'b01100011, 8'b01100011, + 8'b01100010, 8'b01100010, 8'b01100001, 8'b01100001, 8'b01100000, 8'b01100000, 8'b01011111, 8'b01011111, + 8'b01011110, 8'b01011110, 8'b01011101, 8'b01011101, 8'b01011100, 8'b01011100, 8'b01011011, 8'b01011011, + 8'b01011010, 8'b01011001, 8'b01011001, 8'b01011000, 8'b01011000, 8'b01010111, 8'b01010111, 8'b01010110, + 8'b01010101, 8'b01010101, 8'b01010100, 8'b01010100, 8'b01010011, 8'b01010010, 8'b01010010, 8'b01010001, + 8'b01010001, 8'b01010000, 8'b01001111, 8'b01001111, 8'b01001110, 8'b01001110, 8'b01001101, 8'b01001100, + 8'b01001100, 8'b01001011, 8'b01001010, 8'b01001010, 8'b01001001, 8'b01001000, 8'b01001000, 8'b01000111, + 8'b01000111, 8'b01000110, 8'b01000101, 8'b01000101, 8'b01000100, 8'b01000011, 8'b01000011, 8'b01000010, + 8'b01000001, 8'b01000001, 8'b01000000, 8'b00111111, 8'b00111110, 8'b00111110, 8'b00111101, 8'b00111100, + 8'b00111100, 8'b00111011, 8'b00111010, 8'b00111010, 8'b00111001, 8'b00111000, 8'b00111000, 8'b00110111, + 8'b00110110, 8'b00110101, 8'b00110101, 8'b00110100, 8'b00110011, 8'b00110011, 8'b00110010, 8'b00110001, + 8'b00110000, 8'b00110000, 8'b00101111, 8'b00101110, 8'b00101101, 8'b00101101, 8'b00101100, 8'b00101011, + 8'b00101010, 8'b00101010, 8'b00101001, 8'b00101000, 8'b00100111, 8'b00100111, 8'b00100110, 8'b00100101, + 8'b00100100, 8'b00100100, 8'b00100011, 8'b00100010, 8'b00100001, 8'b00100001, 8'b00100000, 8'b00011111, + 8'b00011110, 8'b00011110, 8'b00011101, 8'b00011100, 8'b00011011, 8'b00011011, 8'b00011010, 8'b00011001, + 8'b00011000, 8'b00011000, 8'b00010111, 8'b00010110, 8'b00010101, 8'b00010100, 8'b00010100, 8'b00010011, + 8'b00010010, 8'b00010001, 8'b00010001, 8'b00010000, 8'b00001111, 8'b00001110, 8'b00001101, 8'b00001101, + 8'b00001100, 8'b00001011, 8'b00001010, 8'b00001010, 8'b00001001, 8'b00001000, 8'b00000111, 8'b00000110, + 8'b00000110, 8'b00000101, 8'b00000100, 8'b00000011, 8'b00000010, 8'b00000010, 8'b00000001, 8'b00000000 +}; + +wire ival = ^x[9:8]; +assign y = qcos[x[7:0] ^ {8{x[8]}}] ^ {~ival,{7{ival}}}; + +endmodule + ADDED lfsr.v Index: lfsr.v ================================================================== --- /dev/null +++ lfsr.v @@ -0,0 +1,16 @@ + +module lfsr( + output [N-1:0] rnd +); + +parameter N = 63; + +lcell lc0(~(rnd[N - 1] ^ rnd[N - 3] ^ rnd[N - 4] ^ rnd[N - 6] ^ rnd[N - 10]), rnd[0]); +generate + genvar i; + for (i = 0; i <= N - 2; i = i + 1) begin : lcn + lcell lc(rnd[i], rnd[i + 1]); + end +endgenerate + +endmodule Index: lm3.v ================================================================== --- lm3.v +++ lm3.v @@ -18,24 +18,32 @@ // ---!!! enable_vga / enable_hdmi (???) // ---!!! enable_spy_port // ---!!! enable_mmc // ---!!! enable_ps2 / enable_usb (???) // ---!!! enable_ethernet (???) +`define enable_vga +`define enable_mmc +`define enable_ps2 + `timescale 1ns/1ps `default_nettype none + module lm3(/*AUTOARG*/ // Outputs sdram_addr, sdram_data_cpu2rc, sdram_req, sdram_write, vram_cpu_addr, vram_cpu_data_out, vram_cpu_req, vram_cpu_write, - spy_reg, busint_spyout, spy_rd, spy_wr, disk_state, fetch, - prefetch, mcr_addr, mcr_data_out, mcr_write, mmc_cs, mmc_do, + spy_reg, busint_spyout, spy_rd, spy_wr, disk_state, + mcr_addr, mcr_data_out, mcr_write, mmc_cs, mmc_do, mmc_sclk, vram_vga_addr, vram_vga_req, vga_blank, vga_r, vga_g, - vga_b, vga_hsync, vga_vsync, rs232_txd, + vga_b, vga_hsync, vga_vsync, rs232_txd, o_audio, // Inouts - ms_ps2_clk, ms_ps2_data, + ps2_mouse_clk_out, + ps2_mouse_data_out, + ps2_mouse_clk_in, + ps2_mouse_data_in, // Inputs clk50, reset, sdram_data_rc2cpu, sdram_done, sdram_ready, vram_cpu_data_in, vram_cpu_done, vram_cpu_ready, cpu_clk, boot, halt, interrupt, mcr_data_in, mcr_ready, mcr_done, mmc_di, vram_vga_data_out, vram_vga_ready, vga_clk, kb_ps2_clk, @@ -128,12 +136,10 @@ // ---!!! PC is a dangling output? input boot; /// SUPPORT / RC input halt; /// SUPPORT / RC input interrupt; /// SUPPORT / RC - output fetch; - output prefetch; /// SUPPORT / RC output [13:0] mcr_addr; /// SUPPORT / RC output [48:0] mcr_data_out; /// SUPPORT / RC input [48:0] mcr_data_in; /// SUPPORT / RC input mcr_ready; /// SUPPORT / RC @@ -173,10 +179,12 @@ output vga_r; output vga_g; output vga_b; output vga_hsync; output vga_vsync; + + output [15:0] o_audio; // PS/2 //////////////////////////////////////////////////////////////////////////////// // output [11:0] ms_x; // output [11:0] ms_x; @@ -186,12 +194,14 @@ // output ms_ready; input kb_ps2_clk; input kb_ps2_data; - inout ms_ps2_clk; - inout ms_ps2_data; + output wire ps2_mouse_clk_out; + output wire ps2_mouse_data_out; + input wire ps2_mouse_clk_in; + input wire ps2_mouse_data_in; // SPY //////////////////////////////////////////////////////////////////////////////// // input [15:0] spy_out; // output [15:0] spy_in; @@ -259,11 +269,10 @@ wire bus_int; wire clk50; wire cpu_clk; wire dbread, dbwrite; wire dcm_reset; - wire fetch; wire halt; wire interrupt; wire kb_ps2_clk_in; wire kb_ps2_data_in; wire kb_ready; @@ -280,11 +289,10 @@ wire ms_ps2_data_out; wire ms_ps2_dir; wire ms_ready; wire vga_clk; wire vga_clk_locked; - wire prefetch; wire reset; wire rs232_rxd, rs232_txd; wire sdram_done; wire sdram_ready; wire sdram_req; @@ -352,10 +360,11 @@ .bd_addr (bd_addr[23:0]), .bd_rd (bd_rd), .bd_start (bd_start), .bd_wr (bd_wr), .disk_state (disk_state[4:0]), + .o_audio (o_audio), // Inputs .reset (reset), .sdram_done (sdram_done), .sdram_ready (sdram_ready), .bd_bsy (bd_bsy), @@ -367,11 +376,11 @@ .ms_x (ms_x[11:0]), .ms_y (ms_y[11:0]), .ms_button (ms_button[2:0]), .ms_ready (ms_ready)); // input ms_ready; - assign disk_state_in = busint.disk.state; + assign disk_state_in = disk_state; cadr cpu ( .clk(cpu_clk), // input clk; .ext_int(interrupt), // input ext_int; @@ -403,11 +412,13 @@ .busint_bus (busint_bus[31:0]), .bus_int (bus_int), .memack (memack), .set_promdisable (set_promdisable)); // input set_promdisable; +`define enable_mmc `ifdef enable_mmc + block_dev_mmc mmc_bd ( .clk(cpu_clk), // input clk; .mmcclk(clk50), // input mmcclk; .bd_data_in(bd_data_cpu2bd), // input [15:0] bd_data_in; @@ -430,11 +441,11 @@ .bd_wr (bd_wr), .mmc_di (mmc_di), .reset (reset)); // input reset; `endif -`ifdef enable_vga + vga_display vga ( .vram_addr(vram_vga_addr), // output [14:0] vram_addr; .vram_data(vram_vga_data_out), // input [31:0] vram_data; .vram_req(vram_vga_req), // output vram_req; @@ -448,18 +459,16 @@ .vga_vsync (vga_vsync), .vga_blank (vga_blank), // Inputs .vga_clk (vga_clk), .reset (reset)); -`endif - -`ifdef enable_ps2 - assign ms_ps2_clk_in = ms_ps2_clk; - assign ms_ps2_data_in = ms_ps2_data; - assign ms_ps2_clk = ms_ps2_dir ? ms_ps2_clk_out : 1'bz; - assign ms_ps2_data = ms_ps2_dir ? ms_ps2_data_out : 1'bz; - + + assign ms_ps2_clk_in = ps2_mouse_clk_in; + assign ms_ps2_data_in = ps2_mouse_clk_in; + assign ps2_mouse_clk_out = ms_ps2_clk_out; + assign ps2_mouse_data_out = ms_ps2_data_out; + ps2_support ps2_support ( .clk(cpu_clk), // input clk; .kb_ps2_clk_in(kb_ps2_clk), // input kb_ps2_clk_in; .kb_ps2_data_in(kb_ps2_data), // input kb_ps2_data_in; @@ -476,11 +485,10 @@ .ms_ps2_dir (ms_ps2_dir), // Inputs .reset (reset), .ms_ps2_clk_in (ms_ps2_clk_in), .ms_ps2_data_in (ms_ps2_data_in)); // input ms_ps2_data_in; -`endif `ifdef enable_spy_port spy_port spy_port ( .sysclk(clk50), // input sysclk; @@ -494,14 +502,17 @@ .dbwrite (dbwrite), .rs232_txd (rs232_txd), // Inputs .reset (reset), .rs232_rxd (rs232_rxd)); // input rs232_rxd; +`else +//assign rs232_rxd = 1'b0; +assign rs232_txd = 1'b0; `endif endmodule `default_nettype wire // Local Variables: // verilog-library-directories: (".") // End: ADDED pll.qip Index: pll.qip ================================================================== --- /dev/null +++ pll.qip @@ -0,0 +1,337 @@ +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "18.1" +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] +set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "pll" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "pll" -library "pll" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_NAME "cGxs" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTguMQ==" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_NAME "cGxsXzAwMDI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTguMQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mw==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mw==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTM=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTA4LjMzMzMzMw==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::LTYwLjA=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MjUuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MjY=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NTAuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTA4LjMzMzMzMyBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MjUuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::Nyw2LDI1NiwyNTYsZmFsc2UsdHJ1ZSx0cnVlLGZhbHNlLDcsNiwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDMsMywxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMywxMywxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDMwLDIwMDAsNjUwLjAgTUh6LDEsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" + +set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"] +set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002.qip"] + +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "18.1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" ADDED pll.v Index: pll.v ================================================================== --- /dev/null +++ pll.v @@ -0,0 +1,257 @@ +// megafunction wizard: %PLL Intel FPGA IP v18.1% +// GENERATION: XML +// pll.v + +// Generated using ACDS version 18.1 625 + +`timescale 1 ps / 1 ps +module pll ( + input wire refclk, // refclk.clk + input wire rst, // reset.reset + output wire outclk_0, // outclk0.clk + output wire outclk_1, // outclk1.clk + output wire outclk_2, // outclk2.clk + output wire locked // locked.export + ); + + pll_0002 pll_inst ( + .refclk (refclk), // refclk.clk + .rst (rst), // reset.reset + .outclk_0 (outclk_0), // outclk0.clk + .outclk_1 (outclk_1), // outclk1.clk + .outclk_2 (outclk_2), // outclk2.clk + .locked (locked) // locked.export + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// 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+ + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'outclk1' + output wire outclk_1, + + // interface 'outclk2' + output wire outclk_2, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("false"), + .reference_clock_frequency("50.0 MHz"), + .operation_mode("direct"), + .number_of_clocks(3), + .output_clock_frequency0("50.000000 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("108.333333 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("25.000000 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("0 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("0 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_2, outclk_1, outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + ADDED pll17.qip Index: pll17.qip ================================================================== --- /dev/null +++ pll17.qip @@ -0,0 +1,337 @@ +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] +set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "pll" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "pll" -library "pll" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_NAME "cGxs" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_NAME "cGxsXzAwMDI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjAuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::Ng==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTU=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MjAuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::Ng==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MTU=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::LTYwLjA=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MjAuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjAuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MywzLDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw4LDcsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDMwLDIwMDAsMzAwLjAgTUh6LDEsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" + +set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"] +set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002.qip"] + +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" ADDED ram_controller_cyc2.v Index: ram_controller_cyc2.v ================================================================== --- /dev/null +++ ram_controller_cyc2.v @@ -0,0 +1,351 @@ +// ram_controller_cyc2.v --- ---!!! + +`timescale 1ns/1ps +//`default_nettype none + +module ram_controller_cyc2(/*AUTOARG*/ + // Outputs + sdram_data_out, vram_cpu_data_out, + vram_vga_data_out, mcr_data_out, lpddr_calib_done, lpddr_clk_out, + mcr_done, mcr_ready, sdram_done, sdram_ready, vram_cpu_done, + vram_cpu_ready, vram_vga_ready, + /* + mcb3_dram_a, mcb3_dram_ba, + mcb3_dram_cas_n, mcb3_dram_ck, mcb3_dram_ck_n, mcb3_dram_cke, + mcb3_dram_dm, mcb3_dram_ras_n, mcb3_dram_udm, mcb3_dram_we_n, + */ + // Inouts + //mcb3_dram_dq, mcb3_dram_dqs, mcb3_dram_udqs, mcb3_rzq, + // Inputs + mcr_addr, vram_cpu_addr, vram_vga_addr, sdram_addr, sdram_data_in, + vram_cpu_data_in, mcr_data_in, clk, cpu_clk, fetch, lpddr_reset, + machrun, mcr_write, prefetch, reset, sdram_req, sdram_write, + sysclk, vga_clk, vram_cpu_req, vram_cpu_write, vram_vga_req, + + //LPDDR2 + lpddr2_ca, lpddr2_dq, lpddr2_dm, lpddr2_dqs, lpddr2_dqsn, lpddr2_cke, + lpddr2_csn, lpddr2_ckn, lpddr2_ck, + ); + + output [9:0] lpddr2_ca; + inout [15:0] lpddr2_dq; + output [1:0] lpddr2_dm; + inout [1:0] lpddr2_dqs; + inout [1:0] lpddr2_dqsn; + output lpddr2_cke; + output lpddr2_csn; + inout lpddr2_ckn; + inout lpddr2_ck; + //inout [15:0] mcb3_dram_dq; + //inout [1:0] mcb3_dram_dqs; + //inout [1:0] mcb3_dram_udqs; + //inout mcb3_rzq; + input [13:0] mcr_addr; + input [14:0] vram_cpu_addr; + input [14:0] vram_vga_addr; + input [21:0] sdram_addr; + input [31:0] sdram_data_in; + input [31:0] vram_cpu_data_in; + input [48:0] mcr_data_in; + input clk; + input cpu_clk; + input fetch; + input lpddr_reset; + input machrun; + input mcr_write; + input prefetch; + input reset; + input sdram_req; + input sdram_write; + input sysclk; + input vga_clk; + input vram_cpu_req; + input vram_cpu_write; + input vram_vga_req; + //output [12:0] mcb3_dram_a; + //output [1:0] mcb3_dram_ba; + output [31:0] sdram_data_out; + output [31:0] vram_cpu_data_out; + output [31:0] vram_vga_data_out; + output [48:0] mcr_data_out; + output lpddr_calib_done; + output lpddr_clk_out; + /* + output mcb3_dram_cas_n; + output mcb3_dram_ck; + output mcb3_dram_ck_n; + output mcb3_dram_cke; + output mcb3_dram_dm; + output mcb3_dram_ras_n; + output mcb3_dram_udm; + output mcb3_dram_we_n; + */ + output mcr_done; + output mcr_ready; + output sdram_done; + output sdram_ready; + output vram_cpu_done; + output vram_cpu_ready; + output vram_vga_ready; + + //////////////////////////////////////////////////////////////////////////////// + + parameter [2:0] + NSD_IDLE = 0, + NSD_READ = 1, + NSD_READBSY = 2, + NSD_READW = 3, + NSD_WRITE = 4, + NSD_WRITEBSY = 5, + NSD_WRITEW = 6; + parameter [6:0] + SD_IDLE = 7'b0000001, + SD_READ = 7'b0000010, + SD_READBSY = 7'b0000100, + SD_READW = 7'b0001000, + SD_WRITE = 7'b0010000, + SD_WRITEBSY = 7'b0100000, + SD_WRITEW = 7'b1000000; + + reg [31:0] sdram_out; + reg [31:0] vram_vga_data; + reg [3:0] vram_cpu_ready_dly; + reg [3:0] vram_vga_ready_dly; + reg [6:0] sdram_state; + reg int_sdram_done; + reg int_sdram_ready; + reg sdram_done; + reg sdram_ready; + + wire [29:0] lpddr_addr; + wire [2:0] lpddr_cmd; + wire [31:0] sdram_resp_in; + wire [31:0] vram_vga_ram_out; + wire [6:0] sdram_state_next; + //wire c3_calib_done; + wire clock; + wire i_sdram_req; + wire i_sdram_write; + wire lpddr_clk; + wire lpddr_cmd_en; + wire lpddr_cmd_full; + wire lpddr_rd_done; + wire lpddr_rd_empty; + wire lpddr_rd_rdy; + wire lpddr_wr_done; + wire lpddr_wr_en; + wire lpddr_wr_full; + wire lpddr_wr_rdy; + wire reset; + wire sys_clk; + wire sys_rst; + + //////////////////////////////////////////////////////////////////////////////// + + always @(posedge clk) + if (reset) begin + sdram_state <= SD_IDLE; + end else + sdram_state <= sdram_state_next; + + assign sdram_state_next = + (sdram_state[NSD_IDLE] && sdram_req) ? SD_READ : + (sdram_state[NSD_IDLE] && sdram_write) ? SD_WRITE : + (sdram_state[NSD_READ] && lpddr_rd_rdy) ? SD_READBSY : + (sdram_state[NSD_READBSY] && lpddr_rd_done) ? SD_READW : + (sdram_state[NSD_READW] && ~sdram_req) ? SD_IDLE : + (sdram_state[NSD_WRITE] && lpddr_wr_rdy) ? SD_WRITEBSY : + (sdram_state[NSD_WRITEBSY] && lpddr_wr_done) ? SD_WRITEW : + (sdram_state[NSD_WRITEW] && ~sdram_write) ? SD_IDLE : + sdram_state; + assign i_sdram_req = sdram_state[NSD_READ]; + assign i_sdram_write = sdram_state[NSD_WRITE]; + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + sdram_out <= 32'h0; + // End of automatics + end else begin + if (sdram_state[NSD_READBSY]) begin + sdram_out <= sdram_addr[21:17] == 0 ? sdram_resp_in : 32'hffffffff; + end + end + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + int_sdram_ready <= 1'h0; + // End of automatics + end else if (sdram_state[NSD_READ]) + int_sdram_ready <= 1'b0; + else if (sdram_state[NSD_READW]) + int_sdram_ready <= 1'b1; + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + int_sdram_done <= 1'h0; + // End of automatics + end else if (sdram_state[NSD_WRITE]) + int_sdram_done <= 1'b0; + else if (sdram_state[NSD_WRITEW]) + int_sdram_done <= 1'b1; + + assign sdram_data_out = sdram_out; + + always @(posedge cpu_clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + sdram_ready <= 1'h0; + // End of automatics + end else + sdram_ready <= int_sdram_ready && sdram_req; + + always @(posedge cpu_clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + sdram_done <= 1'h0; + // End of automatics + end else + sdram_done <= int_sdram_done && sdram_write; + + assign lpddr_cmd = sdram_write ? 3'b000 : 3'b001; + assign lpddr_addr = { 6'b0, sdram_addr, 2'b0 }; + assign lpddr_cmd_en = (sdram_state[NSD_READ] && sdram_state_next == SD_READBSY) || + (sdram_state[NSD_WRITE] && sdram_state_next == SD_WRITEBSY); + //assign lpddr_rd_rdy = ~lpddr_cmd_full; + //assign lpddr_rd_done = ~lpddr_rd_empty; + assign lpddr_wr_rdy = ~lpddr_cmd_full && ~lpddr_wr_full; +// assign lpddr_wr_done = 1'b1; + assign lpddr_wr_en = sdram_state[NSD_WRITEBSY]; + assign lpddr_clk_out = lpddr_clk; + //assign lpddr_calib_done = c3_calib_done; + wire ddr_sysclk; + assign ddr_sysclk = sysclk; + + altera_ddr intf( + // clocks + .pll_ref_clk(ddr_sysclk), + .afi_clk(lpddr_clk), + //.afi_half_clk(clk), + // reset + .global_reset_n(lpddr_reset), + // request a read or write + .avl_read_req(i_sdram_req), + .avl_write_req(i_sdram_write), + // address + .avl_addr(lpddr_addr), + // data to write + .avl_wdata(sdram_data_in), + // controls size + .avl_be(8'b00001111), + .avl_size(2'b11), + .avl_ready(lpddr_rd_rdy), + // output data read + .avl_rdata(sdram_resp_in), + .avl_rdata_valid(lpddr_rd_done), + //.local_rdvalid_in_n, + .local_init_done(lpddr_calib_done), + //.local_refresh_ack, // intentionally left blank + //.avl_write_req(lpddr_wr_done), + //.ddr_odt(mcb3_rzq), // odt resistor + .pll_mem_clk(mcb3_dram_ck), + .pll_write_clk(mcb3_dram_ck_n), + .mem_cs_n(lpddr2_csn), + .mem_cke(lpddr2_ck), + .mem_ca(lpddr2_ca), + //.mem_ba(lppdr2_ba), + //.ddr_ras_n(mcb3_dram_ras_n), + //.ddr_cas_n(mcb3_dram_cas_n), + //.ddr_we_n(mcb3_dram_we_n), + .mem_dm(lppdr2_dm), + .mem_dq(lpddr2_dq), + .mem_dqs(lpddr2_dqs), + .mem_dqs_n(lpddr2_dqsn) + ); + + /* + //LPDDR2 + output [9:0] lpddr2_ca, + inout [15:0] lpddr2_dq, + output [1:0] lpddr2_dm, + inout lpddr2_dqs1n, + inout lpddr2_dqs1, + inout lpddr2_dqs0n, + inout lpddr2_dqs0, + output lpddr2_cke, + output lpddr2_csn, + inout lpddr2_ckn, + inout lpddr2_ck, + */ + + wire ena_a = vram_cpu_req | vram_cpu_write; + wire ena_b = vram_vga_req | 1'b0; + alt_vram inst ( + .address_a(vram_cpu_addr), + .address_b(vram_vga_addr), + .clock_a(cpu_clk), + .clock_b(vga_clk), + .data_a(vram_cpu_data_in), + .data_b(32'b0), + .wren_a(ena_a), + .wren_b(vram_cpu_write), + .q_a(vram_cpu_data_out), + .q_b(vram_vga_ram_out)); + + + assign vram_vga_data_out = vram_vga_ready ? vram_vga_ram_out : vram_vga_data; + + always @(posedge vga_clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + vram_vga_data <= 32'h0; + // End of automatics + end else + if (vram_vga_ready) + vram_vga_data <= vram_vga_ram_out; + + always @(posedge vga_clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + vram_vga_ready_dly <= 4'h0; + // End of automatics + end else + vram_vga_ready_dly <= { vram_vga_ready_dly[2:0], vram_vga_req }; + + assign vram_vga_ready = vram_vga_ready_dly[0]; + assign vram_cpu_done = 1'b1; + + always @(posedge cpu_clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + vram_cpu_ready_dly <= 4'h0; + // End of automatics + end else + vram_cpu_ready_dly <= { vram_cpu_ready_dly[2:0], vram_cpu_req }; + + assign vram_cpu_ready = vram_cpu_ready_dly[3]; + `ifndef EXTERNAL_MCR + assign mcr_data_out = 0; + assign mcr_ready = 0; + assign mcr_done = 0; + `else + //TODO + `endif + +endmodule + +`default_nettype wire + +// Local Variables: +// verilog-library-directories: ("." "cores/xilinx" "cores/xilinx/mig_32bit/user_design/rtl") +// End: ADDED ram_controller_mister.sv Index: ram_controller_mister.sv ================================================================== --- /dev/null +++ ram_controller_mister.sv @@ -0,0 +1,249 @@ +/******************************************************************************* + * Engineer: Nicholas Nusgart + * Design Name: LM-3 CADR implementation + * Module Name: ram_controller_mister + * Project Name: LM-3 + * Description: This module is acts as the memory controller for the LM-3. It + acts as the interface from the LM-3 sdram bus to the MiSTer's + DDR3 and from the LM-3 vram bus to the VRAM (implemented as + block ram). + * Dependencies: alt_vram + * Revision: + * Revision 0.01 - File Created + * Additional Comments: +******************************************************************************/ + +`timescale 1ns/1ps +`default_nettype none + +module ram_controller_mister ( + // system interface + input clk, + input cpu_clk, + input vga_clk, + input reset, + // DDR interface + output DDRAM_CLK, + input DDRAM_BUSY, + output [7:0] DDRAM_BURSTCNT, + output [28:0] DDRAM_ADDR, + input [63:0] DDRAM_DOUT, + input DDRAM_DOUT_READY, + output DDRAM_RD, + output [63:0] DDRAM_DIN, + output [7:0] DDRAM_BE, + output DDRAM_WE, + + //// CADR xbus_sdram interface + input wire [21:0] sdram_addr, + input wire [31:0] sdram_data_in, + output [31:0] sdram_data_out, + input wire sdram_req, + input wire sdram_write, + // is the write previously requested finished + output reg sdram_done, + // is the data from the read ready + output reg sdram_ready, + + + // CADR microcode interface + input wire [13:0] mcr_addr, + input wire [48:0] mcr_data_in, + output [48:0] mcr_data_out, + input mcr_write, + output mcr_done, + output mcr_ready, + + // CADR & VGA VRAM interface + input [14:0] vram_cpu_addr, + input [31:0] vram_cpu_data_in, + output [31:0] vram_cpu_data_out, + input vram_cpu_req, + input vram_cpu_write, + output vram_cpu_done, + output vram_cpu_ready, + + input [14:0] vram_vga_addr, + output [31:0] vram_vga_data_out, + input vram_vga_req, + output vram_vga_ready + ); + + + ////// SDRAM support -- this probably needs work. Probably doesn't meet xbus requirements + ////// -- specifically, it might not take enough clock cycles. + // TODO since there is a large amount of free block ram, implement a 64 KW cache (256 KB). + // I think using a direct mapped cache would be fine here since the cachable portion of the + // address space is only 3.75 MW, so that's only 60 addresses mapping to 1 cache line. + assign DDRAM_CLK = clk; + assign DDRAM_BURSTCNT = 1; + + + + assign DDRAM_BE = 0; + + + localparam IDLE = 3'd1; + localparam WRITE = 3'd2; + localparam WRITE_BUSY = 3'd3; + localparam WRITE_WAIT = 3'd4; + localparam READ = 3'd5; + localparam READ_BUSY = 3'd6; + localparam READ_WAIT = 3'd7; + + reg [2:0] state; + reg i_sdram_rdone; + reg i_sdram_wdone; + reg [21:0] i_sdram_addr; + reg [31:0] i_sdram_wdata; + reg [31:0] i_sdram_rdata; + + // DDRAM control + assign DDRAM_ADDR = {7'b0, i_sdram_addr}; + assign DDRAM_DIN = i_sdram_wdata; + assign DDRAM_RD = (state == READ); + assign DDRAM_WE = (state == WRITE); + + + // xbus_sdram interface + always @(posedge cpu_clk) begin + sdram_ready <= i_sdram_rdone && sdram_req; + sdram_done <= i_sdram_wdone && sdram_write; + end + assign sdram_data_out = i_sdram_rdata; + + // core DDR SDRAM state machine + always @(posedge clk) begin + if (reset) begin + state <= IDLE; + i_sdram_rdone <= 0; + i_sdram_wdone <= 0; + i_sdram_addr <= 0; + i_sdram_wdata <= 0; + i_sdram_rdata <= 32'hffff_ffff; + end else begin + case (state) + // idle state + IDLE: begin + if (DDRAM_BUSY) begin + // if there is a refresh going on, can't do anything + state <= IDLE; + end else if (sdram_req) begin + // start read + state <= READ; + end else if (sdram_write) begin + // start write + state <= WRITE; + i_sdram_wdata <= sdram_data_in; + end + end + // write states + WRITE: begin + i_sdram_wdone <= 1'b0; + // wait for write to start + if (DDRAM_BUSY) state <= WRITE_BUSY; + end + WRITE_BUSY: begin + // wait for the DDRAM to complete the write + if (~DDRAM_BUSY) state <= WRITE_WAIT; + end + WRITE_WAIT: begin + // notify xbus that the write is complete + i_sdram_wdone <= 1'b1; + // once xbus stops requesting a write, return to idle + // note that this is correct behavior because xbus doesn't support bursts. + if (~sdram_write) state <= IDLE; + end + // read states + READ: begin + i_sdram_rdone <= 1'b0; + + // wait for read to start + if (DDRAM_BUSY) state <= READ_BUSY; + end + READ_BUSY: begin + // wait for DDRAM to complete the read + if (DDRAM_DOUT_READY) begin + state <= READ_WAIT; + i_sdram_rdata <= DDRAM_DOUT; + end + end + READ_WAIT: begin + // notify xbus that the read is complete + i_sdram_rdone <= 1'b1; + // once xbus stops requesting a read, return to idle + // note that this is correct behavior because xbus doesn't support bursts + if (~sdram_req) state <= IDLE; + end + endcase + end + end + + + //////////////////////////////////////////////////////////////////////////////// + reg [31:0] vram_vga_data; + reg [3:0] vram_cpu_ready_dly; + reg [3:0] vram_vga_ready_dly; + wire [31:0] vram_vga_ram_out; + + + + //wire ena_a = vram_cpu_req | vram_cpu_write; + //wire ena_b = vram_vga_req | 1'b0; + alt_vram inst ( + .address_a(vram_cpu_addr), + .address_b(vram_vga_addr), + .clock_a(cpu_clk), + .clock_b(vga_clk), + .data_a(vram_cpu_data_in), + .data_b(32'b0), + .wren_a(vram_cpu_write), + .wren_b(1'b0), + .q_a(vram_cpu_data_out), + .q_b(vram_vga_ram_out)); + + + assign vram_vga_data_out = vram_vga_ready ? vram_vga_ram_out : vram_vga_data; + + always @(posedge vga_clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + vram_vga_data <= 32'h0; + // End of automatics + end else + if (vram_vga_ready) + vram_vga_data <= vram_vga_ram_out; + + always @(posedge vga_clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + vram_vga_ready_dly <= 4'h0; + // End of automatics + end else + vram_vga_ready_dly <= { vram_vga_ready_dly[2:0], vram_vga_req }; + + assign vram_vga_ready = vram_vga_ready_dly[0]; + assign vram_cpu_done = 1'b1; + + always @(posedge cpu_clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + vram_cpu_ready_dly <= 4'h0; + // End of automatics + end else + vram_cpu_ready_dly <= { vram_cpu_ready_dly[2:0], vram_cpu_req }; + + assign vram_cpu_ready = vram_cpu_ready_dly[3]; + `ifndef EXTERNAL_MCR + assign mcr_data_out = 0; + assign mcr_ready = 0; + assign mcr_done = 0; + `else + //TODO + `endif + +endmodule +`default_nettype wire ADDED ram_controller_mister.v Index: ram_controller_mister.v ================================================================== --- /dev/null +++ ram_controller_mister.v @@ -0,0 +1,351 @@ +// ram_controller_cyc2.v --- ---!!! + +`timescale 1ns/1ps +//`default_nettype none + +module ram_controller_cyc2(/*AUTOARG*/ + // Outputs + sdram_data_out, vram_cpu_data_out, + vram_vga_data_out, mcr_data_out, lpddr_calib_done, lpddr_clk_out, + mcr_done, mcr_ready, sdram_done, sdram_ready, vram_cpu_done, + vram_cpu_ready, vram_vga_ready, + /* + mcb3_dram_a, mcb3_dram_ba, + mcb3_dram_cas_n, mcb3_dram_ck, mcb3_dram_ck_n, mcb3_dram_cke, + mcb3_dram_dm, mcb3_dram_ras_n, mcb3_dram_udm, mcb3_dram_we_n, + */ + // Inouts + //mcb3_dram_dq, mcb3_dram_dqs, mcb3_dram_udqs, mcb3_rzq, + // Inputs + mcr_addr, vram_cpu_addr, vram_vga_addr, sdram_addr, sdram_data_in, + vram_cpu_data_in, mcr_data_in, clk, cpu_clk, fetch, lpddr_reset, + machrun, mcr_write, prefetch, reset, sdram_req, sdram_write, + sysclk, vga_clk, vram_cpu_req, vram_cpu_write, vram_vga_req, + + //LPDDR2 + lpddr2_ca, lpddr2_dq, lpddr2_dm, lpddr2_dqs, lpddr2_dqsn, lpddr2_cke, + lpddr2_csn, lpddr2_ckn, lpddr2_ck, + ); + + output [9:0] lpddr2_ca; + inout [15:0] lpddr2_dq; + output [1:0] lpddr2_dm; + inout [1:0] lpddr2_dqs; + inout [1:0] lpddr2_dqsn; + output lpddr2_cke; + output lpddr2_csn; + inout lpddr2_ckn; + inout lpddr2_ck; + //inout [15:0] mcb3_dram_dq; + //inout [1:0] mcb3_dram_dqs; + //inout [1:0] mcb3_dram_udqs; + //inout mcb3_rzq; + input [13:0] mcr_addr; + input [14:0] vram_cpu_addr; + input [14:0] vram_vga_addr; + input [21:0] sdram_addr; + input [31:0] sdram_data_in; + input [31:0] vram_cpu_data_in; + input [48:0] mcr_data_in; + input clk; + input cpu_clk; + input fetch; + input lpddr_reset; + input machrun; + input mcr_write; + input prefetch; + input reset; + input sdram_req; + input sdram_write; + input sysclk; + input vga_clk; + input vram_cpu_req; + input vram_cpu_write; + input vram_vga_req; + //output [12:0] mcb3_dram_a; + //output [1:0] mcb3_dram_ba; + output [31:0] sdram_data_out; + output [31:0] vram_cpu_data_out; + output [31:0] vram_vga_data_out; + output [48:0] mcr_data_out; + output lpddr_calib_done; + output lpddr_clk_out; + /* + output mcb3_dram_cas_n; + output mcb3_dram_ck; + output mcb3_dram_ck_n; + output mcb3_dram_cke; + output mcb3_dram_dm; + output mcb3_dram_ras_n; + output mcb3_dram_udm; + output mcb3_dram_we_n; + */ + output mcr_done; + output mcr_ready; + output sdram_done; + output sdram_ready; + output vram_cpu_done; + output vram_cpu_ready; + output vram_vga_ready; + + //////////////////////////////////////////////////////////////////////////////// + + parameter [2:0] + NSD_IDLE = 0, + NSD_READ = 1, + NSD_READBSY = 2, + NSD_READW = 3, + NSD_WRITE = 4, + NSD_WRITEBSY = 5, + NSD_WRITEW = 6; + parameter [6:0] + SD_IDLE = 7'b0000001, + SD_READ = 7'b0000010, + SD_READBSY = 7'b0000100, + SD_READW = 7'b0001000, + SD_WRITE = 7'b0010000, + SD_WRITEBSY = 7'b0100000, + SD_WRITEW = 7'b1000000; + + reg [31:0] sdram_out; + reg [31:0] vram_vga_data; + reg [3:0] vram_cpu_ready_dly; + reg [3:0] vram_vga_ready_dly; + reg [6:0] sdram_state; + reg int_sdram_done; + reg int_sdram_ready; + reg sdram_done; + reg sdram_ready; + + wire [29:0] lpddr_addr; + wire [2:0] lpddr_cmd; + wire [31:0] sdram_resp_in; + wire [31:0] vram_vga_ram_out; + wire [6:0] sdram_state_next; + //wire c3_calib_done; + wire clock; + wire i_sdram_req; + wire i_sdram_write; + wire lpddr_clk; + wire lpddr_cmd_en; + wire lpddr_cmd_full; + wire lpddr_rd_done; + wire lpddr_rd_empty; + wire lpddr_rd_rdy; + wire lpddr_wr_done; + wire lpddr_wr_en; + wire lpddr_wr_full; + wire lpddr_wr_rdy; + wire reset; + wire sys_clk; + wire sys_rst; + + //////////////////////////////////////////////////////////////////////////////// + + always @(posedge clk) + if (reset) begin + sdram_state <= SD_IDLE; + end else + sdram_state <= sdram_state_next; + + assign sdram_state_next = + (sdram_state[NSD_IDLE] && sdram_req) ? SD_READ : + (sdram_state[NSD_IDLE] && sdram_write) ? SD_WRITE : + (sdram_state[NSD_READ] && lpddr_rd_rdy) ? SD_READBSY : + (sdram_state[NSD_READBSY] && lpddr_rd_done) ? SD_READW : + (sdram_state[NSD_READW] && ~sdram_req) ? SD_IDLE : + (sdram_state[NSD_WRITE] && lpddr_wr_rdy) ? SD_WRITEBSY : + (sdram_state[NSD_WRITEBSY] && lpddr_wr_done) ? SD_WRITEW : + (sdram_state[NSD_WRITEW] && ~sdram_write) ? SD_IDLE : + sdram_state; + assign i_sdram_req = sdram_state[NSD_READ]; + assign i_sdram_write = sdram_state[NSD_WRITE]; + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + sdram_out <= 32'h0; + // End of automatics + end else begin + if (sdram_state[NSD_READBSY]) begin + sdram_out <= sdram_addr[21:17] == 0 ? sdram_resp_in : 32'hffffffff; + end + end + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + int_sdram_ready <= 1'h0; + // End of automatics + end else if (sdram_state[NSD_READ]) + int_sdram_ready <= 1'b0; + else if (sdram_state[NSD_READW]) + int_sdram_ready <= 1'b1; + + always @(posedge clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + int_sdram_done <= 1'h0; + // End of automatics + end else if (sdram_state[NSD_WRITE]) + int_sdram_done <= 1'b0; + else if (sdram_state[NSD_WRITEW]) + int_sdram_done <= 1'b1; + + assign sdram_data_out = sdram_out; + + always @(posedge cpu_clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + sdram_ready <= 1'h0; + // End of automatics + end else + sdram_ready <= int_sdram_ready && sdram_req; + + always @(posedge cpu_clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + sdram_done <= 1'h0; + // End of automatics + end else + sdram_done <= int_sdram_done && sdram_write; + + assign lpddr_cmd = sdram_write ? 3'b000 : 3'b001; + assign lpddr_addr = { 6'b0, sdram_addr, 2'b0 }; + assign lpddr_cmd_en = (sdram_state[NSD_READ] && sdram_state_next == SD_READBSY) || + (sdram_state[NSD_WRITE] && sdram_state_next == SD_WRITEBSY); + //assign lpddr_rd_rdy = ~lpddr_cmd_full; + //assign lpddr_rd_done = ~lpddr_rd_empty; + assign lpddr_wr_rdy = ~lpddr_cmd_full && ~lpddr_wr_full; +// assign lpddr_wr_done = 1'b1; + assign lpddr_wr_en = sdram_state[NSD_WRITEBSY]; + assign lpddr_clk_out = lpddr_clk; + //assign lpddr_calib_done = c3_calib_done; + wire ddr_sysclk; + assign ddr_sysclk = sysclk; + + altera_ddr intf( + // clocks + .pll_ref_clk(ddr_sysclk), + .afi_clk(lpddr_clk), + //.afi_half_clk(clk), + // reset + .global_reset_n(lpddr_reset), + // request a read or write + .avl_read_req(i_sdram_req), + .avl_write_req(i_sdram_write), + // address + .avl_addr(lpddr_addr), + // data to write + .avl_wdata(sdram_data_in), + // controls size + .avl_be(8'b00001111), + .avl_size(2'b11), + .avl_ready(lpddr_rd_rdy), + // output data read + .avl_rdata(sdram_resp_in), + .avl_rdata_valid(lpddr_rd_done), + //.local_rdvalid_in_n, + .local_init_done(lpddr_calib_done), + //.local_refresh_ack, // intentionally left blank + //.avl_write_req(lpddr_wr_done), + //.ddr_odt(mcb3_rzq), // odt resistor + .pll_mem_clk(mcb3_dram_ck), + .pll_write_clk(mcb3_dram_ck_n), + .mem_cs_n(lpddr2_csn), + .mem_cke(lpddr2_ck), + .mem_ca(lpddr2_ca), + //.mem_ba(lppdr2_ba), + //.ddr_ras_n(mcb3_dram_ras_n), + //.ddr_cas_n(mcb3_dram_cas_n), + //.ddr_we_n(mcb3_dram_we_n), + .mem_dm(lppdr2_dm), + .mem_dq(lpddr2_dq), + .mem_dqs(lpddr2_dqs), + .mem_dqs_n(lpddr2_dqsn) + ); + + /* + //LPDDR2 + output [9:0] lpddr2_ca, + inout [15:0] lpddr2_dq, + output [1:0] lpddr2_dm, + inout lpddr2_dqs1n, + inout lpddr2_dqs1, + inout lpddr2_dqs0n, + inout lpddr2_dqs0, + output lpddr2_cke, + output lpddr2_csn, + inout lpddr2_ckn, + inout lpddr2_ck, + */ + + wire ena_a = vram_cpu_req | vram_cpu_write; + wire ena_b = vram_vga_req | 1'b0; + alt_vram inst ( + .address_a(vram_cpu_addr), + .address_b(vram_vga_addr), + .clock_a(cpu_clk), + .clock_b(vga_clk), + .data_a(vram_cpu_data_in), + .data_b(32'b0), + .wren_a(ena_a), + .wren_b(vram_cpu_write), + .q_a(vram_cpu_data_out), + .q_b(vram_vga_ram_out)); + + + assign vram_vga_data_out = vram_vga_ready ? vram_vga_ram_out : vram_vga_data; + + always @(posedge vga_clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + vram_vga_data <= 32'h0; + // End of automatics + end else + if (vram_vga_ready) + vram_vga_data <= vram_vga_ram_out; + + always @(posedge vga_clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + vram_vga_ready_dly <= 4'h0; + // End of automatics + end else + vram_vga_ready_dly <= { vram_vga_ready_dly[2:0], vram_vga_req }; + + assign vram_vga_ready = vram_vga_ready_dly[0]; + assign vram_cpu_done = 1'b1; + + always @(posedge cpu_clk) + if (reset) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + vram_cpu_ready_dly <= 4'h0; + // End of automatics + end else + vram_cpu_ready_dly <= { vram_cpu_ready_dly[2:0], vram_cpu_req }; + + assign vram_cpu_ready = vram_cpu_ready_dly[3]; + `ifndef EXTERNAL_MCR + assign mcr_data_out = 0; + assign mcr_ready = 0; + assign mcr_done = 0; + `else + //TODO + `endif + +endmodule + +`default_nettype wire + +// Local Variables: +// verilog-library-directories: ("." "cores/xilinx" "cores/xilinx/mig_32bit/user_design/rtl") +// End: ADDED support_cyc2.v Index: support_cyc2.v ================================================================== --- /dev/null +++ support_cyc2.v @@ -0,0 +1,174 @@ +// support_lx45.v --- ---!!! + +`timescale 1ns/1ps +`default_nettype none + +module support_cyc2(/*AUTOARG*/ + // Outputs + boot, dcm_reset, halt, interrupt, lpddr_reset, reset, + // Inputs + button_b, button_c, button_h, button_r, cpu_clk, lpddr_calib_done, + sysclk + ); + + input button_b; + input button_c; + input button_h; + input button_r; + input cpu_clk; + input lpddr_calib_done; + input sysclk; + output boot; + output dcm_reset; + output halt; + output interrupt; + output lpddr_reset; + output reset; + + //////////////////////////////////////////////////////////////////////////////// + + parameter + c_init = 3'd0, + c_reset1 = 3'd1, + c_reset2 = 3'd2, + c_reset3 = 3'd3, + c_boot = 3'd4, + c_wait = 3'd5, + c_idle = 3'd6; + parameter + r_init = 3'd0, + r_reset1 = 3'd1, + r_reset2 = 3'd2, + r_reset3 = 3'd3, + r_reset4 = 3'd4, + r_reset5 = 3'd5, + r_wait = 3'd6, + r_idle = 3'd7; + + reg [11:0] sys_slowcount; + reg [1:0] cpu_slowcount; + reg [2:0] cpu_state; + reg [2:0] reset_state; + reg [3:0] lpddr_reset_holdoff_cnt; + reg [5:0] sys_medcount; + reg [9:0] hold; + reg press_history; + + wire [2:0] cpu_state_next; + wire [2:0] reset_state_next; + wire cpu_in_reset; + wire cpu_slowevent; + wire lpddr_reset_holdoff; + wire press_detected; + wire pressed; + wire sys_medevent; + wire sys_slowevent; + + /*AUTOWIRE*/ + /*AUTOREG*/ + + //////////////////////////////////////////////////////////////////////////////// + + assign interrupt = 1'b0; + assign halt = 1'b0; + + initial begin + reset_state = 0; + cpu_state = 0; + sys_slowcount = 0; + sys_medcount = 0; + cpu_slowcount = 0; + hold = 0; + press_history = 0; + end + + always @(posedge cpu_clk or posedge dcm_reset) + if (dcm_reset) + cpu_slowcount <= 0; + else + cpu_slowcount <= cpu_slowcount + 2'd1; + + initial + lpddr_reset_holdoff_cnt = 0; + + always @(posedge sysclk) + if (lpddr_reset_holdoff_cnt != 4'd4) + lpddr_reset_holdoff_cnt <= lpddr_reset_holdoff_cnt + 4'd1; + + assign lpddr_reset_holdoff = lpddr_reset_holdoff_cnt != 4'd4; + + assign cpu_in_reset = (reset_state == r_init || + reset_state == r_reset1 || + reset_state == r_reset2 || + reset_state == r_reset3) || + (cpu_state == c_init || + cpu_state == c_reset1 || + cpu_state == c_reset2 || + cpu_state == c_reset3); + assign dcm_reset = reset_state == r_init; + assign lpddr_reset = (reset_state == r_init || reset_state == r_reset1) && + ~lpddr_reset_holdoff ? 1'b1 : 1'b0; + assign reset = cpu_in_reset; + assign boot = cpu_state == c_reset3 || cpu_state == c_boot; + assign cpu_state_next = + (cpu_state == c_init && reset_state == r_reset4) ? c_reset1 : + (cpu_state == c_reset1) ? c_reset2 : + (cpu_state == c_reset2) ? c_reset3 : + (cpu_state == c_reset3) ? c_boot : + (cpu_state == c_boot) ? c_wait : + (cpu_state == c_wait && reset_state == r_idle) ? c_idle : + (cpu_state == c_idle && reset_state == r_reset4) ? c_reset1 : + cpu_state; + assign cpu_slowevent = cpu_slowcount == 2'b11; + + always @(posedge cpu_clk) + if (cpu_slowevent) begin + cpu_state <= cpu_state_next; + end + + assign reset_state_next = + (reset_state == r_init) ? r_reset1 : + (reset_state == r_reset1) ? r_reset2 : + (reset_state == r_reset2) ? r_reset3 : + (reset_state == r_reset3 && lpddr_calib_done) ? r_reset4 : + (reset_state == r_reset4 && cpu_state != c_idle) ? r_wait : + (reset_state == r_wait & ~pressed) ? r_idle : + (reset_state == r_idle && pressed) ? r_reset1 : + reset_state; + + always @(posedge sysclk) + if (sys_medevent) begin + reset_state <= reset_state_next; + end + + always @(posedge sysclk) begin + sys_medcount <= sys_medcount + 6'd1; + end + + assign sys_medevent = sys_medcount == 6'b111111; + + always @(posedge sysclk) begin + sys_slowcount <= sys_slowcount + 12'd1; + end + + assign sys_slowevent = sys_slowcount == 12'hfff; + + always @(posedge sysclk) + if (sys_slowevent) + hold <= { hold[8:0], button_r }; + + assign press_detected = hold == 10'b1111111111; + + always @(posedge sysclk) + if (sys_slowevent) + press_history <= press_detected; + + assign pressed = (!press_history && press_detected); + +endmodule + +`default_nettype wire + +// Local Variables: +// verilog-library-directories: (".") +// End: ADDED support_mister.v Index: support_mister.v ================================================================== --- /dev/null +++ support_mister.v @@ -0,0 +1,174 @@ +// support_lx45.v --- ---!!! + +`timescale 1ns/1ps +`default_nettype none + +module support_cyc2(/*AUTOARG*/ + // Outputs + boot, dcm_reset, halt, interrupt, lpddr_reset, reset, + // Inputs + button_b, button_c, button_h, button_r, cpu_clk, lpddr_calib_done, + sysclk + ); + + input button_b; + input button_c; + input button_h; + input button_r; + input cpu_clk; + input lpddr_calib_done; + input sysclk; + output boot; + output dcm_reset; + output halt; + output interrupt; + output lpddr_reset; + output reset; + + //////////////////////////////////////////////////////////////////////////////// + + parameter + c_init = 3'd0, + c_reset1 = 3'd1, + c_reset2 = 3'd2, + c_reset3 = 3'd3, + c_boot = 3'd4, + c_wait = 3'd5, + c_idle = 3'd6; + parameter + r_init = 3'd0, + r_reset1 = 3'd1, + r_reset2 = 3'd2, + r_reset3 = 3'd3, + r_reset4 = 3'd4, + r_reset5 = 3'd5, + r_wait = 3'd6, + r_idle = 3'd7; + + reg [11:0] sys_slowcount; + reg [1:0] cpu_slowcount; + reg [2:0] cpu_state; + reg [2:0] reset_state; + reg [3:0] lpddr_reset_holdoff_cnt; + reg [5:0] sys_medcount; + reg [9:0] hold; + reg press_history; + + wire [2:0] cpu_state_next; + wire [2:0] reset_state_next; + wire cpu_in_reset; + wire cpu_slowevent; + wire lpddr_reset_holdoff; + wire press_detected; + wire pressed; + wire sys_medevent; + wire sys_slowevent; + + /*AUTOWIRE*/ + /*AUTOREG*/ + + //////////////////////////////////////////////////////////////////////////////// + + assign interrupt = 1'b0; + assign halt = 1'b0; + + initial begin + reset_state = 0; + cpu_state = 0; + sys_slowcount = 0; + sys_medcount = 0; + cpu_slowcount = 0; + hold = 0; + press_history = 0; + end + + always @(posedge cpu_clk or posedge dcm_reset) + if (dcm_reset) + cpu_slowcount <= 0; + else + cpu_slowcount <= cpu_slowcount + 2'd1; + + initial + lpddr_reset_holdoff_cnt = 0; + + always @(posedge sysclk) + if (lpddr_reset_holdoff_cnt != 4'd4) + lpddr_reset_holdoff_cnt <= lpddr_reset_holdoff_cnt + 4'd1; + + assign lpddr_reset_holdoff = lpddr_reset_holdoff_cnt != 4'd4; + + assign cpu_in_reset = (reset_state == r_init || + reset_state == r_reset1 || + reset_state == r_reset2 || + reset_state == r_reset3) || + (cpu_state == c_init || + cpu_state == c_reset1 || + cpu_state == c_reset2 || + cpu_state == c_reset3); + assign dcm_reset = reset_state == r_init; + assign lpddr_reset = (reset_state == r_init || reset_state == r_reset1) && + ~lpddr_reset_holdoff ? 1'b1 : 1'b0; + assign reset = cpu_in_reset; + assign boot = cpu_state == c_reset3 || cpu_state == c_boot; + assign cpu_state_next = + (cpu_state == c_init && reset_state == r_reset4) ? c_reset1 : + (cpu_state == c_reset1) ? c_reset2 : + (cpu_state == c_reset2) ? c_reset3 : + (cpu_state == c_reset3) ? c_boot : + (cpu_state == c_boot) ? c_wait : + (cpu_state == c_wait && reset_state == r_idle) ? c_idle : + (cpu_state == c_idle && reset_state == r_reset4) ? c_reset1 : + cpu_state; + assign cpu_slowevent = cpu_slowcount == 2'b11; + + always @(posedge cpu_clk) + if (cpu_slowevent) begin + cpu_state <= cpu_state_next; + end + + assign reset_state_next = + (reset_state == r_init) ? r_reset1 : + (reset_state == r_reset1) ? r_reset2 : + (reset_state == r_reset2) ? r_reset3 : + (reset_state == r_reset3 && lpddr_calib_done) ? r_reset4 : + (reset_state == r_reset4 && cpu_state != c_idle) ? r_wait : + (reset_state == r_wait & ~pressed) ? r_idle : + (reset_state == r_idle && pressed) ? r_reset1 : + reset_state; + + always @(posedge sysclk) + if (sys_medevent) begin + reset_state <= reset_state_next; + end + + always @(posedge sysclk) begin + sys_medcount <= sys_medcount + 6'd1; + end + + assign sys_medevent = sys_medcount == 6'b111111; + + always @(posedge sysclk) begin + sys_slowcount <= sys_slowcount + 12'd1; + end + + assign sys_slowevent = sys_slowcount == 12'hfff; + + always @(posedge sysclk) + if (sys_slowevent) + hold <= { hold[8:0], button_r }; + + assign press_detected = hold == 10'b1111111111; + + always @(posedge sysclk) + if (sys_slowevent) + press_history <= press_detected; + + assign pressed = (!press_history && press_detected); + +endmodule + +`default_nettype wire + +// Local Variables: +// verilog-library-directories: (".") +// End: ADDED top_cyc2.sv Index: top_cyc2.sv ================================================================== --- /dev/null +++ top_cyc2.sv @@ -0,0 +1,273 @@ +// System +// top_cyc2.v --- ---!!! + +`timescale 1ns/1ps +//`default_nettype none + +`define enable_mmc +`define enable_vga +`define enable_ps2 +`define enable_spy_port + +module top_cyc2(/*AUTOARG*/ + // Outputs + rs232_txd, led, vga_hsync, vga_vsync, vga_r, vga_g, vga_b, mmc_cs, + mmc_do, mmc_sclk, + + // Inouts + ms_ps2_clk, ms_ps2_data, + + // Inputs + rs232_rxd, sysclk, kb_ps2_clk, kb_ps2_data, mmc_di, switch, + //LPDDR2 + lpddr2_ca, lpddr2_dq, lpddr2_dm, lpddr2_dqs1n, lpddr2_dqs1, + lpddr2_dqs0n, lpddr2_dqs0, lpddr2_cke, lpddr2_csn, lpddr2_ckn, lpddr2_ck, + ); + + input rs232_rxd; + output rs232_txd; + output [3:0] led; + input sysclk; + input kb_ps2_clk; + input kb_ps2_data; + inout ms_ps2_clk; + inout ms_ps2_data; + output vga_hsync; + output vga_vsync; + output vga_r; + output vga_g; + output vga_b; + output mmc_cs; + output mmc_do; + output mmc_sclk; + input mmc_di; + input switch; + //LPDDR2 + output [9:0] lpddr2_ca; + inout [15:0] lpddr2_dq; + output [1:0] lpddr2_dm; + inout lpddr2_dqs1n; + inout lpddr2_dqs1; + inout lpddr2_dqs0n; + inout lpddr2_dqs0; + output lpddr2_cke; + output lpddr2_csn; + inout lpddr2_ckn; + inout lpddr2_ck; +/* + inout [15:0] mcb3_dram_dq; + output [12:0] mcb3_dram_a; + output [1:0] mcb3_dram_ba; + output mcb3_dram_cke; + output mcb3_dram_ras_n; + output mcb3_dram_cas_n; + output mcb3_dram_we_n; + output mcb3_dram_dm; + inout mcb3_dram_udqs; + inout mcb3_rzq; + output mcb3_dram_udm; + inout mcb3_dram_dqs; + output mcb3_dram_ck; + output mcb3_dram_ck_n; +*/ + //////////////////////////////////////////////////////////////////////////////// + + reg [3:0] clkcnt; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire boot; // From support of support_lx45.v + wire [15:0] busint_spyout; // From lm3 of lm3.v + wire dcm_reset; // From support of support_lx45.v + wire [4:0] disk_state; // From lm3 of lm3.v + wire fetch; // From lm3 of lm3.v + wire halt; // From support of support_lx45.v + wire interrupt; // From support of support_lx45.v + wire lpddr_calib_done; // From rc of ram_controller_lx45.v + wire lpddr_reset; // From support of support_lx45.v + wire [13:0] mcr_addr; // From lm3 of lm3.v + wire [48:0] mcr_data_out; // From lm3 of lm3.v + wire [48:0] mcr_data_in; // From lm3 of lm3.v + wire mcr_done; // From rc of ram_controller_lx45.v + wire mcr_ready; // From rc of ram_controller_lx45.v + wire mcr_write; // From lm3 of lm3.v + wire prefetch; // From lm3 of lm3.v + wire reset; // From support of support_lx45.v + wire [21:0] sdram_addr; // From lm3 of lm3.v + wire [31:0] sdram_data_cpu2rc; // From lm3 of lm3.v + wire [31:0] sdram_data_rc2cpu; // From lm3 of lm3.v + wire sdram_done; // From rc of ram_controller_lx45.v + wire sdram_ready; // From rc of ram_controller_lx45.v + wire sdram_req; // From lm3 of lm3.v + wire sdram_write; // From lm3 of lm3.v + wire spy_rd; // From lm3 of lm3.v + wire [3:0] spy_reg; // From lm3 of lm3.v + wire spy_wr; // From lm3 of lm3.v + wire vga_blank; // From lm3 of lm3.v + wire [14:0] vram_cpu_addr; // From lm3 of lm3.v + wire [31:0] vram_cpu_data_out; // From lm3 of lm3.v + wire vram_cpu_done; // From rc of ram_controller_lx45.v + wire vram_cpu_ready; // From rc of ram_controller_lx45.v + wire vram_cpu_req; // From lm3 of lm3.v + wire vram_cpu_write; // From lm3 of lm3.v + wire [14:0] vram_vga_addr; // From lm3 of lm3.v + wire [31:0] vram_vga_data_out; // From rc of ram_controller_lx45.v + wire [31:0] vram_cpu_data_in; // From rc of ram_controller_lx45.v + wire vram_vga_ready; // From rc of ram_controller_lx45.v + wire vram_vga_req; // From lm3 of lm3.v + // End of automatics + + //////////////////////////////////////////////////////////////////////////////// + + assign clk50 = sysclk; + + clkwiz clocking_inst(.inclk0(clk50), .c0(vga_clk), .areset(dcm_reset), .locked(vga_clk_locked)); + + initial clkcnt = 0; + always @(posedge clk50) + clkcnt <= clkcnt + 4'd1; + + assign cpu_clk = clkcnt[0]; + + support_cyc2 support + ( + .sysclk(clk50), + .button_r(switch), + .button_b(1'b0), + .button_h(1'b0), + .button_c(1'b0), + /*AUTOINST*/ + // Outputs + .boot (boot), + .dcm_reset (dcm_reset), + .halt (halt), + .interrupt (interrupt), + .lpddr_reset (lpddr_reset), + .reset (reset), + // Inputs + .cpu_clk (cpu_clk), + .lpddr_calib_done (lpddr_calib_done)); + + ram_controller_cyc2 rc + ( + .lpddr_clk_out(), + .clk(clk50), + .mcr_data_out(mcr_data_in), + .mcr_data_in(mcr_data_out), + .sdram_data_in(sdram_data_cpu2rc), + .sdram_data_out(sdram_data_rc2cpu), + .vram_cpu_data_in(vram_cpu_data_out), + .vram_cpu_data_out(vram_cpu_data_in), + // lpddr + .lpddr2_ca(lpddr2_ca), + .lpddr2_dq(lpddr2_dq), + .lpddr2_dm(lpddr2_dm), + .lpddr2_dqsn({lpddr2_dqs1n, lpddr2dqs0n}), + .lpddr2_dqs({lpddr2dqs1, lpddr2dqs0}), + .lpddr2_cke(lpddr2_cke), + .lpddr2_csn(lpddr2_csn), + .lpddr2_ckn(lpddr2_ckn), + .lpddr2_ck(lpddr2_ck), + /*AUTOINST*/ + // Outputs + .vram_vga_data_out (vram_vga_data_out[31:0]), + .lpddr_calib_done (lpddr_calib_done), + .mcr_done (mcr_done), + .mcr_ready (mcr_ready), + .sdram_done (sdram_done), + .sdram_ready (sdram_ready), + .vram_cpu_done (vram_cpu_done), + .vram_cpu_ready (vram_cpu_ready), + .vram_vga_ready (vram_vga_ready), + // Inouts + // Inputs + .mcr_addr (mcr_addr[13:0]), + .vram_cpu_addr (vram_cpu_addr[14:0]), + .vram_vga_addr (vram_vga_addr[14:0]), + .sdram_addr (sdram_addr[21:0]), + .cpu_clk (cpu_clk), + .fetch (fetch), + .lpddr_reset (lpddr_reset), + .machrun (machrun), + .mcr_write (mcr_write), + .prefetch (prefetch), + .reset (reset), + .sdram_req (sdram_req), + .sdram_write (sdram_write), + .sysclk (sysclk), + .vga_clk (vga_clk), + .vram_cpu_req (vram_cpu_req), + .vram_cpu_write (vram_cpu_write), + .vram_vga_req (vram_vga_req)); + + lm3 lm3(/*AUTOINST*/ + // Outputs + .sdram_addr (sdram_addr[21:0]), + .sdram_data_cpu2rc (sdram_data_cpu2rc[31:0]), + .sdram_req (sdram_req), + .sdram_write (sdram_write), + .vram_cpu_addr (vram_cpu_addr[14:0]), + .vram_cpu_data_out (vram_cpu_data_out[31:0]), + .vram_cpu_req (vram_cpu_req), + .vram_cpu_write (vram_cpu_write), + .spy_reg (spy_reg[3:0]), + .busint_spyout (busint_spyout[15:0]), + .spy_rd (spy_rd), + .spy_wr (spy_wr), + .disk_state (disk_state[4:0]), + .fetch (fetch), + .prefetch (prefetch), + .mcr_addr (mcr_addr[13:0]), + .mcr_data_out (mcr_data_out[48:0]), + .mcr_write (mcr_write), + .mmc_cs (mmc_cs), + .mmc_do (mmc_do), + .mmc_sclk (mmc_sclk), + .vram_vga_addr (vram_vga_addr[14:0]), + .vram_vga_req (vram_vga_req), + .vga_blank (vga_blank), + .vga_r (vga_r), + .vga_g (vga_g), + .vga_b (vga_b), + .vga_hsync (vga_hsync), + .vga_vsync (vga_vsync), + .rs232_txd (rs232_txd), + // Inouts + .ms_ps2_clk (ms_ps2_clk), + .ms_ps2_data (ms_ps2_data), + // Inputs + .clk50 (clk50), + .reset (reset), + .sdram_data_rc2cpu (sdram_data_rc2cpu[31:0]), + .sdram_done (sdram_done), + .sdram_ready (sdram_ready), + .vram_cpu_data_in (vram_cpu_data_in[31:0]), + .vram_cpu_done (vram_cpu_done), + .vram_cpu_ready (vram_cpu_ready), + .cpu_clk (cpu_clk), + .boot (boot), + .halt (halt), + .interrupt (interrupt), + .mcr_data_in (mcr_data_in[48:0]), + .mcr_ready (mcr_ready), + .mcr_done (mcr_done), + .mmc_di (mmc_di), + .vram_vga_data_out (vram_vga_data_out[31:0]), + .vram_vga_ready (vram_vga_ready), + .vga_clk (vga_clk), + .kb_ps2_clk (kb_ps2_clk), + .kb_ps2_data (kb_ps2_data), + .rs232_rxd (rs232_rxd)); + + assign led[3] = 1'b0; + assign led[2] = disk_state[1]; + assign led[1] = disk_state[2]; + assign led[0] = reset; + +endmodule + +`default_nettype wire + +// Local Variables: +// verilog-library-directories: (".") +// End: ADDED ucadr-mcr-841.bin Index: ucadr-mcr-841.bin ================================================================== --- /dev/null +++ ucadr-mcr-841.bin cannot compute difference between binary files ADDED ucadr-mcr-841.hex Index: ucadr-mcr-841.hex ================================================================== --- /dev/null +++ ucadr-mcr-841.hex @@ -0,0 +1,3512 @@ +/* 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0005FB00 0005FB00 0005FB00 0005FB00 +@00005FFA 0005FB00 0005FB00 0005FB00 0005FB00 0005FB00 0005FB00 Index: vga_display.v ================================================================== --- vga_display.v +++ vga_display.v @@ -2,15 +2,25 @@ `timescale 1ns/1ps `default_nettype none module vga_display(/*AUTOARG*/ - // Outputs - vram_addr, vram_req, vga_r, vga_b, vga_g, vga_hsync, vga_vsync, - vga_blank, - // Inputs - vga_clk, reset, vram_data, vram_ready + // system + input wire vga_clk, + input wire reset, + // videoram + output [14:0] vram_addr, + input [31:0] vram_data, + output wire vram_req, + input wire vram_ready, + // VGA outputs + output wire vga_r, + output wire vga_b, + output wire vga_g, + output wire vga_hsync, + output wire vga_vsync, + output wire vga_blank ); parameter H_DISP = 1280; parameter H_FPORCH = 16; parameter H_SYNC = 100; @@ -22,25 +32,10 @@ parameter V_BPORCH = 38; parameter BOX_WIDTH = 768; parameter BOX_HEIGHT = 896; - input vga_clk; - input reset; - - output [14:0] vram_addr; - input [31:0] vram_data; - input vram_ready; - output vram_req; - - output vga_r; - output vga_b; - output vga_g; - output vga_hsync; - output vga_vsync; - output vga_blank; - //////////////////////////////////////////////////////////////////////////////// localparam H_COUNTER_MAX = (H_DISP + H_FPORCH + H_SYNC + H_BPORCH); localparam V_COUNTER_MAX = (V_DISP + V_FPORCH + V_SYNC + V_BPORCH); @@ -106,25 +101,25 @@ /*AUTORESET*/ // Beginning of autoreset for uninitialized flops h_counter <= 11'h0; // End of automatics end else if (h_counter >= H_COUNTER_MAX) - h_counter <= 0; + h_counter <= 11'b0; else - h_counter <= h_counter + 1; + h_counter <= h_counter + 11'b1; always @(posedge vga_clk or posedge reset) if (reset) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops v_counter <= 11'h0; // End of automatics end else if (vclk) begin if (v_counter >= V_COUNTER_MAX) - v_counter <= 0; + v_counter <= 11'b0; else - v_counter <= v_counter + 1; + v_counter <= v_counter + 11'b1; end //////////////////////////////////////////////////////////////////////////////// // Horizontal and vertical position @@ -134,15 +129,15 @@ // Beginning of autoreset for uninitialized flops h_pos <= 11'h0; // End of automatics end else if (h_in_box) begin if (h_pos >= BOX_WIDTH) - h_pos <= 0; + h_pos <= 11'b0; else - h_pos <= h_pos + 1; + h_pos <= h_pos + 11'b1; end else - h_pos <= 0; + h_pos <= 11'b0; always @(posedge vga_clk or posedge reset) if (reset) begin /*AUTORESET*/ // Beginning of autoreset for uninitialized flops @@ -149,15 +144,15 @@ v_pos <= 11'h0; // End of automatics end else if (vclk) begin if (v_in_box) begin if (v_pos >= BOX_HEIGHT - 1) - v_pos <= 0; + v_pos <= 11'b0; else - v_pos <= v_pos + 1; + v_pos <= v_pos + 11'b1; end else - v_pos <= 0; + v_pos <= 11'b0; end //////////////////////////////////////////////////////////////////////////////// // Grab data from VRAM @@ -221,11 +216,11 @@ // End of automatics end else begin if (~v_in_box) v_addr <= 0; else if (v_addr_inc) - v_addr <= v_addr + 1; + v_addr <= v_addr + 15'b1; end wire preload, preload1, preload2; // Increment once before visable, don't increment after last load. Index: xbus_io.v ================================================================== --- xbus_io.v +++ xbus_io.v @@ -5,11 +5,11 @@ `include ".version" module xbus_io(/*AUTOARG*/ // Outputs - dataout, ack, decode, interrupt, vector, + dataout, ack, decode, interrupt, vector, o_audio, // Inputs clk, reset, addr, datain, req, write, ms_ready, ms_x, ms_y, ms_button, kb_ready, kb_data ); @@ -32,11 +32,11 @@ input kb_ready; input [15:0] kb_data; output [7:0] vector; - + output [15:0] o_audio; //////////////////////////////////////////////////////////////////////////////// reg [3:0] iob_csr; reg [3:0] iob_rdy; @@ -47,10 +47,13 @@ reg [11:0] mouse_y; reg [1:0] mouse_rawy; reg mouse_tail; reg mouse_middle; reg mouse_head; + // is this correct???? + reg [15:0] audio_level; + assign o_audio = audio_level; reg hz60_enabled; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) @@ -88,10 +91,14 @@ begin case (addr) 22'o17772045: begin iob_csr <= datain[3:0]; end + 22'o17772044: begin + // TODO implement click audio correctly: this may be completely wrong + audio_level <= datain[15:0]; + end endcase end endtask task bus_read; @@ -119,10 +126,11 @@ dataout = { 16'b0, mouse_rawy, mouse_rawx, mouse_x }; end 22'o17772044: begin + // click audio does nothing useful on read end 22'o17772045: dataout = { 24'b0, iob_rdy, iob_csr }; 22'o17772050: begin dataout = { 16'b0, us_clk[15:0] };