hdlmake.mk

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hdlmake.mk --- simple HDL build system

hdlmake.mk tries to provide a unified user environment for working with FPGAs.

Minimum requirements:

For synthesise, running simulations, test benches, or doing formal verification additional tools might be required.

The following targets are always available:

	all		Compiles all test-benches and simulation (if any).
	info		Show current configuration.
	check		Runs all test-benches (if any).
	clean		Cleans up any build artifacts.
	help		Prints out a help message.
	indent		Format code using verilog-mode and GNU Emacs.

Creating a very simple project

The absolutely simplest project consists of one GNUmakefile (or Makefile) with the following:

PROJECT		= blinky

include hdlmake.mk/hdlmake.mk

This assumes that your top-level module is called "blinky". You can then put your test-bench HDL in "blinky_tb.v", and your HDL in "blinky.v".

Running "make tb" will run the "blinky_tb" test-bench, and you can view the resulting waveforms using "make vcd"; or just run "make vcd" directly, it will run the test-bench if it hasn't been run.

General Configuration

The following variable must be set by the user:

User configurable variables

Simulation

Verilator (verilator)

User configurable variables:

Available targets:

Simulators for test benches

Supported simulators:

Additional required tools:

User configurable variables:

Available targets:

GHDL

User configurable flags:

Icarus Verilog (icarus)

User configurable flags:

CVC (cvc)

User configurable flags:

GPL Cver (cver)

User configurable flags:

Formal Verification

Supported formal verification tools

Available targets:

SymbiYosys (symbiyosys)

User configurable flags:

Vendors

Supported vendor types:

User configurable variables:

Available targets:

Xilinx ISE (xilinx-ise)

This assumes that Xilinx ISE is properly setup (i.e., settings64.sh or settings32.sh has been sourced), and that the XILINX variable is pointing to its installation directory.

The following variable must be set by the user:

User configurable flags:

Available targets:

Xilinx Vivado (xilinx-vivado)

This assumes that Xilinx Vivado is properly setup (i.e., settings64.sh or settings32.sh has been sourced), and that the XILINX variable is pointing to its installation directory.

The following variable must be set by the user:

User configurable flags:

Altera / Intel Quartus (altera-quartus)

The following variable must be set by the user:

User configurable flags

Available targets:

No Vendor (no-vendor)

FPGA Programming Tools

Supported programmer types:

The variable BITFILE must be set, either by a "vendor" or explicitly by the user.

Available targets:

fpgaprog

User configurable variables:

quartus_pgm

User configurable variables:

impact

User configurable variables:

djtgcfg

User configurable variables:

xc3sprog

User configurable variables:

Conventions for Simulation, Test Benches and Formal Verification

When writing test benches or other simulations, use the SIMULATION macro to toggle the debugging output or checks when run in a simulator. For formal verification properties use the FORMAL macro to guard the statements.

Each module that contains specific simulation statements should also contain a local variable debug' that can be used to toggle additional output (e.g. by settingDUT.debug = 1' in a top-level test bench). Additional variables can be used to allow tracing for specific paths in a module .

All $display/$monitor statements should be of the following format:

	$display("%t: %m: MESSAGE", $time, ARGUMENTS);

When writing or reading from inputs or outputs respectively, try to use the following format, this can be easily parsed by other tools later on:

	$display("%t: %m: W @%o <- %o", $time, address, d);
	$display("%t: %m: R @%o -> %o", $time, address, q);

Glossary / Naming Conventions