uhdl

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Key: Active Review Fixed Tested Deferred Closed
# mtime type status subsystem title
1da93e680d 2021-03-04 07:53:02 Code_Defect Open   vga test benches fail
3a9c840dcb 2021-03-04 07:50:21 Code_Defect Open   Make sure existing test benches work
46a10d1b6c 2021-03-04 07:49:26 Documentation Open   porting UHDL to a different FPGA/board
4ada3a5616 2021-03-04 07:49:03 Documentation Open   block device interface specification
53c1cc9fc2 2021-03-04 07:48:30 Documentation Open   specification of the spy port's serial transport
58b727e5d5 2021-03-04 07:48:48 Documentation Open   guide on using the spy port
5dfda27b82 2021-02-23 10:18:24 Code_Defect Open   Add Chaos support
655cc07868 2021-03-04 07:46:59 Documentation Open   Low level microcode debugging
7caf76eba9 2021-03-04 08:31:22 Code_Defect Open   PS/2 mouse does not work
7ee4eb0dae 2021-03-04 07:47:25 Documentation Open   HDL Xbus specification
a826011f2d 2020-11-02 06:33:26 Feature_Request Open   Arty A7 port
b1704394ad 2021-02-23 10:05:59 Code_Defect Open   Missing wires when synthesizing for Pipistrello
bebccd54ea 2021-03-10 10:27:47 Code_Defect Closed   Create a "gold" tar-ball
bf929185b6 2021-03-10 10:28:57 Code_Defect Closed   cc (C version) towards board doesn't work
d0b2a44e5e 2021-03-04 07:48:13 Documentation Open   HDL Unibus specification
e76f977cb0 2021-03-10 10:30:33 Documentation Closed   Detailed instructions for building uhdl
f82115f6e3 2021-03-04 07:52:21 Code_Defect Open   MiSTer sys/ directory is gone
09e3a3f55a 2023-04-04 06:53:55 Feature_Request Open   Design a new Lisp Machine keyboard suitable with today's standards