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50 most recent check-ins
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2023-11-19
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| 23:42 | m system compiles, ordering instruction system Leaf check-in: 416d11af05 user: aestay tags: aestay/trunk | |
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2023-11-06
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| 02:41 | cadr_cpu_types is now working. Can be used on the rewrite of the rest of the units check-in: 3bdd6744bf user: aestay tags: aestay/trunk | |
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2023-11-05
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| 03:43 | unit-per-unit refactor, WIP. Contact alejandro dot estay at gmail dot com check-in: 19ccdcf169 user: aestay tags: aestay/trunk | |
| 00:49 | hi I'm back, I think I've lost your email. check-in: fbcea22398 user: aestay tags: aestay/trunk | |
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2023-06-21
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| 19:12 | Revert non-working changes. Leaf check-in: 6e49028dcc user: ams tags: trunk | |
| 19:02 | Create new branch named "aestay/trunk" check-in: 2ec22717cd user: ams tags: aestay/trunk | |
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2023-06-12
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| 16:39 | CADR4-notes.text: Update. check-in: d8ce51ed6a user: ams tags: trunk | |
| 16:18 | CADR4-notes.text: Update annotations. check-in: 5a5c39eba1 user: ams tags: trunk | |
| 16:09 | CADR4-notes.text: Annotate some. check-in: bed4c43d0a user: ams tags: trunk | |
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2023-02-12
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| 23:39 | new module layout, created types for every instruction format, fields and possibilities, converting expressions and decisions to new types. check-in: 1087ff9705 user: aestay tags: trunk | |
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2023-02-04
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| 23:19 | created inspection package for led/switch panel and debug. Machine still has startup issues check-in: 9b1f968aed user: aestay tags: trunk | |
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2022-12-22
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| 00:37 | flattened and upgraded to SystemVerilog. BRAM IP's scrapped. Fixed some MIG7 DRC warnings and Verilog Warnings. check-in: 9ed48090b7 user: aestay tags: trunk | |
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2022-12-11
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| 17:56 | Create new branch named "pipistrello" Leaf check-in: a0f12f2428 user: aestay tags: aestay/pipistrello | |
| 04:05 | fixed DRC violations, configured DDR3 controller IP, timing is still off though check-in: 4879fb0047 user: aestay tags: trunk | |
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2022-05-23
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| 11:40 | Reorganize to match Knight paper. check-in: 3eab5c4ca0 user: ams tags: trunk | |
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2022-05-21
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| 15:59 | boards/arty_a7/AXI4_specification.pdf: Add file. check-in: a442a90eed user: ams tags: trunk | |
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2022-04-23
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| 15:52 | CADR4-notes.text: Add file. check-in: 87d0368d0f user: ams tags: trunk | |
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2021-08-06
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| 19:17 | TODO: Update. check-in: 72e44ee0e0 user: ams tags: trunk | |
| 18:39 | TODO: Update. check-in: 5a7eaeb990 user: ams tags: trunk | |
| 18:30 | TODO: Update. check-in: 6c5938f96d user: ams tags: trunk | |
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2021-08-01
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| 20:35 | template.v: Update. Leaf check-in: bc0b4e6451 user: ams tags: ams/arty-a7 | |
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2021-07-30
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| 16:44 | uhdl_arty_a7.v: Show RC state on the second seven segments displays decimal point. check-in: 951befa978 user: ams tags: ams/arty-a7 | |
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2021-06-19
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| 20:15 | uhdl_arty_a7.v: Display PROMDISABLE line on 8-digit display. check-in: da8f4a9b8b user: ams tags: ams/arty-a7 | |
| 19:47 | uhdl_arty_a7.v: Display some extra information on the decimal point. check-in: 8958bc92fe user: ams tags: ams/arty-a7 | |
| 19:46 | ram_controller_X7.v: Fix up. check-in: 9dd122cf48 user: ams tags: ams/arty-a7 | |
| 17:56 | boards/arty_a7/cores/xilinx/sysclk_wiz: Update; added 16MHz clock for M7219. check-in: 67d4fb6725 user: ams tags: ams/arty-a7 | |
| 17:53 | boards/arty_a7.mk, boards/arty_a7.xdc, led_controller.v, ram_controller_X7.v, ram_controller_X7_tb.v, uhdl_arty_a7.v: Fix up indentation; add MAX7219 module. check-in: 7539dea1bd user: ams tags: ams/arty-a7 | |
| 15:40 | .fossil-settings/ignore-glob: Update. check-in: 03f868a41f user: ams tags: ams/arty-a7 | |
| 15:39 | cores/counter.v, cores/spi_master.v, cores/max7219.v: Add files; snarfed from https://cerkit.com/2019/09/15/driving-the-max7219-7-segment-display-device-from-a-tinyfpga-using-verilog/ . check-in: 313d2ef2bb user: ams tags: ams/arty-a7 | |
| 15:36 | mouse.v: Move assignments to after the variables are declared to squeelch warning. check-in: e6fe3d7cd4 user: ams tags: ams/arty-a7 | |
| 15:35 | busint.v: Pass missing reset signals. check-in: d61bfeaad8 user: ams tags: ams/arty-a7 | |
| 15:34 | block_dev_mmc.v: Just use @* in the senstivity list. check-in: 6aff30ca68 user: ams tags: ams/arty-a7 | |
| 15:28 | GNUmakefile (SYN_SRCS_V): Remove variable; cadr.vh is included in cadr.mk. check-in: 8fdce0ab5c user: ams tags: ams/arty-a7 | |
| 07:52 | boards/arty_a7.mk: Set TARGET_BOARD, and correct TARGET accordingly. check-in: 82191d990b user: ams tags: ams/arty-a7 | |
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2021-06-17
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| 07:13 | CADR4.wires: Sort wire names. check-in: f82750264d user: ams tags: ams/arty-a7 | |
| 06:49 | CADR4.TODO: Move CADR4 related stuff here; new file. check-in: cd5d31fb49 user: ams tags: ams/arty-a7 | |
| 06:42 | Remove duplicate RC for Arty A7 / 7-series. check-in: 0968512e64 user: ams tags: ams/arty-a7 | |
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2021-06-15
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| 16:42 | Merge changes from trunk. check-in: f9d933c6a7 user: ams tags: ams/arty-a7 | |
| 10:48 | Merge changes from nusgart/arty-a7. check-in: 5ec5ef7e7e user: ams tags: ams/arty-a7 | |
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2021-06-05
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| 14:33 | boards/arty_a7/MAX7219-MAX7221.pdf: Add document. check-in: 1207de09ac user: ams tags: trunk | |
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2021-06-03
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| 18:59 | GNUmakefile: Add a few lazy targets for using CC. check-in: 31cd59efdb user: ams tags: trunk | |
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2021-06-02
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| 13:18 | CADR4.lisp (cadr4-graphviz-dump): Add function. check-in: b39f1533b8 user: ams tags: trunk | |
| 12:39 | CADR4.lisp: Add a DEFVAR. check-in: df2fe1c3a8 user: ams tags: trunk | |
| 12:36 | CADR4.lisp: Sexpy version of the wire list. check-in: c2bbf46d81 user: ams tags: trunk | |
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2021-05-27
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| 08:38 | ram_controller_pipistrello.v: Minor organization. check-in: 96f77c979f user: ams tags: ams/arty-a7 | |
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2021-05-25
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| 20:29 | ram_controller_pipistrello_tb.v: Fix up to use lpddr model, and Pipistrello RC. This doesn't run through simulation yet: Debug: At time 995.001 ns ram_controller_pipistrello_tb.u_mem3.Control_Logic:LMR : Load Mode Register ram_controller_pipistrello_tb.u_mem3.Control_Logic: At time 995.001 ns ERROR: all banks must be Precharged before Load Mode Register ram_controller_pipistrello_tb.u_mem3.Control_Logic: At time 995.001 ns ERROR: tMRD violation during Load Mode Register check-in: c616639e5e user: ams tags: ams/arty-a7 | |
| 19:49 | ram_controller_pipistrello_tb.v: New file; based of ram_controller_tb.v. check-in: e91f2c11a6 user: ams tags: ams/arty-a7 | |
| 16:06 | boards/arty_a7.mk: Add RC test bench. check-in: e668fec6c0 user: ams tags: ams/arty-a7 | |
| 15:55 | GNUmakefile: hdlmake.mk now does the right thing. check-in: b83e738537 user: ams tags: ams/arty-a7 | |
| 15:48 | GNUmakefile: Update documentation. check-in: ff39054d0e user: ams tags: ams/arty-a7 | |