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162 check-ins using file spy_port.v version c603b574d8
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2023-11-19
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| 23:42 | m system compiles, ordering instruction system Leaf check-in: 416d11af05 user: aestay tags: aestay/trunk | |
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2023-11-06
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| 02:41 | cadr_cpu_types is now working. Can be used on the rewrite of the rest of the units check-in: 3bdd6744bf user: aestay tags: aestay/trunk | |
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2023-11-05
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| 03:43 | unit-per-unit refactor, WIP. Contact alejandro dot estay at gmail dot com check-in: 19ccdcf169 user: aestay tags: aestay/trunk | |
| 00:49 | hi I'm back, I think I've lost your email. check-in: fbcea22398 user: aestay tags: aestay/trunk | |
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2023-06-21
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| 19:12 | Revert non-working changes. Leaf check-in: 6e49028dcc user: ams tags: trunk | |
| 19:02 | Create new branch named "aestay/trunk" check-in: 2ec22717cd user: ams tags: aestay/trunk | |
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2023-06-12
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| 16:39 | CADR4-notes.text: Update. check-in: d8ce51ed6a user: ams tags: trunk | |
| 16:18 | CADR4-notes.text: Update annotations. check-in: 5a5c39eba1 user: ams tags: trunk | |
| 16:09 | CADR4-notes.text: Annotate some. check-in: bed4c43d0a user: ams tags: trunk | |
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2023-02-12
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| 23:39 | new module layout, created types for every instruction format, fields and possibilities, converting expressions and decisions to new types. check-in: 1087ff9705 user: aestay tags: trunk | |
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2023-02-04
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| 23:19 | created inspection package for led/switch panel and debug. Machine still has startup issues check-in: 9b1f968aed user: aestay tags: trunk | |
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2022-12-22
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| 00:37 | flattened and upgraded to SystemVerilog. BRAM IP's scrapped. Fixed some MIG7 DRC warnings and Verilog Warnings. check-in: 9ed48090b7 user: aestay tags: trunk | |
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2022-12-11
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| 17:56 | Create new branch named "pipistrello" Leaf check-in: a0f12f2428 user: aestay tags: aestay/pipistrello | |
| 04:05 | fixed DRC violations, configured DDR3 controller IP, timing is still off though check-in: 4879fb0047 user: aestay tags: trunk | |
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2022-05-23
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| 11:40 | Reorganize to match Knight paper. check-in: 3eab5c4ca0 user: ams tags: trunk | |
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2022-05-21
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| 15:59 | boards/arty_a7/AXI4_specification.pdf: Add file. check-in: a442a90eed user: ams tags: trunk | |
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2022-04-23
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| 15:52 | CADR4-notes.text: Add file. check-in: 87d0368d0f user: ams tags: trunk | |
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2021-08-06
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| 19:17 | TODO: Update. check-in: 72e44ee0e0 user: ams tags: trunk | |
| 18:39 | TODO: Update. check-in: 5a7eaeb990 user: ams tags: trunk | |
| 18:30 | TODO: Update. check-in: 6c5938f96d user: ams tags: trunk | |
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2021-08-01
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| 20:35 | template.v: Update. Leaf check-in: bc0b4e6451 user: ams tags: ams/arty-a7 | |
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2021-07-30
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| 16:44 | uhdl_arty_a7.v: Show RC state on the second seven segments displays decimal point. check-in: 951befa978 user: ams tags: ams/arty-a7 | |
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2021-06-19
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| 20:15 | uhdl_arty_a7.v: Display PROMDISABLE line on 8-digit display. check-in: da8f4a9b8b user: ams tags: ams/arty-a7 | |
| 19:47 | uhdl_arty_a7.v: Display some extra information on the decimal point. check-in: 8958bc92fe user: ams tags: ams/arty-a7 | |
| 19:46 | ram_controller_X7.v: Fix up. check-in: 9dd122cf48 user: ams tags: ams/arty-a7 | |
| 17:56 | boards/arty_a7/cores/xilinx/sysclk_wiz: Update; added 16MHz clock for M7219. check-in: 67d4fb6725 user: ams tags: ams/arty-a7 | |
| 17:53 | boards/arty_a7.mk, boards/arty_a7.xdc, led_controller.v, ram_controller_X7.v, ram_controller_X7_tb.v, uhdl_arty_a7.v: Fix up indentation; add MAX7219 module. check-in: 7539dea1bd user: ams tags: ams/arty-a7 | |
| 15:40 | .fossil-settings/ignore-glob: Update. check-in: 03f868a41f user: ams tags: ams/arty-a7 | |
| 15:39 | cores/counter.v, cores/spi_master.v, cores/max7219.v: Add files; snarfed from https://cerkit.com/2019/09/15/driving-the-max7219-7-segment-display-device-from-a-tinyfpga-using-verilog/ . check-in: 313d2ef2bb user: ams tags: ams/arty-a7 | |
| 15:36 | mouse.v: Move assignments to after the variables are declared to squeelch warning. check-in: e6fe3d7cd4 user: ams tags: ams/arty-a7 | |
| 15:35 | busint.v: Pass missing reset signals. check-in: d61bfeaad8 user: ams tags: ams/arty-a7 | |
| 15:34 | block_dev_mmc.v: Just use @* in the senstivity list. check-in: 6aff30ca68 user: ams tags: ams/arty-a7 | |
| 15:28 | GNUmakefile (SYN_SRCS_V): Remove variable; cadr.vh is included in cadr.mk. check-in: 8fdce0ab5c user: ams tags: ams/arty-a7 | |
| 07:52 | boards/arty_a7.mk: Set TARGET_BOARD, and correct TARGET accordingly. check-in: 82191d990b user: ams tags: ams/arty-a7 | |
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2021-06-17
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| 07:13 | CADR4.wires: Sort wire names. check-in: f82750264d user: ams tags: ams/arty-a7 | |
| 06:49 | CADR4.TODO: Move CADR4 related stuff here; new file. check-in: cd5d31fb49 user: ams tags: ams/arty-a7 | |
| 06:42 | Remove duplicate RC for Arty A7 / 7-series. check-in: 0968512e64 user: ams tags: ams/arty-a7 | |
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2021-06-15
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| 16:42 | Merge changes from trunk. check-in: f9d933c6a7 user: ams tags: ams/arty-a7 | |
| 10:48 | Merge changes from nusgart/arty-a7. check-in: 5ec5ef7e7e user: ams tags: ams/arty-a7 | |
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2021-06-05
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| 14:33 | boards/arty_a7/MAX7219-MAX7221.pdf: Add document. check-in: 1207de09ac user: ams tags: trunk | |
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2021-06-03
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| 18:59 | GNUmakefile: Add a few lazy targets for using CC. check-in: 31cd59efdb user: ams tags: trunk | |
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2021-06-02
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| 13:18 | CADR4.lisp (cadr4-graphviz-dump): Add function. check-in: b39f1533b8 user: ams tags: trunk | |
| 12:39 | CADR4.lisp: Add a DEFVAR. check-in: df2fe1c3a8 user: ams tags: trunk | |
| 12:36 | CADR4.lisp: Sexpy version of the wire list. check-in: c2bbf46d81 user: ams tags: trunk | |
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2021-05-27
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| 08:38 | ram_controller_pipistrello.v: Minor organization. check-in: 96f77c979f user: ams tags: ams/arty-a7 | |
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2021-05-25
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| 20:29 | ram_controller_pipistrello_tb.v: Fix up to use lpddr model, and Pipistrello RC. This doesn't run through simulation yet: Debug: At time 995.001 ns ram_controller_pipistrello_tb.u_mem3.Control_Logic:LMR : Load Mode Register ram_controller_pipistrello_tb.u_mem3.Control_Logic: At time 995.001 ns ERROR: all banks must be Precharged before Load Mode Register ram_controller_pipistrello_tb.u_mem3.Control_Logic: At time 995.001 ns ERROR: tMRD violation during Load Mode Register check-in: c616639e5e user: ams tags: ams/arty-a7 | |
| 19:49 | ram_controller_pipistrello_tb.v: New file; based of ram_controller_tb.v. check-in: e91f2c11a6 user: ams tags: ams/arty-a7 | |
| 16:06 | boards/arty_a7.mk: Add RC test bench. check-in: e668fec6c0 user: ams tags: ams/arty-a7 | |
| 15:55 | GNUmakefile: hdlmake.mk now does the right thing. check-in: b83e738537 user: ams tags: ams/arty-a7 | |
| 15:48 | GNUmakefile: Update documentation. check-in: ff39054d0e user: ams tags: ams/arty-a7 | |
| 15:45 | Try to put cadr.vh first when reading in all files. check-in: 504e7ea61c user: ams tags: ams/arty-a7 | |
| 15:31 | boards/arty_a7.mk: Remove unused cores. check-in: 21976420c3 user: ams tags: ams/arty-a7 | |
| 15:25 | Check point: Board boots; still same issue as before. This mainly moves the PMOD connectors around. check-in: de0be3bcde user: ams tags: ams/arty-a7 | |
| 15:07 | boards/arty_a7.xdc: Update. check-in: 519d3009fe user: ams tags: ams/arty-a7 | |
| 09:11 | build_id.vh: Delete file. check-in: b44964609f user: ams tags: ams/arty-a7 | |
| 08:42 | spy_port_tb.v: Update AUTO* expansions. check-in: b7cc746593 user: ams tags: ams/arty-a7 | |
| 08:41 | GNUmakefile: Revert Git specfic bits to match trunk. check-in: 5c85fbe01c user: ams tags: ams/arty-a7 | |
| 08:28 | Fix location of XDC file. check-in: 368cf54a63 user: ams tags: ams/arty-a7 | |
| 08:26 | Fix previous commit; moved to wrong directory. check-in: 008863ac4f user: ams tags: ams/arty-a7 | |
| 08:18 | Move Arty A7 cores to shared location so it can bed used with hdlmake.mk. check-in: 21007b2dda user: ams tags: ams/arty-a7 | |
| 08:04 | Move XDC file to boards/. check-in: 615fda43c9 user: ams tags: ams/arty-a7 | |
| 08:00 | boards/arty_a7.xdc: Update to match Nusgarts's XDC. check-in: d6538ad27c user: ams tags: ams/arty-a7 | |
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2021-05-23
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| 21:18 | Disable core containers; update project files; regenerate cores. check-in: 6092377a97 user: ams tags: ams/arty-a7 | |
| 21:17 | .fossil-settings/ignore-glob: Ignore more Vivado files. check-in: 8778d23525 user: ams tags: ams/arty-a7 | |
| 21:15 | .fossil-settings/ignore-glob: Ignore some ISE stuff. check-in: ecee99c711 user: ams tags: ams/arty-a7 | |
| 21:14 | cores/rom.v: Move parameter definitions. check-in: 8db43567d2 user: ams tags: ams/arty-a7 | |
| 21:12 | uhdl_pipistrello_tb.v: Small fixes to match wire size, and add missing wires. check-in: f14e6d384f user: ams tags: ams/arty-a7 | |
| 19:32 | cadr.hw/cadr.lpr: Remove ignored file. check-in: a9944603e2 user: ams tags: ams/arty-a7 | |
| 19:31 | .fossil-settings/ignore-glob: Ignore more Vivado stuff. check-in: 176810992e user: ams tags: ams/arty-a7 | |
| 19:30 | .fossil-settings/ignore-glob: Update file; also remove ignored files. check-in: f285984ad3 user: ams tags: ams/arty-a7 | |
| 19:25 | .fossil-settings/ignore-glob: Add file. check-in: fe86636583 user: ams tags: ams/arty-a7 | |
| 17:56 | Vivado decided to do something to the clock wizard. Leaf check-in: bd79d095ae user: nusgart tags: nusgart/arty-a7 | |
| 17:37 | cadr.vh, uhdl_pipistrello.xise: Update. check-in: fb43b590f5 user: ams tags: trunk | |
| 10:19 | Update Pipistrello project file; and see that cadr.vh is correctly read by ISE. check-in: 830a8dba97 user: ams tags: ams/arty-a7 | |
| 10:18 | Check point: System boots and loads microcode; gets stuck in FINDCORE1. check-in: 7b7a7c2a8b user: ams tags: ams/arty-a7 | |
| 10:16 | Check point: Board boots, CC works (115200 baud). check-in: 61e822b1cb user: ams tags: ams/arty-a7 | |
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2021-05-22
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| 02:32 | Minor fixes and tweaks check-in: f92926c5cf user: nusgart tags: nusgart/arty-a7 | |
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2021-05-21
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| 22:35 | Fix VGA horizontal counter overflow The problem was that the horizontal counter was eleven bits but a 1080p line is 2200 pixels wide, so the horizontal counter overflowed. Both the horizontal and vertical counters are thirteen bits now, which should allow resolutions up to 8192x8192, which is probably more than VGA can reasonably support. check-in: ce803b7e1b user: nusgart tags: nusgart/arty-a7 | |
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2021-05-18
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| 22:01 | Vivado generated IP changes check-in: 3a4d27f6f7 user: nusgart tags: nusgart/arty-a7 | |
| 21:59 | Get rid of the non-functional Artix-7 copy of the Spartan 6 MIG IP. This change does _not_ affect anything in the Pipistrello tree. check-in: 946f5a366e user: nusgart tags: nusgart/arty-a7 | |
| 21:55 | Update README with specific information about the Arty A7 port check-in: 138712990f user: nusgart tags: nusgart/arty-a7 | |
| 21:54 | Fix VGA display check-in: 00691c73dc user: nusgart tags: nusgart/arty-a7 | |
| 19:59 | Rename the A7 ram controller to "ram_controller_X7" This better describes what hardware it will work on (it should work on any Xilinx 7-series FPGA using DDR3 SDRAM). check-in: 2da1b574d8 user: nusgart tags: nusgart/arty-a7 | |
| 14:58 | CADR4: Clean up static RAM code; to keep simulation working. check-in: a176742e39 user: ams tags: trunk | |
| 14:28 | cores/ram.v: Fix typos. check-in: d6e1190ad2 user: ams tags: trunk | |
| 09:21 | README.md: Update. check-in: 027a850a87 user: ams tags: trunk | |
| 09:08 | cadr.mk: Add dpram.v and ram.v. check-in: efdd5ac951 user: ams tags: trunk | |
| 09:01 | ram.v: Add file. check-in: 0da70b8cbe user: ams tags: trunk | |
| 09:01 | dpram.v: Add file. check-in: e23180cd85 user: ams tags: trunk | |
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2021-05-15
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| 22:50 | Set default board to Arty A7 and update gitignore check-in: 11c9c64347 user: nusgart tags: nusgart/arty-a7 | |
| 20:18 | block_dev_mmc.v: Typo fix; can't have block labels the same as parameters. check-in: f2bf2db1ec user: ams tags: trunk | |
| 20:03 | block_dev_mmc.v: Doc. fixes. check-in: 40a0f955fa user: ams tags: trunk | |
| 14:41 | block_dev_mmc.v: Typo. check-in: f108941cf0 user: ams tags: trunk | |
| 14:40 | block_dev_mmc.v: Add some basic documentation. check-in: 24a570c90b user: ams tags: trunk | |
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2021-05-14
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| 11:43 | CADR4/MDS.v: Slightly reorder code. check-in: c20772dd81 user: ams tags: trunk | |
| 11:40 | CADR4/MD.v: Whitespace fix. check-in: 1b2a2d036c user: ams tags: trunk | |
| 11:37 | cadr_tb.v: Add a simple test-bench. check-in: dc6fd336b0 user: ams tags: trunk | |
| 11:33 | CADR4/IRAML/IRAM.v: Initialize RAM to zero when simulating. check-in: ecb2317dcf user: ams tags: trunk | |
| 11:33 | CADR4/VMEM1.v: Initialize RAM to zero when simulating. check-in: aa4afaf569 user: ams tags: trunk | |
| 11:33 | CADR4/VMEM0.v: Initialize RAM to zero when simulating. check-in: 5deca4ddc8 user: ams tags: trunk | |
| 11:32 | CADR4/SPC.v: Initialize RAM to zero when simulating. check-in: a649343b72 user: ams tags: trunk | |
| 11:32 | CADR4/PDL.v: Initialize RAM to zero when simulating. check-in: 06254a148c user: ams tags: trunk | |
| 11:32 | CADR4/MMEM.v: Initialize RAM to zero when simulating. check-in: fdb366da50 user: ams tags: trunk | |
| 11:32 | CADR4/DRAM.v: Initialize RAM to zero when simulating. check-in: 13f68c7f96 user: ams tags: trunk | |
| 11:31 | CADR4/AMEM.v: Initialize RAM to zero when simulating. check-in: 55d1cd0c93 user: ams tags: trunk | |
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2021-05-13
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| 17:14 | spy_port_tb.v: Removed unused port. check-in: 9058c93ee1 user: ams tags: trunk | |
| 17:07 | busint_disk_tb.v: Correct module access for busint. check-in: 02dbe48c73 user: ams tags: trunk | |
| 10:19 | block_dev_mmc.v: Formatting. check-in: d81b94ca51 user: ams tags: trunk | |
| 09:51 | block_dev_mmc.v: Reorganize code to make more sense. check-in: 0d93b7275c user: ams tags: trunk | |
| 08:53 | block_dev_mmc.v: Clean up port list; start of documenting generic block interface. check-in: 4ef25b55ac user: ams tags: trunk | |
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2021-05-12
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| 15:17 | uhdl_pipistrello.v: Reduce cognitive effort to decode LEDs; also display if we are still in PROM. check-in: 530d55abf3 user: ams tags: trunk | |
| 13:31 | Merge changes from Nusgart. check-in: 2982d1d10d user: ams tags: trunk | |
| 12:39 | top_A7_routed.dcp -> uhdl_arty_a7_routed.dcp: Rename. check-in: faa4f11b3b user: ams tags: nusgart/arty-a7 | |
| 12:10 | cadr.xpr: Update project file with correct locations. check-in: 0a08957d1e user: ams tags: nusgart/arty-a7 | |
| 11:47 | mmc.v, mmc_model.v, mmc_tb.v, mmc_wrapper.v: Update from Tumbleweed. check-in: fb877f82e2 user: ams tags: nusgart/arty-a7 | |
| 11:46 | uhdl_arty_a7_tb.v: Update from Tumbleweed. check-in: bc5c2fa0e8 user: ams tags: nusgart/arty-a7 | |
| 11:46 | uhdl_common.v: Update from Tumbleweed. check-in: 65b843e1c1 user: ams tags: nusgart/arty-a7 | |
| 11:45 | vga_display.v: Update to Verilog-2001 declerations. check-in: e6175bfbea user: ams tags: nusgart/arty-a7 | |
| 11:43 | xbus_disk.v: Update from Tumbleweed. check-in: cf57db2776 user: ams tags: nusgart/arty-a7 | |
| 11:43 | xbus_io.v: Update from Tumbleweed. check-in: d8123a8c64 user: ams tags: nusgart/arty-a7 | |
| 11:43 | xbus_ram.v: Update from Tumbleweed. check-in: 7c1ba4ad83 user: ams tags: nusgart/arty-a7 | |
| 11:42 | xbus_spy.v: Update from Tumbleweed. check-in: 2b443fa88c user: ams tags: nusgart/arty-a7 | |
| 11:42 | xbus_unibus.v: Update from Tumbleweed. check-in: 78af81dfc1 user: ams tags: nusgart/arty-a7 | |
| 11:42 | xbus_tv.v: Update from Tumbleweed. check-in: 7b3aebf8f1 user: ams tags: nusgart/arty-a7 | |
| 11:34 | cores/ic_74181.v, cores/ic_74182.v: Update from Tumbleweed. check-in: 4aae169fb4 user: ams tags: nusgart/arty-a7 | |
| 11:34 | cores/hz60.v: Update from Tumbleweed. check-in: cc1bfd8bab user: ams tags: nusgart/arty-a7 | |
| 11:33 | cores/ps2.v, cores/ps2_send.v, cores/ps2_send_tb.v: Update from Tumbleweed. check-in: 43567565e0 user: ams tags: nusgart/arty-a7 | |
| 11:33 | cores/us.v: Update from Tumbleweed. check-in: f55be57a1d user: ams tags: nusgart/arty-a7 | |
| 11:33 | cores/rom.v: Update from Tumbleweed. check-in: cbb36613c9 user: ams tags: nusgart/arty-a7 | |
| 11:33 | cores/uart.v: Update from Tumbleweed. check-in: 4b025fba4b user: ams tags: nusgart/arty-a7 | |
| 11:31 | boards/pipistrello.mk: Update from Tumbleweed. check-in: 8ff638874e user: ams tags: nusgart/arty-a7 | |
| 11:31 | boards/arty_a7.mk, boards/arty_a7.xdc: Update from Tumbleweed. check-in: f8d7312437 user: ams tags: nusgart/arty-a7 | |
| 11:30 | uhdl.v: Update from Tumbleweed. check-in: d41c97df3b user: ams tags: nusgart/arty-a7 | |
| 11:29 | uhdl_sim.cpp: Update from Tumbleweed. check-in: 794f5382f6 user: ams tags: nusgart/arty-a7 | |
| 11:29 | uhdl_pipistrello.v, uhdl_pipistrello_tb.v: Restore files; and update from Tumbleweed. check-in: e50465d412 user: ams tags: nusgart/arty-a7 | |
| 11:28 | support_tb.v: Update from Tumbleweed. check-in: 01ef7f81c9 user: ams tags: nusgart/arty-a7 | |
| 11:28 | support_pipistrello.v: Update from Tumbleweed; verilog-2001. check-in: 70460e777c user: ams tags: nusgart/arty-a7 | |
| 11:28 | spy_port.v, spy_port_tb.v: Update from Tumbleweed. check-in: 3c85d22431 user: ams tags: nusgart/arty-a7 | |
| 10:15 | CADR4/DSPCTL.v: Move wire decleration. Closed-Leaf check-in: 1454b12bc1 user: ams tags: nusgart-merge | |
| 09:06 | uhdl.v: Fix module definitions. check-in: 510fdfe808 user: ams tags: nusgart-merge | |
| 09:03 | uhdl_arty_a7.v: Fix comments. check-in: c6a6cf2474 user: ams tags: nusgart-merge | |
| 08:56 | uhdl_pipistrello_tb.v: Fix wire access. check-in: 0454cba00e user: ams tags: nusgart-merge | |
| 07:29 | uhdl_sim.cpp: Update names. check-in: eb694f2aed user: ams tags: trunk | |
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2021-05-11
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| 21:33 | CADR4/VMAS.v: Fix typo. check-in: 0dc5b22d74 user: ams tags: nusgart-merge | |
| 21:20 | ram_controller_arty_a7_tb.v: Add file. check-in: 9ccc897866 user: ams tags: nusgart-merge | |
| 20:44 | uhdl_pipistrello.xise: Update. check-in: 0200e0f6f6 user: ams tags: nusgart-merge | |
| 20:44 | uhdl_pipistrello.xise: Fix typo. check-in: 04cc2182d9 user: ams tags: nusgart-merge | |
| 20:40 | boards/arty_a7.xdc, boards/arty_a7.mk: Update constraints and board configuration/ check-in: ab33ae4f43 user: ams tags: nusgart-merge | |
| 20:38 | uhdl_arty_a7_tb.v: Update file with changes from Nusgart. check-in: e2b6f46ebe user: ams tags: nusgart-merge | |
| 20:37 | support_arty_a7.v: Update file from Nusgart. check-in: d1076b7050 user: ams tags: nusgart-merge | |
| 20:35 | ram_controller_arty_a7.v: Update with changes from Nusgart; this was called memory_controller_A7. check-in: 7c1f69effc user: ams tags: nusgart-merge | |
| 20:34 | uhdl_arty_a7.v: Update with changes from Nusgart; removes aux. UART port, and old RAM controller. check-in: 07dc1f9421 user: ams tags: nusgart-merge | |
| 20:32 | led_controller.sv: Add file; from Nusgart. check-in: 322a2ac7a3 user: ams tags: nusgart-merge | |
| 20:27 | cores/uart.v: Restore clock frequence to 50MHz. check-in: 24befca3ec user: ams tags: trunk | |
| 19:34 | Merge changes from verilog-2001 branch. check-in: c8909e95f6 user: ams tags: trunk | |
| 19:06 | .fossil-settings/ignore-glob: Ignore files. Closed-Leaf check-in: 0de9bf19bc user: ams tags: verilog-2001 | |
| 18:50 | uhdl_pipistrello.v: Define ISE since Pipistrello uses ISE IP. check-in: e7bbda3493 user: ams tags: verilog-2001 | |
| 18:50 | uhdl_pipistrello.v: Update to 2001 declarations. check-in: 779edb3e77 user: ams tags: verilog-2001 | |
| 18:48 | uhdl_common.v: Update to 2001 style declarations. check-in: 0dc7cd0c17 user: ams tags: verilog-2001 | |
| 18:48 | GNUmakefile: Rename .version to build-id.vh so it is slightly more vissible by Vivado/ISE. check-in: f5a83e75e4 user: ams tags: verilog-2001 | |
| 18:45 | ps2_support.v: Fix typos. check-in: ad89d53a6f user: ams tags: verilog-2001 | |
| 18:31 | spy_port.v: Format code. check-in: c8f5a714ef user: ams tags: verilog-2001 | |