uhdl

The following wires are missing, seems verilog-mode isn't picking up that it needs to AUTOWIRE them?

top_lx45.v:
  wire [31:0] sdram_data_rc2cpu;
  wire [31:0] vram_cpu_data_in;
  wire [48:0] mcr_data_in;

cadr.v:
  wire [11:0] bd_state_in;

Double check that they are right (e.g., bd_state_in seems wrong).