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Changes In Branch nusgart/mister Excluding Merge-Ins
This is equivalent to a diff from b192304b48 to c7c59a1a1b
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2020-09-01
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| 03:43 | Implement DDRAM xbus state machine Leaf check-in: c7c59a1a1b user: nusgart tags: nusgart/mister | |
| 03:41 | Add CADR4 code check-in: 91605e5730 user: nusgart tags: nusgart/mister | |
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2020-08-30
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| 17:17 | Initial commit of CADR HDL. This isn't complete yet and will not work. In particular, the block storage device is unimplemented and the RAM controller probably violates the XBUS requirements. Additionally, I would like to take advantage of the large amount of block ram on the MiSTer by making a cache (probably ~64 KW in size). check-in: 1343a6af7b user: nusgart tags: nusgart/mister | |
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2020-03-29
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| 16:22 | README -> TODO: Rename file. check-in: cfb70b4280 user: ams tags: trunk | |
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2019-05-30
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| 23:36 | Initial conversion to Vivado and Artix-7 check-in: aa4c56ce19 user: nusgart tags: nusgart/arty-a7 | |
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2019-05-06
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| 18:59 | Merge ams/next. check-in: b192304b48 user: ams tags: trunk | |
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2018-02-24
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| 12:31 | NIOX: Add submodule for NIOS-II clone core. check-in: 5b47a6e897 user: ams tags: trunk | |
Changes to CADR4/AMEM.v.
Changes to CADR4/DRAM.v.
Changes to CADR4/IRAML/IRAM.v.
Changes to CADR4/MD.v.
Changes to CADR4/MMEM.v.
Changes to CADR4/PDL.v.
Changes to CADR4/SPC.v.
Changes to CADR4/VMEM0.v.
Changes to CADR4/VMEM1.v.
Added block_dev_mister.sv.
Changes to block_dev_mmc.v.
Changes to busint.v.
Changes to cadr.v.
Changes to cadr.vh.
Added cadr_core.sv.
Added clkwiz.v.
Added clkwiz_bb.v.
Added cores/alt_vram.qip.
Added cores/alt_vram.v.
Added cores/alt_vram_bb.v.
Added cos.sv.
Added lfsr.v.
Changes to lm3.v.
Added pll.qip.
Added pll.v.
Added pll/pll_0002.qip.
Added pll/pll_0002.v.
Added pll17.qip.
Added ram_controller_cyc2.v.
Added ram_controller_mister.sv.
Added ram_controller_mister.v.
Added support_cyc2.v.
Added support_mister.v.
Added top_cyc2.sv.
Added ucadr-mcr-841.bin.
Added ucadr-mcr-841.hex.
Changes to vga_display.v.
Changes to xbus_io.v.