Statistics: 32 inputs; 32 outputs; 2406 gates; bus translations

Function: The c6288 benchmark, whose multiplication function was previously known, represents a much larger gate-level circuit that also has a concise functional description. The figure above shows how the 2406 gates form 240 full and half adder cells arranged in a 15x16 matrix. An alternate representation is shown here, and the adder cells are detailed here.

• c6288 ISCAS-85 netlist
• c6288 Verilog hierarchical structural model
• c6288 Verilog hierarchical behavioral model
• c6288 complete gate-level tests