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| Comment: | Import copy of http://web.eecs.umich.edu/~jhayes/iscas.restore/. |
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| User & Date: | ams 2021-04-05 12:11:10 |
Context
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2021-04-05
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| 15:04 | Add FOSSIL-DOC class to all HTML files, and remove boiler plate. check-in: 8cc0186569 user: ams tags: trunk | |
| 12:11 | Import copy of http://web.eecs.umich.edu/~jhayes/iscas.restore/. check-in: 33fa7fc42d user: ams tags: trunk | |
| 12:10 | initial empty check-in check-in: d7a77a0abb user: ams tags: trunk | |
Changes
Added 74181.gif.
cannot compute difference between binary files
Added 74181.html.
> > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>74181</TITLE> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080"> <B><FONT SIZE=5><P ALIGN="CENTER">74181 4-Bit ALU/Function Generator</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="74181.gif" WIDTH=592 HEIGHT=349></P> <B><P>Statistics: </B>14 inputs; 8 outputs; 61 gates; <A HREF="74181gates.html">gate-level schematic</A></P> <B><P ALIGN="JUSTIFY">Function: </B>The 74181 can be modeled as above. <FONT FACE="Times">Recognizing the logic that makes up a CLA block—in this case, the circled elements in the </FONT><A HREF="74181gates.html">gate-level schematic</A><FONT FACE="Times">—is the key step in unraveling the secrets of the 74181. The four boxed circuits in the </FONT><A HREF="74181gates.html">gate-level schematic</A> <FONT FACE="Times">are represented above by the single module </FONT><A HREF="74181m1.html">M1</A><FONT FACE="Times"> with 4-bit I/O buses. The second quadruplicated circuit in the 74181 leads to the high-level module </FONT><A HREF="74181m2.html">M2</A><FONT FACE="Times">. The various XOR gates are also grouped into 4-bit word gates as indicated above. Further analysis shows that the 74181’s original designers cleverly constructed the M<SUB>1</SUB> and M<SUB>2 </SUB>logic so that with input line <I>M</I> = 1, each setting of the <I>S</I> (function select) bus produces one of the 16 possible Boolean functions of the form <I>F</I>(<I>A,B</I>). </P> </FONT><B><P ALIGN="JUSTIFY">Note:</B><FONT FACE="Times"> The M line above has been logically moved from within the CLA block M3, to after the block. This was done to make module M3 a standard CLA block. The change preserves the function, but does make subtle differences when analyzing, for example, path delays in the two circuits.</P> </FONT><B><P>Models:</P> <UL> <LI></B><A HREF="74181.isc">74181 ISCAS-85 netlist</A><B> </LI> </B><LI><A HREF="74181.v">74181 Verilog structural model</A><B> </LI> </B><LI><A HREF="74181b.v">74181 behavioral model</A> </LI> <LI><A HREF="74181.tests">74181 complete gate-level tests</A></LI></UL> <FONT SIZE=2><P> </P></FONT></BODY> </HTML> |
Added 74181.isc.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 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18fan from 7gat >sa0 >sa1 19 19fan from 7gat >sa0 >sa1 20 20fan from 7gat >sa0 >sa1 21 21fan from 9gat >sa0 >sa1 22 22fan from 9gat >sa0 >sa1 23 23fan from 9gat >sa0 >sa1 24 24fan from 11gat >sa0 >sa1 25 25fan from 11gat >sa0 >sa1 26 26fan from 11gat >sa0 >sa1 27 27gat not 10 1 >sa0 >sa1 13 28 28gat not 2 1 >sa0 >sa1 16 29 29gat not 2 1 >sa0 >sa1 19 30 30gat not 2 1 >sa0 >sa1 22 31 31gat not 2 1 >sa0 >sa1 25 32 32fan from 3gat >sa0 >sa1 33 33fan from 3gat >sa0 >sa1 34 34fan from 3gat >sa0 >sa1 35 35fan from 3gat >sa0 >sa1 36 36fan from 4gat >sa0 >sa1 37 37fan from 4gat >sa0 >sa1 38 38fan from 4gat >sa0 >sa1 39 39fan from 4gat >sa0 >sa1 40 40fan from 6gat >sa0 >sa1 41 41fan from 6gat >sa0 >sa1 42 42fan from 6gat >sa0 >sa1 43 43fan from 29gat >sa0 >sa1 44 44fan from 29gat >sa0 >sa1 45 45fan from 8gat >sa0 >sa1 46 46fan from 8gat >sa0 >sa1 47 47fan from 8gat >sa0 >sa1 48 48fan from 28gat >sa0 >sa1 49 49fan from 28gat >sa0 >sa1 50 50fan from 1gat >sa0 >sa1 51 51fan from 1gat >sa0 >sa1 52 52fan from 1gat >sa0 >sa1 53 53fan from 1gat >sa0 >sa1 54 54fan from 2gat >sa0 >sa1 55 55fan from 2gat >sa0 >sa1 56 56fan from 2gat >sa0 >sa1 57 57fan from 2gat >sa0 >sa1 58 58fan from 10gat >sa0 >sa1 59 59fan from 10gat >sa0 >sa1 60 60fan from 10gat >sa0 >sa1 61 61fan from 31gat >sa0 >sa1 62 62fan from 31gat >sa0 >sa1 63 63fan from 12gat >sa0 >sa1 64 64fan from 12gat >sa0 >sa1 65 65fan from 12gat >sa0 >sa1 66 66fan from 30gat >sa0 >sa1 67 67fan from 30gat >sa0 >sa1 68 68gat and 1 3 >sa0 >sa1 15 36 40 69 69gat and 1 3 >sa0 >sa1 41 32 48 70 70gat and 1 2 >sa0 >sa1 49 54 71 71gat and 1 2 >sa0 >sa1 50 17 72 72gat buff 1 1 >sa0 >sa1 42 73 73gat and 1 3 >sa0 >sa1 18 37 45 74 74gat and 1 3 >sa0 >sa1 46 33 43 75 75gat and 1 2 >sa0 >sa1 44 55 76 76gat and 1 2 >sa0 >sa1 51 20 77 77gat buff 1 1 >sa0 >sa1 47 78 78gat and 1 3 >sa0 >sa1 21 38 58 79 79gat and 1 3 >sa0 >sa1 59 34 66 80 80gat and 1 2 >sa0 >sa1 67 56 81 81gat and 1 2 >sa0 >sa1 52 23 82 82gat buff 1 1 >sa0 >sa1 60 83 83gat and 1 3 >sa0 >sa1 24 39 63 84 84gat and 1 3 >sa0 >sa1 64 35 61 85 85gat and 1 2 >sa0 >sa1 62 57 86 86gat and 1 2 >sa0 >sa1 53 26 87 87gat buff 1 1 >sa0 >sa1 65 88 88gat nor 6 2 >sa0 >sa1 68 69 89 89gat nor 2 3 >sa0 >sa1 70 71 72 90 90gat nor 8 2 >sa0 >sa1 73 74 91 91gat nor 3 3 >sa0 >sa1 75 76 77 92 92gat nor 8 2 >sa0 >sa1 78 79 93 93gat nor 4 3 >sa0 >sa1 80 81 82 94 94gat nor 6 2 >sa0 >sa1 83 84 95 95gat nor 5 3 >sa0 >sa1 85 86 87 96 96fan from 88gat >sa0 97 97fan from 88gat >sa0 98 98fan from 88gat >sa0 99 99fan from 88gat >sa0 >sa1 100 100fan from 88gat >sa0 >sa1 101 101fan from 88gat >sa0 >sa1 102 102fan from 89gat >sa0 >sa1 103 103fan from 89gat >sa0 >sa1 104 104fan from 90gat >sa0 105 105fan from 90gat >sa0 106 106fan from 90gat >sa0 >sa1 107 107fan from 90gat >sa0 >sa1 108 108fan from 90gat >sa0 >sa1 109 109fan from 90gat >sa0 >sa1 110 110fan from 90gat >sa0 >sa1 111 111fan from 90gat >sa0 >sa1 112 112fan from 91gat >sa0 >sa1 113 113fan from 91gat >sa0 >sa1 114 114fan from 91gat >sa0 >sa1 115 115fan from 92gat >sa0 116 116fan from 92gat >sa0 >sa1 117 117fan from 92gat >sa0 >sa1 118 118fan from 92gat >sa0 >sa1 119 119fan from 92gat >sa0 >sa1 120 120fan from 92gat >sa0 >sa1 121 121fan from 92gat >sa0 >sa1 122 122fan from 92gat >sa0 >sa1 123 123fan from 93gat >sa0 >sa1 124 124fan from 93gat >sa0 >sa1 125 125fan from 93gat >sa0 >sa1 126 126fan from 93gat >sa0 >sa1 127 127fan from 94gat >sa0 >sa1 128 128fan from 94gat >sa0 >sa1 129 129fan from 94gat >sa0 >sa1 130 130fan from 94gat >sa0 >sa1 131 131fan from 94gat >sa0 >sa1 132 132fan from 94gat >sa0 >sa1 133 133fan from 95gat >sa0 >sa1 134 134fan from 95gat >sa0 >sa1 135 135fan from 95gat >sa0 >sa1 136 136fan from 95gat >sa0 >sa1 137 137fan from 95gat >sa0 >sa1 138 138fan from 27gat >sa0 >sa1 139 139fan from 27gat >sa0 >sa1 140 140fan from 27gat >sa0 >sa1 141 141fan from 27gat >sa0 >sa1 142 142fan from 27gat >sa0 >sa1 143 143fan from 27gat >sa0 >sa1 144 144fan from 27gat >sa0 >sa1 145 145fan from 27gat >sa0 >sa1 146 146fan from 27gat >sa0 >sa1 147 147fan from 27gat >sa0 >sa1 148 148fan from 14gat >sa0 >sa1 149 149fan from 14gat >sa0 >sa1 150 150fan from 14gat >sa0 >sa1 151 151fan from 14gat >sa0 >sa1 152 152fan from 14gat >sa0 >sa1 153 153gat buff 1 1 >sa0 >sa1 102 154 154gat and 1 2 >sa0 >sa1 96 112 155 155gat and 1 3 >sa0 >sa1 97 123 104 156 156gat and 1 4 >sa0 >sa1 98 105 115 133 157 157gat nand 1 5 >sa0 >sa1 99 106 116 127 148 158 158gat nand 1 4 >sa0 >sa1 100 107 117 128 159 159gat xor 1 2 >sa0 >sa1 101 103 160 160gat and 1 5 >sa0 >sa1 149 129 118 108 138 161 161gat and 1 4 >sa0 >sa1 119 109 134 139 162 162gat and 1 3 >sa1 110 124 140 163 163gat and 1 2 >sa0 >sa1 114 141 164 164gat xor 1 2 >sa0 >sa1 111 113 165 165gat and 1 4 >sa1 150 130 120 142 166 166gat and 1 3 >sa0 >sa1 121 135 143 167 167gat and 1 2 >sa1 125 144 168 168gat xor 1 2 >sa0 >sa1 122 126 169 169gat and 1 3 >sa0 >sa1 151 131 145 170 170gat and 1 2 >sa1 136 146 171 171gat xor 1 2 >sa0 >sa1 132 137 172 172gat nand 1 2 >sa0 >sa1 152 147 173 173gat nor 2 4 >sa0 >sa1 153 154 155 156 174 174fan from 173gat >sa0 >sa1 175 175fan from 173gat >sa0 >sa1 176 176gat not 1 1 >sa0 >sa1 175 177 177gat not 1 1 >sa0 >sa1 157 178 178gat nor 1 4 >sa0 >sa1 160 161 162 163 179 179gat nor 1 3 >sa0 >sa1 165 166 167 180 180gat nor 1 2 >sa0 >sa1 169 170 181 181gat or 1 2 >sa0 >sa1 176 177 182 182gat xor 2 2 >sa0 >sa1 159 178 183 183fan from 182gat >sa0 >sa1 184 184fan from 182gat >sa0 >sa1 185 185gat xor 2 2 >sa0 >sa1 164 179 186 186fan from 185gat >sa0 >sa1 187 187fan from 185gat >sa0 >sa1 188 188gat xor 2 2 >sa0 >sa1 168 180 189 189fan from 188gat >sa0 >sa1 190 190fan from 188gat >sa0 >sa1 191 191gat xor 2 2 >sa0 >sa1 171 172 192 192fan from 191gat >sa0 >sa1 193 193fan from 191gat >sa0 >sa1 194 194gat and 1 4 >sa0 >sa1 184 187 189 192 195 195gat xor 1 2 >sa0 >sa1 174 181 196 196gat xor 1 2 >sa0 >sa1 158 183 197 197gat xor 1 2 >sa0 >sa1 186 194 198 198gat xor 1 2 >sa0 >sa1 190 193 199 199gat xor 1 2 >sa0 >sa1 195 196 200 200gat xor 1 2 >sa0 >sa1 197 198 201 201gat xor 0 2 >sa0 >sa1 199 200 |
Added 74181.tests.
> > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 | 01010000111101 01011111111100 01010001111001 01010010110001 01011000000011 01010100100001 10100000000100 10101100001000 10100011010100 10101111111010 01010011000000 10100011101111 |
Added 74181.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 | /**************************************************************************** * * * VERILOG HIGH-LEVEL DESCRIPTION OF THE TI 74181 CIRCUIT * * * * Function: 4-bit ALU/Function Generator * * * * Written by: Mark C. Hansen * * * * Last modified: Dec 11, 1997 * * * ****************************************************************************/ module Circuit74181 (S, A, B, M, CNb, F, X, Y, CN4b, AEB); input [3:0] A, B, S; input CNb, M; output [3:0] F; output AEB, X, Y, CN4b; TopLevel74181 Ckt74181 (S, A, B, M, CNb, F, X, Y, CN4b, AEB); endmodule /* Circuit74181 */ /*************************************************************************/ module TopLevel74181 (S, A, B, M, CNb, F, X, Y, CN4b, AEB); input [3:0] A, B, S; input CNb, M; output [3:0] F; output AEB, X, Y, CN4b; wire [3:0] E, D, C, Bb; Emodule Emod1 (A, B, S, E, Bb); Dmodule Dmod2 (A, B, Bb, S, D); CLAmodule CLAmod3(E, D, CNb, C, X, Y, CN4b); Summodule Summod4(E, D, C, M, F, AEB); endmodule /* TopLevel74181 */ /*************************************************************************/ module Emodule (A, B, S, E, Bb); input [3:0] A, B, S; output [3:0] E, Bb; wire [3:0] ABS3, ABbS2; not Bb0gate(Bb[0], B[0]); not Bb1gate(Bb[1], B[1]); not Bb2gate(Bb[2], B[2]); not Bb3gate(Bb[3], B[3]); and ABS30gate(ABS3[0], A[0], B[0], S[3]); and ABS31gate(ABS3[1], A[1], B[1], S[3]); and ABS32gate(ABS3[2], A[2], B[2], S[3]); and ABS33gate(ABS3[3], A[3], B[3], S[3]); and ABbS20gate(ABbS2[0], A[0], Bb[0], S[2]); and ABbS21gate(ABbS2[1], A[1], Bb[1], S[2]); and ABbS22gate(ABbS2[2], A[2], Bb[2], S[2]); and ABbS23gate(ABbS2[3], A[3], Bb[3], S[2]); nor E0gate(E[0], ABS3[0], ABbS2[0]); nor E1gate(E[1], ABS3[1], ABbS2[1]); nor E2gate(E[2], ABS3[2], ABbS2[2]); nor E3gate(E[3], ABS3[3], ABbS2[3]); endmodule /* Emodule */ /*************************************************************************/ module Dmodule (A, B, Bb, S, D); input [3:0] A, B, Bb, S; output [3:0] D; wire [3:0] BbS1, BS0; and BbS10gate(BbS1[0], Bb[0], S[1]); and BbS11gate(BbS1[1], Bb[1], S[1]); and BbS12gate(BbS1[2], Bb[2], S[1]); and BbS13gate(BbS1[3], Bb[3], S[1]); and BS00gate(BS0[0], B[0], S[0]); and BS01gate(BS0[1], B[1], S[0]); and BS02gate(BS0[2], B[2], S[0]); and BS03gate(BS0[3], B[3], S[0]); nor D0gate(D[0], BbS1[0], BS0[0], A[0]); nor D1gate(D[1], BbS1[1], BS0[1], A[1]); nor D2gate(D[2], BbS1[2], BS0[2], A[2]); nor D3gate(D[3], BbS1[3], BS0[3], A[3]); endmodule /* Dmodule */ /*************************************************************************/ module CLAmodule(Gb, Pb, CNb, C, X, Y, CN4b); input [3:0] Gb, Pb; input CNb; output [3:0] C; output X, Y, CN4b; not C0gate(C[0], CNb); buf Pb0gate(Pb0, Pb[0]); and CNbGb0gate(CNbGb0, CNb, Gb[0]); buf Pb1gate(Pb1, Pb[1]); and Pb0Gb1gate(Pb0Gb1, Pb[0], Gb[1]); and CNbGb01gate(CNbGb01, CNb, Gb[0], Gb[1]); buf Pb2gate(Pb2, Pb[2]); and Pb1Gb2gate(Pb1Gb2, Pb[1], Gb[2]); and Pb0Gb12gate(Pb0Gb12, Pb[0], Gb[1], Gb[2]); and CNbGb012gate(CNbGb012, CNb, Gb[0], Gb[1], Gb[2]); buf Pb3gate(Pb3, Pb[3]); and Pb2Gb3gate(Pb2Gb3, Pb[2], Gb[3]); and Pb1Gb23gate(Pb1Gb23, Pb[1], Gb[2], Gb[3]); and Pb0Gb123gate(Pb0Gb123, Pb[0], Gb[1], Gb[2], Gb[3]); nand Xgate(X, Gb[0], Gb[1], Gb[2], Gb[3]); nor Ygate(Y, Pb3,Pb2Gb3,Pb1Gb23,Pb0Gb123); nand XCNbgate(XCNb, Gb[0], Gb[1], Gb[2], Gb[3], CNb); nand CN4bgate(CN4b, Y, XCNb); nor C3gate(C[3], Pb2, Pb1Gb2, Pb0Gb12, CNbGb012); nor C2gate(C[2], Pb1, Pb0Gb1, CNbGb01); nor C1gate(C[1], Pb0, CNbGb0); endmodule /* CLAmodule */ /*************************************************************************/ module Summodule(E, D, C, M, F, AEB); input [3:0] E, D, C; input M; output [3:0] F; output AEB; wire [3:0] EXD, CM; xor EXD0gate(EXD[0], E[0], D[0]); xor EXD1gate(EXD[1], E[1], D[1]); xor EXD2gate(EXD[2], E[2], D[2]); xor EXD3gate(EXD[3], E[3], D[3]); or CM0gate(CM[0], C[0], M); or CM1gate(CM[1], C[1], M); or CM2gate(CM[2], C[2], M); or CM3gate(CM[3], C[3], M); xor F0gate(F[0], EXD[0], CM[0]); xor F1gate(F[1], EXD[1], CM[1]); xor F2gate(F[2], EXD[2], CM[2]); xor F3gate(F[3], EXD[3], CM[3]); and AEBgate(AEB, F[0], F[1], F[2], F[3]); endmodule /* Summodule */ |
Added 74181b.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 |
/****************************************************************************
* *
* VERILOG BEHAVIORAL DESCRIPTION OF THE TI 74181 CIRCUIT *
* *
* Function: 4-bit ALU/Function Generator *
* *
* Written by: Mark C. Hansen *
* *
* Last modified: Dec 11, 1997 *
* *
****************************************************************************/
module Circuit74181b (S, A, B, M, CNb, F, X, Y, CN4b, AEB);
input [3:0] A, B, S;
input CNb, M;
output [3:0] F;
output AEB, X, Y, CN4b;
TopLevel74181b Ckt74181b (S, A, B, M, CNb, F, X, Y, CN4b, AEB);
endmodule /* Circuit74181b */
/*************************************************************************/
module TopLevel74181b (S, A, B, M, CNb, F, X, Y, CN4b, AEB);
input [3:0] A, B, S;
input CNb, M;
output [3:0] F;
output AEB, X, Y, CN4b;
wire [3:0] E, D, C, Bb;
Emodule Emod1 (A, B, S, E);
Dmodule Dmod2 (A, B, S, D);
CLAmodule CLAmod3(E, D, CNb, C, X, Y, CN4b);
Summodule Summod4(E, D, C, M, F, AEB);
endmodule /* TopLevel74181b */
/*************************************************************************/
module Emodule (A, B, S, E);
input [3:0] A, B, S;
output [3:0] E;
wire [3:0] ABS3, ABbS2;
assign ABS3 = A&B&{4{S[3]}};
assign ABbS2 = A&~B&{4{S[2]}};
assign E = ~(ABS3|ABbS2);
endmodule /* Emodule */
/*************************************************************************/
module Dmodule (A, B, S, D);
input [3:0] A, B, S;
output [3:0] D;
wire [3:0] BbS1, BS0;
assign BbS1 = ~B&{4{S[1]}};
assign BS0 = B&{4{S[0]}};
assign D = ~(BbS1|BS0|A);
endmodule /* Dmodule */
/*************************************************************************/
module CLAmodule(Gb, Pb, CNb, C, X, Y, CN4b);
input [3:0] Gb, Pb;
input CNb;
output [3:0] C;
output X, Y, CN4b;
assign C[0] = ~CNb;
assign C[1] = ~(Pb[0]|(CNb&Gb[0]));
assign C[2] = ~(Pb[1]|(Pb[0]&Gb[1])|(CNb&Gb[0]&Gb[1]));
assign C[3] = ~(Pb[2]|(Pb[1]&Gb[2])|(Pb[0]&Gb[1]&Gb[2])|(CNb&Gb[0]&Gb[1]&Gb[2]));
assign X = ~&Gb;
assign Y = ~(Pb[3]|(Pb[2]&Gb[3])|(Pb[1]&Gb[2]&Gb[3])|(Pb[0]&Gb[1]&Gb[2]&Gb[3]));
assign CN4b = ~(Y&~(&Gb&CNb));
endmodule /* CLAmodule */
/*************************************************************************/
module Summodule(E, D, C, M, F, AEB);
input [3:0] E, D, C;
input M;
output [3:0] F;
output AEB;
assign F = (E ^ D) ^ (C|{4{M}});
assign AEB = &F;
endmodule /* Summodule */
|
Added 74181gates.gif.
cannot compute difference between binary files
Added 74181gates.html.
> > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>74181gates</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\Program Files\Microsoft Office\Office\HTML.DOT"> </HEAD> <BODY TEXT="#000000" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">74181 Gate-Level Schematic</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="74181gates.gif" WIDTH=324 HEIGHT=331></P></BODY> </HTML> |
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> > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>74181m1</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY TEXT="#000000" LINK="#0000ff" VLINK="#800080" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">74181 Module M1</P> </B></FONT><P ALIGN="CENTER"> <IMG SRC="74181m1.gif" WIDTH=433 HEIGHT=150></P></BODY> </HTML> |
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> > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>74181m2</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\Program Files\Microsoft Office\Office\HTML.DOT"> </HEAD> <BODY TEXT="#000000" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">74181 Module M2</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="74181m2.gif" WIDTH=433 HEIGHT=154></P></BODY> </HTML> |
Added 74182.gif.
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> > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>74182</TITLE> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080"> <B><FONT SIZE=5><P ALIGN="CENTER">74182 Carry Look-Ahead Circuit</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="74182.gif" WIDTH=433 HEIGHT=231></P> <B><P>Statistics: </B>9 inputs; 4 output; 19 gates; <A HREF="74182gates.html">gate-level schematic</A></P> <B><P>Function: </B>The carry look-ahead (CLA) realization of the carry function is used by each of the 74X-series circuits modeled here. Given carry-in (C_n), generate (G) and propagate (P) signals, the circuit produces three carry out signals, plus two P and G signals used to cascade into another CLA block. This circuit is small enough to be modeled as a single primitive. </P> <B><P>Models:</P> <UL> <LI></B><A HREF="74182.isc">74182 ISCAS-85 netlist</A><B> </LI> </B><LI><A HREF="74182.v">74182 Verilog structural model</A><B> </LI> </B><LI><A HREF="74182b.v">74182 behavioral model</A> </LI> <LI><A HREF="74182.tests">74182 complete gate-level tests (CN, PB[3:0], GB[3:0])</A></LI></UL> <B><P> </P> <P><DIV></DIV><DIV></DIV></P> </B><FONT SIZE=2><P> </P></FONT></BODY> </HTML> |
Added 74182.isc.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 | 1 1gat inpt 2 0 >sa0 >sa1 2 2fan from 1gat >sa0 >sa1 3 3fan from 1gat >sa0 >sa1 4 4gat inpt 4 0 >sa0 >sa1 5 5fan from 4gat >sa0 >sa1 6 6fan from 4gat >sa0 >sa1 7 7fan from 4gat >sa0 >sa1 8 8fan from 4gat >sa0 >sa1 9 9gat inpt 3 0 >sa0 >sa1 10 10fan from 9gat >sa0 >sa1 11 11fan from 9gat >sa0 >sa1 12 12fan from 9gat >sa0 >sa1 13 13gat inpt 7 0 >sa0 >sa1 14 14fan from 13gat >sa0 >sa1 15 15fan from 13gat >sa0 >sa1 16 16fan from 13gat >sa0 >sa1 17 17fan from 13gat >sa0 >sa1 18 18fan from 13gat >sa0 >sa1 19 19fan from 13gat >sa0 >sa1 20 20fan from 13gat >sa0 >sa1 21 21gat inpt 4 0 >sa0 >sa1 22 22fan from 21gat >sa0 >sa1 23 23fan from 21gat >sa0 >sa1 24 24fan from 21gat >sa0 >sa1 25 25fan from 21gat >sa0 >sa1 26 26gat inpt 8 0 >sa0 >sa1 27 27fan from 26gat >sa0 >sa1 28 28fan from 26gat >sa0 >sa1 29 29fan from 26gat >sa0 >sa1 30 30fan from 26gat >sa0 >sa1 31 31fan from 26gat >sa0 >sa1 32 32fan from 26gat >sa0 >sa1 33 33fan from 26gat >sa0 >sa1 34 34fan from 26gat >sa0 >sa1 35 35gat inpt 4 0 >sa0 >sa1 36 36fan from 35gat >sa0 >sa1 37 37fan from 35gat >sa0 >sa1 38 38fan from 35gat >sa0 >sa1 39 39fan from 35gat >sa0 >sa1 40 40gat inpt 7 0 >sa0 >sa1 41 41fan from 40gat >sa0 >sa1 42 42fan from 40gat >sa0 >sa1 43 43fan from 40gat >sa0 >sa1 44 44fan from 40gat >sa0 >sa1 45 45fan from 40gat >sa0 >sa1 46 46fan from 40gat >sa0 >sa1 47 47fan from 40gat >sa0 >sa1 48 48gat inpt 1 0 >sa0 >sa1 49 49gat not 3 1 >sa0 >sa1 48 50 50fan from 49gat >sa0 >sa1 51 51fan from 49gat >sa0 >sa1 52 52fan from 49gat >sa0 >sa1 53 53gat or 0 4 >sa0 >sa1 2 10 22 36 54 54gat and 1 4 >sa0 >sa1 5 14 27 41 55 55gat and 1 4 >sa0 >sa1 23 6 15 28 56 56gat and 1 3 >sa0 >sa1 11 7 16 57 57gat and 1 2 >sa0 >sa1 3 8 58 58gat or 0 4 >sa0 >sa1 54 55 56 57 59 59gat and 1 4 >sa0 >sa1 17 29 42 50 60 60gat and 1 4 >sa0 >sa1 37 18 30 43 61 61gat and 1 3 >sa0 >sa1 24 19 31 62 62gat and 1 2 >sa0 >sa1 12 20 63 63gat nor 0 4 >sa0 >sa1 59 60 61 62 64 64gat and 1 3 >sa0 >sa1 32 44 51 65 65gat and 1 3 >sa0 >sa1 38 33 45 66 66gat and 1 2 >sa0 >sa1 25 34 67 67gat nor 0 3 >sa0 >sa1 64 65 66 68 68gat and 1 2 >sa0 >sa1 46 52 69 69gat and 1 2 >sa0 >sa1 39 47 70 70gat nor 0 2 >sa0 >sa1 68 69 |
Added 74182.tests.
> > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 | 000001111 100001111 000011110 000111101 001111011 011110111 100011111 100101110 101001100 110001000 |
Added 74182.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 | /**************************************************************************** * * * VERILOG HIGH-LEVEL DESCRIPTION OF THE TI 74182 CIRCUIT * * * * Function: Carry Lookahead Generator * * * * Written by: Mark C. Hansen * * * * Last modified: Dec 10, 1997 * * * ****************************************************************************/ module Circuit74182 (CN, PB, GB, PBo, GBo, CNX, CNY, CNZ); input[3:0] PB, GB; input CN; output PBo, GBo, CNX, CNY, CNZ; TopLevel74182 Ckt74182 (CN, PB, GB, PBo, GBo, CNX, CNY, CNZ); endmodule /* Circuit74182 */ /*************************************************************************/ module TopLevel74182 (CN, PB, GB, PBo, GBo, CNX, CNY, CNZ); input[3:0] PB, GB; input CN; output PBo, GBo, CNX, CNY, CNZ; not CNBgate(CNB, CN); and PB0GB0gate(PB0GB0, PB[0], GB[0]); and CNBGB0gate(CNBGB0, CNB, GB[0]); and PB1GB1gate(PB1GB1, PB[1], GB[1]); and PB0GB01gate(PB0GB01, PB[0], GB[0], GB[1]); and CNBGB01gate(CNBGB01, CNB, GB[0], GB[1]); and PB2GB2gate(PB2GB2, PB[2], GB[2]); and PB1GB12gate(PB1GB12, PB[1], GB[1], GB[2]); and PB0GB012gate(PB0GB012, PB[0], GB[0], GB[1], GB[2]); and CNBGB012gate(CNBGB012, CNB, GB[0], GB[1], GB[2]); and PB3GB3gate(PB3GB3, PB[3], GB[3]); and PB2GB23gate(PB2GB23, PB[2], GB[2], GB[3]); and PB1GB123gate(PB1GB123, PB[1], GB[1], GB[2], GB[3]); and GB0123gate(GB0123, GB[0], GB[1], GB[2], GB[3]); or PBogate(PBo,PB[0],PB[1],PB[2],PB[3]); or GBogate(GBo,PB3GB3,PB2GB23,PB1GB123,GB0123); nor CNZgate(CNZ,PB2GB2,PB1GB12,PB0GB012,CNBGB012); nor CNYgate(CNY,PB1GB1,PB0GB01,CNBGB01); nor CNXgate(CNX,PB0GB0,CNBGB0); endmodule /* TopLevel74182 */ |
Added 74182b.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 |
/****************************************************************************
* *
* VERILOG BEHAVIORAL DESCRIPTION OF THE TI 74182 CIRCUIT *
* *
* Function: Carry Lookahead Generator *
* *
* Written by: Mark C. Hansen *
* *
* Last modified: Dec 10, 1997 *
* *
****************************************************************************/
module Circuit74182 (CN, PB, GB, PBo, GBo, CNX, CNY, CNZ);
input[3:0] PB, GB;
input CN;
output PBo, GBo, CNX, CNY, CNZ;
TopLevel74182b Ckt74182b (CN, PB, GB, PBo, GBo, CNX, CNY, CNZ);
endmodule /* Circuit74182 */
/*************************************************************************/
module TopLevel74182b (CN, PB, GB, PBo, GBo, CNX, CNY, CNZ);
input[3:0] PB, GB;
input CN;
output PBo, GBo, CNX, CNY, CNZ;
assign PBo = (PB[0]|PB[1]|PB[2]|PB[3]);
assign GBo = ((GB[0]&GB[1]&GB[2]&GB[3]) |
(PB[1]&GB[1]&GB[2]&GB[3]) |
(PB[2]&GB[2]&GB[3]) |
(PB[3]&GB[3]));
assign CNX = ~((PB[0]&GB[0]) |
(~CN&GB[0]));
assign CNY = ~((PB[1]&GB[1]) |
(PB[0]&GB[0]&GB[1]) |
(~CN&GB[0]&GB[1]));
assign CNZ = ~((PB[2]&GB[2]) |
(PB[1]&GB[1]&GB[2]) |
(PB[0]&GB[0]&GB[1]&GB[2]) |
(~CN&GB[0]&GB[1]&GB[2]));
endmodule /* TopLevel74182b */
|
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> > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>74182gates</TITLE> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080"> <B><FONT SIZE=5><P ALIGN="CENTER">74182 Gate-Level Schematic</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="74182gates.gif" WIDTH=433 HEIGHT=460></P></BODY> </HTML> |
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> > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>74283</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY TEXT="#000000" LINK="#0000ff" VLINK="#800080" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">74283 Fast Adder Circuit</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="74283.gif" WIDTH=433 HEIGHT=231></P> <B><P>Statistics: </B>9 inputs; 5 outputs; 36 gates; <A HREF="74283gates.html"> gate-level schematic</A></P> <B><P>Function: </B>The 74283 fast adder can be modeled as shown above. The module <A HREF="74283m1.html">M1</A> produces the generate, propagate, and XOR functions. The module M2 is similar to the <A HREF="74182.html">74182</A>. The XOR word gate M3 produces the sum function.</P> <B><P>Models:</P> <UL> </B><LI><A HREF="74283.isc">74283 ISCAS-85 netlist</A><B> </LI> </B><LI><A HREF="74283.v">74283 Verilog structural model</A><B> </LI> </B><LI><A HREF="74283b.v">74283 behavioral model</A> </LI> <LI><A HREF="74283.tests">74283 complete gate-level tests (C0, A[3:0], B[3:0])</A></LI></UL> <P></DIV><DIV></P></BODY> </HTML> |
Added 74283.isc.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 | 1 1gat inpt 2 0 >sa0 >sa1 2 2fan from 1gat >sa0 >sa1 3 3fan from 1gat >sa0 >sa1 4 4gat inpt 2 0 >sa0 >sa1 5 5fan from 4gat >sa0 >sa1 6 6fan from 4gat >sa0 >sa1 7 7gat inpt 2 0 >sa0 >sa1 8 8fan from 7gat >sa0 >sa1 9 9fan from 7gat >sa0 >sa1 10 10gat inpt 2 0 >sa0 >sa1 11 11fan from 10gat >sa0 >sa1 12 12fan from 10gat >sa0 >sa1 13 13gat inpt 2 0 >sa0 >sa1 14 14fan from 13gat >sa0 >sa1 15 15fan from 13gat >sa0 >sa1 16 16gat inpt 2 0 >sa0 >sa1 17 17fan from 16gat >sa0 >sa1 18 18fan from 16gat >sa0 >sa1 19 19gat inpt 2 0 >sa0 >sa1 20 20fan from 19gat >sa0 >sa1 21 21fan from 19gat >sa0 >sa1 22 22gat inpt 2 0 >sa0 >sa1 23 23fan from 22gat >sa0 >sa1 24 24fan from 22gat >sa0 >sa1 25 25gat inpt 1 0 >sa0 >sa1 26 26gat not 5 1 >sa0 >sa1 25 27 27fan from 26gat >sa0 >sa1 28 28fan from 26gat >sa0 >sa1 29 29fan from 26gat >sa0 >sa1 30 30fan from 26gat >sa0 >sa1 31 31fan from 26gat >sa0 >sa1 32 32gat nand 5 2 >sa0 >sa1 2 5 33 33fan from 32gat >sa0 >sa1 34 34fan from 32gat >sa0 >sa1 35 35fan from 32gat >sa0 >sa1 36 36fan from 32gat >sa0 >sa1 37 37fan from 32gat >sa0 >sa1 38 38gat nor 2 2 >sa0 >sa1 3 6 39 39fan from 38gat >sa0 >sa1 40 40fan from 38gat >sa0 >sa1 41 41gat nand 7 2 >sa0 >sa1 8 11 42 42fan from 41gat >sa0 >sa1 43 43fan from 41gat >sa0 >sa1 44 44fan from 41gat >sa0 >sa1 45 45fan from 41gat >sa0 >sa1 46 46fan from 41gat >sa0 >sa1 47 47fan from 41gat >sa0 >sa1 48 48fan from 41gat >sa0 >sa1 49 49gat nor 3 2 >sa0 >sa1 9 12 50 50fan from 49gat >sa0 >sa1 51 51fan from 49gat >sa0 >sa1 52 52fan from 49gat >sa0 >sa1 53 53gat nand 7 2 >sa0 >sa1 14 17 54 54fan from 53gat >sa0 >sa1 55 55fan from 53gat >sa0 >sa1 56 56fan from 53gat >sa0 >sa1 57 57fan from 53gat >sa0 >sa1 58 58fan from 53gat >sa0 >sa1 59 59fan from 53gat >sa0 >sa1 60 60fan from 53gat >sa0 >sa1 61 61gat nor 4 2 >sa0 >sa1 15 18 62 62fan from 61gat >sa0 >sa1 63 63fan from 61gat >sa0 >sa1 64 64fan from 61gat >sa0 >sa1 65 65fan from 61gat >sa0 >sa1 66 66gat nand 5 2 >sa0 >sa1 20 23 67 67fan from 66gat >sa0 >sa1 68 68fan from 66gat >sa0 >sa1 69 69fan from 66gat >sa0 >sa1 70 70fan from 66gat >sa0 >sa1 71 71fan from 66gat >sa0 >sa1 72 72gat nor 5 2 >sa0 >sa1 21 24 73 73fan from 72gat >sa0 >sa1 74 74fan from 72gat >sa0 >sa1 75 75fan from 72gat >sa0 >sa1 76 76fan from 72gat >sa0 >sa1 77 77fan from 72gat >sa0 >sa1 78 78gat not 1 1 >sa0 >sa1 40 79 79gat not 1 1 >sa0 >sa1 52 80 80gat not 1 1 >sa0 >sa1 65 81 81gat not 1 1 >sa0 >sa1 77 82 82gat and 1 2 >sa0 >sa1 33 50 83 83gat and 1 3 >sa0 >sa1 34 42 62 84 84gat and 1 4 >sa0 >sa1 35 43 54 73 85 85gat and 1 5 >sa0 >sa1 36 44 55 67 27 86 86gat and 1 2 >sa0 >sa1 37 78 87 87gat and 1 2 >sa0 >sa1 63 45 88 88gat and 1 3 >sa0 >sa1 74 46 56 89 89gat and 1 4 >sa0 >sa1 47 57 68 28 90 90gat and 1 2 >sa0 >sa1 48 79 91 91gat and 1 2 >sa0 >sa1 75 58 92 92gat and 1 3 >sa0 >sa1 59 69 29 93 93gat and 1 2 >sa0 >sa1 60 80 94 94gat and 1 2 >sa0 >sa1 30 70 95 95gat and 1 2 >sa0 >sa1 71 81 96 96gat not 1 1 >sa0 >sa1 31 97 97gat nor 0 5 >sa0 >sa1 39 82 83 84 85 98 98gat nor 1 4 >sa0 >sa1 51 87 88 89 99 99gat nor 1 3 >sa0 >sa1 64 91 92 100 100gat nor 1 2 >sa0 >sa1 76 94 101 101gat xor 0 2 >sa0 >sa1 86 98 102 102gat xor 0 2 >sa0 >sa1 90 99 103 103gat xor 0 2 >sa0 >sa1 93 100 104 104gat xor 0 2 >sa0 >sa1 95 96 |
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> > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 | 011110000 100001111 011110001 011100010 011000100 010001000 111100000 111010000 110110001 001110011 |
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 | /**************************************************************************** * * * VERILOG HIGH-LEVEL DESCRIPTION OF THE TI 74283 CIRCUIT * * * * Function: Four-bit Fast Adder * * * * Written by: Mark C. Hansen * * * * Last modified: Dec 12, 1997 * * * ****************************************************************************/ module Circuit74283 (C0, A, B, S, C4); input[3:0] A, B; input C0; output[3:0] S; output C4; TopLevel74283 Ckt74283 (C0, A, B, S, C4); endmodule /* Circuit74283 */ /*************************************************************************/ module TopLevel74283 (C0, A, B, S, C4); input[3:0] A, B; input C0; output[3:0] S; output C4; wire[3:0] GB, PB, AxB; wire[3:0] C; GP_Module GP_Mod1(A, B, GB, PB, AxB); CLA_Module CLA_Mod2(GB, PB, C0, C, C4); Sum_Module Sum_Mod3(AxB, C, S); endmodule /* TopLevel74182 */ /*************************************************************************/ module GP_Module(A, B, GB, PB, AxB); input[3:0] A, B; output[3:0] GB, PB, AxB; wire[3:0] P; nor PBgate0(PB[0], A[0], B[0]); nand GBgate0(GB[0], A[0], B[0]); not Pgate0(P[0], PB[0]); and AxBgate0(AxB[0], GB[0], P[0]); nor PBgate1(PB[1], A[1], B[1]); nand GBgate1(GB[1], A[1], B[1]); not Pgate1(P[1], PB[1]); and AxBgate1(AxB[1], GB[1], P[1]); nor PBgate2(PB[2], A[2], B[2]); nand GBgate2(GB[2], A[2], B[2]); not Pgate2(P[2], PB[2]); and AxBgate2(AxB[2], GB[2], P[2]); nor PBgate3(PB[3], A[3], B[3]); nand GBgate3(GB[3], A[3], B[3]); not Pgate3(P[3], PB[3]); and AxBgate3(AxB[3], GB[3], P[3]); endmodule /* GP_Module */ /*************************************************************************/ module CLA_Module(GB, PB, C0, C, C4); input[3:0] GB, PB; input C0; output[3:0] C; output C4; not C0Bgate(C0B, C0); not C0gate(C[0], C0B); buf PB0gate(PB0, PB[0]); and C0BGB0gate(C0BGB0, C0B, GB[0]); buf PB1gate(PB1, PB[1]); and PB0GB1gate(PB0GB1, PB[0], GB[1]); and C0BGB01gate(C0BGB01, C0B, GB[0], GB[1]); buf PB2gate(PB2, PB[2]); and PB1GB2gate(PB1GB2, PB[1], GB[2]); and PB0GB12gate(PB0GB12, PB[0], GB[1], GB[2]); and C0BGB012gate(C0BGB012, C0B, GB[0], GB[1], GB[2]); buf PB3gate(PB3, PB[3]); and PB2GB3gate(PB2GB3, PB[2], GB[3]); and PB1GB23gate(PB1GB23, PB[1], GB[2], GB[3]); and PB0GB123gate(PB0GB123, PB[0], GB[1], GB[2], GB[3]); and C0BGB0123gate(C0BGB0123, C0B, GB[0], GB[1], GB[2], GB[3]); nor C4gate(C4,PB3,PB2GB3,PB1GB23,PB0GB123,C0BGB0123); nor C3gate(C[3],PB2,PB1GB2,PB0GB12,C0BGB012); nor C2gate(C[2],PB1,PB0GB1,C0BGB01); nor C1gate(C[1],PB0,C0BGB0); endmodule /* CLA_Module */ /*************************************************************************/ module Sum_Module(AxB, C, S); input[3:0] AxB; input[3:0] C; output[3:0] S; xor Sum0(S[0], C[0], AxB[0]); xor Sum1(S[1], C[1], AxB[1]); xor Sum2(S[2], C[2], AxB[2]); xor Sum3(S[3], C[3], AxB[3]); endmodule /* Sum_Module */ |
Added 74283b.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 | /**************************************************************************** * * * VERILOG BEHAVIORAL DESCRIPTION OF THE TI 74283 CIRCUIT * * * * Function: Four-bit Fast Adder * * * * Written by: Mark C. Hansen * * * * Last modified: Dec 12, 1997 * * * ****************************************************************************/ module Circuit74283b (C0, A, B, S, C4); input[3:0] A, B; input C0; output[3:0] S; output C4; TopLevel74283b Ckt74283b (C0, A, B, S, C4); endmodule /* Circuit74283b */ /*************************************************************************/ module TopLevel74283b (C0, A, B, S, C4); input[3:0] A, B; input C0; output[3:0] S; output C4; wire[4:0] CS; assign CS = A + B + C0; assign S = CS[3:0]; assign C4 = CS[4]; endmodule /* TopLevel74182b */ |
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> > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>74283gates</TITLE> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080"> <B><FONT SIZE=5><P ALIGN="CENTER">74283 Gate-Level Schematic</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="74283gates.gif" ></P></BODY> </HTML> |
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> > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>74283m1</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\Program Files\Microsoft Office\Office\HTML.DOT"> </HEAD> <BODY TEXT="#000000" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">74283 Module M1</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="74283m1.gif" WIDTH=433 HEIGHT=163></P> <P ALIGN="CENTER"></P></BODY> </HTML> |
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> > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>7485</TITLE> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080"> <B><FONT SIZE=5><P ALIGN="CENTER">74L85 4-Bit Magnitude Comparator</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="74L85.gif" WIDTH=433 HEIGHT=316></P> <B><P>Statistics: </B>11 inputs; 3 outputs; 33 gates;</P> <B><P ALIGN="JUSTIFY">Function: </B>The 74L85 magnitude comparator can be functionally modeled as above. This is a simplification of implementing a magnitude comparator by a carry function with an inverted input bus as shown <A HREF="74L85generic.html">here</A>. Using this concept, common elements of the three comparator functions A < B, A > B, and A = B are combined to construct the model shown above, which maps directly onto the gate-level realization of the 74L85.</P> <B><P>Models:</P> <UL> </B><LI><A HREF="74L85.isc">74L85 ISCAS-85 netlist</A><B> </LI> </B><LI><A HREF="74L85.v">74L85 Verilog structural model</A><B> </LI> </B><LI><A HREF="74L85b.v">74L85 behavioral model</A> </LI> <LI><A HREF="74L85.tests">74L85 complete gate-level tests (A<B, A>B, A=B, A[3:0], B[3:0])</A></LI></UL> <P ALIGN="CENTER"><DIV></DIV><DIV></P></BODY> </HTML> |
Added 74L85.isc.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 | * 74L85 * inpt 3 0 >sa0 >sa1 inpt 3 0 >sa0 >sa1 inpt 3 0 >sa0 >sa1 inpt 3 0 >sa0 >sa1 inpt 3 0 >sa0 >sa1 inpt 3 0 >sa0 >sa1 inpt 3 0 >sa0 >sa1 inpt 3 0 >sa0 >sa1 inpt 1 0 >sa0 >sa1 inpt 1 0 >sa0 >sa1 inpt 1 0 >sa0 >sa1 fan 1 1 >sa0 >sa1 1 fan 1 1 >sa0 >sa1 1 fan 1 1 >sa0 >sa1 1 fan 1 1 >sa0 >sa1 2 fan 1 1 >sa0 >sa1 2 fan 1 1 >sa0 >sa1 2 fan 1 1 >sa0 >sa1 3 fan 1 1 >sa0 >sa1 3 fan 1 1 >sa0 >sa1 3 fan 1 1 >sa0 >sa1 4 fan 1 1 >sa0 >sa1 4 fan 1 1 >sa0 >sa1 4 fan 1 1 >sa0 >sa1 5 fan 1 1 >sa0 >sa1 5 fan 1 1 >sa0 >sa1 5 fan 1 1 >sa0 >sa1 6 fan 1 1 >sa0 >sa1 6 fan 1 1 >sa0 >sa1 6 fan 1 1 >sa0 >sa1 7 fan 1 1 >sa0 >sa1 7 fan 1 1 >sa0 >sa1 7 fan 1 1 >sa0 >sa1 8 fan 1 1 >sa0 >sa1 8 fan 1 1 >sa0 >sa1 8 not 2 1 >sa0 >sa1 12 not 2 1 >sa0 >sa1 15 not 2 1 >sa0 >sa1 18 not 2 1 >sa0 >sa1 21 not 2 1 >sa0 >sa1 24 not 2 1 >sa0 >sa1 27 not 2 1 >sa0 >sa1 30 not 2 1 >sa0 >sa1 33 fan 1 1 >sa0 >sa1 36 fan 1 1 >sa0 >sa1 36 fan 1 1 >sa0 >sa1 37 fan 1 1 >sa0 >sa1 37 fan 1 1 >sa0 >sa1 38 fan 1 1 >sa0 >sa1 38 fan 1 1 >sa0 >sa1 39 fan 1 1 >sa0 >sa1 39 fan 1 1 >sa0 >sa1 40 fan 1 1 >sa0 >sa1 40 fan 1 1 >sa0 >sa1 41 fan 1 1 >sa0 >sa1 41 fan 1 1 >sa0 >sa1 42 fan 1 1 >sa0 >sa1 42 fan 1 1 >sa0 >sa1 43 fan 1 1 >sa0 >sa1 43 and 1 2 >sa0 >sa1 45 17 and 1 2 >sa0 >sa1 46 13 and 1 2 >sa0 >sa1 49 23 and 1 2 >sa0 >sa1 19 50 and 1 2 >sa0 >sa1 53 28 and 1 2 >sa0 >sa1 54 25 and 1 2 >sa0 >sa1 57 34 and 1 2 >sa0 >sa1 58 31 nor 9 2 >sa0 >sa1 60 61 nor 7 2 >sa0 >sa1 62 63 nor 5 2 >sa0 >sa1 64 65 nor 3 2 >sa0 >sa1 66 67 fan 1 1 >sa0 >sa1 68 fan 1 1 >sa0 >sa1 68 fan 1 1 >sa0 >sa1 68 fan 1 1 >sa0 >sa1 68 fan 1 1 >sa0 >sa1 68 fan 1 1 >sa0 >sa1 68 fan 1 1 >sa0 >sa1 68 fan 1 1 >sa0 >sa1 68 fan 1 1 >sa0 >sa1 68 fan 1 1 >sa0 >sa1 69 fan 1 1 >sa0 >sa1 69 fan 1 1 >sa0 >sa1 69 fan 1 1 >sa0 >sa1 69 fan 1 1 >sa0 >sa1 69 fan 1 1 >sa0 >sa1 69 fan 1 1 >sa0 >sa1 69 fan 1 1 >sa0 >sa1 70 fan 1 1 >sa0 >sa1 70 fan 1 1 >sa0 >sa1 70 fan 1 1 >sa0 >sa1 70 fan 1 1 >sa0 >sa1 70 fan 1 1 >sa0 >sa1 71 fan 1 1 >sa0 >sa1 71 fan 1 1 >sa0 >sa1 71 and 1 2 >sa0 >sa1 16 44 and 1 2 >sa0 >sa1 14 47 and 1 3 >sa0 >sa1 22 72 48 and 1 3 >sa0 >sa1 51 73 20 and 1 4 >sa0 >sa1 29 74 81 52 and 1 4 >sa0 >sa1 55 75 82 26 and 1 5 >sa0 >sa1 35 76 83 88 56 and 1 5 >sa0 >sa1 59 77 84 89 32 and 1 5 >sa0 >sa1 78 85 90 93 9 and 1 5 >sa0 >sa1 79 86 91 94 10 and 0 5 >sa0 >sa1 80 87 92 95 11 or 0 5 >sa0 >sa1 97 99 101 103 104 or 0 5 >sa0 >sa1 96 98 100 102 105 |
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> > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 | 00011111111 11111111111 11111111110 11111111101 11111111011 11111110111 11111101111 11111011111 11110111111 11101111111 11111011110 11110111110 11101111110 11110111101 11101111101 11101111011 11111101101 11111101011 11111100111 11111011011 11111010111 11110110111 00100000000 |
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 | /**************************************************************************** * * * VERILOG HIGH-LEVEL DESCRIPTION OF THE TI 74L85 CIRCUIT * * * * Function: Four-Bit Magnitude Comarator * * * * Written by: Mark C. Hansen * * * * Last modified: Dec 20, 1997 * * * ****************************************************************************/ module Circuit74L85 (ALBi, AGBi, AEBi, A, B, ALBo, AGBo, AEBo); input[3:0] A, B; input ALBi, AGBi, AEBi; output ALBo, AGBo, AEBo; TopLevel74L85 Ckt74L85 (ALBi, AGBi, AEBi, A, B, ALBo, AGBo, AEBo); endmodule /* Circuit74L85 */ /*************************************************************************/ module TopLevel74L85 (ALBi, AGBi, AEBi, A, B, ALBo, AGBo, AEBo); input[3:0] A, B; input ALBi, AGBi, AEBi; output ALBo, AGBo, AEBo; wire[3:0] G1, G2, P; GPmodule GPmod0(A,B,G1,G2,P); CLAmodule ALBmod1(G1,P,ALBi,ALBo); CLAmodule AGBmod2(G2,P,AGBi,AGBo); EQmodule EQmod3(AEBi,P,AEBo); endmodule /* TopLevel74L85 */ /*************************************************************************/ module GPmodule(A,B,G1,G2,P); input[3:0] A, B; output[3:0] G1, G2, P; wire[3:0] Ab, Bb, AbB, ABb; not A0bgate(Ab[0], A[0]); not A1bgate(Ab[1], A[1]); not A2bgate(Ab[2], A[2]); not A3bgate(Ab[3], A[3]); not B0bgate(Bb[0], B[0]); not B1bgate(Bb[1], B[1]); not B2bgate(Bb[2], B[2]); not B3bgate(Bb[3], B[3]); and G10gate(G1[0], Ab[0], B[0]); and G11gate(G1[1], Ab[1], B[1]); and G12gate(G1[2], Ab[2], B[2]); and G13gate(G1[3], Ab[3], B[3]); and G20gate(G2[0], A[0], Bb[0]); and G21gate(G2[1], A[1], Bb[1]); and G22gate(G2[2], A[2], Bb[2]); and G23gate(G2[3], A[3], Bb[3]); and AbB0gate(AbB[0], Ab[0], B[0]); and AbB1gate(AbB[1], Ab[1], B[1]); and AbB2gate(AbB[2], Ab[2], B[2]); and AbB3gate(AbB[3], Ab[3], B[3]); and ABb0gate(ABb[0], A[0], Bb[0]); and ABb1gate(ABb[1], A[1], Bb[1]); and ABb2gate(ABb[2], A[2], Bb[2]); and ABb3gate(ABb[3], A[3], Bb[3]); nor P0gate(P[0], AbB[0], ABb[0]); nor P1gate(P[1], AbB[1], ABb[1]); nor P2gate(P[2], AbB[2], ABb[2]); nor P3gate(P[3], AbB[3], ABb[3]); endmodule /* GPmodule */ /*************************************************************************/ module CLAmodule (G,P,AxBi,AxBo); input[3:0] G, P; input AxBi; output AxBo; buf G3gate (G3, G[3]); and G2P3gate (G2P3, G[2], P[3]); and G1P2P3gate(G1P2P3, G[1], P[2], P[3]); and G0P1P2P3gate(G0P1P2P3, G[0], P[1], P[2], P[3]); and AxBiP0P1P2P3gate(AxBiP0P1P2P3, AxBi, P[0], P[1], P[2], P[3]); or AxBogate(AxBo, G3, G2P3, G1P2P3, G0P1P2P3, AxBiP0P1P2P3); endmodule /* CLAmodule */ /*************************************************************************/ module EQmodule (AEBi,P,AEBo); input AEBi; input[3:0] P; output AEBo; and AEBogate(AEBo, AEBi, P[0], P[1], P[2], P[3]); endmodule /* EQmodule */ |
Added 74L85b.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 | /**************************************************************************** * * * VERILOG BEHAVIORAL DESCRIPTION OF THE TI 74L85 CIRCUIT * * * * Function: Four-Bit Magnitude Comarator * * * * Written by: Mark C. Hansen * * * * Last modified: Dec 20, 1997 * * * ****************************************************************************/ module Circuit74L85b (ALBi, AGBi, AEBi, A, B, ALBo, AGBo, AEBo); input[3:0] A, B; input ALBi, AGBi, AEBi; output ALBo, AGBo, AEBo; TopLevel74L85b Ckt74L85b (ALBi, AGBi, AEBi, A, B, ALBo, AGBo, AEBo); endmodule /* Circuit74L85b */ /*************************************************************************/ module TopLevel74L85b (ALBi, AGBi, AEBi, A, B, ALBo, AGBo, AEBo); input[3:0] A, B; input ALBi, AGBi, AEBi; output ALBo, AGBo, AEBo; wire[4:0] CSL, CSG; assign CSL = ~A + B + ALBi; assign ALBo = ~CSL[4]; assign CSG = A + ~B + AGBi; assign AGBo = ~CSG[4]; assign AEBo = ((A == B) && AEBi); endmodule /* TopLevel74L85b */ /*************************************************************************/ |
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> > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>74L85generic</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\Program Files\Microsoft Office\Office\HTML.DOT"> </HEAD> <BODY TEXT="#000000" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">Generic Magnitude Comparator</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="74L85generic.gif" WIDTH=433 HEIGHT=334></P></BODY> </HTML> |
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 |
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<br><B><FONT SIZE=5>ISCAS High-Level Models
<p></font></b>These pages contain high-level models for all ISCAS-85, several of the smaller ISCAS-89, and several 74X-series circuits. These models may be freely copied and used for research purposes.</P>
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<b> Recent Publication:</b>
<ul><li>M. Hansen, H. Yalcin, and J. P. Hayes, "Unveiling the ISCAS-85
Benchmarks: A Case Study in Reverse Engineering," IEEE Design and Test,
vol. 16, no. 3, pp. 72-80, July-Sept. 1999.
<P>Abstract: Digital designers normally proceed from behavioral specification to logic circuit; rarely do they need
to go in the reverse direction. One such situation is examined here: recovering the high-level specifications of a
popular set of benchmark logic circuits. The authors present their methodology and experience in reverse
engineering the ISCAS-85 circuits. They also discuss a few of the practical uses of the resulting high-level
benchmarks, and make them available for other researchers to use.
<p>The high-level ISCAS-85 benchmarks discussed in this paper are available below, and we invite other researchers to use them. The models, of which we have constructed both structural and
behavioral versions, partition the original gate-level netlists into standard RTL blocks and identify the functions of
these blocks. Together, the gate-level and high-level models form a set of hierarchicical benchmark circuits that
have proven to be useful research tools in several areas of digital design, including test generation, timing
analysis, and technology mapping. The web documentation for each model consists of annotated circuit schematic
diagrams, and executable (simulatable) descriptions written in structural Verilog. The structural models are
intended to express the specific high-level structure implicit in the original gate-level designs. In most cases, we
also provide behavioral Verilog models, which define high-level blocks in the form of logical equations that can
readily be synthesized into gates.
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<P> <B>ISCAS-85 Circuits:</P>
<UL>
<UL>
</B><LI><A HREF="c432.html">c432</A><FONT SIZE=2> </FONT>:<FONT SIZE=2> </FONT>27-channel interrupt controller </LI>
<LI><A HREF="c499.html">c499/c1355</A><FONT SIZE=2> </FONT>: 32-bit SEC circuit</LI>
<LI><A HREF="c880.html">c880</A><FONT SIZE=2> </FONT>: 8-bit ALU </LI>
<LI><A HREF="c1908/c1908.html">c1908</A> : 16-bit SEC/DED circuit </LI>
<LI><A HREF="c2670/c2670.html">c2670</A> : 12-bit ALU and controller </LI>
<LI><A HREF="c3540/c3540.html">c3540</A> : 8-bit ALU </LI>
<LI><A HREF="c5315/c5315.html">c5315</A> : 9-bit ALU </LI>
<LI><A HREF="c6288.html">c6288</A><FONT SIZE=2> </FONT>: 16x16 multiplier </LI>
<LI><A HREF="c7552/c7552.html">c7552</A> : 32-bit adder/comparator</LI></UL>
</UL>
<FONT SIZE=2><P> </FONT><B>ISCAS-89 Circuits:</P>
<UL>
<UL>
</B><LI><A HREF="s208_1.html">s208.1</A> : fractional multiplier </LI>
<LI><A HREF="s298.html">s298</A><FONT SIZE=2> </FONT>: traffic light controller </LI>
<LI><A HREF="s344.html">s344/s349</A><FONT SIZE=2> </FONT>: 4x4 add-shift multiplier</LI></UL>
</UL>
<B><P> 74X-Series Circuits:</P>
<UL>
<UL>
</B><LI><A HREF="74182.html">74182</A> : 4-bit carry-lookahead generator </LI>
<LI><A HREF="74283.html">74283</A> : 4-bit adder </LI>
<LI><A HREF="74181.html">74181</A> : 4-bit ALU </LI>
<LI><A HREF="74L85.html">74L85</A> : 4-bit magnitude comparator</LI></UL>
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<p>Acknowledgement: The reverse engineering work was carried out
at the University of Michigan by Mark Hansen, Hakan Yalcin,
and John Hayes. They would like to thank Hyungwon Kim
for his assistance in constructing some of the Verilog models, as
well as Hussain Al-Asaad and Jonathan Hauke for checking the models.
Thanks are also due to Delphi Delco Electronics Systems, the National
Science Foundation (under Grant No. MIP-9503463), and the
Semiconductor Research Corporation for supporting various
portions of the research contributing to this effort.<p>
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Added c1355.isc.
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 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1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 |
* combinational logic example "c1355"
*-------------------------------------------------------------
*
*
* total number of lines in the netlist .............. 1355
* simplistically reduced equivalent fault set size = 1574
* lines from primary input gates ....... 41
* lines from primary output gates ....... 32
* lines from interior gate outputs ...... 514
* lines from ** 259 ** fanout stems ... 768
*
* avg_fanin = 1.95, max_fanin = 5
* avg_fanout = 2.97, max_fanout = 12
*
*
*
*
*
1 1gat inpt 6 0 >sa0 >sa1
2 1f01 from 1gat >sa1
3 1f02 from 1gat >sa1
4 1f03 from 1gat >sa1
5 1f04 from 1gat >sa1
6 1f05 from 1gat >sa1
7 1f06 from 1gat >sa1
8 8gat inpt 6 0 >sa0 >sa1
9 8f01 from 8gat >sa1
10 8f02 from 8gat >sa1
11 8f03 from 8gat >sa1
12 8f04 from 8gat >sa1
13 8f05 from 8gat >sa1
14 8f06 from 8gat >sa1
15 15gat inpt 6 0 >sa0 >sa1
16 15f01 from 15gat >sa1
17 15f02 from 15gat >sa1
18 15f03 from 15gat >sa1
19 15f04 from 15gat >sa1
20 15f05 from 15gat >sa1
21 15f06 from 15gat >sa1
22 22gat inpt 6 0 >sa0 >sa1
23 22f01 from 22gat >sa1
24 22f02 from 22gat >sa1
25 22f03 from 22gat >sa1
26 22f04 from 22gat >sa1
27 22f05 from 22gat >sa1
28 22f06 from 22gat >sa1
29 29gat inpt 6 0 >sa0 >sa1
30 29f01 from 29gat >sa1
31 29f02 from 29gat >sa1
32 29f03 from 29gat >sa1
33 29f04 from 29gat >sa1
34 29f05 from 29gat >sa1
35 29f06 from 29gat >sa1
36 36gat inpt 6 0 >sa0 >sa1
37 36f01 from 36gat >sa1
38 36f02 from 36gat >sa1
39 36f03 from 36gat >sa1
40 36f04 from 36gat >sa1
41 36f05 from 36gat >sa1
42 36f06 from 36gat >sa1
43 43gat inpt 6 0 >sa0 >sa1
44 43f01 from 43gat >sa1
45 43f02 from 43gat >sa1
46 43f03 from 43gat >sa1
47 43f04 from 43gat >sa1
48 43f05 from 43gat >sa1
49 43f06 from 43gat >sa1
50 50gat inpt 6 0 >sa0 >sa1
51 50f01 from 50gat >sa1
52 50f02 from 50gat >sa1
53 50f03 from 50gat >sa1
54 50f04 from 50gat >sa1
55 50f05 from 50gat >sa1
56 50f06 from 50gat >sa1
57 57gat inpt 6 0 >sa0 >sa1
58 57f01 from 57gat >sa1
59 57f02 from 57gat >sa1
60 57f03 from 57gat >sa1
61 57f04 from 57gat >sa1
62 57f05 from 57gat >sa1
63 57f06 from 57gat >sa1
64 64gat inpt 6 0 >sa0 >sa1
65 64f01 from 64gat >sa1
66 64f02 from 64gat >sa1
67 64f03 from 64gat >sa1
68 64f04 from 64gat >sa1
69 64f05 from 64gat >sa1
70 64f06 from 64gat >sa1
71 71gat inpt 6 0 >sa0 >sa1
72 71f01 from 71gat >sa1
73 71f02 from 71gat >sa1
74 71f03 from 71gat >sa1
75 71f04 from 71gat >sa1
76 71f05 from 71gat >sa1
77 71f06 from 71gat >sa1
78 78gat inpt 6 0 >sa0 >sa1
79 78f01 from 78gat >sa1
80 78f02 from 78gat >sa1
81 78f03 from 78gat >sa1
82 78f04 from 78gat >sa1
83 78f05 from 78gat >sa1
84 78f06 from 78gat >sa1
85 85gat inpt 6 0 >sa0 >sa1
86 85f01 from 85gat >sa1
87 85f02 from 85gat >sa1
88 85f03 from 85gat >sa1
89 85f04 from 85gat >sa1
90 85f05 from 85gat >sa1
91 85f06 from 85gat >sa1
92 92gat inpt 6 0 >sa0 >sa1
93 92f01 from 92gat >sa1
94 92f02 from 92gat >sa1
95 92f03 from 92gat >sa1
96 92f04 from 92gat >sa1
97 92f05 from 92gat >sa1
98 92f06 from 92gat >sa1
99 99gat inpt 6 0 >sa0 >sa1
100 99f01 from 99gat >sa1
101 99f02 from 99gat >sa1
102 99f03 from 99gat >sa1
103 99f04 from 99gat >sa1
104 99f05 from 99gat >sa1
105 99f06 from 99gat >sa1
106 106gat inpt 6 0 >sa0 >sa1
107 106f01 from 106gat >sa1
108 106f02 from 106gat >sa1
109 106f03 from 106gat >sa1
110 106f04 from 106gat >sa1
111 106f05 from 106gat >sa1
112 106f06 from 106gat >sa1
113 113gat inpt 6 0 >sa0 >sa1
114 113f01 from 113gat >sa1
115 113f02 from 113gat >sa1
116 113f03 from 113gat >sa1
117 113f04 from 113gat >sa1
118 113f05 from 113gat >sa1
119 113f06 from 113gat >sa1
120 120gat inpt 6 0 >sa0 >sa1
121 120f01 from 120gat >sa1
122 120f02 from 120gat >sa1
123 120f03 from 120gat >sa1
124 120f04 from 120gat >sa1
125 120f05 from 120gat >sa1
126 120f06 from 120gat >sa1
127 127gat inpt 6 0 >sa0 >sa1
128 127f01 from 127gat >sa1
129 127f02 from 127gat >sa1
130 127f03 from 127gat >sa1
131 127f04 from 127gat >sa1
132 127f05 from 127gat >sa1
133 127f06 from 127gat >sa1
134 134gat inpt 6 0 >sa0 >sa1
135 134f01 from 134gat >sa1
136 134f02 from 134gat >sa1
137 134f03 from 134gat >sa1
138 134f04 from 134gat >sa1
139 134f05 from 134gat >sa1
140 134f06 from 134gat >sa1
141 141gat inpt 6 0 >sa0 >sa1
142 141f01 from 141gat >sa1
143 141f02 from 141gat >sa1
144 141f03 from 141gat >sa1
145 141f04 from 141gat >sa1
146 141f05 from 141gat >sa1
147 141f06 from 141gat >sa1
148 148gat inpt 6 0 >sa0 >sa1
149 148f01 from 148gat >sa1
150 148f02 from 148gat >sa1
151 148f03 from 148gat >sa1
152 148f04 from 148gat >sa1
153 148f05 from 148gat >sa1
154 148f06 from 148gat >sa1
155 155gat inpt 6 0 >sa0 >sa1
156 155f01 from 155gat >sa1
157 155f02 from 155gat >sa1
158 155f03 from 155gat >sa1
159 155f04 from 155gat >sa1
160 155f05 from 155gat >sa1
161 155f06 from 155gat >sa1
162 162gat inpt 6 0 >sa0 >sa1
163 162f01 from 162gat >sa1
164 162f02 from 162gat >sa1
165 162f03 from 162gat >sa1
166 162f04 from 162gat >sa1
167 162f05 from 162gat >sa1
168 162f06 from 162gat >sa1
169 169gat inpt 6 0 >sa0 >sa1
170 169f01 from 169gat >sa1
171 169f02 from 169gat >sa1
172 169f03 from 169gat >sa1
173 169f04 from 169gat >sa1
174 169f05 from 169gat >sa1
175 169f06 from 169gat >sa1
176 176gat inpt 6 0 >sa0 >sa1
177 176f01 from 176gat >sa1
178 176f02 from 176gat >sa1
179 176f03 from 176gat >sa1
180 176f04 from 176gat >sa1
181 176f05 from 176gat >sa1
182 176f06 from 176gat >sa1
183 183gat inpt 6 0 >sa0 >sa1
184 183f01 from 183gat >sa1
185 183f02 from 183gat >sa1
186 183f03 from 183gat >sa1
187 183f04 from 183gat >sa1
188 183f05 from 183gat >sa1
189 183f06 from 183gat >sa1
190 190gat inpt 6 0 >sa0 >sa1
191 190f01 from 190gat >sa1
192 190f02 from 190gat >sa1
193 190f03 from 190gat >sa1
194 190f04 from 190gat >sa1
195 190f05 from 190gat >sa1
196 190f06 from 190gat >sa1
197 197gat inpt 6 0 >sa0 >sa1
198 197f01 from 197gat >sa1
199 197f02 from 197gat >sa1
200 197f03 from 197gat >sa1
201 197f04 from 197gat >sa1
202 197f05 from 197gat >sa1
203 197f06 from 197gat >sa1
204 204gat inpt 6 0 >sa0 >sa1
205 204f01 from 204gat >sa1
206 204f02 from 204gat >sa1
207 204f03 from 204gat >sa1
208 204f04 from 204gat >sa1
209 204f05 from 204gat >sa1
210 204f06 from 204gat >sa1
211 211gat inpt 6 0 >sa0 >sa1
212 211f01 from 211gat >sa1
213 211f02 from 211gat >sa1
214 211f03 from 211gat >sa1
215 211f04 from 211gat >sa1
216 211f05 from 211gat >sa1
217 211f06 from 211gat >sa1
218 218gat inpt 6 0 >sa0 >sa1
219 218f01 from 218gat >sa1
220 218f02 from 218gat >sa1
221 218f03 from 218gat >sa1
222 218f04 from 218gat >sa1
223 218f05 from 218gat >sa1
224 218f06 from 218gat >sa1
225 225gat inpt 1 0 >sa1
226 226gat inpt 1 0 >sa1
227 227gat inpt 1 0 >sa1
228 228gat inpt 1 0 >sa1
229 229gat inpt 1 0 >sa1
230 230gat inpt 1 0 >sa1
231 231gat inpt 1 0 >sa1
232 232gat inpt 1 0 >sa1
233 233gat inpt 8 0 >sa0 >sa1
234 233f01 from 233gat >sa1
235 233f02 from 233gat >sa1
236 233f03 from 233gat >sa1
237 233f04 from 233gat >sa1
238 233f05 from 233gat >sa1
239 233f06 from 233gat >sa1
240 233f07 from 233gat >sa1
241 233f08 from 233gat >sa1
242 242gat and 2 2 >sa0 >sa1
225 234
243 242f01 from 242gat >sa1
244 242f02 from 242gat >sa1
245 245gat and 2 2 >sa0 >sa1
226 235
246 245f01 from 245gat >sa1
247 245f02 from 245gat >sa1
248 248gat and 2 2 >sa0 >sa1
227 236
249 248f01 from 248gat >sa1
250 248f02 from 248gat >sa1
251 251gat and 2 2 >sa0 >sa1
228 237
252 251f01 from 251gat >sa1
253 251f02 from 251gat >sa1
254 254gat and 2 2 >sa0 >sa1
229 238
255 254f01 from 254gat >sa1
256 254f02 from 254gat >sa1
257 257gat and 2 2 >sa0 >sa1
230 239
258 257f01 from 257gat >sa1
259 257f02 from 257gat >sa1
260 260gat and 2 2 >sa0 >sa1
231 240
261 260f01 from 260gat >sa1
262 260f02 from 260gat >sa1
263 263gat and 2 2 >sa0 >sa1
232 241
264 263f01 from 263gat >sa1
265 263f02 from 263gat >sa1
266 266gat nand 2 2 >sa0 >sa1
4 11
267 266f01 from 266gat >sa1
268 266f02 from 266gat >sa1
269 269gat nand 2 2 >sa0 >sa1
18 25
270 269f01 from 269gat >sa1
271 269f02 from 269gat >sa1
272 272gat nand 2 2 >sa0 >sa1
32 39
273 272f01 from 272gat >sa1
274 272f02 from 272gat >sa1
275 275gat nand 2 2 >sa0 >sa1
46 53
276 275f01 from 275gat >sa1
277 275f02 from 275gat >sa1
278 278gat nand 2 2 >sa0 >sa1
60 67
279 278f01 from 278gat >sa1
280 278f02 from 278gat >sa1
281 281gat nand 2 2 >sa0 >sa1
74 81
282 281f01 from 281gat >sa1
283 281f02 from 281gat >sa1
284 284gat nand 2 2 >sa0 >sa1
88 95
285 284f01 from 284gat >sa1
286 284f02 from 284gat >sa1
287 287gat nand 2 2 >sa0 >sa1
102 109
288 287f01 from 287gat >sa1
289 287f02 from 287gat >sa1
290 290gat nand 2 2 >sa0 >sa1
116 123
291 290f01 from 290gat >sa1
292 290f02 from 290gat >sa1
293 293gat nand 2 2 >sa0 >sa1
130 137
294 293f01 from 293gat >sa1
295 293f02 from 293gat >sa1
296 296gat nand 2 2 >sa0 >sa1
144 151
297 296f01 from 296gat >sa1
298 296f02 from 296gat >sa1
299 299gat nand 2 2 >sa0 >sa1
158 165
300 299f01 from 299gat >sa1
301 299f02 from 299gat >sa1
302 302gat nand 2 2 >sa0 >sa1
172 179
303 302f01 from 302gat >sa1
304 302f02 from 302gat >sa1
305 305gat nand 2 2 >sa0 >sa1
186 193
306 305f01 from 305gat >sa1
307 305f02 from 305gat >sa1
308 308gat nand 2 2 >sa0 >sa1
200 207
309 308f01 from 308gat >sa1
310 308f02 from 308gat >sa1
311 311gat nand 2 2 >sa0 >sa1
214 221
312 311f01 from 311gat >sa1
313 311f02 from 311gat >sa1
314 314gat nand 2 2 >sa0 >sa1
6 34
315 314f01 from 314gat >sa1
316 314f02 from 314gat >sa1
317 317gat nand 2 2 >sa0 >sa1
62 90
318 317f01 from 317gat >sa1
319 317f02 from 317gat >sa1
320 320gat nand 2 2 >sa0 >sa1
13 41
321 320f01 from 320gat >sa1
322 320f02 from 320gat >sa1
323 323gat nand 2 2 >sa0 >sa1
69 97
324 323f01 from 323gat >sa1
325 323f02 from 323gat >sa1
326 326gat nand 2 2 >sa0 >sa1
20 48
327 326f01 from 326gat >sa1
328 326f02 from 326gat >sa1
329 329gat nand 2 2 >sa0 >sa1
76 104
330 329f01 from 329gat >sa1
331 329f02 from 329gat >sa1
332 332gat nand 2 2 >sa0 >sa1
27 55
333 332f01 from 332gat >sa1
334 332f02 from 332gat >sa1
335 335gat nand 2 2 >sa0 >sa1
83 111
336 335f01 from 335gat >sa1
337 335f02 from 335gat >sa1
338 338gat nand 2 2 >sa0 >sa1
118 146
339 338f01 from 338gat >sa1
340 338f02 from 338gat >sa1
341 341gat nand 2 2 >sa0 >sa1
174 202
342 341f01 from 341gat >sa1
343 341f02 from 341gat >sa1
344 344gat nand 2 2 >sa0 >sa1
125 153
345 344f01 from 344gat >sa1
346 344f02 from 344gat >sa1
347 347gat nand 2 2 >sa0 >sa1
181 209
348 347f01 from 347gat >sa1
349 347f02 from 347gat >sa1
350 350gat nand 2 2 >sa0 >sa1
132 160
351 350f01 from 350gat >sa1
352 350f02 from 350gat >sa1
353 353gat nand 2 2 >sa0 >sa1
188 216
354 353f01 from 353gat >sa1
355 353f02 from 353gat >sa1
356 356gat nand 2 2 >sa0 >sa1
139 167
357 356f01 from 356gat >sa1
358 356f02 from 356gat >sa1
359 359gat nand 2 2 >sa0 >sa1
195 223
360 359f01 from 359gat >sa1
361 359f02 from 359gat >sa1
362 362gat nand 1 2 >sa1
5 267
363 363gat nand 1 2 >sa1
12 268
364 364gat nand 1 2 >sa1
19 270
365 365gat nand 1 2 >sa1
26 271
366 366gat nand 1 2 >sa1
33 273
367 367gat nand 1 2 >sa1
40 274
368 368gat nand 1 2 >sa1
47 276
369 369gat nand 1 2 >sa1
54 277
370 370gat nand 1 2 >sa1
61 279
371 371gat nand 1 2 >sa1
68 280
372 372gat nand 1 2 >sa1
75 282
373 373gat nand 1 2 >sa1
82 283
374 374gat nand 1 2 >sa1
89 285
375 375gat nand 1 2 >sa1
96 286
376 376gat nand 1 2 >sa1
103 288
377 377gat nand 1 2 >sa1
110 289
378 378gat nand 1 2 >sa1
117 291
379 379gat nand 1 2 >sa1
124 292
380 380gat nand 1 2 >sa1
131 294
381 381gat nand 1 2 >sa1
138 295
382 382gat nand 1 2 >sa1
145 297
383 383gat nand 1 2 >sa1
152 298
384 384gat nand 1 2 >sa1
159 300
385 385gat nand 1 2 >sa1
166 301
386 386gat nand 1 2 >sa1
173 303
387 387gat nand 1 2 >sa1
180 304
388 388gat nand 1 2 >sa1
187 306
389 389gat nand 1 2 >sa1
194 307
390 390gat nand 1 2 >sa1
201 309
391 391gat nand 1 2 >sa1
208 310
392 392gat nand 1 2 >sa1
215 312
393 393gat nand 1 2 >sa1
222 313
394 394gat nand 1 2 >sa1
7 315
395 395gat nand 1 2 >sa1
35 316
396 396gat nand 1 2 >sa1
63 318
397 397gat nand 1 2 >sa1
91 319
398 398gat nand 1 2 >sa1
14 321
399 399gat nand 1 2 >sa1
42 322
400 400gat nand 1 2 >sa1
70 324
401 401gat nand 1 2 >sa1
98 325
402 402gat nand 1 2 >sa1
21 327
403 403gat nand 1 2 >sa1
49 328
404 404gat nand 1 2 >sa1
77 330
405 405gat nand 1 2 >sa1
105 331
406 406gat nand 1 2 >sa1
28 333
407 407gat nand 1 2 >sa1
56 334
408 408gat nand 1 2 >sa1
84 336
409 409gat nand 1 2 >sa1
112 337
410 410gat nand 1 2 >sa1
119 339
411 411gat nand 1 2 >sa1
147 340
412 412gat nand 1 2 >sa1
175 342
413 413gat nand 1 2 >sa1
203 343
414 414gat nand 1 2 >sa1
126 345
415 415gat nand 1 2 >sa1
154 346
416 416gat nand 1 2 >sa1
182 348
417 417gat nand 1 2 >sa1
210 349
418 418gat nand 1 2 >sa1
133 351
419 419gat nand 1 2 >sa1
161 352
420 420gat nand 1 2 >sa1
189 354
421 421gat nand 1 2 >sa1
217 355
422 422gat nand 1 2 >sa1
140 357
423 423gat nand 1 2 >sa1
168 358
424 424gat nand 1 2 >sa1
196 360
425 425gat nand 1 2 >sa1
224 361
426 426gat nand 2 2 >sa0 >sa1
362 363
427 426f01 from 426gat >sa1
428 426f02 from 426gat >sa1
429 429gat nand 2 2 >sa0 >sa1
364 365
430 429f01 from 429gat >sa1
431 429f02 from 429gat >sa1
432 432gat nand 2 2 >sa0 >sa1
366 367
433 432f01 from 432gat >sa1
434 432f02 from 432gat >sa1
435 435gat nand 2 2 >sa0 >sa1
368 369
436 435f01 from 435gat >sa1
437 435f02 from 435gat >sa1
438 438gat nand 2 2 >sa0 >sa1
370 371
439 438f01 from 438gat >sa1
440 438f02 from 438gat >sa1
441 441gat nand 2 2 >sa0 >sa1
372 373
442 441f01 from 441gat >sa1
443 441f02 from 441gat >sa1
444 444gat nand 2 2 >sa0 >sa1
374 375
445 444f01 from 444gat >sa1
446 444f02 from 444gat >sa1
447 447gat nand 2 2 >sa0 >sa1
376 377
448 447f01 from 447gat >sa1
449 447f02 from 447gat >sa1
450 450gat nand 2 2 >sa0 >sa1
378 379
451 450f01 from 450gat >sa1
452 450f02 from 450gat >sa1
453 453gat nand 2 2 >sa0 >sa1
380 381
454 453f01 from 453gat >sa1
455 453f02 from 453gat >sa1
456 456gat nand 2 2 >sa0 >sa1
382 383
457 456f01 from 456gat >sa1
458 456f02 from 456gat >sa1
459 459gat nand 2 2 >sa0 >sa1
384 385
460 459f01 from 459gat >sa1
461 459f02 from 459gat >sa1
462 462gat nand 2 2 >sa0 >sa1
386 387
463 462f01 from 462gat >sa1
464 462f02 from 462gat >sa1
465 465gat nand 2 2 >sa0 >sa1
388 389
466 465f01 from 465gat >sa1
467 465f02 from 465gat >sa1
468 468gat nand 2 2 >sa0 >sa1
390 391
469 468f01 from 468gat >sa1
470 468f02 from 468gat >sa1
471 471gat nand 2 2 >sa0 >sa1
392 393
472 471f01 from 471gat >sa1
473 471f02 from 471gat >sa1
474 474gat nand 2 2 >sa0 >sa1
394 395
475 474f01 from 474gat >sa1
476 474f02 from 474gat >sa1
477 477gat nand 2 2 >sa0 >sa1
396 397
478 477f01 from 477gat >sa1
479 477f02 from 477gat >sa1
480 480gat nand 2 2 >sa0 >sa1
398 399
481 480f01 from 480gat >sa1
482 480f02 from 480gat >sa1
483 483gat nand 2 2 >sa0 >sa1
400 401
484 483f01 from 483gat >sa1
485 483f02 from 483gat >sa1
486 486gat nand 2 2 >sa0 >sa1
402 403
487 486f01 from 486gat >sa1
488 486f02 from 486gat >sa1
489 489gat nand 2 2 >sa0 >sa1
404 405
490 489f01 from 489gat >sa1
491 489f02 from 489gat >sa1
492 492gat nand 2 2 >sa0 >sa1
406 407
493 492f01 from 492gat >sa1
494 492f02 from 492gat >sa1
495 495gat nand 2 2 >sa0 >sa1
408 409
496 495f01 from 495gat >sa1
497 495f02 from 495gat >sa1
498 498gat nand 2 2 >sa0 >sa1
410 411
499 498f01 from 498gat >sa1
500 498f02 from 498gat >sa1
501 501gat nand 2 2 >sa0 >sa1
412 413
502 501f01 from 501gat >sa1
503 501f02 from 501gat >sa1
504 504gat nand 2 2 >sa0 >sa1
414 415
505 504f01 from 504gat >sa1
506 504f02 from 504gat >sa1
507 507gat nand 2 2 >sa0 >sa1
416 417
508 507f01 from 507gat >sa1
509 507f02 from 507gat >sa1
510 510gat nand 2 2 >sa0 >sa1
418 419
511 510f01 from 510gat >sa1
512 510f02 from 510gat >sa1
513 513gat nand 2 2 >sa0 >sa1
420 421
514 513f01 from 513gat >sa1
515 513f02 from 513gat >sa1
516 516gat nand 2 2 >sa0 >sa1
422 423
517 516f01 from 516gat >sa1
518 516f02 from 516gat >sa1
519 519gat nand 2 2 >sa0 >sa1
424 425
520 519f01 from 519gat >sa1
521 519f02 from 519gat >sa1
522 522gat nand 2 2 >sa0 >sa1
427 430
523 522f01 from 522gat >sa1
524 522f02 from 522gat >sa1
525 525gat nand 2 2 >sa0 >sa1
433 436
526 525f01 from 525gat >sa1
527 525f02 from 525gat >sa1
528 528gat nand 2 2 >sa0 >sa1
439 442
529 528f01 from 528gat >sa1
530 528f02 from 528gat >sa1
531 531gat nand 2 2 >sa0 >sa1
445 448
532 531f01 from 531gat >sa1
533 531f02 from 531gat >sa1
534 534gat nand 2 2 >sa0 >sa1
451 454
535 534f01 from 534gat >sa1
536 534f02 from 534gat >sa1
537 537gat nand 2 2 >sa0 >sa1
457 460
538 537f01 from 537gat >sa1
539 537f02 from 537gat >sa1
540 540gat nand 2 2 >sa0 >sa1
463 466
541 540f01 from 540gat >sa1
542 540f02 from 540gat >sa1
543 543gat nand 2 2 >sa0 >sa1
469 472
544 543f01 from 543gat >sa1
545 543f02 from 543gat >sa1
546 546gat nand 2 2 >sa0 >sa1
475 478
547 546f01 from 546gat >sa1
548 546f02 from 546gat >sa1
549 549gat nand 2 2 >sa0 >sa1
481 484
550 549f01 from 549gat >sa1
551 549f02 from 549gat >sa1
552 552gat nand 2 2 >sa0 >sa1
487 490
553 552f01 from 552gat >sa1
554 552f02 from 552gat >sa1
555 555gat nand 2 2 >sa0 >sa1
493 496
556 555f01 from 555gat >sa1
557 555f02 from 555gat >sa1
558 558gat nand 2 2 >sa0 >sa1
499 502
559 558f01 from 558gat >sa1
560 558f02 from 558gat >sa1
561 561gat nand 2 2 >sa0 >sa1
505 508
562 561f01 from 561gat >sa1
563 561f02 from 561gat >sa1
564 564gat nand 2 2 >sa0 >sa1
511 514
565 564f01 from 564gat >sa1
566 564f02 from 564gat >sa1
567 567gat nand 2 2 >sa0 >sa1
517 520
568 567f01 from 567gat >sa1
569 567f02 from 567gat >sa1
570 570gat nand 1 2 >sa1
428 523
571 571gat nand 1 2 >sa1
431 524
572 572gat nand 1 2 >sa1
434 526
573 573gat nand 1 2 >sa1
437 527
574 574gat nand 1 2 >sa1
440 529
575 575gat nand 1 2 >sa1
443 530
576 576gat nand 1 2 >sa1
446 532
577 577gat nand 1 2 >sa1
449 533
578 578gat nand 1 2 >sa1
452 535
579 579gat nand 1 2 >sa1
455 536
580 580gat nand 1 2 >sa1
458 538
581 581gat nand 1 2 >sa1
461 539
582 582gat nand 1 2 >sa1
464 541
583 583gat nand 1 2 >sa1
467 542
584 584gat nand 1 2 >sa1
470 544
585 585gat nand 1 2 >sa1
473 545
586 586gat nand 1 2 >sa1
476 547
587 587gat nand 1 2 >sa1
479 548
588 588gat nand 1 2 >sa1
482 550
589 589gat nand 1 2 >sa1
485 551
590 590gat nand 1 2 >sa1
488 553
591 591gat nand 1 2 >sa1
491 554
592 592gat nand 1 2 >sa1
494 556
593 593gat nand 1 2 >sa1
497 557
594 594gat nand 1 2 >sa1
500 559
595 595gat nand 1 2 >sa1
503 560
596 596gat nand 1 2 >sa1
506 562
597 597gat nand 1 2 >sa1
509 563
598 598gat nand 1 2 >sa1
512 565
599 599gat nand 1 2 >sa1
515 566
600 600gat nand 1 2 >sa1
518 568
601 601gat nand 1 2 >sa1
521 569
602 602gat nand 4 2 >sa0 >sa1
570 571
603 602f01 from 602gat >sa1
604 602f02 from 602gat >sa1
605 602f03 from 602gat >sa1
606 602f04 from 602gat >sa1
607 607gat nand 4 2 >sa0 >sa1
572 573
608 607f01 from 607gat >sa1
609 607f02 from 607gat >sa1
610 607f03 from 607gat >sa1
611 607f04 from 607gat >sa1
612 612gat nand 4 2 >sa0 >sa1
574 575
613 612f01 from 612gat >sa1
614 612f02 from 612gat >sa1
615 612f03 from 612gat >sa1
616 612f04 from 612gat >sa1
617 617gat nand 4 2 >sa0 >sa1
576 577
618 617f01 from 617gat >sa1
619 617f02 from 617gat >sa1
620 617f03 from 617gat >sa1
621 617f04 from 617gat >sa1
622 622gat nand 4 2 >sa0 >sa1
578 579
623 622f01 from 622gat >sa1
624 622f02 from 622gat >sa1
625 622f03 from 622gat >sa1
626 622f04 from 622gat >sa1
627 627gat nand 4 2 >sa0 >sa1
580 581
628 627f01 from 627gat >sa1
629 627f02 from 627gat >sa1
630 627f03 from 627gat >sa1
631 627f04 from 627gat >sa1
632 632gat nand 4 2 >sa0 >sa1
582 583
633 632f01 from 632gat >sa1
634 632f02 from 632gat >sa1
635 632f03 from 632gat >sa1
636 632f04 from 632gat >sa1
637 637gat nand 4 2 >sa0 >sa1
584 585
638 637f01 from 637gat >sa1
639 637f02 from 637gat >sa1
640 637f03 from 637gat >sa1
641 637f04 from 637gat >sa1
642 642gat nand 2 2 >sa0 >sa1
586 587
643 642f01 from 642gat >sa1
644 642f02 from 642gat >sa1
645 645gat nand 2 2 >sa0 >sa1
588 589
646 645f01 from 645gat >sa1
647 645f02 from 645gat >sa1
648 648gat nand 2 2 >sa0 >sa1
590 591
649 648f01 from 648gat >sa1
650 648f02 from 648gat >sa1
651 651gat nand 2 2 >sa0 >sa1
592 593
652 651f01 from 651gat >sa1
653 651f02 from 651gat >sa1
654 654gat nand 2 2 >sa0 >sa1
594 595
655 654f01 from 654gat >sa1
656 654f02 from 654gat >sa1
657 657gat nand 2 2 >sa0 >sa1
596 597
658 657f01 from 657gat >sa1
659 657f02 from 657gat >sa1
660 660gat nand 2 2 >sa0 >sa1
598 599
661 660f01 from 660gat >sa1
662 660f02 from 660gat >sa1
663 663gat nand 2 2 >sa0 >sa1
600 601
664 663f01 from 663gat >sa1
665 663f02 from 663gat >sa1
666 666gat nand 2 2 >sa0 >sa1
603 608
667 666f01 from 666gat >sa1
668 666f02 from 666gat >sa1
669 669gat nand 2 2 >sa0 >sa1
613 618
670 669f01 from 669gat >sa1
671 669f02 from 669gat >sa1
672 672gat nand 2 2 >sa0 >sa1
605 615
673 672f01 from 672gat >sa1
674 672f02 from 672gat >sa1
675 675gat nand 2 2 >sa0 >sa1
610 620
676 675f01 from 675gat >sa1
677 675f02 from 675gat >sa1
678 678gat nand 2 2 >sa0 >sa1
623 628
679 678f01 from 678gat >sa1
680 678f02 from 678gat >sa1
681 681gat nand 2 2 >sa0 >sa1
633 638
682 681f01 from 681gat >sa1
683 681f02 from 681gat >sa1
684 684gat nand 2 2 >sa0 >sa1
625 635
685 684f01 from 684gat >sa1
686 684f02 from 684gat >sa1
687 687gat nand 2 2 >sa0 >sa1
630 640
688 687f01 from 687gat >sa1
689 687f02 from 687gat >sa1
690 690gat nand 1 2 >sa1
604 667
691 691gat nand 1 2 >sa1
609 668
692 692gat nand 1 2 >sa1
614 670
693 693gat nand 1 2 >sa1
619 671
694 694gat nand 1 2 >sa1
606 673
695 695gat nand 1 2 >sa1
616 674
696 696gat nand 1 2 >sa1
611 676
697 697gat nand 1 2 >sa1
621 677
698 698gat nand 1 2 >sa1
624 679
699 699gat nand 1 2 >sa1
629 680
700 700gat nand 1 2 >sa1
634 682
701 701gat nand 1 2 >sa1
639 683
702 702gat nand 1 2 >sa1
626 685
703 703gat nand 1 2 >sa1
636 686
704 704gat nand 1 2 >sa1
631 688
705 705gat nand 1 2 >sa1
641 689
706 706gat nand 2 2 >sa0 >sa1
690 691
707 706f01 from 706gat >sa1
708 706f02 from 706gat >sa1
709 709gat nand 2 2 >sa0 >sa1
692 693
710 709f01 from 709gat >sa1
711 709f02 from 709gat >sa1
712 712gat nand 2 2 >sa0 >sa1
694 695
713 712f01 from 712gat >sa1
714 712f02 from 712gat >sa1
715 715gat nand 2 2 >sa0 >sa1
696 697
716 715f01 from 715gat >sa1
717 715f02 from 715gat >sa1
718 718gat nand 2 2 >sa0 >sa1
698 699
719 718f01 from 718gat >sa1
720 718f02 from 718gat >sa1
721 721gat nand 2 2 >sa0 >sa1
700 701
722 721f01 from 721gat >sa1
723 721f02 from 721gat >sa1
724 724gat nand 2 2 >sa0 >sa1
702 703
725 724f01 from 724gat >sa1
726 724f02 from 724gat >sa1
727 727gat nand 2 2 >sa0 >sa1
704 705
728 727f01 from 727gat >sa1
729 727f02 from 727gat >sa1
730 730gat nand 2 2 >sa0 >sa1
243 719
731 730f01 from 730gat >sa1
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734 733f01 from 733gat >sa1
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746 745f01 from 745gat >sa1
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723 735
758 758gat nand 1 2 >sa1
250 737
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786 785f01 from 785gat >sa1
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789 788f01 from 788gat >sa1
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768 769
792 791f01 from 791gat >sa1
793 791f02 from 791gat >sa1
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795 794f01 from 794gat >sa1
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807 806f01 from 806gat >sa1
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810 809f01 from 809gat >sa1
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813 812f01 from 812gat >sa1
814 812f02 from 812gat >sa1
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816 815f01 from 815gat >sa1
817 815f02 from 815gat >sa1
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819 819gat nand 1 2 >sa1
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820 820gat nand 1 2 >sa1
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775 799
822 822gat nand 1 2 >sa1
650 801
823 823gat nand 1 2 >sa1
778 802
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825 825gat nand 1 2 >sa1
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826 826gat nand 1 2 >sa1
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827 827gat nand 1 2 >sa1
784 808
828 828gat nand 1 2 >sa1
659 810
829 829gat nand 1 2 >sa1
787 811
830 830gat nand 1 2 >sa1
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835 834f01 from 834gat
836 834f02 from 834gat
837 834f03 from 834gat
838 834f04 from 834gat
839 834f05 from 834gat
840 834f06 from 834gat >sa1
841 834f07 from 834gat >sa1
842 834f08 from 834gat >sa1
843 834f09 from 834gat >sa1
844 834f10 from 834gat >sa1
845 834f11 from 834gat >sa1
846 834f12 from 834gat >sa1
847 847gat nand 12 2 >sa0 >sa1
820 821
848 847f01 from 847gat
849 847f02 from 847gat
850 847f03 from 847gat
851 847f04 from 847gat
852 847f05 from 847gat
853 847f06 from 847gat >sa1
854 847f07 from 847gat >sa1
855 847f08 from 847gat >sa1
856 847f09 from 847gat >sa1
857 847f10 from 847gat >sa1
858 847f11 from 847gat >sa1
859 847f12 from 847gat >sa1
860 860gat nand 12 2 >sa0 >sa1
822 823
861 860f01 from 860gat
862 860f02 from 860gat
863 860f03 from 860gat
864 860f04 from 860gat
865 860f05 from 860gat
866 860f06 from 860gat >sa1
867 860f07 from 860gat >sa1
868 860f08 from 860gat >sa1
869 860f09 from 860gat >sa1
870 860f10 from 860gat >sa1
871 860f11 from 860gat >sa1
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873 873gat nand 12 2 >sa0 >sa1
824 825
874 873f01 from 873gat
875 873f02 from 873gat
876 873f03 from 873gat
877 873f04 from 873gat
878 873f05 from 873gat
879 873f06 from 873gat >sa1
880 873f07 from 873gat >sa1
881 873f08 from 873gat >sa1
882 873f09 from 873gat >sa1
883 873f10 from 873gat >sa1
884 873f11 from 873gat >sa1
885 873f12 from 873gat >sa1
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828 829
887 886f01 from 886gat
888 886f02 from 886gat
889 886f03 from 886gat
890 886f04 from 886gat
891 886f05 from 886gat
892 886f06 from 886gat >sa1
893 886f07 from 886gat >sa1
894 886f08 from 886gat >sa1
895 886f09 from 886gat >sa1
896 886f10 from 886gat >sa1
897 886f11 from 886gat >sa1
898 886f12 from 886gat >sa1
899 899gat nand 12 2 >sa0 >sa1
832 833
900 899f01 from 899gat
901 899f02 from 899gat
902 899f03 from 899gat
903 899f04 from 899gat
904 899f05 from 899gat
905 899f06 from 899gat >sa1
906 899f07 from 899gat >sa1
907 899f08 from 899gat >sa1
908 899f09 from 899gat >sa1
909 899f10 from 899gat >sa1
910 899f11 from 899gat >sa1
911 899f12 from 899gat >sa1
912 912gat nand 12 2 >sa0 >sa1
830 831
913 912f01 from 912gat
914 912f02 from 912gat
915 912f03 from 912gat
916 912f04 from 912gat
917 912f05 from 912gat
918 912f06 from 912gat >sa1
919 912f07 from 912gat >sa1
920 912f08 from 912gat >sa1
921 912f09 from 912gat >sa1
922 912f10 from 912gat >sa1
923 912f11 from 912gat >sa1
924 912f12 from 912gat >sa1
925 925gat nand 12 2 >sa0 >sa1
826 827
926 925f01 from 925gat
927 925f02 from 925gat
928 925f03 from 925gat
929 925f04 from 925gat
930 925f05 from 925gat
931 925f06 from 925gat >sa1
932 925f07 from 925gat >sa1
933 925f08 from 925gat >sa1
934 925f09 from 925gat >sa1
935 925f10 from 925gat >sa1
936 925f11 from 925gat >sa1
937 925f12 from 925gat >sa1
938 938gat not 1 1 >sa1
835
939 939gat not 1 1 >sa1
848
940 940gat not 1 1 >sa1
861
941 941gat not 1 1 >sa1
836
942 942gat not 1 1 >sa1
849
943 943gat not 1 1 >sa1
874
944 944gat not 1 1 >sa1
837
945 945gat not 1 1 >sa1
862
946 946gat not 1 1 >sa1
875
947 947gat not 1 1 >sa1
850
948 948gat not 1 1 >sa1
863
949 949gat not 1 1 >sa1
876
950 950gat not 1 1 >sa1
887
951 951gat not 1 1 >sa1
900
952 952gat not 1 1 >sa1
888
953 953gat not 1 1 >sa1
913
954 954gat not 1 1 >sa1
926
955 955gat not 1 1 >sa1
901
956 956gat not 1 1 >sa1
927
957 957gat not 1 1 >sa1
914
958 958gat not 1 1 >sa1
928
959 959gat not 1 1 >sa1
889
960 960gat not 1 1 >sa1
915
961 961gat not 1 1 >sa1
929
962 962gat not 1 1 >sa1
890
963 963gat not 1 1 >sa1
902
964 964gat not 1 1 >sa1
930
965 965gat not 1 1 >sa1
916
966 966gat not 1 1 >sa1
903
967 967gat not 1 1 >sa1
891
968 968gat not 1 1 >sa1
917
969 969gat not 1 1 >sa1
904
970 970gat not 1 1 >sa1
851
971 971gat not 1 1 >sa1
877
972 972gat not 1 1 >sa1
852
973 973gat not 1 1 >sa1
864
974 974gat not 1 1 >sa1
838
975 975gat not 1 1 >sa1
878
976 976gat not 1 1 >sa1
839
977 977gat not 1 1 >sa1
865
978 978gat and 1 4 >sa0
938 939 940 879
979 979gat and 1 4 >sa0
941 942 866 943
980 980gat and 1 4 >sa0
944 853 945 946
981 981gat and 1 4 >sa0
840 947 948 949
982 982gat and 1 4 >sa0
958 959 960 905
983 983gat and 1 4 >sa0
961 962 918 963
984 984gat and 1 4 >sa0
964 892 965 966
985 985gat and 1 4 >sa0
931 967 968 969
986 986gat or 4 4 >sa0 >sa1
978 979 980 981
987 986f01 from 986gat >sa1
988 986f02 from 986gat >sa1
989 986f03 from 986gat >sa1
990 986f04 from 986gat >sa1
991 991gat or 4 4 >sa0 >sa1
982 983 984 985
992 991f01 from 991gat >sa1
993 991f02 from 991gat >sa1
994 991f03 from 991gat >sa1
995 991f04 from 991gat >sa1
996 996gat and 4 5 >sa0 >sa1
932 950 919 951 987
997 996f01 from 996gat >sa1
998 996f02 from 996gat >sa1
999 996f03 from 996gat >sa1
1000 996f04 from 996gat >sa1
1001 1001gat and 4 5 >sa0 >sa1
933 952 953 906 988
1002 1001f01 from 1001gat >sa1
1003 1001f02 from 1001gat >sa1
1004 1001f03 from 1001gat >sa1
1005 1001f04 from 1001gat >sa1
1006 1006gat and 4 5 >sa0 >sa1
954 893 920 955 989
1007 1006f01 from 1006gat >sa1
1008 1006f02 from 1006gat >sa1
1009 1006f03 from 1006gat >sa1
1010 1006f04 from 1006gat >sa1
1011 1011gat and 4 5 >sa0 >sa1
956 894 957 907 990
1012 1011f01 from 1011gat >sa1
1013 1011f02 from 1011gat >sa1
1014 1011f03 from 1011gat >sa1
1015 1011f04 from 1011gat >sa1
1016 1016gat and 4 5 >sa0 >sa1
841 970 867 971 992
1017 1016f01 from 1016gat >sa1
1018 1016f02 from 1016gat >sa1
1019 1016f03 from 1016gat >sa1
1020 1016f04 from 1016gat >sa1
1021 1021gat and 4 5 >sa0 >sa1
842 972 973 880 993
1022 1021f01 from 1021gat >sa1
1023 1021f02 from 1021gat >sa1
1024 1021f03 from 1021gat >sa1
1025 1021f04 from 1021gat >sa1
1026 1026gat and 4 5 >sa0 >sa1
974 854 868 975 994
1027 1026f01 from 1026gat >sa1
1028 1026f02 from 1026gat >sa1
1029 1026f03 from 1026gat >sa1
1030 1026f04 from 1026gat >sa1
1031 1031gat and 4 5 >sa0 >sa1
976 855 977 881 995
1032 1031f01 from 1031gat >sa1
1033 1031f02 from 1031gat >sa1
1034 1031f03 from 1031gat >sa1
1035 1031f04 from 1031gat >sa1
1036 1036gat and 2 2 >sa0 >sa1
843 997
1037 1036f01 from 1036gat >sa1
1038 1036f02 from 1036gat >sa1
1039 1039gat and 2 2 >sa0 >sa1
856 998
1040 1039f01 from 1039gat >sa1
1041 1039f02 from 1039gat >sa1
1042 1042gat and 2 2 >sa0 >sa1
869 999
1043 1042f01 from 1042gat >sa1
1044 1042f02 from 1042gat >sa1
1045 1045gat and 2 2 >sa0 >sa1
882 1000
1046 1045f01 from 1045gat >sa1
1047 1045f02 from 1045gat >sa1
1048 1048gat and 2 2 >sa0 >sa1
844 1002
1049 1048f01 from 1048gat >sa1
1050 1048f02 from 1048gat >sa1
1051 1051gat and 2 2 >sa0 >sa1
857 1003
1052 1051f01 from 1051gat >sa1
1053 1051f02 from 1051gat >sa1
1054 1054gat and 2 2 >sa0 >sa1
870 1004
1055 1054f01 from 1054gat >sa1
1056 1054f02 from 1054gat >sa1
1057 1057gat and 2 2 >sa0 >sa1
883 1005
1058 1057f01 from 1057gat >sa1
1059 1057f02 from 1057gat >sa1
1060 1060gat and 2 2 >sa0 >sa1
845 1007
1061 1060f01 from 1060gat >sa1
1062 1060f02 from 1060gat >sa1
1063 1063gat and 2 2 >sa0 >sa1
858 1008
1064 1063f01 from 1063gat >sa1
1065 1063f02 from 1063gat >sa1
1066 1066gat and 2 2 >sa0 >sa1
871 1009
1067 1066f01 from 1066gat >sa1
1068 1066f02 from 1066gat >sa1
1069 1069gat and 2 2 >sa0 >sa1
884 1010
1070 1069f01 from 1069gat >sa1
1071 1069f02 from 1069gat >sa1
1072 1072gat and 2 2 >sa0 >sa1
846 1012
1073 1072f01 from 1072gat >sa1
1074 1072f02 from 1072gat >sa1
1075 1075gat and 2 2 >sa0 >sa1
859 1013
1076 1075f01 from 1075gat >sa1
1077 1075f02 from 1075gat >sa1
1078 1078gat and 2 2 >sa0 >sa1
872 1014
1079 1078f01 from 1078gat >sa1
1080 1078f02 from 1078gat >sa1
1081 1081gat and 2 2 >sa0 >sa1
885 1015
1082 1081f01 from 1081gat >sa1
1083 1081f02 from 1081gat >sa1
1084 1084gat and 2 2 >sa0 >sa1
934 1017
1085 1084f01 from 1084gat >sa1
1086 1084f02 from 1084gat >sa1
1087 1087gat and 2 2 >sa0 >sa1
895 1018
1088 1087f01 from 1087gat >sa1
1089 1087f02 from 1087gat >sa1
1090 1090gat and 2 2 >sa0 >sa1
921 1019
1091 1090f01 from 1090gat >sa1
1092 1090f02 from 1090gat >sa1
1093 1093gat and 2 2 >sa0 >sa1
908 1020
1094 1093f01 from 1093gat >sa1
1095 1093f02 from 1093gat >sa1
1096 1096gat and 2 2 >sa0 >sa1
935 1022
1097 1096f01 from 1096gat >sa1
1098 1096f02 from 1096gat >sa1
1099 1099gat and 2 2 >sa0 >sa1
896 1023
1100 1099f01 from 1099gat >sa1
1101 1099f02 from 1099gat >sa1
1102 1102gat and 2 2 >sa0 >sa1
922 1024
1103 1102f01 from 1102gat >sa1
1104 1102f02 from 1102gat >sa1
1105 1105gat and 2 2 >sa0 >sa1
909 1025
1106 1105f01 from 1105gat >sa1
1107 1105f02 from 1105gat >sa1
1108 1108gat and 2 2 >sa0 >sa1
936 1027
1109 1108f01 from 1108gat >sa1
1110 1108f02 from 1108gat >sa1
1111 1111gat and 2 2 >sa0 >sa1
897 1028
1112 1111f01 from 1111gat >sa1
1113 1111f02 from 1111gat >sa1
1114 1114gat and 2 2 >sa0 >sa1
923 1029
1115 1114f01 from 1114gat >sa1
1116 1114f02 from 1114gat >sa1
1117 1117gat and 2 2 >sa0 >sa1
910 1030
1118 1117f01 from 1117gat >sa1
1119 1117f02 from 1117gat >sa1
1120 1120gat and 2 2 >sa0 >sa1
937 1032
1121 1120f01 from 1120gat >sa1
1122 1120f02 from 1120gat >sa1
1123 1123gat and 2 2 >sa0 >sa1
898 1033
1124 1123f01 from 1123gat >sa1
1125 1123f02 from 1123gat >sa1
1126 1126gat and 2 2 >sa0 >sa1
924 1034
1127 1126f01 from 1126gat >sa1
1128 1126f02 from 1126gat >sa1
1129 1129gat and 2 2 >sa0 >sa1
911 1035
1130 1129f01 from 1129gat >sa1
1131 1129f02 from 1129gat >sa1
1132 1132gat nand 2 2 >sa0 >sa1
2 1037
1133 1132f01 from 1132gat >sa1
1134 1132f02 from 1132gat >sa1
1135 1135gat nand 2 2 >sa0 >sa1
9 1040
1136 1135f01 from 1135gat >sa1
1137 1135f02 from 1135gat >sa1
1138 1138gat nand 2 2 >sa0 >sa1
16 1043
1139 1138f01 from 1138gat >sa1
1140 1138f02 from 1138gat >sa1
1141 1141gat nand 2 2 >sa0 >sa1
23 1046
1142 1141f01 from 1141gat >sa1
1143 1141f02 from 1141gat >sa1
1144 1144gat nand 2 2 >sa0 >sa1
30 1049
1145 1144f01 from 1144gat >sa1
1146 1144f02 from 1144gat >sa1
1147 1147gat nand 2 2 >sa0 >sa1
37 1052
1148 1147f01 from 1147gat >sa1
1149 1147f02 from 1147gat >sa1
1150 1150gat nand 2 2 >sa0 >sa1
44 1055
1151 1150f01 from 1150gat >sa1
1152 1150f02 from 1150gat >sa1
1153 1153gat nand 2 2 >sa0 >sa1
51 1058
1154 1153f01 from 1153gat >sa1
1155 1153f02 from 1153gat >sa1
1156 1156gat nand 2 2 >sa0 >sa1
58 1061
1157 1156f01 from 1156gat >sa1
1158 1156f02 from 1156gat >sa1
1159 1159gat nand 2 2 >sa0 >sa1
65 1064
1160 1159f01 from 1159gat >sa1
1161 1159f02 from 1159gat >sa1
1162 1162gat nand 2 2 >sa0 >sa1
72 1067
1163 1162f01 from 1162gat >sa1
1164 1162f02 from 1162gat >sa1
1165 1165gat nand 2 2 >sa0 >sa1
79 1070
1166 1165f01 from 1165gat >sa1
1167 1165f02 from 1165gat >sa1
1168 1168gat nand 2 2 >sa0 >sa1
86 1073
1169 1168f01 from 1168gat >sa1
1170 1168f02 from 1168gat >sa1
1171 1171gat nand 2 2 >sa0 >sa1
93 1076
1172 1171f01 from 1171gat >sa1
1173 1171f02 from 1171gat >sa1
1174 1174gat nand 2 2 >sa0 >sa1
100 1079
1175 1174f01 from 1174gat >sa1
1176 1174f02 from 1174gat >sa1
1177 1177gat nand 2 2 >sa0 >sa1
107 1082
1178 1177f01 from 1177gat >sa1
1179 1177f02 from 1177gat >sa1
1180 1180gat nand 2 2 >sa0 >sa1
114 1085
1181 1180f01 from 1180gat >sa1
1182 1180f02 from 1180gat >sa1
1183 1183gat nand 2 2 >sa0 >sa1
121 1088
1184 1183f01 from 1183gat >sa1
1185 1183f02 from 1183gat >sa1
1186 1186gat nand 2 2 >sa0 >sa1
128 1091
1187 1186f01 from 1186gat >sa1
1188 1186f02 from 1186gat >sa1
1189 1189gat nand 2 2 >sa0 >sa1
135 1094
1190 1189f01 from 1189gat >sa1
1191 1189f02 from 1189gat >sa1
1192 1192gat nand 2 2 >sa0 >sa1
142 1097
1193 1192f01 from 1192gat >sa1
1194 1192f02 from 1192gat >sa1
1195 1195gat nand 2 2 >sa0 >sa1
149 1100
1196 1195f01 from 1195gat >sa1
1197 1195f02 from 1195gat >sa1
1198 1198gat nand 2 2 >sa0 >sa1
156 1103
1199 1198f01 from 1198gat >sa1
1200 1198f02 from 1198gat >sa1
1201 1201gat nand 2 2 >sa0 >sa1
163 1106
1202 1201f01 from 1201gat >sa1
1203 1201f02 from 1201gat >sa1
1204 1204gat nand 2 2 >sa0 >sa1
170 1109
1205 1204f01 from 1204gat >sa1
1206 1204f02 from 1204gat >sa1
1207 1207gat nand 2 2 >sa0 >sa1
177 1112
1208 1207f01 from 1207gat >sa1
1209 1207f02 from 1207gat >sa1
1210 1210gat nand 2 2 >sa0 >sa1
184 1115
1211 1210f01 from 1210gat >sa1
1212 1210f02 from 1210gat >sa1
1213 1213gat nand 2 2 >sa0 >sa1
191 1118
1214 1213f01 from 1213gat >sa1
1215 1213f02 from 1213gat >sa1
1216 1216gat nand 2 2 >sa0 >sa1
198 1121
1217 1216f01 from 1216gat >sa1
1218 1216f02 from 1216gat >sa1
1219 1219gat nand 2 2 >sa0 >sa1
205 1124
1220 1219f01 from 1219gat >sa1
1221 1219f02 from 1219gat >sa1
1222 1222gat nand 2 2 >sa0 >sa1
212 1127
1223 1222f01 from 1222gat >sa1
1224 1222f02 from 1222gat >sa1
1225 1225gat nand 2 2 >sa0 >sa1
219 1130
1226 1225f01 from 1225gat >sa1
1227 1225f02 from 1225gat >sa1
1228 1228gat nand 1 2 >sa1
3 1133
1229 1229gat nand 1 2 >sa1
1038 1134
1230 1230gat nand 1 2 >sa1
10 1136
1231 1231gat nand 1 2 >sa1
1041 1137
1232 1232gat nand 1 2 >sa1
17 1139
1233 1233gat nand 1 2 >sa1
1044 1140
1234 1234gat nand 1 2 >sa1
24 1142
1235 1235gat nand 1 2 >sa1
1047 1143
1236 1236gat nand 1 2 >sa1
31 1145
1237 1237gat nand 1 2 >sa1
1050 1146
1238 1238gat nand 1 2 >sa1
38 1148
1239 1239gat nand 1 2 >sa1
1053 1149
1240 1240gat nand 1 2 >sa1
45 1151
1241 1241gat nand 1 2 >sa1
1056 1152
1242 1242gat nand 1 2 >sa1
52 1154
1243 1243gat nand 1 2 >sa1
1059 1155
1244 1244gat nand 1 2 >sa1
59 1157
1245 1245gat nand 1 2 >sa1
1062 1158
1246 1246gat nand 1 2 >sa1
66 1160
1247 1247gat nand 1 2 >sa1
1065 1161
1248 1248gat nand 1 2 >sa1
73 1163
1249 1249gat nand 1 2 >sa1
1068 1164
1250 1250gat nand 1 2 >sa1
80 1166
1251 1251gat nand 1 2 >sa1
1071 1167
1252 1252gat nand 1 2 >sa1
87 1169
1253 1253gat nand 1 2 >sa1
1074 1170
1254 1254gat nand 1 2 >sa1
94 1172
1255 1255gat nand 1 2 >sa1
1077 1173
1256 1256gat nand 1 2 >sa1
101 1175
1257 1257gat nand 1 2 >sa1
1080 1176
1258 1258gat nand 1 2 >sa1
108 1178
1259 1259gat nand 1 2 >sa1
1083 1179
1260 1260gat nand 1 2 >sa1
115 1181
1261 1261gat nand 1 2 >sa1
1086 1182
1262 1262gat nand 1 2 >sa1
122 1184
1263 1263gat nand 1 2 >sa1
1089 1185
1264 1264gat nand 1 2 >sa1
129 1187
1265 1265gat nand 1 2 >sa1
1092 1188
1266 1266gat nand 1 2 >sa1
136 1190
1267 1267gat nand 1 2 >sa1
1095 1191
1268 1268gat nand 1 2 >sa1
143 1193
1269 1269gat nand 1 2 >sa1
1098 1194
1270 1270gat nand 1 2 >sa1
150 1196
1271 1271gat nand 1 2 >sa1
1101 1197
1272 1272gat nand 1 2 >sa1
157 1199
1273 1273gat nand 1 2 >sa1
1104 1200
1274 1274gat nand 1 2 >sa1
164 1202
1275 1275gat nand 1 2 >sa1
1107 1203
1276 1276gat nand 1 2 >sa1
171 1205
1277 1277gat nand 1 2 >sa1
1110 1206
1278 1278gat nand 1 2 >sa1
178 1208
1279 1279gat nand 1 2 >sa1
1113 1209
1280 1280gat nand 1 2 >sa1
185 1211
1281 1281gat nand 1 2 >sa1
1116 1212
1282 1282gat nand 1 2 >sa1
192 1214
1283 1283gat nand 1 2 >sa1
1119 1215
1284 1284gat nand 1 2 >sa1
199 1217
1285 1285gat nand 1 2 >sa1
1122 1218
1286 1286gat nand 1 2 >sa1
206 1220
1287 1287gat nand 1 2 >sa1
1125 1221
1288 1288gat nand 1 2 >sa1
213 1223
1289 1289gat nand 1 2 >sa1
1128 1224
1290 1290gat nand 1 2 >sa1
220 1226
1291 1291gat nand 1 2 >sa1
1131 1227
1292 1292gat nand 1 2
1228 1229
1293 1293gat nand 1 2
1230 1231
1294 1294gat nand 1 2
1232 1233
1295 1295gat nand 1 2
1234 1235
1296 1296gat nand 1 2
1236 1237
1297 1297gat nand 1 2
1238 1239
1298 1298gat nand 1 2
1240 1241
1299 1299gat nand 1 2
1242 1243
1300 1300gat nand 1 2
1244 1245
1301 1301gat nand 1 2
1246 1247
1302 1302gat nand 1 2
1248 1249
1303 1303gat nand 1 2
1250 1251
1304 1304gat nand 1 2
1252 1253
1305 1305gat nand 1 2
1254 1255
1306 1306gat nand 1 2
1256 1257
1307 1307gat nand 1 2
1258 1259
1308 1308gat nand 1 2
1260 1261
1309 1309gat nand 1 2
1262 1263
1310 1310gat nand 1 2
1264 1265
1311 1311gat nand 1 2
1266 1267
1312 1312gat nand 1 2
1268 1269
1313 1313gat nand 1 2
1270 1271
1314 1314gat nand 1 2
1272 1273
1315 1315gat nand 1 2
1274 1275
1316 1316gat nand 1 2
1276 1277
1317 1317gat nand 1 2
1278 1279
1318 1318gat nand 1 2
1280 1281
1319 1319gat nand 1 2
1282 1283
1320 1320gat nand 1 2
1284 1285
1321 1321gat nand 1 2
1286 1287
1322 1322gat nand 1 2
1288 1289
1323 1323gat nand 1 2
1290 1291
1324 1324gat buff 0 1 >sa0 >sa1
1292
1325 1325gat buff 0 1 >sa0 >sa1
1293
1326 1326gat buff 0 1 >sa0 >sa1
1294
1327 1327gat buff 0 1 >sa0 >sa1
1295
1328 1328gat buff 0 1 >sa0 >sa1
1296
1329 1329gat buff 0 1 >sa0 >sa1
1297
1330 1330gat buff 0 1 >sa0 >sa1
1298
1331 1331gat buff 0 1 >sa0 >sa1
1299
1332 1332gat buff 0 1 >sa0 >sa1
1300
1333 1333gat buff 0 1 >sa0 >sa1
1301
1334 1334gat buff 0 1 >sa0 >sa1
1302
1335 1335gat buff 0 1 >sa0 >sa1
1303
1336 1336gat buff 0 1 >sa0 >sa1
1304
1337 1337gat buff 0 1 >sa0 >sa1
1305
1338 1338gat buff 0 1 >sa0 >sa1
1306
1339 1339gat buff 0 1 >sa0 >sa1
1307
1340 1340gat buff 0 1 >sa0 >sa1
1308
1341 1341gat buff 0 1 >sa0 >sa1
1309
1342 1342gat buff 0 1 >sa0 >sa1
1310
1343 1343gat buff 0 1 >sa0 >sa1
1311
1344 1344gat buff 0 1 >sa0 >sa1
1312
1345 1345gat buff 0 1 >sa0 >sa1
1313
1346 1346gat buff 0 1 >sa0 >sa1
1314
1347 1347gat buff 0 1 >sa0 >sa1
1315
1348 1348gat buff 0 1 >sa0 >sa1
1316
1349 1349gat buff 0 1 >sa0 >sa1
1317
1350 1350gat buff 0 1 >sa0 >sa1
1318
1351 1351gat buff 0 1 >sa0 >sa1
1319
1352 1352gat buff 0 1 >sa0 >sa1
1320
1353 1353gat buff 0 1 >sa0 >sa1
1321
1354 1354gat buff 0 1 >sa0 >sa1
1322
1355 1355gat buff 0 1 >sa0 >sa1
1323
|
Added c1355.tests.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 | 1:1000 1000 0000 0000 0000 0000 0000 0000 1000 1001 1 2:0100 0000 0000 0000 0000 0000 0000 0000 1111 1111 0 3:0010 0101 0101 0000 0000 0101 0101 0000 0000 0000 1 4:0001 1010 1010 0000 0000 1010 1010 0000 0000 0000 1 5:0110 1110 0110 0110 0000 0000 0000 0000 0000 0000 1 6:0000 0100 0000 0000 0110 0110 0110 0110 0000 0000 1 7:0000 0010 0000 0000 1000 1000 1000 1000 0000 0000 1 8:0000 0001 1000 0000 0000 0000 0000 0000 1000 0110 1 9:0000 0000 1000 0000 0000 1000 0000 0000 1001 1000 1 10:0000 0000 0100 0000 0000 0000 1000 0000 0110 1000 1 11:0000 1000 0010 0000 0000 0000 0000 0000 1000 1001 1 12:0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 1 13:0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 1 14:0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 1 15:0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 1 16:0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 1 17:1000 1000 1000 1000 1000 0000 0000 0000 0000 0000 1 18:0000 0000 0000 0000 0100 0000 0000 0000 0000 0000 1 19:0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 1 20:0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 1 21:0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 1 22:0000 0000 0000 0000 0000 0100 0000 0000 0000 0000 1 23:0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 1 24:0110 0000 0000 0000 1111 0001 0000 0000 0110 1111 1 25:1001 0000 0000 0000 1111 0000 1000 0000 1001 1111 1 26:0000 0000 0000 0000 0000 0000 0100 0000 0000 0000 1 27:0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 1 28:0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 1 29:0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 1 30:0000 0000 0000 0000 0000 0000 0000 0100 0000 0000 1 31:0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 1 32:0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 1 33:0111 1111 1111 1111 1111 1111 1111 1111 0000 0000 1 34:1011 1111 1111 1111 1111 1111 1111 1111 0000 0000 1 35:1101 1111 1111 1111 1111 1111 1111 1111 0000 0000 1 36:1110 1111 1111 1111 1111 1111 1111 1111 0000 0000 1 37:1111 0111 1111 1111 1111 1111 1111 1111 0000 0000 1 38:1111 1011 1111 1111 1111 1111 1111 1111 0000 0000 1 39:1111 1101 1111 1111 1111 1111 1111 1111 0000 0000 1 40:1111 1110 1111 1111 1111 1111 1111 1111 0000 0000 1 41:1111 1111 0111 1111 1111 1111 1111 1111 0000 0000 1 42:1111 1111 1011 1111 1111 1111 1111 1111 0000 0000 1 43:1111 1111 1101 1111 1111 1111 1111 1111 0000 0000 1 44:1111 1111 1110 1111 1111 1111 1111 1111 0000 0000 1 45:1111 1111 1111 0111 1111 1111 1111 1111 0000 0000 1 46:1111 1111 1111 1011 1111 1111 1111 1111 0000 0000 1 47:1111 1111 1111 1101 1111 1111 1111 1111 0000 0000 1 48:1111 1111 1111 1110 1111 1111 1111 1111 0000 0000 1 49:1111 1111 1111 1111 0111 1111 1111 1111 0000 0000 1 50:1111 1111 1111 1111 1011 1111 1111 1111 0000 0000 1 51:1111 1111 1111 1111 1101 1111 1111 1111 0000 0000 1 52:1111 1111 1111 1111 1110 1111 1111 1111 0000 0000 1 53:1111 1111 1111 1111 1111 0111 1111 1111 0000 0000 1 54:1111 1111 1111 1111 1111 1011 1111 1111 0000 0000 1 55:1111 1111 1111 1111 1111 1101 1111 1111 0000 0000 1 56:1111 1111 1111 1111 1111 1110 1111 1111 0000 0000 1 57:1111 1111 1111 1111 1111 1111 0111 1111 0000 0000 1 58:1111 1111 1111 1111 1111 1111 1011 1111 0000 0000 1 59:1111 1111 1111 1111 1111 1111 1101 1111 0000 0000 1 60:1111 1111 1111 1111 1111 1111 1110 1111 0000 0000 1 61:1111 1111 1111 1111 1111 1111 1111 0111 0000 0000 1 62:1111 1111 1111 1111 1111 1111 1111 1011 0000 0000 1 63:1111 1111 1111 1111 1111 1111 1111 1101 0000 0000 1 64:1111 1111 1111 1111 1111 1111 1111 1110 0000 0000 1 65:1111 1111 1111 1111 1111 1111 1111 1111 1000 1000 1 66:1111 1111 1111 1111 1111 1111 1111 1111 0100 0100 1 67:1111 1111 1111 1111 1111 1111 1111 1111 0010 0010 1 68:1111 1111 1111 1111 1111 1111 1111 1111 0001 0001 1 69:1111 1111 1111 1111 1111 1111 1111 1111 1010 1010 1 70:1111 1111 1111 1111 1111 1111 1111 1111 1001 1001 1 71:1111 1111 1111 1111 1111 1111 1111 1111 0110 0110 1 72:1111 1111 1111 1111 1111 1111 1111 1111 0101 0101 1 73:1111 1111 1111 1111 1111 1111 1111 1111 1000 0111 1 74:1111 1111 1111 1111 1111 1111 1111 1111 0100 1011 1 75:1111 1111 1111 1111 1111 1111 1111 1111 0010 1101 1 76:1111 1111 1111 1111 1111 1111 1111 1111 0001 1110 1 77:1111 1111 1111 1111 1111 1111 1111 1111 0111 1000 1 78:1111 1111 1111 1111 1111 1111 1111 1111 1011 0100 1 79:1111 1111 1111 1111 1111 1111 1111 1111 1101 0010 1 80:1111 1111 1111 1111 1111 1111 1111 1111 1110 0001 1 81:1111 1111 1111 1111 1111 1111 1111 1111 1100 1010 1 82:1111 1111 1111 1111 1111 1111 1111 1111 0011 1010 1 83:1111 1111 1111 1111 1111 1111 1111 1111 1010 1100 1 84:1111 1111 1111 1111 1111 1111 1111 1111 1010 0011 1 |
Added c1355.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 |
/****************************************************************************
* *
* VERILOG HIGH-LEVEL DESCRIPTION OF THE ISCAS-85 BENCHMARK CIRCUIT c1355 *
* *
* Function: Single-Error-Correcting Circuit *
* *
* Written by: Mark C. Hansen *
* *
* Last modified: Jan 12, 1998 *
* *
****************************************************************************/
module Circuit1355 (in1, in5, in9, in13, in17, in21, in25, in29,
in33, in37, in41, in45, in49, in53, in57, in61,
in65, in69, in73, in77, in81, in85, in89, in93,
in97, in101, in105, in109, in113, in117, in121, in125,
in129, in130, in131, in132, in133, in134, in135, in136,
in137,
out724, out725, out726, out727, out728, out729, out730, out731,
out732, out733, out734, out735, out736, out737, out738, out739,
out740, out741, out742, out743, out744, out745, out746, out747,
out748, out749, out750, out751, out752, out753, out754, out755);
input in1, in5, in9, in13, in17, in21, in25, in29,
in33, in37, in41, in45, in49, in53, in57, in61,
in65, in69, in73, in77, in81, in85, in89, in93,
in97, in101, in105, in109, in113, in117, in121, in125,
in129, in130, in131, in132, in133, in134, in135, in136,
in137;
output out724, out725, out726, out727, out728, out729, out730, out731,
out732, out733, out734, out735, out736, out737, out738, out739,
out740, out741, out742, out743, out744, out745, out746, out747,
out748, out749, out750, out751, out752, out753, out754, out755;
wire [0:31] ID, OD;
wire [0:7] IC;
wire R;
assign
ID[0:31] = { in1, in5, in9, in13, in17, in21, in25, in29,
in33, in37, in41, in45, in49, in53, in57, in61,
in65, in69, in73, in77, in81, in85, in89, in93,
in97, in101, in105, in109, in113, in117, in121, in125},
IC[0:7] = { in129, in130, in131, in132, in133, in134, in135, in136},
R = in137,
{out724, out725, out726, out727, out728, out729, out730, out731,
out732, out733, out734, out735, out736, out737, out738, out739,
out740, out741, out742, out743, out744, out745, out746, out747,
out748, out749, out750, out751, out752, out753, out754, out755}
= OD[0:31];
TopLevel1355 Ckt1355 (ID, IC, R, OD);
endmodule /* Circuit1355 */
/*************************************************************************/
module TopLevel1355 (ID, IC, R, OD);
input[0:31] ID;
input[0:7] IC;
input R;
output[0:31] OD;
wire[0:7] S;
Syndrome M1(S, R, IC, ID);
Correction M2(OD, S, ID);
endmodule /* TopLevel1355 */
/*************************************************************************/
module Syndrome (S, R, IC, ID);
input[0:31] ID;
input[0:7] IC;
input R;
output[0:7] S;
wire[0:15] XA;
wire[0:7] XB, XC, XD, XE, F, G, H;
/* xor XA0(XA[0], ID[0], ID[1]);*/
nand XA0_n1(XA[0]_n1, ID[0], ID[1]);
nand XA0_n2(XA[0]_n2, ID[0], XA[0]_n1);
nand XA0_n3(XA[0]_n3, XA[0]_n1, ID[1]);
nand XA0_n4(XA[0], XA[0]_n2, XA[0]_n3);
/* xor XA1(XA[1], ID[2], ID[3]);*/
nand XA1_n1(XA[1]_n1, ID[2], ID[3]);
nand XA1_n2(XA[1]_n2, ID[2], XA[1]_n1);
nand XA1_n3(XA[1]_n3, XA[1]_n1, ID[3]);
nand XA1_n4(XA[1], XA[1]_n2, XA[1]_n3);
/* xor XA2(XA[2], ID[4], ID[5]);*/
nand XA2_n1(XA[2]_n1, ID[4], ID[5]);
nand XA2_n2(XA[2]_n2, ID[4], XA[2]_n1);
nand XA2_n3(XA[2]_n3, XA[2]_n1, ID[5]);
nand XA2_n4(XA[2], XA[2]_n2, XA[2]_n3);
/* xor XA3(XA[3], ID[6], ID[7]);*/
nand XA3_n1(XA[3]_n1, ID[6], ID[7]);
nand XA3_n2(XA[3]_n2, ID[6], XA[3]_n1);
nand XA3_n3(XA[3]_n3, XA[3]_n1, ID[7]);
nand XA3_n4(XA[3], XA[3]_n2, XA[3]_n3);
/* xor XA4(XA[4], ID[8], ID[9]);*/
nand XA4_n1(XA[4]_n1, ID[8], ID[9]);
nand XA4_n2(XA[4]_n2, ID[8], XA[4]_n1);
nand XA4_n3(XA[4]_n3, XA[4]_n1, ID[9]);
nand XA4_n4(XA[4], XA[4]_n2, XA[4]_n3);
/* xor XA5(XA[5], ID[10], ID[11]);*/
nand XA5_n1(XA[5]_n1, ID[10], ID[11]);
nand XA5_n2(XA[5]_n2, ID[10], XA[5]_n1);
nand XA5_n3(XA[5]_n3, XA[5]_n1, ID[11]);
nand XA5_n4(XA[5], XA[5]_n2, XA[5]_n3);
/* xor XA6(XA[6], ID[12], ID[13]);*/
nand XA6_n1(XA[6]_n1, ID[12], ID[13]);
nand XA6_n2(XA[6]_n2, ID[12], XA[6]_n1);
nand XA6_n3(XA[6]_n3, XA[6]_n1, ID[13]);
nand XA6_n4(XA[6], XA[6]_n2, XA[6]_n3);
/* xor XA7(XA[7], ID[14], ID[15]);*/
nand XA7_n1(XA[7]_n1, ID[14], ID[15]);
nand XA7_n2(XA[7]_n2, ID[14], XA[7]_n1);
nand XA7_n3(XA[7]_n3, XA[7]_n1, ID[15]);
nand XA7_n4(XA[7], XA[7]_n2, XA[7]_n3);
/* xor XA8(XA[8], ID[16], ID[17]);*/
nand XA8_n1(XA[8]_n1, ID[16], ID[17]);
nand XA8_n2(XA[8]_n2, ID[16], XA[8]_n1);
nand XA8_n3(XA[8]_n3, XA[8]_n1, ID[17]);
nand XA8_n4(XA[8], XA[8]_n2, XA[8]_n3);
/* xor XA9(XA[9], ID[18], ID[19]);*/
nand XA9_n1(XA[9]_n1, ID[18], ID[19]);
nand XA9_n2(XA[9]_n2, ID[18], XA[9]_n1);
nand XA9_n3(XA[9]_n3, XA[9]_n1, ID[19]);
nand XA9_n4(XA[9], XA[9]_n2, XA[9]_n3);
/* xor XA10(XA[10], ID[20], ID[21]);*/
nand XA10_n1(XA[10]_n1, ID[20], ID[21]);
nand XA10_n2(XA[10]_n2, ID[20], XA[10]_n1);
nand XA10_n3(XA[10]_n3, XA[10]_n1, ID[21]);
nand XA10_n4(XA[10], XA[10]_n2, XA[10]_n3);
/* xor XA11(XA[11], ID[22], ID[23]);*/
nand XA11_n1(XA[11]_n1, ID[22], ID[23]);
nand XA11_n2(XA[11]_n2, ID[22], XA[11]_n1);
nand XA11_n3(XA[11]_n3, XA[11]_n1, ID[23]);
nand XA11_n4(XA[11], XA[11]_n2, XA[11]_n3);
/* xor XA12(XA[12], ID[24], ID[25]);*/
nand XA12_n1(XA[12]_n1, ID[24], ID[25]);
nand XA12_n2(XA[12]_n2, ID[24], XA[12]_n1);
nand XA12_n3(XA[12]_n3, XA[12]_n1, ID[25]);
nand XA12_n4(XA[12], XA[12]_n2, XA[12]_n3);
/* xor XA13(XA[13], ID[26], ID[27]);*/
nand XA13_n1(XA[13]_n1, ID[26], ID[27]);
nand XA13_n2(XA[13]_n2, ID[26], XA[13]_n1);
nand XA13_n3(XA[13]_n3, XA[13]_n1, ID[27]);
nand XA13_n4(XA[13], XA[13]_n2, XA[13]_n3);
/* xor XA14(XA[14], ID[28], ID[29]);*/
nand XA14_n1(XA[14]_n1, ID[28], ID[29]);
nand XA14_n2(XA[14]_n2, ID[28], XA[14]_n1);
nand XA14_n3(XA[14]_n3, XA[14]_n1, ID[29]);
nand XA14_n4(XA[14], XA[14]_n2, XA[14]_n3);
/* xor XA15(XA[15], ID[30], ID[31]);*/
nand XA15_n1(XA[15]_n1, ID[30], ID[31]);
nand XA15_n2(XA[15]_n2, ID[30], XA[15]_n1);
nand XA15_n3(XA[15]_n3, XA[15]_n1, ID[31]);
nand XA15_n4(XA[15], XA[15]_n2, XA[15]_n3);
/* xor F0(F[0], XA[0], XA[1]);*/
nand F0_n1(F[0]_n1, XA[0], XA[1]);
nand F0_n2(F[0]_n2, XA[0], F[0]_n1);
nand F0_n3(F[0]_n3, F[0]_n1, XA[1]);
nand F0_n4(F[0], F[0]_n2, F[0]_n3);
/* xor F1(F[1], XA[2], XA[3]);*/
nand F1_n1(F[1]_n1, XA[2], XA[3]);
nand F1_n2(F[1]_n2, XA[2], F[1]_n1);
nand F1_n3(F[1]_n3, F[1]_n1, XA[3]);
nand F1_n4(F[1], F[1]_n2, F[1]_n3);
/* xor F2(F[2], XA[4], XA[5]);*/
nand F2_n1(F[2]_n1, XA[4], XA[5]);
nand F2_n2(F[2]_n2, XA[4], F[2]_n1);
nand F2_n3(F[2]_n3, F[2]_n1, XA[5]);
nand F2_n4(F[2], F[2]_n2, F[2]_n3);
/* xor F3(F[3], XA[6], XA[7]);*/
nand F3_n1(F[3]_n1, XA[6], XA[7]);
nand F3_n2(F[3]_n2, XA[6], F[3]_n1);
nand F3_n3(F[3]_n3, F[3]_n1, XA[7]);
nand F3_n4(F[3], F[3]_n2, F[3]_n3);
/* xor F4(F[4], XA[8], XA[9]);*/
nand F4_n1(F[4]_n1, XA[8], XA[9]);
nand F4_n2(F[4]_n2, XA[8], F[4]_n1);
nand F4_n3(F[4]_n3, F[4]_n1, XA[9]);
nand F4_n4(F[4], F[4]_n2, F[4]_n3);
/* xor F5(F[5], XA[10], XA[11]);*/
nand F5_n1(F[5]_n1, XA[10], XA[11]);
nand F5_n2(F[5]_n2, XA[10], F[5]_n1);
nand F5_n3(F[5]_n3, F[5]_n1, XA[11]);
nand F5_n4(F[5], F[5]_n2, F[5]_n3);
/* xor F6(F[6], XA[12], XA[13]);*/
nand F6_n1(F[6]_n1, XA[12], XA[13]);
nand F6_n2(F[6]_n2, XA[12], F[6]_n1);
nand F6_n3(F[6]_n3, F[6]_n1, XA[13]);
nand F6_n4(F[6], F[6]_n2, F[6]_n3);
/* xor F7(F[7], XA[14], XA[15]);*/
nand F7_n1(F[7]_n1, XA[14], XA[15]);
nand F7_n2(F[7]_n2, XA[14], F[7]_n1);
nand F7_n3(F[7]_n3, F[7]_n1, XA[15]);
nand F7_n4(F[7], F[7]_n2, F[7]_n3);
and H0(H[0], IC[0], R);
and H1(H[1], IC[1], R);
and H2(H[2], IC[2], R);
and H3(H[3], IC[3], R);
and H4(H[4], IC[4], R);
and H5(H[5], IC[5], R);
and H6(H[6], IC[6], R);
and H7(H[7], IC[7], R);
/* xor XB0(XB[0], ID[0], ID[4]);*/
nand XB0_n1(XB[0]_n1, ID[0], ID[4]);
nand XB0_n2(XB[0]_n2, ID[0], XB[0]_n1);
nand XB0_n3(XB[0]_n3, XB[0]_n1, ID[4]);
nand XB0_n4(XB[0], XB[0]_n2, XB[0]_n3);
/* xor XB1(XB[1], ID[1], ID[5]);*/
nand XB1_n1(XB[1]_n1, ID[1], ID[5]);
nand XB1_n2(XB[1]_n2, ID[1], XB[1]_n1);
nand XB1_n3(XB[1]_n3, XB[1]_n1, ID[5]);
nand XB1_n4(XB[1], XB[1]_n2, XB[1]_n3);
/* xor XB2(XB[2], ID[2], ID[6]);*/
nand XB2_n1(XB[2]_n1, ID[2], ID[6]);
nand XB2_n2(XB[2]_n2, ID[2], XB[2]_n1);
nand XB2_n3(XB[2]_n3, XB[2]_n1, ID[6]);
nand XB2_n4(XB[2], XB[2]_n2, XB[2]_n3);
/* xor XB3(XB[3], ID[3], ID[7]);*/
nand XB3_n1(XB[3]_n1, ID[3], ID[7]);
nand XB3_n2(XB[3]_n2, ID[3], XB[3]_n1);
nand XB3_n3(XB[3]_n3, XB[3]_n1, ID[7]);
nand XB3_n4(XB[3], XB[3]_n2, XB[3]_n3);
/* xor XB4(XB[4], ID[16], ID[20]);*/
nand XB4_n1(XB[4]_n1, ID[16], ID[20]);
nand XB4_n2(XB[4]_n2, ID[16], XB[4]_n1);
nand XB4_n3(XB[4]_n3, XB[4]_n1, ID[20]);
nand XB4_n4(XB[4], XB[4]_n2, XB[4]_n3);
/* xor XB5(XB[5], ID[17], ID[21]);*/
nand XB5_n1(XB[5]_n1, ID[17], ID[21]);
nand XB5_n2(XB[5]_n2, ID[17], XB[5]_n1);
nand XB5_n3(XB[5]_n3, XB[5]_n1, ID[21]);
nand XB5_n4(XB[5], XB[5]_n2, XB[5]_n3);
/* xor XB6(XB[6], ID[18], ID[22]);*/
nand XB6_n1(XB[6]_n1, ID[18], ID[22]);
nand XB6_n2(XB[6]_n2, ID[18], XB[6]_n1);
nand XB6_n3(XB[6]_n3, XB[6]_n1, ID[22]);
nand XB6_n4(XB[6], XB[6]_n2, XB[6]_n3);
/* xor XB7(XB[7], ID[19], ID[23]);*/
nand XB7_n1(XB[7]_n1, ID[19], ID[23]);
nand XB7_n2(XB[7]_n2, ID[19], XB[7]_n1);
nand XB7_n3(XB[7]_n3, XB[7]_n1, ID[23]);
nand XB7_n4(XB[7], XB[7]_n2, XB[7]_n3);
/* xor XC0(XC[0], ID[8], ID[12]);*/
nand XC0_n1(XC[0]_n1, ID[8], ID[12]);
nand XC0_n2(XC[0]_n2, ID[8], XC[0]_n1);
nand XC0_n3(XC[0]_n3, XC[0]_n1, ID[12]);
nand XC0_n4(XC[0], XC[0]_n2, XC[0]_n3);
/* xor XC1(XC[1], ID[9], ID[13]);*/
nand XC1_n1(XC[1]_n1, ID[9], ID[13]);
nand XC1_n2(XC[1]_n2, ID[9], XC[1]_n1);
nand XC1_n3(XC[1]_n3, XC[1]_n1, ID[13]);
nand XC1_n4(XC[1], XC[1]_n2, XC[1]_n3);
/* xor XC2(XC[2], ID[10], ID[14]);*/
nand XC2_n1(XC[2]_n1, ID[10], ID[14]);
nand XC2_n2(XC[2]_n2, ID[10], XC[2]_n1);
nand XC2_n3(XC[2]_n3, XC[2]_n1, ID[14]);
nand XC2_n4(XC[2], XC[2]_n2, XC[2]_n3);
/* xor XC3(XC[3], ID[11], ID[15]);*/
nand XC3_n1(XC[3]_n1, ID[11], ID[15]);
nand XC3_n2(XC[3]_n2, ID[11], XC[3]_n1);
nand XC3_n3(XC[3]_n3, XC[3]_n1, ID[15]);
nand XC3_n4(XC[3], XC[3]_n2, XC[3]_n3);
/* xor XC4(XC[4], ID[24], ID[28]);*/
nand XC4_n1(XC[4]_n1, ID[24], ID[28]);
nand XC4_n2(XC[4]_n2, ID[24], XC[4]_n1);
nand XC4_n3(XC[4]_n3, XC[4]_n1, ID[28]);
nand XC4_n4(XC[4], XC[4]_n2, XC[4]_n3);
/* xor XC5(XC[5], ID[25], ID[29]);*/
nand XC5_n1(XC[5]_n1, ID[25], ID[29]);
nand XC5_n2(XC[5]_n2, ID[25], XC[5]_n1);
nand XC5_n3(XC[5]_n3, XC[5]_n1, ID[29]);
nand XC5_n4(XC[5], XC[5]_n2, XC[5]_n3);
/* xor XC6(XC[6], ID[26], ID[30]);*/
nand XC6_n1(XC[6]_n1, ID[26], ID[30]);
nand XC6_n2(XC[6]_n2, ID[26], XC[6]_n1);
nand XC6_n3(XC[6]_n3, XC[6]_n1, ID[30]);
nand XC6_n4(XC[6], XC[6]_n2, XC[6]_n3);
/* xor XC7(XC[7], ID[27], ID[31]);*/
nand XC7_n1(XC[7]_n1, ID[27], ID[31]);
nand XC7_n2(XC[7]_n2, ID[27], XC[7]_n1);
nand XC7_n3(XC[7]_n3, XC[7]_n1, ID[31]);
nand XC7_n4(XC[7], XC[7]_n2, XC[7]_n3);
/* xor XE0(XE[0], XB[0], XC[0]);*/
nand XE0_n1(XE[0]_n1, XB[0], XC[0]);
nand XE0_n2(XE[0]_n2, XB[0], XE[0]_n1);
nand XE0_n3(XE[0]_n3, XE[0]_n1, XC[0]);
nand XE0_n4(XE[0], XE[0]_n2, XE[0]_n3);
/* xor XE1(XE[1], XB[1], XC[1]);*/
nand XE1_n1(XE[1]_n1, XB[1], XC[1]);
nand XE1_n2(XE[1]_n2, XB[1], XE[1]_n1);
nand XE1_n3(XE[1]_n3, XE[1]_n1, XC[1]);
nand XE1_n4(XE[1], XE[1]_n2, XE[1]_n3);
/* xor XE2(XE[2], XB[2], XC[2]);*/
nand XE2_n1(XE[2]_n1, XB[2], XC[2]);
nand XE2_n2(XE[2]_n2, XB[2], XE[2]_n1);
nand XE2_n3(XE[2]_n3, XE[2]_n1, XC[2]);
nand XE2_n4(XE[2], XE[2]_n2, XE[2]_n3);
/* xor XE3(XE[3], XB[3], XC[3]);*/
nand XE3_n1(XE[3]_n1, XB[3], XC[3]);
nand XE3_n2(XE[3]_n2, XB[3], XE[3]_n1);
nand XE3_n3(XE[3]_n3, XE[3]_n1, XC[3]);
nand XE3_n4(XE[3], XE[3]_n2, XE[3]_n3);
/* xor XE4(XE[4], XB[4], XC[4]);*/
nand XE4_n1(XE[4]_n1, XB[4], XC[4]);
nand XE4_n2(XE[4]_n2, XB[4], XE[4]_n1);
nand XE4_n3(XE[4]_n3, XE[4]_n1, XC[4]);
nand XE4_n4(XE[4], XE[4]_n2, XE[4]_n3);
/* xor XE5(XE[5], XB[5], XC[5]);*/
nand XE5_n1(XE[5]_n1, XB[5], XC[5]);
nand XE5_n2(XE[5]_n2, XB[5], XE[5]_n1);
nand XE5_n3(XE[5]_n3, XE[5]_n1, XC[5]);
nand XE5_n4(XE[5], XE[5]_n2, XE[5]_n3);
/* xor XE6(XE[6], XB[6], XC[6]);*/
nand XE6_n1(XE[6]_n1, XB[6], XC[6]);
nand XE6_n2(XE[6]_n2, XB[6], XE[6]_n1);
nand XE6_n3(XE[6]_n3, XE[6]_n1, XC[6]);
nand XE6_n4(XE[6], XE[6]_n2, XE[6]_n3);
/* xor XE7(XE[7], XB[7], XC[7]);*/
nand XE7_n1(XE[7]_n1, XB[7], XC[7]);
nand XE7_n2(XE[7]_n2, XB[7], XE[7]_n1);
nand XE7_n3(XE[7]_n3, XE[7]_n1, XC[7]);
nand XE7_n4(XE[7], XE[7]_n2, XE[7]_n3);
/* xor G0(G[0], F[0], F[1]);*/
nand G0_n1(G[0]_n1, F[0], F[1]);
nand G0_n2(G[0]_n2, F[0], G[0]_n1);
nand G0_n3(G[0]_n3, G[0]_n1, F[1]);
nand G0_n4(G[0], G[0]_n2, G[0]_n3);
/* xor G1(G[1], F[2], F[3]);*/
nand G1_n1(G[1]_n1, F[2], F[3]);
nand G1_n2(G[1]_n2, F[2], G[1]_n1);
nand G1_n3(G[1]_n3, G[1]_n1, F[3]);
nand G1_n4(G[1], G[1]_n2, G[1]_n3);
/* xor G2(G[2], F[0], F[2]);*/
nand G2_n1(G[2]_n1, F[0], F[2]);
nand G2_n2(G[2]_n2, F[0], G[2]_n1);
nand G2_n3(G[2]_n3, G[2]_n1, F[2]);
nand G2_n4(G[2], G[2]_n2, G[2]_n3);
/* xor G3(G[3], F[1], F[3]);*/
nand G3_n1(G[3]_n1, F[1], F[3]);
nand G3_n2(G[3]_n2, F[1], G[3]_n1);
nand G3_n3(G[3]_n3, G[3]_n1, F[3]);
nand G3_n4(G[3], G[3]_n2, G[3]_n3);
/* xor G4(G[4], F[4], F[5]);*/
nand G4_n1(G[4]_n1, F[4], F[5]);
nand G4_n2(G[4]_n2, F[4], G[4]_n1);
nand G4_n3(G[4]_n3, G[4]_n1, F[5]);
nand G4_n4(G[4], G[4]_n2, G[4]_n3);
/* xor G5(G[5], F[6], F[7]);*/
nand G5_n1(G[5]_n1, F[6], F[7]);
nand G5_n2(G[5]_n2, F[6], G[5]_n1);
nand G5_n3(G[5]_n3, G[5]_n1, F[7]);
nand G5_n4(G[5], G[5]_n2, G[5]_n3);
/* xor G6(G[6], F[4], F[6]);*/
nand G6_n1(G[6]_n1, F[4], F[6]);
nand G6_n2(G[6]_n2, F[4], G[6]_n1);
nand G6_n3(G[6]_n3, G[6]_n1, F[6]);
nand G6_n4(G[6], G[6]_n2, G[6]_n3);
/* xor G7(G[7], F[5], F[7]);*/
nand G7_n1(G[7]_n1, F[5], F[7]);
nand G7_n2(G[7]_n2, F[5], G[7]_n1);
nand G7_n3(G[7]_n3, G[7]_n1, F[7]);
nand G7_n4(G[7], G[7]_n2, G[7]_n3);
/* xor XD0(XD[0], G[4], H[0]);*/
nand XD0_n1(XD[0]_n1, G[4], H[0]);
nand XD0_n2(XD[0]_n2, G[4], XD[0]_n1);
nand XD0_n3(XD[0]_n3, XD[0]_n1, H[0]);
nand XD0_n4(XD[0], XD[0]_n2, XD[0]_n3);
/* xor XD1(XD[1], G[5], H[1]);*/
nand XD1_n1(XD[1]_n1, G[5], H[1]);
nand XD1_n2(XD[1]_n2, G[5], XD[1]_n1);
nand XD1_n3(XD[1]_n3, XD[1]_n1, H[1]);
nand XD1_n4(XD[1], XD[1]_n2, XD[1]_n3);
/* xor XD2(XD[2], G[6], H[2]);*/
nand XD2_n1(XD[2]_n1, G[6], H[2]);
nand XD2_n2(XD[2]_n2, G[6], XD[2]_n1);
nand XD2_n3(XD[2]_n3, XD[2]_n1, H[2]);
nand XD2_n4(XD[2], XD[2]_n2, XD[2]_n3);
/* xor XD3(XD[3], G[7], H[3]);*/
nand XD3_n1(XD[3]_n1, G[7], H[3]);
nand XD3_n2(XD[3]_n2, G[7], XD[3]_n1);
nand XD3_n3(XD[3]_n3, XD[3]_n1, H[3]);
nand XD3_n4(XD[3], XD[3]_n2, XD[3]_n3);
/* xor XD4(XD[4], G[0], H[4]);*/
nand XD4_n1(XD[4]_n1, G[0], H[4]);
nand XD4_n2(XD[4]_n2, G[0], XD[4]_n1);
nand XD4_n3(XD[4]_n3, XD[4]_n1, H[4]);
nand XD4_n4(XD[4], XD[4]_n2, XD[4]_n3);
/* xor XD5(XD[5], G[1], H[5]);*/
nand XD5_n1(XD[5]_n1, G[1], H[5]);
nand XD5_n2(XD[5]_n2, G[1], XD[5]_n1);
nand XD5_n3(XD[5]_n3, XD[5]_n1, H[5]);
nand XD5_n4(XD[5], XD[5]_n2, XD[5]_n3);
/* xor XD6(XD[6], G[2], H[6]);*/
nand XD6_n1(XD[6]_n1, G[2], H[6]);
nand XD6_n2(XD[6]_n2, G[2], XD[6]_n1);
nand XD6_n3(XD[6]_n3, XD[6]_n1, H[6]);
nand XD6_n4(XD[6], XD[6]_n2, XD[6]_n3);
/* xor XD7(XD[7], G[3], H[7]);*/
nand XD7_n1(XD[7]_n1, G[3], H[7]);
nand XD7_n2(XD[7]_n2, G[3], XD[7]_n1);
nand XD7_n3(XD[7]_n3, XD[7]_n1, H[7]);
nand XD7_n4(XD[7], XD[7]_n2, XD[7]_n3);
/* xor S0(S[0], XD[0], XE[0]);*/
nand S0_n1(S[0]_n1, XD[0], XE[0]);
nand S0_n2(S[0]_n2, XD[0], S[0]_n1);
nand S0_n3(S[0]_n3, S[0]_n1, XE[0]);
nand S0_n4(S[0], S[0]_n2, S[0]_n3);
/* xor S1(S[1], XD[1], XE[1]);*/
nand S1_n1(S[1]_n1, XD[1], XE[1]);
nand S1_n2(S[1]_n2, XD[1], S[1]_n1);
nand S1_n3(S[1]_n3, S[1]_n1, XE[1]);
nand S1_n4(S[1], S[1]_n2, S[1]_n3);
/* xor S2(S[2], XD[2], XE[2]);*/
nand S2_n1(S[2]_n1, XD[2], XE[2]);
nand S2_n2(S[2]_n2, XD[2], S[2]_n1);
nand S2_n3(S[2]_n3, S[2]_n1, XE[2]);
nand S2_n4(S[2], S[2]_n2, S[2]_n3);
/* xor S3(S[3], XD[3], XE[3]);*/
nand S3_n1(S[3]_n1, XD[3], XE[3]);
nand S3_n2(S[3]_n2, XD[3], S[3]_n1);
nand S3_n3(S[3]_n3, S[3]_n1, XE[3]);
nand S3_n4(S[3], S[3]_n2, S[3]_n3);
/* xor S4(S[4], XD[4], XE[4]);*/
nand S4_n1(S[4]_n1, XD[4], XE[4]);
nand S4_n2(S[4]_n2, XD[4], S[4]_n1);
nand S4_n3(S[4]_n3, S[4]_n1, XE[4]);
nand S4_n4(S[4], S[4]_n2, S[4]_n3);
/* xor S5(S[5], XD[5], XE[5]);*/
nand S5_n1(S[5]_n1, XD[5], XE[5]);
nand S5_n2(S[5]_n2, XD[5], S[5]_n1);
nand S5_n3(S[5]_n3, S[5]_n1, XE[5]);
nand S5_n4(S[5], S[5]_n2, S[5]_n3);
/* xor S6(S[6], XD[6], XE[6]);*/
nand S6_n1(S[6]_n1, XD[6], XE[6]);
nand S6_n2(S[6]_n2, XD[6], S[6]_n1);
nand S6_n3(S[6]_n3, S[6]_n1, XE[6]);
nand S6_n4(S[6], S[6]_n2, S[6]_n3);
/* xor S7(S[7], XD[7], XE[7]);*/
nand S7_n1(S[7]_n1, XD[7], XE[7]);
nand S7_n2(S[7]_n2, XD[7], S[7]_n1);
nand S7_n3(S[7]_n3, S[7]_n1, XE[7]);
nand S7_n4(S[7], S[7]_n2, S[7]_n3);
endmodule /* Syndrome */
/*************************************************************************/
module Correction (OD, S, ID);
input[0:31] ID;
input[0:7] S;
output[0:31] OD;
wire[0:31] E;
wire[0:15] XA;
wire[0:7] XB, XC, XD, XE, F, G, H, T, W;
wire[0:4] S0B, S1B, S2B, S3B, S4B, S5B, S6B, S7B;
wire[0:1] U;
not S0B0(S0B[0], S[0]);
not S0B1(S0B[1], S[0]);
not S0B2(S0B[2], S[0]);
not S0B3(S0B[3], S[0]);
not S0B4(S0B[4], S[0]);
not S1B0(S1B[0], S[1]);
not S1B1(S1B[1], S[1]);
not S1B2(S1B[2], S[1]);
not S1B3(S1B[3], S[1]);
not S1B4(S1B[4], S[1]);
not S2B0(S2B[0], S[2]);
not S2B1(S2B[1], S[2]);
not S2B2(S2B[2], S[2]);
not S2B3(S2B[3], S[2]);
not S2B4(S2B[4], S[2]);
not S3B0(S3B[0], S[3]);
not S3B1(S3B[1], S[3]);
not S3B2(S3B[2], S[3]);
not S3B3(S3B[3], S[3]);
not S3B4(S3B[4], S[3]);
not S4B0(S4B[0], S[4]);
not S4B1(S4B[1], S[4]);
not S4B2(S4B[2], S[4]);
not S4B3(S4B[3], S[4]);
not S4B4(S4B[4], S[4]);
not S5B0(S5B[0], S[5]);
not S5B1(S5B[1], S[5]);
not S5B2(S5B[2], S[5]);
not S5B3(S5B[3], S[5]);
not S5B4(S5B[4], S[5]);
not S6B0(S6B[0], S[6]);
not S6B1(S6B[1], S[6]);
not S6B2(S6B[2], S[6]);
not S6B3(S6B[3], S[6]);
not S6B4(S6B[4], S[6]);
not S7B0(S7B[0], S[7]);
not S7B1(S7B[1], S[7]);
not S7B2(S7B[2], S[7]);
not S7B3(S7B[3], S[7]);
not S7B4(S7B[4], S[7]);
and T0(T[0], S0B[0], S1B[0], S2B[0], S[3]);
and T1(T[1], S0B[1], S1B[1], S[2], S3B[0]);
and T2(T[2], S0B[2], S[1], S2B[1], S3B[1]);
and T3(T[3], S[0], S1B[2], S2B[2], S3B[2]);
and T4(T[4], S4B[0], S5B[0], S6B[0], S[7]);
and T5(T[5], S4B[1], S5B[1], S[6], S7B[0]);
and T6(T[6], S4B[2], S[5], S6B[1], S7B[1]);
and T7(T[7], S[4], S5B[2], S6B[2], S7B[2]);
or U0(U[0], T[0], T[1], T[2], T[3]);
or U1(U[1], T[4], T[5], T[6], T[7]);
and W0(W[0], S[4], S5B[3], S[6], S7B[3], U[0]);
and W1(W[1], S[4], S5B[4], S6B[3], S[7], U[0]);
and W2(W[2], S4B[3], S[5], S[6], S7B[4], U[0]);
and W3(W[3], S4B[4], S[5], S6B[4], S[7], U[0]);
and W4(W[4], S[0], S1B[3], S[2], S3B[3], U[1]);
and W5(W[5], S[0], S1B[4], S2B[3], S[3], U[1]);
and W6(W[6], S0B[3], S[1], S[2], S3B[4], U[1]);
and W7(W[7], S0B[4], S[1], S2B[4], S[3], U[1]);
and E0(E[0], W[0], S[0]);
and E1(E[1], W[0], S[1]);
and E2(E[2], W[0], S[2]);
and E3(E[3], W[0], S[3]);
and E4(E[4], W[1], S[0]);
and E5(E[5], W[1], S[1]);
and E6(E[6], W[1], S[2]);
and E7(E[7], W[1], S[3]);
and E8(E[8], W[2], S[0]);
and E9(E[9], W[2], S[1]);
and E10(E[10], W[2], S[2]);
and E11(E[11], W[2], S[3]);
and E12(E[12], W[3], S[0]);
and E13(E[13], W[3], S[1]);
and E14(E[14], W[3], S[2]);
and E15(E[15], W[3], S[3]);
and E16(E[16], W[4], S[4]);
and E17(E[17], W[4], S[5]);
and E18(E[18], W[4], S[6]);
and E19(E[19], W[4], S[7]);
and E20(E[20], W[5], S[4]);
and E21(E[21], W[5], S[5]);
and E22(E[22], W[5], S[6]);
and E23(E[23], W[5], S[7]);
and E24(E[24], W[6], S[4]);
and E25(E[25], W[6], S[5]);
and E26(E[26], W[6], S[6]);
and E27(E[27], W[6], S[7]);
and E28(E[28], W[7], S[4]);
and E29(E[29], W[7], S[5]);
and E30(E[30], W[7], S[6]);
and E31(E[31], W[7], S[7]);
/* xor OD0(OD[0], ID[0], E[0]);*/
nand OD0_n1(OD[0]_n1, ID[0], E[0]);
nand OD0_n2(OD[0]_n2, ID[0], OD[0]_n1);
nand OD0_n3(OD[0]_n3, OD[0]_n1, E[0]);
nand OD0_n4(OD[0], OD[0]_n2, OD[0]_n3);
/* xor OD1(OD[1], ID[1], E[1]);*/
nand OD1_n1(OD[1]_n1, ID[1], E[1]);
nand OD1_n2(OD[1]_n2, ID[1], OD[1]_n1);
nand OD1_n3(OD[1]_n3, OD[1]_n1, E[1]);
nand OD1_n4(OD[1], OD[1]_n2, OD[1]_n3);
/* xor OD2(OD[2], ID[2], E[2]);*/
nand OD2_n1(OD[2]_n1, ID[2], E[2]);
nand OD2_n2(OD[2]_n2, ID[2], OD[2]_n1);
nand OD2_n3(OD[2]_n3, OD[2]_n1, E[2]);
nand OD2_n4(OD[2], OD[2]_n2, OD[2]_n3);
/* xor OD3(OD[3], ID[3], E[3]);*/
nand OD3_n1(OD[3]_n1, ID[3], E[3]);
nand OD3_n2(OD[3]_n2, ID[3], OD[3]_n1);
nand OD3_n3(OD[3]_n3, OD[3]_n1, E[3]);
nand OD3_n4(OD[3], OD[3]_n2, OD[3]_n3);
/* xor OD4(OD[4], ID[4], E[4]);*/
nand OD4_n1(OD[4]_n1, ID[4], E[4]);
nand OD4_n2(OD[4]_n2, ID[4], OD[4]_n1);
nand OD4_n3(OD[4]_n3, OD[4]_n1, E[4]);
nand OD4_n4(OD[4], OD[4]_n2, OD[4]_n3);
/* xor OD5(OD[5], ID[5], E[5]);*/
nand OD5_n1(OD[5]_n1, ID[5], E[5]);
nand OD5_n2(OD[5]_n2, ID[5], OD[5]_n1);
nand OD5_n3(OD[5]_n3, OD[5]_n1, E[5]);
nand OD5_n4(OD[5], OD[5]_n2, OD[5]_n3);
/* xor OD6(OD[6], ID[6], E[6]);*/
nand OD6_n1(OD[6]_n1, ID[6], E[6]);
nand OD6_n2(OD[6]_n2, ID[6], OD[6]_n1);
nand OD6_n3(OD[6]_n3, OD[6]_n1, E[6]);
nand OD6_n4(OD[6], OD[6]_n2, OD[6]_n3);
/* xor OD7(OD[7], ID[7], E[7]);*/
nand OD7_n1(OD[7]_n1, ID[7], E[7]);
nand OD7_n2(OD[7]_n2, ID[7], OD[7]_n1);
nand OD7_n3(OD[7]_n3, OD[7]_n1, E[7]);
nand OD7_n4(OD[7], OD[7]_n2, OD[7]_n3);
/* xor OD8(OD[8], ID[8], E[8]);*/
nand OD8_n1(OD[8]_n1, ID[8], E[8]);
nand OD8_n2(OD[8]_n2, ID[8], OD[8]_n1);
nand OD8_n3(OD[8]_n3, OD[8]_n1, E[8]);
nand OD8_n4(OD[8], OD[8]_n2, OD[8]_n3);
/* xor OD9(OD[9], ID[9], E[9]);*/
nand OD9_n1(OD[9]_n1, ID[9], E[9]);
nand OD9_n2(OD[9]_n2, ID[9], OD[9]_n1);
nand OD9_n3(OD[9]_n3, OD[9]_n1, E[9]);
nand OD9_n4(OD[9], OD[9]_n2, OD[9]_n3);
/* xor OD10(OD[10], ID[10], E[10]);*/
nand OD10_n1(OD[10]_n1, ID[10], E[10]);
nand OD10_n2(OD[10]_n2, ID[10], OD[10]_n1);
nand OD10_n3(OD[10]_n3, OD[10]_n1, E[10]);
nand OD10_n4(OD[10], OD[10]_n2, OD[10]_n3);
/* xor OD11(OD[11], ID[11], E[11]);*/
nand OD11_n1(OD[11]_n1, ID[11], E[11]);
nand OD11_n2(OD[11]_n2, ID[11], OD[11]_n1);
nand OD11_n3(OD[11]_n3, OD[11]_n1, E[11]);
nand OD11_n4(OD[11], OD[11]_n2, OD[11]_n3);
/* xor OD12(OD[12], ID[12], E[12]);*/
nand OD12_n1(OD[12]_n1, ID[12], E[12]);
nand OD12_n2(OD[12]_n2, ID[12], OD[12]_n1);
nand OD12_n3(OD[12]_n3, OD[12]_n1, E[12]);
nand OD12_n4(OD[12], OD[12]_n2, OD[12]_n3);
/* xor OD13(OD[13], ID[13], E[13]);*/
nand OD13_n1(OD[13]_n1, ID[13], E[13]);
nand OD13_n2(OD[13]_n2, ID[13], OD[13]_n1);
nand OD13_n3(OD[13]_n3, OD[13]_n1, E[13]);
nand OD13_n4(OD[13], OD[13]_n2, OD[13]_n3);
/* xor OD14(OD[14], ID[14], E[14]);*/
nand OD14_n1(OD[14]_n1, ID[14], E[14]);
nand OD14_n2(OD[14]_n2, ID[14], OD[14]_n1);
nand OD14_n3(OD[14]_n3, OD[14]_n1, E[14]);
nand OD14_n4(OD[14], OD[14]_n2, OD[14]_n3);
/* xor OD15(OD[15], ID[15], E[15]);*/
nand OD15_n1(OD[15]_n1, ID[15], E[15]);
nand OD15_n2(OD[15]_n2, ID[15], OD[15]_n1);
nand OD15_n3(OD[15]_n3, OD[15]_n1, E[15]);
nand OD15_n4(OD[15], OD[15]_n2, OD[15]_n3);
/* xor OD16(OD[16], ID[16], E[16]);*/
nand OD16_n1(OD[16]_n1, ID[16], E[16]);
nand OD16_n2(OD[16]_n2, ID[16], OD[16]_n1);
nand OD16_n3(OD[16]_n3, OD[16]_n1, E[16]);
nand OD16_n4(OD[16], OD[16]_n2, OD[16]_n3);
/* xor OD17(OD[17], ID[17], E[17]);*/
nand OD17_n1(OD[17]_n1, ID[17], E[17]);
nand OD17_n2(OD[17]_n2, ID[17], OD[17]_n1);
nand OD17_n3(OD[17]_n3, OD[17]_n1, E[17]);
nand OD17_n4(OD[17], OD[17]_n2, OD[17]_n3);
/* xor OD18(OD[18], ID[18], E[18]);*/
nand OD18_n1(OD[18]_n1, ID[18], E[18]);
nand OD18_n2(OD[18]_n2, ID[18], OD[18]_n1);
nand OD18_n3(OD[18]_n3, OD[18]_n1, E[18]);
nand OD18_n4(OD[18], OD[18]_n2, OD[18]_n3);
/* xor OD19(OD[19], ID[19], E[19]);*/
nand OD19_n1(OD[19]_n1, ID[19], E[19]);
nand OD19_n2(OD[19]_n2, ID[19], OD[19]_n1);
nand OD19_n3(OD[19]_n3, OD[19]_n1, E[19]);
nand OD19_n4(OD[19], OD[19]_n2, OD[19]_n3);
/* xor OD20(OD[20], ID[20], E[20]);*/
nand OD20_n1(OD[20]_n1, ID[20], E[20]);
nand OD20_n2(OD[20]_n2, ID[20], OD[20]_n1);
nand OD20_n3(OD[20]_n3, OD[20]_n1, E[20]);
nand OD20_n4(OD[20], OD[20]_n2, OD[20]_n3);
/* xor OD21(OD[21], ID[21], E[21]);*/
nand OD21_n1(OD[21]_n1, ID[21], E[21]);
nand OD21_n2(OD[21]_n2, ID[21], OD[21]_n1);
nand OD21_n3(OD[21]_n3, OD[21]_n1, E[21]);
nand OD21_n4(OD[21], OD[21]_n2, OD[21]_n3);
/* xor OD22(OD[22], ID[22], E[22]);*/
nand OD22_n1(OD[22]_n1, ID[22], E[22]);
nand OD22_n2(OD[22]_n2, ID[22], OD[22]_n1);
nand OD22_n3(OD[22]_n3, OD[22]_n1, E[22]);
nand OD22_n4(OD[22], OD[22]_n2, OD[22]_n3);
/* xor OD23(OD[23], ID[23], E[23]);*/
nand OD23_n1(OD[23]_n1, ID[23], E[23]);
nand OD23_n2(OD[23]_n2, ID[23], OD[23]_n1);
nand OD23_n3(OD[23]_n3, OD[23]_n1, E[23]);
nand OD23_n4(OD[23], OD[23]_n2, OD[23]_n3);
/* xor OD24(OD[24], ID[24], E[24]);*/
nand OD24_n1(OD[24]_n1, ID[24], E[24]);
nand OD24_n2(OD[24]_n2, ID[24], OD[24]_n1);
nand OD24_n3(OD[24]_n3, OD[24]_n1, E[24]);
nand OD24_n4(OD[24], OD[24]_n2, OD[24]_n3);
/* xor OD25(OD[25], ID[25], E[25]);*/
nand OD25_n1(OD[25]_n1, ID[25], E[25]);
nand OD25_n2(OD[25]_n2, ID[25], OD[25]_n1);
nand OD25_n3(OD[25]_n3, OD[25]_n1, E[25]);
nand OD25_n4(OD[25], OD[25]_n2, OD[25]_n3);
/* xor OD26(OD[26], ID[26], E[26]);*/
nand OD26_n1(OD[26]_n1, ID[26], E[26]);
nand OD26_n2(OD[26]_n2, ID[26], OD[26]_n1);
nand OD26_n3(OD[26]_n3, OD[26]_n1, E[26]);
nand OD26_n4(OD[26], OD[26]_n2, OD[26]_n3);
/* xor OD27(OD[27], ID[27], E[27]);*/
nand OD27_n1(OD[27]_n1, ID[27], E[27]);
nand OD27_n2(OD[27]_n2, ID[27], OD[27]_n1);
nand OD27_n3(OD[27]_n3, OD[27]_n1, E[27]);
nand OD27_n4(OD[27], OD[27]_n2, OD[27]_n3);
/* xor OD28(OD[28], ID[28], E[28]);*/
nand OD28_n1(OD[28]_n1, ID[28], E[28]);
nand OD28_n2(OD[28]_n2, ID[28], OD[28]_n1);
nand OD28_n3(OD[28]_n3, OD[28]_n1, E[28]);
nand OD28_n4(OD[28], OD[28]_n2, OD[28]_n3);
/* xor OD29(OD[29], ID[29], E[29]);*/
nand OD29_n1(OD[29]_n1, ID[29], E[29]);
nand OD29_n2(OD[29]_n2, ID[29], OD[29]_n1);
nand OD29_n3(OD[29]_n3, OD[29]_n1, E[29]);
nand OD29_n4(OD[29], OD[29]_n2, OD[29]_n3);
/* xor OD30(OD[30], ID[30], E[30]);*/
nand OD30_n1(OD[30]_n1, ID[30], E[30]);
nand OD30_n2(OD[30]_n2, ID[30], OD[30]_n1);
nand OD30_n3(OD[30]_n3, OD[30]_n1, E[30]);
nand OD30_n4(OD[30], OD[30]_n2, OD[30]_n3);
/* xor OD31(OD[31], ID[31], E[31]);*/
nand OD31_n1(OD[31]_n1, ID[31], E[31]);
nand OD31_n2(OD[31]_n2, ID[31], OD[31]_n1);
nand OD31_n3(OD[31]_n3, OD[31]_n1, E[31]);
nand OD31_n4(OD[31], OD[31]_n2, OD[31]_n3);
endmodule /* Correction */
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Added c1908/c1908.css.
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2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 | <HTML> <HEAD> <META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter"> <LINK REL="STYLESHEET" HREF="c1908.css"> <BODY BGCOLOR="#ffffff"> <TITLE> c1908 Benchmark Circuit </TITLE> </HEAD> <H1> <A NAME="pgfId=5"> </A> High-Level Model of c1908</H1> <br> <P> <B>Statistics: </B>33 inputs; 25 outputs; 880 gates</P> <P> <B>Function: </B> 16-bit error detector/corrector</P> <P> This is a 16-bit single-error-correcting and double-error-detecting (SEC/DED) circuit with some byte-error detection capability. It generates a 6-bit syndrome from the 16-bit data input IN, which is decoded to find the bit in error, if any. If an error is detected and the control inputs are set appropriately, error correction is performed. c1908 has an output indicating an uncorrectable error; this is set when more than one erroneous bit is detected. The circuit can also generate syndrome bits, which are sent out via the SC lines. The external syndrome lines make it possible to cascade several copies of c1908 so that detection and correction can be done for words of size greater than 16. This circuit is quite similar to the Advanced Micro Devices Am2960 16-bit error detection and correction unit. </P> <br> <A HREF="#pgfId=920223"> <B>Inputs/Outputs vs. Netlist Numbers</B></A> <HR> <B><P>Models:</P> </B> <UL> <LI>I. Original ISCAS gate-level netlist <UL> <LI><A HREF="c1908.isc">in ISCAS-89 format</A> </LI> <LI><A HREF="c1908gate.v">in Verilog</A></LI> </UL> </LI> <LI>II. <A HREF="c1908high.v">Verilog hierarchical netlist</A> (functionally equivalent to I) </LI> <LI>III. <A HREF="flat1908.v">Verilog flat netlist </A> (flat version of II; functionally equivalent to I, but with minor structural differences) </LI> </UL> <DIV> <MAP NAME="c1908"> </MAP> <IMG SRC="c1908-1.gif" USEMAP="#c1908"> </DIV> <P CLASS="Body"> <A NAME="pgfId=916443"> </A> <B>Major Input/Output/Internal Signals:</B></P> <UL> <LI CLASS="Bulleted"> <A NAME="pgfId=918075"> </A> IN[15:0] (InDataBus): 16-bit data input</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=918512"> </A> OUT[15:0] (OutDataBus): 16-bit data output</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=918521"> </A> InCheckBits[5:0]: input check bits</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=917429"> </A> SYN[5:0] (SynBits): 6-bit syndrome</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=918522"> </A> SYN'[5:0] (NewSynBits): modified syndrome (used internally)</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=918510"> </A> SC[5:0] (OutSynCheckBits): output syndrome or check bits</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=917435"> </A> InExtSynBits[3:0]: external syndrome inputs (used in cascaded mode to handle word size >16)</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=917436"> </A> BPH (ByteParHi), BPL (ByteParLo): Low- and high-byte parities</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=917437"> </A> UE : uncorrectable error</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=917459"> </A> E, B, F, G, H, K, L: control inputs</LI> <LI CLASS="Bulleted"> <B>Internal control signals:</B> <UL> <LI> M = (H + E). InCheckBits[1]</LI> <LI> P = (!G + E). InCheckBits[4]</LI> <LI> CH = !(GH). (!K.BE + F. !B)</LI> <LI> CL = !(GH). (!L.BE + F. !B)</LI> <LI> CUE = !(GH). F. !B</LI> </UL> </IL> </UL> <DIV> <IMG SRC="c1908-2.gif" USEMAP="#c1908"> </DIV> <P CLASS="Body"> <A NAME="pgfId=918538"> </A> <B>Modules:</B></P> <UL> <LI CLASS="Bulleted"> <A HREF="#pgfId=919287"> M1: generates a 6-bit syndrome (SYN[5:0])</A></LI> <LI CLASS="Bulleted"> <A HREF="#pgfId=918774"> M2: may modify the syndrome with external inputs; outputs SYN'[5:0]</A></LI> <LI CLASS="Bulleted"> <A HREF="#pgfId=919018"> M3: decodes the syndrome to identify the bit in error, if any</A></LI> <LI CLASS="Bulleted"> M4: corrects the input bit in error</LI> <LI CLASS="Bulleted"> M5: produces the output syndrome SC[5:0]</LI> <LI CLASS="Bulleted"> M6-M7: calculate a parity bit for the high (M6) and low byte (M7)</LI> <LI CLASS="Bulleted"> <A HREF="#pgfId=919031"> M8: asserts its output UE if an uncorrectable error is found in the input data bus</A></LI> </UL> <HR> <P CLASS="Body"> <A NAME="pgfId=919287"> </A> <B>Module M1 (SyndromeGenerator)</B></P> <P CLASS="Body"> <A NAME="pgfId=917463"> </A> This module generates a 6-bit syndrome (SYN) from the 16-bit input data bus (IN) and 6 input check bits (InCheckBits). The input check bits are modified with the control inputs G and H as follows:</P> <UL> <LI CLASS="Bulleted"> <A NAME="pgfId=918662"> </A> Check bit #0 = InCheckBits[0].G</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=918663"> </A> Check bit #1 = InCheckBits[1].!H</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=918670"> </A> Check bit #2 = InCheckBits[2].!H</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=918673"> </A> Check bit #3 = InCheckBits[3]</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=918676"> </A> Check bit #4 = InCheckBits[4].G</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=918679"> </A> Check bit #5 = InCheckBits[5]</LI> </UL> <P CLASS="Body"> <A NAME="pgfId=918690"> </A> The syndrome bits are calculated according to a modified Hamming matrix shown below.</P> <TABLE BORDER="1" CELLPADDING=4> <TR> <TH ROWSPAN="2" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916450"> </A> Output</P> </TH> <TH ROWSPAN="1" COLSPAN="16"> <P CLASS="CellHeading"> <A NAME="pgfId=916452"> </A> Data bits (IN)</P> </TH> <TH ROWSPAN="1" COLSPAN="6"> <P CLASS="CellHeading"> <A NAME="pgfId=916484"> </A> Check bits</P> </TH> </TR> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916498"> </A> 0</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916500"> </A> 1</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916502"> </A> 2</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916504"> </A> 3</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916506"> </A> 4</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916508"> </A> 5</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916510"> </A> 6</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916512"> </A> 7</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916514"> </A> 8</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916516"> </A> 9</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916518"> </A> 10</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916520"> </A> 11</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916522"> </A> 12</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916524"> </A> 13</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916526"> </A> 14</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=916528"> </A> 15</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=917418"> </A> #0</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=917420"> </A> #1</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=917422"> </A> #2</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=917424"> </A> #3</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=917426"> </A> #4</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=917428"> </A> #5</P> </TH> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916542"> </A> SYN[0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916544"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916546"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916548"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916550"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916552"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916554"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916556"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916558"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916560"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916562"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916564"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916566"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916568"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916570"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916572"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916574"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916576"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916578"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916580"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916582"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916584"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916586"> </A> .</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916588"> </A> SYN[1]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916590"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916592"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916594"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916596"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916598"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916600"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916602"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916604"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916606"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916608"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916610"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916612"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916614"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916616"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916618"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916620"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916622"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916624"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916626"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916628"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916630"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916632"> </A> .</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916634"> </A> SYN[2]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916636"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916638"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916640"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916642"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916644"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916646"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916648"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916650"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916652"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916654"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916656"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916658"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916660"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916662"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916664"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916666"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916668"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916670"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916672"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916674"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916676"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916678"> </A> .</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916680"> </A> SYN[3]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916682"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916684"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916686"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916688"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916690"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916692"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916694"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916696"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916698"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916700"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916702"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916704"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916706"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916708"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916710"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916712"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916714"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916716"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916718"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916720"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916722"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916724"> </A> .</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916726"> </A> SYN[4]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916728"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916730"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916732"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916734"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916736"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916738"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916740"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916742"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916744"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916746"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916748"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916750"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916752"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916754"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916756"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916758"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916760"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916762"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916764"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916766"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916768"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916770"> </A> .</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916772"> </A> SYN[5]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916774"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916776"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916778"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916780"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916782"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916784"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916786"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916788"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916790"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916792"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916794"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916796"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916798"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916800"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916802"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916804"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916806"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916808"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916810"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916812"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916814"> </A> .</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=916816"> </A> 1</P> </TD> </TR> </TABLE> <HR> <P CLASS="Body"> <A NAME="pgfId=918774"> </A> <B>Module M2 (ModifySyndrome)</B></P> <P CLASS="Body"> <A NAME="pgfId=919017"> </A> This module is used to change the 6-bit syndrome (SYN) generated by M1. Its output is called SYN'[5:0] (NewSynBits) that also depends on the control input E, and another bus named <i>AllExtSynBits</i>. The definition of AllExtSynBits[5:0] is as follows:</P> <UL> <LI CLASS="Bulleted"> <A NAME="pgfId=919389"> </A> AllExtSynBits[3:0] = InExtSynBits[3:0] (primary inputs)</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=919390"> </A> AllExtSynBits[4] = InCheckBits[0].(!G + E)</LI> <LI CLASS="Bulleted"> <A NAME="pgfId=919391"> </A> AllExtSynBits[5] = InCheckBits[2].(H + E)</LI> </UL> <P CLASS="Body"> <A NAME="pgfId=919386"> </A> The AllExtSynBits bus appears to be an external set of syndrome inputs that can override the syndrome (SYN) when E is set to 1. Otherwise the SYN' output is the XNOR of SYN and AllExtSynBits. The ability of c1908 to change the calculated syndrome is probably exercised when it is cascaded to handle words of size greater than 16. When E is set to 0 and AllExtSynBits are all 1's, the syndrome goes through M2 unchanged.</P> <HR> <P CLASS="Body"> <A NAME="pgfId=919018"> </A> <B>Module M3 (SyndromeDecode)</B></P> <P CLASS="Body"> <A NAME="pgfId=919015"> </A> This module consists of 16 AND gates that decode the syndrome bits to identify the erroneous bit, if there is one. It matches the syndrome bits against the columns of the above Hamming matrix. The product term calculated by each AND gate is shown in the following table.</P> <TABLE BORDER="1"> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=918778"> </A> Output</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=918780"> </A> SYN'[0]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=918782"> </A> SYN'[1]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=918784"> </A> SYN'[2]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=918786"> </A> SYN'[3]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=918788"> </A> SYN'[4]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=918790"> </A> SYN'[5]</P> </TH> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918792"> </A> R0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918794"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918796"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918798"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918800"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918802"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918804"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918806"> </A> R1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918808"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918810"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918812"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918814"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918816"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918818"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918820"> </A> R2</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918822"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918824"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918826"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918828"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918830"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918832"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918834"> </A> R3</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918836"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918838"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918840"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918842"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918844"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918846"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918848"> </A> R4</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918850"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918852"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918854"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918856"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918858"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918860"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918862"> </A> R5</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918864"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918866"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918868"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918870"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918872"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918874"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918876"> </A> R6</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918878"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918880"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918882"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918884"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918886"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918888"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918890"> </A> R7</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918892"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918894"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918896"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918898"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918900"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918902"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918904"> </A> R8</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918906"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918908"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918910"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918912"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918914"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918916"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918918"> </A> R9</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918920"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918922"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918924"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918926"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918928"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918930"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918932"> </A> R10</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918934"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918936"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918938"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918940"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918942"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918944"> </A> 0</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918946"> </A> R11</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918948"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918950"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918952"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918954"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918956"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918958"> </A> 0</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918960"> </A> R12</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918962"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918964"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918966"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918968"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918970"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918972"> </A> 0</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918974"> </A> R13</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918976"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918978"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918980"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918982"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918984"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918986"> </A> 0</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918988"> </A> R14</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918990"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918992"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918994"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918996"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=918998"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919000"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919002"> </A> R15</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919004"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919006"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919008"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919010"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919012"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919014"> </A> 1</P> </TD> </TR> </TABLE> <P CLASS="Body"> <A NAME="pgfId=917057"> </A> If bit <i>i</i> is in error, then Ri will be set to 1, while all the others are 0. Notice that the rows of the above table are identical to the columns of the modified Hamming matrix.</P> <P CLASS="Body"> <A NAME="pgfId=919253"> </A> Module M3 generates three additional signals called <i>CorrectionFlag</i>, <i>CorrectionFlagLo</i> and <i>CorrectionFlagHi</i> that are fed into modules M5, M6, M7 and M8. <i>CorrectionFlag</i> is the OR of R0-R15, which is set to 1 when any bit is in error. <i>CorrectionFlagLo</i> is the OR of R0-R7, which is set to 1 only when the lower byte includes the erroneous bit. Similarly, <i>CorrectionFlagHi</i> is the OR of R8-R15, which is set to 1 only when the upper byte includes the erroneous bit. </P> <HR> <P CLASS="Body"> <A NAME="pgfId=919031"> </A> <B>Module M8 (UncorrErrorGenerator)</B></P> <P CLASS="Body"> <A NAME="pgfId=919033"> </A> When an error is found in the data input or check bits, this module identifies whether it is an uncorrectable one. For certain cases of multiple errors, correction is not possible, but its occurrence can be signaled so that the problem can be handled by other means. If such a case is found, the output of M8 is asserted. The following term calculated by M8 evaluates to true when there is no error in any bit:</P> <P CLASS="Body"> <A NAME="pgfId=919192"> </A> SYN'[0].SYN'[1].SYN'[2].SYN'[3].SYN'[4].SYN'[5].M.P</P> <P CLASS="Body"> <A NAME="pgfId=919191"> </A> It is a sub-module named <B>UEGen</B> that detects if there is an uncorrectable error condition. There are 8 cases of uncorrectable error, each of which is calculated by an AND gate. The product terms for these 8 cases are given below.</P> <TABLE BORDER="1" CELLPADDING=5> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=919036"> </A> -M-</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=919038"> </A> -P-</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=919040"> </A> SYN'[0]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=919042"> </A> SYN'[1]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=919044"> </A> SYN'[2]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=919046"> </A> SYN'[3]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=919048"> </A> SYN'[4]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=919050"> </A> SYN'[5]</P> </TH> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919052"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919054"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919056"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919058"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919060"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919062"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919064"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919066"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919068"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919070"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919072"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919074"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919076"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919078"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919080"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919082"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919084"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919086"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919088"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919090"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919092"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919094"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919096"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919098"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919100"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919102"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919104"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919106"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919108"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919110"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919112"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919114"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919116"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919118"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919120"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919122"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919124"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919126"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919128"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919130"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919132"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919134"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919136"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919138"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919140"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919142"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919144"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919146"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919148"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919150"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919152"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919154"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919156"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919158"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919160"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919162"> </A> 1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919164"> </A> 0</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919166"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919168"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919170"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919172"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919174"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919176"> </A> 1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=919178"> </A> 1</P> </TD> </TR> </TABLE> <HR> <P CLASS="Body"> <A NAME="pgfId=920223"> </A> </P> <TABLE BORDER="2" WIDTH=600> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=920227"> </A> Inputs</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=920229"> </A> Netlist number</P> </TH> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920231"> </A> InDataBus[15:0] (IN)</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920233"> </A> 146, 143, 140, 137, 134, 131, 128, 125, 122, 119, 116, 113, 110, 107, 104, 101</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920235"> </A> InCheckBits[5:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920237"> </A> 224, 221, 227, 210, 214, 217</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920239"> </A> InExtSynBits[3:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920241"> </A> 469, 472, 475, 478</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920243"> </A> E,B,F (control inputs)</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920245"> </A> 902, 953, 952</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920247"> </A> G,H,K,L (control inputs)</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920249"> </A> 234, 237, 898, 900</P> </TD> </TR> </TABLE> <P CLASS="Body"> <A NAME="pgfId=920189"> </A> </P> <TABLE BORDER="2"> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=920197"> </A> Outputs</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=920199"> </A> Netlist number</P> </TH> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920201"> </A> OutDataBus[15:0] (OUT)</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920203"> </A> 48, 45, 42, 39, 36, 33, 30, 27, 24, 21, 18, 15, 12, 9, 6, 3</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920205"> </A> OutSynCheckBits[5:0] (SC)</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920207"> </A> 51, 66, 54, 57, 60, 63</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920209"> </A> ByteParHi (BPH)</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920211"> </A> 72</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920213"> </A> ByteParLo (BPL)</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920215"> </A> 69</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920217"> </A> UncorrError (UE)</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=920219"> </A> 75</P> </TD> </TR> </TABLE> <br> <P> <A HREF="#pgfId=5"> Go to top of this file</A></P> <P> <A HREF="../benchmark.html"> Go back to the Benchmark List</A></P> </BODY> </HTML> |
Added c1908/c1908.isc.
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 | # combinational logic example "c1908" #------------------------------------------------------------- # # # total number of lines in the netlist .............. 1908 # simplistically reduced equivalent fault set size = 1879 # lines from primary input gates ....... 33 # lines from primary output gates ....... 25 # lines from interior gate outputs ...... 855 # lines from ** 385 ** fanout stems ... 995 # # avg_fanin = 1.70, max_fanin = 8 # avg_fanout = 2.58, max_fanout = 16 # # # # # INPUT(101) #... primary input INPUT(104) #... primary input INPUT(107) #... primary input INPUT(110) #... primary input INPUT(113) #... primary input INPUT(116) #... primary input INPUT(119) #... primary input INPUT(122) #... primary input INPUT(125) #... primary input INPUT(128) #... primary input INPUT(131) #... primary input INPUT(134) #... primary input INPUT(137) #... primary input INPUT(140) #... primary input INPUT(143) #... primary input INPUT(146) #... primary input INPUT(210) #... primary input INPUT(214) #... primary input INPUT(217) #... primary input INPUT(221) #... primary input INPUT(224) #... primary input INPUT(227) #... primary input INPUT(234) #... primary input INPUT(237) #... primary input INPUT(469) #... primary input INPUT(472) #... primary input INPUT(475) #... primary input INPUT(478) #... primary input INPUT(898) #... primary input INPUT(900) #... primary input INPUT(902) #... primary input INPUT(952) #... primary input INPUT(953) #... primary input # # OUTPUT(3) #... primary output OUTPUT(6) #... primary output OUTPUT(9) #... primary output OUTPUT(12) #... primary output OUTPUT(30) #... primary output OUTPUT(45) #... primary output OUTPUT(48) #... primary output OUTPUT(15) #... primary output OUTPUT(18) #... primary output OUTPUT(21) #... primary output OUTPUT(24) #... primary output OUTPUT(27) #... primary output OUTPUT(33) #... primary output OUTPUT(36) #... primary output OUTPUT(39) #... primary output OUTPUT(42) #... primary output OUTPUT(75) #... primary output OUTPUT(51) #... primary output OUTPUT(54) #... primary output OUTPUT(60) #... primary output OUTPUT(63) #... primary output OUTPUT(66) #... primary output OUTPUT(69) #... primary output OUTPUT(72) #... primary output OUTPUT(57) #... primary output # # # Output Type Inputs... # ------ ---- --------- 149 = not( 101) 153 = not( 104) 156 = not( 107) 160 = not( 110) 165 = not( 113) 168 = not( 116) 171 = not( 119) 175 = not( 122) 179 = not( 125) 184 = not( 128) 188 = not( 131) 191 = not( 134) 194 = not( 137) 198 = not( 140) 202 = not( 143) 206 = not( 146) 231 = nand( 224, 898) 233 = nand( 227, 900) 241 = not( 237) 244 = not( 237) 245 = buff( 234) 248 = buff( 234) 517 = not( 469) 529 = not( 472) 541 = not( 475) 553 = not( 478) 859 = not( 953) 862 = not( 953) 907 = not( 898) 909 = not( 900) 911 = buff( 902) 918 = not( 902) 919 = buff( 902) 922 = not( 902) 926 = buff( 952) 930 = not( 952) 932 = not( 952) 934 = buff( 953) 938 = not( 953) 943 = buff( 953) 947 = buff( 953) 949 = not( 953) 1506 = buff( 101) 1514 = buff( 104) 1522 = buff( 107) 1530 = buff( 110) 1538 = buff( 113) 1546 = buff( 116) 1554 = buff( 119) 1562 = buff( 122) 1570 = buff( 125) 1578 = buff( 128) 1586 = buff( 131) 1594 = buff( 134) 1602 = buff( 137) 1610 = buff( 140) 1618 = buff( 143) 1626 = buff( 146) 1512 = not( 1506) 1520 = not( 1514) 1528 = not( 1522) 1536 = not( 1530) 1544 = not( 1538) 1552 = not( 1546) 1560 = not( 1554) 1568 = not( 1562) 1576 = not( 1570) 1584 = not( 1578) 1592 = not( 1586) 1600 = not( 1594) 1608 = not( 1602) 1616 = not( 1610) 1624 = not( 1618) 1632 = not( 1626) 50 = nand( 930, 947) 52 = nand( 930, 947) 56 = nand( 930, 947) 58 = nand( 930, 947) 62 = nand( 930, 947) 64 = nand( 930, 947) 251 = buff( 149) 254 = buff( 153) 288 = buff( 165) 291 = buff( 168) 299 = buff( 184) 302 = buff( 202) 318 = and( 224, 938) 321 = buff( 179) 327 = buff( 188) 330 = buff( 191) 352 = and( 227, 938) 355 = buff( 198) 369 = and( 210, 241, 938) 382 = buff( 206) 385 = buff( 198) 853 = nand( 943, 907) 856 = nand( 943, 909) 893 = nand( 248, 237) 954 = nand( 248, 922) 955 = nand( 244, 922) 1050 = buff( 160) 1053 = buff( 175) 1176 = buff( 179) 1179 = buff( 198) 1197 = buff( 149) 1207 = buff( 149) 1222 = buff( 153) 1244 = buff( 188) 1278 = buff( 156) 1290 = and( 217, 245, 938) 1300 = buff( 191) 1312 = buff( 160) 1332 = buff( 194) 1335 = and( 221, 245, 938) 1442 = buff( 517) 1450 = buff( 517) 1458 = buff( 529) 1466 = buff( 529) 1474 = buff( 541) 1482 = buff( 541) 1490 = buff( 553) 1498 = buff( 553) 1634 = and( 231, 934) 1644 = and( 233, 934) 1657 = buff( 156) 1665 = buff( 156) 1697 = buff( 171) 1705 = buff( 171) 1713 = buff( 206) 1721 = buff( 206) 1745 = buff( 194) 1753 = buff( 194) 1785 = buff( 160) 1793 = buff( 160) 1814 = buff( 165) 1817 = buff( 175) 1830 = and( 214, 241, 938) 1833 = buff( 202) 1841 = buff( 179) 1849 = buff( 179) 1854 = buff( 168) 1857 = buff( 175) 1870 = buff( 184) 1873 = buff( 202) 1878 = buff( 171) 1881 = buff( 184) 1642 = not( 1634) 1652 = not( 1644) 1056 = not( 1050) 1057 = not( 1053) 1182 = not( 1176) 1183 = not( 1179) 1211 = not( 1207) 1298 = not( 1290) 1320 = not( 1312) 1338 = not( 1332) 1339 = not( 1335) 457 = and( 210, 955) 459 = and( 217, 954) 482 = nand( 214, 955) 487 = nand( 221, 954) 492 = nand( 210, 955) 505 = nand( 217, 954) 1456 = not( 1450) 1448 = not( 1442) 1472 = not( 1466) 1464 = not( 1458) 1488 = not( 1482) 1480 = not( 1474) 1504 = not( 1498) 1496 = not( 1490) 956 = nand( 907, 919, 943, 893) 967 = nand( 909, 919, 943, 893) 978 = nand( 926, 949, 893) 979 = and( 926, 949, 893) 980 = buff( 251) 1661 = not( 1657) 990 = buff( 251) 1669 = not( 1665) 1030 = buff( 288) 1701 = not( 1697) 1040 = buff( 288) 1709 = not( 1705) 1058 = buff( 299) 1717 = not( 1713) 1068 = buff( 299) 1725 = not( 1721) 1078 = buff( 318) 1090 = buff( 318) 1100 = buff( 327) 1749 = not( 1745) 1112 = buff( 327) 1757 = not( 1753) 1154 = buff( 352) 1789 = not( 1785) 1166 = buff( 352) 1797 = not( 1793) 1194 = buff( 369) 1201 = not( 1197) 1204 = buff( 369) 1820 = not( 1814) 1821 = not( 1817) 1230 = not( 1222) 1836 = not( 1830) 1837 = not( 1833) 1252 = not( 1244) 1256 = buff( 382) 1845 = not( 1841) 1268 = buff( 382) 1853 = not( 1849) 1860 = not( 1854) 1861 = not( 1857) 1286 = not( 1278) 1876 = not( 1870) 1877 = not( 1873) 1308 = not( 1300) 1884 = not( 1878) 1885 = not( 1881) 1654 = buff( 254) 1662 = buff( 254) 1694 = buff( 291) 1702 = buff( 291) 1710 = buff( 302) 1718 = buff( 302) 1726 = buff( 321) 1734 = buff( 321) 1742 = buff( 330) 1750 = buff( 330) 1782 = buff( 355) 1790 = buff( 355) 1838 = buff( 385) 1846 = buff( 385) 297 = nand( 1053, 1056) 298 = nand( 1050, 1057) 361 = nand( 1179, 1182) 362 = nand( 1176, 1183) 404 = nand( 1335, 1338) 405 = nand( 1332, 1339) 1225 = nand( 1817, 1820) 1226 = nand( 1814, 1821) 1247 = nand( 1833, 1836) 1248 = nand( 1830, 1837) 1281 = nand( 1857, 1860) 1282 = nand( 1854, 1861) 1303 = nand( 1873, 1876) 1304 = nand( 1870, 1877) 1315 = nand( 1881, 1884) 1316 = nand( 1878, 1885) 998 = not( 990) 988 = not( 980) 268 = nand( 297, 298) 1038 = not( 1030) 1048 = not( 1040) 1076 = not( 1068) 1066 = not( 1058) 1098 = not( 1090) 1120 = not( 1112) 1174 = not( 1166) 363 = nand( 361, 362) 1210 = not( 1204) 373 = nand( 1204, 1211) 1276 = not( 1268) 406 = nand( 404, 405) 565 = not( 482) 566 = buff( 482) 614 = not( 487) 615 = buff( 487) 958 = nand( 956, 978) 969 = nand( 967, 978) 1660 = not( 1654) 984 = nand( 1654, 1661) 1668 = not( 1662) 994 = nand( 1662, 1669) 1700 = not( 1694) 1034 = nand( 1694, 1701) 1708 = not( 1702) 1044 = nand( 1702, 1709) 1716 = not( 1710) 1062 = nand( 1710, 1717) 1724 = not( 1718) 1072 = nand( 1718, 1725) 1732 = not( 1726) 1086 = not( 1078) 1740 = not( 1734) 1748 = not( 1742) 1104 = nand( 1742, 1749) 1108 = not( 1100) 1756 = not( 1750) 1116 = nand( 1750, 1757) 1788 = not( 1782) 1158 = nand( 1782, 1789) 1162 = not( 1154) 1796 = not( 1790) 1170 = nand( 1790, 1797) 1200 = not( 1194) 1203 = nand( 1194, 1201) 1227 = nand( 1225, 1226) 1249 = nand( 1247, 1248) 1844 = not( 1838) 1260 = nand( 1838, 1845) 1264 = not( 1256) 1852 = not( 1846) 1272 = nand( 1846, 1853) 1283 = nand( 1281, 1282) 1305 = nand( 1303, 1304) 1317 = nand( 1315, 1316) 1410 = buff( 492) 1418 = buff( 492) 1426 = buff( 505) 1434 = buff( 505) 269 = not( 268) 372 = nand( 1207, 1210) 983 = nand( 1657, 1660) 993 = nand( 1665, 1668) 1033 = nand( 1697, 1700) 1043 = nand( 1705, 1708) 1061 = nand( 1713, 1716) 1071 = nand( 1721, 1724) 1103 = nand( 1745, 1748) 1115 = nand( 1753, 1756) 1157 = nand( 1785, 1788) 1169 = nand( 1793, 1796) 1184 = not( 363) 1202 = nand( 1197, 1200) 1259 = nand( 1841, 1844) 1271 = nand( 1849, 1852) 1322 = not( 406) 374 = nand( 372, 373) 396 = nand( 1317, 1320) 1321 = not( 1317) 1424 = not( 1418) 1416 = not( 1410) 1440 = not( 1434) 1432 = not( 1426) 985 = nand( 983, 984) 995 = nand( 993, 994) 1035 = nand( 1033, 1034) 1045 = nand( 1043, 1044) 1063 = nand( 1061, 1062) 1073 = nand( 1071, 1072) 1105 = nand( 1103, 1104) 1117 = nand( 1115, 1116) 1159 = nand( 1157, 1158) 1171 = nand( 1169, 1170) 1212 = nand( 1202, 1203) 1231 = not( 1227) 1232 = nand( 1227, 1230) 1253 = not( 1249) 1254 = nand( 1249, 1252) 1261 = nand( 1259, 1260) 1273 = nand( 1271, 1272) 1287 = not( 1283) 1288 = nand( 1283, 1286) 1309 = not( 1305) 1310 = nand( 1305, 1308) 1192 = not( 1184) 397 = nand( 1312, 1321) 1330 = not( 1322) 1000 = buff( 269) 1010 = buff( 269) 1233 = nand( 1222, 1231) 1255 = nand( 1244, 1253) 1289 = nand( 1278, 1287) 1311 = nand( 1300, 1309) 1381 = not( 374) 257 = nand( 995, 998) 999 = not( 995) 260 = nand( 985, 988) 989 = not( 985) 272 = nand( 1035, 1038) 1039 = not( 1035) 294 = nand( 1045, 1048) 1049 = not( 1045) 305 = nand( 1073, 1076) 1077 = not( 1073) 308 = nand( 1063, 1066) 1067 = not( 1063) 333 = nand( 1117, 1120) 1121 = not( 1117) 358 = nand( 1171, 1174) 1175 = not( 1171) 1220 = not( 1212) 388 = nand( 1273, 1276) 1277 = not( 1273) 398 = nand( 396, 397) 1109 = not( 1105) 1110 = nand( 1105, 1108) 1163 = not( 1159) 1164 = nand( 1159, 1162) 1234 = nand( 1232, 1233) 1265 = not( 1261) 1266 = nand( 1261, 1264) 1822 = nand( 1254, 1255) 1862 = nand( 1310, 1311) 1865 = nand( 1288, 1289) 258 = nand( 990, 999) 261 = nand( 980, 989) 273 = nand( 1030, 1039) 1018 = not( 1010) 1008 = not( 1000) 295 = nand( 1040, 1049) 306 = nand( 1068, 1077) 309 = nand( 1058, 1067) 334 = nand( 1112, 1121) 359 = nand( 1166, 1175) 389 = nand( 1268, 1277) 1385 = not( 1381) 1111 = nand( 1100, 1109) 1165 = nand( 1154, 1163) 1267 = nand( 1256, 1265) 1886 = not( 398) 259 = nand( 257, 258) 262 = nand( 260, 261) 274 = nand( 272, 273) 296 = nand( 294, 295) 307 = nand( 305, 306) 310 = nand( 308, 309) 335 = nand( 333, 334) 360 = nand( 358, 359) 1242 = not( 1234) 390 = nand( 388, 389) 1828 = not( 1822) 1868 = not( 1862) 1869 = not( 1865) 1373 = nand( 1164, 1165) 1798 = nand( 1110, 1111) 1825 = nand( 1266, 1267) 265 = not( 259) 314 = not( 307) 336 = not( 335) 407 = not( 296) 1293 = nand( 1865, 1868) 1294 = nand( 1862, 1869) 1892 = not( 1886) 1777 = not( 360) 1889 = not( 390) 410 = buff( 310) 1377 = not( 1373) 1804 = not( 1798) 1237 = nand( 1825, 1828) 1829 = not( 1825) 1295 = nand( 1293, 1294) 1670 = buff( 274) 1678 = buff( 274) 1729 = buff( 310) 1737 = buff( 310) 1761 = buff( 262) 1769 = buff( 262) 340 = buff( 336) 343 = buff( 314) 1781 = not( 1777) 1238 = nand( 1822, 1829) 1325 = nand( 1889, 1892) 1893 = not( 1889) 1340 = buff( 407) 1352 = buff( 407) 1673 = buff( 265) 1681 = buff( 265) 1801 = buff( 314) 1897 = buff( 336) 1905 = buff( 336) 391 = nand( 1295, 1298) 1299 = not( 1295) 1676 = not( 1670) 1684 = not( 1678) 1081 = nand( 1729, 1732) 1733 = not( 1729) 1093 = nand( 1737, 1740) 1741 = not( 1737) 1765 = not( 1761) 1773 = not( 1769) 1239 = nand( 1237, 1238) 1326 = nand( 1886, 1893) 1894 = buff( 410) 1902 = buff( 410) 392 = nand( 1290, 1299) 1360 = not( 1352) 1003 = nand( 1673, 1676) 1677 = not( 1673) 1013 = nand( 1681, 1684) 1685 = not( 1681) 1082 = nand( 1726, 1733) 1094 = nand( 1734, 1741) 1122 = buff( 340) 1134 = buff( 340) 1187 = nand( 1801, 1804) 1805 = not( 1801) 1327 = nand( 1325, 1326) 1901 = not( 1897) 1348 = not( 1340) 1909 = not( 1905) 1758 = buff( 343) 1766 = buff( 343) 377 = nand( 1239, 1242) 1243 = not( 1239) 393 = nand( 391, 392) 1004 = nand( 1670, 1677) 1014 = nand( 1678, 1685) 1083 = nand( 1081, 1082) 1095 = nand( 1093, 1094) 1188 = nand( 1798, 1805) 1900 = not( 1894) 1344 = nand( 1894, 1901) 1908 = not( 1902) 1356 = nand( 1902, 1909) 1142 = not( 1134) 378 = nand( 1234, 1243) 399 = nand( 1327, 1330) 1331 = not( 1327) 1005 = nand( 1003, 1004) 1015 = nand( 1013, 1014) 1764 = not( 1758) 1126 = nand( 1758, 1765) 1130 = not( 1122) 1772 = not( 1766) 1138 = nand( 1766, 1773) 1189 = nand( 1187, 1188) 1343 = nand( 1897, 1900) 1355 = nand( 1905, 1908) 324 = nand( 1095, 1098) 1099 = not( 1095) 379 = nand( 377, 378) 400 = nand( 1322, 1331) 449 = nand( 393, 918) 1087 = not( 1083) 1088 = nand( 1083, 1086) 1125 = nand( 1761, 1764) 1137 = nand( 1769, 1772) 1345 = nand( 1343, 1344) 1357 = nand( 1355, 1356) 1397 = buff( 393) 277 = nand( 1015, 1018) 1019 = not( 1015) 280 = nand( 1005, 1008) 1009 = not( 1005) 325 = nand( 1090, 1099) 364 = nand( 1189, 1192) 1193 = not( 1189) 401 = nand( 399, 400) 1089 = nand( 1078, 1087) 1127 = nand( 1125, 1126) 1139 = nand( 1137, 1138) 278 = nand( 1010, 1019) 281 = nand( 1000, 1009) 326 = nand( 324, 325) 365 = nand( 1184, 1193) 413 = nand( 1357, 1360) 1361 = not( 1357) 1401 = not( 1397) 445 = nand( 379, 918) 1349 = not( 1345) 1350 = nand( 1345, 1348) 1389 = buff( 379) 1493 = buff( 449) 1501 = buff( 449) 1689 = nand( 1088, 1089) 279 = nand( 277, 278) 282 = nand( 280, 281) 346 = nand( 1139, 1142) 1143 = not( 1139) 366 = nand( 364, 365) 414 = nand( 1352, 1361) 453 = nand( 401, 918) 1131 = not( 1127) 1132 = nand( 1127, 1130) 1351 = nand( 1340, 1349) 1365 = not( 326) 1405 = buff( 401) 285 = not( 279) 347 = nand( 1134, 1143) 367 = not( 366) 415 = nand( 413, 414) 1393 = not( 1389) 556 = nand( 1501, 1504) 1505 = not( 1501) 559 = nand( 1493, 1496) 1497 = not( 1493) 1693 = not( 1689) 1133 = nand( 1122, 1131) 1477 = buff( 445) 1485 = buff( 445) 1809 = nand( 1350, 1351) 348 = nand( 346, 347) 1369 = not( 1365) 1409 = not( 1405) 557 = nand( 1498, 1505) 560 = nand( 1490, 1497) 1362 = buff( 282) 1378 = not( 415) 1429 = buff( 453) 1437 = buff( 453) 1686 = buff( 282) 1774 = nand( 1132, 1133) 1910 = and( 285, 853) 1918 = and( 856, 367) 544 = nand( 1485, 1488) 1489 = not( 1485) 547 = nand( 1477, 1480) 1481 = not( 1477) 558 = nand( 556, 557) 561 = nand( 559, 560) 1813 = not( 1809) 1370 = not( 348) 1368 = not( 1362) 417 = nand( 1362, 1369) 1384 = not( 1378) 424 = nand( 1378, 1385) 508 = nand( 1437, 1440) 1441 = not( 1437) 511 = nand( 1429, 1432) 1433 = not( 1429) 545 = nand( 1482, 1489) 548 = nand( 1474, 1481) 564 = not( 558) 1692 = not( 1686) 1024 = nand( 1686, 1693) 1780 = not( 1774) 1148 = nand( 1774, 1781) 1916 = not( 1910) 1924 = not( 1918) 416 = nand( 1365, 1368) 1376 = not( 1370) 421 = nand( 1370, 1377) 423 = nand( 1381, 1384) 509 = nand( 1434, 1441) 512 = nand( 1426, 1433) 546 = nand( 544, 545) 549 = nand( 547, 548) 719 = not( 561) 722 = buff( 561) 1023 = nand( 1689, 1692) 1147 = nand( 1777, 1780) 418 = nand( 416, 417) 420 = nand( 1373, 1376) 425 = nand( 423, 424) 510 = nand( 508, 509) 513 = nand( 511, 512) 552 = not( 546) 1025 = nand( 1023, 1024) 1149 = nand( 1147, 1148) 419 = not( 418) 422 = nand( 420, 421) 441 = nand( 425, 918) 516 = not( 510) 725 = not( 549) 728 = buff( 549) 1029 = not( 1025) 1153 = not( 1149) 433 = nand( 419, 918) 437 = nand( 422, 918) 663 = not( 513) 666 = buff( 513) 731 = and( 719, 725) 746 = and( 722, 725) 756 = and( 719, 728) 770 = and( 722, 728) 1461 = buff( 441) 1469 = buff( 441) 1413 = buff( 433) 1421 = buff( 433) 1445 = buff( 437) 1453 = buff( 437) 532 = nand( 1469, 1472) 1473 = not( 1469) 535 = nand( 1461, 1464) 1465 = not( 1461) 495 = nand( 1421, 1424) 1425 = not( 1421) 498 = nand( 1413, 1416) 1417 = not( 1413) 520 = nand( 1453, 1456) 1457 = not( 1453) 523 = nand( 1445, 1448) 1449 = not( 1445) 533 = nand( 1466, 1473) 536 = nand( 1458, 1465) 496 = nand( 1418, 1425) 499 = nand( 1410, 1417) 521 = nand( 1450, 1457) 524 = nand( 1442, 1449) 534 = nand( 532, 533) 537 = nand( 535, 536) 497 = nand( 495, 496) 500 = nand( 498, 499) 522 = nand( 520, 521) 525 = nand( 523, 524) 540 = not( 534) 503 = not( 497) 528 = not( 522) 669 = not( 537) 672 = buff( 537) 569 = not( 500) 588 = and( 566, 500) 618 = not( 525) 639 = and( 615, 525) 867 = nand( 516, 564, 552, 540, 482, 528, 503, 487) 588a = buff( 588) 588b = buff( 588) 639a = buff( 639) 639b = buff( 639) 675 = and( 663, 669) 688 = and( 666, 669) 696 = and( 663, 672) 710 = and( 666, 672) 73 = and( 949, 867, 932, 932) 572 = and( 565, 569) 573 = and( 566, 569) 621 = and( 614, 618) 622 = and( 615, 618) 776 = nand( 588a, 639a, 696, 731, 958) 780 = nand( 588a, 639a, 675, 756, 958) 784 = nand( 588a, 639a, 675, 746, 958) 788 = nand( 588a, 639a, 688, 731, 958) 812 = nand( 588b, 639a, 710, 746, 969) 832 = nand( 588b, 639b, 696, 770, 969) 836 = nand( 588b, 639b, 710, 756, 969) 1509 = and( 588a, 639a, 696, 731, 958) 1517 = and( 588a, 639a, 675, 756, 958) 1525 = and( 588a, 639a, 675, 746, 958) 1533 = and( 588a, 639a, 688, 731, 958) 1581 = and( 588b, 639a, 710, 746, 969) 1621 = and( 588b, 639b, 696, 770, 969) 1629 = and( 588b, 639b, 710, 756, 969) 792 = nand( 588a, 622, 696, 756, 958) 796 = nand( 588b, 622, 696, 746, 958) 800 = nand( 588b, 622, 710, 731, 958) 804 = nand( 588b, 622, 675, 770, 958) 808 = nand( 588b, 622, 688, 756, 969) 816 = nand( 573, 639b, 696, 756, 969) 820 = nand( 573, 639b, 696, 746, 969) 824 = nand( 573, 639b, 710, 731, 969) 828 = nand( 573, 639b, 688, 756, 969) 871 = nand( 588b, 622, 675, 731, 979) 873 = nand( 573, 639b, 675, 731, 979) 875 = nand( 573, 622, 696, 731, 979) 877 = nand( 573, 622, 675, 756, 979) 879 = nand( 573, 622, 675, 746, 979) 881 = nand( 573, 622, 688, 731, 979) 883 = nand( 573, 621, 675, 731, 979) 885 = nand( 572, 622, 675, 731, 979) 1541 = and( 588a, 622, 696, 756, 958) 1549 = and( 588b, 622, 696, 746, 958) 1557 = and( 588b, 622, 710, 731, 958) 1565 = and( 588b, 622, 675, 770, 958) 1573 = and( 588b, 622, 688, 756, 969) 1589 = and( 573, 639b, 696, 756, 969) 1597 = and( 573, 639b, 696, 746, 969) 1605 = and( 573, 639b, 710, 731, 969) 1613 = and( 573, 639b, 688, 756, 969) 1 = nand( 1509, 1512) 1513 = not( 1509) 4 = nand( 1517, 1520) 1521 = not( 1517) 7 = nand( 1525, 1528) 1529 = not( 1525) 10 = nand( 1533, 1536) 1537 = not( 1533) 28 = nand( 1581, 1584) 1585 = not( 1581) 43 = nand( 1621, 1624) 1625 = not( 1621) 46 = nand( 1629, 1632) 1633 = not( 1629) 886 = and( 871, 873, 875, 877, 879, 881, 883, 885) 2 = nand( 1506, 1513) 5 = nand( 1514, 1521) 8 = nand( 1522, 1529) 11 = nand( 1530, 1537) 13 = nand( 1541, 1544) 1545 = not( 1541) 16 = nand( 1549, 1552) 1553 = not( 1549) 19 = nand( 1557, 1560) 1561 = not( 1557) 22 = nand( 1565, 1568) 1569 = not( 1565) 25 = nand( 1573, 1576) 1577 = not( 1573) 29 = nand( 1578, 1585) 31 = nand( 1589, 1592) 1593 = not( 1589) 34 = nand( 1597, 1600) 1601 = not( 1597) 37 = nand( 1605, 1608) 1609 = not( 1605) 40 = nand( 1613, 1616) 1617 = not( 1613) 44 = nand( 1618, 1625) 47 = nand( 1626, 1633) 857 = nand( 776, 780, 784, 788, 792, 796, 800, 804) 860 = nand( 808, 812, 816, 820, 824, 828, 832, 836) 863 = and( 776, 780, 784, 788, 792, 796, 800, 804) 865 = and( 808, 812, 816, 820, 824, 828, 832, 836) 3 = nand( 1, 2) 6 = nand( 4, 5) 9 = nand( 7, 8) 12 = nand( 10, 11) 14 = nand( 1538, 1545) 17 = nand( 1546, 1553) 20 = nand( 1554, 1561) 23 = nand( 1562, 1569) 26 = nand( 1570, 1577) 30 = nand( 28, 29) 32 = nand( 1586, 1593) 35 = nand( 1594, 1601) 38 = nand( 1602, 1609) 41 = nand( 1610, 1617) 45 = nand( 43, 44) 48 = nand( 46, 47) 1913 = and( 857, 859) 1921 = and( 860, 862) 15 = nand( 13, 14) 18 = nand( 16, 17) 21 = nand( 19, 20) 24 = nand( 22, 23) 27 = nand( 25, 26) 33 = nand( 31, 32) 36 = nand( 34, 35) 39 = nand( 37, 38) 42 = nand( 40, 41) 887 = and( 863, 865, 886) 462 = nand( 863, 865) 74 = and( 949, 867, 952, 887) 1637 = nand( 1913, 1916) 1917 = not( 1913) 1647 = nand( 1921, 1924) 1925 = not( 1921) 75 = nor( 73, 74) 1020 = and( 457, 911, 462) 1144 = and( 469, 911, 462) 1386 = and( 475, 911, 462) 1394 = and( 478, 911, 462) 1402 = and( 459, 911, 462) 1638 = nand( 1910, 1917) 1648 = nand( 1918, 1925) 1806 = and( 472, 911, 462) 1639 = nand( 1637, 1638) 1649 = nand( 1647, 1648) 287 = nand( 1020, 1029) 350 = nand( 1144, 1153) 427 = nand( 1386, 1393) 429 = nand( 1394, 1401) 431 = nand( 1402, 1409) 1028 = not( 1020) 1152 = not( 1144) 1392 = not( 1386) 1400 = not( 1394) 1408 = not( 1402) 1812 = not( 1806) 1216 = nand( 1806, 1813) 286 = nand( 1025, 1028) 349 = nand( 1149, 1152) 426 = nand( 1389, 1392) 428 = nand( 1397, 1400) 430 = nand( 1405, 1408) 67 = nand( 1639, 1642) 1643 = not( 1639) 70 = nand( 1649, 1652) 1653 = not( 1649) 1215 = nand( 1809, 1812) 49 = nand( 286, 287) 53 = nand( 349, 350) 59 = nand( 426, 427) 61 = nand( 428, 429) 65 = nand( 430, 431) 68 = nand( 1634, 1643) 71 = nand( 1644, 1653) 1217 = nand( 1215, 1216) 51 = and( 49, 50) 54 = and( 52, 53) 60 = and( 58, 59) 63 = and( 61, 62) 66 = and( 64, 65) 69 = nand( 67, 68) 72 = nand( 70, 71) 375 = nand( 1217, 1220) 1221 = not( 1217) 376 = nand( 1212, 1221) 55 = nand( 375, 376) 57 = and( 55, 56) |
Added c1908/c1908gate.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 |
/****************************************************************************
* *
* VERILOG VERSION of ORIGINAL NETLIST for c1908 *
* *
* *
* Generated by: Hakan Yalcin (hyalcin@cadence.com) *
* *
* Sep 16, 1998 *
* *
****************************************************************************/
module c1908g (
L101, L104, L107, L110, L113, L116, L119,
L122, L125, L128, L131, L134, L137, L140, L143,
L146, L210, L214, L217, L221, L224, L227, L234,
L237, L469, L472, L475, L478, L898, L900, L902,
L952, L953,
L3, L6, L9, L12, L30, L45, L48,
L15, L18, L21, L24, L27, L33, L36, L39,
L42, L75, L51, L54, L60, L63, L66, L69,
L72, L57);
input
L101, L104, L107, L110, L113, L116, L119,
L122, L125, L128, L131, L134, L137, L140, L143,
L146, L210, L214, L217, L221, L224, L227, L234,
L237, L469, L472, L475, L478, L898, L900, L902,
L952, L953;
output
L3, L6, L9, L12, L30, L45, L48,
L15, L18, L21, L24, L27, L33, L36, L39,
L42, L75, L51, L54, L60, L63, L66, L69,
L72, L57;
inv U1 ( L101, L149 );
inv U2 ( L104, L153 );
inv U3 ( L107, L156 );
inv U4 ( L110, L160 );
inv U5 ( L113, L165 );
inv U6 ( L116, L168 );
inv U7 ( L119, L171 );
inv U8 ( L122, L175 );
inv U9 ( L125, L179 );
inv U10 ( L128, L184 );
inv U11 ( L131, L188 );
inv U12 ( L134, L191 );
inv U13 ( L137, L194 );
inv U14 ( L140, L198 );
inv U15 ( L143, L202 );
inv U16 ( L146, L206 );
nand2 U17 ( L224, L898, L231 );
nand2 U18 ( L227, L900, L233 );
inv U19 ( L237, L241 );
inv U20 ( L237, L244 );
buffer U21 ( L234, L245 );
buffer U22 ( L234, L248 );
inv U23 ( L469, L517 );
inv U24 ( L472, L529 );
inv U25 ( L475, L541 );
inv U26 ( L478, L553 );
inv U27 ( L953, L859 );
inv U28 ( L953, L862 );
inv U29 ( L898, L907 );
inv U30 ( L900, L909 );
buffer U31 ( L902, L911 );
inv U32 ( L902, L918 );
buffer U33 ( L902, L919 );
inv U34 ( L902, L922 );
buffer U35 ( L952, L926 );
inv U36 ( L952, L930 );
inv U37 ( L952, L932 );
buffer U38 ( L953, L934 );
inv U39 ( L953, L938 );
buffer U40 ( L953, L943 );
buffer U41 ( L953, L947 );
inv U42 ( L953, L949 );
buffer U43 ( L101, L1506 );
buffer U44 ( L104, L1514 );
buffer U45 ( L107, L1522 );
buffer U46 ( L110, L1530 );
buffer U47 ( L113, L1538 );
buffer U48 ( L116, L1546 );
buffer U49 ( L119, L1554 );
buffer U50 ( L122, L1562 );
buffer U51 ( L125, L1570 );
buffer U52 ( L128, L1578 );
buffer U53 ( L131, L1586 );
buffer U54 ( L134, L1594 );
buffer U55 ( L137, L1602 );
buffer U56 ( L140, L1610 );
buffer U57 ( L143, L1618 );
buffer U58 ( L146, L1626 );
inv U59 ( L1506, L1512 );
inv U60 ( L1514, L1520 );
inv U61 ( L1522, L1528 );
inv U62 ( L1530, L1536 );
inv U63 ( L1538, L1544 );
inv U64 ( L1546, L1552 );
inv U65 ( L1554, L1560 );
inv U66 ( L1562, L1568 );
inv U67 ( L1570, L1576 );
inv U68 ( L1578, L1584 );
inv U69 ( L1586, L1592 );
inv U70 ( L1594, L1600 );
inv U71 ( L1602, L1608 );
inv U72 ( L1610, L1616 );
inv U73 ( L1618, L1624 );
inv U74 ( L1626, L1632 );
nand2 U75 ( L930, L947, L50 );
nand2 U76 ( L930, L947, L52 );
nand2 U77 ( L930, L947, L56 );
nand2 U78 ( L930, L947, L58 );
nand2 U79 ( L930, L947, L62 );
nand2 U80 ( L930, L947, L64 );
buffer U81 ( L149, L251 );
buffer U82 ( L153, L254 );
buffer U83 ( L165, L288 );
buffer U84 ( L168, L291 );
buffer U85 ( L184, L299 );
buffer U86 ( L202, L302 );
and2 U87 ( L224, L938, L318 );
buffer U88 ( L179, L321 );
buffer U89 ( L188, L327 );
buffer U90 ( L191, L330 );
and2 U91 ( L227, L938, L352 );
buffer U92 ( L198, L355 );
and3 U93 ( L210, L241, L938, L369 );
buffer U94 ( L206, L382 );
buffer U95 ( L198, L385 );
nand2 U96 ( L943, L907, L853 );
nand2 U97 ( L943, L909, L856 );
nand2 U98 ( L248, L237, L893 );
nand2 U99 ( L248, L922, L954 );
nand2 U100 ( L244, L922, L955 );
buffer U101 ( L160, L1050 );
buffer U102 ( L175, L1053 );
buffer U103 ( L179, L1176 );
buffer U104 ( L198, L1179 );
buffer U105 ( L149, L1197 );
buffer U106 ( L149, L1207 );
buffer U107 ( L153, L1222 );
buffer U108 ( L188, L1244 );
buffer U109 ( L156, L1278 );
and3 U110 ( L217, L245, L938, L1290 );
buffer U111 ( L191, L1300 );
buffer U112 ( L160, L1312 );
buffer U113 ( L194, L1332 );
and3 U114 ( L221, L245, L938, L1335 );
buffer U115 ( L517, L1442 );
buffer U116 ( L517, L1450 );
buffer U117 ( L529, L1458 );
buffer U118 ( L529, L1466 );
buffer U119 ( L541, L1474 );
buffer U120 ( L541, L1482 );
buffer U121 ( L553, L1490 );
buffer U122 ( L553, L1498 );
and2 U123 ( L231, L934, L1634 );
and2 U124 ( L233, L934, L1644 );
buffer U125 ( L156, L1657 );
buffer U126 ( L156, L1665 );
buffer U127 ( L171, L1697 );
buffer U128 ( L171, L1705 );
buffer U129 ( L206, L1713 );
buffer U130 ( L206, L1721 );
buffer U131 ( L194, L1745 );
buffer U132 ( L194, L1753 );
buffer U133 ( L160, L1785 );
buffer U134 ( L160, L1793 );
buffer U135 ( L165, L1814 );
buffer U136 ( L175, L1817 );
and3 U137 ( L214, L241, L938, L1830 );
buffer U138 ( L202, L1833 );
buffer U139 ( L179, L1841 );
buffer U140 ( L179, L1849 );
buffer U141 ( L168, L1854 );
buffer U142 ( L175, L1857 );
buffer U143 ( L184, L1870 );
buffer U144 ( L202, L1873 );
buffer U145 ( L171, L1878 );
buffer U146 ( L184, L1881 );
inv U147 ( L1634, L1642 );
inv U148 ( L1644, L1652 );
inv U149 ( L1050, L1056 );
inv U150 ( L1053, L1057 );
inv U151 ( L1176, L1182 );
inv U152 ( L1179, L1183 );
inv U153 ( L1207, L1211 );
inv U154 ( L1290, L1298 );
inv U155 ( L1312, L1320 );
inv U156 ( L1332, L1338 );
inv U157 ( L1335, L1339 );
and2 U158 ( L210, L955, L457 );
and2 U159 ( L217, L954, L459 );
nand2 U160 ( L214, L955, L482 );
nand2 U161 ( L221, L954, L487 );
nand2 U162 ( L210, L955, L492 );
nand2 U163 ( L217, L954, L505 );
inv U164 ( L1450, L1456 );
inv U165 ( L1442, L1448 );
inv U166 ( L1466, L1472 );
inv U167 ( L1458, L1464 );
inv U168 ( L1482, L1488 );
inv U169 ( L1474, L1480 );
inv U170 ( L1498, L1504 );
inv U171 ( L1490, L1496 );
nand4 U172 ( L907, L919, L943, L893, L956 );
nand4 U173 ( L909, L919, L943, L893, L967 );
nand3 U174 ( L926, L949, L893, L978 );
and3 U175 ( L926, L949, L893, L979 );
buffer U176 ( L251, L980 );
inv U177 ( L1657, L1661 );
buffer U178 ( L251, L990 );
inv U179 ( L1665, L1669 );
buffer U180 ( L288, L1030 );
inv U181 ( L1697, L1701 );
buffer U182 ( L288, L1040 );
inv U183 ( L1705, L1709 );
buffer U184 ( L299, L1058 );
inv U185 ( L1713, L1717 );
buffer U186 ( L299, L1068 );
inv U187 ( L1721, L1725 );
buffer U188 ( L318, L1078 );
buffer U189 ( L318, L1090 );
buffer U190 ( L327, L1100 );
inv U191 ( L1745, L1749 );
buffer U192 ( L327, L1112 );
inv U193 ( L1753, L1757 );
buffer U194 ( L352, L1154 );
inv U195 ( L1785, L1789 );
buffer U196 ( L352, L1166 );
inv U197 ( L1793, L1797 );
buffer U198 ( L369, L1194 );
inv U199 ( L1197, L1201 );
buffer U200 ( L369, L1204 );
inv U201 ( L1814, L1820 );
inv U202 ( L1817, L1821 );
inv U203 ( L1222, L1230 );
inv U204 ( L1830, L1836 );
inv U205 ( L1833, L1837 );
inv U206 ( L1244, L1252 );
buffer U207 ( L382, L1256 );
inv U208 ( L1841, L1845 );
buffer U209 ( L382, L1268 );
inv U210 ( L1849, L1853 );
inv U211 ( L1854, L1860 );
inv U212 ( L1857, L1861 );
inv U213 ( L1278, L1286 );
inv U214 ( L1870, L1876 );
inv U215 ( L1873, L1877 );
inv U216 ( L1300, L1308 );
inv U217 ( L1878, L1884 );
inv U218 ( L1881, L1885 );
buffer U219 ( L254, L1654 );
buffer U220 ( L254, L1662 );
buffer U221 ( L291, L1694 );
buffer U222 ( L291, L1702 );
buffer U223 ( L302, L1710 );
buffer U224 ( L302, L1718 );
buffer U225 ( L321, L1726 );
buffer U226 ( L321, L1734 );
buffer U227 ( L330, L1742 );
buffer U228 ( L330, L1750 );
buffer U229 ( L355, L1782 );
buffer U230 ( L355, L1790 );
buffer U231 ( L385, L1838 );
buffer U232 ( L385, L1846 );
nand2 U233 ( L1053, L1056, L297 );
nand2 U234 ( L1050, L1057, L298 );
nand2 U235 ( L1179, L1182, L361 );
nand2 U236 ( L1176, L1183, L362 );
nand2 U237 ( L1335, L1338, L404 );
nand2 U238 ( L1332, L1339, L405 );
nand2 U239 ( L1817, L1820, L1225 );
nand2 U240 ( L1814, L1821, L1226 );
nand2 U241 ( L1833, L1836, L1247 );
nand2 U242 ( L1830, L1837, L1248 );
nand2 U243 ( L1857, L1860, L1281 );
nand2 U244 ( L1854, L1861, L1282 );
nand2 U245 ( L1873, L1876, L1303 );
nand2 U246 ( L1870, L1877, L1304 );
nand2 U247 ( L1881, L1884, L1315 );
nand2 U248 ( L1878, L1885, L1316 );
inv U249 ( L990, L998 );
inv U250 ( L980, L988 );
nand2 U251 ( L297, L298, L268 );
inv U252 ( L1030, L1038 );
inv U253 ( L1040, L1048 );
inv U254 ( L1068, L1076 );
inv U255 ( L1058, L1066 );
inv U256 ( L1090, L1098 );
inv U257 ( L1112, L1120 );
inv U258 ( L1166, L1174 );
nand2 U259 ( L361, L362, L363 );
inv U260 ( L1204, L1210 );
nand2 U261 ( L1204, L1211, L373 );
inv U262 ( L1268, L1276 );
nand2 U263 ( L404, L405, L406 );
inv U264 ( L482, L565 );
buffer U265 ( L482, L566 );
inv U266 ( L487, L614 );
buffer U267 ( L487, L615 );
nand2 U268 ( L956, L978, L958 );
nand2 U269 ( L967, L978, L969 );
inv U270 ( L1654, L1660 );
nand2 U271 ( L1654, L1661, L984 );
inv U272 ( L1662, L1668 );
nand2 U273 ( L1662, L1669, L994 );
inv U274 ( L1694, L1700 );
nand2 U275 ( L1694, L1701, L1034 );
inv U276 ( L1702, L1708 );
nand2 U277 ( L1702, L1709, L1044 );
inv U278 ( L1710, L1716 );
nand2 U279 ( L1710, L1717, L1062 );
inv U280 ( L1718, L1724 );
nand2 U281 ( L1718, L1725, L1072 );
inv U282 ( L1726, L1732 );
inv U283 ( L1078, L1086 );
inv U284 ( L1734, L1740 );
inv U285 ( L1742, L1748 );
nand2 U286 ( L1742, L1749, L1104 );
inv U287 ( L1100, L1108 );
inv U288 ( L1750, L1756 );
nand2 U289 ( L1750, L1757, L1116 );
inv U290 ( L1782, L1788 );
nand2 U291 ( L1782, L1789, L1158 );
inv U292 ( L1154, L1162 );
inv U293 ( L1790, L1796 );
nand2 U294 ( L1790, L1797, L1170 );
inv U295 ( L1194, L1200 );
nand2 U296 ( L1194, L1201, L1203 );
nand2 U297 ( L1225, L1226, L1227 );
nand2 U298 ( L1247, L1248, L1249 );
inv U299 ( L1838, L1844 );
nand2 U300 ( L1838, L1845, L1260 );
inv U301 ( L1256, L1264 );
inv U302 ( L1846, L1852 );
nand2 U303 ( L1846, L1853, L1272 );
nand2 U304 ( L1281, L1282, L1283 );
nand2 U305 ( L1303, L1304, L1305 );
nand2 U306 ( L1315, L1316, L1317 );
buffer U307 ( L492, L1410 );
buffer U308 ( L492, L1418 );
buffer U309 ( L505, L1426 );
buffer U310 ( L505, L1434 );
inv U311 ( L268, L269 );
nand2 U312 ( L1207, L1210, L372 );
nand2 U313 ( L1657, L1660, L983 );
nand2 U314 ( L1665, L1668, L993 );
nand2 U315 ( L1697, L1700, L1033 );
nand2 U316 ( L1705, L1708, L1043 );
nand2 U317 ( L1713, L1716, L1061 );
nand2 U318 ( L1721, L1724, L1071 );
nand2 U319 ( L1745, L1748, L1103 );
nand2 U320 ( L1753, L1756, L1115 );
nand2 U321 ( L1785, L1788, L1157 );
nand2 U322 ( L1793, L1796, L1169 );
inv U323 ( L363, L1184 );
nand2 U324 ( L1197, L1200, L1202 );
nand2 U325 ( L1841, L1844, L1259 );
nand2 U326 ( L1849, L1852, L1271 );
inv U327 ( L406, L1322 );
nand2 U328 ( L372, L373, L374 );
nand2 U329 ( L1317, L1320, L396 );
inv U330 ( L1317, L1321 );
inv U331 ( L1418, L1424 );
inv U332 ( L1410, L1416 );
inv U333 ( L1434, L1440 );
inv U334 ( L1426, L1432 );
nand2 U335 ( L983, L984, L985 );
nand2 U336 ( L993, L994, L995 );
nand2 U337 ( L1033, L1034, L1035 );
nand2 U338 ( L1043, L1044, L1045 );
nand2 U339 ( L1061, L1062, L1063 );
nand2 U340 ( L1071, L1072, L1073 );
nand2 U341 ( L1103, L1104, L1105 );
nand2 U342 ( L1115, L1116, L1117 );
nand2 U343 ( L1157, L1158, L1159 );
nand2 U344 ( L1169, L1170, L1171 );
nand2 U345 ( L1202, L1203, L1212 );
inv U346 ( L1227, L1231 );
nand2 U347 ( L1227, L1230, L1232 );
inv U348 ( L1249, L1253 );
nand2 U349 ( L1249, L1252, L1254 );
nand2 U350 ( L1259, L1260, L1261 );
nand2 U351 ( L1271, L1272, L1273 );
inv U352 ( L1283, L1287 );
nand2 U353 ( L1283, L1286, L1288 );
inv U354 ( L1305, L1309 );
nand2 U355 ( L1305, L1308, L1310 );
inv U356 ( L1184, L1192 );
nand2 U357 ( L1312, L1321, L397 );
inv U358 ( L1322, L1330 );
buffer U359 ( L269, L1000 );
buffer U360 ( L269, L1010 );
nand2 U361 ( L1222, L1231, L1233 );
nand2 U362 ( L1244, L1253, L1255 );
nand2 U363 ( L1278, L1287, L1289 );
nand2 U364 ( L1300, L1309, L1311 );
inv U365 ( L374, L1381 );
nand2 U366 ( L995, L998, L257 );
inv U367 ( L995, L999 );
nand2 U368 ( L985, L988, L260 );
inv U369 ( L985, L989 );
nand2 U370 ( L1035, L1038, L272 );
inv U371 ( L1035, L1039 );
nand2 U372 ( L1045, L1048, L294 );
inv U373 ( L1045, L1049 );
nand2 U374 ( L1073, L1076, L305 );
inv U375 ( L1073, L1077 );
nand2 U376 ( L1063, L1066, L308 );
inv U377 ( L1063, L1067 );
nand2 U378 ( L1117, L1120, L333 );
inv U379 ( L1117, L1121 );
nand2 U380 ( L1171, L1174, L358 );
inv U381 ( L1171, L1175 );
inv U382 ( L1212, L1220 );
nand2 U383 ( L1273, L1276, L388 );
inv U384 ( L1273, L1277 );
nand2 U385 ( L396, L397, L398 );
inv U386 ( L1105, L1109 );
nand2 U387 ( L1105, L1108, L1110 );
inv U388 ( L1159, L1163 );
nand2 U389 ( L1159, L1162, L1164 );
nand2 U390 ( L1232, L1233, L1234 );
inv U391 ( L1261, L1265 );
nand2 U392 ( L1261, L1264, L1266 );
nand2 U393 ( L1254, L1255, L1822 );
nand2 U394 ( L1310, L1311, L1862 );
nand2 U395 ( L1288, L1289, L1865 );
nand2 U396 ( L990, L999, L258 );
nand2 U397 ( L980, L989, L261 );
nand2 U398 ( L1030, L1039, L273 );
inv U399 ( L1010, L1018 );
inv U400 ( L1000, L1008 );
nand2 U401 ( L1040, L1049, L295 );
nand2 U402 ( L1068, L1077, L306 );
nand2 U403 ( L1058, L1067, L309 );
nand2 U404 ( L1112, L1121, L334 );
nand2 U405 ( L1166, L1175, L359 );
nand2 U406 ( L1268, L1277, L389 );
inv U407 ( L1381, L1385 );
nand2 U408 ( L1100, L1109, L1111 );
nand2 U409 ( L1154, L1163, L1165 );
nand2 U410 ( L1256, L1265, L1267 );
inv U411 ( L398, L1886 );
nand2 U412 ( L257, L258, L259 );
nand2 U413 ( L260, L261, L262 );
nand2 U414 ( L272, L273, L274 );
nand2 U415 ( L294, L295, L296 );
nand2 U416 ( L305, L306, L307 );
nand2 U417 ( L308, L309, L310 );
nand2 U418 ( L333, L334, L335 );
nand2 U419 ( L358, L359, L360 );
inv U420 ( L1234, L1242 );
nand2 U421 ( L388, L389, L390 );
inv U422 ( L1822, L1828 );
inv U423 ( L1862, L1868 );
inv U424 ( L1865, L1869 );
nand2 U425 ( L1164, L1165, L1373 );
nand2 U426 ( L1110, L1111, L1798 );
nand2 U427 ( L1266, L1267, L1825 );
inv U428 ( L259, L265 );
inv U429 ( L307, L314 );
inv U430 ( L335, L336 );
inv U431 ( L296, L407 );
nand2 U432 ( L1865, L1868, L1293 );
nand2 U433 ( L1862, L1869, L1294 );
inv U434 ( L1886, L1892 );
inv U435 ( L360, L1777 );
inv U436 ( L390, L1889 );
buffer U437 ( L310, L410 );
inv U438 ( L1373, L1377 );
inv U439 ( L1798, L1804 );
nand2 U440 ( L1825, L1828, L1237 );
inv U441 ( L1825, L1829 );
nand2 U442 ( L1293, L1294, L1295 );
buffer U443 ( L274, L1670 );
buffer U444 ( L274, L1678 );
buffer U445 ( L310, L1729 );
buffer U446 ( L310, L1737 );
buffer U447 ( L262, L1761 );
buffer U448 ( L262, L1769 );
buffer U449 ( L336, L340 );
buffer U450 ( L314, L343 );
inv U451 ( L1777, L1781 );
nand2 U452 ( L1822, L1829, L1238 );
nand2 U453 ( L1889, L1892, L1325 );
inv U454 ( L1889, L1893 );
buffer U455 ( L407, L1340 );
buffer U456 ( L407, L1352 );
buffer U457 ( L265, L1673 );
buffer U458 ( L265, L1681 );
buffer U459 ( L314, L1801 );
buffer U460 ( L336, L1897 );
buffer U461 ( L336, L1905 );
nand2 U462 ( L1295, L1298, L391 );
inv U463 ( L1295, L1299 );
inv U464 ( L1670, L1676 );
inv U465 ( L1678, L1684 );
nand2 U466 ( L1729, L1732, L1081 );
inv U467 ( L1729, L1733 );
nand2 U468 ( L1737, L1740, L1093 );
inv U469 ( L1737, L1741 );
inv U470 ( L1761, L1765 );
inv U471 ( L1769, L1773 );
nand2 U472 ( L1237, L1238, L1239 );
nand2 U473 ( L1886, L1893, L1326 );
buffer U474 ( L410, L1894 );
buffer U475 ( L410, L1902 );
nand2 U476 ( L1290, L1299, L392 );
inv U477 ( L1352, L1360 );
nand2 U478 ( L1673, L1676, L1003 );
inv U479 ( L1673, L1677 );
nand2 U480 ( L1681, L1684, L1013 );
inv U481 ( L1681, L1685 );
nand2 U482 ( L1726, L1733, L1082 );
nand2 U483 ( L1734, L1741, L1094 );
buffer U484 ( L340, L1122 );
buffer U485 ( L340, L1134 );
nand2 U486 ( L1801, L1804, L1187 );
inv U487 ( L1801, L1805 );
nand2 U488 ( L1325, L1326, L1327 );
inv U489 ( L1897, L1901 );
inv U490 ( L1340, L1348 );
inv U491 ( L1905, L1909 );
buffer U492 ( L343, L1758 );
buffer U493 ( L343, L1766 );
nand2 U494 ( L1239, L1242, L377 );
inv U495 ( L1239, L1243 );
nand2 U496 ( L391, L392, L393 );
nand2 U497 ( L1670, L1677, L1004 );
nand2 U498 ( L1678, L1685, L1014 );
nand2 U499 ( L1081, L1082, L1083 );
nand2 U500 ( L1093, L1094, L1095 );
nand2 U501 ( L1798, L1805, L1188 );
inv U502 ( L1894, L1900 );
nand2 U503 ( L1894, L1901, L1344 );
inv U504 ( L1902, L1908 );
nand2 U505 ( L1902, L1909, L1356 );
inv U506 ( L1134, L1142 );
nand2 U507 ( L1234, L1243, L378 );
nand2 U508 ( L1327, L1330, L399 );
inv U509 ( L1327, L1331 );
nand2 U510 ( L1003, L1004, L1005 );
nand2 U511 ( L1013, L1014, L1015 );
inv U512 ( L1758, L1764 );
nand2 U513 ( L1758, L1765, L1126 );
inv U514 ( L1122, L1130 );
inv U515 ( L1766, L1772 );
nand2 U516 ( L1766, L1773, L1138 );
nand2 U517 ( L1187, L1188, L1189 );
nand2 U518 ( L1897, L1900, L1343 );
nand2 U519 ( L1905, L1908, L1355 );
nand2 U520 ( L1095, L1098, L324 );
inv U521 ( L1095, L1099 );
nand2 U522 ( L377, L378, L379 );
nand2 U523 ( L1322, L1331, L400 );
nand2 U524 ( L393, L918, L449 );
inv U525 ( L1083, L1087 );
nand2 U526 ( L1083, L1086, L1088 );
nand2 U527 ( L1761, L1764, L1125 );
nand2 U528 ( L1769, L1772, L1137 );
nand2 U529 ( L1343, L1344, L1345 );
nand2 U530 ( L1355, L1356, L1357 );
buffer U531 ( L393, L1397 );
nand2 U532 ( L1015, L1018, L277 );
inv U533 ( L1015, L1019 );
nand2 U534 ( L1005, L1008, L280 );
inv U535 ( L1005, L1009 );
nand2 U536 ( L1090, L1099, L325 );
nand2 U537 ( L1189, L1192, L364 );
inv U538 ( L1189, L1193 );
nand2 U539 ( L399, L400, L401 );
nand2 U540 ( L1078, L1087, L1089 );
nand2 U541 ( L1125, L1126, L1127 );
nand2 U542 ( L1137, L1138, L1139 );
nand2 U543 ( L1010, L1019, L278 );
nand2 U544 ( L1000, L1009, L281 );
nand2 U545 ( L324, L325, L326 );
nand2 U546 ( L1184, L1193, L365 );
nand2 U547 ( L1357, L1360, L413 );
inv U548 ( L1357, L1361 );
inv U549 ( L1397, L1401 );
nand2 U550 ( L379, L918, L445 );
inv U551 ( L1345, L1349 );
nand2 U552 ( L1345, L1348, L1350 );
buffer U553 ( L379, L1389 );
buffer U554 ( L449, L1493 );
buffer U555 ( L449, L1501 );
nand2 U556 ( L1088, L1089, L1689 );
nand2 U557 ( L277, L278, L279 );
nand2 U558 ( L280, L281, L282 );
nand2 U559 ( L1139, L1142, L346 );
inv U560 ( L1139, L1143 );
nand2 U561 ( L364, L365, L366 );
nand2 U562 ( L1352, L1361, L414 );
nand2 U563 ( L401, L918, L453 );
inv U564 ( L1127, L1131 );
nand2 U565 ( L1127, L1130, L1132 );
nand2 U566 ( L1340, L1349, L1351 );
inv U567 ( L326, L1365 );
buffer U568 ( L401, L1405 );
inv U569 ( L279, L285 );
nand2 U570 ( L1134, L1143, L347 );
inv U571 ( L366, L367 );
nand2 U572 ( L413, L414, L415 );
inv U573 ( L1389, L1393 );
nand2 U574 ( L1501, L1504, L556 );
inv U575 ( L1501, L1505 );
nand2 U576 ( L1493, L1496, L559 );
inv U577 ( L1493, L1497 );
inv U578 ( L1689, L1693 );
nand2 U579 ( L1122, L1131, L1133 );
buffer U580 ( L445, L1477 );
buffer U581 ( L445, L1485 );
nand2 U582 ( L1350, L1351, L1809 );
nand2 U583 ( L346, L347, L348 );
inv U584 ( L1365, L1369 );
inv U585 ( L1405, L1409 );
nand2 U586 ( L1498, L1505, L557 );
nand2 U587 ( L1490, L1497, L560 );
buffer U588 ( L282, L1362 );
inv U589 ( L415, L1378 );
buffer U590 ( L453, L1429 );
buffer U591 ( L453, L1437 );
buffer U592 ( L282, L1686 );
nand2 U593 ( L1132, L1133, L1774 );
and2 U594 ( L285, L853, L1910 );
and2 U595 ( L856, L367, L1918 );
nand2 U596 ( L1485, L1488, L544 );
inv U597 ( L1485, L1489 );
nand2 U598 ( L1477, L1480, L547 );
inv U599 ( L1477, L1481 );
nand2 U600 ( L556, L557, L558 );
nand2 U601 ( L559, L560, L561 );
inv U602 ( L1809, L1813 );
inv U603 ( L348, L1370 );
inv U604 ( L1362, L1368 );
nand2 U605 ( L1362, L1369, L417 );
inv U606 ( L1378, L1384 );
nand2 U607 ( L1378, L1385, L424 );
nand2 U608 ( L1437, L1440, L508 );
inv U609 ( L1437, L1441 );
nand2 U610 ( L1429, L1432, L511 );
inv U611 ( L1429, L1433 );
nand2 U612 ( L1482, L1489, L545 );
nand2 U613 ( L1474, L1481, L548 );
inv U614 ( L558, L564 );
inv U615 ( L1686, L1692 );
nand2 U616 ( L1686, L1693, L1024 );
inv U617 ( L1774, L1780 );
nand2 U618 ( L1774, L1781, L1148 );
inv U619 ( L1910, L1916 );
inv U620 ( L1918, L1924 );
nand2 U621 ( L1365, L1368, L416 );
inv U622 ( L1370, L1376 );
nand2 U623 ( L1370, L1377, L421 );
nand2 U624 ( L1381, L1384, L423 );
nand2 U625 ( L1434, L1441, L509 );
nand2 U626 ( L1426, L1433, L512 );
nand2 U627 ( L544, L545, L546 );
nand2 U628 ( L547, L548, L549 );
inv U629 ( L561, L719 );
buffer U630 ( L561, L722 );
nand2 U631 ( L1689, L1692, L1023 );
nand2 U632 ( L1777, L1780, L1147 );
nand2 U633 ( L416, L417, L418 );
nand2 U634 ( L1373, L1376, L420 );
nand2 U635 ( L423, L424, L425 );
nand2 U636 ( L508, L509, L510 );
nand2 U637 ( L511, L512, L513 );
inv U638 ( L546, L552 );
nand2 U639 ( L1023, L1024, L1025 );
nand2 U640 ( L1147, L1148, L1149 );
inv U641 ( L418, L419 );
nand2 U642 ( L420, L421, L422 );
nand2 U643 ( L425, L918, L441 );
inv U644 ( L510, L516 );
inv U645 ( L549, L725 );
buffer U646 ( L549, L728 );
inv U647 ( L1025, L1029 );
inv U648 ( L1149, L1153 );
nand2 U649 ( L419, L918, L433 );
nand2 U650 ( L422, L918, L437 );
inv U651 ( L513, L663 );
buffer U652 ( L513, L666 );
and2 U653 ( L719, L725, L731 );
and2 U654 ( L722, L725, L746 );
and2 U655 ( L719, L728, L756 );
and2 U656 ( L722, L728, L770 );
buffer U657 ( L441, L1461 );
buffer U658 ( L441, L1469 );
buffer U659 ( L433, L1413 );
buffer U660 ( L433, L1421 );
buffer U661 ( L437, L1445 );
buffer U662 ( L437, L1453 );
nand2 U663 ( L1469, L1472, L532 );
inv U664 ( L1469, L1473 );
nand2 U665 ( L1461, L1464, L535 );
inv U666 ( L1461, L1465 );
nand2 U667 ( L1421, L1424, L495 );
inv U668 ( L1421, L1425 );
nand2 U669 ( L1413, L1416, L498 );
inv U670 ( L1413, L1417 );
nand2 U671 ( L1453, L1456, L520 );
inv U672 ( L1453, L1457 );
nand2 U673 ( L1445, L1448, L523 );
inv U674 ( L1445, L1449 );
nand2 U675 ( L1466, L1473, L533 );
nand2 U676 ( L1458, L1465, L536 );
nand2 U677 ( L1418, L1425, L496 );
nand2 U678 ( L1410, L1417, L499 );
nand2 U679 ( L1450, L1457, L521 );
nand2 U680 ( L1442, L1449, L524 );
nand2 U681 ( L532, L533, L534 );
nand2 U682 ( L535, L536, L537 );
nand2 U683 ( L495, L496, L497 );
nand2 U684 ( L498, L499, L500 );
nand2 U685 ( L520, L521, L522 );
nand2 U686 ( L523, L524, L525 );
inv U687 ( L534, L540 );
inv U688 ( L497, L503 );
inv U689 ( L522, L528 );
inv U690 ( L537, L669 );
buffer U691 ( L537, L672 );
inv U692 ( L500, L569 );
and2 U693 ( L566, L500, L588 );
inv U694 ( L525, L618 );
and2 U695 ( L615, L525, L639 );
nand8 U696 ( L516, L564, L552, L540, L482, L528, L503, L487, L867 );
buffer U697 ( L588, L588a );
buffer U698 ( L588, L588b );
buffer U699 ( L639, L639a );
buffer U700 ( L639, L639b );
and2 U701 ( L663, L669, L675 );
and2 U702 ( L666, L669, L688 );
and2 U703 ( L663, L672, L696 );
and2 U704 ( L666, L672, L710 );
and3 U705 ( L949, L867, L932, L73 );
and2 U706 ( L565, L569, L572 );
and2 U707 ( L566, L569, L573 );
and2 U708 ( L614, L618, L621 );
and2 U709 ( L615, L618, L622 );
nand5 U710 ( L588a, L639a, L696, L731, L958, L776 );
nand5 U711 ( L588a, L639a, L675, L756, L958, L780 );
nand5 U712 ( L588a, L639a, L675, L746, L958, L784 );
nand5 U713 ( L588a, L639a, L688, L731, L958, L788 );
nand5 U714 ( L588b, L639a, L710, L746, L969, L812 );
nand5 U715 ( L588b, L639b, L696, L770, L969, L832 );
nand5 U716 ( L588b, L639b, L710, L756, L969, L836 );
and5 U717 ( L588a, L639a, L696, L731, L958, L1509 );
and5 U718 ( L588a, L639a, L675, L756, L958, L1517 );
and5 U719 ( L588a, L639a, L675, L746, L958, L1525 );
and5 U720 ( L588a, L639a, L688, L731, L958, L1533 );
and5 U721 ( L588b, L639a, L710, L746, L969, L1581 );
and5 U722 ( L588b, L639b, L696, L770, L969, L1621 );
and5 U723 ( L588b, L639b, L710, L756, L969, L1629 );
nand5 U724 ( L588a, L622, L696, L756, L958, L792 );
nand5 U725 ( L588b, L622, L696, L746, L958, L796 );
nand5 U726 ( L588b, L622, L710, L731, L958, L800 );
nand5 U727 ( L588b, L622, L675, L770, L958, L804 );
nand5 U728 ( L588b, L622, L688, L756, L969, L808 );
nand5 U729 ( L573, L639b, L696, L756, L969, L816 );
nand5 U730 ( L573, L639b, L696, L746, L969, L820 );
nand5 U731 ( L573, L639b, L710, L731, L969, L824 );
nand5 U732 ( L573, L639b, L688, L756, L969, L828 );
nand5 U733 ( L588b, L622, L675, L731, L979, L871 );
nand5 U734 ( L573, L639b, L675, L731, L979, L873 );
nand5 U735 ( L573, L622, L696, L731, L979, L875 );
nand5 U736 ( L573, L622, L675, L756, L979, L877 );
nand5 U737 ( L573, L622, L675, L746, L979, L879 );
nand5 U738 ( L573, L622, L688, L731, L979, L881 );
nand5 U739 ( L573, L621, L675, L731, L979, L883 );
nand5 U740 ( L572, L622, L675, L731, L979, L885 );
and5 U741 ( L588a, L622, L696, L756, L958, L1541 );
and5 U742 ( L588b, L622, L696, L746, L958, L1549 );
and5 U743 ( L588b, L622, L710, L731, L958, L1557 );
and5 U744 ( L588b, L622, L675, L770, L958, L1565 );
and5 U745 ( L588b, L622, L688, L756, L969, L1573 );
and5 U746 ( L573, L639b, L696, L756, L969, L1589 );
and5 U747 ( L573, L639b, L696, L746, L969, L1597 );
and5 U748 ( L573, L639b, L710, L731, L969, L1605 );
and5 U749 ( L573, L639b, L688, L756, L969, L1613 );
nand2 U750 ( L1509, L1512, L1 );
inv U751 ( L1509, L1513 );
nand2 U752 ( L1517, L1520, L4 );
inv U753 ( L1517, L1521 );
nand2 U754 ( L1525, L1528, L7 );
inv U755 ( L1525, L1529 );
nand2 U756 ( L1533, L1536, L10 );
inv U757 ( L1533, L1537 );
nand2 U758 ( L1581, L1584, L28 );
inv U759 ( L1581, L1585 );
nand2 U760 ( L1621, L1624, L43 );
inv U761 ( L1621, L1625 );
nand2 U762 ( L1629, L1632, L46 );
inv U763 ( L1629, L1633 );
and8 U764 ( L871, L873, L875, L877, L879, L881, L883, L885, L886 );
nand2 U765 ( L1506, L1513, L2 );
nand2 U766 ( L1514, L1521, L5 );
nand2 U767 ( L1522, L1529, L8 );
nand2 U768 ( L1530, L1537, L11 );
nand2 U769 ( L1541, L1544, L13 );
inv U770 ( L1541, L1545 );
nand2 U771 ( L1549, L1552, L16 );
inv U772 ( L1549, L1553 );
nand2 U773 ( L1557, L1560, L19 );
inv U774 ( L1557, L1561 );
nand2 U775 ( L1565, L1568, L22 );
inv U776 ( L1565, L1569 );
nand2 U777 ( L1573, L1576, L25 );
inv U778 ( L1573, L1577 );
nand2 U779 ( L1578, L1585, L29 );
nand2 U780 ( L1589, L1592, L31 );
inv U781 ( L1589, L1593 );
nand2 U782 ( L1597, L1600, L34 );
inv U783 ( L1597, L1601 );
nand2 U784 ( L1605, L1608, L37 );
inv U785 ( L1605, L1609 );
nand2 U786 ( L1613, L1616, L40 );
inv U787 ( L1613, L1617 );
nand2 U788 ( L1618, L1625, L44 );
nand2 U789 ( L1626, L1633, L47 );
nand8 U790 ( L776, L780, L784, L788, L792, L796, L800, L804, L857 );
nand8 U791 ( L808, L812, L816, L820, L824, L828, L832, L836, L860 );
and8 U792 ( L776, L780, L784, L788, L792, L796, L800, L804, L863 );
and8 U793 ( L808, L812, L816, L820, L824, L828, L832, L836, L865 );
nand2 U794 ( L1, L2, L3 );
nand2 U795 ( L4, L5, L6 );
nand2 U796 ( L7, L8, L9 );
nand2 U797 ( L10, L11, L12 );
nand2 U798 ( L1538, L1545, L14 );
nand2 U799 ( L1546, L1553, L17 );
nand2 U800 ( L1554, L1561, L20 );
nand2 U801 ( L1562, L1569, L23 );
nand2 U802 ( L1570, L1577, L26 );
nand2 U803 ( L28, L29, L30 );
nand2 U804 ( L1586, L1593, L32 );
nand2 U805 ( L1594, L1601, L35 );
nand2 U806 ( L1602, L1609, L38 );
nand2 U807 ( L1610, L1617, L41 );
nand2 U808 ( L43, L44, L45 );
nand2 U809 ( L46, L47, L48 );
and2 U810 ( L857, L859, L1913 );
and2 U811 ( L860, L862, L1921 );
nand2 U812 ( L13, L14, L15 );
nand2 U813 ( L16, L17, L18 );
nand2 U814 ( L19, L20, L21 );
nand2 U815 ( L22, L23, L24 );
nand2 U816 ( L25, L26, L27 );
nand2 U817 ( L31, L32, L33 );
nand2 U818 ( L34, L35, L36 );
nand2 U819 ( L37, L38, L39 );
nand2 U820 ( L40, L41, L42 );
and3 U821 ( L863, L865, L886, L887 );
nand2 U822 ( L863, L865, L462 );
and4 U823 ( L949, L867, L952, L887, L74 );
nand2 U824 ( L1913, L1916, L1637 );
inv U825 ( L1913, L1917 );
nand2 U826 ( L1921, L1924, L1647 );
inv U827 ( L1921, L1925 );
nor2 U828 ( L73, L74, L75 );
and3 U829 ( L457, L911, L462, L1020 );
and3 U830 ( L469, L911, L462, L1144 );
and3 U831 ( L475, L911, L462, L1386 );
and3 U832 ( L478, L911, L462, L1394 );
and3 U833 ( L459, L911, L462, L1402 );
nand2 U834 ( L1910, L1917, L1638 );
nand2 U835 ( L1918, L1925, L1648 );
and3 U836 ( L472, L911, L462, L1806 );
nand2 U837 ( L1637, L1638, L1639 );
nand2 U838 ( L1647, L1648, L1649 );
nand2 U839 ( L1020, L1029, L287 );
nand2 U840 ( L1144, L1153, L350 );
nand2 U841 ( L1386, L1393, L427 );
nand2 U842 ( L1394, L1401, L429 );
nand2 U843 ( L1402, L1409, L431 );
inv U844 ( L1020, L1028 );
inv U845 ( L1144, L1152 );
inv U846 ( L1386, L1392 );
inv U847 ( L1394, L1400 );
inv U848 ( L1402, L1408 );
inv U849 ( L1806, L1812 );
nand2 U850 ( L1806, L1813, L1216 );
nand2 U851 ( L1025, L1028, L286 );
nand2 U852 ( L1149, L1152, L349 );
nand2 U853 ( L1389, L1392, L426 );
nand2 U854 ( L1397, L1400, L428 );
nand2 U855 ( L1405, L1408, L430 );
nand2 U856 ( L1639, L1642, L67 );
inv U857 ( L1639, L1643 );
nand2 U858 ( L1649, L1652, L70 );
inv U859 ( L1649, L1653 );
nand2 U860 ( L1809, L1812, L1215 );
nand2 U861 ( L286, L287, L49 );
nand2 U862 ( L349, L350, L53 );
nand2 U863 ( L426, L427, L59 );
nand2 U864 ( L428, L429, L61 );
nand2 U865 ( L430, L431, L65 );
nand2 U866 ( L1634, L1643, L68 );
nand2 U867 ( L1644, L1653, L71 );
nand2 U868 ( L1215, L1216, L1217 );
and2 U869 ( L49, L50, L51 );
and2 U870 ( L52, L53, L54 );
and2 U871 ( L58, L59, L60 );
and2 U872 ( L61, L62, L63 );
and2 U873 ( L64, L65, L66 );
nand2 U874 ( L67, L68, L69 );
nand2 U875 ( L70, L71, L72 );
nand2 U876 ( L1217, L1220, L375 );
inv U877 ( L1217, L1221 );
nand2 U878 ( L1212, L1221, L376 );
nand2 U879 ( L375, L376, L55 );
and2 U880 ( L55, L56, L57 );
endmodule
|
Added c1908/c1908high.v.
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/****************************************************************************
* *
* VERILOG HIGH-LEVEL DESCRIPTION OF THE ISCAS-85 BENCHMARK CIRCUIT c1908 *
* *
* *
* Written by : Hakan Yalcin (hyalcin@cadence.com) *
* Verified by : Jonathan David Hauke (jhauke@eecs.umich.edu) *
* *
* First created: Jan 7, 1997 *
* Last modified: Oct 20, 1998 *
* *
****************************************************************************/
module Circuit1908(
in101, in104, in107, in110, in113, in116, in119,
in122, in125, in128, in131, in134, in137, in140, in143,
in146, in210, in214, in217, in221, in224, in227, in234,
in237, in469, in472, in475, in478, in898, in900, in902,
in952, in953,
out3, out6, out9, out12, out30, out45, out48,
out15, out18, out21, out24, out27, out33, out36, out39,
out42, out75, out51, out54, out60, out63, out66, out69,
out72, out57);
input
in101, in104, in107, in110, in113, in116, in119,
in122, in125, in128, in131, in134, in137, in140, in143,
in146, in210, in214, in217, in221, in224, in227, in234,
in237, in469, in472, in475, in478, in898, in900, in902,
in952, in953;
output
out3, out6, out9, out12, out30, out45, out48,
out15, out18, out21, out24, out27, out33, out36, out39,
out42, out75, out51, out54, out60, out63, out66, out69,
out72, out57;
wire [15:0] InDataBus, OutDataBus;
wire [5:0] InCheckBits, OutSynCheckBits;
wire [3:0] InExtSynBits;
wire ContE, ContB, ContF, ContG, ContH, ContK, ContL;
wire ByteParLo, ByteParHi, UncorrError;
/* In connections */
assign
InDataBus[15:0] = { in146, in143, in140, in137, in134, in131, in128,
in125, in122, in119, in116, in113, in110, in107,
in104, in101 };
assign
InCheckBits[5:0] = { in224, in221, in227, in210, in214, in217 };
// f e d c b a
assign
InExtSynBits[3:0] = { in469, in472, in475, in478 };
// s r q p
assign ContE = in902,
ContB = in953,
ContF = in952,
ContG = in234,
ContH = in237,
ContK = in898,
ContL = in900;
/* Out connections */
assign
{out48, out45, out42, out39, out36, out33,
out30, out27, out24, out21, out18, out15,
out12, out9, out6, out3} = OutDataBus[15:0];
assign
{ out51, out66, out54, out57, out60, out63 } = OutSynCheckBits[5:0];
assign out69 = ByteParLo,
out72 = ByteParHi,
out75 = UncorrError;
/* top level circuit */
TopLevel1908 Ckt1908(InDataBus, InCheckBits, InExtSynBits,
ContE, ContB, ContF, ContG, ContH, ContK, ContL,
OutDataBus, OutSynCheckBits,
ByteParLo, ByteParHi, UncorrError);
endmodule // Circuit1908
/*************************************************************************/
/*************************************************************************/
module TopLevel1908(InDataBus, InCheckBits, InExtSynBits,
ContE, ContB, ContF, ContG, ContH, ContK, ContL,
OutDataBus, OutSynCheckBits,
ByteParLo, ByteParHi, UncorrError);
input [15:0] InDataBus;
input [5:0] InCheckBits;
input [3:0] InExtSynBits;
input ContE, ContB, ContF, ContG, ContH, ContK, ContL;
output [15:0] OutDataBus;
output [5:0] OutSynCheckBits;
output ByteParLo, ByteParHi, UncorrError;
wire [5:0] SynBits, NewSynBits, Not_NewSynBits, AllExtSynBits;
/* AllExtSynBits=InExtSynBits+ 2 new ones generated from a,c,G,H,E */
wire ContIntM, ContIntP, CorrectionFlag;
wire CorrectionFlagLo, CorrectionFlagHi;
wire InDBParityLo, InDBParityHi;
wire [15:0] DecodedSyn;
wire [11:0] ProductSyn;
SyndromeGenerator M1(InDataBus, InCheckBits, ContB, ContG, ContH,
SynBits, InDBParityLo, InDBParityHi);
ModifySyndrome M2(SynBits, InExtSynBits, InCheckBits, ContE, ContG, ContH,
NewSynBits, Not_NewSynBits, AllExtSynBits,
ContIntM, ContIntP);
SyndromeDecode M3(NewSynBits, Not_NewSynBits, ContIntM, ContIntP,
ContE, ContB, ContF, ContG, ContH, ContK, ContL,
DecodedSyn, ProductSyn,
CorrectionFlag, CorrectionFlagLo, CorrectionFlagHi);
DataBusCorrect M4(InDataBus, DecodedSyn, OutDataBus);
SynCheckGenerator M5(SynBits, AllExtSynBits, CorrectionFlag, ContE, ContF, ContB,
OutSynCheckBits);
ByteParity M6(InDBParityHi, InCheckBits[3], CorrectionFlagHi, ContB, ContL,
ByteParHi);
ByteParity M7(InDBParityLo, InCheckBits[5], CorrectionFlagLo, ContB, ContK,
ByteParLo);
UncorrErrorGenerator M8(ProductSyn, Not_NewSynBits, CorrectionFlagHi, CorrectionFlagLo,
InCheckBits[1], InCheckBits[4],
ContE, ContF, ContB, ContG, ContH, ContIntM, ContIntP,
UncorrError);
endmodule // TopLevel1908
/*************************************************************************
* Module SyndromeGenerator
*
* Function: Generate a 6-bit syndrome (SynBits) from a 16-bit data bus
* (InDataBus) and 6 checkbits (InCheckBits). InCheckbits are masked/modified
* with control inputs ContB, ContG and ContH.
* Also generated are the parities of the high and low byte of InDataBus
* called InDBParityHi and InDBParityLo.
*
***************************************************************************/
module SyndromeGenerator(InDataBus, InCheckBits, ContB, ContG, ContH,
SynBits, InDBParityLo, InDBParityHi);
input [15:0] InDataBus;
input [5:0] InCheckBits;
input ContB, ContG, ContH;
output [5:0] SynBits;
output InDBParityLo, InDBParityHi;
wire [15:0] NotInDataBus;
inv UM1_0( .A(ContB), .Y(Not_ContB) );
inv UM1_1( .A(ContH), .Y(Not_ContH) );
and3 UM1_2( .A(InCheckBits[0]), .B(ContG), .C(Not_ContB), .Y(temp0) );
and3 UM1_3( .A(InCheckBits[1]), .B(Not_ContH), .C(Not_ContB), .Y(temp1) );
and3 UM1_4( .A(InCheckBits[2]), .B(Not_ContH), .C(Not_ContB), .Y(temp2) );
and2 UM1_5( .A(InCheckBits[3]), .B(Not_ContB), .Y(temp3) );
and3 UM1_6( .A(InCheckBits[4]), .B(ContG), .C(Not_ContB), .Y(temp4) );
and2 UM1_7( .A(InCheckBits[5]), .B(Not_ContB), .Y(temp5) );
inv UM1_8( .A(InDataBus[0]), .Y(NotInDataBus[0]) ),
UM1_9( .A(InDataBus[1]), .Y(NotInDataBus[1]) ),
UM1_10( .A(InDataBus[2]), .Y(NotInDataBus[2]) ),
UM1_11( .A(InDataBus[3]), .Y(NotInDataBus[3]) ),
UM1_12( .A(InDataBus[4]), .Y(NotInDataBus[4]) ),
UM1_13( .A(InDataBus[5]), .Y(NotInDataBus[5]) ),
UM1_14( .A(InDataBus[6]), .Y(NotInDataBus[6]) ),
UM1_15( .A(InDataBus[7]), .Y(NotInDataBus[7]) ),
UM1_16( .A(InDataBus[8]), .Y(NotInDataBus[8]) ),
UM1_17( .A(InDataBus[9]), .Y(NotInDataBus[9]) ),
UM1_18( .A(InDataBus[10]), .Y(NotInDataBus[10]) ),
UM1_19( .A(InDataBus[11]), .Y(NotInDataBus[11]) ),
UM1_20( .A(InDataBus[12]), .Y(NotInDataBus[12]) ),
UM1_21( .A(InDataBus[13]), .Y(NotInDataBus[13]) ),
UM1_22( .A(InDataBus[14]), .Y(NotInDataBus[14]) ),
UM1_23( .A(InDataBus[15]), .Y(NotInDataBus[15]) );
/* Parity trees for SynBits[5:0] */
xor2 UM1_46( .A(NotInDataBus[7]), .B(NotInDataBus[5]), .Y(line46) );
xor2 UM1_47( .A(line46), .B(NotInDataBus[2]), .Y(line47) );
xor2 UM1_48( .A(NotInDataBus[14]), .B(NotInDataBus[9]), .Y(line48) );
xor2 UM1_49( .A(line48), .B(NotInDataBus[11]), .Y(line49) );
xor2 UM1_50( .A(line47), .B(line49), .Y(line50) );
xor2 UM1_51( .A(line50), .B(temp0), .Y(SynBits[0]) );
xor2 UM1_38( .A(NotInDataBus[8]), .B(NotInDataBus[13]), .Y(line38) );
xor2 UM1_39( .A(line38), .B(NotInDataBus[15]), .Y(line39) );
xor2 UM1_40( .A(NotInDataBus[14]), .B(temp1), .Y(line40) );
xor2 UM1_41( .A(line40), .B(NotInDataBus[10]), .Y(line41) );
xor2 UM1_42( .A(line39), .B(line41), .Y(line42) );
xor2 UM1_43( .A(NotInDataBus[7]), .B(NotInDataBus[4]), .Y(line43) );
xor2 UM1_44( .A(line43), .B(NotInDataBus[1]), .Y(line44) );
xor2 UM1_45( .A(line42), .B(line44), .Y(SynBits[1]) );
xor2 UM1_24( .A(NotInDataBus[0]), .B(temp2), .Y(line24) );
xor2 UM1_25( .A(NotInDataBus[12]), .B(NotInDataBus[11]), .Y(line25) );
xor2 UM1_26( .A(line25), .B(NotInDataBus[10]), .Y(line26) );
inv UM1_27( .A(line26), .Y(line27) );
xor2 UM1_28( .A(NotInDataBus[15]), .B(NotInDataBus[14]), .Y(line28) );
xor2 UM1_29( .A(line28), .B(NotInDataBus[9]), .Y(line29) );
xor2 UM1_30( .A(line27), .B(line29), .Y(line30) );
xor2 UM1_31( .A(NotInDataBus[6]), .B(NotInDataBus[5]), .Y(line31) );
xor2 UM1_32( .A(line31), .B(NotInDataBus[4]), .Y(line32) );
inv UM1_33( .A(line32), .Y(line33) );
xor2 UM1_34( .A(line30), .B(line33), .Y(line34) );
inv UM1_35( .A(line34), .Y(line35) );
inv UM1_36( .A(line24), .Y(line36) );
xor2 UM1_37( .A(line36), .B(line35), .Y(SynBits[2]) );
xor2 UM1_76( .A(NotInDataBus[3]), .B(NotInDataBus[13]), .Y(line76) );
xor2 UM1_77( .A(line76), .B(temp3), .Y(line77) );
xor2 UM1_78( .A(NotInDataBus[2]), .B(NotInDataBus[1]), .Y(line78) );
xor2 UM1_79( .A(line78), .B(NotInDataBus[0]), .Y(line79) );
xor2 UM1_80( .A(NotInDataBus[15]), .B(NotInDataBus[14]), .Y(line80) );
xor2 UM1_81( .A(line80), .B(NotInDataBus[9]), .Y(line81) );
inv UM1_82( .A(line81), .Y(line82) );
xor2 UM1_83( .A(line79), .B(line82), .Y(line83) );
xor2 UM1_84( .A(line83), .B(line27), .Y(line84) );
inv UM1_85( .A(line84), .Y(line85) );
xor2 UM1_86( .A(line77), .B(line85), .Y(SynBits[3]) );
xor2 UM1_52( .A(NotInDataBus[8]), .B(NotInDataBus[13]), .Y(line52) );
xor2 UM1_53( .A(line52), .B(NotInDataBus[15]), .Y(line53) );
inv UM1_54( .A(line53), .Y(line54) );
xor2 UM1_55( .A(NotInDataBus[9]), .B(NotInDataBus[6]), .Y(line55) );
xor2 UM1_56( .A(line55), .B(NotInDataBus[3]), .Y(line56) );
inv UM1_57( .A(line56), .Y(line57) );
xor2 UM1_58( .A(line54), .B(line57), .Y(line58) );
xor2 UM1_59( .A(temp4), .B(NotInDataBus[12]), .Y(line59) );
inv UM1_60( .A(line59), .Y(line60) );
xor2 UM1_61( .A(line58), .B(line60), .Y(SynBits[4]) );
xor2 UM1_62( .A(line29), .B(NotInDataBus[8]), .Y(line62) );
xor2 UM1_63( .A(line62), .B(temp5), .Y(line63) );
inv UM1_64( .A(line63), .Y(line64) );
xor2 UM1_65( .A(NotInDataBus[2]), .B(NotInDataBus[1]), .Y(line65) );
xor2 UM1_66( .A(line65), .B(NotInDataBus[0]), .Y(line66) );
inv UM1_67( .A(line66), .Y(line67) );
xor2 UM1_68( .A(NotInDataBus[6]), .B(NotInDataBus[5]), .Y(line68) );
xor2 UM1_69( .A(line68), .B(NotInDataBus[4]), .Y(line69) );
xor2 UM1_70( .A(line67), .B(line69), .Y(line70) );
xor2 UM1_71( .A(NotInDataBus[7]), .B(NotInDataBus[3]), .Y(line71) );
inv UM1_72( .A(line71), .Y(line72) );
xor2 UM1_73( .A(line70), .B(line72), .Y(line73) );
xor2 UM1_74( .A(line64), .B(line73), .Y(line74) );
inv UM1_75( .A(line74), .Y(SynBits[5]) );
/* Parity trees for the low and high byte of InDataBus: InDBParityLo, InDBParityHi */
xor2 UM1_87( .A(line67), .B(line69), .Y(line87) );
xor2 UM1_88( .A(line87), .B(line72), .Y(InDBParityLo) );
xor2 UM1_89( .A(NotInDataBus[12]), .B(NotInDataBus[11]), .Y(line89) );
xor2 UM1_90( .A(line89), .B(NotInDataBus[10]), .Y(line90) );
xor2 UM1_91( .A(line82), .B(line90), .Y(line91) );
xor2 UM1_92( .A(NotInDataBus[13]), .B(NotInDataBus[8]), .Y(line92) );
inv UM1_93( .A(line92), .Y(line93) );
xor2 UM1_94( .A(line91), .B(line93), .Y(InDBParityHi) );
endmodule // SyndromeGenerator
/*************************************************************************
* Module ModifySyndrome
*
* Function: The 6-bit syndrome (SynBits) is masked with Not_ContE,
* and xor'ed with AllExtSynBits, which are made up of InExtSynBits
* plus two more lines obtained from InCheckBits[0], InCheckBits[2]
* and some control inputs. The external syndrome bits are probably
* used when the c1908 is cascaded to handle words of size>=16.
* The output is a modified 6-bit syndrome NewSynBits and its
* complement Not_NewSynBits.
*
***************************************************************************/
module ModifySyndrome(SynBits, InExtSynBits, InCheckBits, ContE, ContG, ContH,
NewSynBits, Not_NewSynBits, AllExtSynBits,
ContIntM, ContIntP);
input [5:0] SynBits;
input [3:0] InExtSynBits;
input [5:0] InCheckBits;
input ContE, ContG, ContH;
output [5:0] NewSynBits, Not_NewSynBits, AllExtSynBits;
output ContIntM, ContIntP;
inv UM2_0( .A(ContE), .Y(Not_ContE) );
and2 UM2_1( .A(SynBits[0]), .B(Not_ContE), .Y(temp0) ),
UM2_2( .A(SynBits[1]), .B(Not_ContE), .Y(temp1) ),
UM2_3( .A(SynBits[2]), .B(Not_ContE), .Y(temp2) ),
UM2_4( .A(SynBits[3]), .B(Not_ContE), .Y(temp3) ),
UM2_5( .A(SynBits[4]), .B(Not_ContE), .Y(temp4) ),
UM2_6( .A(SynBits[5]), .B(Not_ContE), .Y(temp5) );
assign AllExtSynBits[3:0] = InExtSynBits[3:0];
nand2 UM2_7( .A(ContG), .B(Not_ContE), .Y(line7) );
and2 UM2_8( .A(InCheckBits[0]), .B(line7), .Y(AllExtSynBits[4]) );
inv UM2_9( .A(ContH), .Y(Not_ContH) );
nand2 UM2_10( .A(Not_ContH), .B(Not_ContE), .Y(line10) );
and2 UM2_11( .A(line10), .B(InCheckBits[2]), .Y(AllExtSynBits[5]) );
nand2 UM2_12( .A(InCheckBits[1]), .B(line10), .Y(ContIntM) );
nand2 UM2_13( .A(InCheckBits[4]), .B(line7), .Y(ContIntP) );
xor2 UM2_14( .A(temp0), .B(AllExtSynBits[0]), .Y(NewSynBits[0]) ),
UM2_15( .A(temp1), .B(AllExtSynBits[1]), .Y(NewSynBits[1]) ),
UM2_16( .A(temp2), .B(AllExtSynBits[2]), .Y(NewSynBits[2]) ),
UM2_17( .A(temp3), .B(AllExtSynBits[3]), .Y(NewSynBits[3]) ),
UM2_18( .A(temp4), .B(AllExtSynBits[4]), .Y(NewSynBits[4]) ),
UM2_19( .A(temp5), .B(AllExtSynBits[5]), .Y(NewSynBits[5]) );
inv UM2_20( .A(NewSynBits[0]), .Y(Not_NewSynBits[0]) ),
UM2_21( .A(NewSynBits[1]), .Y(Not_NewSynBits[1]) ),
UM2_22( .A(NewSynBits[2]), .Y(Not_NewSynBits[2]) ),
UM2_23( .A(NewSynBits[3]), .Y(Not_NewSynBits[3]) ),
UM2_24( .A(NewSynBits[4]), .Y(Not_NewSynBits[4]) ),
UM2_25( .A(NewSynBits[5]), .Y(Not_NewSynBits[5]) );
endmodule // ModifySyndrome
/*************************************************************************
* Module SyndromeDecode
*
* Function: The syndrome bits (NewSynBits, Not_NewSynBits) are decoded
* to identify the bit in error. The result is DecodedSyn, whose ith
* bit indicates whether the ith input should be corrected: 1 if so,
* 0 otherwise. At most one bit can be equal to 1, that is, single
* error correction. The correction can be masked by appropriately setting
* the control inputs.
* ProductSyn are intermediate product terms, also used by module
* UncorrErrorGenerator. If any DecodedSyn bit is set to 1, CorrectionFlag
* becomes 1. Similarly, CorrectionFlagLo and CorrectionFlagHi indicate
* whether correction is performed for the low and high byte of InDataBus,
* respectively.
*
***************************************************************************/
module SyndromeDecode(NewSynBits, Not_NewSynBits, ContIntM, ContIntP,
ContE, ContB, ContF, ContG, ContH, ContK, ContL,
DecodedSyn, ProductSyn,
CorrectionFlag, CorrectionFlagLo, CorrectionFlagHi);
input [5:0] NewSynBits, Not_NewSynBits;
input ContIntM, ContIntP;
input ContE, ContB, ContF, ContG, ContH, ContK, ContL;
output [15:0] DecodedSyn;
output [11:0] ProductSyn;
output CorrectionFlag, CorrectionFlagLo, CorrectionFlagHi;
inv UM3_0( .A(ContK), .Y(Not_ContK) );
inv UM3_1( .A(ContL), .Y(Not_ContL) );
inv UM3_2( .A(ContB), .Y(Not_ContB) );
nand2 UM3_3( .A(ContG), .B(ContH), .Y(NotGH) );
nand4 UM3_4( .A(Not_ContK), .B(ContE), .C(ContB), .D(NotGH), .Y(line4) );
nand3 UM3_5( .A(ContF), .B(Not_ContB), .C(NotGH), .Y(line5) );
nand2 UM3_6( .A(line4), .B(line5), .Y(ContIntLo) );
nand4 UM3_7( .A(Not_ContL), .B(ContE), .C(ContB), .D(NotGH), .Y(line7) );
nand2 UM3_8( .A(line7), .B(line5), .Y(ContIntHi) );
and2 UM3_9 ( .A(ContIntM), .B(NewSynBits[5]), .Y(ProductSyn[0]) ),
UM3_10( .A(Not_NewSynBits[0]), .B(Not_NewSynBits[1]), .Y(ProductSyn[1]) ),
UM3_11( .A(Not_NewSynBits[4]), .B(Not_NewSynBits[2]), .Y(ProductSyn[2]) ),
UM3_12( .A(Not_NewSynBits[0]), .B(NewSynBits[1]), .Y(ProductSyn[3]) ),
UM3_13( .A(NewSynBits[0]), .B(Not_NewSynBits[1]), .Y(ProductSyn[4]) ),
UM3_14( .A(NewSynBits[4]), .B(Not_NewSynBits[2]), .Y(ProductSyn[5]) ),
UM3_15( .A(ContIntP), .B(Not_NewSynBits[3]), .Y(ProductSyn[6]) ),
UM3_16( .A(NewSynBits[4]), .B(NewSynBits[2]), .Y(ProductSyn[7]) ),
UM3_17( .A(ContIntM), .B(Not_NewSynBits[5]), .Y(ProductSyn[8]) ),
UM3_18( .A(Not_NewSynBits[4]), .B(NewSynBits[2]), .Y(ProductSyn[9]) ),
UM3_19( .A(ContIntP), .B(NewSynBits[3]), .Y(ProductSyn[10]) ),
UM3_20( .A(NewSynBits[0]), .B(NewSynBits[1]), .Y(ProductSyn[11]) );
and5 UM3_21( .A(ProductSyn[0]), .B(ProductSyn[10]), .C(ProductSyn[9]),
.D(ProductSyn[1]), .E(ContIntLo), .Y(DecodedSyn[0]) ),
UM3_22( .A(ProductSyn[0]), .B(ProductSyn[10]), .C(ProductSyn[2]),
.D(ProductSyn[3]), .E(ContIntLo), .Y(DecodedSyn[1]) ),
UM3_23( .A(ProductSyn[0]), .B(ProductSyn[10]), .C(ProductSyn[2]),
.D(ProductSyn[4]), .E(ContIntLo), .Y(DecodedSyn[2]) ),
UM3_24( .A(ProductSyn[0]), .B(ProductSyn[10]), .C(ProductSyn[5]),
.D(ProductSyn[1]), .E(ContIntLo), .Y(DecodedSyn[3]) ),
UM3_25( .A(ProductSyn[0]), .B(ProductSyn[6]), .C(ProductSyn[9]),
.D(ProductSyn[3]), .E(ContIntLo), .Y(DecodedSyn[4]) ),
UM3_26( .A(ProductSyn[0]), .B(ProductSyn[6]), .C(ProductSyn[9]),
.D(ProductSyn[4]), .E(ContIntLo), .Y(DecodedSyn[5]) ),
UM3_27( .A(ProductSyn[0]), .B(ProductSyn[6]), .C(ProductSyn[7]),
.D(ProductSyn[1]), .E(ContIntLo), .Y(DecodedSyn[6]) ),
UM3_28( .A(ProductSyn[0]), .B(ProductSyn[6]), .C(ProductSyn[2]),
.D(ProductSyn[11]), .E(ContIntLo), .Y(DecodedSyn[7]) ),
UM3_29( .A(ProductSyn[0]), .B(ProductSyn[6]), .C(ProductSyn[5]),
.D(ProductSyn[3]), .E(ContIntHi), .Y(DecodedSyn[8]) ),
UM3_30( .A(ProductSyn[0]), .B(ProductSyn[10]), .C(ProductSyn[7]),
.D(ProductSyn[4]), .E(ContIntHi), .Y(DecodedSyn[9]) ),
UM3_31( .A(ProductSyn[8]), .B(ProductSyn[10]), .C(ProductSyn[9]),
.D(ProductSyn[3]), .E(ContIntHi), .Y(DecodedSyn[10]) ),
UM3_32( .A(ProductSyn[8]), .B(ProductSyn[10]), .C(ProductSyn[9]),
.D(ProductSyn[4]), .E(ContIntHi), .Y(DecodedSyn[11]) ),
UM3_33( .A(ProductSyn[8]), .B(ProductSyn[10]), .C(ProductSyn[7]),
.D(ProductSyn[1]), .E(ContIntHi), .Y(DecodedSyn[12]) ),
UM3_34( .A(ProductSyn[8]), .B(ProductSyn[10]), .C(ProductSyn[5]),
.D(ProductSyn[3]), .E(ContIntHi), .Y(DecodedSyn[13]) ),
UM3_35( .A(ProductSyn[0]), .B(ProductSyn[10]), .C(ProductSyn[9]),
.D(ProductSyn[11]), .E(ContIntHi), .Y(DecodedSyn[14]) ),
UM3_36( .A(ProductSyn[0]), .B(ProductSyn[10]), .C(ProductSyn[7]),
.D(ProductSyn[3]), .E(ContIntHi), .Y(DecodedSyn[15]) );
or8 UM3_37( .A(DecodedSyn[0]), .B(DecodedSyn[1]), .C(DecodedSyn[2]),
.D(DecodedSyn[3]), .E(DecodedSyn[4]), .F(DecodedSyn[5]),
.G(DecodedSyn[6]), .H(DecodedSyn[7]), .Y(CorrectionFlagLo) );
or8 UM3_38( .A(DecodedSyn[8]), .B(DecodedSyn[9]), .C(DecodedSyn[10]),
.D(DecodedSyn[11]), .E(DecodedSyn[12]), .F(DecodedSyn[13]),
.G(DecodedSyn[14]), .H(DecodedSyn[15]), .Y(CorrectionFlagHi) );
or2 UM3_39( .A(CorrectionFlagLo), .B(CorrectionFlagHi), .Y(CorrectionFlag) );
endmodule // SyndromeDecode
/*************************************************************************
* Module DataBusCorrect
*
* Function: InDataBus is xor'ed with DecodedSyn for correcting
* the bit in error, if there is any and if the control inputs are set
* to do so.
*
***************************************************************************/
module DataBusCorrect(InDataBus, DecodedSyn, OutDataBus);
input [15:0] InDataBus, DecodedSyn;
output [15:0] OutDataBus;
xor2 UM4_0( .A(InDataBus[0]), .B(DecodedSyn[0]), .Y(OutDataBus[0]) ),
UM4_1( .A(InDataBus[1]), .B(DecodedSyn[1]), .Y(OutDataBus[1]) ),
UM4_2( .A(InDataBus[2]), .B(DecodedSyn[2]), .Y(OutDataBus[2]) ),
UM4_3( .A(InDataBus[3]), .B(DecodedSyn[3]), .Y(OutDataBus[3]) ),
UM4_4( .A(InDataBus[4]), .B(DecodedSyn[4]), .Y(OutDataBus[4]) ),
UM4_5( .A(InDataBus[5]), .B(DecodedSyn[5]), .Y(OutDataBus[5]) ),
UM4_6( .A(InDataBus[6]), .B(DecodedSyn[6]), .Y(OutDataBus[6]) ),
UM4_7( .A(InDataBus[7]), .B(DecodedSyn[7]), .Y(OutDataBus[7]) ),
UM4_8( .A(InDataBus[8]), .B(DecodedSyn[8]), .Y(OutDataBus[8]) ),
UM4_9( .A(InDataBus[9]), .B(DecodedSyn[9]), .Y(OutDataBus[9]) ),
UM4_10( .A(InDataBus[10]), .B(DecodedSyn[10]), .Y(OutDataBus[10]) ),
UM4_11( .A(InDataBus[11]), .B(DecodedSyn[11]), .Y(OutDataBus[11]) ),
UM4_12( .A(InDataBus[12]), .B(DecodedSyn[12]), .Y(OutDataBus[12]) ),
UM4_13( .A(InDataBus[13]), .B(DecodedSyn[13]), .Y(OutDataBus[13]) ),
UM4_14( .A(InDataBus[14]), .B(DecodedSyn[14]), .Y(OutDataBus[14]) ),
UM4_15( .A(InDataBus[15]), .B(DecodedSyn[15]), .Y(OutDataBus[15]) );
endmodule // DataBusCorrect
/*************************************************************************
* Module SynCheckGenerator
*
* Function: computes the OutSynCheckBits, which are the syndrome or check
* bits depending on the mode being activated.
*
***************************************************************************/
module SynCheckGenerator(SynBits, AllExtSynBits, CorrectionFlag, ContE,
ContF, ContB, OutSynCheckBits);
input [5:0] SynBits, AllExtSynBits;
input CorrectionFlag;
input ContE, ContF, ContB;
output [5:0] OutSynCheckBits;
inv UM5_0( .A(ContF), .Y(Not_ContF) );
SynCheckSlice UM5_1(SynBits[0], AllExtSynBits[0], CorrectionFlag, ContE,
Not_ContF, ContB, OutSynCheckBits[0]),
UM5_2(SynBits[1], AllExtSynBits[1], CorrectionFlag, ContE,
Not_ContF, ContB, OutSynCheckBits[1]),
UM5_3(SynBits[2], AllExtSynBits[2], CorrectionFlag, ContE,
Not_ContF, ContB, OutSynCheckBits[2]),
UM5_4(SynBits[3], AllExtSynBits[3], CorrectionFlag, ContE,
Not_ContF, ContB, OutSynCheckBits[3]),
UM5_5(SynBits[4], AllExtSynBits[4], CorrectionFlag, ContE,
Not_ContF, ContB, OutSynCheckBits[4]),
UM5_6(SynBits[5], AllExtSynBits[5], CorrectionFlag, ContE,
Not_ContF, ContB, OutSynCheckBits[5]);
endmodule // SynCheckGenerator
/************************************************/
module SynCheckSlice(SynBits_i, AllExtSynBits_i, CorrectionFlag, ContE,
NotContF, ContB, OutSynCheckBits_i);
input SynBits_i, AllExtSynBits_i;
input CorrectionFlag;
input ContE, NotContF, ContB;
output OutSynCheckBits_i;
and3 SCS_0( .A(AllExtSynBits_i), .B(ContE), .C(CorrectionFlag), .Y(line0) );
xor2 SCS_1( .A(SynBits_i), .B(line0), .Y(line1) );
nand2 SCS_2( .A(NotContF), .B(ContB), .Y(line2) );
and2 SCS_3( .A(line2), .B(line1), .Y(OutSynCheckBits_i) );
endmodule // SynCheckSlice
/*************************************************************************
* Module Byteparity
*
* Function: computes the corrected parity for low/high byte of InDataBus.
*
***************************************************************************/
module ByteParity (InDBParity_N, InCheckBit_N, CorrectionFlag_N, ContB, Cont_N,
ByteParity_N);
input InDBParity_N, InCheckBit_N, CorrectionFlag_N;
input ContB, Cont_N;
output ByteParity_N;
inv UM6_7_0( .A(ContB), .Y(Not_ContB) ),
UM6_7_1( .A(Cont_N), .Y(Not_Cont_N) ),
UM6_7_2( .A(InDBParity_N), .Y(Not_InDBParity_N) );
nand2 UM6_7_3( .A(ContB), .B(Not_Cont_N), .Y(line3) );
and2 UM6_7_4( .A(line3), .B(Not_InDBParity_N), .Y(line4) );
and2 UM6_7_5( .A(CorrectionFlag_N), .B(Not_ContB), .Y(line5) );
xor2 UM6_7_6( .A(line5), .B(line4), .Y(line6) );
nand2 UM6_7_7( .A(InCheckBit_N), .B(Cont_N), .Y(line7) );
and2 UM6_7_8( .A(line7), .B(ContB), .Y(line8) );
xor2 UM6_7_9( .A(line6), .B(line8), .Y(ByteParity_N) );
endmodule // ByteParity
/*************************************************************************
* Module UncorrErrorGenerator
*
* Function: computes the final uncorrectable error signal (UncorrError)
* from UESignal, the error-free syndrome (ErrorFREE), the CorrectionFlag's,
* and some control inputs.
*
***************************************************************************/
module UncorrErrorGenerator (ProductSyn, Not_NewSynBits, CorrectionFlagHi, CorrectionFlagLo,
InCheckBit1, InCheckBit4,
ContE,ContF, ContB, ContG, ContH, ContIntM, ContIntP,
UncorrError);
input [11:0] ProductSyn;
input [5:0] Not_NewSynBits;
input InCheckBit1, InCheckBit4;
input CorrectionFlagHi, CorrectionFlagLo;
input ContE, ContF, ContB, ContG, ContH, ContIntM, ContIntP;
output UncorrError;
wire UESignal, ErrorFREE;
inv UM8_0( .A(ContH), .Y(Not_ContH) ),
UM8_1( .A(ContE), .Y(Not_ContE) ),
UM8_2( .A(ContB), .Y(Not_ContB) ),
UM8_3( .A(ContF), .Y(Not_ContF) ),
UM8_4( .A(ContIntM), .Y(NotM) ),
UM8_5( .A(ContIntP), .Y(NotP) );
nand2 UM8_6( .A(ContG), .B(ContH), .Y(NotGH) );
and3 UM8_7( .A(ContF), .B(Not_ContB), .C(NotGH), .Y(ContIntUE) );
UEGen UM8_8(ProductSyn, ContIntUE, NotM, NotP, Not_NewSynBits[3], Not_NewSynBits[5],
UESignal);
nand2 UM8_9( .A(Not_ContH), .B(Not_ContE), .Y(line9) ),
UM8_10( .A(InCheckBit1), .B(line9), .Y(line10) ),
UM8_11( .A(ContG), .B(Not_ContE), .Y(line11) ),
UM8_12( .A(InCheckBit4), .B(line11), .Y(line12 ) );
nand8 UM8_13( .A(Not_NewSynBits[0]), .B(Not_NewSynBits[1]), .C(Not_NewSynBits[2]),
.D(Not_NewSynBits[3]), .E(Not_NewSynBits[4]), .F(Not_NewSynBits[5]),
.G(line10), .H(line12), .Y(ErrorFREE) );
inv UM8_14( .A(CorrectionFlagHi), .Y(NotCorrFlagHi) ),
UM8_15( .A(CorrectionFlagLo), .Y(NotCorrFlagLo) );
and3 UM8_16( .A(NotCorrFlagLo), .B(NotCorrFlagHi), .C(UESignal), .Y(line16) );
and4 UM8_17( .A(Not_ContB), .B(ErrorFREE), .C(ContF), .D(line16), .Y(line17) );
and3 UM8_18( .A(Not_ContB), .B(ErrorFREE), .C(Not_ContF), .Y(line18) );
nor2 UM8_19( .A(line18), .B(line17), .Y(UncorrError) );
endmodule // UncorrErrorGenerator
/**************************************************************
* Module UEGen
*
* Function: computes the uncorrectable error signal (UESignal)
* from the product terms of the syndrome (ProductSyn).
* UESignal can be masked by control inputs.
*
***************************************************************/
module UEGen(ProductSyn, ContIntUE, NotM, NotP, NotNewSynBit3, NotNewSynBit5,
UESignal);
input [11:0] ProductSyn;
input ContIntUE, NotM, NotP, NotNewSynBit3, NotNewSynBit5;
output UESignal;
and2 UEG_0( .A(NotP), .B(NotNewSynBit3), .Y(line0) ),
UEG_1( .A(NotM), .B(NotNewSynBit5), .Y(line1) );
nand5 UEG_2( .A(ProductSyn[0]), .B(ProductSyn[6]), .C(ProductSyn[2]),
.D(ProductSyn[1]), .E(ContIntUE), .Y(line2) ),
UEG_3( .A(ProductSyn[8]), .B(ProductSyn[10]), .C(ProductSyn[2]),
.D(ProductSyn[1]), .E(ContIntUE), .Y(line3) ),
UEG_4( .A(ProductSyn[8]), .B(ProductSyn[6]), .C(ProductSyn[9]),
.D(ProductSyn[1]), .E(ContIntUE), .Y(line4) ),
UEG_5( .A(ProductSyn[8]), .B(ProductSyn[6]), .C(ProductSyn[2]),
.D(ProductSyn[3]), .E(ContIntUE), .Y(line5) ),
UEG_6( .A(ProductSyn[8]), .B(ProductSyn[6]), .C(ProductSyn[2]),
.D(ProductSyn[4]), .E(ContIntUE), .Y(line6) ),
UEG_7( .A(ProductSyn[8]), .B(ProductSyn[6]), .C(ProductSyn[5]),
.D(ProductSyn[1]), .E(ContIntUE), .Y(line7) ),
UEG_8( .A(ProductSyn[8]), .B(line0), .C(ProductSyn[2]),
.D(ProductSyn[1]), .E(ContIntUE), .Y(line8) ),
UEG_9( .A(line1), .B(ProductSyn[6]), .C(ProductSyn[2]),
.D(ProductSyn[1]), .E(ContIntUE), .Y(line9) );
and8 UEG_10( .A(line2), .B(line3), .C(line4), .D(line5), .E(line6),
.F(line7), .G(line8), .H(line9), .Y(UESignal) );
endmodule // UEGen
|
Added c1908/flat1908.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 | /**************************************************************************** * * * FLAT VERSION of HIGH-LEVEL MODEL for c1908 * * * * * * Generated by: Hakan Yalcin (hyalcin@cadence.com) * * Verified by: Jonathan David Hauke (jhauke@eecs.umich.edu) * * * * Oct 20, 1998 * * * ****************************************************************************/ // Flat Verilog File module c1908g ( in101, in104, in107, in110, in113, in116, in119, in122, in125, in128, in131, in134, in137, in140, in143, in146, in210, in214, in217, in221, in224, in227, in234, in237, in469, in472, in475, in478, in898, in900, in902, in952, in953, out3, out6, out9, out12, out30, out45, out48, out15, out18, out21, out24, out27, out33, out36, out39, out42, out75, out51, out54, out60, out63, out66, out69, out72, out57); input in101, in104, in107, in110, in113, in116, in119, in122, in125, in128, in131, in134, in137, in140, in143, in146, in210, in214, in217, in221, in224, in227, in234, in237, in469, in472, in475, in478, in898, in900, in902, in952, in953; output out3, out6, out9, out12, out30, out45, out48, out15, out18, out21, out24, out27, out33, out36, out39, out42, out75, out51, out54, out60, out63, out66, out69, out72, out57; inv M1_UM1_0(in953, M1_Not_ContB); inv M1_UM1_1(in237, M1_Not_ContH); and3 M1_UM1_2(in217, in234, M1_Not_ContB, M1_temp0); and3 M1_UM1_3(in214, M1_Not_ContH, M1_Not_ContB, M1_temp1); and3 M1_UM1_4(in210, M1_Not_ContH, M1_Not_ContB, M1_temp2); and2 M1_UM1_5(in227, M1_Not_ContB, M1_temp3); and3 M1_UM1_6(in221, in234, M1_Not_ContB, M1_temp4); and2 M1_UM1_7(in224, M1_Not_ContB, M1_temp5); inv M1_UM1_8(in101, M1_NotInDataBus_0); inv M1_UM1_9(in104, M1_NotInDataBus_1); inv M1_UM1_10(in107, M1_NotInDataBus_2); inv M1_UM1_11(in110, M1_NotInDataBus_3); inv M1_UM1_12(in113, M1_NotInDataBus_4); inv M1_UM1_13(in116, M1_NotInDataBus_5); inv M1_UM1_14(in119, M1_NotInDataBus_6); inv M1_UM1_15(in122, M1_NotInDataBus_7); inv M1_UM1_16(in125, M1_NotInDataBus_8); inv M1_UM1_17(in128, M1_NotInDataBus_9); inv M1_UM1_18(in131, M1_NotInDataBus_10); inv M1_UM1_19(in134, M1_NotInDataBus_11); inv M1_UM1_20(in137, M1_NotInDataBus_12); inv M1_UM1_21(in140, M1_NotInDataBus_13); inv M1_UM1_22(in143, M1_NotInDataBus_14); inv M1_UM1_23(in146, M1_NotInDataBus_15); xor2 M1_UM1_46(M1_NotInDataBus_7, M1_NotInDataBus_5, M1_line46); xor2 M1_UM1_47(M1_line46, M1_NotInDataBus_2, M1_line47); xor2 M1_UM1_48(M1_NotInDataBus_14, M1_NotInDataBus_9, M1_line48); xor2 M1_UM1_49(M1_line48, M1_NotInDataBus_11, M1_line49); xor2 M1_UM1_50(M1_line47, M1_line49, M1_line50); xor2 M1_UM1_51(M1_line50, M1_temp0, SynBits_0); xor2 M1_UM1_38(M1_NotInDataBus_8, M1_NotInDataBus_13, M1_line38); xor2 M1_UM1_39(M1_line38, M1_NotInDataBus_15, M1_line39); xor2 M1_UM1_40(M1_NotInDataBus_14, M1_temp1, M1_line40); xor2 M1_UM1_41(M1_line40, M1_NotInDataBus_10, M1_line41); xor2 M1_UM1_42(M1_line39, M1_line41, M1_line42); xor2 M1_UM1_43(M1_NotInDataBus_7, M1_NotInDataBus_4, M1_line43); xor2 M1_UM1_44(M1_line43, M1_NotInDataBus_1, M1_line44); xor2 M1_UM1_45(M1_line42, M1_line44, SynBits_1); xor2 M1_UM1_24(M1_NotInDataBus_0, M1_temp2, M1_line24); xor2 M1_UM1_25(M1_NotInDataBus_12, M1_NotInDataBus_11, M1_line25); xor2 M1_UM1_26(M1_line25, M1_NotInDataBus_10, M1_line26); inv M1_UM1_27(M1_line26, M1_line27); xor2 M1_UM1_28(M1_NotInDataBus_15, M1_NotInDataBus_14, M1_line28); xor2 M1_UM1_29(M1_line28, M1_NotInDataBus_9, M1_line29); xor2 M1_UM1_30(M1_line27, M1_line29, M1_line30); xor2 M1_UM1_31(M1_NotInDataBus_6, M1_NotInDataBus_5, M1_line31); xor2 M1_UM1_32(M1_line31, M1_NotInDataBus_4, M1_line32); inv M1_UM1_33(M1_line32, M1_line33); xor2 M1_UM1_34(M1_line30, M1_line33, M1_line34); inv M1_UM1_35(M1_line34, M1_line35); inv M1_UM1_36(M1_line24, M1_line36); xor2 M1_UM1_37(M1_line36, M1_line35, SynBits_2); xor2 M1_UM1_76(M1_NotInDataBus_3, M1_NotInDataBus_13, M1_line76); xor2 M1_UM1_77(M1_line76, M1_temp3, M1_line77); xor2 M1_UM1_78(M1_NotInDataBus_2, M1_NotInDataBus_1, M1_line78); xor2 M1_UM1_79(M1_line78, M1_NotInDataBus_0, M1_line79); xor2 M1_UM1_80(M1_NotInDataBus_15, M1_NotInDataBus_14, M1_line80); xor2 M1_UM1_81(M1_line80, M1_NotInDataBus_9, M1_line81); inv M1_UM1_82(M1_line81, M1_line82); xor2 M1_UM1_83(M1_line79, M1_line82, M1_line83); xor2 M1_UM1_84(M1_line83, M1_line27, M1_line84); inv M1_UM1_85(M1_line84, M1_line85); xor2 M1_UM1_86(M1_line77, M1_line85, SynBits_3); xor2 M1_UM1_52(M1_NotInDataBus_8, M1_NotInDataBus_13, M1_line52); xor2 M1_UM1_53(M1_line52, M1_NotInDataBus_15, M1_line53); inv M1_UM1_54(M1_line53, M1_line54); xor2 M1_UM1_55(M1_NotInDataBus_9, M1_NotInDataBus_6, M1_line55); xor2 M1_UM1_56(M1_line55, M1_NotInDataBus_3, M1_line56); inv M1_UM1_57(M1_line56, M1_line57); xor2 M1_UM1_58(M1_line54, M1_line57, M1_line58); xor2 M1_UM1_59(M1_temp4, M1_NotInDataBus_12, M1_line59); inv M1_UM1_60(M1_line59, M1_line60); xor2 M1_UM1_61(M1_line58, M1_line60, SynBits_4); xor2 M1_UM1_62(M1_line29, M1_NotInDataBus_8, M1_line62); xor2 M1_UM1_63(M1_line62, M1_temp5, M1_line63); inv M1_UM1_64(M1_line63, M1_line64); xor2 M1_UM1_65(M1_NotInDataBus_2, M1_NotInDataBus_1, M1_line65); xor2 M1_UM1_66(M1_line65, M1_NotInDataBus_0, M1_line66); inv M1_UM1_67(M1_line66, M1_line67); xor2 M1_UM1_68(M1_NotInDataBus_6, M1_NotInDataBus_5, M1_line68); xor2 M1_UM1_69(M1_line68, M1_NotInDataBus_4, M1_line69); xor2 M1_UM1_70(M1_line67, M1_line69, M1_line70); xor2 M1_UM1_71(M1_NotInDataBus_7, M1_NotInDataBus_3, M1_line71); inv M1_UM1_72(M1_line71, M1_line72); xor2 M1_UM1_73(M1_line70, M1_line72, M1_line73); xor2 M1_UM1_74(M1_line64, M1_line73, M1_line74); inv M1_UM1_75(M1_line74, SynBits_5); xor2 M1_UM1_87(M1_line67, M1_line69, M1_line87); xor2 M1_UM1_88(M1_line87, M1_line72, InDBParityLo); xor2 M1_UM1_89(M1_NotInDataBus_12, M1_NotInDataBus_11, M1_line89); xor2 M1_UM1_90(M1_line89, M1_NotInDataBus_10, M1_line90); xor2 M1_UM1_91(M1_line82, M1_line90, M1_line91); xor2 M1_UM1_92(M1_NotInDataBus_13, M1_NotInDataBus_8, M1_line92); inv M1_UM1_93(M1_line92, M1_line93); xor2 M1_UM1_94(M1_line91, M1_line93, InDBParityHi); inv M2_UM2_0(in902, M2_Not_ContE); and2 M2_UM2_1(SynBits_0, M2_Not_ContE, M2_temp0); and2 M2_UM2_2(SynBits_1, M2_Not_ContE, M2_temp1); and2 M2_UM2_3(SynBits_2, M2_Not_ContE, M2_temp2); and2 M2_UM2_4(SynBits_3, M2_Not_ContE, M2_temp3); and2 M2_UM2_5(SynBits_4, M2_Not_ContE, M2_temp4); and2 M2_UM2_6(SynBits_5, M2_Not_ContE, M2_temp5); nand2 M2_UM2_7(in234, M2_Not_ContE, M2_line7); and2 M2_UM2_8(in217, M2_line7, AllExtSynBits_4); inv M2_UM2_9(in237, M2_Not_ContH); nand2 M2_UM2_10(M2_Not_ContH, M2_Not_ContE, M2_line10); and2 M2_UM2_11(M2_line10, in210, AllExtSynBits_5); nand2 M2_UM2_12(in214, M2_line10, ContIntM); nand2 M2_UM2_13(in221, M2_line7, ContIntP); xor2 M2_UM2_14(M2_temp0, in478, NewSynBits_0); xor2 M2_UM2_15(M2_temp1, in475, NewSynBits_1); xor2 M2_UM2_16(M2_temp2, in472, NewSynBits_2); xor2 M2_UM2_17(M2_temp3, in469, NewSynBits_3); xor2 M2_UM2_18(M2_temp4, AllExtSynBits_4, NewSynBits_4); xor2 M2_UM2_19(M2_temp5, AllExtSynBits_5, NewSynBits_5); inv M2_UM2_20(NewSynBits_0, Not_NewSynBits_0); inv M2_UM2_21(NewSynBits_1, Not_NewSynBits_1); inv M2_UM2_22(NewSynBits_2, Not_NewSynBits_2); inv M2_UM2_23(NewSynBits_3, Not_NewSynBits_3); inv M2_UM2_24(NewSynBits_4, Not_NewSynBits_4); inv M2_UM2_25(NewSynBits_5, Not_NewSynBits_5); inv M3_UM3_0(in898, M3_Not_ContK); inv M3_UM3_1(in900, M3_Not_ContL); inv M3_UM3_2(in953, M3_Not_ContB); nand2 M3_UM3_3(in234, in237, M3_NotGH); nand4 M3_UM3_4(M3_Not_ContK, in902, in953, M3_NotGH, M3_line4); nand3 M3_UM3_5(in952, M3_Not_ContB, M3_NotGH, M3_line5); nand2 M3_UM3_6(M3_line4, M3_line5, M3_ContIntLo); nand4 M3_UM3_7(M3_Not_ContL, in902, in953, M3_NotGH, M3_line7); nand2 M3_UM3_8(M3_line7, M3_line5, M3_ContIntHi); and2 M3_UM3_9(ContIntM, NewSynBits_5, ProductSyn_0); and2 M3_UM3_10(Not_NewSynBits_0, Not_NewSynBits_1, ProductSyn_1); and2 M3_UM3_11(Not_NewSynBits_4, Not_NewSynBits_2, ProductSyn_2); and2 M3_UM3_12(Not_NewSynBits_0, NewSynBits_1, ProductSyn_3); and2 M3_UM3_13(NewSynBits_0, Not_NewSynBits_1, ProductSyn_4); and2 M3_UM3_14(NewSynBits_4, Not_NewSynBits_2, ProductSyn_5); and2 M3_UM3_15(ContIntP, Not_NewSynBits_3, ProductSyn_6); and2 M3_UM3_16(NewSynBits_4, NewSynBits_2, ProductSyn_7); and2 M3_UM3_17(ContIntM, Not_NewSynBits_5, ProductSyn_8); and2 M3_UM3_18(Not_NewSynBits_4, NewSynBits_2, ProductSyn_9); and2 M3_UM3_19(ContIntP, NewSynBits_3, ProductSyn_10); and2 M3_UM3_20(NewSynBits_0, NewSynBits_1, ProductSyn_11); and5 M3_UM3_21(ProductSyn_0, ProductSyn_10, ProductSyn_9, ProductSyn_1, M3_ContIntLo, DecodedSyn_0); and5 M3_UM3_22(ProductSyn_0, ProductSyn_10, ProductSyn_2, ProductSyn_3, M3_ContIntLo, DecodedSyn_1); and5 M3_UM3_23(ProductSyn_0, ProductSyn_10, ProductSyn_2, ProductSyn_4, M3_ContIntLo, DecodedSyn_2); and5 M3_UM3_24(ProductSyn_0, ProductSyn_10, ProductSyn_5, ProductSyn_1, M3_ContIntLo, DecodedSyn_3); and5 M3_UM3_25(ProductSyn_0, ProductSyn_6, ProductSyn_9, ProductSyn_3, M3_ContIntLo, DecodedSyn_4); and5 M3_UM3_26(ProductSyn_0, ProductSyn_6, ProductSyn_9, ProductSyn_4, M3_ContIntLo, DecodedSyn_5); and5 M3_UM3_27(ProductSyn_0, ProductSyn_6, ProductSyn_7, ProductSyn_1, M3_ContIntLo, DecodedSyn_6); and5 M3_UM3_28(ProductSyn_0, ProductSyn_6, ProductSyn_2, ProductSyn_11, M3_ContIntLo, DecodedSyn_7); and5 M3_UM3_29(ProductSyn_0, ProductSyn_6, ProductSyn_5, ProductSyn_3, M3_ContIntHi, DecodedSyn_8); and5 M3_UM3_30(ProductSyn_0, ProductSyn_10, ProductSyn_7, ProductSyn_4, M3_ContIntHi, DecodedSyn_9); and5 M3_UM3_31(ProductSyn_8, ProductSyn_10, ProductSyn_9, ProductSyn_3, M3_ContIntHi, DecodedSyn_10); and5 M3_UM3_32(ProductSyn_8, ProductSyn_10, ProductSyn_9, ProductSyn_4, M3_ContIntHi, DecodedSyn_11); and5 M3_UM3_33(ProductSyn_8, ProductSyn_10, ProductSyn_7, ProductSyn_1, M3_ContIntHi, DecodedSyn_12); and5 M3_UM3_34(ProductSyn_8, ProductSyn_10, ProductSyn_5, ProductSyn_3, M3_ContIntHi, DecodedSyn_13); and5 M3_UM3_35(ProductSyn_0, ProductSyn_10, ProductSyn_9, ProductSyn_11, M3_ContIntHi, DecodedSyn_14); and5 M3_UM3_36(ProductSyn_0, ProductSyn_10, ProductSyn_7, ProductSyn_3, M3_ContIntHi, DecodedSyn_15); or8 M3_UM3_37(DecodedSyn_0, DecodedSyn_1, DecodedSyn_2, DecodedSyn_3, DecodedSyn_4, DecodedSyn_5, DecodedSyn_6, DecodedSyn_7, CorrectionFlagLo); or8 M3_UM3_38(DecodedSyn_8, DecodedSyn_9, DecodedSyn_10, DecodedSyn_11, DecodedSyn_12, DecodedSyn_13, DecodedSyn_14, DecodedSyn_15, CorrectionFlagHi); or2 M3_UM3_39(CorrectionFlagLo, CorrectionFlagHi, CorrectionFlag); xor2 M4_UM4_0(in101, DecodedSyn_0, out3); xor2 M4_UM4_1(in104, DecodedSyn_1, out6); xor2 M4_UM4_2(in107, DecodedSyn_2, out9); xor2 M4_UM4_3(in110, DecodedSyn_3, out12); xor2 M4_UM4_4(in113, DecodedSyn_4, out15); xor2 M4_UM4_5(in116, DecodedSyn_5, out18); xor2 M4_UM4_6(in119, DecodedSyn_6, out21); xor2 M4_UM4_7(in122, DecodedSyn_7, out24); xor2 M4_UM4_8(in125, DecodedSyn_8, out27); xor2 M4_UM4_9(in128, DecodedSyn_9, out30); xor2 M4_UM4_10(in131, DecodedSyn_10, out33); xor2 M4_UM4_11(in134, DecodedSyn_11, out36); xor2 M4_UM4_12(in137, DecodedSyn_12, out39); xor2 M4_UM4_13(in140, DecodedSyn_13, out42); xor2 M4_UM4_14(in143, DecodedSyn_14, out45); xor2 M4_UM4_15(in146, DecodedSyn_15, out48); inv M5_UM5_0(in952, M5_Not_ContF); and3 M5_UM5_1_SCS_0(in478, in902, CorrectionFlag, M5_UM5_1_line0); xor2 M5_UM5_1_SCS_1(SynBits_0, M5_UM5_1_line0, M5_UM5_1_line1); nand2 M5_UM5_1_SCS_2(M5_Not_ContF, in953, M5_UM5_1_line2); and2 M5_UM5_1_SCS_3(M5_UM5_1_line2, M5_UM5_1_line1, out63); and3 M5_UM5_2_SCS_0(in475, in902, CorrectionFlag, M5_UM5_2_line0); xor2 M5_UM5_2_SCS_1(SynBits_1, M5_UM5_2_line0, M5_UM5_2_line1); nand2 M5_UM5_2_SCS_2(M5_Not_ContF, in953, M5_UM5_2_line2); and2 M5_UM5_2_SCS_3(M5_UM5_2_line2, M5_UM5_2_line1, out60); and3 M5_UM5_3_SCS_0(in472, in902, CorrectionFlag, M5_UM5_3_line0); xor2 M5_UM5_3_SCS_1(SynBits_2, M5_UM5_3_line0, M5_UM5_3_line1); nand2 M5_UM5_3_SCS_2(M5_Not_ContF, in953, M5_UM5_3_line2); and2 M5_UM5_3_SCS_3(M5_UM5_3_line2, M5_UM5_3_line1, out57); and3 M5_UM5_4_SCS_0(in469, in902, CorrectionFlag, M5_UM5_4_line0); xor2 M5_UM5_4_SCS_1(SynBits_3, M5_UM5_4_line0, M5_UM5_4_line1); nand2 M5_UM5_4_SCS_2(M5_Not_ContF, in953, M5_UM5_4_line2); and2 M5_UM5_4_SCS_3(M5_UM5_4_line2, M5_UM5_4_line1, out54); and3 M5_UM5_5_SCS_0(AllExtSynBits_4, in902, CorrectionFlag, M5_UM5_5_line0); xor2 M5_UM5_5_SCS_1(SynBits_4, M5_UM5_5_line0, M5_UM5_5_line1); nand2 M5_UM5_5_SCS_2(M5_Not_ContF, in953, M5_UM5_5_line2); and2 M5_UM5_5_SCS_3(M5_UM5_5_line2, M5_UM5_5_line1, out66); and3 M5_UM5_6_SCS_0(AllExtSynBits_5, in902, CorrectionFlag, M5_UM5_6_line0); xor2 M5_UM5_6_SCS_1(SynBits_5, M5_UM5_6_line0, M5_UM5_6_line1); nand2 M5_UM5_6_SCS_2(M5_Not_ContF, in953, M5_UM5_6_line2); and2 M5_UM5_6_SCS_3(M5_UM5_6_line2, M5_UM5_6_line1, out51); inv M6_UM6_7_0(in953, M6_Not_ContB); inv M6_UM6_7_1(in900, M6_Not_Cont_N); inv M6_UM6_7_2(InDBParityHi, M6_Not_InDBParity_N); nand2 M6_UM6_7_3(in953, M6_Not_Cont_N, M6_line3); and2 M6_UM6_7_4(M6_line3, M6_Not_InDBParity_N, M6_line4); and2 M6_UM6_7_5(CorrectionFlagHi, M6_Not_ContB, M6_line5); xor2 M6_UM6_7_6(M6_line5, M6_line4, M6_line6); nand2 M6_UM6_7_7(in227, in900, M6_line7); and2 M6_UM6_7_8(M6_line7, in953, M6_line8); xor2 M6_UM6_7_9(M6_line6, M6_line8, out72); inv M7_UM6_7_0(in953, M7_Not_ContB); inv M7_UM6_7_1(in898, M7_Not_Cont_N); inv M7_UM6_7_2(InDBParityLo, M7_Not_InDBParity_N); nand2 M7_UM6_7_3(in953, M7_Not_Cont_N, M7_line3); and2 M7_UM6_7_4(M7_line3, M7_Not_InDBParity_N, M7_line4); and2 M7_UM6_7_5(CorrectionFlagLo, M7_Not_ContB, M7_line5); xor2 M7_UM6_7_6(M7_line5, M7_line4, M7_line6); nand2 M7_UM6_7_7(in224, in898, M7_line7); and2 M7_UM6_7_8(M7_line7, in953, M7_line8); xor2 M7_UM6_7_9(M7_line6, M7_line8, out69); inv M8_UM8_0(in237, M8_Not_ContH); inv M8_UM8_1(in902, M8_Not_ContE); inv M8_UM8_2(in953, M8_Not_ContB); inv M8_UM8_3(in952, M8_Not_ContF); inv M8_UM8_4(ContIntM, M8_NotM); inv M8_UM8_5(ContIntP, M8_NotP); nand2 M8_UM8_6(in234, in237, M8_NotGH); and3 M8_UM8_7(in952, M8_Not_ContB, M8_NotGH, M8_ContIntUE); and2 M8_UM8_8_UEG_0(M8_NotP, Not_NewSynBits_3, M8_UM8_8_line0); and2 M8_UM8_8_UEG_1(M8_NotM, Not_NewSynBits_5, M8_UM8_8_line1); nand5 M8_UM8_8_UEG_2(ProductSyn_0, ProductSyn_6, ProductSyn_2, ProductSyn_1, M8_ContIntUE, M8_UM8_8_line2); nand5 M8_UM8_8_UEG_3(ProductSyn_8, ProductSyn_10, ProductSyn_2, ProductSyn_1, M8_ContIntUE, M8_UM8_8_line3); nand5 M8_UM8_8_UEG_4(ProductSyn_8, ProductSyn_6, ProductSyn_9, ProductSyn_1, M8_ContIntUE, M8_UM8_8_line4); nand5 M8_UM8_8_UEG_5(ProductSyn_8, ProductSyn_6, ProductSyn_2, ProductSyn_3, M8_ContIntUE, M8_UM8_8_line5); nand5 M8_UM8_8_UEG_6(ProductSyn_8, ProductSyn_6, ProductSyn_2, ProductSyn_4, M8_ContIntUE, M8_UM8_8_line6); nand5 M8_UM8_8_UEG_7(ProductSyn_8, ProductSyn_6, ProductSyn_5, ProductSyn_1, M8_ContIntUE, M8_UM8_8_line7); nand5 M8_UM8_8_UEG_8(ProductSyn_8, M8_UM8_8_line0, ProductSyn_2, ProductSyn_1, M8_ContIntUE, M8_UM8_8_line8); nand5 M8_UM8_8_UEG_9(M8_UM8_8_line1, ProductSyn_6, ProductSyn_2, ProductSyn_1, M8_ContIntUE, M8_UM8_8_line9); and8 M8_UM8_8_UEG_10(M8_UM8_8_line2, M8_UM8_8_line3, M8_UM8_8_line4, M8_UM8_8_line5, M8_UM8_8_line6, M8_UM8_8_line7, M8_UM8_8_line8, M8_UM8_8_line9, M8_UESignal); nand2 M8_UM8_9(M8_Not_ContH, M8_Not_ContE, M8_line9); nand2 M8_UM8_10(in214, M8_line9, M8_line10); nand2 M8_UM8_11(in234, M8_Not_ContE, M8_line11); nand2 M8_UM8_12(in221, M8_line11, M8_line12); nand8 M8_UM8_13(Not_NewSynBits_0, Not_NewSynBits_1, Not_NewSynBits_2, Not_NewSynBits_3, Not_NewSynBits_4, Not_NewSynBits_5, M8_line10, M8_line12, M8_ErrorFREE); inv M8_UM8_14(CorrectionFlagHi, M8_NotCorrFlagHi); inv M8_UM8_15(CorrectionFlagLo, M8_NotCorrFlagLo); and3 M8_UM8_16(M8_NotCorrFlagLo, M8_NotCorrFlagHi, M8_UESignal, M8_line16); and4 M8_UM8_17(M8_Not_ContB, M8_ErrorFREE, in952, M8_line16, M8_line17); and3 M8_UM8_18(M8_Not_ContB, M8_ErrorFREE, M8_Not_ContF, M8_line18); nor2 M8_UM8_19(M8_line18, M8_line17, out75); endmodule |
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Added c2670/c2670.css.
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2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 | <HTML> <HEAD> <BODY BGCOLOR="#ffffff"> <META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter"> <LINK REL="STYLESHEET" HREF="c2670.css"> <TITLE> c2670 Benchmark Circuit </TITLE> </HEAD> <H1> <A NAME="pgfId=5"> </A> High-Level Model of c2670</H1> <br> <P> <B>Statistics: </B>233 inputs; 140 outputs; 1193 gates <P> <B>Function: </B> 12-bit ALU and controller </P> <P> This benchmark consists of an ALU with a comparator, an equality checker, and several parity trees. The comparator has two 12-bit inputs X and Y, and computes Y>X using a carry-lookahead adder (CLA) that performs the addition !X+Y. It can be programmed to do a 4, 6, 8 or 12-bit comparison of its inputs. An interesting feature of the comparator is that it uses two identical CLAs that have identical inputs, a redundancy technique commonly used in fault-tolerant systems. The CLAs have a fairly standard structure with 3, 4 and 5-bit blocks. The carry output signal of each CLA gives the result of (Y>X). The output labeled <i>OutYgreaterX_Equal</i> (line number 231) is constant 1 if the outputs of the two CLAs are identical, as would normally be the case. If, however, the CLAs produced different results, the <i>OutYgreaterX_Equal</i> output would be <B>logic 0</B>, implying an error in the circuit. This would happen, for example, if there were manufacturing defects in one of the CLAs. </P> Module M7 <i>(EqualZ_W)</i> performs an equality check on two 17-bit buses. The <i>ParityChecker</i> module (M8) contains five 10-input parity trees, whose outputs are all ANDed. This module seems to perform a sanity check on the input buses of c2670. There are also several small pieces of logic which are mostly random. </P> <br> <br> <A HREF="#pgfId=1006502"> <B>Inputs/Outputs vs. Netlist Numbers</B></A> <HR> <B><P>Models:</B></P> <UL> <LI>I. Original ISCAS gate-level netlist <UL> <LI><A HREF="c2670.isc">in ISCAS-89 format</A> </LI> <LI><A HREF="c2670gate.v">in Verilog</A></LI> </UL> </LI> <LI>II. <A HREF="c2670high.v">Verilog hierarchical netlist</A> (functionally equivalent to I) </LI> <LI>III. <A HREF="flat2670.v">Verilog flat netlist </A> (flat version of II; functionally equivalent to I, but with minor structural differences) </LI> </UL> <HR> <DIV> <MAP NAME="c2670"> </MAP> <IMG SRC="c2670-1.gif" USEMAP="#c2670"> </DIV> <br> <DIV> <IMG SRC="c2670-2.gif" USEMAP="#c2670"> </DIV> <P CLASS="Body"> <A NAME="pgfId=1006502"> </A> <B>* Netlist numbers for input buses A[9:0] and B[9:0]: </B></P> <TABLE BORDER="1" CELLPADDING=3> <TR> <TH ROWSPAN="1" COLSPAN="2"> <P CLASS="CellHeading"> <A NAME="pgfId=1004628"> </A> Input bus</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1004632"> </A> 0[lo]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1004634"> </A> 1</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1004636"> </A> 2</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1004638"> </A> 3</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1004640"> </A> 4</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1004642"> </A> 5</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1004644"> </A> 6</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1004646"> </A> 7</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1004648"> </A> 8</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1004650"> </A> 9 [h]</P> </TH> </TR> <TR> <TH ROWSPAN="4" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1004676"> </A> A</P> </TH> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004678"> </A> A1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004680"> </A> 81</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004682"> </A> 92</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004684"> </A> 91</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004686"> </A> 90</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004688"> </A> 89</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004690"> </A> 88</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004692"> </A> 87</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004694"> </A> 86</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004696"> </A> 85</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004698"> </A> 93</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004702"> </A> A2</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004704"> </A> 43</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004706"> </A> 54</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004708"> </A> 53</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004710"> </A> 52</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004712"> </A> 51</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004714"> </A> 50</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004716"> </A> 49</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004718"> </A> 48</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004720"> </A> 47</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004722"> </A> 55</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004726"> </A> A3</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004728"> </A> 56</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004730"> </A> 66</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004732"> </A> 65</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004734"> </A> 64</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004736"> </A> 63</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004738"> </A> 62</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004740"> </A> logc1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004742"> </A> 61</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004744"> </A> 60</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004746"> </A> 67</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004750"> </A> A4</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004752"> </A> 68</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004754"> </A> 79</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004756"> </A> 78</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004758"> </A> 77</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004760"> </A> 76</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004762"> </A> 75</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004764"> </A> 74</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004766"> </A> 73</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004768"> </A> 72</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004770"> </A> 80</P> </TD> </TR> <TR> <TH ROWSPAN="4" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004796"> </A> B</P> </TH> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004798"> </A> B1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004800"> </A> 131</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004802"> </A> 141</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004804"> </A> 140</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004806"> </A> 139</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004808"> </A> 138</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004810"> </A> 137</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004812"> </A> 136</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004814"> </A> 135</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004816"> </A> 142</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004818"> </A> <B>logic1</B></P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004822"> </A> B2</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004824"> </A> 95</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004826"> </A> 105</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004828"> </A> 104</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004830"> </A> 103</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004832"> </A> 102</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004834"> </A> 101</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004836"> </A> 100</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004838"> </A> 99</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004840"> </A> 106</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004842"> </A> <B>logic1</B></P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004846"> </A> B3</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004848"> </A> 119</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004850"> </A> 129</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004852"> </A> 128</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004854"> </A> 127</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004856"> </A> 126</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004858"> </A> 125</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004860"> </A> 124</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004862"> </A> 123</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004864"> </A> 130</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004866"> </A> <B>logic1</B></P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004870"> </A> B4</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004872"> </A> 107</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004874"> </A> 117</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004876"> </A> 116</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004878"> </A> 115</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004880"> </A> 114</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004882"> </A> 113</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004884"> </A> 112</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004886"> </A> 111</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004888"> </A> 118</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1004890"> </A> <B>logic1</B></P> </TD> </TR> </TABLE> <P CLASS="Body"> <A NAME="pgfId=1003687"> </A> <B>* Input buses Y1[5:0], Y2[5:0], Y3[3:0]:</B></P> <TABLE BORDER="1" CELLPADDING=3> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005513"> </A> </P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005515"> </A> 0 [lo]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005517"> </A> 1</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005519"> </A> 2</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005521"> </A> 3</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005523"> </A> 4</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005525"> </A> 5 [h]</P> </TH> </TR> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005527"> </A> <B>Y1</B></P> </TH> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005529"> </A> 1341</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005531"> </A> 1348</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005533"> </A> 1956</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005535"> </A> 1961</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005537"> </A> 1966</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005539"> </A> 1971</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005541"> </A> <B>Y2</B></P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005543"> </A> 1996</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005545"> </A> 2067</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005547"> </A> 2072</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005549"> </A> 2078</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005551"> </A> 2084</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005553"> </A> 2090</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005555"> </A> <B>Y3</B></P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005557"> </A> 1976</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005559"> </A> 1981</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005561"> </A> 1986</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005563"> </A> 1991</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005565"> </A> -</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005567"> </A> -</P> </TD> </TR> </TABLE> <P CLASS="Body"> <A NAME="pgfId=1008874"> </A> <B>* Inputs X[11:0] and Y[11:0] of CompareXY (M4):</B></P> <TABLE BORDER="1" CELLPADDING=2> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1004998"> </A> </P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005000"> </A> 0[lo]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005002"> </A> 1</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005004"> </A> 2</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005006"> </A> 3</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005008"> </A> 4</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005010"> </A> 5</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005012"> </A> 6</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005014"> </A> 7</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005016"> </A> 8</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005018"> </A> 9</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005020"> </A> 10</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1005022"> </A> 11[h]</P> </TH> </TR> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005024"> </A> X</P> </TH> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005026"> </A> A[0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005028"> </A> A[1]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005030"> </A> A[2]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005032"> </A> A[3]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005034"> </A> A[4]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005036"> </A> A[5]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005038"> </A> A[6]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005040"> </A> A[7]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005042"> </A> A[8]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005044"> </A> B[0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005046"> </A> B[1]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005048"> </A> B[2]</P> </TD> </TR> <TR> <TH ROWSPAN="2" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005050"> </A> Y</P> </TH> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005052"> </A> Y1[0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005102"> </A> Y1[1]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005106"> </A> Y1[2]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005058"> </A> Y1[3]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005060"> </A> Y1[4]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005062"> </A> Y1[5]</P> </TD> <TD ROWSPAN="2" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005064"> </A> Y3[0]</P> </TD> <TD ROWSPAN="2" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005066"> </A> Y3[1]</P> </TD> <TD ROWSPAN="2" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005068"> </A> Y3[2]</P> </TD> <TD ROWSPAN="2" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005070"> </A> Y3[3]</P> </TD> <TD ROWSPAN="2" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005072"> </A> Y2[0]</P> </TD> <TD ROWSPAN="2" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005074"> </A> Y2[1]</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005078"> </A> Y2[0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005080"> </A> Y2[1]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005082"> </A> Y2[2]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005084"> </A> Y2[3]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005086"> </A> Y2[4]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1005088"> </A> Y2[5]</P> </TD> </TR> </TABLE> <P CLASS="Body"> <A NAME="pgfId=1001390"> </A> <B>* Inputs W[16:0] and Z[16:0] of Bitwise Comparator (M7):</B> </P> <TABLE BORDER="1"> <TR> <TH ROWSPAN="1" COLSPAN="2"> <P CLASS="CellHeading"> <A NAME="pgfId=1006325"> </A> </P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006329"> </A> 0[lo]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006331"> </A> 1</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006333"> </A> 2</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006335"> </A> 3</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006337"> </A> 4</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006339"> </A> 5</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006341"> </A> 6</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006343"> </A> 7</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006345"> </A> 8</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006347"> </A> 9</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006349"> </A> 10</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006351"> </A> 11</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006353"> </A> 12</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006355"> </A> 13</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006357"> </A> 14</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006359"> </A> 15</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1006361"> </A> 16[hi]</P> </TH> </TR> <TR> <TH ROWSPAN="2" COLSPAN="2"> <P CLASS="CellBody"> <A NAME="pgfId=1006363"> </A> Z</P> </TH> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006367"> </A> A[0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006369"> </A> A[1]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006371"> </A> A[2]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006373"> </A> A[3]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006375"> </A> A[4]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006377"> </A> A[5]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006379"> </A> A[6]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006381"> </A> A[7]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006383"> </A> A[8]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006385"> </A> B[0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006387"> </A> B[1]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006389"> </A> B[2]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006391"> </A> B[3]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006393"> </A> B[4]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006395"> </A> B[5]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006397"> </A> B[6]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006399"> </A> B[7]</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006405"> </A> 19</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006407"> </A> 4</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006409"> </A> 20</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006411"> </A> 5</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006413"> </A> 21</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006415"> </A> 22</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006417"> </A> 23</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006419"> </A> 6</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006421"> </A> 24</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006423"> </A> 25</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006425"> </A> 32</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006427"> </A> 26</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006429"> </A> 33</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006431"> </A> 27</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006433"> </A> 34</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006435"> </A> 35</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006437"> </A> 28</P> </TD> </TR> <TR> <TH ROWSPAN="1" COLSPAN="2"> <P CLASS="CellBody"> <A NAME="pgfId=1006439"> </A> W</P> </TH> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006443"> </A> Y1[0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006445"> </A> Y1[1]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006447"> </A> Y1[2]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006449"> </A> Y1[3]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006451"> </A> Y1[4]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006453"> </A> Y1[5]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006455"> </A> Y3[0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006457"> </A> Y3[1]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006459"> </A> Y3[2]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006461"> </A> Y3[3]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006463"> </A> Y2[0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006465"> </A> Y2[1]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006467"> </A> Y2[2]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006469"> </A> Y2[3]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006471"> </A> Y2[4]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006473"> </A> Y2[5]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1006475"> </A> <B>logic0</B></P> </TD> </TR> </TABLE> <P CLASS="Body"> <A NAME="pgfId=1009263"> </A> <B>* Q[9:0], R[9:0], S[9:0] (inputs to ParityChecker M8) are three 10-bit buses multiplexed out of Y1, Y2, Y3 and ParTreeIns:</B> </P> <TABLE BORDER="1" CELLPADDING=2> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1009266"> </A> </P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1009268"> </A> 0 [lo]</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1009270"> </A> 1</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1009272"> </A> 2</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1009274"> </A> 3</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1009276"> </A> 4</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1009278"> </A> 5</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1009280"> </A> 6</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1009282"> </A> 7</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1009284"> </A> 8</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1009286"> </A> 9 [hi]</P> </TH> </TR> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009288"> </A> Q</P> </TH> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009290"> </A> Y1[2]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009292"> </A> Y1[3]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009294"> </A> Y1[4]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009296"> </A> Y1[5]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009298"> </A> Y3[0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009300"> </A> Y3[1]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009302"> </A> Y3[2]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009304"> </A> Y3[3]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009306"> </A> Y2[0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009308"> </A> 2474 </P> </TD> </TR> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009310"> </A> R</P> </TH> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009312"> </A> Y1[0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009314"> </A> Y1[1]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009316"> </A> 2427 </P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009318"> </A> 2430 </P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009320"> </A> 2451 </P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009322"> </A> 2454 </P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009324"> </A> 2443 </P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009326"> </A> 2446 </P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009328"> </A> 2435 </P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009330"> </A> 2438 </P> </TD> </TR> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009332"> </A> S</P> </TH> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009334"> </A> Y2[2]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009336"> </A> Y2[3]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009338"> </A> Y2[4]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009340"> </A> Y2[5]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009342"> </A> Y2[1]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009344"> </A> 2096</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009346"> </A> 2100</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009348"> </A> 2678</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009350"> </A> <B>logic0</B></P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009352"> </A> <B>logic0</B></P> </TD> </TR> </TABLE> <P CLASS="Body"> <A NAME="pgfId=1009412"> </A> <B>* Netlist numbers for the remaining inputs:</B></P> <TABLE BORDER="1"> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009356"> </A> Inputs</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009358"> </A> Netlist numbers</P> </TH> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009360"> </A> ContA0, ContA1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009362"> </A> 651, 543</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009364"> </A> ContB0, ContB1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009366"> </A> 2105, 2104</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009368"> </A> ContZ0. ContZ1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009370"> </A> 16, 29</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009372"> </A> ContEq</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009374"> </A> 11</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009376"> </A> ContMask0,1,2</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009378"> </A> 8, 1384, 40</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009380"> </A> ContAlpha</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009382"> </A> !B[5]. ContMask2. B[4]. !ContMask1</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009384"> </A> ContBeta</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009386"> </A> !B[5]. ContMask2. (!B[4] + ContMask1)</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009388"> </A> ContPar0,1,2,3</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009390"> </A> 14, 37, 2106, 567</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009392"> </A> ParTreeIns[11:0]</P> <P CLASS="CellBody"> <A NAME="pgfId=1009393"> </A> (fanin of Q,R,S)</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009395"> </A> 2096, 2100, 2678, 2454, 2451, 2446, 2443, 2438, 2435, 2430, 2427, 2474</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009397"> </A> InTbus[7:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009399"> </A> 108, 57, 120, 69, 96, 82, 132, 44</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009401"> </A> MiscRandomIns[11:0] </P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009403"> </A> 3, 1, 483, 36, 15, 2, 661, 7, 94, 1083, 2066, 452</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009405"> </A> MiscMuxIn</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009407"> </A> 559</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009409"> </A> MiscMuxCont0,1</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009411"> </A> 868, 860</P> </TD> </TR> </TABLE> <P CLASS="Body"> <A NAME="pgfId=1008885"> </A> <B>* Netlist numbers for outputs:</B> </P> <TABLE BORDER="1"> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009163"> </A> Outputs</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009165"> </A> Netlist numbers</P> </TH> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009167"> </A> OutYgreaterX <FONT SIZE=2>(Y>X)</FONT></P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009169"> </A> 329</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009171"> </A> OutYgreaterX_Equal</P> <P CLASS="CellBody"> <A NAME="pgfId=1009256"> </A> <FONT SIZE=2> (Y>X)#1 == (Y>X)#2</FONT></P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009173"> </A> 231</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009175"> </A> OutZequalW <FONT SIZE=2>(Z==W)</FONT></P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009177"> </A> 150</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009450"> </A> OutNot_ZequalW <FONT SIZE=2>(Z != W)</FONT></P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009435"> </A> 311</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009179"> </A> OutParCheck</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009181"> </A> 308</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009437"> </A> OutNot_ParCheck</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009439"> </A> 225</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009183"> </A> ParChkOuts[7:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009185"> </A> 261, 325, 319, 401, 229, 227, 397, 395</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009187"> </A> OutTbus[7:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009545"> </A> 238, 237, 236, 235, 221, 220, 219, 218</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009191"> </A> MiscMuxOuts[10:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009193"> </A> 280, 321, 323, 331, 153, 148, 145, 297, 284, 282, 295</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009195"> </A> MiscBusOuts[12:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009197"> </A> 164, 160, 162, 171, 168, 166, 299, 301, 286, 303, 288, 305, 290</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009200"> </A> MiscRandomOuts[17:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009202"> </A> 158, 188, 176, 259, 234, 217, 223, 156, 173, 369, 367, 411, 384, 337, 409, 391, 350, 335</P> </TD> </TR> </TABLE> </A> <br> <P> <A HREF="#pgfId=5"> Go to top of this file</A></P> <P> <A HREF="../benchmark.html"> Go back to the Benchmark List</A></P> </BODY> </HTML> |
Added c2670/c2670.isc.
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732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 | # combinational logic example "c2670" #------------------------------------------------------------- # # # total number of lines in the netlist .............. 2670 # simplistically reduced equivalent fault set size = 2747 # lines from primary input gates ....... 233 # lines from primary output gates ....... 140 # lines from interior gate outputs ...... 1129 # lines from ** 454 ** fanout stems ... 1244 # # avg_fanin = 1.64, max_fanin = 5 # avg_fanout = 2.74, max_fanout = 11 # # # # # INPUT(1) #... primary input INPUT(2) #... primary input INPUT(3) #... primary input INPUT(4) #... primary input INPUT(5) #... primary input INPUT(6) #... primary input INPUT(7) #... primary input INPUT(8) #... primary input INPUT(11) #... primary input INPUT(14) #... primary input INPUT(15) #... primary input INPUT(16) #... primary input INPUT(19) #... primary input INPUT(20) #... primary input INPUT(21) #... primary input INPUT(22) #... primary input INPUT(23) #... primary input INPUT(24) #... primary input INPUT(25) #... primary input INPUT(26) #... primary input INPUT(27) #... primary input INPUT(28) #... primary input INPUT(29) #... primary input INPUT(32) #... primary input INPUT(33) #... primary input INPUT(34) #... primary input INPUT(35) #... primary input INPUT(36) #... primary input INPUT(37) #... primary input INPUT(40) #... primary input INPUT(43) #... primary input INPUT(44) #... primary input INPUT(47) #... primary input INPUT(48) #... primary input INPUT(49) #... primary input INPUT(50) #... primary input INPUT(51) #... primary input INPUT(52) #... primary input INPUT(53) #... primary input INPUT(54) #... primary input INPUT(55) #... primary input INPUT(56) #... primary input INPUT(57) #... primary input INPUT(60) #... primary input INPUT(61) #... primary input INPUT(62) #... primary input INPUT(63) #... primary input INPUT(64) #... primary input INPUT(65) #... primary input INPUT(66) #... primary input INPUT(67) #... primary input INPUT(68) #... primary input INPUT(69) #... primary input INPUT(72) #... primary input INPUT(73) #... primary input INPUT(74) #... primary input INPUT(75) #... primary input INPUT(76) #... primary input INPUT(77) #... primary input INPUT(78) #... primary input INPUT(79) #... primary input INPUT(80) #... primary input INPUT(81) #... primary input INPUT(82) #... primary input INPUT(85) #... primary input INPUT(86) #... primary input INPUT(87) #... primary input INPUT(88) #... primary input INPUT(89) #... primary input INPUT(90) #... primary input INPUT(91) #... primary input INPUT(92) #... primary input INPUT(93) #... primary input INPUT(94) #... primary input INPUT(95) #... primary input INPUT(96) #... primary input INPUT(99) #... primary input INPUT(100) #... primary input INPUT(101) #... primary input INPUT(102) #... primary input INPUT(103) #... primary input INPUT(104) #... primary input INPUT(105) #... primary input INPUT(106) #... primary input INPUT(107) #... primary input INPUT(108) #... primary input INPUT(111) #... primary input INPUT(112) #... primary input INPUT(113) #... primary input INPUT(114) #... primary input INPUT(115) #... primary input INPUT(116) #... primary input INPUT(117) #... primary input INPUT(118) #... primary input INPUT(119) #... primary input INPUT(120) #... primary input INPUT(123) #... primary input INPUT(124) #... primary input INPUT(125) #... primary input INPUT(126) #... primary input INPUT(127) #... primary input INPUT(128) #... primary input INPUT(129) #... primary input INPUT(130) #... primary input INPUT(131) #... primary input INPUT(132) #... primary input INPUT(135) #... primary input INPUT(136) #... primary input INPUT(137) #... primary input INPUT(138) #... primary input INPUT(139) #... primary input INPUT(140) #... primary input INPUT(141) #... primary input INPUT(142) #... primary input INPUT(169) #... primary input INPUT(174) #... primary input INPUT(177) #... primary input INPUT(178) #... primary input INPUT(179) #... primary input INPUT(180) #... primary input INPUT(181) #... primary input INPUT(182) #... primary input INPUT(183) #... primary input INPUT(184) #... primary input INPUT(185) #... primary input INPUT(186) #... primary input INPUT(189) #... primary input INPUT(190) #... primary input INPUT(191) #... primary input INPUT(192) #... primary input INPUT(193) #... primary input INPUT(194) #... primary input INPUT(195) #... primary input INPUT(196) #... primary input INPUT(197) #... primary input INPUT(198) #... primary input INPUT(199) #... primary input INPUT(200) #... primary input INPUT(201) #... primary input INPUT(202) #... primary input INPUT(203) #... primary input INPUT(204) #... primary input INPUT(205) #... primary input INPUT(206) #... primary input INPUT(207) #... primary input INPUT(208) #... primary input INPUT(209) #... primary input INPUT(210) #... primary input INPUT(211) #... primary input INPUT(212) #... primary input INPUT(213) #... primary input INPUT(214) #... primary input INPUT(215) #... primary input INPUT(239) #... primary input INPUT(240) #... primary input INPUT(241) #... primary input INPUT(242) #... primary input INPUT(243) #... primary input INPUT(244) #... primary input INPUT(245) #... primary input INPUT(246) #... primary input INPUT(247) #... primary input INPUT(248) #... primary input INPUT(249) #... primary input INPUT(250) #... primary input INPUT(251) #... primary input INPUT(252) #... primary input INPUT(253) #... primary input INPUT(254) #... primary input INPUT(255) #... primary input INPUT(256) #... primary input INPUT(257) #... primary input INPUT(262) #... primary input INPUT(263) #... primary input INPUT(264) #... primary input INPUT(265) #... primary input INPUT(266) #... primary input INPUT(267) #... primary input INPUT(268) #... primary input INPUT(269) #... primary input INPUT(270) #... primary input INPUT(271) #... primary input INPUT(272) #... primary input INPUT(273) #... primary input INPUT(274) #... primary input INPUT(275) #... primary input INPUT(276) #... primary input INPUT(277) #... primary input INPUT(278) #... primary input INPUT(279) #... primary input INPUT(452) #... primary input INPUT(483) #... primary input INPUT(543) #... primary input INPUT(559) #... primary input INPUT(567) #... primary input INPUT(651) #... primary input INPUT(661) #... primary input INPUT(860) #... primary input INPUT(868) #... primary input INPUT(1083) #... primary input INPUT(1341) #... primary input INPUT(1348) #... primary input INPUT(1384) #... primary input INPUT(1956) #... primary input INPUT(1961) #... primary input INPUT(1966) #... primary input INPUT(1971) #... primary input INPUT(1976) #... primary input INPUT(1981) #... primary input INPUT(1986) #... primary input INPUT(1991) #... primary input INPUT(1996) #... primary input INPUT(2066) #... primary input INPUT(2067) #... primary input INPUT(2072) #... primary input INPUT(2078) #... primary input INPUT(2084) #... primary input INPUT(2090) #... primary input INPUT(2096) #... primary input INPUT(2100) #... primary input INPUT(2104) #... primary input INPUT(2105) #... primary input INPUT(2106) #... primary input INPUT(2427) #... primary input INPUT(2430) #... primary input INPUT(2435) #... primary input INPUT(2438) #... primary input INPUT(2443) #... primary input INPUT(2446) #... primary input INPUT(2451) #... primary input INPUT(2454) #... primary input INPUT(2474) #... primary input INPUT(2678) #... primary input # # OUTPUT(169) #... primary output OUTPUT(174) #... primary output OUTPUT(177) #... primary output OUTPUT(178) #... primary output OUTPUT(179) #... primary output OUTPUT(180) #... primary output OUTPUT(181) #... primary output OUTPUT(182) #... primary output OUTPUT(183) #... primary output OUTPUT(184) #... primary output OUTPUT(185) #... primary output OUTPUT(186) #... primary output OUTPUT(189) #... primary output OUTPUT(190) #... primary output OUTPUT(191) #... primary output OUTPUT(192) #... primary output OUTPUT(193) #... primary output OUTPUT(194) #... primary output OUTPUT(195) #... primary output OUTPUT(196) #... primary output OUTPUT(197) #... primary output OUTPUT(198) #... primary output OUTPUT(199) #... primary output OUTPUT(200) #... primary output OUTPUT(201) #... primary output OUTPUT(202) #... primary output OUTPUT(203) #... primary output OUTPUT(204) #... primary output OUTPUT(205) #... primary output OUTPUT(206) #... primary output OUTPUT(207) #... primary output OUTPUT(208) #... primary output OUTPUT(209) #... primary output OUTPUT(210) #... primary output OUTPUT(211) #... primary output OUTPUT(212) #... primary output OUTPUT(213) #... primary output OUTPUT(214) #... primary output OUTPUT(215) #... primary output OUTPUT(239) #... primary output OUTPUT(240) #... primary output OUTPUT(241) #... primary output OUTPUT(242) #... primary output OUTPUT(243) #... primary output OUTPUT(244) #... primary output OUTPUT(245) #... primary output OUTPUT(246) #... primary output OUTPUT(247) #... primary output OUTPUT(248) #... primary output OUTPUT(249) #... primary output OUTPUT(250) #... primary output OUTPUT(251) #... primary output OUTPUT(252) #... primary output OUTPUT(253) #... primary output OUTPUT(254) #... primary output OUTPUT(255) #... primary output OUTPUT(256) #... primary output OUTPUT(257) #... primary output OUTPUT(262) #... primary output OUTPUT(263) #... primary output OUTPUT(264) #... primary output OUTPUT(265) #... primary output OUTPUT(266) #... primary output OUTPUT(267) #... primary output OUTPUT(268) #... primary output OUTPUT(269) #... primary output OUTPUT(270) #... primary output OUTPUT(271) #... primary output OUTPUT(272) #... primary output OUTPUT(273) #... primary output OUTPUT(274) #... primary output OUTPUT(275) #... primary output OUTPUT(276) #... primary output OUTPUT(277) #... primary output OUTPUT(278) #... primary output OUTPUT(279) #... primary output OUTPUT(350) #... primary output OUTPUT(335) #... primary output OUTPUT(409) #... primary output OUTPUT(369) #... primary output OUTPUT(367) #... primary output OUTPUT(411) #... primary output OUTPUT(337) #... primary output OUTPUT(384) #... primary output OUTPUT(218) #... primary output OUTPUT(219) #... primary output OUTPUT(220) #... primary output OUTPUT(221) #... primary output OUTPUT(235) #... primary output OUTPUT(236) #... primary output OUTPUT(237) #... primary output OUTPUT(238) #... primary output OUTPUT(158) #... primary output OUTPUT(259) #... primary output OUTPUT(391) #... primary output OUTPUT(173) #... primary output OUTPUT(223) #... primary output OUTPUT(234) #... primary output OUTPUT(217) #... primary output OUTPUT(325) #... primary output OUTPUT(261) #... primary output OUTPUT(319) #... primary output OUTPUT(160) #... primary output OUTPUT(162) #... primary output OUTPUT(164) #... primary output OUTPUT(166) #... primary output OUTPUT(168) #... primary output OUTPUT(171) #... primary output OUTPUT(153) #... primary output OUTPUT(176) #... primary output OUTPUT(188) #... primary output OUTPUT(299) #... primary output OUTPUT(301) #... primary output OUTPUT(286) #... primary output OUTPUT(303) #... primary output OUTPUT(288) #... primary output OUTPUT(305) #... primary output OUTPUT(290) #... primary output OUTPUT(284) #... primary output OUTPUT(321) #... primary output OUTPUT(297) #... primary output OUTPUT(280) #... primary output OUTPUT(148) #... primary output OUTPUT(282) #... primary output OUTPUT(323) #... primary output OUTPUT(156) #... primary output OUTPUT(401) #... primary output OUTPUT(227) #... primary output OUTPUT(229) #... primary output OUTPUT(311) #... primary output OUTPUT(150) #... primary output OUTPUT(145) #... primary output OUTPUT(395) #... primary output OUTPUT(295) #... primary output OUTPUT(331) #... primary output OUTPUT(397) #... primary output OUTPUT(329) #... primary output OUTPUT(231) #... primary output OUTPUT(308) #... primary output OUTPUT(225) #... primary output # # # Output Type Inputs... # ------ ---- --------- 350 = buff( 452) 335 = buff( 452) 409 = buff( 452) 546 = and( 1, 3) 560 = not( 559) 369 = buff( 1083) 367 = buff( 1083) 1385 = not( 1384) 411 = buff( 2066) 337 = buff( 2066) 384 = buff( 2066) 157 = and( 2090, 2084, 2078, 2072) 547 = not( 546) 218 = not( 44) 219 = not( 132) 220 = not( 82) 221 = not( 96) 235 = not( 69) 236 = not( 120) 237 = not( 57) 238 = not( 108) 258 = and( 2, 15, 661) 480 = buff( 661) 486 = and( 37, 37) 654 = buff( 452) 655 = buff( 8) 658 = buff( 8) 772 = buff( 543) 795 = buff( 651) 865 = not( 860) 875 = not( 868) 882 = and( 11, 868) 1251 = and( 132, 82, 96, 44) 1254 = and( 120, 57, 108, 69) 1261 = buff( 543) 1284 = buff( 651) 1344 = not( 1341) 1351 = not( 1348) 1394 = buff( 2104) 1418 = buff( 2105) 2433 = not( 2427) 2434 = not( 2430) 2441 = not( 2435) 2442 = not( 2438) 2449 = not( 2443) 2450 = not( 2446) 2478 = not( 2474) 1631 = buff( 2104) 1655 = buff( 2105) 1710 = buff( 16) 1721 = buff( 16) 2682 = not( 2678) 1955 = and( 7, 661) 1959 = not( 1956) 1964 = not( 1961) 1969 = not( 1966) 1974 = not( 1971) 1979 = not( 1976) 1984 = not( 1981) 1989 = not( 1986) 1994 = not( 1991) 1999 = not( 1996) 2001 = buff( 29) 2012 = buff( 29) 2070 = not( 2067) 2076 = not( 2072) 2082 = not( 2078) 2088 = not( 2084) 2094 = not( 2090) 2099 = not( 2096) 2103 = not( 2100) 2457 = not( 2451) 2458 = not( 2454) 2461 = buff( 1348) 2464 = buff( 1341) 2471 = buff( 1956) 2479 = buff( 1966) 2482 = buff( 1961) 2487 = buff( 1976) 2490 = buff( 1971) 2495 = buff( 1986) 2498 = buff( 1981) 2505 = buff( 1996) 2508 = buff( 1991) 2675 = buff( 2067) 2683 = buff( 2078) 2686 = buff( 2072) 2691 = buff( 2090) 2694 = buff( 2084) 2699 = buff( 2100) 2702 = buff( 2096) 158 = not( 157) 259 = not( 258) 487 = not( 486) 391 = buff( 654) 1475 = nand( 2430, 2433) 1476 = nand( 2427, 2434) 1484 = nand( 2438, 2441) 1485 = nand( 2435, 2442) 1493 = nand( 2446, 2449) 1494 = nand( 2443, 2450) 2459 = nand( 2454, 2457) 2460 = nand( 2451, 2458) 173 = and( 94, 654) 216 = and( 2106, 1955) 223 = not( 1955) 234 = nand( 567, 1955) 1253 = not( 1251) 1256 = not( 1254) 558 = and( 1254, 1251) 748 = buff( 655) 784 = not( 772) 807 = not( 795) 821 = and( 80, 772, 795) 825 = and( 68, 772, 795) 829 = and( 79, 772, 795) 833 = and( 78, 772, 795) 837 = and( 77, 772, 795) 881 = and( 11, 875) 994 = buff( 655) 1273 = not( 1261) 1296 = not( 1284) 1310 = and( 76, 1261, 1284) 1314 = and( 75, 1261, 1284) 1318 = and( 74, 1261, 1284) 1322 = and( 73, 1261, 1284) 1326 = and( 72, 1261, 1284) 1406 = not( 1394) 1430 = not( 1418) 1444 = and( 114, 1394, 1418) 1448 = and( 113, 1394, 1418) 1452 = and( 112, 1394, 1418) 1456 = and( 111, 1394, 1418) 1460 = and( 1394, 1418) 1477 = nand( 1475, 1476) 1486 = nand( 1484, 1485) 1495 = nand( 1493, 1494) 2477 = not( 2471) 1499 = nand( 2471, 2478) 2485 = not( 2479) 2486 = not( 2482) 2493 = not( 2487) 2494 = not( 2490) 1643 = not( 1631) 1667 = not( 1655) 1681 = and( 118, 1631, 1655) 1685 = and( 107, 1631, 1655) 1689 = and( 117, 1631, 1655) 1693 = and( 116, 1631, 1655) 1697 = and( 115, 1631, 1655) 1716 = not( 1710) 1728 = not( 1721) 2681 = not( 2675) 1776 = nand( 2675, 2682) 2689 = not( 2683) 2690 = not( 2686) 2697 = not( 2691) 2698 = not( 2694) 1831 = buff( 658) 1893 = buff( 658) 2007 = not( 2001) 2018 = not( 2012) 2467 = not( 2461) 2468 = not( 2464) 2501 = not( 2495) 2502 = not( 2498) 2511 = not( 2505) 2512 = not( 2508) 2518 = nand( 2459, 2460) 2551 = buff( 1344) 2559 = buff( 1351) 2567 = buff( 1959) 2575 = buff( 1964) 2583 = buff( 1969) 2591 = buff( 1974) 2599 = buff( 1979) 2607 = buff( 1984) 2615 = buff( 1989) 2623 = buff( 1994) 2705 = not( 2699) 2706 = not( 2702) 2735 = buff( 1999) 2743 = buff( 2070) 2751 = buff( 2076) 2759 = buff( 2082) 2767 = buff( 2088) 2775 = buff( 2094) 217 = not( 216) 550 = and( 2106, 1253) 552 = and( 567, 1256) 325 = buff( 558) 894 = or( 881, 882) 1498 = nand( 2474, 2477) 1507 = nand( 2482, 2485) 1508 = nand( 2479, 2486) 1516 = nand( 2490, 2493) 1517 = nand( 2487, 2494) 1775 = nand( 2678, 2681) 1784 = nand( 2686, 2689) 1785 = nand( 2683, 2690) 1793 = nand( 2694, 2697) 1794 = nand( 2691, 2698) 2469 = nand( 2464, 2467) 2470 = nand( 2461, 2468) 2503 = nand( 2498, 2501) 2504 = nand( 2495, 2502) 2513 = nand( 2508, 2511) 2514 = nand( 2505, 2512) 2707 = nand( 2702, 2705) 2708 = nand( 2699, 2706) 261 = not( 558) 551 = not( 550) 553 = not( 552) 818 = and( 93, 784, 807) 819 = and( 55, 772, 807) 820 = and( 67, 784, 795) 822 = and( 81, 784, 807) 823 = and( 43, 772, 807) 824 = and( 56, 784, 795) 826 = and( 92, 784, 807) 827 = and( 54, 772, 807) 828 = and( 66, 784, 795) 830 = and( 91, 784, 807) 831 = and( 53, 772, 807) 832 = and( 65, 784, 795) 834 = and( 90, 784, 807) 835 = and( 52, 772, 807) 836 = and( 64, 784, 795) 1307 = and( 89, 1273, 1296) 1308 = and( 51, 1261, 1296) 1309 = and( 63, 1273, 1284) 1311 = and( 88, 1273, 1296) 1312 = and( 50, 1261, 1296) 1313 = and( 62, 1273, 1284) 1315 = and( 87, 1273, 1296) 1316 = and( 49, 1261, 1296) 1317 = and( 1273, 1284) 1319 = and( 86, 1273, 1296) 1320 = and( 48, 1261, 1296) 1321 = and( 61, 1273, 1284) 1323 = and( 85, 1273, 1296) 1324 = and( 47, 1261, 1296) 1325 = and( 60, 1273, 1284) 1441 = and( 138, 1406, 1430) 1442 = and( 102, 1394, 1430) 1443 = and( 126, 1406, 1418) 1445 = and( 137, 1406, 1430) 1446 = and( 101, 1394, 1430) 1447 = and( 125, 1406, 1418) 1449 = and( 136, 1406, 1430) 1450 = and( 100, 1394, 1430) 1451 = and( 124, 1406, 1418) 1453 = and( 135, 1406, 1430) 1454 = and( 99, 1394, 1430) 1455 = and( 123, 1406, 1418) 1457 = and( 1406, 1430) 1458 = and( 1394, 1430) 1459 = and( 1406, 1418) 1481 = not( 1477) 1490 = not( 1486) 1500 = nand( 1498, 1499) 1509 = nand( 1507, 1508) 1518 = nand( 1516, 1517) 1521 = buff( 1495) 1525 = buff( 1495) 2557 = not( 2551) 2565 = not( 2559) 2573 = not( 2567) 2581 = not( 2575) 2589 = not( 2583) 2597 = not( 2591) 2605 = not( 2599) 2613 = not( 2607) 2621 = not( 2615) 2629 = not( 2623) 1678 = and( 142, 1643, 1667) 1679 = and( 106, 1631, 1667) 1680 = and( 130, 1643, 1655) 1682 = and( 131, 1643, 1667) 1683 = and( 95, 1631, 1667) 1684 = and( 119, 1643, 1655) 1686 = and( 141, 1643, 1667) 1687 = and( 105, 1631, 1667) 1688 = and( 129, 1643, 1655) 1690 = and( 140, 1643, 1667) 1691 = and( 104, 1631, 1667) 1692 = and( 128, 1643, 1655) 1694 = and( 139, 1643, 1667) 1695 = and( 103, 1631, 1667) 1696 = and( 127, 1643, 1655) 1734 = and( 19, 1716) 1736 = and( 4, 1716) 1738 = and( 20, 1716) 1740 = and( 5, 1716) 1742 = and( 21, 1728) 1744 = and( 22, 1728) 1746 = and( 23, 1728) 1748 = and( 6, 1728) 1750 = and( 24, 1728) 1777 = nand( 1775, 1776) 1786 = nand( 1784, 1785) 1795 = nand( 1793, 1794) 2023 = and( 25, 2007) 2025 = and( 32, 2007) 2027 = and( 26, 2007) 2029 = and( 33, 2007) 2031 = and( 27, 2018) 2033 = and( 34, 2018) 2035 = and( 35, 2018) 2037 = and( 28, 2018) 2741 = not( 2735) 2749 = not( 2743) 2757 = not( 2751) 2765 = not( 2759) 2773 = not( 2767) 2781 = not( 2775) 2515 = nand( 2469, 2470) 2522 = not( 2518) 2525 = nand( 2513, 2514) 2528 = nand( 2503, 2504) 2730 = nand( 2707, 2708) 554 = and( 551, 553) 838 = or( 818, 819, 820, 821) 841 = or( 822, 823, 824, 825) 846 = or( 826, 827, 828, 829) 854 = or( 830, 831, 832, 833) 857 = or( 834, 835, 836, 837) 1327 = or( 1307, 1308, 1309, 1310) 1329 = or( 1311, 1312, 1313, 1314) 1331 = or( 1315, 1316, 1317, 1318) 1333 = or( 1319, 1320, 1321, 1322) 1335 = or( 1323, 1324, 1325, 1326) 1461 = or( 1441, 1442, 1443, 1444) 1464 = or( 1445, 1446, 1447, 1448) 1467 = or( 1449, 1450, 1451, 1452) 1470 = or( 1453, 1454, 1455, 1456) 1473 = or( 1457, 1458, 1459, 1460) 1698 = or( 1682, 1683, 1684, 1685) 1701 = or( 1686, 1687, 1688, 1689) 1704 = or( 1690, 1691, 1692, 1693) 1707 = or( 1694, 1695, 1696, 1697) 2634 = or( 1678, 1679, 1680, 1681) 319 = buff( 554) 1504 = not( 1500) 1513 = not( 1509) 1524 = not( 1521) 1528 = not( 1525) 1529 = buff( 1518) 1533 = buff( 1518) 1538 = and( 1486, 1477, 1521) 1541 = and( 1490, 1481, 1525) 1781 = not( 1777) 1790 = not( 1786) 1806 = buff( 1795) 1810 = buff( 1795) 2734 = not( 2730) 2521 = not( 2515) 2524 = nand( 2515, 2522) 2531 = not( 2525) 2532 = not( 2528) 144 = and( 838, 860) 147 = and( 846, 860) 152 = and( 841, 860) 160 = not( 1464) 162 = not( 1467) 164 = not( 1461) 166 = not( 1329) 168 = not( 1327) 171 = not( 857) 175 = and( 480, 483, 36, 554) 187 = and( 480, 483, 554, 547) 516 = buff( 838) 852 = not( 846) 885 = and( 841, 875) 887 = and( 846, 875) 893 = and( 1327, 868) 1028 = not( 838) 1031 = not( 841) 1035 = not( 846) 1041 = buff( 854) 1049 = buff( 857) 1057 = buff( 1327) 1060 = buff( 1329) 1066 = buff( 1331) 1072 = buff( 1333) 1078 = buff( 1335) 1213 = nand( 2099, 1470) 1218 = nand( 2103, 1473) 1250 = buff( 1704) 1387 = and( 1461, 1385) 1389 = not( 1464) 1537 = and( 1481, 1486, 1524) 1540 = and( 1477, 1490, 1528) 1735 = and( 841, 1710) 1737 = and( 846, 1710) 1739 = and( 854, 1710) 1741 = and( 857, 1710) 1743 = and( 1327, 1721) 1745 = and( 1329, 1721) 1747 = and( 1331, 1721) 1749 = and( 1333, 1721) 1751 = and( 1335, 1721) 2638 = not( 2634) 2024 = and( 1698, 2001) 2026 = and( 1701, 2001) 2028 = and( 1704, 2001) 2030 = and( 1707, 2001) 2032 = and( 1461, 2012) 2034 = and( 1464, 2012) 2036 = and( 1467, 2012) 2038 = and( 1470, 2012) 2154 = buff( 841) 2523 = nand( 2518, 2521) 2533 = nand( 2528, 2531) 2534 = nand( 2525, 2532) 2631 = buff( 1698) 2639 = buff( 1704) 2642 = buff( 1701) 2647 = buff( 1461) 2650 = buff( 1707) 2655 = buff( 1467) 2658 = buff( 1464) 2665 = buff( 1473) 2668 = buff( 1470) 153 = or( 865, 152) 176 = not( 175) 188 = not( 187) 299 = buff( 1041) 301 = buff( 1049) 286 = buff( 1057) 303 = buff( 1060) 288 = buff( 1066) 305 = buff( 1072) 290 = buff( 1078) 1532 = not( 1529) 1536 = not( 1533) 1539 = nor( 1537, 1538) 1542 = nor( 1540, 1541) 1544 = and( 1509, 1500, 1529) 1547 = and( 1513, 1504, 1533) 2065 = or( 2037, 2038) 1809 = not( 1806) 1813 = not( 1810) 1821 = and( 1786, 1777, 1806) 1824 = and( 1790, 1781, 1810) 2538 = nand( 2523, 2524) 2546 = nand( 2533, 2534) 2554 = or( 1734, 1735) 2562 = or( 1736, 1737) 2570 = or( 1738, 1739) 2578 = or( 1740, 1741) 2586 = or( 1742, 1743) 2594 = or( 1744, 1745) 2602 = or( 1746, 1747) 2610 = or( 1748, 1749) 2618 = or( 1750, 1751) 2626 = or( 2023, 2024) 2738 = or( 2025, 2026) 2746 = or( 2027, 2028) 2754 = or( 2029, 2030) 2762 = or( 2031, 2032) 2770 = or( 2033, 2034) 2778 = or( 2035, 2036) 456 = and( 1389, 1387, 40) 466 = not( 1387) 562 = nand( 560, 852) 883 = and( 516, 875) 889 = and( 1049, 868) 891 = and( 1041, 875) 1043 = not( 1041) 1051 = not( 1049) 1062 = not( 1060) 1068 = not( 1066) 1074 = not( 1072) 1080 = not( 1078) 1225 = and( 2099, 1213) 1227 = and( 1213, 1470) 1232 = and( 2103, 1218) 1234 = and( 1218, 1473) 1543 = and( 1504, 1509, 1532) 1546 = and( 1500, 1513, 1536) 2637 = not( 2631) 1753 = nand( 2631, 2638) 2645 = not( 2639) 2646 = not( 2642) 2653 = not( 2647) 2654 = not( 2650) 1820 = and( 1781, 1786, 1809) 1823 = and( 1777, 1790, 1813) 2107 = buff( 1031) 2110 = buff( 1028) 2118 = buff( 1035) 2123 = not( 1057) 2151 = not( 852) 2158 = not( 2154) 2161 = buff( 1031) 2164 = buff( 1028) 2172 = buff( 1035) 2235 = buff( 516) 2262 = buff( 1035) 2350 = buff( 1035) 2535 = nand( 1542, 1539) 2661 = not( 2655) 2662 = not( 2658) 2671 = not( 2665) 2672 = not( 2668) 468 = and( 40, 1389, 466) 897 = or( 887, 889) 898 = or( 891, 893) 1228 = or( 1225, 1227) 1235 = or( 1232, 1234) 1545 = nor( 1543, 1544) 1548 = nor( 1546, 1547) 2542 = not( 2538) 2550 = not( 2546) 1561 = nand( 2554, 2557) 2558 = not( 2554) 1565 = nand( 2562, 2565) 2566 = not( 2562) 1569 = nand( 2570, 2573) 2574 = not( 2570) 1573 = nand( 2578, 2581) 2582 = not( 2578) 1577 = nand( 2586, 2589) 2590 = not( 2586) 1581 = nand( 2594, 2597) 2598 = not( 2594) 1585 = nand( 2602, 2605) 2606 = not( 2602) 1589 = nand( 2610, 2613) 2614 = not( 2610) 1593 = nand( 2618, 2621) 2622 = not( 2618) 1597 = nand( 2626, 2629) 2630 = not( 2626) 1752 = nand( 2634, 2637) 1761 = nand( 2642, 2645) 1762 = nand( 2639, 2646) 1770 = nand( 2650, 2653) 1771 = nand( 2647, 2654) 1822 = nor( 1820, 1821) 1825 = nor( 1823, 1824) 2039 = nand( 2738, 2741) 2742 = not( 2738) 2043 = nand( 2746, 2749) 2750 = not( 2746) 2047 = nand( 2754, 2757) 2758 = not( 2754) 2051 = nand( 2762, 2765) 2766 = not( 2762) 2055 = nand( 2770, 2773) 2774 = not( 2770) 2059 = nand( 2778, 2781) 2782 = not( 2778) 2663 = nand( 2658, 2661) 2664 = nand( 2655, 2662) 2673 = nand( 2668, 2671) 2674 = nand( 2665, 2672) 146 = and( 562, 865) 462 = not( 456) 2113 = not( 2107) 2114 = not( 2110) 2122 = not( 2118) 2129 = not( 2123) 592 = buff( 562) 2167 = not( 2161) 2168 = not( 2164) 2176 = not( 2172) 2241 = not( 2235) 2266 = not( 2262) 743 = not( 456) 749 = buff( 456) 886 = and( 562, 868) 284 = buff( 897) 321 = buff( 897) 297 = buff( 898) 280 = buff( 898) 995 = buff( 456) 1006 = not( 456) 1550 = nand( 2535, 2542) 2354 = not( 2350) 2541 = not( 2535) 1562 = nand( 2551, 2558) 1566 = nand( 2559, 2566) 1570 = nand( 2567, 2574) 1574 = nand( 2575, 2582) 1578 = nand( 2583, 2590) 1582 = nand( 2591, 2598) 1586 = nand( 2599, 2606) 1590 = nand( 2607, 2614) 1594 = nand( 2615, 2622) 1598 = nand( 2623, 2630) 1754 = nand( 1752, 1753) 1763 = nand( 1761, 1762) 1772 = nand( 1770, 1771) 2040 = nand( 2735, 2742) 2044 = nand( 2743, 2750) 2048 = nand( 2751, 2758) 2052 = nand( 2759, 2766) 2056 = nand( 2767, 2774) 2060 = nand( 2775, 2782) 2115 = buff( 1043) 2126 = buff( 1051) 2131 = buff( 1068) 2134 = buff( 1062) 2141 = buff( 1080) 2144 = buff( 1074) 2157 = not( 2151) 2160 = nand( 2151, 2158) 2169 = buff( 1043) 2177 = buff( 1068) 2180 = buff( 1062) 2187 = buff( 1080) 2190 = buff( 1074) 2207 = not( 562) 2254 = buff( 1043) 2334 = buff( 1051) 2342 = buff( 1043) 2422 = buff( 1051) 2543 = nand( 1548, 1545) 2709 = nand( 2673, 2674) 2712 = nand( 2663, 2664) 2727 = nand( 1825, 1822) 148 = or( 146, 147) 569 = nand( 2110, 2113) 570 = nand( 2107, 2114) 599 = nand( 2164, 2167) 600 = nand( 2161, 2168) 896 = or( 885, 886) 1549 = nand( 2538, 2541) 1243 = not( 1228) 1245 = not( 1235) 1257 = buff( 468) 1258 = buff( 468) 1563 = nand( 1561, 1562) 1567 = nand( 1565, 1566) 1571 = nand( 1569, 1570) 1575 = nand( 1573, 1574) 1579 = nand( 1577, 1578) 1583 = nand( 1581, 1582) 1587 = nand( 1585, 1586) 1591 = nand( 1589, 1590) 1595 = nand( 1593, 1594) 1599 = nand( 1597, 1598) 2041 = nand( 2039, 2040) 2045 = nand( 2043, 2044) 2049 = nand( 2047, 2048) 2053 = nand( 2051, 2052) 2057 = nand( 2055, 2056) 2061 = nand( 2059, 2060) 2159 = nand( 2154, 2157) 475 = buff( 462) 490 = and( 1078, 743) 496 = and( 1698, 743) 502 = and( 1701, 743) 508 = and( 1250, 743) 765 = and( 1057, 749) 769 = and( 1060, 749) 571 = nand( 569, 570) 2121 = not( 2115) 579 = nand( 2115, 2122) 587 = nand( 2126, 2129) 2130 = not( 2126) 596 = not( 592) 601 = nand( 599, 600) 2175 = not( 2169) 609 = nand( 2169, 2176) 2258 = not( 2254) 1014 = and( 1057, 995) 1018 = and( 1060, 995) 717 = and( 1078, 1006) 723 = and( 1698, 1006) 729 = and( 1701, 1006) 735 = and( 1250, 1006) 753 = not( 749) 282 = buff( 896) 323 = buff( 896) 2338 = not( 2334) 999 = not( 995) 1091 = nand( 1549, 1550) 2346 = not( 2342) 2426 = not( 2422) 1337 = buff( 462) 2549 = not( 2543) 1552 = nand( 2543, 2550) 1600 = not( 1599) 1596 = not( 1595) 1592 = not( 1591) 1588 = not( 1587) 1584 = not( 1583) 1580 = not( 1579) 1576 = not( 1575) 1572 = not( 1571) 1568 = not( 1567) 1564 = not( 1563) 2062 = not( 2061) 2058 = not( 2057) 2054 = not( 2053) 2050 = not( 2049) 2046 = not( 2045) 2042 = not( 2041) 1758 = not( 1754) 1767 = not( 1763) 1798 = buff( 1772) 1802 = buff( 1772) 2733 = not( 2727) 1829 = nand( 2727, 2734) 2137 = not( 2131) 2138 = not( 2134) 2147 = not( 2141) 2148 = not( 2144) 2183 = not( 2177) 2184 = not( 2180) 2193 = not( 2187) 2194 = not( 2190) 2210 = nand( 2159, 2160) 2213 = not( 2207) 2715 = not( 2709) 2716 = not( 2712) 1094 = and( 1235, 1245) 1096 = and( 1228, 1243) 578 = nand( 2118, 2121) 588 = nand( 2123, 2130) 608 = nand( 2172, 2175) 742 = buff( 1257) 1005 = buff( 1257) 1092 = not( 1091) 1551 = nand( 2546, 2549) 1554 = and( 1600, 1596, 1592, 1588, 1584) 1555 = and( 1580, 1576, 1572, 1568, 1564) 1557 = and( 2065, 2062) 1558 = and( 2058, 2054, 2050, 2046, 2042) 1828 = nand( 2730, 2733) 1845 = buff( 1258) 1907 = buff( 1258) 2139 = nand( 2134, 2137) 2140 = nand( 2131, 2138) 2149 = nand( 2144, 2147) 2150 = nand( 2141, 2148) 2185 = nand( 2180, 2183) 2186 = nand( 2177, 2184) 2195 = nand( 2190, 2193) 2196 = nand( 2187, 2194) 2717 = nand( 2712, 2715) 2718 = nand( 2709, 2716) 154 = or( 1094, 1245) 155 = or( 1096, 1243) 763 = and( 1057, 753) 767 = and( 1060, 753) 531 = and( 1066, 753) 537 = and( 1072, 753) 575 = not( 571) 580 = nand( 578, 579) 589 = nand( 587, 588) 605 = not( 601) 610 = nand( 608, 609) 1012 = and( 1057, 999) 1016 = and( 1060, 999) 705 = and( 1066, 999) 711 = and( 1072, 999) 1093 = and( 1092, 14) 1355 = buff( 475) 1553 = nand( 1551, 1552) 1556 = and( 1554, 1555) 1559 = and( 1557, 1558) 1601 = buff( 1337) 1801 = not( 1798) 1805 = not( 1802) 1815 = and( 1763, 1754, 1798) 1818 = and( 1767, 1758, 1802) 1830 = nand( 1828, 1829) 1836 = buff( 475) 1850 = buff( 475) 1898 = buff( 1337) 1912 = buff( 1337) 2197 = nand( 2149, 2150) 2200 = nand( 2139, 2140) 2214 = not( 2210) 2215 = nand( 2210, 2213) 2217 = nand( 2195, 2196) 2220 = nand( 2185, 2186) 2722 = nand( 2717, 2718) 156 = nand( 154, 155) 492 = and( 490, 742) 498 = and( 496, 742) 504 = and( 502, 742) 510 = and( 508, 742) 519 = or( 763, 765) 525 = or( 767, 769) 533 = and( 531, 748) 539 = and( 537, 748) 693 = or( 1012, 1014) 699 = or( 1016, 1018) 707 = and( 705, 994) 713 = and( 711, 994) 719 = and( 717, 1005) 725 = and( 723, 1005) 731 = and( 729, 1005) 737 = and( 735, 1005) 401 = buff( 1093) 1560 = and( 1556, 1559, 894) 1814 = and( 1758, 1763, 1801) 1817 = and( 1754, 1767, 1805) 2216 = nand( 2207, 2214) 227 = not( 1830) 229 = not( 1553) 493 = not( 492) 499 = not( 498) 505 = not( 504) 511 = not( 510) 521 = and( 519, 748) 527 = and( 525, 748) 534 = not( 533) 540 = not( 539) 584 = not( 580) 613 = buff( 589) 617 = buff( 589) 621 = buff( 610) 625 = buff( 610) 676 = and( 1344, 1355) 695 = and( 693, 994) 701 = and( 699, 994) 708 = not( 707) 714 = not( 713) 720 = not( 719) 726 = not( 725) 732 = not( 731) 738 = not( 737) 1087 = not( 1093) 1108 = and( 1344, 1601) 1361 = not( 1355) 1369 = and( 1351, 1355) 1373 = and( 1959, 1355) 1377 = and( 1964, 1355) 311 = buff( 1560) 1607 = not( 1601) 1615 = and( 1351, 1601) 1619 = and( 1959, 1601) 1623 = and( 1964, 1601) 1816 = nor( 1814, 1815) 1819 = nor( 1817, 1818) 2726 = not( 2722) 1842 = not( 1836) 1858 = and( 1969, 1836) 1863 = and( 1974, 1836) 1866 = and( 1979, 1836) 1868 = and( 1984, 1836) 1870 = and( 1989, 1850) 1872 = and( 1994, 1850) 1874 = and( 1999, 1850) 1876 = and( 2070, 1850) 1904 = not( 1898) 1920 = and( 1969, 1898) 1925 = and( 1974, 1898) 1928 = and( 1979, 1898) 1930 = and( 1984, 1898) 1932 = and( 1989, 1912) 1934 = and( 1994, 1912) 1936 = and( 1999, 1912) 1938 = and( 2070, 1912) 2203 = not( 2197) 2204 = not( 2200) 2223 = not( 2217) 2224 = not( 2220) 2238 = nand( 2215, 2216) 150 = not( 1560) 522 = not( 521) 528 = not( 527) 696 = not( 695) 702 = not( 701) 1881 = and( 1866, 1831) 1883 = and( 1868, 1831) 1885 = and( 1870, 1845) 1887 = and( 1872, 1845) 1889 = and( 1874, 1845) 1891 = and( 1876, 1845) 1943 = and( 1928, 1893) 1945 = and( 1930, 1893) 1947 = and( 1932, 1907) 1949 = and( 1934, 1907) 1951 = and( 1936, 1907) 1953 = and( 1938, 1907) 2205 = nand( 2200, 2203) 2206 = nand( 2197, 2204) 2225 = nand( 2220, 2223) 2226 = nand( 2217, 2224) 2719 = nand( 1819, 1816) 616 = not( 613) 620 = not( 617) 624 = not( 621) 628 = not( 625) 630 = and( 580, 571, 613) 633 = and( 584, 575, 617) 636 = and( 601, 592, 621) 639 = and( 605, 596, 625) 645 = nand( 2238, 2241) 2242 = not( 2238) 675 = and( 1999, 1361) 1107 = and( 1999, 1607) 1368 = and( 2070, 1361) 1371 = and( 2076, 1361) 1375 = and( 2082, 1361) 1614 = and( 2070, 1607) 1617 = and( 2076, 1607) 1621 = and( 2082, 1607) 1856 = and( 2088, 1842) 1861 = and( 2094, 1842) 1918 = and( 2088, 1904) 1923 = and( 2094, 1904) 2230 = nand( 2205, 2206) 2246 = nand( 2225, 2226) 2270 = buff( 511) 2278 = buff( 505) 2286 = buff( 499) 2294 = buff( 493) 2302 = buff( 540) 2310 = buff( 534) 2358 = buff( 738) 2366 = buff( 732) 2374 = buff( 726) 2382 = buff( 720) 2390 = buff( 714) 2398 = buff( 708) 629 = and( 575, 580, 616) 632 = and( 571, 584, 620) 635 = and( 596, 601, 624) 638 = and( 592, 605, 628) 646 = nand( 2235, 2242) 677 = or( 675, 676) 1827 = nand( 2719, 2726) 907 = and( 1891, 511) 915 = and( 1889, 505) 922 = and( 1887, 499) 924 = and( 493, 1885) 937 = and( 1883, 540) 946 = and( 1881, 534) 1109 = or( 1107, 1108) 1125 = and( 1953, 738) 1133 = and( 1951, 732) 1140 = and( 1949, 726) 1142 = and( 720, 1947) 1155 = and( 1945, 714) 1164 = and( 1943, 708) 1378 = or( 1368, 1369) 1380 = or( 1371, 1373) 1382 = or( 1375, 1377) 1624 = or( 1614, 1615) 1626 = or( 1617, 1619) 1628 = or( 1621, 1623) 2725 = not( 2719) 1859 = or( 1856, 1858) 1864 = or( 1861, 1863) 1921 = or( 1918, 1920) 1926 = or( 1923, 1925) 2267 = buff( 1891) 2275 = buff( 1889) 2283 = buff( 1887) 2291 = buff( 1885) 2299 = buff( 1883) 2307 = buff( 1881) 2318 = buff( 528) 2326 = buff( 522) 2355 = buff( 1953) 2363 = buff( 1951) 2371 = buff( 1949) 2379 = buff( 1947) 2387 = buff( 1945) 2395 = buff( 1943) 2406 = buff( 702) 2414 = buff( 696) 647 = nand( 645, 646) 631 = nor( 629, 630) 634 = nor( 632, 633) 637 = nor( 635, 636) 640 = nor( 638, 639) 2234 = not( 2230) 2250 = not( 2246) 679 = and( 677, 1031) 1826 = nand( 2722, 2725) 2274 = not( 2270) 2282 = not( 2278) 2290 = not( 2286) 2298 = not( 2294) 2306 = not( 2302) 2314 = not( 2310) 1110 = and( 1109, 1031) 2362 = not( 2358) 2370 = not( 2366) 2378 = not( 2374) 2386 = not( 2382) 2394 = not( 2390) 2402 = not( 2398) 1877 = and( 1859, 1831) 1879 = and( 1864, 1831) 1939 = and( 1921, 1893) 1941 = and( 1926, 1893) 143 = and( 647, 865) 671 = and( 1380, 1043) 674 = and( 1378, 1035) 686 = nand( 1826, 1827) 2273 = not( 2267) 900 = nand( 2267, 2274) 2281 = not( 2275) 909 = nand( 2275, 2282) 2289 = not( 2283) 917 = nand( 2283, 2290) 2297 = not( 2291) 926 = nand( 2291, 2298) 2305 = not( 2299) 929 = nand( 2299, 2306) 2313 = not( 2307) 939 = nand( 2307, 2314) 2322 = not( 2318) 2330 = not( 2326) 967 = and( 1382, 1051) 1104 = and( 1626, 1043) 1106 = and( 1624, 1035) 2361 = not( 2355) 1118 = nand( 2355, 2362) 2369 = not( 2363) 1127 = nand( 2363, 2370) 2377 = not( 2371) 1135 = nand( 2371, 2378) 2385 = not( 2379) 1144 = nand( 2379, 2386) 2393 = not( 2387) 1147 = nand( 2387, 2394) 2401 = not( 2395) 1157 = nand( 2395, 2402) 2410 = not( 2406) 2418 = not( 2414) 1184 = and( 1628, 1051) 2227 = nand( 634, 631) 2243 = nand( 640, 637) 2251 = buff( 1380) 2259 = buff( 1378) 2331 = buff( 1382) 2339 = buff( 1626) 2347 = buff( 1624) 2419 = buff( 1628) 145 = or( 143, 144) 687 = not( 686) 899 = nand( 2270, 2273) 908 = nand( 2278, 2281) 916 = nand( 2286, 2289) 925 = nand( 2294, 2297) 928 = nand( 2302, 2305) 938 = nand( 2310, 2313) 954 = and( 1879, 528) 961 = and( 1877, 522) 1117 = nand( 2358, 2361) 1126 = nand( 2366, 2369) 1134 = nand( 2374, 2377) 1143 = nand( 2382, 2385) 1146 = nand( 2390, 2393) 1156 = nand( 2398, 2401) 1172 = and( 1941, 702) 1179 = and( 1939, 696) 2315 = buff( 1879) 2323 = buff( 1877) 2403 = buff( 1941) 2411 = buff( 1939) 2233 = not( 2227) 642 = nand( 2227, 2234) 2249 = not( 2243) 649 = nand( 2243, 2250) 2257 = not( 2251) 665 = nand( 2251, 2258) 684 = nand( 2259, 2266) 2265 = not( 2259) 688 = and( 687, 487) 901 = nand( 899, 900) 910 = nand( 908, 909) 918 = nand( 916, 917) 927 = nand( 925, 926) 930 = nand( 928, 929) 940 = nand( 938, 939) 2337 = not( 2331) 963 = nand( 2331, 2338) 2345 = not( 2339) 1099 = nand( 2339, 2346) 1115 = nand( 2347, 2354) 2353 = not( 2347) 1119 = nand( 1117, 1118) 1128 = nand( 1126, 1127) 1136 = nand( 1134, 1135) 1145 = nand( 1143, 1144) 1148 = nand( 1146, 1147) 1158 = nand( 1156, 1157) 2425 = not( 2419) 1181 = nand( 2419, 2426) 641 = nand( 2230, 2233) 648 = nand( 2246, 2249) 664 = nand( 2254, 2257) 683 = nand( 2262, 2265) 395 = buff( 688) 2321 = not( 2315) 948 = nand( 2315, 2322) 2329 = not( 2323) 956 = nand( 2323, 2330) 962 = nand( 2334, 2337) 1098 = nand( 2342, 2345) 1114 = nand( 2350, 2353) 2409 = not( 2403) 1166 = nand( 2403, 2410) 2417 = not( 2411) 1174 = nand( 2411, 2418) 1180 = nand( 2422, 2425) 643 = nand( 641, 642) 650 = nand( 648, 649) 666 = nand( 664, 665) 681 = nand( 683, 684) 690 = not( 688) 947 = nand( 2318, 2321) 955 = nand( 2326, 2329) 964 = nand( 962, 963) 968 = and( 910, 927, 918, 901) 970 = and( 901, 915) 971 = and( 910, 901, 922) 972 = and( 918, 901, 924, 910) 978 = and( 930, 946) 979 = and( 940, 930, 954) 1100 = nand( 1098, 1099) 1112 = nand( 1114, 1115) 1165 = nand( 2406, 2409) 1173 = nand( 2414, 2417) 1182 = nand( 1180, 1181) 1185 = and( 1128, 1145, 1136, 1119) 1187 = and( 1119, 1133) 1188 = and( 1128, 1119, 1140) 1189 = and( 1136, 1119, 1142, 1128) 1195 = and( 1148, 1164) 1196 = and( 1158, 1148, 1172) 644 = not( 643) 884 = and( 650, 868) 949 = nand( 947, 948) 957 = nand( 955, 956) 969 = not( 968) 973 = or( 907, 970, 971, 972) 1167 = nand( 1165, 1166) 1175 = nand( 1173, 1174) 1186 = not( 1185) 1190 = or( 1125, 1187, 1188, 1189) 680 = and( 666, 674) 682 = and( 681, 666, 679) 895 = or( 883, 884) 1025 = and( 644, 487) 1111 = and( 1100, 1106) 1113 = and( 1112, 1100, 1110) 685 = or( 671, 680, 682) 295 = buff( 895) 331 = buff( 895) 976 = not( 973) 977 = and( 940, 964, 949, 930, 957) 980 = and( 949, 930, 961, 940) 981 = and( 957, 949, 930, 967, 940) 397 = buff( 1025) 1116 = or( 1104, 1111, 1113) 1193 = not( 1190) 1194 = and( 1158, 1182, 1167, 1148, 1175) 1197 = and( 1167, 1148, 1179, 1158) 1198 = and( 1175, 1167, 1148, 1184, 1158) 982 = or( 937, 978, 979, 980, 981) 983 = and( 977, 685) 988 = nand( 976, 969) 1027 = not( 1025) 1199 = or( 1155, 1195, 1196, 1197, 1198) 1200 = and( 1194, 1116) 1205 = nand( 1193, 1186) 984 = or( 982, 983) 1085 = and( 690, 1027, 1830) 1201 = or( 1199, 1200) 987 = not( 984) 990 = and( 988, 984) 1204 = not( 1201) 1207 = and( 1205, 1201) 989 = and( 973, 987) 1206 = and( 1190, 1204) 991 = or( 989, 990) 1208 = or( 1206, 1207) 329 = buff( 1208) 1221 = nand( 1208, 991) 1238 = and( 1208, 1221) 1239 = and( 1221, 991) 1240 = or( 1238, 1239) 1247 = not( 1240) 471 = and( 1240, 1247) 473 = or( 471, 1247) 231 = not( 473) 1088 = and( 1553, 1087, 473) 1089 = and( 1085, 1088, 554) 308 = buff( 1089) 225 = not( 1089) |
Added c2670/c2670gate.v.
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 |
/****************************************************************************
* *
* VERILOG VERSION of ORIGINAL NETLIST for c2670 *
* *
* *
* Generated by: Hakan Yalcin (hyalcin@cadence.com) *
* *
* Sep 16, 1998 *
* *
****************************************************************************/
module c2670g (
L81, L92, L91, L90, L89, L88, L87,
L86, L85, L93, L43, L54, L53, L52, L51,
L50, L49, L48, L47, L55, L56, L66, L65,
L64, L63, L62, L61, L60, L67, L68, L79,
L78, L77, L76, L75, L74, L73, L72, L80,
L131, L141, L140, L139, L138, L137, L136, L135,
L142, L95, L105, L104, L103, L102, L101, L100,
L99, L106, L119, L129, L128, L127, L126, L125,
L124, L123, L130, L107, L117, L116, L115, L114,
L113, L112, L111, L118, L1971, L1966, L1961, L1956,
L1348, L1341, L2090, L2084, L2078, L2072, L2067, L1996,
L1991, L1986, L1981, L1976, L2096, L2100, L2678, L2474,
L2427, L2430, L2451, L2454, L2443, L2446, L2435, L2438,
L24, L6, L23, L22, L21, L5, L20, L4,
L19, L28, L35, L34, L27, L33, L26, L32,
L25, L651, L543, L2105, L2104, L1384, L40, L16,
L29, L11, L8, L37, L14, L44, L132, L82,
L96, L69, L120, L57, L108, L2106, L567, L559,
L860, L868, L452, L2066, L1083, L94, L7, L661,
L1, L2, L3, L15, L36, L483, L169, L174,
L177, L178, L179, L180, L181, L182, L183, L184,
L185, L186, L189, L190, L191, L192, L193, L194,
L195, L196, L197, L198, L199, L200, L201, L202,
L203, L204, L205, L206, L207, L208, L209, L210,
L211, L212, L213, L214, L215, L239, L240, L241,
L242, L243, L244, L245, L246, L247, L248, L249,
L250, L251, L252, L253, L254, L255, L256, L257,
L262, L263, L264, L265, L266, L267, L268, L269,
L270, L271, L272, L273, L274, L275, L276, L277,
L278, L279,
L329, L231, L311, L150, L308, L225, L395,
L397, L227, L229, L401, L319, L325, L261, L220,
L221, L219, L218, L235, L236, L237, L238, L335,
L350, L391, L409, L337, L384, L411, L367, L369,
L173, L295, L331, L145, L148, L282, L323, L284,
L321, L297, L280, L153, L290, L305, L288, L303,
L286, L301, L299, L166, L168, L171, L162, L160,
L164, L156, L223, L217, L234, L259, L176, L188,
L158, L169o, L174o, L177o, L178o, L179o, L180o, L181o,
L182o, L183o, L184o, L185o, L186o, L189o, L190o, L191o,
L192o, L193o, L194o, L195o, L196o, L197o, L198o, L199o,
L200o, L201o, L202o, L203o, L204o, L205o, L206o, L207o,
L208o, L209o, L210o, L211o, L212o, L213o, L214o, L215o,
L239o, L240o, L241o, L242o, L243o, L244o, L245o, L246o,
L247o, L248o, L249o, L250o, L251o, L252o, L253o, L254o,
L255o, L256o, L257o, L262o, L263o, L264o, L265o, L266o,
L267o, L268o, L269o, L270o, L271o, L272o, L273o, L274o,
L275o, L276o, L277o, L278o, L279o);
input
L81, L92, L91, L90, L89, L88, L87,
L86, L85, L93, L43, L54, L53, L52, L51,
L50, L49, L48, L47, L55, L56, L66, L65,
L64, L63, L62, L61, L60, L67, L68, L79,
L78, L77, L76, L75, L74, L73, L72, L80,
L131, L141, L140, L139, L138, L137, L136, L135,
L142, L95, L105, L104, L103, L102, L101, L100,
L99, L106, L119, L129, L128, L127, L126, L125,
L124, L123, L130, L107, L117, L116, L115, L114,
L113, L112, L111, L118, L1971, L1966, L1961, L1956,
L1348, L1341, L2090, L2084, L2078, L2072, L2067, L1996,
L1991, L1986, L1981, L1976, L2096, L2100, L2678, L2474,
L2427, L2430, L2451, L2454, L2443, L2446, L2435, L2438,
L24, L6, L23, L22, L21, L5, L20, L4,
L19, L28, L35, L34, L27, L33, L26, L32,
L25, L651, L543, L2105, L2104, L1384, L40, L16,
L29, L11, L8, L37, L14, L44, L132, L82,
L96, L69, L120, L57, L108, L2106, L567, L559,
L860, L868, L452, L2066, L1083, L94, L7, L661,
L1, L2, L3, L15, L36, L483, L169, L174,
L177, L178, L179, L180, L181, L182, L183, L184,
L185, L186, L189, L190, L191, L192, L193, L194,
L195, L196, L197, L198, L199, L200, L201, L202,
L203, L204, L205, L206, L207, L208, L209, L210,
L211, L212, L213, L214, L215, L239, L240, L241,
L242, L243, L244, L245, L246, L247, L248, L249,
L250, L251, L252, L253, L254, L255, L256, L257,
L262, L263, L264, L265, L266, L267, L268, L269,
L270, L271, L272, L273, L274, L275, L276, L277,
L278, L279;
output
L329, L231, L311, L150, L308, L225, L395,
L397, L227, L229, L401, L319, L325, L261, L220,
L221, L219, L218, L235, L236, L237, L238, L335,
L350, L391, L409, L337, L384, L411, L367, L369,
L173, L295, L331, L145, L148, L282, L323, L284,
L321, L297, L280, L153, L290, L305, L288, L303,
L286, L301, L299, L166, L168, L171, L162, L160,
L164, L156, L223, L217, L234, L259, L176, L188,
L158, L169o, L174o, L177o, L178o, L179o, L180o, L181o,
L182o, L183o, L184o, L185o, L186o, L189o, L190o, L191o,
L192o, L193o, L194o, L195o, L196o, L197o, L198o, L199o,
L200o, L201o, L202o, L203o, L204o, L205o, L206o, L207o,
L208o, L209o, L210o, L211o, L212o, L213o, L214o, L215o,
L239o, L240o, L241o, L242o, L243o, L244o, L245o, L246o,
L247o, L248o, L249o, L250o, L251o, L252o, L253o, L254o,
L255o, L256o, L257o, L262o, L263o, L264o, L265o, L266o,
L267o, L268o, L269o, L270o, L271o, L272o, L273o, L274o,
L275o, L276o, L277o, L278o, L279o;
assign L169o = L169;
assign L174o = L174;
assign L177o = L177;
assign L178o = L178;
assign L179o = L179;
assign L180o = L180;
assign L181o = L181;
assign L182o = L182;
assign L183o = L183;
assign L184o = L184;
assign L185o = L185;
assign L186o = L186;
assign L189o = L189;
assign L190o = L190;
assign L191o = L191;
assign L192o = L192;
assign L193o = L193;
assign L194o = L194;
assign L195o = L195;
assign L196o = L196;
assign L197o = L197;
assign L198o = L198;
assign L199o = L199;
assign L200o = L200;
assign L201o = L201;
assign L202o = L202;
assign L203o = L203;
assign L204o = L204;
assign L205o = L205;
assign L206o = L206;
assign L207o = L207;
assign L208o = L208;
assign L209o = L209;
assign L210o = L210;
assign L211o = L211;
assign L212o = L212;
assign L213o = L213;
assign L214o = L214;
assign L215o = L215;
assign L239o = L239;
assign L240o = L240;
assign L241o = L241;
assign L242o = L242;
assign L243o = L243;
assign L244o = L244;
assign L245o = L245;
assign L246o = L246;
assign L247o = L247;
assign L248o = L248;
assign L249o = L249;
assign L250o = L250;
assign L251o = L251;
assign L252o = L252;
assign L253o = L253;
assign L254o = L254;
assign L255o = L255;
assign L256o = L256;
assign L257o = L257;
assign L262o = L262;
assign L263o = L263;
assign L264o = L264;
assign L265o = L265;
assign L266o = L266;
assign L267o = L267;
assign L268o = L268;
assign L269o = L269;
assign L270o = L270;
assign L271o = L271;
assign L272o = L272;
assign L273o = L273;
assign L274o = L274;
assign L275o = L275;
assign L276o = L276;
assign L277o = L277;
assign L278o = L278;
assign L279o = L279;
buffer U77 ( L452, L350 );
buffer U78 ( L452, L335 );
buffer U79 ( L452, L409 );
and2 U80 ( L1, L3, L546 );
inv U81 ( L559, L560 );
buffer U82 ( L1083, L369 );
buffer U83 ( L1083, L367 );
inv U84 ( L1384, L1385 );
buffer U85 ( L2066, L411 );
buffer U86 ( L2066, L337 );
buffer U87 ( L2066, L384 );
and4 U88 ( L2090, L2084, L2078, L2072, L157 );
inv U89 ( L546, L547 );
inv U90 ( L44, L218 );
inv U91 ( L132, L219 );
inv U92 ( L82, L220 );
inv U93 ( L96, L221 );
inv U94 ( L69, L235 );
inv U95 ( L120, L236 );
inv U96 ( L57, L237 );
inv U97 ( L108, L238 );
and3 U98 ( L2, L15, L661, L258 );
buffer U99 ( L661, L480 );
buffer U100 ( L37, L486 );
buffer U101 ( L452, L654 );
buffer U102 ( L8, L655 );
buffer U103 ( L8, L658 );
buffer U104 ( L543, L772 );
buffer U105 ( L651, L795 );
inv U106 ( L860, L865 );
inv U107 ( L868, L875 );
and2 U108 ( L11, L868, L882 );
and4 U109 ( L132, L82, L96, L44, L1251 );
and4 U110 ( L120, L57, L108, L69, L1254 );
buffer U111 ( L543, L1261 );
buffer U112 ( L651, L1284 );
inv U113 ( L1341, L1344 );
inv U114 ( L1348, L1351 );
buffer U115 ( L2104, L1394 );
buffer U116 ( L2105, L1418 );
inv U117 ( L2427, L2433 );
inv U118 ( L2430, L2434 );
inv U119 ( L2435, L2441 );
inv U120 ( L2438, L2442 );
inv U121 ( L2443, L2449 );
inv U122 ( L2446, L2450 );
inv U123 ( L2474, L2478 );
buffer U124 ( L2104, L1631 );
buffer U125 ( L2105, L1655 );
buffer U126 ( L16, L1710 );
buffer U127 ( L16, L1721 );
inv U128 ( L2678, L2682 );
and2 U129 ( L7, L661, L1955 );
inv U130 ( L1956, L1959 );
inv U131 ( L1961, L1964 );
inv U132 ( L1966, L1969 );
inv U133 ( L1971, L1974 );
inv U134 ( L1976, L1979 );
inv U135 ( L1981, L1984 );
inv U136 ( L1986, L1989 );
inv U137 ( L1991, L1994 );
inv U138 ( L1996, L1999 );
buffer U139 ( L29, L2001 );
buffer U140 ( L29, L2012 );
inv U141 ( L2067, L2070 );
inv U142 ( L2072, L2076 );
inv U143 ( L2078, L2082 );
inv U144 ( L2084, L2088 );
inv U145 ( L2090, L2094 );
inv U146 ( L2096, L2099 );
inv U147 ( L2100, L2103 );
inv U148 ( L2451, L2457 );
inv U149 ( L2454, L2458 );
buffer U150 ( L1348, L2461 );
buffer U151 ( L1341, L2464 );
buffer U152 ( L1956, L2471 );
buffer U153 ( L1966, L2479 );
buffer U154 ( L1961, L2482 );
buffer U155 ( L1976, L2487 );
buffer U156 ( L1971, L2490 );
buffer U157 ( L1986, L2495 );
buffer U158 ( L1981, L2498 );
buffer U159 ( L1996, L2505 );
buffer U160 ( L1991, L2508 );
buffer U161 ( L2067, L2675 );
buffer U162 ( L2078, L2683 );
buffer U163 ( L2072, L2686 );
buffer U164 ( L2090, L2691 );
buffer U165 ( L2084, L2694 );
buffer U166 ( L2100, L2699 );
buffer U167 ( L2096, L2702 );
inv U168 ( L157, L158 );
inv U169 ( L258, L259 );
inv U170 ( L486, L487 );
buffer U171 ( L654, L391 );
nand2 U172 ( L2430, L2433, L1475 );
nand2 U173 ( L2427, L2434, L1476 );
nand2 U174 ( L2438, L2441, L1484 );
nand2 U175 ( L2435, L2442, L1485 );
nand2 U176 ( L2446, L2449, L1493 );
nand2 U177 ( L2443, L2450, L1494 );
nand2 U178 ( L2454, L2457, L2459 );
nand2 U179 ( L2451, L2458, L2460 );
and2 U180 ( L94, L654, L173 );
and2 U181 ( L2106, L1955, L216 );
inv U182 ( L1955, L223 );
nand2 U183 ( L567, L1955, L234 );
inv U184 ( L1251, L1253 );
inv U185 ( L1254, L1256 );
and2 U186 ( L1254, L1251, L558 );
buffer U187 ( L655, L748 );
inv U188 ( L772, L784 );
inv U189 ( L795, L807 );
and3 U190 ( L80, L772, L795, L821 );
and3 U191 ( L68, L772, L795, L825 );
and3 U192 ( L79, L772, L795, L829 );
and3 U193 ( L78, L772, L795, L833 );
and3 U194 ( L77, L772, L795, L837 );
and2 U195 ( L11, L875, L881 );
buffer U196 ( L655, L994 );
inv U197 ( L1261, L1273 );
inv U198 ( L1284, L1296 );
and3 U199 ( L76, L1261, L1284, L1310 );
and3 U200 ( L75, L1261, L1284, L1314 );
and3 U201 ( L74, L1261, L1284, L1318 );
and3 U202 ( L73, L1261, L1284, L1322 );
and3 U203 ( L72, L1261, L1284, L1326 );
inv U204 ( L1394, L1406 );
inv U205 ( L1418, L1430 );
and3 U206 ( L114, L1394, L1418, L1444 );
and3 U207 ( L113, L1394, L1418, L1448 );
and3 U208 ( L112, L1394, L1418, L1452 );
and3 U209 ( L111, L1394, L1418, L1456 );
and2 U210 ( L1394, L1418, L1460 );
nand2 U211 ( L1475, L1476, L1477 );
nand2 U212 ( L1484, L1485, L1486 );
nand2 U213 ( L1493, L1494, L1495 );
inv U214 ( L2471, L2477 );
nand2 U215 ( L2471, L2478, L1499 );
inv U216 ( L2479, L2485 );
inv U217 ( L2482, L2486 );
inv U218 ( L2487, L2493 );
inv U219 ( L2490, L2494 );
inv U220 ( L1631, L1643 );
inv U221 ( L1655, L1667 );
and3 U222 ( L118, L1631, L1655, L1681 );
and3 U223 ( L107, L1631, L1655, L1685 );
and3 U224 ( L117, L1631, L1655, L1689 );
and3 U225 ( L116, L1631, L1655, L1693 );
and3 U226 ( L115, L1631, L1655, L1697 );
inv U227 ( L1710, L1716 );
inv U228 ( L1721, L1728 );
inv U229 ( L2675, L2681 );
nand2 U230 ( L2675, L2682, L1776 );
inv U231 ( L2683, L2689 );
inv U232 ( L2686, L2690 );
inv U233 ( L2691, L2697 );
inv U234 ( L2694, L2698 );
buffer U235 ( L658, L1831 );
buffer U236 ( L658, L1893 );
inv U237 ( L2001, L2007 );
inv U238 ( L2012, L2018 );
inv U239 ( L2461, L2467 );
inv U240 ( L2464, L2468 );
inv U241 ( L2495, L2501 );
inv U242 ( L2498, L2502 );
inv U243 ( L2505, L2511 );
inv U244 ( L2508, L2512 );
nand2 U245 ( L2459, L2460, L2518 );
buffer U246 ( L1344, L2551 );
buffer U247 ( L1351, L2559 );
buffer U248 ( L1959, L2567 );
buffer U249 ( L1964, L2575 );
buffer U250 ( L1969, L2583 );
buffer U251 ( L1974, L2591 );
buffer U252 ( L1979, L2599 );
buffer U253 ( L1984, L2607 );
buffer U254 ( L1989, L2615 );
buffer U255 ( L1994, L2623 );
inv U256 ( L2699, L2705 );
inv U257 ( L2702, L2706 );
buffer U258 ( L1999, L2735 );
buffer U259 ( L2070, L2743 );
buffer U260 ( L2076, L2751 );
buffer U261 ( L2082, L2759 );
buffer U262 ( L2088, L2767 );
buffer U263 ( L2094, L2775 );
inv U264 ( L216, L217 );
and2 U265 ( L2106, L1253, L550 );
and2 U266 ( L567, L1256, L552 );
buffer U267 ( L558, L325 );
or2 U268 ( L881, L882, L894 );
nand2 U269 ( L2474, L2477, L1498 );
nand2 U270 ( L2482, L2485, L1507 );
nand2 U271 ( L2479, L2486, L1508 );
nand2 U272 ( L2490, L2493, L1516 );
nand2 U273 ( L2487, L2494, L1517 );
nand2 U274 ( L2678, L2681, L1775 );
nand2 U275 ( L2686, L2689, L1784 );
nand2 U276 ( L2683, L2690, L1785 );
nand2 U277 ( L2694, L2697, L1793 );
nand2 U278 ( L2691, L2698, L1794 );
nand2 U279 ( L2464, L2467, L2469 );
nand2 U280 ( L2461, L2468, L2470 );
nand2 U281 ( L2498, L2501, L2503 );
nand2 U282 ( L2495, L2502, L2504 );
nand2 U283 ( L2508, L2511, L2513 );
nand2 U284 ( L2505, L2512, L2514 );
nand2 U285 ( L2702, L2705, L2707 );
nand2 U286 ( L2699, L2706, L2708 );
inv U287 ( L558, L261 );
inv U288 ( L550, L551 );
inv U289 ( L552, L553 );
and3 U290 ( L93, L784, L807, L818 );
and3 U291 ( L55, L772, L807, L819 );
and3 U292 ( L67, L784, L795, L820 );
and3 U293 ( L81, L784, L807, L822 );
and3 U294 ( L43, L772, L807, L823 );
and3 U295 ( L56, L784, L795, L824 );
and3 U296 ( L92, L784, L807, L826 );
and3 U297 ( L54, L772, L807, L827 );
and3 U298 ( L66, L784, L795, L828 );
and3 U299 ( L91, L784, L807, L830 );
and3 U300 ( L53, L772, L807, L831 );
and3 U301 ( L65, L784, L795, L832 );
and3 U302 ( L90, L784, L807, L834 );
and3 U303 ( L52, L772, L807, L835 );
and3 U304 ( L64, L784, L795, L836 );
and3 U305 ( L89, L1273, L1296, L1307 );
and3 U306 ( L51, L1261, L1296, L1308 );
and3 U307 ( L63, L1273, L1284, L1309 );
and3 U308 ( L88, L1273, L1296, L1311 );
and3 U309 ( L50, L1261, L1296, L1312 );
and3 U310 ( L62, L1273, L1284, L1313 );
and3 U311 ( L87, L1273, L1296, L1315 );
and3 U312 ( L49, L1261, L1296, L1316 );
and2 U313 ( L1273, L1284, L1317 );
and3 U314 ( L86, L1273, L1296, L1319 );
and3 U315 ( L48, L1261, L1296, L1320 );
and3 U316 ( L61, L1273, L1284, L1321 );
and3 U317 ( L85, L1273, L1296, L1323 );
and3 U318 ( L47, L1261, L1296, L1324 );
and3 U319 ( L60, L1273, L1284, L1325 );
and3 U320 ( L138, L1406, L1430, L1441 );
and3 U321 ( L102, L1394, L1430, L1442 );
and3 U322 ( L126, L1406, L1418, L1443 );
and3 U323 ( L137, L1406, L1430, L1445 );
and3 U324 ( L101, L1394, L1430, L1446 );
and3 U325 ( L125, L1406, L1418, L1447 );
and3 U326 ( L136, L1406, L1430, L1449 );
and3 U327 ( L100, L1394, L1430, L1450 );
and3 U328 ( L124, L1406, L1418, L1451 );
and3 U329 ( L135, L1406, L1430, L1453 );
and3 U330 ( L99, L1394, L1430, L1454 );
and3 U331 ( L123, L1406, L1418, L1455 );
and2 U332 ( L1406, L1430, L1457 );
and2 U333 ( L1394, L1430, L1458 );
and2 U334 ( L1406, L1418, L1459 );
inv U335 ( L1477, L1481 );
inv U336 ( L1486, L1490 );
nand2 U337 ( L1498, L1499, L1500 );
nand2 U338 ( L1507, L1508, L1509 );
nand2 U339 ( L1516, L1517, L1518 );
buffer U340 ( L1495, L1521 );
buffer U341 ( L1495, L1525 );
inv U342 ( L2551, L2557 );
inv U343 ( L2559, L2565 );
inv U344 ( L2567, L2573 );
inv U345 ( L2575, L2581 );
inv U346 ( L2583, L2589 );
inv U347 ( L2591, L2597 );
inv U348 ( L2599, L2605 );
inv U349 ( L2607, L2613 );
inv U350 ( L2615, L2621 );
inv U351 ( L2623, L2629 );
and3 U352 ( L142, L1643, L1667, L1678 );
and3 U353 ( L106, L1631, L1667, L1679 );
and3 U354 ( L130, L1643, L1655, L1680 );
and3 U355 ( L131, L1643, L1667, L1682 );
and3 U356 ( L95, L1631, L1667, L1683 );
and3 U357 ( L119, L1643, L1655, L1684 );
and3 U358 ( L141, L1643, L1667, L1686 );
and3 U359 ( L105, L1631, L1667, L1687 );
and3 U360 ( L129, L1643, L1655, L1688 );
and3 U361 ( L140, L1643, L1667, L1690 );
and3 U362 ( L104, L1631, L1667, L1691 );
and3 U363 ( L128, L1643, L1655, L1692 );
and3 U364 ( L139, L1643, L1667, L1694 );
and3 U365 ( L103, L1631, L1667, L1695 );
and3 U366 ( L127, L1643, L1655, L1696 );
and2 U367 ( L19, L1716, L1734 );
and2 U368 ( L4, L1716, L1736 );
and2 U369 ( L20, L1716, L1738 );
and2 U370 ( L5, L1716, L1740 );
and2 U371 ( L21, L1728, L1742 );
and2 U372 ( L22, L1728, L1744 );
and2 U373 ( L23, L1728, L1746 );
and2 U374 ( L6, L1728, L1748 );
and2 U375 ( L24, L1728, L1750 );
nand2 U376 ( L1775, L1776, L1777 );
nand2 U377 ( L1784, L1785, L1786 );
nand2 U378 ( L1793, L1794, L1795 );
and2 U379 ( L25, L2007, L2023 );
and2 U380 ( L32, L2007, L2025 );
and2 U381 ( L26, L2007, L2027 );
and2 U382 ( L33, L2007, L2029 );
and2 U383 ( L27, L2018, L2031 );
and2 U384 ( L34, L2018, L2033 );
and2 U385 ( L35, L2018, L2035 );
and2 U386 ( L28, L2018, L2037 );
inv U387 ( L2735, L2741 );
inv U388 ( L2743, L2749 );
inv U389 ( L2751, L2757 );
inv U390 ( L2759, L2765 );
inv U391 ( L2767, L2773 );
inv U392 ( L2775, L2781 );
nand2 U393 ( L2469, L2470, L2515 );
inv U394 ( L2518, L2522 );
nand2 U395 ( L2513, L2514, L2525 );
nand2 U396 ( L2503, L2504, L2528 );
nand2 U397 ( L2707, L2708, L2730 );
and2 U398 ( L551, L553, L554 );
or4 U399 ( L818, L819, L820, L821, L838 );
or4 U400 ( L822, L823, L824, L825, L841 );
or4 U401 ( L826, L827, L828, L829, L846 );
or4 U402 ( L830, L831, L832, L833, L854 );
or4 U403 ( L834, L835, L836, L837, L857 );
or4 U404 ( L1307, L1308, L1309, L1310, L1327 );
or4 U405 ( L1311, L1312, L1313, L1314, L1329 );
or4 U406 ( L1315, L1316, L1317, L1318, L1331 );
or4 U407 ( L1319, L1320, L1321, L1322, L1333 );
or4 U408 ( L1323, L1324, L1325, L1326, L1335 );
or4 U409 ( L1441, L1442, L1443, L1444, L1461 );
or4 U410 ( L1445, L1446, L1447, L1448, L1464 );
or4 U411 ( L1449, L1450, L1451, L1452, L1467 );
or4 U412 ( L1453, L1454, L1455, L1456, L1470 );
or4 U413 ( L1457, L1458, L1459, L1460, L1473 );
or4 U414 ( L1682, L1683, L1684, L1685, L1698 );
or4 U415 ( L1686, L1687, L1688, L1689, L1701 );
or4 U416 ( L1690, L1691, L1692, L1693, L1704 );
or4 U417 ( L1694, L1695, L1696, L1697, L1707 );
or4 U418 ( L1678, L1679, L1680, L1681, L2634 );
buffer U419 ( L554, L319 );
inv U420 ( L1500, L1504 );
inv U421 ( L1509, L1513 );
inv U422 ( L1521, L1524 );
inv U423 ( L1525, L1528 );
buffer U424 ( L1518, L1529 );
buffer U425 ( L1518, L1533 );
and3 U426 ( L1486, L1477, L1521, L1538 );
and3 U427 ( L1490, L1481, L1525, L1541 );
inv U428 ( L1777, L1781 );
inv U429 ( L1786, L1790 );
buffer U430 ( L1795, L1806 );
buffer U431 ( L1795, L1810 );
inv U432 ( L2730, L2734 );
inv U433 ( L2515, L2521 );
nand2 U434 ( L2515, L2522, L2524 );
inv U435 ( L2525, L2531 );
inv U436 ( L2528, L2532 );
and2 U437 ( L838, L860, L144 );
and2 U438 ( L846, L860, L147 );
and2 U439 ( L841, L860, L152 );
inv U440 ( L1464, L160 );
inv U441 ( L1467, L162 );
inv U442 ( L1461, L164 );
inv U443 ( L1329, L166 );
inv U444 ( L1327, L168 );
inv U445 ( L857, L171 );
and4 U446 ( L480, L483, L36, L554, L175 );
and4 U447 ( L480, L483, L554, L547, L187 );
buffer U448 ( L838, L516 );
inv U449 ( L846, L852 );
and2 U450 ( L841, L875, L885 );
and2 U451 ( L846, L875, L887 );
and2 U452 ( L1327, L868, L893 );
inv U453 ( L838, L1028 );
inv U454 ( L841, L1031 );
inv U455 ( L846, L1035 );
buffer U456 ( L854, L1041 );
buffer U457 ( L857, L1049 );
buffer U458 ( L1327, L1057 );
buffer U459 ( L1329, L1060 );
buffer U460 ( L1331, L1066 );
buffer U461 ( L1333, L1072 );
buffer U462 ( L1335, L1078 );
nand2 U463 ( L2099, L1470, L1213 );
nand2 U464 ( L2103, L1473, L1218 );
buffer U465 ( L1704, L1250 );
and2 U466 ( L1461, L1385, L1387 );
inv U467 ( L1464, L1389 );
and3 U468 ( L1481, L1486, L1524, L1537 );
and3 U469 ( L1477, L1490, L1528, L1540 );
and2 U470 ( L841, L1710, L1735 );
and2 U471 ( L846, L1710, L1737 );
and2 U472 ( L854, L1710, L1739 );
and2 U473 ( L857, L1710, L1741 );
and2 U474 ( L1327, L1721, L1743 );
and2 U475 ( L1329, L1721, L1745 );
and2 U476 ( L1331, L1721, L1747 );
and2 U477 ( L1333, L1721, L1749 );
and2 U478 ( L1335, L1721, L1751 );
inv U479 ( L2634, L2638 );
and2 U480 ( L1698, L2001, L2024 );
and2 U481 ( L1701, L2001, L2026 );
and2 U482 ( L1704, L2001, L2028 );
and2 U483 ( L1707, L2001, L2030 );
and2 U484 ( L1461, L2012, L2032 );
and2 U485 ( L1464, L2012, L2034 );
and2 U486 ( L1467, L2012, L2036 );
and2 U487 ( L1470, L2012, L2038 );
buffer U488 ( L841, L2154 );
nand2 U489 ( L2518, L2521, L2523 );
nand2 U490 ( L2528, L2531, L2533 );
nand2 U491 ( L2525, L2532, L2534 );
buffer U492 ( L1698, L2631 );
buffer U493 ( L1704, L2639 );
buffer U494 ( L1701, L2642 );
buffer U495 ( L1461, L2647 );
buffer U496 ( L1707, L2650 );
buffer U497 ( L1467, L2655 );
buffer U498 ( L1464, L2658 );
buffer U499 ( L1473, L2665 );
buffer U500 ( L1470, L2668 );
or2 U501 ( L865, L152, L153 );
inv U502 ( L175, L176 );
inv U503 ( L187, L188 );
buffer U504 ( L1041, L299 );
buffer U505 ( L1049, L301 );
buffer U506 ( L1057, L286 );
buffer U507 ( L1060, L303 );
buffer U508 ( L1066, L288 );
buffer U509 ( L1072, L305 );
buffer U510 ( L1078, L290 );
inv U511 ( L1529, L1532 );
inv U512 ( L1533, L1536 );
nor2 U513 ( L1537, L1538, L1539 );
nor2 U514 ( L1540, L1541, L1542 );
and3 U515 ( L1509, L1500, L1529, L1544 );
and3 U516 ( L1513, L1504, L1533, L1547 );
or2 U517 ( L2037, L2038, L2065 );
inv U518 ( L1806, L1809 );
inv U519 ( L1810, L1813 );
and3 U520 ( L1786, L1777, L1806, L1821 );
and3 U521 ( L1790, L1781, L1810, L1824 );
nand2 U522 ( L2523, L2524, L2538 );
nand2 U523 ( L2533, L2534, L2546 );
or2 U524 ( L1734, L1735, L2554 );
or2 U525 ( L1736, L1737, L2562 );
or2 U526 ( L1738, L1739, L2570 );
or2 U527 ( L1740, L1741, L2578 );
or2 U528 ( L1742, L1743, L2586 );
or2 U529 ( L1744, L1745, L2594 );
or2 U530 ( L1746, L1747, L2602 );
or2 U531 ( L1748, L1749, L2610 );
or2 U532 ( L1750, L1751, L2618 );
or2 U533 ( L2023, L2024, L2626 );
or2 U534 ( L2025, L2026, L2738 );
or2 U535 ( L2027, L2028, L2746 );
or2 U536 ( L2029, L2030, L2754 );
or2 U537 ( L2031, L2032, L2762 );
or2 U538 ( L2033, L2034, L2770 );
or2 U539 ( L2035, L2036, L2778 );
and3 U540 ( L1389, L1387, L40, L456 );
inv U541 ( L1387, L466 );
nand2 U542 ( L560, L852, L562 );
and2 U543 ( L516, L875, L883 );
and2 U544 ( L1049, L868, L889 );
and2 U545 ( L1041, L875, L891 );
inv U546 ( L1041, L1043 );
inv U547 ( L1049, L1051 );
inv U548 ( L1060, L1062 );
inv U549 ( L1066, L1068 );
inv U550 ( L1072, L1074 );
inv U551 ( L1078, L1080 );
and2 U552 ( L2099, L1213, L1225 );
and2 U553 ( L1213, L1470, L1227 );
and2 U554 ( L2103, L1218, L1232 );
and2 U555 ( L1218, L1473, L1234 );
and3 U556 ( L1504, L1509, L1532, L1543 );
and3 U557 ( L1500, L1513, L1536, L1546 );
inv U558 ( L2631, L2637 );
nand2 U559 ( L2631, L2638, L1753 );
inv U560 ( L2639, L2645 );
inv U561 ( L2642, L2646 );
inv U562 ( L2647, L2653 );
inv U563 ( L2650, L2654 );
and3 U564 ( L1781, L1786, L1809, L1820 );
and3 U565 ( L1777, L1790, L1813, L1823 );
buffer U566 ( L1031, L2107 );
buffer U567 ( L1028, L2110 );
buffer U568 ( L1035, L2118 );
inv U569 ( L1057, L2123 );
inv U570 ( L852, L2151 );
inv U571 ( L2154, L2158 );
buffer U572 ( L1031, L2161 );
buffer U573 ( L1028, L2164 );
buffer U574 ( L1035, L2172 );
buffer U575 ( L516, L2235 );
buffer U576 ( L1035, L2262 );
buffer U577 ( L1035, L2350 );
nand2 U578 ( L1542, L1539, L2535 );
inv U579 ( L2655, L2661 );
inv U580 ( L2658, L2662 );
inv U581 ( L2665, L2671 );
inv U582 ( L2668, L2672 );
and3 U583 ( L40, L1389, L466, L468 );
or2 U584 ( L887, L889, L897 );
or2 U585 ( L891, L893, L898 );
or2 U586 ( L1225, L1227, L1228 );
or2 U587 ( L1232, L1234, L1235 );
nor2 U588 ( L1543, L1544, L1545 );
nor2 U589 ( L1546, L1547, L1548 );
inv U590 ( L2538, L2542 );
inv U591 ( L2546, L2550 );
nand2 U592 ( L2554, L2557, L1561 );
inv U593 ( L2554, L2558 );
nand2 U594 ( L2562, L2565, L1565 );
inv U595 ( L2562, L2566 );
nand2 U596 ( L2570, L2573, L1569 );
inv U597 ( L2570, L2574 );
nand2 U598 ( L2578, L2581, L1573 );
inv U599 ( L2578, L2582 );
nand2 U600 ( L2586, L2589, L1577 );
inv U601 ( L2586, L2590 );
nand2 U602 ( L2594, L2597, L1581 );
inv U603 ( L2594, L2598 );
nand2 U604 ( L2602, L2605, L1585 );
inv U605 ( L2602, L2606 );
nand2 U606 ( L2610, L2613, L1589 );
inv U607 ( L2610, L2614 );
nand2 U608 ( L2618, L2621, L1593 );
inv U609 ( L2618, L2622 );
nand2 U610 ( L2626, L2629, L1597 );
inv U611 ( L2626, L2630 );
nand2 U612 ( L2634, L2637, L1752 );
nand2 U613 ( L2642, L2645, L1761 );
nand2 U614 ( L2639, L2646, L1762 );
nand2 U615 ( L2650, L2653, L1770 );
nand2 U616 ( L2647, L2654, L1771 );
nor2 U617 ( L1820, L1821, L1822 );
nor2 U618 ( L1823, L1824, L1825 );
nand2 U619 ( L2738, L2741, L2039 );
inv U620 ( L2738, L2742 );
nand2 U621 ( L2746, L2749, L2043 );
inv U622 ( L2746, L2750 );
nand2 U623 ( L2754, L2757, L2047 );
inv U624 ( L2754, L2758 );
nand2 U625 ( L2762, L2765, L2051 );
inv U626 ( L2762, L2766 );
nand2 U627 ( L2770, L2773, L2055 );
inv U628 ( L2770, L2774 );
nand2 U629 ( L2778, L2781, L2059 );
inv U630 ( L2778, L2782 );
nand2 U631 ( L2658, L2661, L2663 );
nand2 U632 ( L2655, L2662, L2664 );
nand2 U633 ( L2668, L2671, L2673 );
nand2 U634 ( L2665, L2672, L2674 );
and2 U635 ( L562, L865, L146 );
inv U636 ( L456, L462 );
inv U637 ( L2107, L2113 );
inv U638 ( L2110, L2114 );
inv U639 ( L2118, L2122 );
inv U640 ( L2123, L2129 );
buffer U641 ( L562, L592 );
inv U642 ( L2161, L2167 );
inv U643 ( L2164, L2168 );
inv U644 ( L2172, L2176 );
inv U645 ( L2235, L2241 );
inv U646 ( L2262, L2266 );
inv U647 ( L456, L743 );
buffer U648 ( L456, L749 );
and2 U649 ( L562, L868, L886 );
buffer U650 ( L897, L284 );
buffer U651 ( L897, L321 );
buffer U652 ( L898, L297 );
buffer U653 ( L898, L280 );
buffer U654 ( L456, L995 );
inv U655 ( L456, L1006 );
nand2 U656 ( L2535, L2542, L1550 );
inv U657 ( L2350, L2354 );
inv U658 ( L2535, L2541 );
nand2 U659 ( L2551, L2558, L1562 );
nand2 U660 ( L2559, L2566, L1566 );
nand2 U661 ( L2567, L2574, L1570 );
nand2 U662 ( L2575, L2582, L1574 );
nand2 U663 ( L2583, L2590, L1578 );
nand2 U664 ( L2591, L2598, L1582 );
nand2 U665 ( L2599, L2606, L1586 );
nand2 U666 ( L2607, L2614, L1590 );
nand2 U667 ( L2615, L2622, L1594 );
nand2 U668 ( L2623, L2630, L1598 );
nand2 U669 ( L1752, L1753, L1754 );
nand2 U670 ( L1761, L1762, L1763 );
nand2 U671 ( L1770, L1771, L1772 );
nand2 U672 ( L2735, L2742, L2040 );
nand2 U673 ( L2743, L2750, L2044 );
nand2 U674 ( L2751, L2758, L2048 );
nand2 U675 ( L2759, L2766, L2052 );
nand2 U676 ( L2767, L2774, L2056 );
nand2 U677 ( L2775, L2782, L2060 );
buffer U678 ( L1043, L2115 );
buffer U679 ( L1051, L2126 );
buffer U680 ( L1068, L2131 );
buffer U681 ( L1062, L2134 );
buffer U682 ( L1080, L2141 );
buffer U683 ( L1074, L2144 );
inv U684 ( L2151, L2157 );
nand2 U685 ( L2151, L2158, L2160 );
buffer U686 ( L1043, L2169 );
buffer U687 ( L1068, L2177 );
buffer U688 ( L1062, L2180 );
buffer U689 ( L1080, L2187 );
buffer U690 ( L1074, L2190 );
inv U691 ( L562, L2207 );
buffer U692 ( L1043, L2254 );
buffer U693 ( L1051, L2334 );
buffer U694 ( L1043, L2342 );
buffer U695 ( L1051, L2422 );
nand2 U696 ( L1548, L1545, L2543 );
nand2 U697 ( L2673, L2674, L2709 );
nand2 U698 ( L2663, L2664, L2712 );
nand2 U699 ( L1825, L1822, L2727 );
or2 U700 ( L146, L147, L148 );
nand2 U701 ( L2110, L2113, L569 );
nand2 U702 ( L2107, L2114, L570 );
nand2 U703 ( L2164, L2167, L599 );
nand2 U704 ( L2161, L2168, L600 );
or2 U705 ( L885, L886, L896 );
nand2 U706 ( L2538, L2541, L1549 );
inv U707 ( L1228, L1243 );
inv U708 ( L1235, L1245 );
buffer U709 ( L468, L1257 );
buffer U710 ( L468, L1258 );
nand2 U711 ( L1561, L1562, L1563 );
nand2 U712 ( L1565, L1566, L1567 );
nand2 U713 ( L1569, L1570, L1571 );
nand2 U714 ( L1573, L1574, L1575 );
nand2 U715 ( L1577, L1578, L1579 );
nand2 U716 ( L1581, L1582, L1583 );
nand2 U717 ( L1585, L1586, L1587 );
nand2 U718 ( L1589, L1590, L1591 );
nand2 U719 ( L1593, L1594, L1595 );
nand2 U720 ( L1597, L1598, L1599 );
nand2 U721 ( L2039, L2040, L2041 );
nand2 U722 ( L2043, L2044, L2045 );
nand2 U723 ( L2047, L2048, L2049 );
nand2 U724 ( L2051, L2052, L2053 );
nand2 U725 ( L2055, L2056, L2057 );
nand2 U726 ( L2059, L2060, L2061 );
nand2 U727 ( L2154, L2157, L2159 );
buffer U728 ( L462, L475 );
and2 U729 ( L1078, L743, L490 );
and2 U730 ( L1698, L743, L496 );
and2 U731 ( L1701, L743, L502 );
and2 U732 ( L1250, L743, L508 );
and2 U733 ( L1057, L749, L765 );
and2 U734 ( L1060, L749, L769 );
nand2 U735 ( L569, L570, L571 );
inv U736 ( L2115, L2121 );
nand2 U737 ( L2115, L2122, L579 );
nand2 U738 ( L2126, L2129, L587 );
inv U739 ( L2126, L2130 );
inv U740 ( L592, L596 );
nand2 U741 ( L599, L600, L601 );
inv U742 ( L2169, L2175 );
nand2 U743 ( L2169, L2176, L609 );
inv U744 ( L2254, L2258 );
and2 U745 ( L1057, L995, L1014 );
and2 U746 ( L1060, L995, L1018 );
and2 U747 ( L1078, L1006, L717 );
and2 U748 ( L1698, L1006, L723 );
and2 U749 ( L1701, L1006, L729 );
and2 U750 ( L1250, L1006, L735 );
inv U751 ( L749, L753 );
buffer U752 ( L896, L282 );
buffer U753 ( L896, L323 );
inv U754 ( L2334, L2338 );
inv U755 ( L995, L999 );
nand2 U756 ( L1549, L1550, L1091 );
inv U757 ( L2342, L2346 );
inv U758 ( L2422, L2426 );
buffer U759 ( L462, L1337 );
inv U760 ( L2543, L2549 );
nand2 U761 ( L2543, L2550, L1552 );
inv U762 ( L1599, L1600 );
inv U763 ( L1595, L1596 );
inv U764 ( L1591, L1592 );
inv U765 ( L1587, L1588 );
inv U766 ( L1583, L1584 );
inv U767 ( L1579, L1580 );
inv U768 ( L1575, L1576 );
inv U769 ( L1571, L1572 );
inv U770 ( L1567, L1568 );
inv U771 ( L1563, L1564 );
inv U772 ( L2061, L2062 );
inv U773 ( L2057, L2058 );
inv U774 ( L2053, L2054 );
inv U775 ( L2049, L2050 );
inv U776 ( L2045, L2046 );
inv U777 ( L2041, L2042 );
inv U778 ( L1754, L1758 );
inv U779 ( L1763, L1767 );
buffer U780 ( L1772, L1798 );
buffer U781 ( L1772, L1802 );
inv U782 ( L2727, L2733 );
nand2 U783 ( L2727, L2734, L1829 );
inv U784 ( L2131, L2137 );
inv U785 ( L2134, L2138 );
inv U786 ( L2141, L2147 );
inv U787 ( L2144, L2148 );
inv U788 ( L2177, L2183 );
inv U789 ( L2180, L2184 );
inv U790 ( L2187, L2193 );
inv U791 ( L2190, L2194 );
nand2 U792 ( L2159, L2160, L2210 );
inv U793 ( L2207, L2213 );
inv U794 ( L2709, L2715 );
inv U795 ( L2712, L2716 );
and2 U796 ( L1235, L1245, L1094 );
and2 U797 ( L1228, L1243, L1096 );
nand2 U798 ( L2118, L2121, L578 );
nand2 U799 ( L2123, L2130, L588 );
nand2 U800 ( L2172, L2175, L608 );
buffer U801 ( L1257, L742 );
buffer U802 ( L1257, L1005 );
inv U803 ( L1091, L1092 );
nand2 U804 ( L2546, L2549, L1551 );
and5 U805 ( L1600, L1596, L1592, L1588, L1584, L1554 );
and5 U806 ( L1580, L1576, L1572, L1568, L1564, L1555 );
and2 U807 ( L2065, L2062, L1557 );
and5 U808 ( L2058, L2054, L2050, L2046, L2042, L1558 );
nand2 U809 ( L2730, L2733, L1828 );
buffer U810 ( L1258, L1845 );
buffer U811 ( L1258, L1907 );
nand2 U812 ( L2134, L2137, L2139 );
nand2 U813 ( L2131, L2138, L2140 );
nand2 U814 ( L2144, L2147, L2149 );
nand2 U815 ( L2141, L2148, L2150 );
nand2 U816 ( L2180, L2183, L2185 );
nand2 U817 ( L2177, L2184, L2186 );
nand2 U818 ( L2190, L2193, L2195 );
nand2 U819 ( L2187, L2194, L2196 );
nand2 U820 ( L2712, L2715, L2717 );
nand2 U821 ( L2709, L2716, L2718 );
or2 U822 ( L1094, L1245, L154 );
or2 U823 ( L1096, L1243, L155 );
and2 U824 ( L1057, L753, L763 );
and2 U825 ( L1060, L753, L767 );
and2 U826 ( L1066, L753, L531 );
and2 U827 ( L1072, L753, L537 );
inv U828 ( L571, L575 );
nand2 U829 ( L578, L579, L580 );
nand2 U830 ( L587, L588, L589 );
inv U831 ( L601, L605 );
nand2 U832 ( L608, L609, L610 );
and2 U833 ( L1057, L999, L1012 );
and2 U834 ( L1060, L999, L1016 );
and2 U835 ( L1066, L999, L705 );
and2 U836 ( L1072, L999, L711 );
and2 U837 ( L1092, L14, L1093 );
buffer U838 ( L475, L1355 );
nand2 U839 ( L1551, L1552, L1553 );
and2 U840 ( L1554, L1555, L1556 );
and2 U841 ( L1557, L1558, L1559 );
buffer U842 ( L1337, L1601 );
inv U843 ( L1798, L1801 );
inv U844 ( L1802, L1805 );
and3 U845 ( L1763, L1754, L1798, L1815 );
and3 U846 ( L1767, L1758, L1802, L1818 );
nand2 U847 ( L1828, L1829, L1830 );
buffer U848 ( L475, L1836 );
buffer U849 ( L475, L1850 );
buffer U850 ( L1337, L1898 );
buffer U851 ( L1337, L1912 );
nand2 U852 ( L2149, L2150, L2197 );
nand2 U853 ( L2139, L2140, L2200 );
inv U854 ( L2210, L2214 );
nand2 U855 ( L2210, L2213, L2215 );
nand2 U856 ( L2195, L2196, L2217 );
nand2 U857 ( L2185, L2186, L2220 );
nand2 U858 ( L2717, L2718, L2722 );
nand2 U859 ( L154, L155, L156 );
and2 U860 ( L490, L742, L492 );
and2 U861 ( L496, L742, L498 );
and2 U862 ( L502, L742, L504 );
and2 U863 ( L508, L742, L510 );
or2 U864 ( L763, L765, L519 );
or2 U865 ( L767, L769, L525 );
and2 U866 ( L531, L748, L533 );
and2 U867 ( L537, L748, L539 );
or2 U868 ( L1012, L1014, L693 );
or2 U869 ( L1016, L1018, L699 );
and2 U870 ( L705, L994, L707 );
and2 U871 ( L711, L994, L713 );
and2 U872 ( L717, L1005, L719 );
and2 U873 ( L723, L1005, L725 );
and2 U874 ( L729, L1005, L731 );
and2 U875 ( L735, L1005, L737 );
buffer U876 ( L1093, L401 );
and3 U877 ( L1556, L1559, L894, L1560 );
and3 U878 ( L1758, L1763, L1801, L1814 );
and3 U879 ( L1754, L1767, L1805, L1817 );
nand2 U880 ( L2207, L2214, L2216 );
inv U881 ( L1830, L227 );
inv U882 ( L1553, L229 );
inv U883 ( L492, L493 );
inv U884 ( L498, L499 );
inv U885 ( L504, L505 );
inv U886 ( L510, L511 );
and2 U887 ( L519, L748, L521 );
and2 U888 ( L525, L748, L527 );
inv U889 ( L533, L534 );
inv U890 ( L539, L540 );
inv U891 ( L580, L584 );
buffer U892 ( L589, L613 );
buffer U893 ( L589, L617 );
buffer U894 ( L610, L621 );
buffer U895 ( L610, L625 );
and2 U896 ( L1344, L1355, L676 );
and2 U897 ( L693, L994, L695 );
and2 U898 ( L699, L994, L701 );
inv U899 ( L707, L708 );
inv U900 ( L713, L714 );
inv U901 ( L719, L720 );
inv U902 ( L725, L726 );
inv U903 ( L731, L732 );
inv U904 ( L737, L738 );
inv U905 ( L1093, L1087 );
and2 U906 ( L1344, L1601, L1108 );
inv U907 ( L1355, L1361 );
and2 U908 ( L1351, L1355, L1369 );
and2 U909 ( L1959, L1355, L1373 );
and2 U910 ( L1964, L1355, L1377 );
buffer U911 ( L1560, L311 );
inv U912 ( L1601, L1607 );
and2 U913 ( L1351, L1601, L1615 );
and2 U914 ( L1959, L1601, L1619 );
and2 U915 ( L1964, L1601, L1623 );
nor2 U916 ( L1814, L1815, L1816 );
nor2 U917 ( L1817, L1818, L1819 );
inv U918 ( L2722, L2726 );
inv U919 ( L1836, L1842 );
and2 U920 ( L1969, L1836, L1858 );
and2 U921 ( L1974, L1836, L1863 );
and2 U922 ( L1979, L1836, L1866 );
and2 U923 ( L1984, L1836, L1868 );
and2 U924 ( L1989, L1850, L1870 );
and2 U925 ( L1994, L1850, L1872 );
and2 U926 ( L1999, L1850, L1874 );
and2 U927 ( L2070, L1850, L1876 );
inv U928 ( L1898, L1904 );
and2 U929 ( L1969, L1898, L1920 );
and2 U930 ( L1974, L1898, L1925 );
and2 U931 ( L1979, L1898, L1928 );
and2 U932 ( L1984, L1898, L1930 );
and2 U933 ( L1989, L1912, L1932 );
and2 U934 ( L1994, L1912, L1934 );
and2 U935 ( L1999, L1912, L1936 );
and2 U936 ( L2070, L1912, L1938 );
inv U937 ( L2197, L2203 );
inv U938 ( L2200, L2204 );
inv U939 ( L2217, L2223 );
inv U940 ( L2220, L2224 );
nand2 U941 ( L2215, L2216, L2238 );
inv U942 ( L1560, L150 );
inv U943 ( L521, L522 );
inv U944 ( L527, L528 );
inv U945 ( L695, L696 );
inv U946 ( L701, L702 );
and2 U947 ( L1866, L1831, L1881 );
and2 U948 ( L1868, L1831, L1883 );
and2 U949 ( L1870, L1845, L1885 );
and2 U950 ( L1872, L1845, L1887 );
and2 U951 ( L1874, L1845, L1889 );
and2 U952 ( L1876, L1845, L1891 );
and2 U953 ( L1928, L1893, L1943 );
and2 U954 ( L1930, L1893, L1945 );
and2 U955 ( L1932, L1907, L1947 );
and2 U956 ( L1934, L1907, L1949 );
and2 U957 ( L1936, L1907, L1951 );
and2 U958 ( L1938, L1907, L1953 );
nand2 U959 ( L2200, L2203, L2205 );
nand2 U960 ( L2197, L2204, L2206 );
nand2 U961 ( L2220, L2223, L2225 );
nand2 U962 ( L2217, L2224, L2226 );
nand2 U963 ( L1819, L1816, L2719 );
inv U964 ( L613, L616 );
inv U965 ( L617, L620 );
inv U966 ( L621, L624 );
inv U967 ( L625, L628 );
and3 U968 ( L580, L571, L613, L630 );
and3 U969 ( L584, L575, L617, L633 );
and3 U970 ( L601, L592, L621, L636 );
and3 U971 ( L605, L596, L625, L639 );
nand2 U972 ( L2238, L2241, L645 );
inv U973 ( L2238, L2242 );
and2 U974 ( L1999, L1361, L675 );
and2 U975 ( L1999, L1607, L1107 );
and2 U976 ( L2070, L1361, L1368 );
and2 U977 ( L2076, L1361, L1371 );
and2 U978 ( L2082, L1361, L1375 );
and2 U979 ( L2070, L1607, L1614 );
and2 U980 ( L2076, L1607, L1617 );
and2 U981 ( L2082, L1607, L1621 );
and2 U982 ( L2088, L1842, L1856 );
and2 U983 ( L2094, L1842, L1861 );
and2 U984 ( L2088, L1904, L1918 );
and2 U985 ( L2094, L1904, L1923 );
nand2 U986 ( L2205, L2206, L2230 );
nand2 U987 ( L2225, L2226, L2246 );
buffer U988 ( L511, L2270 );
buffer U989 ( L505, L2278 );
buffer U990 ( L499, L2286 );
buffer U991 ( L493, L2294 );
buffer U992 ( L540, L2302 );
buffer U993 ( L534, L2310 );
buffer U994 ( L738, L2358 );
buffer U995 ( L732, L2366 );
buffer U996 ( L726, L2374 );
buffer U997 ( L720, L2382 );
buffer U998 ( L714, L2390 );
buffer U999 ( L708, L2398 );
and3 U1000 ( L575, L580, L616, L629 );
and3 U1001 ( L571, L584, L620, L632 );
and3 U1002 ( L596, L601, L624, L635 );
and3 U1003 ( L592, L605, L628, L638 );
nand2 U1004 ( L2235, L2242, L646 );
or2 U1005 ( L675, L676, L677 );
nand2 U1006 ( L2719, L2726, L1827 );
and2 U1007 ( L1891, L511, L907 );
and2 U1008 ( L1889, L505, L915 );
and2 U1009 ( L1887, L499, L922 );
and2 U1010 ( L493, L1885, L924 );
and2 U1011 ( L1883, L540, L937 );
and2 U1012 ( L1881, L534, L946 );
or2 U1013 ( L1107, L1108, L1109 );
and2 U1014 ( L1953, L738, L1125 );
and2 U1015 ( L1951, L732, L1133 );
and2 U1016 ( L1949, L726, L1140 );
and2 U1017 ( L720, L1947, L1142 );
and2 U1018 ( L1945, L714, L1155 );
and2 U1019 ( L1943, L708, L1164 );
or2 U1020 ( L1368, L1369, L1378 );
or2 U1021 ( L1371, L1373, L1380 );
or2 U1022 ( L1375, L1377, L1382 );
or2 U1023 ( L1614, L1615, L1624 );
or2 U1024 ( L1617, L1619, L1626 );
or2 U1025 ( L1621, L1623, L1628 );
inv U1026 ( L2719, L2725 );
or2 U1027 ( L1856, L1858, L1859 );
or2 U1028 ( L1861, L1863, L1864 );
or2 U1029 ( L1918, L1920, L1921 );
or2 U1030 ( L1923, L1925, L1926 );
buffer U1031 ( L1891, L2267 );
buffer U1032 ( L1889, L2275 );
buffer U1033 ( L1887, L2283 );
buffer U1034 ( L1885, L2291 );
buffer U1035 ( L1883, L2299 );
buffer U1036 ( L1881, L2307 );
buffer U1037 ( L528, L2318 );
buffer U1038 ( L522, L2326 );
buffer U1039 ( L1953, L2355 );
buffer U1040 ( L1951, L2363 );
buffer U1041 ( L1949, L2371 );
buffer U1042 ( L1947, L2379 );
buffer U1043 ( L1945, L2387 );
buffer U1044 ( L1943, L2395 );
buffer U1045 ( L702, L2406 );
buffer U1046 ( L696, L2414 );
nand2 U1047 ( L645, L646, L647 );
nor2 U1048 ( L629, L630, L631 );
nor2 U1049 ( L632, L633, L634 );
nor2 U1050 ( L635, L636, L637 );
nor2 U1051 ( L638, L639, L640 );
inv U1052 ( L2230, L2234 );
inv U1053 ( L2246, L2250 );
and2 U1054 ( L677, L1031, L679 );
nand2 U1055 ( L2722, L2725, L1826 );
inv U1056 ( L2270, L2274 );
inv U1057 ( L2278, L2282 );
inv U1058 ( L2286, L2290 );
inv U1059 ( L2294, L2298 );
inv U1060 ( L2302, L2306 );
inv U1061 ( L2310, L2314 );
and2 U1062 ( L1109, L1031, L1110 );
inv U1063 ( L2358, L2362 );
inv U1064 ( L2366, L2370 );
inv U1065 ( L2374, L2378 );
inv U1066 ( L2382, L2386 );
inv U1067 ( L2390, L2394 );
inv U1068 ( L2398, L2402 );
and2 U1069 ( L1859, L1831, L1877 );
and2 U1070 ( L1864, L1831, L1879 );
and2 U1071 ( L1921, L1893, L1939 );
and2 U1072 ( L1926, L1893, L1941 );
and2 U1073 ( L647, L865, L143 );
and2 U1074 ( L1380, L1043, L671 );
and2 U1075 ( L1378, L1035, L674 );
nand2 U1076 ( L1826, L1827, L686 );
inv U1077 ( L2267, L2273 );
nand2 U1078 ( L2267, L2274, L900 );
inv U1079 ( L2275, L2281 );
nand2 U1080 ( L2275, L2282, L909 );
inv U1081 ( L2283, L2289 );
nand2 U1082 ( L2283, L2290, L917 );
inv U1083 ( L2291, L2297 );
nand2 U1084 ( L2291, L2298, L926 );
inv U1085 ( L2299, L2305 );
nand2 U1086 ( L2299, L2306, L929 );
inv U1087 ( L2307, L2313 );
nand2 U1088 ( L2307, L2314, L939 );
inv U1089 ( L2318, L2322 );
inv U1090 ( L2326, L2330 );
and2 U1091 ( L1382, L1051, L967 );
and2 U1092 ( L1626, L1043, L1104 );
and2 U1093 ( L1624, L1035, L1106 );
inv U1094 ( L2355, L2361 );
nand2 U1095 ( L2355, L2362, L1118 );
inv U1096 ( L2363, L2369 );
nand2 U1097 ( L2363, L2370, L1127 );
inv U1098 ( L2371, L2377 );
nand2 U1099 ( L2371, L2378, L1135 );
inv U1100 ( L2379, L2385 );
nand2 U1101 ( L2379, L2386, L1144 );
inv U1102 ( L2387, L2393 );
nand2 U1103 ( L2387, L2394, L1147 );
inv U1104 ( L2395, L2401 );
nand2 U1105 ( L2395, L2402, L1157 );
inv U1106 ( L2406, L2410 );
inv U1107 ( L2414, L2418 );
and2 U1108 ( L1628, L1051, L1184 );
nand2 U1109 ( L634, L631, L2227 );
nand2 U1110 ( L640, L637, L2243 );
buffer U1111 ( L1380, L2251 );
buffer U1112 ( L1378, L2259 );
buffer U1113 ( L1382, L2331 );
buffer U1114 ( L1626, L2339 );
buffer U1115 ( L1624, L2347 );
buffer U1116 ( L1628, L2419 );
or2 U1117 ( L143, L144, L145 );
inv U1118 ( L686, L687 );
nand2 U1119 ( L2270, L2273, L899 );
nand2 U1120 ( L2278, L2281, L908 );
nand2 U1121 ( L2286, L2289, L916 );
nand2 U1122 ( L2294, L2297, L925 );
nand2 U1123 ( L2302, L2305, L928 );
nand2 U1124 ( L2310, L2313, L938 );
and2 U1125 ( L1879, L528, L954 );
and2 U1126 ( L1877, L522, L961 );
nand2 U1127 ( L2358, L2361, L1117 );
nand2 U1128 ( L2366, L2369, L1126 );
nand2 U1129 ( L2374, L2377, L1134 );
nand2 U1130 ( L2382, L2385, L1143 );
nand2 U1131 ( L2390, L2393, L1146 );
nand2 U1132 ( L2398, L2401, L1156 );
and2 U1133 ( L1941, L702, L1172 );
and2 U1134 ( L1939, L696, L1179 );
buffer U1135 ( L1879, L2315 );
buffer U1136 ( L1877, L2323 );
buffer U1137 ( L1941, L2403 );
buffer U1138 ( L1939, L2411 );
inv U1139 ( L2227, L2233 );
nand2 U1140 ( L2227, L2234, L642 );
inv U1141 ( L2243, L2249 );
nand2 U1142 ( L2243, L2250, L649 );
inv U1143 ( L2251, L2257 );
nand2 U1144 ( L2251, L2258, L665 );
nand2 U1145 ( L2259, L2266, L684 );
inv U1146 ( L2259, L2265 );
and2 U1147 ( L687, L487, L688 );
nand2 U1148 ( L899, L900, L901 );
nand2 U1149 ( L908, L909, L910 );
nand2 U1150 ( L916, L917, L918 );
nand2 U1151 ( L925, L926, L927 );
nand2 U1152 ( L928, L929, L930 );
nand2 U1153 ( L938, L939, L940 );
inv U1154 ( L2331, L2337 );
nand2 U1155 ( L2331, L2338, L963 );
inv U1156 ( L2339, L2345 );
nand2 U1157 ( L2339, L2346, L1099 );
nand2 U1158 ( L2347, L2354, L1115 );
inv U1159 ( L2347, L2353 );
nand2 U1160 ( L1117, L1118, L1119 );
nand2 U1161 ( L1126, L1127, L1128 );
nand2 U1162 ( L1134, L1135, L1136 );
nand2 U1163 ( L1143, L1144, L1145 );
nand2 U1164 ( L1146, L1147, L1148 );
nand2 U1165 ( L1156, L1157, L1158 );
inv U1166 ( L2419, L2425 );
nand2 U1167 ( L2419, L2426, L1181 );
nand2 U1168 ( L2230, L2233, L641 );
nand2 U1169 ( L2246, L2249, L648 );
nand2 U1170 ( L2254, L2257, L664 );
nand2 U1171 ( L2262, L2265, L683 );
buffer U1172 ( L688, L395 );
inv U1173 ( L2315, L2321 );
nand2 U1174 ( L2315, L2322, L948 );
inv U1175 ( L2323, L2329 );
nand2 U1176 ( L2323, L2330, L956 );
nand2 U1177 ( L2334, L2337, L962 );
nand2 U1178 ( L2342, L2345, L1098 );
nand2 U1179 ( L2350, L2353, L1114 );
inv U1180 ( L2403, L2409 );
nand2 U1181 ( L2403, L2410, L1166 );
inv U1182 ( L2411, L2417 );
nand2 U1183 ( L2411, L2418, L1174 );
nand2 U1184 ( L2422, L2425, L1180 );
nand2 U1185 ( L641, L642, L643 );
nand2 U1186 ( L648, L649, L650 );
nand2 U1187 ( L664, L665, L666 );
nand2 U1188 ( L683, L684, L681 );
inv U1189 ( L688, L690 );
nand2 U1190 ( L2318, L2321, L947 );
nand2 U1191 ( L2326, L2329, L955 );
nand2 U1192 ( L962, L963, L964 );
and4 U1193 ( L910, L927, L918, L901, L968 );
and2 U1194 ( L901, L915, L970 );
and3 U1195 ( L910, L901, L922, L971 );
and4 U1196 ( L918, L901, L924, L910, L972 );
and2 U1197 ( L930, L946, L978 );
and3 U1198 ( L940, L930, L954, L979 );
nand2 U1199 ( L1098, L1099, L1100 );
nand2 U1200 ( L1114, L1115, L1112 );
nand2 U1201 ( L2406, L2409, L1165 );
nand2 U1202 ( L2414, L2417, L1173 );
nand2 U1203 ( L1180, L1181, L1182 );
and4 U1204 ( L1128, L1145, L1136, L1119, L1185 );
and2 U1205 ( L1119, L1133, L1187 );
and3 U1206 ( L1128, L1119, L1140, L1188 );
and4 U1207 ( L1136, L1119, L1142, L1128, L1189 );
and2 U1208 ( L1148, L1164, L1195 );
and3 U1209 ( L1158, L1148, L1172, L1196 );
inv U1210 ( L643, L644 );
and2 U1211 ( L650, L868, L884 );
nand2 U1212 ( L947, L948, L949 );
nand2 U1213 ( L955, L956, L957 );
inv U1214 ( L968, L969 );
or4 U1215 ( L907, L970, L971, L972, L973 );
nand2 U1216 ( L1165, L1166, L1167 );
nand2 U1217 ( L1173, L1174, L1175 );
inv U1218 ( L1185, L1186 );
or4 U1219 ( L1125, L1187, L1188, L1189, L1190 );
and2 U1220 ( L666, L674, L680 );
and3 U1221 ( L681, L666, L679, L682 );
or2 U1222 ( L883, L884, L895 );
and2 U1223 ( L644, L487, L1025 );
and2 U1224 ( L1100, L1106, L1111 );
and3 U1225 ( L1112, L1100, L1110, L1113 );
or3 U1226 ( L671, L680, L682, L685 );
buffer U1227 ( L895, L295 );
buffer U1228 ( L895, L331 );
inv U1229 ( L973, L976 );
and5 U1230 ( L940, L964, L949, L930, L957, L977 );
and4 U1231 ( L949, L930, L961, L940, L980 );
and5 U1232 ( L957, L949, L930, L967, L940, L981 );
buffer U1233 ( L1025, L397 );
or3 U1234 ( L1104, L1111, L1113, L1116 );
inv U1235 ( L1190, L1193 );
and5 U1236 ( L1158, L1182, L1167, L1148, L1175, L1194 );
and4 U1237 ( L1167, L1148, L1179, L1158, L1197 );
and5 U1238 ( L1175, L1167, L1148, L1184, L1158, L1198 );
or5 U1239 ( L937, L978, L979, L980, L981, L982 );
and2 U1240 ( L977, L685, L983 );
nand2 U1241 ( L976, L969, L988 );
inv U1242 ( L1025, L1027 );
or5 U1243 ( L1155, L1195, L1196, L1197, L1198, L1199 );
and2 U1244 ( L1194, L1116, L1200 );
nand2 U1245 ( L1193, L1186, L1205 );
or2 U1246 ( L982, L983, L984 );
and3 U1247 ( L690, L1027, L1830, L1085 );
or2 U1248 ( L1199, L1200, L1201 );
inv U1249 ( L984, L987 );
and2 U1250 ( L988, L984, L990 );
inv U1251 ( L1201, L1204 );
and2 U1252 ( L1205, L1201, L1207 );
and2 U1253 ( L973, L987, L989 );
and2 U1254 ( L1190, L1204, L1206 );
or2 U1255 ( L989, L990, L991 );
or2 U1256 ( L1206, L1207, L1208 );
buffer U1257 ( L1208, L329 );
nand2 U1258 ( L1208, L991, L1221 );
and2 U1259 ( L1208, L1221, L1238 );
and2 U1260 ( L1221, L991, L1239 );
or2 U1261 ( L1238, L1239, L1240 );
inv U1262 ( L1240, L1247 );
and2 U1263 ( L1240, L1247, L471 );
or2 U1264 ( L471, L1247, L473 );
inv U1265 ( L473, L231 );
and3 U1266 ( L1553, L1087, L473, L1088 );
and3 U1267 ( L1085, L1088, L554, L1089 );
buffer U1268 ( L1089, L308 );
inv U1269 ( L1089, L225 );
endmodule
|
Added c2670/c2670high.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 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/****************************************************************************
* *
* VERILOG HIGH-LEVEL DESCRIPTION OF THE ISCAS-85 BENCHMARK CIRCUIT c2670 *
* *
* *
* Written by : Hakan Yalcin (hyalcin@cadence.com) *
* Verified by : Jonathan David Hauke (jhauke@eecs.umich.edu) *
* *
* First created: Jan 14, 1997 *
* Last modified: Oct 20, 1998 *
* *
****************************************************************************/
module Circuit2670 (
in81, in92, in91, in90, in89, in88, in87,
in86, in85, in93, in43, in54, in53, in52, in51,
in50, in49, in48, in47, in55, in56, in66, in65,
in64, in63, in62, in61, in60, in67, in68, in79,
in78, in77, in76, in75, in74, in73, in72, in80,
in131, in141, in140, in139, in138, in137, in136, in135,
in142, in95, in105, in104, in103, in102, in101, in100,
in99, in106, in119, in129, in128, in127, in126, in125,
in124, in123, in130, in107, in117, in116, in115, in114,
in113, in112, in111, in118, in1971, in1966, in1961, in1956,
in1348, in1341, in2090, in2084, in2078, in2072, in2067, in1996,
in1991, in1986, in1981, in1976, in2096, in2100, in2678, in2474,
in2427, in2430, in2451, in2454, in2443, in2446, in2435, in2438,
in24, in6, in23, in22, in21, in5, in20, in4,
in19, in28, in35, in34, in27, in33, in26, in32,
in25, in651, in543, in2105, in2104, in1384, in40, in16,
in29, in11, in8, in37, in14, in44, in132, in82,
in96, in69, in120, in57, in108, in2106, in567, in559,
in860, in868, in452, in2066, in1083, in94, in7, in661,
in1, in2, in3, in15, in36, in483, in169, in174,
in177, in178, in179, in180, in181, in182, in183, in184,
in185, in186, in189, in190, in191, in192, in193, in194,
in195, in196, in197, in198, in199, in200, in201, in202,
in203, in204, in205, in206, in207, in208, in209, in210,
in211, in212, in213, in214, in215, in239, in240, in241,
in242, in243, in244, in245, in246, in247, in248, in249,
in250, in251, in252, in253, in254, in255, in256, in257,
in262, in263, in264, in265, in266, in267, in268, in269,
in270, in271, in272, in273, in274, in275, in276, in277,
in278, in279,
out329, out231, out311, out150, out308, out225, out395,
out397, out227, out229, out401, out319, out325, out261, out220,
out221, out219, out218, out235, out236, out237, out238, out335,
out350, out391, out409, out337, out384, out411, out367, out369,
out173, out295, out331, out145, out148, out282, out323, out284,
out321, out297, out280, out153, out290, out305, out288, out303,
out286, out301, out299, out166, out168, out171, out162, out160,
out164, out156, out223, out217, out234, out259, out176, out188,
out158, out169, out174, out177, out178, out179, out180, out181,
out182, out183, out184, out185, out186, out189, out190, out191,
out192, out193, out194, out195, out196, out197, out198, out199,
out200, out201, out202, out203, out204, out205, out206, out207,
out208, out209, out210, out211, out212, out213, out214, out215,
out239, out240, out241, out242, out243, out244, out245, out246,
out247, out248, out249, out250, out251, out252, out253, out254,
out255, out256, out257, out262, out263, out264, out265, out266,
out267, out268, out269, out270, out271, out272, out273, out274,
out275, out276, out277, out278, out279);
input
in81, in92, in91, in90, in89, in88, in87,
in86, in85, in93, in43, in54, in53, in52, in51,
in50, in49, in48, in47, in55, in56, in66, in65,
in64, in63, in62, in61, in60, in67, in68, in79,
in78, in77, in76, in75, in74, in73, in72, in80,
in131, in141, in140, in139, in138, in137, in136, in135,
in142, in95, in105, in104, in103, in102, in101, in100,
in99, in106, in119, in129, in128, in127, in126, in125,
in124, in123, in130, in107, in117, in116, in115, in114,
in113, in112, in111, in118, in1971, in1966, in1961, in1956,
in1348, in1341, in2090, in2084, in2078, in2072, in2067, in1996,
in1991, in1986, in1981, in1976, in2096, in2100, in2678, in2474,
in2427, in2430, in2451, in2454, in2443, in2446, in2435, in2438,
in24, in6, in23, in22, in21, in5, in20, in4,
in19, in28, in35, in34, in27, in33, in26, in32,
in25, in651, in543, in2105, in2104, in1384, in40, in16,
in29, in11, in8, in37, in14, in44, in132, in82,
in96, in69, in120, in57, in108, in2106, in567, in559,
in860, in868, in452, in2066, in1083, in94, in7, in661,
in1, in2, in3, in15, in36, in483, in169, in174,
in177, in178, in179, in180, in181, in182, in183, in184,
in185, in186, in189, in190, in191, in192, in193, in194,
in195, in196, in197, in198, in199, in200, in201, in202,
in203, in204, in205, in206, in207, in208, in209, in210,
in211, in212, in213, in214, in215, in239, in240, in241,
in242, in243, in244, in245, in246, in247, in248, in249,
in250, in251, in252, in253, in254, in255, in256, in257,
in262, in263, in264, in265, in266, in267, in268, in269,
in270, in271, in272, in273, in274, in275, in276, in277,
in278, in279;
output
out329, out231, out311, out150, out308, out225, out395,
out397, out227, out229, out401, out319, out325, out261, out220,
out221, out219, out218, out235, out236, out237, out238, out335,
out350, out391, out409, out337, out384, out411, out367, out369,
out173, out295, out331, out145, out148, out282, out323, out284,
out321, out297, out280, out153, out290, out305, out288, out303,
out286, out301, out299, out166, out168, out171, out162, out160,
out164, out156, out223, out217, out234, out259, out176, out188,
out158, out169, out174, out177, out178, out179, out180, out181,
out182, out183, out184, out185, out186, out189, out190, out191,
out192, out193, out194, out195, out196, out197, out198, out199,
out200, out201, out202, out203, out204, out205, out206, out207,
out208, out209, out210, out211, out212, out213, out214, out215,
out239, out240, out241, out242, out243, out244, out245, out246,
out247, out248, out249, out250, out251, out252, out253, out254,
out255, out256, out257, out262, out263, out264, out265, out266,
out267, out268, out269, out270, out271, out272, out273, out274,
out275, out276, out277, out278, out279;
/********************************************************/
wire VDD;
assign VDD = 1'b1;
// Inputs/Outputs to TopLevel2670
wire [9:0] A1bus, A2bus, A3bus, A4bus;
wire [9:0] B1bus, B2bus, B3bus, B4bus;
wire [5:0] Y1bus, Y2bus;
wire [3:0] Y3bus;
wire [8:0] Z1bus;
wire [7:0] Z2bus;
wire [11:0] ParTreeIns;
wire ContA0, ContA1, ContB0, ContB1;
wire ContMask0, ContMask1, ContMask2;
wire ContZ0, ContZ1, ContEq;
wire ContPar0, ContPar1, ContPar2, ContPar3;
wire OutYgreaterX, OutYgreaterX_Equal, OutZequalW, OutNot_ZequalW;
wire OutParCheck, OutNot_ParCheck;
wire [7:0] ParChkOuts;
wire [7:0] InTbus, OutTbus;
wire MiscMuxIn, MiscMuxCont0, MiscMuxCont1;
wire [10:0] MiscMuxOuts;
wire [12:0] MiscBusOuts;
wire [11:0] MiscRandomIns;
wire [17:0] MiscRandomOuts;
/********************************************************/
// inputs
assign
A1bus[9:0] = { in93, in85, in86, in87, in88,
in89, in90, in91, in92, in81 },
A2bus[9:0] = { in55, in47, in48, in49, in50,
in51, in52, in53, in54, in43 },
A3bus[9:0] = { in67, in60, in61, VDD, in62,
in63, in64, in65, in66, in56 },
A4bus[9:0] = { in80, in72, in73, in74, in75,
in76, in77, in78, in79, in68 };
assign
B1bus[9:0] = { VDD, in142, in135, in136, in137,
in138, in139, in140, in141, in131 },
B2bus[9:0] = { VDD, in106, in99, in100, in101,
in102, in103, in104, in105, in95 },
B3bus[9:0] = {VDD, in130, in123, in124, in125,
in126, in127, in128, in129, in119 },
B4bus[9:0] = { VDD, in118, in111, in112, in113,
in114, in115, in116, in117, in107 };
assign
Y1bus[5:0] = { in1971, in1966, in1961, in1956, in1348, in1341 },
Y2bus[5:0] = { in2090, in2084, in2078, in2072, in2067, in1996 },
Y3bus[3:0] = { in1991, in1986, in1981, in1976 };
assign
Z1bus[8:0] = { in24, in6, in23, in22, in21, in5, in20, in4, in19 },
Z2bus[7:0] = { in28, in35, in34, in27, in33, in26, in32, in25 };
assign
ParTreeIns[11:0] = { in2096, in2100, in2678, in2454, in2451, in2446,
in2443, in2438, in2435, in2430, in2427, in2474 };
assign
InTbus[7:0] = { in108, in57, in120, in69, in96, in82, in132, in44 };
assign
MiscRandomIns[11:0] = { in3, in1, in483, in36, in15, in2,
in661, in7, in94, in1083, in2066, in452 };
assign
ContA0 = in651, ContA1 = in543,
ContB0 = in2105, ContB1 = in2104,
ContMask0 = in8, ContMask1 = in1384, ContMask2 = in40,
ContZ0 = in16, ContZ1 = in29,
ContEq = in11,
ContPar0 = in14, ContPar1 = in37,
ContPar2 = in2106, ContPar3 = in567;
assign
MiscMuxIn = in559, MiscMuxCont0 = in868, MiscMuxCont1 = in860;
// outputs
assign
out329 = OutYgreaterX, out231 = OutYgreaterX_Equal,
out150 = OutZequalW, out311 = OutNot_ZequalW,
out308 = OutParCheck, out225 = OutNot_ParCheck;
assign
{ out261, out325, out319, out401, out229, out227, out397, out395 } = ParChkOuts[7:0];
assign
{ out238, out237, out236, out235, out221, out220, out219, out218 } = OutTbus[7:0];
assign
{ out280, out321, out323, out331, out153, out148,
out145, out297, out284, out282, out295 } = MiscMuxOuts[10:0],
{ out164, out160, out162, out171, out168, out166,
out299, out301, out286, out303, out288, out305,
out290 } = MiscBusOuts[12:0],
{ out158, out188, out176, out259, out234, out217,
out223, out156, out173, out369, out367, out411,
out384, out337, out409, out391, out350, out335 } = MiscRandomOuts[17:0];
/* instantiate top level circuit */
TopLevel2670 Ckt2670(A1bus, A2bus, A3bus, A4bus, B1bus, B2bus, B3bus, B4bus,
Y1bus, Y2bus, Y3bus, Z1bus, Z2bus, ParTreeIns,
InTbus, ContA0, ContA1, ContB0, ContB1,
ContMask0, ContMask1, ContMask2, ContZ0, ContZ1, ContEq,
ContPar0, ContPar1, ContPar2, ContPar3,
MiscMuxIn, MiscMuxCont0, MiscMuxCont1, MiscRandomIns,
OutYgreaterX, OutYgreaterX_Equal, OutZequalW,
OutNot_ZequalW, OutParCheck, OutNot_ParCheck,
ParChkOuts, OutTbus, MiscMuxOuts, MiscBusOuts, MiscRandomOuts);
/* these 76 lines go straigh through the circuit */
assign
out169 = in169, out174 = in174, out177 = in177, out178 = in178,
out179 = in179, out180 = in180, out181 = in181, out182 = in182,
out183 = in183, out184 = in184, out185 = in185, out186 = in186,
out189 = in189, out190 = in190, out191 = in191, out192 = in192,
out193 = in193, out194 = in194, out195 = in195, out196 = in196,
out197 = in197, out198 = in198, out199 = in199, out200 = in200,
out201 = in201, out202 = in202, out203 = in203, out204 = in204,
out205 = in205, out206 = in206, out207 = in207, out208 = in208,
out209 = in209, out210 = in210, out211 = in211, out212 = in212,
out213 = in213, out214 = in214, out215 = in215, out239 = in239,
out240 = in240, out241 = in241, out242 = in242, out243 = in243,
out244 = in244, out245 = in245, out246 = in246, out247 = in247,
out248 = in248, out249 = in249, out250 = in250, out251 = in251,
out252 = in252, out253 = in253, out254 = in254, out255 = in255,
out256 = in256, out257 = in257, out262 = in262, out263 = in263,
out264 = in264, out265 = in265, out266 = in266, out267 = in267,
out268 = in268, out269 = in269, out270 = in270, out271 = in271,
out272 = in272, out273 = in273, out274 = in274, out275 = in275,
out276 = in276, out277 = in277, out278 = in278, out279 = in279;
endmodule // Circuit2670
/***************************************************************************/
/***************************************************************************/
module TopLevel2670(A1bus, A2bus, A3bus, A4bus, B1bus, B2bus, B3bus, B4bus,
Y1bus, Y2bus, Y3bus, Z1bus, Z2bus, ParTreeIns,
InTbus, ContA0, ContA1, ContB0, ContB1,
ContMask0, ContMask1, ContMask2, ContZ0, ContZ1, ContEq,
ContPar0, ContPar1, ContPar2, ContPar3,
MiscMuxIn, MiscMuxCont0, MiscMuxCont1, MiscRandomIns,
OutYgreaterX, OutYgreaterX_Equal, OutZequalW,
OutNot_ZequalW, OutParCheck, OutNot_ParCheck,
ParChkOuts, OutTbus, MiscMuxOuts, MiscBusOuts, MiscRandomOuts);
input [9:0] A1bus, A2bus, A3bus, A4bus;
input [9:0] B1bus, B2bus, B3bus, B4bus;
input [5:0] Y1bus, Y2bus;
input [3:0] Y3bus;
input [8:0] Z1bus;
input [7:0] Z2bus;
input [11:0] ParTreeIns;
input [7:0] InTbus;
input ContA0, ContA1, ContB0, ContB1, ContMask0, ContMask1, ContMask2;
input ContZ0, ContZ1, ContEq;
input ContPar0, ContPar1, ContPar2, ContPar3;
input MiscMuxIn, MiscMuxCont0, MiscMuxCont1;
input [11:0] MiscRandomIns;
output OutYgreaterX, OutYgreaterX_Equal, OutZequalW, OutNot_ZequalW;
output OutParCheck, OutNot_ParCheck;
output [7:0] ParChkOuts;
output [7:0] OutTbus;
output [10:0] MiscMuxOuts;
output [12:0] MiscBusOuts;
output [17:0] MiscRandomOuts;
wire [9:0] Abus, Bbus, Qbus, Rbus, Sbus;
wire [11:0] Xbus, Ybus;
wire [16:0] Wbus, Zbus;
wire [8:0] V1bus;
wire [7:0] V2bus;
wire CompCLAs;
Mux10bit_4_1 M1( A1bus, A2bus, A3bus, A4bus, ContA0, ContA1, Abus ),
M2( B1bus, B2bus, B3bus, B4bus, ContB0, ContB1, Bbus );
assign Xbus[8:0] = Abus[8:0],
Xbus[11:9] = Bbus[2:0];
ContSignalGen M3( Bbus[4], Bbus[5], ContMask1, ContMask2, ContAlpha, ContBeta );
CompareXY M4( Xbus, Ybus, ContAlpha, ContBeta, ContMask0,
OutYgreaterX, OutYgreaterX_Equal, CompCLAs );
MuxSpecY M5( Y1bus, Y2bus, Y3bus, ContAlpha, ParTreeIns,
Ybus, Wbus, Qbus, Rbus, Sbus );
assign
V1bus[8:0] = Abus[8:0],
V2bus[7:0] = Bbus[7:0];
MuxSpecZ M6( Z1bus, Z2bus, V1bus, V2bus, ContZ0, ContZ1, Zbus );
EqualZ_W M7( Zbus, Wbus, ContEq, OutZequalW, OutNot_ZequalW );
ParityChecker M8( Abus, Bbus, Qbus, Rbus, Sbus, CompCLAs,
ContPar0, ContPar1, ContPar2, ContPar3, InTbus,
OutParCheck, OutNot_ParCheck, ParChkOuts, OutTbus );
MiscLogic M9( Abus, Bbus, Y2bus, ParTreeIns, MiscRandomIns, ContPar2, ContPar3,
MiscMuxIn, MiscMuxCont0, MiscMuxCont1, ParChkOuts[5],
MiscMuxOuts, MiscBusOuts, MiscRandomOuts );
endmodule // TopLevel2670
/***************************************************************************
* module: Mux10bit_4_1
*
* Function: 10 bit 4:1 muxes
*
***************************************************************************/
module Mux10bit_4_1( In1bus, In2bus, In3bus, In4bus, Cont0, Cont1, Outbus );
input [9:0] In1bus, In2bus, In3bus, In4bus;
input Cont0, Cont1;
output [9:0] Outbus;
Mux4_1 Mux0( In1bus[0], In2bus[0], In3bus[0], In4bus[0], Cont0, Cont1, Outbus[0] ),
Mux1( In1bus[1], In2bus[1], In3bus[1], In4bus[1], Cont0, Cont1, Outbus[1] ),
Mux2( In1bus[2], In2bus[2], In3bus[2], In4bus[2], Cont0, Cont1, Outbus[2] ),
Mux3( In1bus[3], In2bus[3], In3bus[3], In4bus[3], Cont0, Cont1, Outbus[3] ),
Mux4( In1bus[4], In2bus[4], In3bus[4], In4bus[4], Cont0, Cont1, Outbus[4] ),
Mux5( In1bus[5], In2bus[5], In3bus[5], In4bus[5], Cont0, Cont1, Outbus[5] ),
Mux6( In1bus[6], In2bus[6], In3bus[6], In4bus[6], Cont0, Cont1, Outbus[6] ),
Mux7( In1bus[7], In2bus[7], In3bus[7], In4bus[7], Cont0, Cont1, Outbus[7] ),
Mux8( In1bus[8], In2bus[8], In3bus[8], In4bus[8], Cont0, Cont1, Outbus[8] ),
Mux9( In1bus[9], In2bus[9], In3bus[9], In4bus[9], Cont0, Cont1, Outbus[9] );
endmodule // Mux10bit_4_1
/******************************************************/
module Mux4_1( In1, In2, In3, In4, Cont0, Cont1, Out );
input In1, In2, In3, In4;
input Cont0, Cont1;
output Out;
inv Mux0( .A(Cont0), .Y(Not_Cont0) ),
Mux1( .A(Cont1), .Y(Not_Cont1) );
and3 Mux2( .A(In1), .B(Not_Cont0), .C(Not_Cont1), .Y(line2) ),
Mux3( .A(In2), .B(Not_Cont0), .C(Cont1), .Y(line3) ),
Mux4( .A(In3), .B(Cont0), .C(Not_Cont1), .Y(line4) ),
Mux5( .A(In4), .B(Cont0), .C(Cont1), .Y(line5) );
or4 Mux6( .A(line2), .B(line3), .C(line4), .D(line5), .Y(Out) );
endmodule // Mux4_1
/***************************************************************************
* module: ContSignalGen
*
* Function: generate control signals ContAlpha and ContBeta
*
***************************************************************************/
module ContSignalGen ( Bbus4, Bbus5, ContMask1, ContMask2, ContAlpha, ContBeta);
input Bbus4, Bbus5, ContMask1, ContMask2;
output ContAlpha, ContBeta;
inv UM3_0( .A(Bbus5), .Y(NotB5) ),
UM3_1( .A(ContMask1), .Y(NotMask1) );
and2 UM3_2( .A(Bbus4), .B(NotMask1), .Y(line2) );
and3 UM3_3( .A(NotB5), .B(line2), .C(ContMask2), .Y(ContAlpha) );
inv UM3_4( .A(line2), .Y(line4) );
and3 UM3_5( .A(ContMask2), .B(line4), .C(NotB5), .Y(ContBeta) );
endmodule // ContSignalGen
/***************************************************************************
* module: CompareXY
*
* Function: compute OutYgreaterX = Ybus > Xbus
* using a CLA.
* There are actually two CLAs with identical inputs. The outputs
* of the CLAs are are exored (for comparison) the output OutYgreaterX_Equal.
* The complement of this signal, CompCLAs, is fed to ParityChecker.
*
* The upper 8 bits of Xbus and Ybus can be masked out in groups of 4,6,8.
* which gives the ability to compare buses of size 4,6,8 and 12.
*
* RedundantInv is an inverter with redundancy in it, which causes
* the longest path going through it to be false.
*
***************************************************************************/
module CompareXY( Xbus, Ybus, ContAlpha, ContBeta, ContMask0,
OutYgreaterX, OutYgreaterX_Equal, CompCLAs );
input [11:0] Xbus, Ybus;
input ContAlpha, ContBeta, ContMask0;
output OutYgreaterX, OutYgreaterX_Equal, CompCLAs;
wire [11:0] XMbus, YMbus, Not_XMbus;
wire YgX1, YgX2, Not_CompCLAs;
MaskBus UM4_0( Xbus, ContAlpha, ContBeta, ContMask0, XMbus ),
UM4_1( Ybus, ContAlpha, ContBeta, ContMask0, YMbus );
Invert12 UM4_2( XMbus, Not_XMbus );
CLA12_XY UM4_3( Not_XMbus, YMbus, YgX1 ),
UM4_4( Not_XMbus, YMbus, YgX2 );
assign OutYgreaterX = YgX1;
XOR2b UM4_5( .A(YgX1), .B(YgX2), .Y(Not_CompCLAs) );
RedundantInv UM4_6( .A(Not_CompCLAs), .Y(CompCLAs) );
inv UM4_7( .A(CompCLAs), .Y(OutYgreaterX_Equal) );
endmodule // CompareXY
/********************************************/
module MaskBus( Inbus, ContAlpha, ContBeta, ContMask0, OutMbus );
input [11:0] Inbus;
input ContAlpha, ContBeta, ContMask0;
output [11:0] OutMbus;
assign OutMbus[3:0] = Inbus[3:0];
and2 MB0( .A(Inbus[4]), .B(ContMask0), .Y(OutMbus[4]) ),
MB1( .A(Inbus[5]), .B(ContMask0), .Y(OutMbus[5]) );
inv MB2( .A(ContAlpha), .Y(NotAlpha) );
and2 MB3( .A(Inbus[6]), .B(NotAlpha), .Y(line3) ),
MB4( .A(line3), .B(ContMask0), .Y(OutMbus[6]) ),
MB5( .A(Inbus[7]), .B(NotAlpha), .Y(line5) ),
MB6( .A(line5), .B(ContMask0), .Y(OutMbus[7]) );
// InBus[11:8] are ANDed with NotAlpha.ContBeta
// note that NotAlpha.ContBeta = ContBeta
// so there's some redundancy!!!
and2 MB7( .A(Inbus[8]), .B(NotAlpha), .Y(line7) ),
MB8( .A(line7), .B(ContBeta), .Y(OutMbus[8]) ),
MB9( .A(Inbus[9]), .B(NotAlpha), .Y(line9) ),
MB10( .A(line9), .B(ContBeta), .Y(OutMbus[9]) ),
MB11( .A(Inbus[10]), .B(NotAlpha), .Y(line11) ),
MB12( .A(line11), .B(ContBeta), .Y(OutMbus[10]) ),
MB13( .A(Inbus[11]), .B(NotAlpha), .Y(line13) ),
MB14( .A(line13), .B(ContBeta), .Y(OutMbus[11]) );
endmodule // MaskBus
/********************************************/
module Invert12( Inbus, Outbus );
input [11:0] Inbus;
output [11:0] Outbus;
inv Inv12_0( .A(Inbus[0]), .Y(Outbus[0]) ),
Inv12_1( .A(Inbus[1]), .Y(Outbus[1]) ),
Inv12_2( .A(Inbus[2]), .Y(Outbus[2]) ),
Inv12_3( .A(Inbus[3]), .Y(Outbus[3]) ),
Inv12_4( .A(Inbus[4]), .Y(Outbus[4]) ),
Inv12_5( .A(Inbus[5]), .Y(Outbus[5]) ),
Inv12_6( .A(Inbus[6]), .Y(Outbus[6]) ),
Inv12_7( .A(Inbus[7]), .Y(Outbus[7]) ),
Inv12_8( .A(Inbus[8]), .Y(Outbus[8]) ),
Inv12_9( .A(Inbus[9]), .Y(Outbus[9]) ),
Inv12_10( .A(Inbus[10]), .Y(Outbus[10]) ),
Inv12_11( .A(Inbus[11]), .Y(Outbus[11]) );
endmodule // Invert12
/********************************************/
module CLA12_XY( In1bus, In2bus, OutCarry );
input [11:0] In1bus, In2bus;
output OutCarry;
wire [11:0] Gbus, Pbus;
CalcGP GP( In1bus, In2bus, Gbus, Pbus);
CLACarry12_Cin0 CalcCy( Gbus, Pbus, OutCarry );
endmodule // Cla12XY
/********************************************/
module CalcGP( In1bus, In2bus, Gbus, Pbus);
input [11:0] In1bus, In2bus;
output [11:0] Gbus, Pbus;
and2 CalGP0( .A(In1bus[0]), .B(In2bus[0]), .Y(Gbus[0]) ),
CalGP1( .A(In1bus[1]), .B(In2bus[1]), .Y(Gbus[1]) ),
CalGP2( .A(In1bus[2]), .B(In2bus[2]), .Y(Gbus[2]) ),
CalGP3( .A(In1bus[3]), .B(In2bus[3]), .Y(Gbus[3]) ),
CalGP4( .A(In1bus[4]), .B(In2bus[4]), .Y(Gbus[4]) ),
CalGP5( .A(In1bus[5]), .B(In2bus[5]), .Y(Gbus[5]) ),
CalGP6( .A(In1bus[6]), .B(In2bus[6]), .Y(Gbus[6]) ),
CalGP7( .A(In1bus[7]), .B(In2bus[7]), .Y(Gbus[7]) ),
CalGP8( .A(In1bus[8]), .B(In2bus[8]), .Y(Gbus[8]) ),
CalGP9( .A(In1bus[9]), .B(In2bus[9]), .Y(Gbus[9]) ),
CalGP10( .A(In1bus[10]), .B(In2bus[10]), .Y(Gbus[10]) ),
CalGP11( .A(In1bus[11]), .B(In2bus[11]), .Y(Gbus[11]) );
XOR2a CalGP12( .A(In1bus[0]), .B(In2bus[0]), .Y(Pbus[0]) ),
CalGP13( .A(In1bus[1]), .B(In2bus[1]), .Y(Pbus[1]) ),
CalGP14( .A(In1bus[2]), .B(In2bus[2]), .Y(Pbus[2]) ),
CalGP15( .A(In1bus[3]), .B(In2bus[3]), .Y(Pbus[3]) ),
CalGP16( .A(In1bus[4]), .B(In2bus[4]), .Y(Pbus[4]) ),
CalGP17( .A(In1bus[5]), .B(In2bus[5]), .Y(Pbus[5]) ),
CalGP18( .A(In1bus[6]), .B(In2bus[6]), .Y(Pbus[6]) ),
CalGP19( .A(In1bus[7]), .B(In2bus[7]), .Y(Pbus[7]) ),
CalGP20( .A(In1bus[8]), .B(In2bus[8]), .Y(Pbus[8]) ),
CalGP21( .A(In1bus[9]), .B(In2bus[9]), .Y(Pbus[9]) ),
CalGP22( .A(In1bus[10]), .B(In2bus[10]), .Y(Pbus[10]) ),
CalGP23( .A(In1bus[11]), .B(In2bus[11]), .Y(Pbus[11]) );
endmodule // CalcGP
/********************************************
*
* This 12-bit CLA is made up of 3-, 4- and
* 5-bit CLAs, whose outputs are appropriately
* connected with the group propagate signals
* Prop7_3 and Prop11_8 to generate the carry
* output.
*
********************************************/
module CLACarry12_Cin0( Gbus, Pbus, OutCarry11_0 );
input [11:0] Gbus, Pbus;
output OutCarry11_0;
CLACarry3_Cin0 Cla12_0( Gbus[2:0], Pbus[2:0], OutCarry2_0 );
CLACarry5_Cin0 Cla12_1( Gbus[7:3], Pbus[7:3], OutCarry7_3 );
CLACarry4_Cin0 Cla12_2( Gbus[11:8], Pbus[11:8], OutCarry11_8 );
and5 Cla12_3( .A(Pbus[3]), .B(Pbus[4]), .C(Pbus[5]),
.D(Pbus[6]), .E(Pbus[7]), .Y(Prop7_3) );
and4 Cla12_4( .A(Pbus[8]), .B(Pbus[9]), .C(Pbus[10]),
.D(Pbus[11]), .Y(Prop11_8) );
and2 Cla12_5( .A(Prop7_3), .B(OutCarry2_0), .Y(line5) );
or2 Cla12_6( .A(OutCarry7_3), .B(line5), .Y(OutCarry7_0) );
inv Cla12_7( .A(OutCarry7_0), .Y(NotOutCarry7_0) );
or2 Cla12_8( .A(OutCarry11_8), .B(Prop11_8), .Y(line8) );
and2 Cla12_9( .A(NotOutCarry7_0), .B(OutCarry11_8), .Y(line9) ),
Cla12_10( .A(line8), .B(OutCarry7_0), .Y(line10) );
or2 Cla12_11( .A(line9), .B(line10), .Y(OutCarry11_0) );
endmodule // CLACarry12_Cin0
/********************************************/
module CLACarry3_Cin0( Gbus, Pbus, OutCarry );
input [2:0] Gbus, Pbus;
output OutCarry;
and2 Cla3_0( .A(Pbus[2]), .B(Gbus[1]), .Y(line0) );
and3 Cla3_1( .A(Pbus[2]), .B(Pbus[1]), .C(Gbus[0]), .Y(line1) );
or3 Cla3_2( .A(Gbus[2]), .B(line0), .C(line1), .Y(OutCarry) );
endmodule // CLACarry3_Cin0
/********************************************/
module CLACarry4_Cin0( Gbus, Pbus, OutCarry );
input [3:0] Gbus, Pbus;
output OutCarry;
and2 Cla4_0( .A(Pbus[3]), .B(Gbus[2]), .Y(line0) );
and3 Cla4_1( .A(Pbus[3]), .B(Pbus[2]), .C(Gbus[1]), .Y(line1) );
and4 Cla4_2( .A(Pbus[3]), .B(Pbus[2]), .C(Pbus[1]), .D(Gbus[0]), .Y(line2) );
or4 Cla4_3( .A(Gbus[3]), .B(line0), .C(line1), .D(line2), .Y(OutCarry) );
endmodule // CLACarry4_Cin0
/********************************************/
module CLACarry5_Cin0( Gbus, Pbus, OutCarry );
input [4:0] Gbus, Pbus;
output OutCarry;
and2 Cla5_0( .A(Pbus[4]), .B(Gbus[3]), .Y(line0) );
and3 Cla5_1( .A(Pbus[4]), .B(Pbus[3]), .C(Gbus[2]), .Y(line1) );
and4 Cla5_2( .A(Pbus[4]), .B(Pbus[3]), .C(Pbus[2]), .D(Gbus[1]), .Y(line2) );
and5 Cla5_3( .A(Pbus[4]), .B(Pbus[3]), .C(Pbus[2]), .D(Pbus[1]),
.E(Gbus[0]), .Y(line3) );
or5 Cla5_4( .A(Gbus[4]), .B(line0), .C(line1), .D(line2),
.E(line3), .Y(OutCarry) );
endmodule // CLACarry5_Cin0
/***************************************************************************
* module: MuxSpecY
*
* Function: generate buses Ybus, Wbus, Qbus, Rbus and Sbus.
* There are 2:1 muxes to generate Ybus from Y1bus, Y2bus and Y3bus.
* The other output buses are fanouts of Y1bus, Y2bus, Y3bus and ParTreeIns.
* (Note: The parities of Qbus, Rbus and Sbus are computed in
* ParityChecker.)
*
***************************************************************************/
module MuxSpecY( Y1bus, Y2bus, Y3bus, ContAlpha, ParTreeIns,
Ybus, Wbus, Qbus, Rbus, Sbus);
input [5:0] Y1bus, Y2bus;
input [3:0] Y3bus;
input ContAlpha;
input [11:0] ParTreeIns;
output [11:0] Ybus;
output [16:0] Wbus;
output [9:0] Qbus, Rbus, Sbus;
wire [5:0] Not_Y1bus, Not_Y2bus;
wire [3:0] Not_Y3bus;
Invert6 UM5_0( Y1bus, Not_Y1bus ),
UM5_1( Y2bus, Not_Y2bus );
Mux6bit_2_1 UM5_2( Not_Y1bus, Not_Y2bus, ContAlpha, Ybus[5:0] );
Invert4 UM5_3( Y3bus, Not_Y3bus );
assign
Ybus[9:6] = Not_Y3bus[3:0],
Ybus[11:10] = Not_Y2bus[1:0];
assign
Wbus[5:0] = Y1bus[5:0],
Wbus[9:6] = Y3bus[3:0],
Wbus[15:10] = Y2bus[5:0],
Wbus[16] = 1'b0;
assign
Qbus[3:0] = Y1bus[5:2],
Qbus[7:4] = Y3bus[3:0],
Qbus[8] = Y2bus[0],
Qbus[9] = ParTreeIns[0];
assign
Rbus[1:0] = Y1bus[1:0],
Rbus[9:2] = ParTreeIns[8:1];
assign
Sbus[4:0] = Y2bus[5:1],
Sbus[7:5] = ParTreeIns[11:9],
Sbus[8] = 1'b0,
Sbus[9] = 1'b0;
endmodule // MuxSpecY
/******************************************************/
module Invert6( Inbus, Outbus );
input [5:0] Inbus;
output [5:0] Outbus;
inv Inv6_0( .A(Inbus[0]), .Y(Outbus[0]) ),
Inv6_1( .A(Inbus[1]), .Y(Outbus[1]) ),
Inv6_2( .A(Inbus[2]), .Y(Outbus[2]) ),
Inv6_3( .A(Inbus[3]), .Y(Outbus[3]) ),
Inv6_4( .A(Inbus[4]), .Y(Outbus[4]) ),
Inv6_5( .A(Inbus[5]), .Y(Outbus[5]) );
endmodule // Invert6
/******************************************************/
module Invert4( Inbus, Outbus );
input [3:0] Inbus;
output [3:0] Outbus;
inv Inv4_0( .A(Inbus[0]), .Y(Outbus[0]) ),
Inv4_1( .A(Inbus[1]), .Y(Outbus[1]) ),
Inv4_2( .A(Inbus[2]), .Y(Outbus[2]) ),
Inv4_3( .A(Inbus[3]), .Y(Outbus[3]) );
endmodule // Invert4
/******************************************************/
module Mux2_1( In1, In2, ContIn, Out );
input In1, In2, ContIn;
output Out;
inv Mux0( .A(ContIn), .Y(Not_ContIn) );
and2 Mux1( .A(In1), .B(Not_ContIn), .Y(line1) ),
Mux2( .A(In2), .B(ContIn), .Y(line2) );
or2 Mux3( .A(line1), .B(line2), .Y(Out) );
endmodule
/******************************************************/
module Mux6bit_2_1( In1bus, In2bus, ContIn, Outbus );
input [5:0] In1bus, In2bus;
input ContIn;
output [5:0] Outbus;
Mux2_1 Mux6_0( In1bus[0], In2bus[0], ContIn, Outbus[0] ),
Mux6_1( In1bus[1], In2bus[1], ContIn, Outbus[1] ),
Mux6_2( In1bus[2], In2bus[2], ContIn, Outbus[2] ),
Mux6_3( In1bus[3], In2bus[3], ContIn, Outbus[3] ),
Mux6_4( In1bus[4], In2bus[4], ContIn, Outbus[4] ),
Mux6_5( In1bus[5], In2bus[5], ContIn, Outbus[5] );
endmodule // Mux6bit_2_1
/***************************************************************************
* module: MuxSpecZ
*
* Function: generate Zbus from (Z1bus,V1bus) and (Z2bus,V2bus).
* (Note: V1bus is essentially Abus, and V2bus is Bbus.)
*
***************************************************************************/
module MuxSpecZ( Z1bus, Z2bus, V1bus, V2bus, ContZ0, ContZ1, Zbus);
input [8:0] Z1bus, V1bus;
input [7:0] Z2bus, V2bus;
input ContZ0, ContZ1;
output [16:0] Zbus;
Mux9bit_2_1 UM6_0( Z1bus, V1bus, ContZ0, Zbus[8:0] );
Mux8bit_2_1 UM6_1( Z2bus, V2bus, ContZ1, Zbus[16:9] );
endmodule // MuxSpecZ
/******************************************************/
module Mux9bit_2_1( In1bus, In2bus, ContIn, Outbus );
input [8:0] In1bus, In2bus;
input ContIn;
output [8:0] Outbus;
Mux2_1 Mux9_0( In1bus[0], In2bus[0], ContIn, Outbus[0] ),
Mux9_1( In1bus[1], In2bus[1], ContIn, Outbus[1] ),
Mux9_2( In1bus[2], In2bus[2], ContIn, Outbus[2] ),
Mux9_3( In1bus[3], In2bus[3], ContIn, Outbus[3] ),
Mux9_4( In1bus[4], In2bus[4], ContIn, Outbus[4] ),
Mux9_5( In1bus[5], In2bus[5], ContIn, Outbus[5] ),
Mux9_6( In1bus[6], In2bus[6], ContIn, Outbus[6] ),
Mux9_7( In1bus[7], In2bus[7], ContIn, Outbus[7] ),
Mux9_8( In1bus[8], In2bus[8], ContIn, Outbus[8] );
endmodule // Mux9bit_2_1
/******************************************************/
module Mux8bit_2_1( In1bus, In2bus, ContIn, Outbus );
input [7:0] In1bus, In2bus;
input ContIn;
output [7:0] Outbus;
Mux2_1 Mux8_0( In1bus[0], In2bus[0], ContIn, Outbus[0] ),
Mux8_1( In1bus[1], In2bus[1], ContIn, Outbus[1] ),
Mux8_2( In1bus[2], In2bus[2], ContIn, Outbus[2] ),
Mux8_3( In1bus[3], In2bus[3], ContIn, Outbus[3] ),
Mux8_4( In1bus[4], In2bus[4], ContIn, Outbus[4] ),
Mux8_5( In1bus[5], In2bus[5], ContIn, Outbus[5] ),
Mux8_6( In1bus[6], In2bus[6], ContIn, Outbus[6] ),
Mux8_7( In1bus[7], In2bus[7], ContIn, Outbus[7] );
endmodule // Mux8bit_2_1
/***************************************************************************
* module: EqualZ_W
*
* Function: compute OutZequalW = (Zbus=Wbus)
*
***************************************************************************/
module EqualZ_W( Zbus, Wbus, ContEq, OutZequalW, OutNot_ZequalW );
input [16:0] Zbus, Wbus;
input ContEq;
output OutZequalW, OutNot_ZequalW;
wire [16:0] XorZW;
Xor17bit UM7_0( Zbus, Wbus, XorZW );
AN18 UM7_1( XorZW, ContEq, OutNot_ZequalW );
inv UM7_2( .A(OutNot_ZequalW), .Y(OutZequalW) );
endmodule
/********************************************/
module Xor17bit( Zbus, Wbus, XorZW );
input [16:0] Zbus, Wbus;
output [16:0] XorZW;
XOR2a Xr0( .A(Zbus[0]), .B(Wbus[0]), .Y(XorZW[0]) ),
Xr1( .A(Zbus[1]), .B(Wbus[1]), .Y(XorZW[1]) ),
Xr2( .A(Zbus[2]), .B(Wbus[2]), .Y(XorZW[2]) ),
Xr3( .A(Zbus[3]), .B(Wbus[3]), .Y(XorZW[3]) ),
Xr4( .A(Zbus[4]), .B(Wbus[4]), .Y(XorZW[4]) ),
Xr5( .A(Zbus[5]), .B(Wbus[5]), .Y(XorZW[5]) ),
Xr6( .A(Zbus[6]), .B(Wbus[6]), .Y(XorZW[6]) ),
Xr7( .A(Zbus[7]), .B(Wbus[7]), .Y(XorZW[7]) ),
Xr8( .A(Zbus[8]), .B(Wbus[8]), .Y(XorZW[8]) ),
Xr9( .A(Zbus[9]), .B(Wbus[9]), .Y(XorZW[9]) ),
Xr10( .A(Zbus[10]), .B(Wbus[10]), .Y(XorZW[10]) ),
Xr11( .A(Zbus[11]), .B(Wbus[11]), .Y(XorZW[11]) ),
Xr12( .A(Zbus[12]), .B(Wbus[12]), .Y(XorZW[12]) ),
Xr13( .A(Zbus[13]), .B(Wbus[13]), .Y(XorZW[13]) ),
Xr14( .A(Zbus[14]), .B(Wbus[14]), .Y(XorZW[14]) ),
Xr15( .A(Zbus[15]), .B(Wbus[15]), .Y(XorZW[15]) ),
Xr16( .A(Zbus[16]), .B(Wbus[16]), .Y(XorZW[16]) );
endmodule // Xor17bit
/***************************************************************************
* module: ParityChecker
*
* Function: This module ANDs various bus parities and control signals
* including the output of xor of the CLAs (CompCLAs).
* The buses whose parities are ANDed are Abus, Bbus, Qbus, Rbus and Sbus.
* Another control signal called Lambda is computed by SmallCircuitLambda.
*
***************************************************************************/
module ParityChecker( Abus, Bbus, Qbus, Rbus, Sbus, CompCLAs,
ContPar0, ContPar1, ContPar2, ContPar3, InTbus,
OutParCheck, OutNot_ParCheck, ParChkOuts, OutTbus );
input [9:0] Abus, Bbus;
input [9:0] Qbus, Rbus, Sbus;
input CompCLAs, ContPar0, ContPar1, ContPar2, ContPar3;
input [7:0] InTbus;
output OutParCheck, OutNot_ParCheck;
output [7:0] ParChkOuts;
output [7:0] OutTbus;
wire ParA, ParB, ParP, ParQ, ParR;
wire Lambda;
SmallCircuitLambda UM8_0( InTbus, ContPar2, ContPar3, OutTbus, ParChkOuts[7:5] );
assign Lambda = ParChkOuts[5];
ParityTree10bit UM8_1( Abus, ParA ),
UM8_2( Bbus, ParB ),
UM8_3( Qbus, ParQ ),
UM8_4( Rbus, ParR ),
UM8_5( Sbus, ParS );
inv UM8_6( .A(ContPar0), .Y(NotPar0) );
or2 UM8_7( .A(ParA), .B(ContPar1), .Y(line7) ),
UM8_8( .A(ParB), .B(ContPar1), .Y(line8) ),
UM8_9( .A(ParR), .B(NotPar0), .Y(line9) );
and3 UM8_10( .A(line8), .B(line7), .C(ParS), .Y(line10) ),
UM8_11( .A(ParQ), .B(line9), .C(CompCLAs), .Y(line11) ),
UM8_12( .A(line10), .B(line11), .C(Lambda), .Y(OutParCheck) );
inv UM8_13( .A(OutParCheck), .Y(OutNot_ParCheck) ),
UM8_14( .A(line8), .Y(ParChkOuts[0]) ),
UM8_15( .A(line7), .Y(ParChkOuts[1]) ),
UM8_16( .A(ParS), .Y(ParChkOuts[2]) ),
UM8_17( .A(ParQ), .Y(ParChkOuts[3]) ),
UM8_18( .A(line9), .Y(ParChkOuts[4]) );
endmodule // ParityChecker
/********************************************/
module SmallCircuitLambda( InTbus, ContPar2, ContPar3, OutTbus, ParChkOuts7_5 );
input [7:0] InTbus;
input ContPar2, ContPar3;
output [7:0] OutTbus;
output [2:0] ParChkOuts7_5;
and4 SCL0( .A(InTbus[0]), .B(InTbus[1]), .C(InTbus[2]),
.D(InTbus[3]), .Y(line0) ),
SCL1( .A(InTbus[4]), .B(InTbus[5]), .C(InTbus[6]),
.D(InTbus[7]), .Y(line1) );
and2 SCL2( .A(line0), .B(line1), .Y(ParChkOuts7_5[1]) );
inv SCL3( .A(ParChkOuts7_5[1]), .Y(ParChkOuts7_5[2]) );
inv SCL4( .A(ContPar2), .Y(NotPar2) ),
SCL5( .A(ContPar3), .Y(NotPar3) );
or2 SCL6( .A(NotPar2), .B(line0), .Y(line6) ),
SCL7( .A(NotPar3), .B(line1), .Y(line7) );
and2 SCL8( .A(line6), .B(line7), .Y(ParChkOuts7_5[0]) );
inv SCL9( .A(InTbus[0]), .Y(OutTbus[0]) ),
SCL10( .A(InTbus[1]), .Y(OutTbus[1]) ),
SCL11( .A(InTbus[2]), .Y(OutTbus[2]) ),
SCL12( .A(InTbus[3]), .Y(OutTbus[3]) ),
SCL13( .A(InTbus[4]), .Y(OutTbus[4]) ),
SCL14( .A(InTbus[5]), .Y(OutTbus[5]) ),
SCL15( .A(InTbus[6]), .Y(OutTbus[6]) ),
SCL16( .A(InTbus[7]), .Y(OutTbus[7]) );
endmodule // SmallCircuitLambda
/********************************************/
module ParityTree10bit( Inbus, ParOut );
input [9:0] Inbus;
output ParOut;
XOR2a PT0( .A(Inbus[0]), .B(Inbus[1]), .Y(line0) ),
PT1( .A(Inbus[2]), .B(Inbus[3]), .Y(line1) ),
PT2( .A(Inbus[4]), .B(Inbus[5]), .Y(line2) ),
PT3( .A(Inbus[6]), .B(Inbus[7]), .Y(line3) ),
PT4( .A(Inbus[8]), .B(Inbus[9]), .Y(line4) );
XOR3a PT5( .A(line0), .B(line1), .C(line2), .Y(line5) );
XOR2a PT6( .A(line3), .B(line4), .Y(line6) );
XOR2a PT7( .A(line5), .B(line6), .Y(ParOut) );
endmodule // ParityTree10bit
/***************************************************************************
* module: MiscLogic
*
* Function: mostly a random circuit.
* Three major parts are 1) muxes fed by Abus, 2) buses (with buf and inv)
* 3) a few random gates.
*
****************************************************************************/
module MiscLogic( Abus, Bbus, Y2bus, ParTreeIns, MiscRandomIns, ContPar2, ContPar3,
MiscMuxIn, MiscMuxCont0, MiscMuxCont1, Lambda,
MiscMuxOuts, MiscBusOuts, MiscRandomOuts );
input [9:0] Abus, Bbus;
input [5:0] Y2bus;
input [11:0] ParTreeIns;
input [11:0] MiscRandomIns;
input ContPar2, ContPar3;
input MiscMuxIn, MiscMuxCont0, MiscMuxCont1, Lambda;
output [10:0] MiscMuxOuts;
output [12:0] MiscBusOuts;
output [17:0] MiscRandomOuts;
MiscMuxCircuit UM9_0( Abus, MiscMuxIn, MiscMuxCont0, MiscMuxCont1, MiscMuxOuts);
MiscBusCircuit UM9_1( Abus, Bbus, MiscBusOuts);
MiscRandomCircuit UM9_2( Bbus, Y2bus, ParTreeIns, MiscRandomIns,
ContPar2, ContPar3, Lambda, MiscRandomOuts );
endmodule // MiscLogic
/********************************************/
module MiscMuxCircuit( Abus, MiscMuxIn, MiscMuxCont0, MiscMuxCont1, MiscMuxOuts);
input [9:0] Abus;
input MiscMuxIn, MiscMuxCont0, MiscMuxCont1;
output [10:0] MiscMuxOuts;
wire [9:0] NewAbus;
wire ParNewA;
assign
NewAbus[2:0] = Abus[2:0],
NewAbus[7:3] = Abus[9:5],
NewAbus[8] = 1'b0;
or2 MMC0( .A(Abus[1]), .B(MiscMuxIn), .Y(NewAbus[9]) );
ParityTree10bit PTMuxA( NewAbus, ParNewA );
Mux2_1 MMC2( Abus[9], ParNewA, MiscMuxCont0, MiscMuxOuts[0] ),
MMC3( Abus[0], NewAbus[9], MiscMuxCont0, MiscMuxOuts[1] ),
MMC4( Abus[1], Abus[3], MiscMuxCont0, MiscMuxOuts[2] ),
MMC5( Abus[2], Abus[4], MiscMuxCont0, MiscMuxOuts[3] );
inv MMC6( .A(NewAbus[9]), .Y(NotNewA9) );
XOR2a MMC7( .A(Abus[0]), .B(Abus[1]), .Y(line7) ),
MMC8( .A(line7), .B(NotNewA9), .Y(line8) ),
MMC9( .A(line8), .B(Abus[9]), .Y(line9) );
Mux2_1 MMC10( line9, Abus[9], MiscMuxCont1, MiscMuxOuts[4] ),
MMC11( NewAbus[9], Abus[1], MiscMuxCont1, MiscMuxOuts[5] ),
MMC12( 1'b1, Abus[0], MiscMuxCont1, MiscMuxOuts[6] );
assign
MiscMuxOuts[7] = MiscMuxOuts[0],
MiscMuxOuts[8] = MiscMuxOuts[1],
MiscMuxOuts[9] = MiscMuxOuts[2],
MiscMuxOuts[10] = MiscMuxOuts[3];
endmodule // MiscMuxCircuit
/********************************************/
module MiscBusCircuit( Abus, Bbus, MiscBusOuts);
input [9:0] Abus, Bbus;
output [12:0] MiscBusOuts;
buffer MBC0( .A(Abus[8]), .Y(MiscBusOuts[0]) ),
MBC1( .A(Abus[7]), .Y(MiscBusOuts[1]) ),
MBC2( .A(Abus[6]), .Y(MiscBusOuts[2]) ),
MBC3( .A(Abus[5]), .Y(MiscBusOuts[3]) ),
MBC4( .A(Abus[4]), .Y(MiscBusOuts[4]) ),
MBC5( .A(Abus[3]), .Y(MiscBusOuts[5]) ),
MBC6( .A(Abus[2]), .Y(MiscBusOuts[6]) );
inv MBC7( .A(Abus[5]), .Y(MiscBusOuts[7]) ),
MBC8( .A(Abus[4]), .Y(MiscBusOuts[8]) ),
MBC9( .A(Abus[3]), .Y(MiscBusOuts[9]) );
inv MBC10( .A(Bbus[6]), .Y(MiscBusOuts[10]) ),
MBC11( .A(Bbus[5]), .Y(MiscBusOuts[11]) ),
MBC12( .A(Bbus[4]), .Y(MiscBusOuts[12]) );
endmodule // MiscBusCircuit
/********************************************/
module MiscRandomCircuit( Bbus, Y2bus, ParTreeIns, MiscRandomIns,
ContPar2, ContPar3, Lambda, MiscRandomOuts );
input [9:0] Bbus;
input [5:0] Y2bus;
input [11:0] ParTreeIns;
input [11:0] MiscRandomIns;
input ContPar2, ContPar3;
input Lambda;
output [17:0] MiscRandomOuts;
buffer MRC0( .A(MiscRandomIns[0]), .Y(MiscRandomOuts[0]) ),
MRC1( .A(MiscRandomIns[0]), .Y(MiscRandomOuts[1]) ),
MRC2( .A(MiscRandomIns[0]), .Y(MiscRandomOuts[2]) ),
MRC3( .A(MiscRandomIns[0]), .Y(MiscRandomOuts[3]) ),
MRC4( .A(MiscRandomIns[1]), .Y(MiscRandomOuts[4]) ),
MRC5( .A(MiscRandomIns[1]), .Y(MiscRandomOuts[5]) ),
MRC6( .A(MiscRandomIns[1]), .Y(MiscRandomOuts[6]) ),
MRC7( .A(MiscRandomIns[2]), .Y(MiscRandomOuts[7]) ),
MRC8( .A(MiscRandomIns[2]), .Y(MiscRandomOuts[8]) );
and2 MRC9( .A(MiscRandomIns[0]), .B(MiscRandomIns[3]),
.Y(MiscRandomOuts[9]) );
inv MRC10( .A(ParTreeIns[10]), .Y(NotPTIns10) ),
MRC11( .A(ParTreeIns[11]), .Y(NotPTIns11) );
XOR2b MRC12( .A(Bbus[9]), .B(NotPTIns10), .Y(line12) ),
MRC13( .A(Bbus[7]), .B(NotPTIns11), .Y(line13) );
RedundantInv MRC14( .A(line12), .Y(line14) ),
MRC15( .A(line13), .Y(line15) );
nand2 MRC16( .A(line14), .B(line15), .Y(MiscRandomOuts[10]) );
and2 MRC17( .A(MiscRandomIns[4]), .B(MiscRandomIns[5]), .Y(line17) );
inv MRC18( .A(line17), .Y(MiscRandomOuts[11]) );
and2 MRC19( .A(ContPar2), .B(line17), .Y(line19) );
inv MRC20( .A(line19), .Y(MiscRandomOuts[12]) );
nand2 MRC21( .A(ContPar3), .B(line17), .Y(MiscRandomOuts[13]) );
and3 MRC22( .A(MiscRandomIns[6]), .B(MiscRandomIns[7]),
.C(MiscRandomIns[5]), .Y(line22) );
inv MRC23( .A(line22), .Y(MiscRandomOuts[14]) );
and4 MRC24( .A(MiscRandomIns[5]), .B(MiscRandomIns[9]), .C(MiscRandomIns[8]),
.D(Lambda), .Y(line24) );
inv MRC25( .A(line24), .Y(MiscRandomOuts[15]) );
and2 MRC26( .A(MiscRandomIns[10]), .B(MiscRandomIns[11]), .Y(line26) );
inv MRC27( .A(line26), .Y(line27) );
and4 MRC28( .A(MiscRandomIns[5]), .B(MiscRandomIns[9]), .C(Lambda),
.D(line27), .Y(line28) );
inv MRC29( .A(line28), .Y(MiscRandomOuts[16]) );
and4 MRC30( .A(Y2bus[2]), .B(Y2bus[3]), .C(Y2bus[4]), .D(Y2bus[5]),
.Y(line30) );
inv MRC31( .A(line30), .Y(MiscRandomOuts[17]) );
endmodule // MiscRandomCircuit
/***************************************************************************/
/***************************************************************************/
module AN18( Inbus, ContEq, Out );
input [16:0] Inbus;
input ContEq;
output Out;
and5 A0( .A(Inbus[0]), .B(Inbus[1]), .C(Inbus[2]),
.D(Inbus[3]), .E(Inbus[4]), .Y(line0) ),
A1( .A(Inbus[5]), .B(Inbus[6]), .C(Inbus[7]),
.D(Inbus[8]), .E(Inbus[9]), .Y(line1) );
and2 A2( .A(line0), .B(line1) ,.Y(line2) ),
A3( .A(Inbus[10]), .B(Inbus[11]), .Y(line3) );
and5 A4( .A(Inbus[12]), .B(Inbus[13]), .C(Inbus[14]),
.D(Inbus[15]), .E(Inbus[16]), .Y(line4) );
and2 A5( .A(line3), .B(line4), .Y(line5) );
and3 A6( .A(line2), .B(line5), .C(ContEq), .Y(Out) );
endmodule // AN18
/********************************************/
module XOR2a ( A, B, Y );
input A, B;
output Y;
inv Xo0( .A(A), .Y(NotA) ),
Xo1( .A(B), .Y(NotB) );
nand2 Xo2( .A(NotA), .B(B), .Y(line2) ),
Xo3( .A(NotB), .B(A), .Y(line3) ),
Xo4( .A(line2), .B(line3), .Y(Y) );
endmodule // XOR2a
/********************************************/
module XOR2b ( A, B, Y );
input A, B;
output Y;
wire NotAB;
nand2 Xo1_0( .A(A), .B(B), .Y(NotAB) );
and2 Xo1_1( .A(A), .B(NotAB), .Y(line1) ),
Xo1_2( .A(NotAB), .B(B), .Y(line2) );
or2 Xo1_3( .A(line1), .B(line2), .Y(Y) );
endmodule // XOR2b
/********************************************/
module XOR3a( A, B, C, Y);
input A, B, C;
output Y;
inv Xo3_0( .A(A), .Y(NotA) ),
Xo3_1( .A(B), .Y(NotB) ),
Xo3_2( .A(C), .Y(NotC) );
and3 Xo3_3( .A(NotA), .B(NotB), .C(C), .Y(line3) ),
Xo3_4( .A(NotA), .B(B), .C(NotC), .Y(line4) ),
Xo3_5( .A(A), .B(NotB), .C(NotC), .Y(line5) ),
Xo3_6( .A(A), .B(B), .C(C), .Y(line6) );
nor2 Xo3_7( .A(line3), .B(line4), .Y(line7) ),
Xo3_8( .A(line5), .B(line6), .Y(line8) );
nand2 Xo3_9( .A(line7), .B(line8), .Y(Y) );
endmodule // XOR3a
/********************************************/
module RedundantInv( A, Y );
input A;
output Y;
inv RIV0( .A(A), .Y(NotA) );
and2 RIV1( .A(A), .B(NotA), .Y(line1) ); // line1=logic 0
or2 RIV2( .A(line1), .B(NotA), .Y(Y) );
endmodule // RedundantIV
|
Added c2670/flat2670.v.
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436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 | /**************************************************************************** * * * FLAT VERSION of HIGH-LEVEL MODEL for c2670 * * * * * * Generated by: Hakan Yalcin (hyalcin@cadence.com) * * Verified by: Jonathan David Hauke (jhauke@eecs.umich.edu) * * * * Oct 20, 1998 * * * ****************************************************************************/ // Flat Verilog File module c2670g ( in81, in92, in91, in90, in89, in88, in87, in86, in85, in93, in43, in54, in53, in52, in51, in50, in49, in48, in47, in55, in56, in66, in65, in64, in63, in62, in61, in60, in67, in68, in79, in78, in77, in76, in75, in74, in73, in72, in80, in131, in141, in140, in139, in138, in137, in136, in135, in142, in95, in105, in104, in103, in102, in101, in100, in99, in106, in119, in129, in128, in127, in126, in125, in124, in123, in130, in107, in117, in116, in115, in114, in113, in112, in111, in118, in1971, in1966, in1961, in1956, in1348, in1341, in2090, in2084, in2078, in2072, in2067, in1996, in1991, in1986, in1981, in1976, in2096, in2100, in2678, in2474, in2427, in2430, in2451, in2454, in2443, in2446, in2435, in2438, in24, in6, in23, in22, in21, in5, in20, in4, in19, in28, in35, in34, in27, in33, in26, in32, in25, in651, in543, in2105, in2104, in1384, in40, in16, in29, in11, in8, in37, in14, in44, in132, in82, in96, in69, in120, in57, in108, in2106, in567, in559, in860, in868, in452, in2066, in1083, in94, in7, in661, in1, in2, in3, in15, in36, in483, in169, in174, in177, in178, in179, in180, in181, in182, in183, in184, in185, in186, in189, in190, in191, in192, in193, in194, in195, in196, in197, in198, in199, in200, in201, in202, in203, in204, in205, in206, in207, in208, in209, in210, in211, in212, in213, in214, in215, in239, in240, in241, in242, in243, in244, in245, in246, in247, in248, in249, in250, in251, in252, in253, in254, in255, in256, in257, in262, in263, in264, in265, in266, in267, in268, in269, in270, in271, in272, in273, in274, in275, in276, in277, in278, in279, out329, out231, out311, out150, out308, out225, out395, out397, out227, out229, out401, out319, out325, out261, out220, out221, out219, out218, out235, out236, out237, out238, out335, out350, out391, out409, out337, out384, out411, out367, out369, out173, out295, out331, out145, out148, out282, out323, out284, out321, out297, out280, out153, out290, out305, out288, out303, out286, out301, out299, out166, out168, out171, out162, out160, out164, out156, out223, out217, out234, out259, out176, out188, out158, out169, out174, out177, out178, out179, out180, out181, out182, out183, out184, out185, out186, out189, out190, out191, out192, out193, out194, out195, out196, out197, out198, out199, out200, out201, out202, out203, out204, out205, out206, out207, out208, out209, out210, out211, out212, out213, out214, out215, out239, out240, out241, out242, out243, out244, out245, out246, out247, out248, out249, out250, out251, out252, out253, out254, out255, out256, out257, out262, out263, out264, out265, out266, out267, out268, out269, out270, out271, out272, out273, out274, out275, out276, out277, out278, out279); input in81, in92, in91, in90, in89, in88, in87, in86, in85, in93, in43, in54, in53, in52, in51, in50, in49, in48, in47, in55, in56, in66, in65, in64, in63, in62, in61, in60, in67, in68, in79, in78, in77, in76, in75, in74, in73, in72, in80, in131, in141, in140, in139, in138, in137, in136, in135, in142, in95, in105, in104, in103, in102, in101, in100, in99, in106, in119, in129, in128, in127, in126, in125, in124, in123, in130, in107, in117, in116, in115, in114, in113, in112, in111, in118, in1971, in1966, in1961, in1956, in1348, in1341, in2090, in2084, in2078, in2072, in2067, in1996, in1991, in1986, in1981, in1976, in2096, in2100, in2678, in2474, in2427, in2430, in2451, in2454, in2443, in2446, in2435, in2438, in24, in6, in23, in22, in21, in5, in20, in4, in19, in28, in35, in34, in27, in33, in26, in32, in25, in651, in543, in2105, in2104, in1384, in40, in16, in29, in11, in8, in37, in14, in44, in132, in82, in96, in69, in120, in57, in108, in2106, in567, in559, in860, in868, in452, in2066, in1083, in94, in7, in661, in1, in2, in3, in15, in36, in483, in169, in174, in177, in178, in179, in180, in181, in182, in183, in184, in185, in186, in189, in190, in191, in192, in193, in194, in195, in196, in197, in198, in199, in200, in201, in202, in203, in204, in205, in206, in207, in208, in209, in210, in211, in212, in213, in214, in215, in239, in240, in241, in242, in243, in244, in245, in246, in247, in248, in249, in250, in251, in252, in253, in254, in255, in256, in257, in262, in263, in264, in265, in266, in267, in268, in269, in270, in271, in272, in273, in274, in275, in276, in277, in278, in279; output out329, out231, out311, out150, out308, out225, out395, out397, out227, out229, out401, out319, out325, out261, out220, out221, out219, out218, out235, out236, out237, out238, out335, out350, out391, out409, out337, out384, out411, out367, out369, out173, out295, out331, out145, out148, out282, out323, out284, out321, out297, out280, out153, out290, out305, out288, out303, out286, out301, out299, out166, out168, out171, out162, out160, out164, out156, out223, out217, out234, out259, out176, out188, out158, out169, out174, out177, out178, out179, out180, out181, out182, out183, out184, out185, out186, out189, out190, out191, out192, out193, out194, out195, out196, out197, out198, out199, out200, out201, out202, out203, out204, out205, out206, out207, out208, out209, out210, out211, out212, out213, out214, out215, out239, out240, out241, out242, out243, out244, out245, out246, out247, out248, out249, out250, out251, out252, out253, out254, out255, out256, out257, out262, out263, out264, out265, out266, out267, out268, out269, out270, out271, out272, out273, out274, out275, out276, out277, out278, out279; inv M1_Mux0_Mux0(in651, M1_Mux0_Not_Cont0); inv M1_Mux0_Mux1(in543, M1_Mux0_Not_Cont1); and3 M1_Mux0_Mux2(in81, M1_Mux0_Not_Cont0, M1_Mux0_Not_Cont1, M1_Mux0_line2); and3 M1_Mux0_Mux3(in43, M1_Mux0_Not_Cont0, in543, M1_Mux0_line3); and3 M1_Mux0_Mux4(in56, in651, M1_Mux0_Not_Cont1, M1_Mux0_line4); and3 M1_Mux0_Mux5(in68, in651, in543, M1_Mux0_line5); or4 M1_Mux0_Mux6(M1_Mux0_line2, M1_Mux0_line3, M1_Mux0_line4, M1_Mux0_line5, Abus_0); inv M1_Mux1_Mux0(in651, M1_Mux1_Not_Cont0); inv M1_Mux1_Mux1(in543, M1_Mux1_Not_Cont1); and3 M1_Mux1_Mux2(in92, M1_Mux1_Not_Cont0, M1_Mux1_Not_Cont1, M1_Mux1_line2); and3 M1_Mux1_Mux3(in54, M1_Mux1_Not_Cont0, in543, M1_Mux1_line3); and3 M1_Mux1_Mux4(in66, in651, M1_Mux1_Not_Cont1, M1_Mux1_line4); and3 M1_Mux1_Mux5(in79, in651, in543, M1_Mux1_line5); or4 M1_Mux1_Mux6(M1_Mux1_line2, M1_Mux1_line3, M1_Mux1_line4, M1_Mux1_line5, Abus_1); inv M1_Mux2_Mux0(in651, M1_Mux2_Not_Cont0); inv M1_Mux2_Mux1(in543, M1_Mux2_Not_Cont1); and3 M1_Mux2_Mux2(in91, M1_Mux2_Not_Cont0, M1_Mux2_Not_Cont1, M1_Mux2_line2); and3 M1_Mux2_Mux3(in53, M1_Mux2_Not_Cont0, in543, M1_Mux2_line3); and3 M1_Mux2_Mux4(in65, in651, M1_Mux2_Not_Cont1, M1_Mux2_line4); and3 M1_Mux2_Mux5(in78, in651, in543, M1_Mux2_line5); or4 M1_Mux2_Mux6(M1_Mux2_line2, M1_Mux2_line3, M1_Mux2_line4, M1_Mux2_line5, Abus_2); inv M1_Mux3_Mux0(in651, M1_Mux3_Not_Cont0); inv M1_Mux3_Mux1(in543, M1_Mux3_Not_Cont1); and3 M1_Mux3_Mux2(in90, M1_Mux3_Not_Cont0, M1_Mux3_Not_Cont1, M1_Mux3_line2); and3 M1_Mux3_Mux3(in52, M1_Mux3_Not_Cont0, in543, M1_Mux3_line3); and3 M1_Mux3_Mux4(in64, in651, M1_Mux3_Not_Cont1, M1_Mux3_line4); and3 M1_Mux3_Mux5(in77, in651, in543, M1_Mux3_line5); or4 M1_Mux3_Mux6(M1_Mux3_line2, M1_Mux3_line3, M1_Mux3_line4, M1_Mux3_line5, Abus_3); inv M1_Mux4_Mux0(in651, M1_Mux4_Not_Cont0); inv M1_Mux4_Mux1(in543, M1_Mux4_Not_Cont1); and3 M1_Mux4_Mux2(in89, M1_Mux4_Not_Cont0, M1_Mux4_Not_Cont1, M1_Mux4_line2); and3 M1_Mux4_Mux3(in51, M1_Mux4_Not_Cont0, in543, M1_Mux4_line3); and3 M1_Mux4_Mux4(in63, in651, M1_Mux4_Not_Cont1, M1_Mux4_line4); and3 M1_Mux4_Mux5(in76, in651, in543, M1_Mux4_line5); or4 M1_Mux4_Mux6(M1_Mux4_line2, M1_Mux4_line3, M1_Mux4_line4, M1_Mux4_line5, Abus_4); inv M1_Mux5_Mux0(in651, M1_Mux5_Not_Cont0); inv M1_Mux5_Mux1(in543, M1_Mux5_Not_Cont1); and3 M1_Mux5_Mux2(in88, M1_Mux5_Not_Cont0, M1_Mux5_Not_Cont1, M1_Mux5_line2); and3 M1_Mux5_Mux3(in50, M1_Mux5_Not_Cont0, in543, M1_Mux5_line3); and3 M1_Mux5_Mux4(in62, in651, M1_Mux5_Not_Cont1, M1_Mux5_line4); and3 M1_Mux5_Mux5(in75, in651, in543, M1_Mux5_line5); or4 M1_Mux5_Mux6(M1_Mux5_line2, M1_Mux5_line3, M1_Mux5_line4, M1_Mux5_line5, Abus_5); inv M1_Mux6_Mux0(in651, M1_Mux6_Not_Cont0); inv M1_Mux6_Mux1(in543, M1_Mux6_Not_Cont1); and3 M1_Mux6_Mux2(in87, M1_Mux6_Not_Cont0, M1_Mux6_Not_Cont1, M1_Mux6_line2); and3 M1_Mux6_Mux3(in49, M1_Mux6_Not_Cont0, in543, M1_Mux6_line3); and3 M1_Mux6_Mux4(vdd, in651, M1_Mux6_Not_Cont1, M1_Mux6_line4); and3 M1_Mux6_Mux5(in74, in651, in543, M1_Mux6_line5); or4 M1_Mux6_Mux6(M1_Mux6_line2, M1_Mux6_line3, M1_Mux6_line4, M1_Mux6_line5, Abus_6); inv M1_Mux7_Mux0(in651, M1_Mux7_Not_Cont0); inv M1_Mux7_Mux1(in543, M1_Mux7_Not_Cont1); and3 M1_Mux7_Mux2(in86, M1_Mux7_Not_Cont0, M1_Mux7_Not_Cont1, M1_Mux7_line2); and3 M1_Mux7_Mux3(in48, M1_Mux7_Not_Cont0, in543, M1_Mux7_line3); and3 M1_Mux7_Mux4(in61, in651, M1_Mux7_Not_Cont1, M1_Mux7_line4); and3 M1_Mux7_Mux5(in73, in651, in543, M1_Mux7_line5); or4 M1_Mux7_Mux6(M1_Mux7_line2, M1_Mux7_line3, M1_Mux7_line4, M1_Mux7_line5, Abus_7); inv M1_Mux8_Mux0(in651, M1_Mux8_Not_Cont0); inv M1_Mux8_Mux1(in543, M1_Mux8_Not_Cont1); and3 M1_Mux8_Mux2(in85, M1_Mux8_Not_Cont0, M1_Mux8_Not_Cont1, M1_Mux8_line2); and3 M1_Mux8_Mux3(in47, M1_Mux8_Not_Cont0, in543, M1_Mux8_line3); and3 M1_Mux8_Mux4(in60, in651, M1_Mux8_Not_Cont1, M1_Mux8_line4); and3 M1_Mux8_Mux5(in72, in651, in543, M1_Mux8_line5); or4 M1_Mux8_Mux6(M1_Mux8_line2, M1_Mux8_line3, M1_Mux8_line4, M1_Mux8_line5, Abus_8); inv M1_Mux9_Mux0(in651, M1_Mux9_Not_Cont0); inv M1_Mux9_Mux1(in543, M1_Mux9_Not_Cont1); and3 M1_Mux9_Mux2(in93, M1_Mux9_Not_Cont0, M1_Mux9_Not_Cont1, M1_Mux9_line2); and3 M1_Mux9_Mux3(in55, M1_Mux9_Not_Cont0, in543, M1_Mux9_line3); and3 M1_Mux9_Mux4(in67, in651, M1_Mux9_Not_Cont1, M1_Mux9_line4); and3 M1_Mux9_Mux5(in80, in651, in543, M1_Mux9_line5); or4 M1_Mux9_Mux6(M1_Mux9_line2, M1_Mux9_line3, M1_Mux9_line4, M1_Mux9_line5, Abus_9); inv M2_Mux0_Mux0(in2105, M2_Mux0_Not_Cont0); inv M2_Mux0_Mux1(in2104, M2_Mux0_Not_Cont1); and3 M2_Mux0_Mux2(in131, M2_Mux0_Not_Cont0, M2_Mux0_Not_Cont1, M2_Mux0_line2); and3 M2_Mux0_Mux3(in95, M2_Mux0_Not_Cont0, in2104, M2_Mux0_line3); and3 M2_Mux0_Mux4(in119, in2105, M2_Mux0_Not_Cont1, M2_Mux0_line4); and3 M2_Mux0_Mux5(in107, in2105, in2104, M2_Mux0_line5); or4 M2_Mux0_Mux6(M2_Mux0_line2, M2_Mux0_line3, M2_Mux0_line4, M2_Mux0_line5, Bbus_0); inv M2_Mux1_Mux0(in2105, M2_Mux1_Not_Cont0); inv M2_Mux1_Mux1(in2104, M2_Mux1_Not_Cont1); and3 M2_Mux1_Mux2(in141, M2_Mux1_Not_Cont0, M2_Mux1_Not_Cont1, M2_Mux1_line2); and3 M2_Mux1_Mux3(in105, M2_Mux1_Not_Cont0, in2104, M2_Mux1_line3); and3 M2_Mux1_Mux4(in129, in2105, M2_Mux1_Not_Cont1, M2_Mux1_line4); and3 M2_Mux1_Mux5(in117, in2105, in2104, M2_Mux1_line5); or4 M2_Mux1_Mux6(M2_Mux1_line2, M2_Mux1_line3, M2_Mux1_line4, M2_Mux1_line5, Bbus_1); inv M2_Mux2_Mux0(in2105, M2_Mux2_Not_Cont0); inv M2_Mux2_Mux1(in2104, M2_Mux2_Not_Cont1); and3 M2_Mux2_Mux2(in140, M2_Mux2_Not_Cont0, M2_Mux2_Not_Cont1, M2_Mux2_line2); and3 M2_Mux2_Mux3(in104, M2_Mux2_Not_Cont0, in2104, M2_Mux2_line3); and3 M2_Mux2_Mux4(in128, in2105, M2_Mux2_Not_Cont1, M2_Mux2_line4); and3 M2_Mux2_Mux5(in116, in2105, in2104, M2_Mux2_line5); or4 M2_Mux2_Mux6(M2_Mux2_line2, M2_Mux2_line3, M2_Mux2_line4, M2_Mux2_line5, Bbus_2); inv M2_Mux3_Mux0(in2105, M2_Mux3_Not_Cont0); inv M2_Mux3_Mux1(in2104, M2_Mux3_Not_Cont1); and3 M2_Mux3_Mux2(in139, M2_Mux3_Not_Cont0, M2_Mux3_Not_Cont1, M2_Mux3_line2); and3 M2_Mux3_Mux3(in103, M2_Mux3_Not_Cont0, in2104, M2_Mux3_line3); and3 M2_Mux3_Mux4(in127, in2105, M2_Mux3_Not_Cont1, M2_Mux3_line4); and3 M2_Mux3_Mux5(in115, in2105, in2104, M2_Mux3_line5); or4 M2_Mux3_Mux6(M2_Mux3_line2, M2_Mux3_line3, M2_Mux3_line4, M2_Mux3_line5, Bbus_3); inv M2_Mux4_Mux0(in2105, M2_Mux4_Not_Cont0); inv M2_Mux4_Mux1(in2104, M2_Mux4_Not_Cont1); and3 M2_Mux4_Mux2(in138, M2_Mux4_Not_Cont0, M2_Mux4_Not_Cont1, M2_Mux4_line2); and3 M2_Mux4_Mux3(in102, M2_Mux4_Not_Cont0, in2104, M2_Mux4_line3); and3 M2_Mux4_Mux4(in126, in2105, M2_Mux4_Not_Cont1, M2_Mux4_line4); and3 M2_Mux4_Mux5(in114, in2105, in2104, M2_Mux4_line5); or4 M2_Mux4_Mux6(M2_Mux4_line2, M2_Mux4_line3, M2_Mux4_line4, M2_Mux4_line5, Bbus_4); inv M2_Mux5_Mux0(in2105, M2_Mux5_Not_Cont0); inv M2_Mux5_Mux1(in2104, M2_Mux5_Not_Cont1); and3 M2_Mux5_Mux2(in137, M2_Mux5_Not_Cont0, M2_Mux5_Not_Cont1, M2_Mux5_line2); and3 M2_Mux5_Mux3(in101, M2_Mux5_Not_Cont0, in2104, M2_Mux5_line3); and3 M2_Mux5_Mux4(in125, in2105, M2_Mux5_Not_Cont1, M2_Mux5_line4); and3 M2_Mux5_Mux5(in113, in2105, in2104, M2_Mux5_line5); or4 M2_Mux5_Mux6(M2_Mux5_line2, M2_Mux5_line3, M2_Mux5_line4, M2_Mux5_line5, Bbus_5); inv M2_Mux6_Mux0(in2105, M2_Mux6_Not_Cont0); inv M2_Mux6_Mux1(in2104, M2_Mux6_Not_Cont1); and3 M2_Mux6_Mux2(in136, M2_Mux6_Not_Cont0, M2_Mux6_Not_Cont1, M2_Mux6_line2); and3 M2_Mux6_Mux3(in100, M2_Mux6_Not_Cont0, in2104, M2_Mux6_line3); and3 M2_Mux6_Mux4(in124, in2105, M2_Mux6_Not_Cont1, M2_Mux6_line4); and3 M2_Mux6_Mux5(in112, in2105, in2104, M2_Mux6_line5); or4 M2_Mux6_Mux6(M2_Mux6_line2, M2_Mux6_line3, M2_Mux6_line4, M2_Mux6_line5, Bbus_6); inv M2_Mux7_Mux0(in2105, M2_Mux7_Not_Cont0); inv M2_Mux7_Mux1(in2104, M2_Mux7_Not_Cont1); and3 M2_Mux7_Mux2(in135, M2_Mux7_Not_Cont0, M2_Mux7_Not_Cont1, M2_Mux7_line2); and3 M2_Mux7_Mux3(in99, M2_Mux7_Not_Cont0, in2104, M2_Mux7_line3); and3 M2_Mux7_Mux4(in123, in2105, M2_Mux7_Not_Cont1, M2_Mux7_line4); and3 M2_Mux7_Mux5(in111, in2105, in2104, M2_Mux7_line5); or4 M2_Mux7_Mux6(M2_Mux7_line2, M2_Mux7_line3, M2_Mux7_line4, M2_Mux7_line5, Bbus_7); inv M2_Mux8_Mux0(in2105, M2_Mux8_Not_Cont0); inv M2_Mux8_Mux1(in2104, M2_Mux8_Not_Cont1); and3 M2_Mux8_Mux2(in142, M2_Mux8_Not_Cont0, M2_Mux8_Not_Cont1, M2_Mux8_line2); and3 M2_Mux8_Mux3(in106, M2_Mux8_Not_Cont0, in2104, M2_Mux8_line3); and3 M2_Mux8_Mux4(in130, in2105, M2_Mux8_Not_Cont1, M2_Mux8_line4); and3 M2_Mux8_Mux5(in118, in2105, in2104, M2_Mux8_line5); or4 M2_Mux8_Mux6(M2_Mux8_line2, M2_Mux8_line3, M2_Mux8_line4, M2_Mux8_line5, Bbus_8); inv M2_Mux9_Mux0(in2105, M2_Mux9_Not_Cont0); inv M2_Mux9_Mux1(in2104, M2_Mux9_Not_Cont1); and3 M2_Mux9_Mux2(vdd, M2_Mux9_Not_Cont0, M2_Mux9_Not_Cont1, M2_Mux9_line2); and3 M2_Mux9_Mux3(vdd, M2_Mux9_Not_Cont0, in2104, M2_Mux9_line3); and3 M2_Mux9_Mux4(vdd, in2105, M2_Mux9_Not_Cont1, M2_Mux9_line4); and3 M2_Mux9_Mux5(vdd, in2105, in2104, M2_Mux9_line5); or4 M2_Mux9_Mux6(M2_Mux9_line2, M2_Mux9_line3, M2_Mux9_line4, M2_Mux9_line5, Bbus_9); inv M3_UM3_0(Bbus_5, M3_NotB5); inv M3_UM3_1(in1384, M3_NotMask1); and2 M3_UM3_2(Bbus_4, M3_NotMask1, M3_line2); and3 M3_UM3_3(M3_NotB5, M3_line2, in40, ContAlpha); inv M3_UM3_4(M3_line2, M3_line4); and3 M3_UM3_5(in40, M3_line4, M3_NotB5, ContBeta); and2 M4_UM4_0_MB0(Abus_4, in8, M4_XMbus_4); and2 M4_UM4_0_MB1(Abus_5, in8, M4_XMbus_5); inv M4_UM4_0_MB2(ContAlpha, M4_UM4_0_NotAlpha); and2 M4_UM4_0_MB3(Abus_6, M4_UM4_0_NotAlpha, M4_UM4_0_line3); and2 M4_UM4_0_MB4(M4_UM4_0_line3, in8, M4_XMbus_6); and2 M4_UM4_0_MB5(Abus_7, M4_UM4_0_NotAlpha, M4_UM4_0_line5); and2 M4_UM4_0_MB6(M4_UM4_0_line5, in8, M4_XMbus_7); and2 M4_UM4_0_MB7(Abus_8, M4_UM4_0_NotAlpha, M4_UM4_0_line7); and2 M4_UM4_0_MB8(M4_UM4_0_line7, ContBeta, M4_XMbus_8); and2 M4_UM4_0_MB9(Bbus_0, M4_UM4_0_NotAlpha, M4_UM4_0_line9); and2 M4_UM4_0_MB10(M4_UM4_0_line9, ContBeta, M4_XMbus_9); and2 M4_UM4_0_MB11(Bbus_1, M4_UM4_0_NotAlpha, M4_UM4_0_line11); and2 M4_UM4_0_MB12(M4_UM4_0_line11, ContBeta, M4_XMbus_10); and2 M4_UM4_0_MB13(Bbus_2, M4_UM4_0_NotAlpha, M4_UM4_0_line13); and2 M4_UM4_0_MB14(M4_UM4_0_line13, ContBeta, M4_XMbus_11); and2 M4_UM4_1_MB0(Ybus_4, in8, M4_YMbus_4); and2 M4_UM4_1_MB1(Ybus_5, in8, M4_YMbus_5); inv M4_UM4_1_MB2(ContAlpha, M4_UM4_1_NotAlpha); and2 M4_UM4_1_MB3(Ybus_6, M4_UM4_1_NotAlpha, M4_UM4_1_line3); and2 M4_UM4_1_MB4(M4_UM4_1_line3, in8, M4_YMbus_6); and2 M4_UM4_1_MB5(Ybus_7, M4_UM4_1_NotAlpha, M4_UM4_1_line5); and2 M4_UM4_1_MB6(M4_UM4_1_line5, in8, M4_YMbus_7); and2 M4_UM4_1_MB7(Ybus_8, M4_UM4_1_NotAlpha, M4_UM4_1_line7); and2 M4_UM4_1_MB8(M4_UM4_1_line7, ContBeta, M4_YMbus_8); and2 M4_UM4_1_MB9(Ybus_9, M4_UM4_1_NotAlpha, M4_UM4_1_line9); and2 M4_UM4_1_MB10(M4_UM4_1_line9, ContBeta, M4_YMbus_9); and2 M4_UM4_1_MB11(Ybus_10, M4_UM4_1_NotAlpha, M4_UM4_1_line11); and2 M4_UM4_1_MB12(M4_UM4_1_line11, ContBeta, M4_YMbus_10); and2 M4_UM4_1_MB13(Ybus_11, M4_UM4_1_NotAlpha, M4_UM4_1_line13); and2 M4_UM4_1_MB14(M4_UM4_1_line13, ContBeta, M4_YMbus_11); inv M4_UM4_2_Inv12_0(Abus_0, M4_Not_XMbus_0); inv M4_UM4_2_Inv12_1(Abus_1, M4_Not_XMbus_1); inv M4_UM4_2_Inv12_2(Abus_2, M4_Not_XMbus_2); inv M4_UM4_2_Inv12_3(Abus_3, M4_Not_XMbus_3); inv M4_UM4_2_Inv12_4(M4_XMbus_4, M4_Not_XMbus_4); inv M4_UM4_2_Inv12_5(M4_XMbus_5, M4_Not_XMbus_5); inv M4_UM4_2_Inv12_6(M4_XMbus_6, M4_Not_XMbus_6); inv M4_UM4_2_Inv12_7(M4_XMbus_7, M4_Not_XMbus_7); inv M4_UM4_2_Inv12_8(M4_XMbus_8, M4_Not_XMbus_8); inv M4_UM4_2_Inv12_9(M4_XMbus_9, M4_Not_XMbus_9); inv M4_UM4_2_Inv12_10(M4_XMbus_10, M4_Not_XMbus_10); inv M4_UM4_2_Inv12_11(M4_XMbus_11, M4_Not_XMbus_11); and2 M4_UM4_3_GP_CalGP0(M4_Not_XMbus_0, Ybus_0, M4_UM4_3_Gbus_0); and2 M4_UM4_3_GP_CalGP1(M4_Not_XMbus_1, Ybus_1, M4_UM4_3_Gbus_1); and2 M4_UM4_3_GP_CalGP2(M4_Not_XMbus_2, Ybus_2, M4_UM4_3_Gbus_2); and2 M4_UM4_3_GP_CalGP3(M4_Not_XMbus_3, Ybus_3, M4_UM4_3_Gbus_3); and2 M4_UM4_3_GP_CalGP4(M4_Not_XMbus_4, M4_YMbus_4, M4_UM4_3_Gbus_4); and2 M4_UM4_3_GP_CalGP5(M4_Not_XMbus_5, M4_YMbus_5, M4_UM4_3_Gbus_5); and2 M4_UM4_3_GP_CalGP6(M4_Not_XMbus_6, M4_YMbus_6, M4_UM4_3_Gbus_6); and2 M4_UM4_3_GP_CalGP7(M4_Not_XMbus_7, M4_YMbus_7, M4_UM4_3_Gbus_7); and2 M4_UM4_3_GP_CalGP8(M4_Not_XMbus_8, M4_YMbus_8, M4_UM4_3_Gbus_8); and2 M4_UM4_3_GP_CalGP9(M4_Not_XMbus_9, M4_YMbus_9, M4_UM4_3_Gbus_9); and2 M4_UM4_3_GP_CalGP10(M4_Not_XMbus_10, M4_YMbus_10, M4_UM4_3_Gbus_10); and2 M4_UM4_3_GP_CalGP11(M4_Not_XMbus_11, M4_YMbus_11, M4_UM4_3_Gbus_11); inv M4_UM4_3_GP_CalGP12_Xo0(M4_Not_XMbus_0, M4_UM4_3_GP_CalGP12_NotA); inv M4_UM4_3_GP_CalGP12_Xo1(Ybus_0, M4_UM4_3_GP_CalGP12_NotB); nand2 M4_UM4_3_GP_CalGP12_Xo2(M4_UM4_3_GP_CalGP12_NotA, Ybus_0, M4_UM4_3_GP_CalGP12_line2); nand2 M4_UM4_3_GP_CalGP12_Xo3(M4_UM4_3_GP_CalGP12_NotB, M4_Not_XMbus_0, M4_UM4_3_GP_CalGP12_line3); nand2 M4_UM4_3_GP_CalGP12_Xo4(M4_UM4_3_GP_CalGP12_line2, M4_UM4_3_GP_CalGP12_line3, M4_UM4_3_Pbus_0); inv M4_UM4_3_GP_CalGP13_Xo0(M4_Not_XMbus_1, M4_UM4_3_GP_CalGP13_NotA); inv M4_UM4_3_GP_CalGP13_Xo1(Ybus_1, M4_UM4_3_GP_CalGP13_NotB); nand2 M4_UM4_3_GP_CalGP13_Xo2(M4_UM4_3_GP_CalGP13_NotA, Ybus_1, M4_UM4_3_GP_CalGP13_line2); nand2 M4_UM4_3_GP_CalGP13_Xo3(M4_UM4_3_GP_CalGP13_NotB, M4_Not_XMbus_1, M4_UM4_3_GP_CalGP13_line3); nand2 M4_UM4_3_GP_CalGP13_Xo4(M4_UM4_3_GP_CalGP13_line2, M4_UM4_3_GP_CalGP13_line3, M4_UM4_3_Pbus_1); inv M4_UM4_3_GP_CalGP14_Xo0(M4_Not_XMbus_2, M4_UM4_3_GP_CalGP14_NotA); inv M4_UM4_3_GP_CalGP14_Xo1(Ybus_2, M4_UM4_3_GP_CalGP14_NotB); nand2 M4_UM4_3_GP_CalGP14_Xo2(M4_UM4_3_GP_CalGP14_NotA, Ybus_2, M4_UM4_3_GP_CalGP14_line2); nand2 M4_UM4_3_GP_CalGP14_Xo3(M4_UM4_3_GP_CalGP14_NotB, M4_Not_XMbus_2, M4_UM4_3_GP_CalGP14_line3); nand2 M4_UM4_3_GP_CalGP14_Xo4(M4_UM4_3_GP_CalGP14_line2, M4_UM4_3_GP_CalGP14_line3, M4_UM4_3_Pbus_2); inv M4_UM4_3_GP_CalGP15_Xo0(M4_Not_XMbus_3, M4_UM4_3_GP_CalGP15_NotA); inv M4_UM4_3_GP_CalGP15_Xo1(Ybus_3, M4_UM4_3_GP_CalGP15_NotB); nand2 M4_UM4_3_GP_CalGP15_Xo2(M4_UM4_3_GP_CalGP15_NotA, Ybus_3, M4_UM4_3_GP_CalGP15_line2); nand2 M4_UM4_3_GP_CalGP15_Xo3(M4_UM4_3_GP_CalGP15_NotB, M4_Not_XMbus_3, M4_UM4_3_GP_CalGP15_line3); nand2 M4_UM4_3_GP_CalGP15_Xo4(M4_UM4_3_GP_CalGP15_line2, M4_UM4_3_GP_CalGP15_line3, M4_UM4_3_Pbus_3); inv M4_UM4_3_GP_CalGP16_Xo0(M4_Not_XMbus_4, M4_UM4_3_GP_CalGP16_NotA); inv M4_UM4_3_GP_CalGP16_Xo1(M4_YMbus_4, M4_UM4_3_GP_CalGP16_NotB); nand2 M4_UM4_3_GP_CalGP16_Xo2(M4_UM4_3_GP_CalGP16_NotA, M4_YMbus_4, M4_UM4_3_GP_CalGP16_line2); nand2 M4_UM4_3_GP_CalGP16_Xo3(M4_UM4_3_GP_CalGP16_NotB, M4_Not_XMbus_4, M4_UM4_3_GP_CalGP16_line3); nand2 M4_UM4_3_GP_CalGP16_Xo4(M4_UM4_3_GP_CalGP16_line2, M4_UM4_3_GP_CalGP16_line3, M4_UM4_3_Pbus_4); inv M4_UM4_3_GP_CalGP17_Xo0(M4_Not_XMbus_5, M4_UM4_3_GP_CalGP17_NotA); inv M4_UM4_3_GP_CalGP17_Xo1(M4_YMbus_5, M4_UM4_3_GP_CalGP17_NotB); nand2 M4_UM4_3_GP_CalGP17_Xo2(M4_UM4_3_GP_CalGP17_NotA, M4_YMbus_5, M4_UM4_3_GP_CalGP17_line2); nand2 M4_UM4_3_GP_CalGP17_Xo3(M4_UM4_3_GP_CalGP17_NotB, M4_Not_XMbus_5, M4_UM4_3_GP_CalGP17_line3); nand2 M4_UM4_3_GP_CalGP17_Xo4(M4_UM4_3_GP_CalGP17_line2, M4_UM4_3_GP_CalGP17_line3, M4_UM4_3_Pbus_5); inv M4_UM4_3_GP_CalGP18_Xo0(M4_Not_XMbus_6, M4_UM4_3_GP_CalGP18_NotA); inv M4_UM4_3_GP_CalGP18_Xo1(M4_YMbus_6, M4_UM4_3_GP_CalGP18_NotB); nand2 M4_UM4_3_GP_CalGP18_Xo2(M4_UM4_3_GP_CalGP18_NotA, M4_YMbus_6, M4_UM4_3_GP_CalGP18_line2); nand2 M4_UM4_3_GP_CalGP18_Xo3(M4_UM4_3_GP_CalGP18_NotB, M4_Not_XMbus_6, M4_UM4_3_GP_CalGP18_line3); nand2 M4_UM4_3_GP_CalGP18_Xo4(M4_UM4_3_GP_CalGP18_line2, M4_UM4_3_GP_CalGP18_line3, M4_UM4_3_Pbus_6); inv M4_UM4_3_GP_CalGP19_Xo0(M4_Not_XMbus_7, M4_UM4_3_GP_CalGP19_NotA); inv M4_UM4_3_GP_CalGP19_Xo1(M4_YMbus_7, M4_UM4_3_GP_CalGP19_NotB); nand2 M4_UM4_3_GP_CalGP19_Xo2(M4_UM4_3_GP_CalGP19_NotA, M4_YMbus_7, M4_UM4_3_GP_CalGP19_line2); nand2 M4_UM4_3_GP_CalGP19_Xo3(M4_UM4_3_GP_CalGP19_NotB, M4_Not_XMbus_7, M4_UM4_3_GP_CalGP19_line3); nand2 M4_UM4_3_GP_CalGP19_Xo4(M4_UM4_3_GP_CalGP19_line2, M4_UM4_3_GP_CalGP19_line3, M4_UM4_3_Pbus_7); inv M4_UM4_3_GP_CalGP20_Xo0(M4_Not_XMbus_8, M4_UM4_3_GP_CalGP20_NotA); inv M4_UM4_3_GP_CalGP20_Xo1(M4_YMbus_8, M4_UM4_3_GP_CalGP20_NotB); nand2 M4_UM4_3_GP_CalGP20_Xo2(M4_UM4_3_GP_CalGP20_NotA, M4_YMbus_8, M4_UM4_3_GP_CalGP20_line2); nand2 M4_UM4_3_GP_CalGP20_Xo3(M4_UM4_3_GP_CalGP20_NotB, M4_Not_XMbus_8, M4_UM4_3_GP_CalGP20_line3); nand2 M4_UM4_3_GP_CalGP20_Xo4(M4_UM4_3_GP_CalGP20_line2, M4_UM4_3_GP_CalGP20_line3, M4_UM4_3_Pbus_8); inv M4_UM4_3_GP_CalGP21_Xo0(M4_Not_XMbus_9, M4_UM4_3_GP_CalGP21_NotA); inv M4_UM4_3_GP_CalGP21_Xo1(M4_YMbus_9, M4_UM4_3_GP_CalGP21_NotB); nand2 M4_UM4_3_GP_CalGP21_Xo2(M4_UM4_3_GP_CalGP21_NotA, M4_YMbus_9, M4_UM4_3_GP_CalGP21_line2); nand2 M4_UM4_3_GP_CalGP21_Xo3(M4_UM4_3_GP_CalGP21_NotB, M4_Not_XMbus_9, M4_UM4_3_GP_CalGP21_line3); nand2 M4_UM4_3_GP_CalGP21_Xo4(M4_UM4_3_GP_CalGP21_line2, M4_UM4_3_GP_CalGP21_line3, M4_UM4_3_Pbus_9); inv M4_UM4_3_GP_CalGP22_Xo0(M4_Not_XMbus_10, M4_UM4_3_GP_CalGP22_NotA); inv M4_UM4_3_GP_CalGP22_Xo1(M4_YMbus_10, M4_UM4_3_GP_CalGP22_NotB); nand2 M4_UM4_3_GP_CalGP22_Xo2(M4_UM4_3_GP_CalGP22_NotA, M4_YMbus_10, M4_UM4_3_GP_CalGP22_line2); nand2 M4_UM4_3_GP_CalGP22_Xo3(M4_UM4_3_GP_CalGP22_NotB, M4_Not_XMbus_10, M4_UM4_3_GP_CalGP22_line3); nand2 M4_UM4_3_GP_CalGP22_Xo4(M4_UM4_3_GP_CalGP22_line2, M4_UM4_3_GP_CalGP22_line3, M4_UM4_3_Pbus_10); inv M4_UM4_3_GP_CalGP23_Xo0(M4_Not_XMbus_11, M4_UM4_3_GP_CalGP23_NotA); inv M4_UM4_3_GP_CalGP23_Xo1(M4_YMbus_11, M4_UM4_3_GP_CalGP23_NotB); nand2 M4_UM4_3_GP_CalGP23_Xo2(M4_UM4_3_GP_CalGP23_NotA, M4_YMbus_11, M4_UM4_3_GP_CalGP23_line2); nand2 M4_UM4_3_GP_CalGP23_Xo3(M4_UM4_3_GP_CalGP23_NotB, M4_Not_XMbus_11, M4_UM4_3_GP_CalGP23_line3); nand2 M4_UM4_3_GP_CalGP23_Xo4(M4_UM4_3_GP_CalGP23_line2, M4_UM4_3_GP_CalGP23_line3, M4_UM4_3_Pbus_11); and2 M4_UM4_3_CalcCy_Cla12_0_Cla3_0(M4_UM4_3_Pbus_2, M4_UM4_3_Gbus_1, M4_UM4_3_CalcCy_Cla12_0_line0); and3 M4_UM4_3_CalcCy_Cla12_0_Cla3_1(M4_UM4_3_Pbus_2, M4_UM4_3_Pbus_1, M4_UM4_3_Gbus_0, M4_UM4_3_CalcCy_Cla12_0_line1); or3 M4_UM4_3_CalcCy_Cla12_0_Cla3_2(M4_UM4_3_Gbus_2, M4_UM4_3_CalcCy_Cla12_0_line0, M4_UM4_3_CalcCy_Cla12_0_line1, M4_UM4_3_CalcCy_OutCarry2_0); and2 M4_UM4_3_CalcCy_Cla12_1_Cla5_0(M4_UM4_3_Pbus_7, M4_UM4_3_Gbus_6, M4_UM4_3_CalcCy_Cla12_1_line0); and3 M4_UM4_3_CalcCy_Cla12_1_Cla5_1(M4_UM4_3_Pbus_7, M4_UM4_3_Pbus_6, M4_UM4_3_Gbus_5, M4_UM4_3_CalcCy_Cla12_1_line1); and4 M4_UM4_3_CalcCy_Cla12_1_Cla5_2(M4_UM4_3_Pbus_7, M4_UM4_3_Pbus_6, M4_UM4_3_Pbus_5, M4_UM4_3_Gbus_4, M4_UM4_3_CalcCy_Cla12_1_line2); and5 M4_UM4_3_CalcCy_Cla12_1_Cla5_3(M4_UM4_3_Pbus_7, M4_UM4_3_Pbus_6, M4_UM4_3_Pbus_5, M4_UM4_3_Pbus_4, M4_UM4_3_Gbus_3, M4_UM4_3_CalcCy_Cla12_1_line3); or5 M4_UM4_3_CalcCy_Cla12_1_Cla5_4(M4_UM4_3_Gbus_7, M4_UM4_3_CalcCy_Cla12_1_line0, M4_UM4_3_CalcCy_Cla12_1_line1, M4_UM4_3_CalcCy_Cla12_1_line2, M4_UM4_3_CalcCy_Cla12_1_line3, M4_UM4_3_CalcCy_OutCarry7_3); and2 M4_UM4_3_CalcCy_Cla12_2_Cla4_0(M4_UM4_3_Pbus_11, M4_UM4_3_Gbus_10, M4_UM4_3_CalcCy_Cla12_2_line0); and3 M4_UM4_3_CalcCy_Cla12_2_Cla4_1(M4_UM4_3_Pbus_11, M4_UM4_3_Pbus_10, M4_UM4_3_Gbus_9, M4_UM4_3_CalcCy_Cla12_2_line1); and4 M4_UM4_3_CalcCy_Cla12_2_Cla4_2(M4_UM4_3_Pbus_11, M4_UM4_3_Pbus_10, M4_UM4_3_Pbus_9, M4_UM4_3_Gbus_8, M4_UM4_3_CalcCy_Cla12_2_line2); or4 M4_UM4_3_CalcCy_Cla12_2_Cla4_3(M4_UM4_3_Gbus_11, M4_UM4_3_CalcCy_Cla12_2_line0, M4_UM4_3_CalcCy_Cla12_2_line1, M4_UM4_3_CalcCy_Cla12_2_line2, M4_UM4_3_CalcCy_OutCarry11_8); and5 M4_UM4_3_CalcCy_Cla12_3(M4_UM4_3_Pbus_3, M4_UM4_3_Pbus_4, M4_UM4_3_Pbus_5, M4_UM4_3_Pbus_6, M4_UM4_3_Pbus_7, M4_UM4_3_CalcCy_Prop7_3); and4 M4_UM4_3_CalcCy_Cla12_4(M4_UM4_3_Pbus_8, M4_UM4_3_Pbus_9, M4_UM4_3_Pbus_10, M4_UM4_3_Pbus_11, M4_UM4_3_CalcCy_Prop11_8); and2 M4_UM4_3_CalcCy_Cla12_5(M4_UM4_3_CalcCy_Prop7_3, M4_UM4_3_CalcCy_OutCarry2_0, M4_UM4_3_CalcCy_line5); or2 M4_UM4_3_CalcCy_Cla12_6(M4_UM4_3_CalcCy_OutCarry7_3, M4_UM4_3_CalcCy_line5, M4_UM4_3_CalcCy_OutCarry7_0); inv M4_UM4_3_CalcCy_Cla12_7(M4_UM4_3_CalcCy_OutCarry7_0, M4_UM4_3_CalcCy_NotOutCarry7_0); or2 M4_UM4_3_CalcCy_Cla12_8(M4_UM4_3_CalcCy_OutCarry11_8, M4_UM4_3_CalcCy_Prop11_8, M4_UM4_3_CalcCy_line8); and2 M4_UM4_3_CalcCy_Cla12_9(M4_UM4_3_CalcCy_NotOutCarry7_0, M4_UM4_3_CalcCy_OutCarry11_8, M4_UM4_3_CalcCy_line9); and2 M4_UM4_3_CalcCy_Cla12_10(M4_UM4_3_CalcCy_line8, M4_UM4_3_CalcCy_OutCarry7_0, M4_UM4_3_CalcCy_line10); or2 M4_UM4_3_CalcCy_Cla12_11(M4_UM4_3_CalcCy_line9, M4_UM4_3_CalcCy_line10, out329); and2 M4_UM4_4_GP_CalGP0(M4_Not_XMbus_0, Ybus_0, M4_UM4_4_Gbus_0); and2 M4_UM4_4_GP_CalGP1(M4_Not_XMbus_1, Ybus_1, M4_UM4_4_Gbus_1); and2 M4_UM4_4_GP_CalGP2(M4_Not_XMbus_2, Ybus_2, M4_UM4_4_Gbus_2); and2 M4_UM4_4_GP_CalGP3(M4_Not_XMbus_3, Ybus_3, M4_UM4_4_Gbus_3); and2 M4_UM4_4_GP_CalGP4(M4_Not_XMbus_4, M4_YMbus_4, M4_UM4_4_Gbus_4); and2 M4_UM4_4_GP_CalGP5(M4_Not_XMbus_5, M4_YMbus_5, M4_UM4_4_Gbus_5); and2 M4_UM4_4_GP_CalGP6(M4_Not_XMbus_6, M4_YMbus_6, M4_UM4_4_Gbus_6); and2 M4_UM4_4_GP_CalGP7(M4_Not_XMbus_7, M4_YMbus_7, M4_UM4_4_Gbus_7); and2 M4_UM4_4_GP_CalGP8(M4_Not_XMbus_8, M4_YMbus_8, M4_UM4_4_Gbus_8); and2 M4_UM4_4_GP_CalGP9(M4_Not_XMbus_9, M4_YMbus_9, M4_UM4_4_Gbus_9); and2 M4_UM4_4_GP_CalGP10(M4_Not_XMbus_10, M4_YMbus_10, M4_UM4_4_Gbus_10); and2 M4_UM4_4_GP_CalGP11(M4_Not_XMbus_11, M4_YMbus_11, M4_UM4_4_Gbus_11); inv M4_UM4_4_GP_CalGP12_Xo0(M4_Not_XMbus_0, M4_UM4_4_GP_CalGP12_NotA); inv M4_UM4_4_GP_CalGP12_Xo1(Ybus_0, M4_UM4_4_GP_CalGP12_NotB); nand2 M4_UM4_4_GP_CalGP12_Xo2(M4_UM4_4_GP_CalGP12_NotA, Ybus_0, M4_UM4_4_GP_CalGP12_line2); nand2 M4_UM4_4_GP_CalGP12_Xo3(M4_UM4_4_GP_CalGP12_NotB, M4_Not_XMbus_0, M4_UM4_4_GP_CalGP12_line3); nand2 M4_UM4_4_GP_CalGP12_Xo4(M4_UM4_4_GP_CalGP12_line2, M4_UM4_4_GP_CalGP12_line3, M4_UM4_4_Pbus_0); inv M4_UM4_4_GP_CalGP13_Xo0(M4_Not_XMbus_1, M4_UM4_4_GP_CalGP13_NotA); inv M4_UM4_4_GP_CalGP13_Xo1(Ybus_1, M4_UM4_4_GP_CalGP13_NotB); nand2 M4_UM4_4_GP_CalGP13_Xo2(M4_UM4_4_GP_CalGP13_NotA, Ybus_1, M4_UM4_4_GP_CalGP13_line2); nand2 M4_UM4_4_GP_CalGP13_Xo3(M4_UM4_4_GP_CalGP13_NotB, M4_Not_XMbus_1, M4_UM4_4_GP_CalGP13_line3); nand2 M4_UM4_4_GP_CalGP13_Xo4(M4_UM4_4_GP_CalGP13_line2, M4_UM4_4_GP_CalGP13_line3, M4_UM4_4_Pbus_1); inv M4_UM4_4_GP_CalGP14_Xo0(M4_Not_XMbus_2, M4_UM4_4_GP_CalGP14_NotA); inv M4_UM4_4_GP_CalGP14_Xo1(Ybus_2, M4_UM4_4_GP_CalGP14_NotB); nand2 M4_UM4_4_GP_CalGP14_Xo2(M4_UM4_4_GP_CalGP14_NotA, Ybus_2, M4_UM4_4_GP_CalGP14_line2); nand2 M4_UM4_4_GP_CalGP14_Xo3(M4_UM4_4_GP_CalGP14_NotB, M4_Not_XMbus_2, M4_UM4_4_GP_CalGP14_line3); nand2 M4_UM4_4_GP_CalGP14_Xo4(M4_UM4_4_GP_CalGP14_line2, M4_UM4_4_GP_CalGP14_line3, M4_UM4_4_Pbus_2); inv M4_UM4_4_GP_CalGP15_Xo0(M4_Not_XMbus_3, M4_UM4_4_GP_CalGP15_NotA); inv M4_UM4_4_GP_CalGP15_Xo1(Ybus_3, M4_UM4_4_GP_CalGP15_NotB); nand2 M4_UM4_4_GP_CalGP15_Xo2(M4_UM4_4_GP_CalGP15_NotA, Ybus_3, M4_UM4_4_GP_CalGP15_line2); nand2 M4_UM4_4_GP_CalGP15_Xo3(M4_UM4_4_GP_CalGP15_NotB, M4_Not_XMbus_3, M4_UM4_4_GP_CalGP15_line3); nand2 M4_UM4_4_GP_CalGP15_Xo4(M4_UM4_4_GP_CalGP15_line2, M4_UM4_4_GP_CalGP15_line3, M4_UM4_4_Pbus_3); inv M4_UM4_4_GP_CalGP16_Xo0(M4_Not_XMbus_4, M4_UM4_4_GP_CalGP16_NotA); inv M4_UM4_4_GP_CalGP16_Xo1(M4_YMbus_4, M4_UM4_4_GP_CalGP16_NotB); nand2 M4_UM4_4_GP_CalGP16_Xo2(M4_UM4_4_GP_CalGP16_NotA, M4_YMbus_4, M4_UM4_4_GP_CalGP16_line2); nand2 M4_UM4_4_GP_CalGP16_Xo3(M4_UM4_4_GP_CalGP16_NotB, M4_Not_XMbus_4, M4_UM4_4_GP_CalGP16_line3); nand2 M4_UM4_4_GP_CalGP16_Xo4(M4_UM4_4_GP_CalGP16_line2, M4_UM4_4_GP_CalGP16_line3, M4_UM4_4_Pbus_4); inv M4_UM4_4_GP_CalGP17_Xo0(M4_Not_XMbus_5, M4_UM4_4_GP_CalGP17_NotA); inv M4_UM4_4_GP_CalGP17_Xo1(M4_YMbus_5, M4_UM4_4_GP_CalGP17_NotB); nand2 M4_UM4_4_GP_CalGP17_Xo2(M4_UM4_4_GP_CalGP17_NotA, M4_YMbus_5, M4_UM4_4_GP_CalGP17_line2); nand2 M4_UM4_4_GP_CalGP17_Xo3(M4_UM4_4_GP_CalGP17_NotB, M4_Not_XMbus_5, M4_UM4_4_GP_CalGP17_line3); nand2 M4_UM4_4_GP_CalGP17_Xo4(M4_UM4_4_GP_CalGP17_line2, M4_UM4_4_GP_CalGP17_line3, M4_UM4_4_Pbus_5); inv M4_UM4_4_GP_CalGP18_Xo0(M4_Not_XMbus_6, M4_UM4_4_GP_CalGP18_NotA); inv M4_UM4_4_GP_CalGP18_Xo1(M4_YMbus_6, M4_UM4_4_GP_CalGP18_NotB); nand2 M4_UM4_4_GP_CalGP18_Xo2(M4_UM4_4_GP_CalGP18_NotA, M4_YMbus_6, M4_UM4_4_GP_CalGP18_line2); nand2 M4_UM4_4_GP_CalGP18_Xo3(M4_UM4_4_GP_CalGP18_NotB, M4_Not_XMbus_6, M4_UM4_4_GP_CalGP18_line3); nand2 M4_UM4_4_GP_CalGP18_Xo4(M4_UM4_4_GP_CalGP18_line2, M4_UM4_4_GP_CalGP18_line3, M4_UM4_4_Pbus_6); inv M4_UM4_4_GP_CalGP19_Xo0(M4_Not_XMbus_7, M4_UM4_4_GP_CalGP19_NotA); inv M4_UM4_4_GP_CalGP19_Xo1(M4_YMbus_7, M4_UM4_4_GP_CalGP19_NotB); nand2 M4_UM4_4_GP_CalGP19_Xo2(M4_UM4_4_GP_CalGP19_NotA, M4_YMbus_7, M4_UM4_4_GP_CalGP19_line2); nand2 M4_UM4_4_GP_CalGP19_Xo3(M4_UM4_4_GP_CalGP19_NotB, M4_Not_XMbus_7, M4_UM4_4_GP_CalGP19_line3); nand2 M4_UM4_4_GP_CalGP19_Xo4(M4_UM4_4_GP_CalGP19_line2, M4_UM4_4_GP_CalGP19_line3, M4_UM4_4_Pbus_7); inv M4_UM4_4_GP_CalGP20_Xo0(M4_Not_XMbus_8, M4_UM4_4_GP_CalGP20_NotA); inv M4_UM4_4_GP_CalGP20_Xo1(M4_YMbus_8, M4_UM4_4_GP_CalGP20_NotB); nand2 M4_UM4_4_GP_CalGP20_Xo2(M4_UM4_4_GP_CalGP20_NotA, M4_YMbus_8, M4_UM4_4_GP_CalGP20_line2); nand2 M4_UM4_4_GP_CalGP20_Xo3(M4_UM4_4_GP_CalGP20_NotB, M4_Not_XMbus_8, M4_UM4_4_GP_CalGP20_line3); nand2 M4_UM4_4_GP_CalGP20_Xo4(M4_UM4_4_GP_CalGP20_line2, M4_UM4_4_GP_CalGP20_line3, M4_UM4_4_Pbus_8); inv M4_UM4_4_GP_CalGP21_Xo0(M4_Not_XMbus_9, M4_UM4_4_GP_CalGP21_NotA); inv M4_UM4_4_GP_CalGP21_Xo1(M4_YMbus_9, M4_UM4_4_GP_CalGP21_NotB); nand2 M4_UM4_4_GP_CalGP21_Xo2(M4_UM4_4_GP_CalGP21_NotA, M4_YMbus_9, M4_UM4_4_GP_CalGP21_line2); nand2 M4_UM4_4_GP_CalGP21_Xo3(M4_UM4_4_GP_CalGP21_NotB, M4_Not_XMbus_9, M4_UM4_4_GP_CalGP21_line3); nand2 M4_UM4_4_GP_CalGP21_Xo4(M4_UM4_4_GP_CalGP21_line2, M4_UM4_4_GP_CalGP21_line3, M4_UM4_4_Pbus_9); inv M4_UM4_4_GP_CalGP22_Xo0(M4_Not_XMbus_10, M4_UM4_4_GP_CalGP22_NotA); inv M4_UM4_4_GP_CalGP22_Xo1(M4_YMbus_10, M4_UM4_4_GP_CalGP22_NotB); nand2 M4_UM4_4_GP_CalGP22_Xo2(M4_UM4_4_GP_CalGP22_NotA, M4_YMbus_10, M4_UM4_4_GP_CalGP22_line2); nand2 M4_UM4_4_GP_CalGP22_Xo3(M4_UM4_4_GP_CalGP22_NotB, M4_Not_XMbus_10, M4_UM4_4_GP_CalGP22_line3); nand2 M4_UM4_4_GP_CalGP22_Xo4(M4_UM4_4_GP_CalGP22_line2, M4_UM4_4_GP_CalGP22_line3, M4_UM4_4_Pbus_10); inv M4_UM4_4_GP_CalGP23_Xo0(M4_Not_XMbus_11, M4_UM4_4_GP_CalGP23_NotA); inv M4_UM4_4_GP_CalGP23_Xo1(M4_YMbus_11, M4_UM4_4_GP_CalGP23_NotB); nand2 M4_UM4_4_GP_CalGP23_Xo2(M4_UM4_4_GP_CalGP23_NotA, M4_YMbus_11, M4_UM4_4_GP_CalGP23_line2); nand2 M4_UM4_4_GP_CalGP23_Xo3(M4_UM4_4_GP_CalGP23_NotB, M4_Not_XMbus_11, M4_UM4_4_GP_CalGP23_line3); nand2 M4_UM4_4_GP_CalGP23_Xo4(M4_UM4_4_GP_CalGP23_line2, M4_UM4_4_GP_CalGP23_line3, M4_UM4_4_Pbus_11); and2 M4_UM4_4_CalcCy_Cla12_0_Cla3_0(M4_UM4_4_Pbus_2, M4_UM4_4_Gbus_1, M4_UM4_4_CalcCy_Cla12_0_line0); and3 M4_UM4_4_CalcCy_Cla12_0_Cla3_1(M4_UM4_4_Pbus_2, M4_UM4_4_Pbus_1, M4_UM4_4_Gbus_0, M4_UM4_4_CalcCy_Cla12_0_line1); or3 M4_UM4_4_CalcCy_Cla12_0_Cla3_2(M4_UM4_4_Gbus_2, M4_UM4_4_CalcCy_Cla12_0_line0, M4_UM4_4_CalcCy_Cla12_0_line1, M4_UM4_4_CalcCy_OutCarry2_0); and2 M4_UM4_4_CalcCy_Cla12_1_Cla5_0(M4_UM4_4_Pbus_7, M4_UM4_4_Gbus_6, M4_UM4_4_CalcCy_Cla12_1_line0); and3 M4_UM4_4_CalcCy_Cla12_1_Cla5_1(M4_UM4_4_Pbus_7, M4_UM4_4_Pbus_6, M4_UM4_4_Gbus_5, M4_UM4_4_CalcCy_Cla12_1_line1); and4 M4_UM4_4_CalcCy_Cla12_1_Cla5_2(M4_UM4_4_Pbus_7, M4_UM4_4_Pbus_6, M4_UM4_4_Pbus_5, M4_UM4_4_Gbus_4, M4_UM4_4_CalcCy_Cla12_1_line2); and5 M4_UM4_4_CalcCy_Cla12_1_Cla5_3(M4_UM4_4_Pbus_7, M4_UM4_4_Pbus_6, M4_UM4_4_Pbus_5, M4_UM4_4_Pbus_4, M4_UM4_4_Gbus_3, M4_UM4_4_CalcCy_Cla12_1_line3); or5 M4_UM4_4_CalcCy_Cla12_1_Cla5_4(M4_UM4_4_Gbus_7, M4_UM4_4_CalcCy_Cla12_1_line0, M4_UM4_4_CalcCy_Cla12_1_line1, M4_UM4_4_CalcCy_Cla12_1_line2, M4_UM4_4_CalcCy_Cla12_1_line3, M4_UM4_4_CalcCy_OutCarry7_3); and2 M4_UM4_4_CalcCy_Cla12_2_Cla4_0(M4_UM4_4_Pbus_11, M4_UM4_4_Gbus_10, M4_UM4_4_CalcCy_Cla12_2_line0); and3 M4_UM4_4_CalcCy_Cla12_2_Cla4_1(M4_UM4_4_Pbus_11, M4_UM4_4_Pbus_10, M4_UM4_4_Gbus_9, M4_UM4_4_CalcCy_Cla12_2_line1); and4 M4_UM4_4_CalcCy_Cla12_2_Cla4_2(M4_UM4_4_Pbus_11, M4_UM4_4_Pbus_10, M4_UM4_4_Pbus_9, M4_UM4_4_Gbus_8, M4_UM4_4_CalcCy_Cla12_2_line2); or4 M4_UM4_4_CalcCy_Cla12_2_Cla4_3(M4_UM4_4_Gbus_11, M4_UM4_4_CalcCy_Cla12_2_line0, M4_UM4_4_CalcCy_Cla12_2_line1, M4_UM4_4_CalcCy_Cla12_2_line2, M4_UM4_4_CalcCy_OutCarry11_8); and5 M4_UM4_4_CalcCy_Cla12_3(M4_UM4_4_Pbus_3, M4_UM4_4_Pbus_4, M4_UM4_4_Pbus_5, M4_UM4_4_Pbus_6, M4_UM4_4_Pbus_7, M4_UM4_4_CalcCy_Prop7_3); and4 M4_UM4_4_CalcCy_Cla12_4(M4_UM4_4_Pbus_8, M4_UM4_4_Pbus_9, M4_UM4_4_Pbus_10, M4_UM4_4_Pbus_11, M4_UM4_4_CalcCy_Prop11_8); and2 M4_UM4_4_CalcCy_Cla12_5(M4_UM4_4_CalcCy_Prop7_3, M4_UM4_4_CalcCy_OutCarry2_0, M4_UM4_4_CalcCy_line5); or2 M4_UM4_4_CalcCy_Cla12_6(M4_UM4_4_CalcCy_OutCarry7_3, M4_UM4_4_CalcCy_line5, M4_UM4_4_CalcCy_OutCarry7_0); inv M4_UM4_4_CalcCy_Cla12_7(M4_UM4_4_CalcCy_OutCarry7_0, M4_UM4_4_CalcCy_NotOutCarry7_0); or2 M4_UM4_4_CalcCy_Cla12_8(M4_UM4_4_CalcCy_OutCarry11_8, M4_UM4_4_CalcCy_Prop11_8, M4_UM4_4_CalcCy_line8); and2 M4_UM4_4_CalcCy_Cla12_9(M4_UM4_4_CalcCy_NotOutCarry7_0, M4_UM4_4_CalcCy_OutCarry11_8, M4_UM4_4_CalcCy_line9); and2 M4_UM4_4_CalcCy_Cla12_10(M4_UM4_4_CalcCy_line8, M4_UM4_4_CalcCy_OutCarry7_0, M4_UM4_4_CalcCy_line10); or2 M4_UM4_4_CalcCy_Cla12_11(M4_UM4_4_CalcCy_line9, M4_UM4_4_CalcCy_line10, M4_YgX2); nand2 M4_UM4_5_Xo1_0(out329, M4_YgX2, M4_UM4_5_NotAB); and2 M4_UM4_5_Xo1_1(out329, M4_UM4_5_NotAB, M4_UM4_5_line1); and2 M4_UM4_5_Xo1_2(M4_UM4_5_NotAB, M4_YgX2, M4_UM4_5_line2); or2 M4_UM4_5_Xo1_3(M4_UM4_5_line1, M4_UM4_5_line2, M4_Not_CompCLAs); inv M4_UM4_6_RIV0(M4_Not_CompCLAs, M4_UM4_6_NotA); and2 M4_UM4_6_RIV1(M4_Not_CompCLAs, M4_UM4_6_NotA, M4_UM4_6_line1); or2 M4_UM4_6_RIV2(M4_UM4_6_line1, M4_UM4_6_NotA, CompCLAs); inv M4_UM4_7(CompCLAs, out231); inv M5_UM5_0_Inv6_0(in1341, M5_Not_Y1bus_0); inv M5_UM5_0_Inv6_1(in1348, M5_Not_Y1bus_1); inv M5_UM5_0_Inv6_2(in1956, M5_Not_Y1bus_2); inv M5_UM5_0_Inv6_3(in1961, M5_Not_Y1bus_3); inv M5_UM5_0_Inv6_4(in1966, M5_Not_Y1bus_4); inv M5_UM5_0_Inv6_5(in1971, M5_Not_Y1bus_5); inv M5_UM5_1_Inv6_0(in1996, Ybus_10); inv M5_UM5_1_Inv6_1(in2067, Ybus_11); inv M5_UM5_1_Inv6_2(in2072, M5_Not_Y2bus_2); inv M5_UM5_1_Inv6_3(in2078, M5_Not_Y2bus_3); inv M5_UM5_1_Inv6_4(in2084, M5_Not_Y2bus_4); inv M5_UM5_1_Inv6_5(in2090, M5_Not_Y2bus_5); inv M5_UM5_2_Mux6_0_Mux0(ContAlpha, M5_UM5_2_Mux6_0_Not_ContIn); and2 M5_UM5_2_Mux6_0_Mux1(M5_Not_Y1bus_0, M5_UM5_2_Mux6_0_Not_ContIn, M5_UM5_2_Mux6_0_line1); and2 M5_UM5_2_Mux6_0_Mux2(Ybus_10, ContAlpha, M5_UM5_2_Mux6_0_line2); or2 M5_UM5_2_Mux6_0_Mux3(M5_UM5_2_Mux6_0_line1, M5_UM5_2_Mux6_0_line2, Ybus_0); inv M5_UM5_2_Mux6_1_Mux0(ContAlpha, M5_UM5_2_Mux6_1_Not_ContIn); and2 M5_UM5_2_Mux6_1_Mux1(M5_Not_Y1bus_1, M5_UM5_2_Mux6_1_Not_ContIn, M5_UM5_2_Mux6_1_line1); and2 M5_UM5_2_Mux6_1_Mux2(Ybus_11, ContAlpha, M5_UM5_2_Mux6_1_line2); or2 M5_UM5_2_Mux6_1_Mux3(M5_UM5_2_Mux6_1_line1, M5_UM5_2_Mux6_1_line2, Ybus_1); inv M5_UM5_2_Mux6_2_Mux0(ContAlpha, M5_UM5_2_Mux6_2_Not_ContIn); and2 M5_UM5_2_Mux6_2_Mux1(M5_Not_Y1bus_2, M5_UM5_2_Mux6_2_Not_ContIn, M5_UM5_2_Mux6_2_line1); and2 M5_UM5_2_Mux6_2_Mux2(M5_Not_Y2bus_2, ContAlpha, M5_UM5_2_Mux6_2_line2); or2 M5_UM5_2_Mux6_2_Mux3(M5_UM5_2_Mux6_2_line1, M5_UM5_2_Mux6_2_line2, Ybus_2); inv M5_UM5_2_Mux6_3_Mux0(ContAlpha, M5_UM5_2_Mux6_3_Not_ContIn); and2 M5_UM5_2_Mux6_3_Mux1(M5_Not_Y1bus_3, M5_UM5_2_Mux6_3_Not_ContIn, M5_UM5_2_Mux6_3_line1); and2 M5_UM5_2_Mux6_3_Mux2(M5_Not_Y2bus_3, ContAlpha, M5_UM5_2_Mux6_3_line2); or2 M5_UM5_2_Mux6_3_Mux3(M5_UM5_2_Mux6_3_line1, M5_UM5_2_Mux6_3_line2, Ybus_3); inv M5_UM5_2_Mux6_4_Mux0(ContAlpha, M5_UM5_2_Mux6_4_Not_ContIn); and2 M5_UM5_2_Mux6_4_Mux1(M5_Not_Y1bus_4, M5_UM5_2_Mux6_4_Not_ContIn, M5_UM5_2_Mux6_4_line1); and2 M5_UM5_2_Mux6_4_Mux2(M5_Not_Y2bus_4, ContAlpha, M5_UM5_2_Mux6_4_line2); or2 M5_UM5_2_Mux6_4_Mux3(M5_UM5_2_Mux6_4_line1, M5_UM5_2_Mux6_4_line2, Ybus_4); inv M5_UM5_2_Mux6_5_Mux0(ContAlpha, M5_UM5_2_Mux6_5_Not_ContIn); and2 M5_UM5_2_Mux6_5_Mux1(M5_Not_Y1bus_5, M5_UM5_2_Mux6_5_Not_ContIn, M5_UM5_2_Mux6_5_line1); and2 M5_UM5_2_Mux6_5_Mux2(M5_Not_Y2bus_5, ContAlpha, M5_UM5_2_Mux6_5_line2); or2 M5_UM5_2_Mux6_5_Mux3(M5_UM5_2_Mux6_5_line1, M5_UM5_2_Mux6_5_line2, Ybus_5); inv M5_UM5_3_Inv4_0(in1976, Ybus_6); inv M5_UM5_3_Inv4_1(in1981, Ybus_7); inv M5_UM5_3_Inv4_2(in1986, Ybus_8); inv M5_UM5_3_Inv4_3(in1991, Ybus_9); inv M6_UM6_0_Mux9_0_Mux0(in16, M6_UM6_0_Mux9_0_Not_ContIn); and2 M6_UM6_0_Mux9_0_Mux1(in19, M6_UM6_0_Mux9_0_Not_ContIn, M6_UM6_0_Mux9_0_line1); and2 M6_UM6_0_Mux9_0_Mux2(Abus_0, in16, M6_UM6_0_Mux9_0_line2); or2 M6_UM6_0_Mux9_0_Mux3(M6_UM6_0_Mux9_0_line1, M6_UM6_0_Mux9_0_line2, Zbus_0); inv M6_UM6_0_Mux9_1_Mux0(in16, M6_UM6_0_Mux9_1_Not_ContIn); and2 M6_UM6_0_Mux9_1_Mux1(in4, M6_UM6_0_Mux9_1_Not_ContIn, M6_UM6_0_Mux9_1_line1); and2 M6_UM6_0_Mux9_1_Mux2(Abus_1, in16, M6_UM6_0_Mux9_1_line2); or2 M6_UM6_0_Mux9_1_Mux3(M6_UM6_0_Mux9_1_line1, M6_UM6_0_Mux9_1_line2, Zbus_1); inv M6_UM6_0_Mux9_2_Mux0(in16, M6_UM6_0_Mux9_2_Not_ContIn); and2 M6_UM6_0_Mux9_2_Mux1(in20, M6_UM6_0_Mux9_2_Not_ContIn, M6_UM6_0_Mux9_2_line1); and2 M6_UM6_0_Mux9_2_Mux2(Abus_2, in16, M6_UM6_0_Mux9_2_line2); or2 M6_UM6_0_Mux9_2_Mux3(M6_UM6_0_Mux9_2_line1, M6_UM6_0_Mux9_2_line2, Zbus_2); inv M6_UM6_0_Mux9_3_Mux0(in16, M6_UM6_0_Mux9_3_Not_ContIn); and2 M6_UM6_0_Mux9_3_Mux1(in5, M6_UM6_0_Mux9_3_Not_ContIn, M6_UM6_0_Mux9_3_line1); and2 M6_UM6_0_Mux9_3_Mux2(Abus_3, in16, M6_UM6_0_Mux9_3_line2); or2 M6_UM6_0_Mux9_3_Mux3(M6_UM6_0_Mux9_3_line1, M6_UM6_0_Mux9_3_line2, Zbus_3); inv M6_UM6_0_Mux9_4_Mux0(in16, M6_UM6_0_Mux9_4_Not_ContIn); and2 M6_UM6_0_Mux9_4_Mux1(in21, M6_UM6_0_Mux9_4_Not_ContIn, M6_UM6_0_Mux9_4_line1); and2 M6_UM6_0_Mux9_4_Mux2(Abus_4, in16, M6_UM6_0_Mux9_4_line2); or2 M6_UM6_0_Mux9_4_Mux3(M6_UM6_0_Mux9_4_line1, M6_UM6_0_Mux9_4_line2, Zbus_4); inv M6_UM6_0_Mux9_5_Mux0(in16, M6_UM6_0_Mux9_5_Not_ContIn); and2 M6_UM6_0_Mux9_5_Mux1(in22, M6_UM6_0_Mux9_5_Not_ContIn, M6_UM6_0_Mux9_5_line1); and2 M6_UM6_0_Mux9_5_Mux2(Abus_5, in16, M6_UM6_0_Mux9_5_line2); or2 M6_UM6_0_Mux9_5_Mux3(M6_UM6_0_Mux9_5_line1, M6_UM6_0_Mux9_5_line2, Zbus_5); inv M6_UM6_0_Mux9_6_Mux0(in16, M6_UM6_0_Mux9_6_Not_ContIn); and2 M6_UM6_0_Mux9_6_Mux1(in23, M6_UM6_0_Mux9_6_Not_ContIn, M6_UM6_0_Mux9_6_line1); and2 M6_UM6_0_Mux9_6_Mux2(Abus_6, in16, M6_UM6_0_Mux9_6_line2); or2 M6_UM6_0_Mux9_6_Mux3(M6_UM6_0_Mux9_6_line1, M6_UM6_0_Mux9_6_line2, Zbus_6); inv M6_UM6_0_Mux9_7_Mux0(in16, M6_UM6_0_Mux9_7_Not_ContIn); and2 M6_UM6_0_Mux9_7_Mux1(in6, M6_UM6_0_Mux9_7_Not_ContIn, M6_UM6_0_Mux9_7_line1); and2 M6_UM6_0_Mux9_7_Mux2(Abus_7, in16, M6_UM6_0_Mux9_7_line2); or2 M6_UM6_0_Mux9_7_Mux3(M6_UM6_0_Mux9_7_line1, M6_UM6_0_Mux9_7_line2, Zbus_7); inv M6_UM6_0_Mux9_8_Mux0(in16, M6_UM6_0_Mux9_8_Not_ContIn); and2 M6_UM6_0_Mux9_8_Mux1(in24, M6_UM6_0_Mux9_8_Not_ContIn, M6_UM6_0_Mux9_8_line1); and2 M6_UM6_0_Mux9_8_Mux2(Abus_8, in16, M6_UM6_0_Mux9_8_line2); or2 M6_UM6_0_Mux9_8_Mux3(M6_UM6_0_Mux9_8_line1, M6_UM6_0_Mux9_8_line2, Zbus_8); inv M6_UM6_1_Mux8_0_Mux0(in29, M6_UM6_1_Mux8_0_Not_ContIn); and2 M6_UM6_1_Mux8_0_Mux1(in25, M6_UM6_1_Mux8_0_Not_ContIn, M6_UM6_1_Mux8_0_line1); and2 M6_UM6_1_Mux8_0_Mux2(Bbus_0, in29, M6_UM6_1_Mux8_0_line2); or2 M6_UM6_1_Mux8_0_Mux3(M6_UM6_1_Mux8_0_line1, M6_UM6_1_Mux8_0_line2, Zbus_9); inv M6_UM6_1_Mux8_1_Mux0(in29, M6_UM6_1_Mux8_1_Not_ContIn); and2 M6_UM6_1_Mux8_1_Mux1(in32, M6_UM6_1_Mux8_1_Not_ContIn, M6_UM6_1_Mux8_1_line1); and2 M6_UM6_1_Mux8_1_Mux2(Bbus_1, in29, M6_UM6_1_Mux8_1_line2); or2 M6_UM6_1_Mux8_1_Mux3(M6_UM6_1_Mux8_1_line1, M6_UM6_1_Mux8_1_line2, Zbus_10); inv M6_UM6_1_Mux8_2_Mux0(in29, M6_UM6_1_Mux8_2_Not_ContIn); and2 M6_UM6_1_Mux8_2_Mux1(in26, M6_UM6_1_Mux8_2_Not_ContIn, M6_UM6_1_Mux8_2_line1); and2 M6_UM6_1_Mux8_2_Mux2(Bbus_2, in29, M6_UM6_1_Mux8_2_line2); or2 M6_UM6_1_Mux8_2_Mux3(M6_UM6_1_Mux8_2_line1, M6_UM6_1_Mux8_2_line2, Zbus_11); inv M6_UM6_1_Mux8_3_Mux0(in29, M6_UM6_1_Mux8_3_Not_ContIn); and2 M6_UM6_1_Mux8_3_Mux1(in33, M6_UM6_1_Mux8_3_Not_ContIn, M6_UM6_1_Mux8_3_line1); and2 M6_UM6_1_Mux8_3_Mux2(Bbus_3, in29, M6_UM6_1_Mux8_3_line2); or2 M6_UM6_1_Mux8_3_Mux3(M6_UM6_1_Mux8_3_line1, M6_UM6_1_Mux8_3_line2, Zbus_12); inv M6_UM6_1_Mux8_4_Mux0(in29, M6_UM6_1_Mux8_4_Not_ContIn); and2 M6_UM6_1_Mux8_4_Mux1(in27, M6_UM6_1_Mux8_4_Not_ContIn, M6_UM6_1_Mux8_4_line1); and2 M6_UM6_1_Mux8_4_Mux2(Bbus_4, in29, M6_UM6_1_Mux8_4_line2); or2 M6_UM6_1_Mux8_4_Mux3(M6_UM6_1_Mux8_4_line1, M6_UM6_1_Mux8_4_line2, Zbus_13); inv M6_UM6_1_Mux8_5_Mux0(in29, M6_UM6_1_Mux8_5_Not_ContIn); and2 M6_UM6_1_Mux8_5_Mux1(in34, M6_UM6_1_Mux8_5_Not_ContIn, M6_UM6_1_Mux8_5_line1); and2 M6_UM6_1_Mux8_5_Mux2(Bbus_5, in29, M6_UM6_1_Mux8_5_line2); or2 M6_UM6_1_Mux8_5_Mux3(M6_UM6_1_Mux8_5_line1, M6_UM6_1_Mux8_5_line2, Zbus_14); inv M6_UM6_1_Mux8_6_Mux0(in29, M6_UM6_1_Mux8_6_Not_ContIn); and2 M6_UM6_1_Mux8_6_Mux1(in35, M6_UM6_1_Mux8_6_Not_ContIn, M6_UM6_1_Mux8_6_line1); and2 M6_UM6_1_Mux8_6_Mux2(Bbus_6, in29, M6_UM6_1_Mux8_6_line2); or2 M6_UM6_1_Mux8_6_Mux3(M6_UM6_1_Mux8_6_line1, M6_UM6_1_Mux8_6_line2, Zbus_15); inv M6_UM6_1_Mux8_7_Mux0(in29, M6_UM6_1_Mux8_7_Not_ContIn); and2 M6_UM6_1_Mux8_7_Mux1(in28, M6_UM6_1_Mux8_7_Not_ContIn, M6_UM6_1_Mux8_7_line1); and2 M6_UM6_1_Mux8_7_Mux2(Bbus_7, in29, M6_UM6_1_Mux8_7_line2); or2 M6_UM6_1_Mux8_7_Mux3(M6_UM6_1_Mux8_7_line1, M6_UM6_1_Mux8_7_line2, Zbus_16); inv M7_UM7_0_Xr0_Xo0(Zbus_0, M7_UM7_0_Xr0_NotA); inv M7_UM7_0_Xr0_Xo1(in1341, M7_UM7_0_Xr0_NotB); nand2 M7_UM7_0_Xr0_Xo2(M7_UM7_0_Xr0_NotA, in1341, M7_UM7_0_Xr0_line2); nand2 M7_UM7_0_Xr0_Xo3(M7_UM7_0_Xr0_NotB, Zbus_0, M7_UM7_0_Xr0_line3); nand2 M7_UM7_0_Xr0_Xo4(M7_UM7_0_Xr0_line2, M7_UM7_0_Xr0_line3, M7_XorZW_0); inv M7_UM7_0_Xr1_Xo0(Zbus_1, M7_UM7_0_Xr1_NotA); inv M7_UM7_0_Xr1_Xo1(in1348, M7_UM7_0_Xr1_NotB); nand2 M7_UM7_0_Xr1_Xo2(M7_UM7_0_Xr1_NotA, in1348, M7_UM7_0_Xr1_line2); nand2 M7_UM7_0_Xr1_Xo3(M7_UM7_0_Xr1_NotB, Zbus_1, M7_UM7_0_Xr1_line3); nand2 M7_UM7_0_Xr1_Xo4(M7_UM7_0_Xr1_line2, M7_UM7_0_Xr1_line3, M7_XorZW_1); inv M7_UM7_0_Xr2_Xo0(Zbus_2, M7_UM7_0_Xr2_NotA); inv M7_UM7_0_Xr2_Xo1(in1956, M7_UM7_0_Xr2_NotB); nand2 M7_UM7_0_Xr2_Xo2(M7_UM7_0_Xr2_NotA, in1956, M7_UM7_0_Xr2_line2); nand2 M7_UM7_0_Xr2_Xo3(M7_UM7_0_Xr2_NotB, Zbus_2, M7_UM7_0_Xr2_line3); nand2 M7_UM7_0_Xr2_Xo4(M7_UM7_0_Xr2_line2, M7_UM7_0_Xr2_line3, M7_XorZW_2); inv M7_UM7_0_Xr3_Xo0(Zbus_3, M7_UM7_0_Xr3_NotA); inv M7_UM7_0_Xr3_Xo1(in1961, M7_UM7_0_Xr3_NotB); nand2 M7_UM7_0_Xr3_Xo2(M7_UM7_0_Xr3_NotA, in1961, M7_UM7_0_Xr3_line2); nand2 M7_UM7_0_Xr3_Xo3(M7_UM7_0_Xr3_NotB, Zbus_3, M7_UM7_0_Xr3_line3); nand2 M7_UM7_0_Xr3_Xo4(M7_UM7_0_Xr3_line2, M7_UM7_0_Xr3_line3, M7_XorZW_3); inv M7_UM7_0_Xr4_Xo0(Zbus_4, M7_UM7_0_Xr4_NotA); inv M7_UM7_0_Xr4_Xo1(in1966, M7_UM7_0_Xr4_NotB); nand2 M7_UM7_0_Xr4_Xo2(M7_UM7_0_Xr4_NotA, in1966, M7_UM7_0_Xr4_line2); nand2 M7_UM7_0_Xr4_Xo3(M7_UM7_0_Xr4_NotB, Zbus_4, M7_UM7_0_Xr4_line3); nand2 M7_UM7_0_Xr4_Xo4(M7_UM7_0_Xr4_line2, M7_UM7_0_Xr4_line3, M7_XorZW_4); inv M7_UM7_0_Xr5_Xo0(Zbus_5, M7_UM7_0_Xr5_NotA); inv M7_UM7_0_Xr5_Xo1(in1971, M7_UM7_0_Xr5_NotB); nand2 M7_UM7_0_Xr5_Xo2(M7_UM7_0_Xr5_NotA, in1971, M7_UM7_0_Xr5_line2); nand2 M7_UM7_0_Xr5_Xo3(M7_UM7_0_Xr5_NotB, Zbus_5, M7_UM7_0_Xr5_line3); nand2 M7_UM7_0_Xr5_Xo4(M7_UM7_0_Xr5_line2, M7_UM7_0_Xr5_line3, M7_XorZW_5); inv M7_UM7_0_Xr6_Xo0(Zbus_6, M7_UM7_0_Xr6_NotA); inv M7_UM7_0_Xr6_Xo1(in1976, M7_UM7_0_Xr6_NotB); nand2 M7_UM7_0_Xr6_Xo2(M7_UM7_0_Xr6_NotA, in1976, M7_UM7_0_Xr6_line2); nand2 M7_UM7_0_Xr6_Xo3(M7_UM7_0_Xr6_NotB, Zbus_6, M7_UM7_0_Xr6_line3); nand2 M7_UM7_0_Xr6_Xo4(M7_UM7_0_Xr6_line2, M7_UM7_0_Xr6_line3, M7_XorZW_6); inv M7_UM7_0_Xr7_Xo0(Zbus_7, M7_UM7_0_Xr7_NotA); inv M7_UM7_0_Xr7_Xo1(in1981, M7_UM7_0_Xr7_NotB); nand2 M7_UM7_0_Xr7_Xo2(M7_UM7_0_Xr7_NotA, in1981, M7_UM7_0_Xr7_line2); nand2 M7_UM7_0_Xr7_Xo3(M7_UM7_0_Xr7_NotB, Zbus_7, M7_UM7_0_Xr7_line3); nand2 M7_UM7_0_Xr7_Xo4(M7_UM7_0_Xr7_line2, M7_UM7_0_Xr7_line3, M7_XorZW_7); inv M7_UM7_0_Xr8_Xo0(Zbus_8, M7_UM7_0_Xr8_NotA); inv M7_UM7_0_Xr8_Xo1(in1986, M7_UM7_0_Xr8_NotB); nand2 M7_UM7_0_Xr8_Xo2(M7_UM7_0_Xr8_NotA, in1986, M7_UM7_0_Xr8_line2); nand2 M7_UM7_0_Xr8_Xo3(M7_UM7_0_Xr8_NotB, Zbus_8, M7_UM7_0_Xr8_line3); nand2 M7_UM7_0_Xr8_Xo4(M7_UM7_0_Xr8_line2, M7_UM7_0_Xr8_line3, M7_XorZW_8); inv M7_UM7_0_Xr9_Xo0(Zbus_9, M7_UM7_0_Xr9_NotA); inv M7_UM7_0_Xr9_Xo1(in1991, M7_UM7_0_Xr9_NotB); nand2 M7_UM7_0_Xr9_Xo2(M7_UM7_0_Xr9_NotA, in1991, M7_UM7_0_Xr9_line2); nand2 M7_UM7_0_Xr9_Xo3(M7_UM7_0_Xr9_NotB, Zbus_9, M7_UM7_0_Xr9_line3); nand2 M7_UM7_0_Xr9_Xo4(M7_UM7_0_Xr9_line2, M7_UM7_0_Xr9_line3, M7_XorZW_9); inv M7_UM7_0_Xr10_Xo0(Zbus_10, M7_UM7_0_Xr10_NotA); inv M7_UM7_0_Xr10_Xo1(in1996, M7_UM7_0_Xr10_NotB); nand2 M7_UM7_0_Xr10_Xo2(M7_UM7_0_Xr10_NotA, in1996, M7_UM7_0_Xr10_line2); nand2 M7_UM7_0_Xr10_Xo3(M7_UM7_0_Xr10_NotB, Zbus_10, M7_UM7_0_Xr10_line3); nand2 M7_UM7_0_Xr10_Xo4(M7_UM7_0_Xr10_line2, M7_UM7_0_Xr10_line3, M7_XorZW_10); inv M7_UM7_0_Xr11_Xo0(Zbus_11, M7_UM7_0_Xr11_NotA); inv M7_UM7_0_Xr11_Xo1(in2067, M7_UM7_0_Xr11_NotB); nand2 M7_UM7_0_Xr11_Xo2(M7_UM7_0_Xr11_NotA, in2067, M7_UM7_0_Xr11_line2); nand2 M7_UM7_0_Xr11_Xo3(M7_UM7_0_Xr11_NotB, Zbus_11, M7_UM7_0_Xr11_line3); nand2 M7_UM7_0_Xr11_Xo4(M7_UM7_0_Xr11_line2, M7_UM7_0_Xr11_line3, M7_XorZW_11); inv M7_UM7_0_Xr12_Xo0(Zbus_12, M7_UM7_0_Xr12_NotA); inv M7_UM7_0_Xr12_Xo1(in2072, M7_UM7_0_Xr12_NotB); nand2 M7_UM7_0_Xr12_Xo2(M7_UM7_0_Xr12_NotA, in2072, M7_UM7_0_Xr12_line2); nand2 M7_UM7_0_Xr12_Xo3(M7_UM7_0_Xr12_NotB, Zbus_12, M7_UM7_0_Xr12_line3); nand2 M7_UM7_0_Xr12_Xo4(M7_UM7_0_Xr12_line2, M7_UM7_0_Xr12_line3, M7_XorZW_12); inv M7_UM7_0_Xr13_Xo0(Zbus_13, M7_UM7_0_Xr13_NotA); inv M7_UM7_0_Xr13_Xo1(in2078, M7_UM7_0_Xr13_NotB); nand2 M7_UM7_0_Xr13_Xo2(M7_UM7_0_Xr13_NotA, in2078, M7_UM7_0_Xr13_line2); nand2 M7_UM7_0_Xr13_Xo3(M7_UM7_0_Xr13_NotB, Zbus_13, M7_UM7_0_Xr13_line3); nand2 M7_UM7_0_Xr13_Xo4(M7_UM7_0_Xr13_line2, M7_UM7_0_Xr13_line3, M7_XorZW_13); inv M7_UM7_0_Xr14_Xo0(Zbus_14, M7_UM7_0_Xr14_NotA); inv M7_UM7_0_Xr14_Xo1(in2084, M7_UM7_0_Xr14_NotB); nand2 M7_UM7_0_Xr14_Xo2(M7_UM7_0_Xr14_NotA, in2084, M7_UM7_0_Xr14_line2); nand2 M7_UM7_0_Xr14_Xo3(M7_UM7_0_Xr14_NotB, Zbus_14, M7_UM7_0_Xr14_line3); nand2 M7_UM7_0_Xr14_Xo4(M7_UM7_0_Xr14_line2, M7_UM7_0_Xr14_line3, M7_XorZW_14); inv M7_UM7_0_Xr15_Xo0(Zbus_15, M7_UM7_0_Xr15_NotA); inv M7_UM7_0_Xr15_Xo1(in2090, M7_UM7_0_Xr15_NotB); nand2 M7_UM7_0_Xr15_Xo2(M7_UM7_0_Xr15_NotA, in2090, M7_UM7_0_Xr15_line2); nand2 M7_UM7_0_Xr15_Xo3(M7_UM7_0_Xr15_NotB, Zbus_15, M7_UM7_0_Xr15_line3); nand2 M7_UM7_0_Xr15_Xo4(M7_UM7_0_Xr15_line2, M7_UM7_0_Xr15_line3, M7_XorZW_15); inv M7_UM7_0_Xr16_Xo0(Zbus_16, M7_UM7_0_Xr16_NotA); inv M7_UM7_0_Xr16_Xo1(gnd, M7_UM7_0_Xr16_NotB); nand2 M7_UM7_0_Xr16_Xo2(M7_UM7_0_Xr16_NotA, gnd, M7_UM7_0_Xr16_line2); nand2 M7_UM7_0_Xr16_Xo3(M7_UM7_0_Xr16_NotB, Zbus_16, M7_UM7_0_Xr16_line3); nand2 M7_UM7_0_Xr16_Xo4(M7_UM7_0_Xr16_line2, M7_UM7_0_Xr16_line3, M7_XorZW_16); and5 M7_UM7_1_A0(M7_XorZW_0, M7_XorZW_1, M7_XorZW_2, M7_XorZW_3, M7_XorZW_4, M7_UM7_1_line0); and5 M7_UM7_1_A1(M7_XorZW_5, M7_XorZW_6, M7_XorZW_7, M7_XorZW_8, M7_XorZW_9, M7_UM7_1_line1); and2 M7_UM7_1_A2(M7_UM7_1_line0, M7_UM7_1_line1, M7_UM7_1_line2); and2 M7_UM7_1_A3(M7_XorZW_10, M7_XorZW_11, M7_UM7_1_line3); and5 M7_UM7_1_A4(M7_XorZW_12, M7_XorZW_13, M7_XorZW_14, M7_XorZW_15, M7_XorZW_16, M7_UM7_1_line4); and2 M7_UM7_1_A5(M7_UM7_1_line3, M7_UM7_1_line4, M7_UM7_1_line5); and3 M7_UM7_1_A6(M7_UM7_1_line2, M7_UM7_1_line5, in11, out311); inv M7_UM7_2(out311, out150); and4 M8_UM8_0_SCL0(in44, in132, in82, in96, M8_UM8_0_line0); and4 M8_UM8_0_SCL1(in69, in120, in57, in108, M8_UM8_0_line1); and2 M8_UM8_0_SCL2(M8_UM8_0_line0, M8_UM8_0_line1, out325); inv M8_UM8_0_SCL3(out325, out261); inv M8_UM8_0_SCL4(in2106, M8_UM8_0_NotPar2); inv M8_UM8_0_SCL5(in567, M8_UM8_0_NotPar3); or2 M8_UM8_0_SCL6(M8_UM8_0_NotPar2, M8_UM8_0_line0, M8_UM8_0_line6); or2 M8_UM8_0_SCL7(M8_UM8_0_NotPar3, M8_UM8_0_line1, M8_UM8_0_line7); and2 M8_UM8_0_SCL8(M8_UM8_0_line6, M8_UM8_0_line7, out319); inv M8_UM8_0_SCL9(in44, out218); inv M8_UM8_0_SCL10(in132, out219); inv M8_UM8_0_SCL11(in82, out220); inv M8_UM8_0_SCL12(in96, out221); inv M8_UM8_0_SCL13(in69, out235); inv M8_UM8_0_SCL14(in120, out236); inv M8_UM8_0_SCL15(in57, out237); inv M8_UM8_0_SCL16(in108, out238); inv M8_UM8_1_PT0_Xo0(Abus_0, M8_UM8_1_PT0_NotA); inv M8_UM8_1_PT0_Xo1(Abus_1, M8_UM8_1_PT0_NotB); nand2 M8_UM8_1_PT0_Xo2(M8_UM8_1_PT0_NotA, Abus_1, M8_UM8_1_PT0_line2); nand2 M8_UM8_1_PT0_Xo3(M8_UM8_1_PT0_NotB, Abus_0, M8_UM8_1_PT0_line3); nand2 M8_UM8_1_PT0_Xo4(M8_UM8_1_PT0_line2, M8_UM8_1_PT0_line3, M8_UM8_1_line0); inv M8_UM8_1_PT1_Xo0(Abus_2, M8_UM8_1_PT1_NotA); inv M8_UM8_1_PT1_Xo1(Abus_3, M8_UM8_1_PT1_NotB); nand2 M8_UM8_1_PT1_Xo2(M8_UM8_1_PT1_NotA, Abus_3, M8_UM8_1_PT1_line2); nand2 M8_UM8_1_PT1_Xo3(M8_UM8_1_PT1_NotB, Abus_2, M8_UM8_1_PT1_line3); nand2 M8_UM8_1_PT1_Xo4(M8_UM8_1_PT1_line2, M8_UM8_1_PT1_line3, M8_UM8_1_line1); inv M8_UM8_1_PT2_Xo0(Abus_4, M8_UM8_1_PT2_NotA); inv M8_UM8_1_PT2_Xo1(Abus_5, M8_UM8_1_PT2_NotB); nand2 M8_UM8_1_PT2_Xo2(M8_UM8_1_PT2_NotA, Abus_5, M8_UM8_1_PT2_line2); nand2 M8_UM8_1_PT2_Xo3(M8_UM8_1_PT2_NotB, Abus_4, M8_UM8_1_PT2_line3); nand2 M8_UM8_1_PT2_Xo4(M8_UM8_1_PT2_line2, M8_UM8_1_PT2_line3, M8_UM8_1_line2); inv M8_UM8_1_PT3_Xo0(Abus_6, M8_UM8_1_PT3_NotA); inv M8_UM8_1_PT3_Xo1(Abus_7, M8_UM8_1_PT3_NotB); nand2 M8_UM8_1_PT3_Xo2(M8_UM8_1_PT3_NotA, Abus_7, M8_UM8_1_PT3_line2); nand2 M8_UM8_1_PT3_Xo3(M8_UM8_1_PT3_NotB, Abus_6, M8_UM8_1_PT3_line3); nand2 M8_UM8_1_PT3_Xo4(M8_UM8_1_PT3_line2, M8_UM8_1_PT3_line3, M8_UM8_1_line3); inv M8_UM8_1_PT4_Xo0(Abus_8, M8_UM8_1_PT4_NotA); inv M8_UM8_1_PT4_Xo1(Abus_9, M8_UM8_1_PT4_NotB); nand2 M8_UM8_1_PT4_Xo2(M8_UM8_1_PT4_NotA, Abus_9, M8_UM8_1_PT4_line2); nand2 M8_UM8_1_PT4_Xo3(M8_UM8_1_PT4_NotB, Abus_8, M8_UM8_1_PT4_line3); nand2 M8_UM8_1_PT4_Xo4(M8_UM8_1_PT4_line2, M8_UM8_1_PT4_line3, M8_UM8_1_line4); inv M8_UM8_1_PT5_Xo3_0(M8_UM8_1_line0, M8_UM8_1_PT5_NotA); inv M8_UM8_1_PT5_Xo3_1(M8_UM8_1_line1, M8_UM8_1_PT5_NotB); inv M8_UM8_1_PT5_Xo3_2(M8_UM8_1_line2, M8_UM8_1_PT5_NotC); and3 M8_UM8_1_PT5_Xo3_3(M8_UM8_1_PT5_NotA, M8_UM8_1_PT5_NotB, M8_UM8_1_line2, M8_UM8_1_PT5_line3); and3 M8_UM8_1_PT5_Xo3_4(M8_UM8_1_PT5_NotA, M8_UM8_1_line1, M8_UM8_1_PT5_NotC, M8_UM8_1_PT5_line4); and3 M8_UM8_1_PT5_Xo3_5(M8_UM8_1_line0, M8_UM8_1_PT5_NotB, M8_UM8_1_PT5_NotC, M8_UM8_1_PT5_line5); and3 M8_UM8_1_PT5_Xo3_6(M8_UM8_1_line0, M8_UM8_1_line1, M8_UM8_1_line2, M8_UM8_1_PT5_line6); nor2 M8_UM8_1_PT5_Xo3_7(M8_UM8_1_PT5_line3, M8_UM8_1_PT5_line4, M8_UM8_1_PT5_line7); nor2 M8_UM8_1_PT5_Xo3_8(M8_UM8_1_PT5_line5, M8_UM8_1_PT5_line6, M8_UM8_1_PT5_line8); nand2 M8_UM8_1_PT5_Xo3_9(M8_UM8_1_PT5_line7, M8_UM8_1_PT5_line8, M8_UM8_1_line5); inv M8_UM8_1_PT6_Xo0(M8_UM8_1_line3, M8_UM8_1_PT6_NotA); inv M8_UM8_1_PT6_Xo1(M8_UM8_1_line4, M8_UM8_1_PT6_NotB); nand2 M8_UM8_1_PT6_Xo2(M8_UM8_1_PT6_NotA, M8_UM8_1_line4, M8_UM8_1_PT6_line2); nand2 M8_UM8_1_PT6_Xo3(M8_UM8_1_PT6_NotB, M8_UM8_1_line3, M8_UM8_1_PT6_line3); nand2 M8_UM8_1_PT6_Xo4(M8_UM8_1_PT6_line2, M8_UM8_1_PT6_line3, M8_UM8_1_line6); inv M8_UM8_1_PT7_Xo0(M8_UM8_1_line5, M8_UM8_1_PT7_NotA); inv M8_UM8_1_PT7_Xo1(M8_UM8_1_line6, M8_UM8_1_PT7_NotB); nand2 M8_UM8_1_PT7_Xo2(M8_UM8_1_PT7_NotA, M8_UM8_1_line6, M8_UM8_1_PT7_line2); nand2 M8_UM8_1_PT7_Xo3(M8_UM8_1_PT7_NotB, M8_UM8_1_line5, M8_UM8_1_PT7_line3); nand2 M8_UM8_1_PT7_Xo4(M8_UM8_1_PT7_line2, M8_UM8_1_PT7_line3, M8_ParA); inv M8_UM8_2_PT0_Xo0(Bbus_0, M8_UM8_2_PT0_NotA); inv M8_UM8_2_PT0_Xo1(Bbus_1, M8_UM8_2_PT0_NotB); nand2 M8_UM8_2_PT0_Xo2(M8_UM8_2_PT0_NotA, Bbus_1, M8_UM8_2_PT0_line2); nand2 M8_UM8_2_PT0_Xo3(M8_UM8_2_PT0_NotB, Bbus_0, M8_UM8_2_PT0_line3); nand2 M8_UM8_2_PT0_Xo4(M8_UM8_2_PT0_line2, M8_UM8_2_PT0_line3, M8_UM8_2_line0); inv M8_UM8_2_PT1_Xo0(Bbus_2, M8_UM8_2_PT1_NotA); inv M8_UM8_2_PT1_Xo1(Bbus_3, M8_UM8_2_PT1_NotB); nand2 M8_UM8_2_PT1_Xo2(M8_UM8_2_PT1_NotA, Bbus_3, M8_UM8_2_PT1_line2); nand2 M8_UM8_2_PT1_Xo3(M8_UM8_2_PT1_NotB, Bbus_2, M8_UM8_2_PT1_line3); nand2 M8_UM8_2_PT1_Xo4(M8_UM8_2_PT1_line2, M8_UM8_2_PT1_line3, M8_UM8_2_line1); inv M8_UM8_2_PT2_Xo0(Bbus_4, M8_UM8_2_PT2_NotA); inv M8_UM8_2_PT2_Xo1(Bbus_5, M8_UM8_2_PT2_NotB); nand2 M8_UM8_2_PT2_Xo2(M8_UM8_2_PT2_NotA, Bbus_5, M8_UM8_2_PT2_line2); nand2 M8_UM8_2_PT2_Xo3(M8_UM8_2_PT2_NotB, Bbus_4, M8_UM8_2_PT2_line3); nand2 M8_UM8_2_PT2_Xo4(M8_UM8_2_PT2_line2, M8_UM8_2_PT2_line3, M8_UM8_2_line2); inv M8_UM8_2_PT3_Xo0(Bbus_6, M8_UM8_2_PT3_NotA); inv M8_UM8_2_PT3_Xo1(Bbus_7, M8_UM8_2_PT3_NotB); nand2 M8_UM8_2_PT3_Xo2(M8_UM8_2_PT3_NotA, Bbus_7, M8_UM8_2_PT3_line2); nand2 M8_UM8_2_PT3_Xo3(M8_UM8_2_PT3_NotB, Bbus_6, M8_UM8_2_PT3_line3); nand2 M8_UM8_2_PT3_Xo4(M8_UM8_2_PT3_line2, M8_UM8_2_PT3_line3, M8_UM8_2_line3); inv M8_UM8_2_PT4_Xo0(Bbus_8, M8_UM8_2_PT4_NotA); inv M8_UM8_2_PT4_Xo1(Bbus_9, M8_UM8_2_PT4_NotB); nand2 M8_UM8_2_PT4_Xo2(M8_UM8_2_PT4_NotA, Bbus_9, M8_UM8_2_PT4_line2); nand2 M8_UM8_2_PT4_Xo3(M8_UM8_2_PT4_NotB, Bbus_8, M8_UM8_2_PT4_line3); nand2 M8_UM8_2_PT4_Xo4(M8_UM8_2_PT4_line2, M8_UM8_2_PT4_line3, M8_UM8_2_line4); inv M8_UM8_2_PT5_Xo3_0(M8_UM8_2_line0, M8_UM8_2_PT5_NotA); inv M8_UM8_2_PT5_Xo3_1(M8_UM8_2_line1, M8_UM8_2_PT5_NotB); inv M8_UM8_2_PT5_Xo3_2(M8_UM8_2_line2, M8_UM8_2_PT5_NotC); and3 M8_UM8_2_PT5_Xo3_3(M8_UM8_2_PT5_NotA, M8_UM8_2_PT5_NotB, M8_UM8_2_line2, M8_UM8_2_PT5_line3); and3 M8_UM8_2_PT5_Xo3_4(M8_UM8_2_PT5_NotA, M8_UM8_2_line1, M8_UM8_2_PT5_NotC, M8_UM8_2_PT5_line4); and3 M8_UM8_2_PT5_Xo3_5(M8_UM8_2_line0, M8_UM8_2_PT5_NotB, M8_UM8_2_PT5_NotC, M8_UM8_2_PT5_line5); and3 M8_UM8_2_PT5_Xo3_6(M8_UM8_2_line0, M8_UM8_2_line1, M8_UM8_2_line2, M8_UM8_2_PT5_line6); nor2 M8_UM8_2_PT5_Xo3_7(M8_UM8_2_PT5_line3, M8_UM8_2_PT5_line4, M8_UM8_2_PT5_line7); nor2 M8_UM8_2_PT5_Xo3_8(M8_UM8_2_PT5_line5, M8_UM8_2_PT5_line6, M8_UM8_2_PT5_line8); nand2 M8_UM8_2_PT5_Xo3_9(M8_UM8_2_PT5_line7, M8_UM8_2_PT5_line8, M8_UM8_2_line5); inv M8_UM8_2_PT6_Xo0(M8_UM8_2_line3, M8_UM8_2_PT6_NotA); inv M8_UM8_2_PT6_Xo1(M8_UM8_2_line4, M8_UM8_2_PT6_NotB); nand2 M8_UM8_2_PT6_Xo2(M8_UM8_2_PT6_NotA, M8_UM8_2_line4, M8_UM8_2_PT6_line2); nand2 M8_UM8_2_PT6_Xo3(M8_UM8_2_PT6_NotB, M8_UM8_2_line3, M8_UM8_2_PT6_line3); nand2 M8_UM8_2_PT6_Xo4(M8_UM8_2_PT6_line2, M8_UM8_2_PT6_line3, M8_UM8_2_line6); inv M8_UM8_2_PT7_Xo0(M8_UM8_2_line5, M8_UM8_2_PT7_NotA); inv M8_UM8_2_PT7_Xo1(M8_UM8_2_line6, M8_UM8_2_PT7_NotB); nand2 M8_UM8_2_PT7_Xo2(M8_UM8_2_PT7_NotA, M8_UM8_2_line6, M8_UM8_2_PT7_line2); nand2 M8_UM8_2_PT7_Xo3(M8_UM8_2_PT7_NotB, M8_UM8_2_line5, M8_UM8_2_PT7_line3); nand2 M8_UM8_2_PT7_Xo4(M8_UM8_2_PT7_line2, M8_UM8_2_PT7_line3, M8_ParB); inv M8_UM8_3_PT0_Xo0(in1956, M8_UM8_3_PT0_NotA); inv M8_UM8_3_PT0_Xo1(in1961, M8_UM8_3_PT0_NotB); nand2 M8_UM8_3_PT0_Xo2(M8_UM8_3_PT0_NotA, in1961, M8_UM8_3_PT0_line2); nand2 M8_UM8_3_PT0_Xo3(M8_UM8_3_PT0_NotB, in1956, M8_UM8_3_PT0_line3); nand2 M8_UM8_3_PT0_Xo4(M8_UM8_3_PT0_line2, M8_UM8_3_PT0_line3, M8_UM8_3_line0); inv M8_UM8_3_PT1_Xo0(in1966, M8_UM8_3_PT1_NotA); inv M8_UM8_3_PT1_Xo1(in1971, M8_UM8_3_PT1_NotB); nand2 M8_UM8_3_PT1_Xo2(M8_UM8_3_PT1_NotA, in1971, M8_UM8_3_PT1_line2); nand2 M8_UM8_3_PT1_Xo3(M8_UM8_3_PT1_NotB, in1966, M8_UM8_3_PT1_line3); nand2 M8_UM8_3_PT1_Xo4(M8_UM8_3_PT1_line2, M8_UM8_3_PT1_line3, M8_UM8_3_line1); inv M8_UM8_3_PT2_Xo0(in1976, M8_UM8_3_PT2_NotA); inv M8_UM8_3_PT2_Xo1(in1981, M8_UM8_3_PT2_NotB); nand2 M8_UM8_3_PT2_Xo2(M8_UM8_3_PT2_NotA, in1981, M8_UM8_3_PT2_line2); nand2 M8_UM8_3_PT2_Xo3(M8_UM8_3_PT2_NotB, in1976, M8_UM8_3_PT2_line3); nand2 M8_UM8_3_PT2_Xo4(M8_UM8_3_PT2_line2, M8_UM8_3_PT2_line3, M8_UM8_3_line2); inv M8_UM8_3_PT3_Xo0(in1986, M8_UM8_3_PT3_NotA); inv M8_UM8_3_PT3_Xo1(in1991, M8_UM8_3_PT3_NotB); nand2 M8_UM8_3_PT3_Xo2(M8_UM8_3_PT3_NotA, in1991, M8_UM8_3_PT3_line2); nand2 M8_UM8_3_PT3_Xo3(M8_UM8_3_PT3_NotB, in1986, M8_UM8_3_PT3_line3); nand2 M8_UM8_3_PT3_Xo4(M8_UM8_3_PT3_line2, M8_UM8_3_PT3_line3, M8_UM8_3_line3); inv M8_UM8_3_PT4_Xo0(in1996, M8_UM8_3_PT4_NotA); inv M8_UM8_3_PT4_Xo1(in2474, M8_UM8_3_PT4_NotB); nand2 M8_UM8_3_PT4_Xo2(M8_UM8_3_PT4_NotA, in2474, M8_UM8_3_PT4_line2); nand2 M8_UM8_3_PT4_Xo3(M8_UM8_3_PT4_NotB, in1996, M8_UM8_3_PT4_line3); nand2 M8_UM8_3_PT4_Xo4(M8_UM8_3_PT4_line2, M8_UM8_3_PT4_line3, M8_UM8_3_line4); inv M8_UM8_3_PT5_Xo3_0(M8_UM8_3_line0, M8_UM8_3_PT5_NotA); inv M8_UM8_3_PT5_Xo3_1(M8_UM8_3_line1, M8_UM8_3_PT5_NotB); inv M8_UM8_3_PT5_Xo3_2(M8_UM8_3_line2, M8_UM8_3_PT5_NotC); and3 M8_UM8_3_PT5_Xo3_3(M8_UM8_3_PT5_NotA, M8_UM8_3_PT5_NotB, M8_UM8_3_line2, M8_UM8_3_PT5_line3); and3 M8_UM8_3_PT5_Xo3_4(M8_UM8_3_PT5_NotA, M8_UM8_3_line1, M8_UM8_3_PT5_NotC, M8_UM8_3_PT5_line4); and3 M8_UM8_3_PT5_Xo3_5(M8_UM8_3_line0, M8_UM8_3_PT5_NotB, M8_UM8_3_PT5_NotC, M8_UM8_3_PT5_line5); and3 M8_UM8_3_PT5_Xo3_6(M8_UM8_3_line0, M8_UM8_3_line1, M8_UM8_3_line2, M8_UM8_3_PT5_line6); nor2 M8_UM8_3_PT5_Xo3_7(M8_UM8_3_PT5_line3, M8_UM8_3_PT5_line4, M8_UM8_3_PT5_line7); nor2 M8_UM8_3_PT5_Xo3_8(M8_UM8_3_PT5_line5, M8_UM8_3_PT5_line6, M8_UM8_3_PT5_line8); nand2 M8_UM8_3_PT5_Xo3_9(M8_UM8_3_PT5_line7, M8_UM8_3_PT5_line8, M8_UM8_3_line5); inv M8_UM8_3_PT6_Xo0(M8_UM8_3_line3, M8_UM8_3_PT6_NotA); inv M8_UM8_3_PT6_Xo1(M8_UM8_3_line4, M8_UM8_3_PT6_NotB); nand2 M8_UM8_3_PT6_Xo2(M8_UM8_3_PT6_NotA, M8_UM8_3_line4, M8_UM8_3_PT6_line2); nand2 M8_UM8_3_PT6_Xo3(M8_UM8_3_PT6_NotB, M8_UM8_3_line3, M8_UM8_3_PT6_line3); nand2 M8_UM8_3_PT6_Xo4(M8_UM8_3_PT6_line2, M8_UM8_3_PT6_line3, M8_UM8_3_line6); inv M8_UM8_3_PT7_Xo0(M8_UM8_3_line5, M8_UM8_3_PT7_NotA); inv M8_UM8_3_PT7_Xo1(M8_UM8_3_line6, M8_UM8_3_PT7_NotB); nand2 M8_UM8_3_PT7_Xo2(M8_UM8_3_PT7_NotA, M8_UM8_3_line6, M8_UM8_3_PT7_line2); nand2 M8_UM8_3_PT7_Xo3(M8_UM8_3_PT7_NotB, M8_UM8_3_line5, M8_UM8_3_PT7_line3); nand2 M8_UM8_3_PT7_Xo4(M8_UM8_3_PT7_line2, M8_UM8_3_PT7_line3, M8_ParQ); inv M8_UM8_4_PT0_Xo0(in1341, M8_UM8_4_PT0_NotA); inv M8_UM8_4_PT0_Xo1(in1348, M8_UM8_4_PT0_NotB); nand2 M8_UM8_4_PT0_Xo2(M8_UM8_4_PT0_NotA, in1348, M8_UM8_4_PT0_line2); nand2 M8_UM8_4_PT0_Xo3(M8_UM8_4_PT0_NotB, in1341, M8_UM8_4_PT0_line3); nand2 M8_UM8_4_PT0_Xo4(M8_UM8_4_PT0_line2, M8_UM8_4_PT0_line3, M8_UM8_4_line0); inv M8_UM8_4_PT1_Xo0(in2427, M8_UM8_4_PT1_NotA); inv M8_UM8_4_PT1_Xo1(in2430, M8_UM8_4_PT1_NotB); nand2 M8_UM8_4_PT1_Xo2(M8_UM8_4_PT1_NotA, in2430, M8_UM8_4_PT1_line2); nand2 M8_UM8_4_PT1_Xo3(M8_UM8_4_PT1_NotB, in2427, M8_UM8_4_PT1_line3); nand2 M8_UM8_4_PT1_Xo4(M8_UM8_4_PT1_line2, M8_UM8_4_PT1_line3, M8_UM8_4_line1); inv M8_UM8_4_PT2_Xo0(in2435, M8_UM8_4_PT2_NotA); inv M8_UM8_4_PT2_Xo1(in2438, M8_UM8_4_PT2_NotB); nand2 M8_UM8_4_PT2_Xo2(M8_UM8_4_PT2_NotA, in2438, M8_UM8_4_PT2_line2); nand2 M8_UM8_4_PT2_Xo3(M8_UM8_4_PT2_NotB, in2435, M8_UM8_4_PT2_line3); nand2 M8_UM8_4_PT2_Xo4(M8_UM8_4_PT2_line2, M8_UM8_4_PT2_line3, M8_UM8_4_line2); inv M8_UM8_4_PT3_Xo0(in2443, M8_UM8_4_PT3_NotA); inv M8_UM8_4_PT3_Xo1(in2446, M8_UM8_4_PT3_NotB); nand2 M8_UM8_4_PT3_Xo2(M8_UM8_4_PT3_NotA, in2446, M8_UM8_4_PT3_line2); nand2 M8_UM8_4_PT3_Xo3(M8_UM8_4_PT3_NotB, in2443, M8_UM8_4_PT3_line3); nand2 M8_UM8_4_PT3_Xo4(M8_UM8_4_PT3_line2, M8_UM8_4_PT3_line3, M8_UM8_4_line3); inv M8_UM8_4_PT4_Xo0(in2451, M8_UM8_4_PT4_NotA); inv M8_UM8_4_PT4_Xo1(in2454, M8_UM8_4_PT4_NotB); nand2 M8_UM8_4_PT4_Xo2(M8_UM8_4_PT4_NotA, in2454, M8_UM8_4_PT4_line2); nand2 M8_UM8_4_PT4_Xo3(M8_UM8_4_PT4_NotB, in2451, M8_UM8_4_PT4_line3); nand2 M8_UM8_4_PT4_Xo4(M8_UM8_4_PT4_line2, M8_UM8_4_PT4_line3, M8_UM8_4_line4); inv M8_UM8_4_PT5_Xo3_0(M8_UM8_4_line0, M8_UM8_4_PT5_NotA); inv M8_UM8_4_PT5_Xo3_1(M8_UM8_4_line1, M8_UM8_4_PT5_NotB); inv M8_UM8_4_PT5_Xo3_2(M8_UM8_4_line2, M8_UM8_4_PT5_NotC); and3 M8_UM8_4_PT5_Xo3_3(M8_UM8_4_PT5_NotA, M8_UM8_4_PT5_NotB, M8_UM8_4_line2, M8_UM8_4_PT5_line3); and3 M8_UM8_4_PT5_Xo3_4(M8_UM8_4_PT5_NotA, M8_UM8_4_line1, M8_UM8_4_PT5_NotC, M8_UM8_4_PT5_line4); and3 M8_UM8_4_PT5_Xo3_5(M8_UM8_4_line0, M8_UM8_4_PT5_NotB, M8_UM8_4_PT5_NotC, M8_UM8_4_PT5_line5); and3 M8_UM8_4_PT5_Xo3_6(M8_UM8_4_line0, M8_UM8_4_line1, M8_UM8_4_line2, M8_UM8_4_PT5_line6); nor2 M8_UM8_4_PT5_Xo3_7(M8_UM8_4_PT5_line3, M8_UM8_4_PT5_line4, M8_UM8_4_PT5_line7); nor2 M8_UM8_4_PT5_Xo3_8(M8_UM8_4_PT5_line5, M8_UM8_4_PT5_line6, M8_UM8_4_PT5_line8); nand2 M8_UM8_4_PT5_Xo3_9(M8_UM8_4_PT5_line7, M8_UM8_4_PT5_line8, M8_UM8_4_line5); inv M8_UM8_4_PT6_Xo0(M8_UM8_4_line3, M8_UM8_4_PT6_NotA); inv M8_UM8_4_PT6_Xo1(M8_UM8_4_line4, M8_UM8_4_PT6_NotB); nand2 M8_UM8_4_PT6_Xo2(M8_UM8_4_PT6_NotA, M8_UM8_4_line4, M8_UM8_4_PT6_line2); nand2 M8_UM8_4_PT6_Xo3(M8_UM8_4_PT6_NotB, M8_UM8_4_line3, M8_UM8_4_PT6_line3); nand2 M8_UM8_4_PT6_Xo4(M8_UM8_4_PT6_line2, M8_UM8_4_PT6_line3, M8_UM8_4_line6); inv M8_UM8_4_PT7_Xo0(M8_UM8_4_line5, M8_UM8_4_PT7_NotA); inv M8_UM8_4_PT7_Xo1(M8_UM8_4_line6, M8_UM8_4_PT7_NotB); nand2 M8_UM8_4_PT7_Xo2(M8_UM8_4_PT7_NotA, M8_UM8_4_line6, M8_UM8_4_PT7_line2); nand2 M8_UM8_4_PT7_Xo3(M8_UM8_4_PT7_NotB, M8_UM8_4_line5, M8_UM8_4_PT7_line3); nand2 M8_UM8_4_PT7_Xo4(M8_UM8_4_PT7_line2, M8_UM8_4_PT7_line3, M8_ParR); inv M8_UM8_5_PT0_Xo0(in2067, M8_UM8_5_PT0_NotA); inv M8_UM8_5_PT0_Xo1(in2072, M8_UM8_5_PT0_NotB); nand2 M8_UM8_5_PT0_Xo2(M8_UM8_5_PT0_NotA, in2072, M8_UM8_5_PT0_line2); nand2 M8_UM8_5_PT0_Xo3(M8_UM8_5_PT0_NotB, in2067, M8_UM8_5_PT0_line3); nand2 M8_UM8_5_PT0_Xo4(M8_UM8_5_PT0_line2, M8_UM8_5_PT0_line3, M8_UM8_5_line0); inv M8_UM8_5_PT1_Xo0(in2078, M8_UM8_5_PT1_NotA); inv M8_UM8_5_PT1_Xo1(in2084, M8_UM8_5_PT1_NotB); nand2 M8_UM8_5_PT1_Xo2(M8_UM8_5_PT1_NotA, in2084, M8_UM8_5_PT1_line2); nand2 M8_UM8_5_PT1_Xo3(M8_UM8_5_PT1_NotB, in2078, M8_UM8_5_PT1_line3); nand2 M8_UM8_5_PT1_Xo4(M8_UM8_5_PT1_line2, M8_UM8_5_PT1_line3, M8_UM8_5_line1); inv M8_UM8_5_PT2_Xo0(in2090, M8_UM8_5_PT2_NotA); inv M8_UM8_5_PT2_Xo1(in2678, M8_UM8_5_PT2_NotB); nand2 M8_UM8_5_PT2_Xo2(M8_UM8_5_PT2_NotA, in2678, M8_UM8_5_PT2_line2); nand2 M8_UM8_5_PT2_Xo3(M8_UM8_5_PT2_NotB, in2090, M8_UM8_5_PT2_line3); nand2 M8_UM8_5_PT2_Xo4(M8_UM8_5_PT2_line2, M8_UM8_5_PT2_line3, M8_UM8_5_line2); inv M8_UM8_5_PT3_Xo0(in2100, M8_UM8_5_PT3_NotA); inv M8_UM8_5_PT3_Xo1(in2096, M8_UM8_5_PT3_NotB); nand2 M8_UM8_5_PT3_Xo2(M8_UM8_5_PT3_NotA, in2096, M8_UM8_5_PT3_line2); nand2 M8_UM8_5_PT3_Xo3(M8_UM8_5_PT3_NotB, in2100, M8_UM8_5_PT3_line3); nand2 M8_UM8_5_PT3_Xo4(M8_UM8_5_PT3_line2, M8_UM8_5_PT3_line3, M8_UM8_5_line3); inv M8_UM8_5_PT4_Xo0(gnd, M8_UM8_5_PT4_NotA); inv M8_UM8_5_PT4_Xo1(gnd, M8_UM8_5_PT4_NotB); nand2 M8_UM8_5_PT4_Xo2(M8_UM8_5_PT4_NotA, gnd, M8_UM8_5_PT4_line2); nand2 M8_UM8_5_PT4_Xo3(M8_UM8_5_PT4_NotB, gnd, M8_UM8_5_PT4_line3); nand2 M8_UM8_5_PT4_Xo4(M8_UM8_5_PT4_line2, M8_UM8_5_PT4_line3, M8_UM8_5_line4); inv M8_UM8_5_PT5_Xo3_0(M8_UM8_5_line0, M8_UM8_5_PT5_NotA); inv M8_UM8_5_PT5_Xo3_1(M8_UM8_5_line1, M8_UM8_5_PT5_NotB); inv M8_UM8_5_PT5_Xo3_2(M8_UM8_5_line2, M8_UM8_5_PT5_NotC); and3 M8_UM8_5_PT5_Xo3_3(M8_UM8_5_PT5_NotA, M8_UM8_5_PT5_NotB, M8_UM8_5_line2, M8_UM8_5_PT5_line3); and3 M8_UM8_5_PT5_Xo3_4(M8_UM8_5_PT5_NotA, M8_UM8_5_line1, M8_UM8_5_PT5_NotC, M8_UM8_5_PT5_line4); and3 M8_UM8_5_PT5_Xo3_5(M8_UM8_5_line0, M8_UM8_5_PT5_NotB, M8_UM8_5_PT5_NotC, M8_UM8_5_PT5_line5); and3 M8_UM8_5_PT5_Xo3_6(M8_UM8_5_line0, M8_UM8_5_line1, M8_UM8_5_line2, M8_UM8_5_PT5_line6); nor2 M8_UM8_5_PT5_Xo3_7(M8_UM8_5_PT5_line3, M8_UM8_5_PT5_line4, M8_UM8_5_PT5_line7); nor2 M8_UM8_5_PT5_Xo3_8(M8_UM8_5_PT5_line5, M8_UM8_5_PT5_line6, M8_UM8_5_PT5_line8); nand2 M8_UM8_5_PT5_Xo3_9(M8_UM8_5_PT5_line7, M8_UM8_5_PT5_line8, M8_UM8_5_line5); inv M8_UM8_5_PT6_Xo0(M8_UM8_5_line3, M8_UM8_5_PT6_NotA); inv M8_UM8_5_PT6_Xo1(M8_UM8_5_line4, M8_UM8_5_PT6_NotB); nand2 M8_UM8_5_PT6_Xo2(M8_UM8_5_PT6_NotA, M8_UM8_5_line4, M8_UM8_5_PT6_line2); nand2 M8_UM8_5_PT6_Xo3(M8_UM8_5_PT6_NotB, M8_UM8_5_line3, M8_UM8_5_PT6_line3); nand2 M8_UM8_5_PT6_Xo4(M8_UM8_5_PT6_line2, M8_UM8_5_PT6_line3, M8_UM8_5_line6); inv M8_UM8_5_PT7_Xo0(M8_UM8_5_line5, M8_UM8_5_PT7_NotA); inv M8_UM8_5_PT7_Xo1(M8_UM8_5_line6, M8_UM8_5_PT7_NotB); nand2 M8_UM8_5_PT7_Xo2(M8_UM8_5_PT7_NotA, M8_UM8_5_line6, M8_UM8_5_PT7_line2); nand2 M8_UM8_5_PT7_Xo3(M8_UM8_5_PT7_NotB, M8_UM8_5_line5, M8_UM8_5_PT7_line3); nand2 M8_UM8_5_PT7_Xo4(M8_UM8_5_PT7_line2, M8_UM8_5_PT7_line3, M8_ParS); inv M8_UM8_6(in14, M8_NotPar0); or2 M8_UM8_7(M8_ParA, in37, M8_line7); or2 M8_UM8_8(M8_ParB, in37, M8_line8); or2 M8_UM8_9(M8_ParR, M8_NotPar0, M8_line9); and3 M8_UM8_10(M8_line8, M8_line7, M8_ParS, M8_line10); and3 M8_UM8_11(M8_ParQ, M8_line9, CompCLAs, M8_line11); and3 M8_UM8_12(M8_line10, M8_line11, out319, out308); inv M8_UM8_13(out308, out225); inv M8_UM8_14(M8_line8, out395); inv M8_UM8_15(M8_line7, out397); inv M8_UM8_16(M8_ParS, out227); inv M8_UM8_17(M8_ParQ, out229); inv M8_UM8_18(M8_line9, out401); or2 M9_UM9_0_MMC0(Abus_1, in559, M9_UM9_0_NewAbus_9); inv M9_UM9_0_PTMuxA_PT0_Xo0(Abus_0, M9_UM9_0_PTMuxA_PT0_NotA); inv M9_UM9_0_PTMuxA_PT0_Xo1(Abus_1, M9_UM9_0_PTMuxA_PT0_NotB); nand2 M9_UM9_0_PTMuxA_PT0_Xo2(M9_UM9_0_PTMuxA_PT0_NotA, Abus_1, M9_UM9_0_PTMuxA_PT0_line2); nand2 M9_UM9_0_PTMuxA_PT0_Xo3(M9_UM9_0_PTMuxA_PT0_NotB, Abus_0, M9_UM9_0_PTMuxA_PT0_line3); nand2 M9_UM9_0_PTMuxA_PT0_Xo4(M9_UM9_0_PTMuxA_PT0_line2, M9_UM9_0_PTMuxA_PT0_line3, M9_UM9_0_PTMuxA_line0); inv M9_UM9_0_PTMuxA_PT1_Xo0(Abus_2, M9_UM9_0_PTMuxA_PT1_NotA); inv M9_UM9_0_PTMuxA_PT1_Xo1(Abus_5, M9_UM9_0_PTMuxA_PT1_NotB); nand2 M9_UM9_0_PTMuxA_PT1_Xo2(M9_UM9_0_PTMuxA_PT1_NotA, Abus_5, M9_UM9_0_PTMuxA_PT1_line2); nand2 M9_UM9_0_PTMuxA_PT1_Xo3(M9_UM9_0_PTMuxA_PT1_NotB, Abus_2, M9_UM9_0_PTMuxA_PT1_line3); nand2 M9_UM9_0_PTMuxA_PT1_Xo4(M9_UM9_0_PTMuxA_PT1_line2, M9_UM9_0_PTMuxA_PT1_line3, M9_UM9_0_PTMuxA_line1); inv M9_UM9_0_PTMuxA_PT2_Xo0(Abus_6, M9_UM9_0_PTMuxA_PT2_NotA); inv M9_UM9_0_PTMuxA_PT2_Xo1(Abus_7, M9_UM9_0_PTMuxA_PT2_NotB); nand2 M9_UM9_0_PTMuxA_PT2_Xo2(M9_UM9_0_PTMuxA_PT2_NotA, Abus_7, M9_UM9_0_PTMuxA_PT2_line2); nand2 M9_UM9_0_PTMuxA_PT2_Xo3(M9_UM9_0_PTMuxA_PT2_NotB, Abus_6, M9_UM9_0_PTMuxA_PT2_line3); nand2 M9_UM9_0_PTMuxA_PT2_Xo4(M9_UM9_0_PTMuxA_PT2_line2, M9_UM9_0_PTMuxA_PT2_line3, M9_UM9_0_PTMuxA_line2); inv M9_UM9_0_PTMuxA_PT3_Xo0(Abus_8, M9_UM9_0_PTMuxA_PT3_NotA); inv M9_UM9_0_PTMuxA_PT3_Xo1(Abus_9, M9_UM9_0_PTMuxA_PT3_NotB); nand2 M9_UM9_0_PTMuxA_PT3_Xo2(M9_UM9_0_PTMuxA_PT3_NotA, Abus_9, M9_UM9_0_PTMuxA_PT3_line2); nand2 M9_UM9_0_PTMuxA_PT3_Xo3(M9_UM9_0_PTMuxA_PT3_NotB, Abus_8, M9_UM9_0_PTMuxA_PT3_line3); nand2 M9_UM9_0_PTMuxA_PT3_Xo4(M9_UM9_0_PTMuxA_PT3_line2, M9_UM9_0_PTMuxA_PT3_line3, M9_UM9_0_PTMuxA_line3); inv M9_UM9_0_PTMuxA_PT4_Xo0(gnd, M9_UM9_0_PTMuxA_PT4_NotA); inv M9_UM9_0_PTMuxA_PT4_Xo1(M9_UM9_0_NewAbus_9, M9_UM9_0_PTMuxA_PT4_NotB); nand2 M9_UM9_0_PTMuxA_PT4_Xo2(M9_UM9_0_PTMuxA_PT4_NotA, M9_UM9_0_NewAbus_9, M9_UM9_0_PTMuxA_PT4_line2); nand2 M9_UM9_0_PTMuxA_PT4_Xo3(M9_UM9_0_PTMuxA_PT4_NotB, gnd, M9_UM9_0_PTMuxA_PT4_line3); nand2 M9_UM9_0_PTMuxA_PT4_Xo4(M9_UM9_0_PTMuxA_PT4_line2, M9_UM9_0_PTMuxA_PT4_line3, M9_UM9_0_PTMuxA_line4); inv M9_UM9_0_PTMuxA_PT5_Xo3_0(M9_UM9_0_PTMuxA_line0, M9_UM9_0_PTMuxA_PT5_NotA); inv M9_UM9_0_PTMuxA_PT5_Xo3_1(M9_UM9_0_PTMuxA_line1, M9_UM9_0_PTMuxA_PT5_NotB); inv M9_UM9_0_PTMuxA_PT5_Xo3_2(M9_UM9_0_PTMuxA_line2, M9_UM9_0_PTMuxA_PT5_NotC); and3 M9_UM9_0_PTMuxA_PT5_Xo3_3(M9_UM9_0_PTMuxA_PT5_NotA, M9_UM9_0_PTMuxA_PT5_NotB, M9_UM9_0_PTMuxA_line2, M9_UM9_0_PTMuxA_PT5_line3); and3 M9_UM9_0_PTMuxA_PT5_Xo3_4(M9_UM9_0_PTMuxA_PT5_NotA, M9_UM9_0_PTMuxA_line1, M9_UM9_0_PTMuxA_PT5_NotC, M9_UM9_0_PTMuxA_PT5_line4); and3 M9_UM9_0_PTMuxA_PT5_Xo3_5(M9_UM9_0_PTMuxA_line0, M9_UM9_0_PTMuxA_PT5_NotB, M9_UM9_0_PTMuxA_PT5_NotC, M9_UM9_0_PTMuxA_PT5_line5); and3 M9_UM9_0_PTMuxA_PT5_Xo3_6(M9_UM9_0_PTMuxA_line0, M9_UM9_0_PTMuxA_line1, M9_UM9_0_PTMuxA_line2, M9_UM9_0_PTMuxA_PT5_line6); nor2 M9_UM9_0_PTMuxA_PT5_Xo3_7(M9_UM9_0_PTMuxA_PT5_line3, M9_UM9_0_PTMuxA_PT5_line4, M9_UM9_0_PTMuxA_PT5_line7); nor2 M9_UM9_0_PTMuxA_PT5_Xo3_8(M9_UM9_0_PTMuxA_PT5_line5, M9_UM9_0_PTMuxA_PT5_line6, M9_UM9_0_PTMuxA_PT5_line8); nand2 M9_UM9_0_PTMuxA_PT5_Xo3_9(M9_UM9_0_PTMuxA_PT5_line7, M9_UM9_0_PTMuxA_PT5_line8, M9_UM9_0_PTMuxA_line5); inv M9_UM9_0_PTMuxA_PT6_Xo0(M9_UM9_0_PTMuxA_line3, M9_UM9_0_PTMuxA_PT6_NotA); inv M9_UM9_0_PTMuxA_PT6_Xo1(M9_UM9_0_PTMuxA_line4, M9_UM9_0_PTMuxA_PT6_NotB); nand2 M9_UM9_0_PTMuxA_PT6_Xo2(M9_UM9_0_PTMuxA_PT6_NotA, M9_UM9_0_PTMuxA_line4, M9_UM9_0_PTMuxA_PT6_line2); nand2 M9_UM9_0_PTMuxA_PT6_Xo3(M9_UM9_0_PTMuxA_PT6_NotB, M9_UM9_0_PTMuxA_line3, M9_UM9_0_PTMuxA_PT6_line3); nand2 M9_UM9_0_PTMuxA_PT6_Xo4(M9_UM9_0_PTMuxA_PT6_line2, M9_UM9_0_PTMuxA_PT6_line3, M9_UM9_0_PTMuxA_line6); inv M9_UM9_0_PTMuxA_PT7_Xo0(M9_UM9_0_PTMuxA_line5, M9_UM9_0_PTMuxA_PT7_NotA); inv M9_UM9_0_PTMuxA_PT7_Xo1(M9_UM9_0_PTMuxA_line6, M9_UM9_0_PTMuxA_PT7_NotB); nand2 M9_UM9_0_PTMuxA_PT7_Xo2(M9_UM9_0_PTMuxA_PT7_NotA, M9_UM9_0_PTMuxA_line6, M9_UM9_0_PTMuxA_PT7_line2); nand2 M9_UM9_0_PTMuxA_PT7_Xo3(M9_UM9_0_PTMuxA_PT7_NotB, M9_UM9_0_PTMuxA_line5, M9_UM9_0_PTMuxA_PT7_line3); nand2 M9_UM9_0_PTMuxA_PT7_Xo4(M9_UM9_0_PTMuxA_PT7_line2, M9_UM9_0_PTMuxA_PT7_line3, M9_UM9_0_ParNewA); inv M9_UM9_0_MMC2_Mux0(in868, M9_UM9_0_MMC2_Not_ContIn); and2 M9_UM9_0_MMC2_Mux1(Abus_9, M9_UM9_0_MMC2_Not_ContIn, M9_UM9_0_MMC2_line1); and2 M9_UM9_0_MMC2_Mux2(M9_UM9_0_ParNewA, in868, M9_UM9_0_MMC2_line2); or2 M9_UM9_0_MMC2_Mux3(M9_UM9_0_MMC2_line1, M9_UM9_0_MMC2_line2, out331); inv M9_UM9_0_MMC3_Mux0(in868, M9_UM9_0_MMC3_Not_ContIn); and2 M9_UM9_0_MMC3_Mux1(Abus_0, M9_UM9_0_MMC3_Not_ContIn, M9_UM9_0_MMC3_line1); and2 M9_UM9_0_MMC3_Mux2(M9_UM9_0_NewAbus_9, in868, M9_UM9_0_MMC3_line2); or2 M9_UM9_0_MMC3_Mux3(M9_UM9_0_MMC3_line1, M9_UM9_0_MMC3_line2, out323); inv M9_UM9_0_MMC4_Mux0(in868, M9_UM9_0_MMC4_Not_ContIn); and2 M9_UM9_0_MMC4_Mux1(Abus_1, M9_UM9_0_MMC4_Not_ContIn, M9_UM9_0_MMC4_line1); and2 M9_UM9_0_MMC4_Mux2(Abus_3, in868, M9_UM9_0_MMC4_line2); or2 M9_UM9_0_MMC4_Mux3(M9_UM9_0_MMC4_line1, M9_UM9_0_MMC4_line2, out321); inv M9_UM9_0_MMC5_Mux0(in868, M9_UM9_0_MMC5_Not_ContIn); and2 M9_UM9_0_MMC5_Mux1(Abus_2, M9_UM9_0_MMC5_Not_ContIn, M9_UM9_0_MMC5_line1); and2 M9_UM9_0_MMC5_Mux2(Abus_4, in868, M9_UM9_0_MMC5_line2); or2 M9_UM9_0_MMC5_Mux3(M9_UM9_0_MMC5_line1, M9_UM9_0_MMC5_line2, out280); inv M9_UM9_0_MMC6(M9_UM9_0_NewAbus_9, M9_UM9_0_NotNewA9); inv M9_UM9_0_MMC7_Xo0(Abus_0, M9_UM9_0_MMC7_NotA); inv M9_UM9_0_MMC7_Xo1(Abus_1, M9_UM9_0_MMC7_NotB); nand2 M9_UM9_0_MMC7_Xo2(M9_UM9_0_MMC7_NotA, Abus_1, M9_UM9_0_MMC7_line2); nand2 M9_UM9_0_MMC7_Xo3(M9_UM9_0_MMC7_NotB, Abus_0, M9_UM9_0_MMC7_line3); nand2 M9_UM9_0_MMC7_Xo4(M9_UM9_0_MMC7_line2, M9_UM9_0_MMC7_line3, M9_UM9_0_line7); inv M9_UM9_0_MMC8_Xo0(M9_UM9_0_line7, M9_UM9_0_MMC8_NotA); inv M9_UM9_0_MMC8_Xo1(M9_UM9_0_NotNewA9, M9_UM9_0_MMC8_NotB); nand2 M9_UM9_0_MMC8_Xo2(M9_UM9_0_MMC8_NotA, M9_UM9_0_NotNewA9, M9_UM9_0_MMC8_line2); nand2 M9_UM9_0_MMC8_Xo3(M9_UM9_0_MMC8_NotB, M9_UM9_0_line7, M9_UM9_0_MMC8_line3); nand2 M9_UM9_0_MMC8_Xo4(M9_UM9_0_MMC8_line2, M9_UM9_0_MMC8_line3, M9_UM9_0_line8); inv M9_UM9_0_MMC9_Xo0(M9_UM9_0_line8, M9_UM9_0_MMC9_NotA); inv M9_UM9_0_MMC9_Xo1(Abus_9, M9_UM9_0_MMC9_NotB); nand2 M9_UM9_0_MMC9_Xo2(M9_UM9_0_MMC9_NotA, Abus_9, M9_UM9_0_MMC9_line2); nand2 M9_UM9_0_MMC9_Xo3(M9_UM9_0_MMC9_NotB, M9_UM9_0_line8, M9_UM9_0_MMC9_line3); nand2 M9_UM9_0_MMC9_Xo4(M9_UM9_0_MMC9_line2, M9_UM9_0_MMC9_line3, M9_UM9_0_line9); inv M9_UM9_0_MMC10_Mux0(in860, M9_UM9_0_MMC10_Not_ContIn); and2 M9_UM9_0_MMC10_Mux1(M9_UM9_0_line9, M9_UM9_0_MMC10_Not_ContIn, M9_UM9_0_MMC10_line1); and2 M9_UM9_0_MMC10_Mux2(Abus_9, in860, M9_UM9_0_MMC10_line2); or2 M9_UM9_0_MMC10_Mux3(M9_UM9_0_MMC10_line1, M9_UM9_0_MMC10_line2, out145); inv M9_UM9_0_MMC11_Mux0(in860, M9_UM9_0_MMC11_Not_ContIn); and2 M9_UM9_0_MMC11_Mux1(M9_UM9_0_NewAbus_9, M9_UM9_0_MMC11_Not_ContIn, M9_UM9_0_MMC11_line1); and2 M9_UM9_0_MMC11_Mux2(Abus_1, in860, M9_UM9_0_MMC11_line2); or2 M9_UM9_0_MMC11_Mux3(M9_UM9_0_MMC11_line1, M9_UM9_0_MMC11_line2, out148); inv M9_UM9_0_MMC12_Mux0(in860, M9_UM9_0_MMC12_Not_ContIn); and2 M9_UM9_0_MMC12_Mux1(vdd, M9_UM9_0_MMC12_Not_ContIn, M9_UM9_0_MMC12_line1); and2 M9_UM9_0_MMC12_Mux2(Abus_0, in860, M9_UM9_0_MMC12_line2); or2 M9_UM9_0_MMC12_Mux3(M9_UM9_0_MMC12_line1, M9_UM9_0_MMC12_line2, out153); buffer M9_UM9_1_MBC0(Abus_8, out290); buffer M9_UM9_1_MBC1(Abus_7, out305); buffer M9_UM9_1_MBC2(Abus_6, out288); buffer M9_UM9_1_MBC3(Abus_5, out303); buffer M9_UM9_1_MBC4(Abus_4, out286); buffer M9_UM9_1_MBC5(Abus_3, out301); buffer M9_UM9_1_MBC6(Abus_2, out299); inv M9_UM9_1_MBC7(Abus_5, out166); inv M9_UM9_1_MBC8(Abus_4, out168); inv M9_UM9_1_MBC9(Abus_3, out171); inv M9_UM9_1_MBC10(Bbus_6, out162); inv M9_UM9_1_MBC11(Bbus_5, out160); inv M9_UM9_1_MBC12(Bbus_4, out164); buffer M9_UM9_2_MRC0(in452, out335); buffer M9_UM9_2_MRC1(in452, out350); buffer M9_UM9_2_MRC2(in452, out391); buffer M9_UM9_2_MRC3(in452, out409); buffer M9_UM9_2_MRC4(in2066, out337); buffer M9_UM9_2_MRC5(in2066, out384); buffer M9_UM9_2_MRC6(in2066, out411); buffer M9_UM9_2_MRC7(in1083, out367); buffer M9_UM9_2_MRC8(in1083, out369); and2 M9_UM9_2_MRC9(in452, in94, out173); inv M9_UM9_2_MRC10(in2100, M9_UM9_2_NotPTIns10); inv M9_UM9_2_MRC11(in2096, M9_UM9_2_NotPTIns11); nand2 M9_UM9_2_MRC12_Xo1_0(Bbus_9, M9_UM9_2_NotPTIns10, M9_UM9_2_MRC12_NotAB); and2 M9_UM9_2_MRC12_Xo1_1(Bbus_9, M9_UM9_2_MRC12_NotAB, M9_UM9_2_MRC12_line1); and2 M9_UM9_2_MRC12_Xo1_2(M9_UM9_2_MRC12_NotAB, M9_UM9_2_NotPTIns10, M9_UM9_2_MRC12_line2); or2 M9_UM9_2_MRC12_Xo1_3(M9_UM9_2_MRC12_line1, M9_UM9_2_MRC12_line2, M9_UM9_2_line12); nand2 M9_UM9_2_MRC13_Xo1_0(Bbus_7, M9_UM9_2_NotPTIns11, M9_UM9_2_MRC13_NotAB); and2 M9_UM9_2_MRC13_Xo1_1(Bbus_7, M9_UM9_2_MRC13_NotAB, M9_UM9_2_MRC13_line1); and2 M9_UM9_2_MRC13_Xo1_2(M9_UM9_2_MRC13_NotAB, M9_UM9_2_NotPTIns11, M9_UM9_2_MRC13_line2); or2 M9_UM9_2_MRC13_Xo1_3(M9_UM9_2_MRC13_line1, M9_UM9_2_MRC13_line2, M9_UM9_2_line13); inv M9_UM9_2_MRC14_RIV0(M9_UM9_2_line12, M9_UM9_2_MRC14_NotA); and2 M9_UM9_2_MRC14_RIV1(M9_UM9_2_line12, M9_UM9_2_MRC14_NotA, M9_UM9_2_MRC14_line1); or2 M9_UM9_2_MRC14_RIV2(M9_UM9_2_MRC14_line1, M9_UM9_2_MRC14_NotA, M9_UM9_2_line14); inv M9_UM9_2_MRC15_RIV0(M9_UM9_2_line13, M9_UM9_2_MRC15_NotA); and2 M9_UM9_2_MRC15_RIV1(M9_UM9_2_line13, M9_UM9_2_MRC15_NotA, M9_UM9_2_MRC15_line1); or2 M9_UM9_2_MRC15_RIV2(M9_UM9_2_MRC15_line1, M9_UM9_2_MRC15_NotA, M9_UM9_2_line15); nand2 M9_UM9_2_MRC16(M9_UM9_2_line14, M9_UM9_2_line15, out156); and2 M9_UM9_2_MRC17(in7, in661, M9_UM9_2_line17); inv M9_UM9_2_MRC18(M9_UM9_2_line17, out223); and2 M9_UM9_2_MRC19(in2106, M9_UM9_2_line17, M9_UM9_2_line19); inv M9_UM9_2_MRC20(M9_UM9_2_line19, out217); nand2 M9_UM9_2_MRC21(in567, M9_UM9_2_line17, out234); and3 M9_UM9_2_MRC22(in2, in15, in661, M9_UM9_2_line22); inv M9_UM9_2_MRC23(M9_UM9_2_line22, out259); and4 M9_UM9_2_MRC24(in661, in483, in36, out319, M9_UM9_2_line24); inv M9_UM9_2_MRC25(M9_UM9_2_line24, out176); and2 M9_UM9_2_MRC26(in1, in3, M9_UM9_2_line26); inv M9_UM9_2_MRC27(M9_UM9_2_line26, M9_UM9_2_line27); and4 M9_UM9_2_MRC28(in661, in483, out319, M9_UM9_2_line27, M9_UM9_2_line28); inv M9_UM9_2_MRC29(M9_UM9_2_line28, out188); and4 M9_UM9_2_MRC30(in2072, in2078, in2084, in2090, M9_UM9_2_line30); inv M9_UM9_2_MRC31(M9_UM9_2_line30, out158); assign out295 = out331; assign out282 = out323; assign out284 = out321; assign out297 = out280; assign out169 = in169; assign out174 = in174; assign out177 = in177; assign out178 = in178; assign out179 = in179; assign out180 = in180; assign out181 = in181; assign out182 = in182; assign out183 = in183; assign out184 = in184; assign out185 = in185; assign out186 = in186; assign out189 = in189; assign out190 = in190; assign out191 = in191; assign out192 = in192; assign out193 = in193; assign out194 = in194; assign out195 = in195; assign out196 = in196; assign out197 = in197; assign out198 = in198; assign out199 = in199; assign out200 = in200; assign out201 = in201; assign out202 = in202; assign out203 = in203; assign out204 = in204; assign out205 = in205; assign out206 = in206; assign out207 = in207; assign out208 = in208; assign out209 = in209; assign out210 = in210; assign out211 = in211; assign out212 = in212; assign out213 = in213; assign out214 = in214; assign out215 = in215; assign out239 = in239; assign out240 = in240; assign out241 = in241; assign out242 = in242; assign out243 = in243; assign out244 = in244; assign out245 = in245; assign out246 = in246; assign out247 = in247; assign out248 = in248; assign out249 = in249; assign out250 = in250; assign out251 = in251; assign out252 = in252; assign out253 = in253; assign out254 = in254; assign out255 = in255; assign out256 = in256; assign out257 = in257; assign out262 = in262; assign out263 = in263; assign out264 = in264; assign out265 = in265; assign out266 = in266; assign out267 = in267; assign out268 = in268; assign out269 = in269; assign out270 = in270; assign out271 = in271; assign out272 = in272; assign out273 = in273; assign out274 = in274; assign out275 = in275; assign out276 = in276; assign out277 = in277; assign out278 = in278; assign out279 = in279; assign vdd = 1'b1; assign gnd = 1'b0; endmodule |
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<TITLE>
High-Level Model of c3540
</TITLE>
</HEAD>
<DIV>
<H1 CLASS="Title">
<A NAME="pgfId=933994">
</A>
High-Level Model of c3540</H1>
<br>
<P>
<B>Statistics: </B>50 inputs; 22 outputs; 1669 gates</P>
<P>
<B>Function: </B>8-bit ALU with binary and BCD arithmetic, and logic and shift operations.</P>
<P>
This benchmark is an 8-bit ALU that can perform binary and BCD arithmetic operations as well as logic and shift operations. Logic operations are intermixed with arithmetic ones, much as in the TTL 74181. BCD addition is done via a two's-complement adder by adding 6 to both digits of the first operand, and then subtracting 6 from the digits of the result if they do not generate a carry. A total of 14 control inputs are used for multiplexing and masking data inputs. Most multiplexers in this circuit have an odd-number of inputs, e.g, 3 and 5, and their selection is different between lower and upper digits (4 bits). The selection mechanism of M4 (output MB) is even more complicated; see below for details. The largest module is M5 (ALU_Core), which consists of two 4-bit CLAs. Module M8 (Shifter) can shift the input bus A by 1 to 8 bits in either direction. Parity and zero flags are generated by module M12 (Flags) using the input buses A, B and the output bus Z; see the relevant figures or the Verilog model for their exact definition. Various logic functions of A and B are calculated by module M13 which does not have an apparent high-level structure.</P>
<br>
<A HREF="#pgfId=934023">
<B>Inputs/Outputs vs. Netlist Numbers</B></A>
<HR>
<P><B>Models:</B></P>
<UL>
<LI>I. Original ISCAS gate-level netlist
<UL>
<LI><A HREF="c3540.isc">in ISCAS-89 format</A> </LI>
<LI><A HREF="c3540gate.v">in Verilog</A></LI>
</UL>
</LI>
<LI>II. <A HREF="c3540high.v">Verilog hierarchical netlist</A>
(functionally equivalent to I) </LI>
<LI>III. <A HREF="flat3540.v">Verilog flat netlist </A>
(flat version of II; functionally equivalent to I,
but with minor structural differences) </LI>
</UL>
<HR>
<DIV>
<MAP NAME="c3540-1">
</MAP>
<IMG SRC="c3540-1.gif" USEMAP="#c3540-1">
</DIV>
<br>
<HR>
<B>Modules M1 (BCD_add) and M7 (BCD_sub)</B>
<P>In order to perform BCD addition with a two's complement adder, module M1 adds 6 to each digit of the input bus, and module M7 subtracts 6 from each digit of the result if there is no carry from that digit. </P>
<P>
The logic equations for the lower digit of M1 (upper digit is similar):</P>
<UL>
<LI CLASS="Bulleted">
<A NAME="pgfId=924788">
</A>
Out[3] = In[3] + In[2] + In[1]</LI>
<LI CLASS="Bulleted">
<A NAME="pgfId=925123">
</A>
Out[2] = !(In[2] In[1])</LI>
<LI CLASS="Bulleted">
<A NAME="pgfId=925124">
</A>
Out[1] = !In[1]</LI>
<LI CLASS="Bulleted">
<A NAME="pgfId=925125">
</A>
Out[0] = In[0]</LI>
</UL>
<P>The logic equations for the lower digit of M7 (upper digit is similar):</P>
<UL>
<LI CLASS="Bulleted">
<A NAME="pgfId=925092">
</A>
Out[3] = In[3].Carry4 + In[3]. In[2] . In[1]. !Carry4</LI>
<LI CLASS="Bulleted">
<A NAME="pgfId=925116">
</A>
Out[2] = In[2] In[1]. !Carry4</LI>
<LI CLASS="Bulleted">
<A NAME="pgfId=925117">
</A>
Out[1] = In[1] !Carry4</LI>
<LI CLASS="Bulleted">
<A NAME="pgfId=925122">
</A>
Out[0] = In[0]</LI>
</UL>
<HR>
<B>Module M3 (MainMux1)</B>
<DIV>
<IMG SRC="c3540-2.gif">
</DIV>
<P CLASS="Paragraph">
<A NAME="pgfId=934696">
</A>
This module consists of two cascaded multiplexers, as shown above. The control signals Cont[3:0] determine the select inputs of M3. Notice that selection is different between the lower and the upper digits of the output.</P>
<TABLE BORDER="2">
<TR>
<TH ROWSPAN="1" COLSPAN="2">
<P CLASS="CellHeading">
<A NAME="pgfId=931752">
</A>
Cont3[3:0]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931756">
</A>
0</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931758">
</A>
1</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931760">
</A>
2</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931762">
</A>
3</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931764">
</A>
4</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931766">
</A>
5</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931768">
</A>
6</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931770">
</A>
7</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931772">
</A>
8</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931774">
</A>
9</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931776">
</A>
10</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931778">
</A>
11</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931780">
</A>
12</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931782">
</A>
13</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931784">
</A>
14</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931786">
</A>
15</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="2" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931788">
</A>
MA</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931790">
</A>
MA[3:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931792">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931794">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931796">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931798">
</A>
In3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931800">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931802">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931804">
</A>
In1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931806">
</A>
In5</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931808">
</A>
In2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931810">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931812">
</A>
In2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931814">
</A>
In4</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931816">
</A>
In2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931818">
</A>
In5</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931820">
</A>
In1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931822">
</A>
In5</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931826">
</A>
MA[7:4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931828">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931830">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931832">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931834">
</A>
In3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931836">
</A>
In2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931838">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931840">
</A>
In1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931842">
</A>
In5</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931844">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931846">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931848">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931850">
</A>
In4</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931852">
</A>
In2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931854">
</A>
In5</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931856">
</A>
In1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931858">
</A>
In5</P>
</TD>
</TR>
</TABLE>
<br>
<HR>
<P>
<B>Module M4 (MainMux2)</B></P>
<DIV>
<IMG SRC="c3540-3.gif">
</DIV>
<P CLASS="Paragraph">
<A NAME="pgfId=934751">
</A>
Like M3, Module M4 is made up of two cascaded multiplexers. However, it's select logic is more involved. The control signals Cont[6:3] and Cont[1:0] are decoded into the following select signals:</P>
<UL>
<LI CLASS="Bulleted">
<A NAME="pgfId=932037">
</A>
CHi = Cont[0]. Cont[1]. !(Cont[3]. Cont[5])</LI>
<LI CLASS="Bulleted">
<A NAME="pgfId=924346">
</A>
CLo1 = !Cont[0]. !Cont[5]. Cont[6]</LI>
<LI CLASS="Bulleted">
<A NAME="pgfId=924352">
</A>
CLo2 = !Cont[0]. Cont[6]</LI>
<LI CLASS="Bulleted">
<A NAME="pgfId=924358">
</A>
CLo3 = !Cont[0]. (Cont[5]+Cont[6])</LI>
</UL>
<br>
<TABLE BORDER="2">
<TR>
<TH ROWSPAN="2" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931926">
</A>
Selected input</P>
</TH>
<TH ROWSPAN="1" COLSPAN="3">
<P CLASS="CellHeading">
<A NAME="pgfId=931928">
</A>
Mux output MB[7:0]</P>
</TH>
</TR>
<TR>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931936">
</A>
MB[2:0]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931938">
</A>
MB[3]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=931940">
</A>
MB[7:4]</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931942">
</A>
In0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931944">
</A>
!CHi. !CLo1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931946">
</A>
!CHi. !CLo2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931948">
</A>
!CHi. !CLo3</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931950">
</A>
In1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931952">
</A>
!CHi. CLo1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931954">
</A>
!CHi. CLo2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931956">
</A>
!CHi. CLo3</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931958">
</A>
In2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931960">
</A>
CHi. !Cont[3]. !Cont[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931962">
</A>
CHi .!Cont[3]. !Cont[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931964">
</A>
CHi. !Cont[3]. !Cont[4]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931966">
</A>
In3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931968">
</A>
CHi. !Cont[3]. Cont[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931970">
</A>
CHi. !Cont[3]. Cont[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931972">
</A>
CHi. !Cont[3]. Cont[4]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931974">
</A>
In4</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931976">
</A>
CHi. Cont[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931978">
</A>
CHi. Cont[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=931980">
</A>
CHi. Cont[3]</P>
</TD>
</TR>
</TABLE>
<P>
Notice that since In1 is connected to the single bit K input, all the bits of MB can be set to K (0 or 1).</P>
<br>
<HR>
<B>Module M5 (ALU_Core)</B>
<P CLASS="Paragraph">
<A NAME="pgfId=925345">
</A>
This is the largest module of the c3540 benchmark. The control inputs to this module are Cont[12:7] and Cont[2:0]. An internal signal called Mode determines whether a logic or an arithmetic operation is to be performed:</P>
<UL>
<LI CLASS="Bulleted">
<A NAME="pgfId=925441">
</A>
Mode = !Cont[0]. Cont[1]. !Cont[2]. Cont[8]. Cont[9]</LI>
</UL>
<P CLASS="Paragraph-cont">
<A NAME="pgfId=925358">
</A>
Mode is 1 for a logic operation, and 0 for an arithmetic operation. In the case of arithmetic operations, an additional control signal named Mask7_6 is used to mask bits #7 and #6 of the MA bus:</P>
<UL>
<LI CLASS="Bulleted">
<A NAME="pgfId=925455">
</A>
Mask7_6 = !Cont[0]. Cont[1]. !Cont[2]. Cont[8]</LI>
</UL>
<P CLASS="Paragraph-cont">
<A NAME="pgfId=925443">
</A>
As in the TTL circuit 74181, logic and arithmetic operations are intermixed. A block named Logic_and_GP computes both logic operations as well as the generate and propagate signals used for binary addition. The carry signals are computed by CalcCarry, and the final result of the ALU is obtained by XORing the carry signals with a modified propagate signal called XP.</P>
<P>
<DIV>
<IMG SRC="c3540-4.gif" USEMAP="#c3540-1">
</DIV>
<br>
<DIV>
<IMG SRC="c3540-5.gif" USEMAP="#c3540-1">
</DIV>
<br>
<DIV>
<IMG SRC="c3540-6.gif" USEMAP="#c3540-1">
</DIV>
<P>
The set of logic and arithmetic operations performed by ALU_Core is shown below. The table is valid for Cin=0. Logic 1 is added to the result if Cin=1 (this applies to arithmetic as well as logic operations.)</P>
<TABLE BORDER="2">
<TR>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935095">
</A>
Cont [11]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935097">
</A>
Cont[12]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935099">
</A>
Cont [10]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935101">
</A>
Cont[7]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935103">
</A>
Arithmetic Function </P>
<P CLASS="CellHeading">
<A NAME="pgfId=935104">
</A>
(XP xor XCarry)</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935106">
</A>
Logic Function (XP)</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935108">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935110">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935112">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935114">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935116">
</A>
MA</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935118">
</A>
0</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935120">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935122">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935124">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935126">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935128">
</A>
MA plus MA.MB</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935130">
</A>
MA.MB</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935132">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935134">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935136">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935138">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935140">
</A>
MA plus MA.!MB
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935142">
</A>
MA.!MB
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935144">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935146">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935148">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935150">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935155">
</A>
MA plus MA (shift left)
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935157">
</A>
MA</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935159">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935161">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935163">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935165">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935167">
</A>
MA+MB</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935169">
</A>
!MA.MB</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935171">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935173">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935175">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935177">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935179">
</A>
MA plus MB</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935181">
</A>
MB</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935183">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935185">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935187">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935189">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935191">
</A>
(MA+MB) plus MA.!MB
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935193">
</A>
MA xor MB</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935195">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935197">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935199">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935201">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935203">
</A>
(MA+MB) plus MA</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935205">
</A>
MA+MB</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935207">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935209">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935211">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935213">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935215">
</A>
MA+!MB
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935217">
</A>
!MA.!MB
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935219">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935221">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935223">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935225">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935227">
</A>
(MA+!MB) plus MA.MB</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935229">
</A>
MA xnor MB
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935231">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935233">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935235">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935237">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935239">
</A>
MA minus MB minus 1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935241">
</A>
!MB
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935243">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935245">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935247">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935249">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935251">
</A>
(MA+!MB) plus MA</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935253">
</A>
MA+!MB
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935255">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935257">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935259">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935261">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935263">
</A>
minus 1 (2's compl)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935265">
</A>
!MA
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935267">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935269">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935271">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935273">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935275">
</A>
MA.MB minus 1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935277">
</A>
!MA+MB</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935279">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935281">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935283">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935285">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935287">
</A>
MA.!MB minus 1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935289">
</A>
!MA+!MB
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935291">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935293">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935295">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935297">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935299">
</A>
MA minus 1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935301">
</A>
1</P>
</TD>
</TR>
</TABLE>
<br>
Legend for operators:
<UL>
<LI>! : complement</LI>
<LI>+ : logical OR</LI>
<LI>. : logical AND</LI>
<LI>xor : logical XOR</LI>
<LI>xnor : logical XNOR</LI>
<LI>plus : arithmetic add</LI>
<LI>minus: arithmetic subtract</LI>
</UL>
<br>
<HR>
<B>Module M8 (Shifter)</B>
<DIV>
<IMG SRC="c3540-7.gif">
</DIV>
<P CLASS="Paragraph">
<A NAME="pgfId=928565">
</A>
This module contains logic for shifting the input bus A by 1 to 8 bits in either direction. When shifting towards LSB (MSB), the empty bit positions are filled by a Q (R) bus. The Shifter decodes the control signals Cont[12:10], and Cont[2] into 8 signals, which are the select inputs for sixteen 8:1 multiplexers. Input selection for these multiplexers is shown below. The X and Y buses are fed into a 2:1 multiplexer controlled by Cont[3]. There is an additional multiplexer for bit #7 whose second input is A[7]; this can be used for shifting signed input data.</P>
<br>
<TABLE BORDER="2">
<TR>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935385">
</A>
Cont[2,10,11,12]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935387">
</A>
X</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935389">
</A>
X[0]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935391">
</A>
X[1]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935393">
</A>
X[2]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935395">
</A>
X[3]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935397">
</A>
X[4]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935399">
</A>
X[5]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935401">
</A>
X[6]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935403">
</A>
X[7]</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935405">
</A>
9</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935407">
</A>
X0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935409">
</A>
A[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935411">
</A>
A[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935413">
</A>
A[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935415">
</A>
A[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935417">
</A>
A[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935419">
</A>
A[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935421">
</A>
A[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935423">
</A>
Q[0]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935425">
</A>
0-7,10</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935427">
</A>
X1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935429">
</A>
A[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935431">
</A>
A[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935433">
</A>
A[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935435">
</A>
A[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935437">
</A>
A[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935439">
</A>
A[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935441">
</A>
Q[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935443">
</A>
Q[1]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935445">
</A>
11</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935447">
</A>
X2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935449">
</A>
A[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935451">
</A>
A[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935453">
</A>
A[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935455">
</A>
A[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935457">
</A>
A[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935459">
</A>
Q[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935461">
</A>
Q[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935463">
</A>
Q[2]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935465">
</A>
12</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935467">
</A>
X3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935469">
</A>
A[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935471">
</A>
A[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935473">
</A>
A[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935475">
</A>
A[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935477">
</A>
Q[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935479">
</A>
Q[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935481">
</A>
Q[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935483">
</A>
Q[3]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935485">
</A>
13</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935487">
</A>
X4</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935489">
</A>
A[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935491">
</A>
A[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935493">
</A>
A[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935495">
</A>
Q[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935497">
</A>
Q[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935499">
</A>
Q[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935501">
</A>
Q[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935503">
</A>
Q[4]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935505">
</A>
14</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935507">
</A>
X5</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935509">
</A>
A[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935511">
</A>
A[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935513">
</A>
Q[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935515">
</A>
Q[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935517">
</A>
Q[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935519">
</A>
Q[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935521">
</A>
Q[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935523">
</A>
Q[5]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935525">
</A>
15</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935527">
</A>
X6</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935529">
</A>
A[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935531">
</A>
Q[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935533">
</A>
Q[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935535">
</A>
Q[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935537">
</A>
Q[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935539">
</A>
Q[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935541">
</A>
Q[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935543">
</A>
Q[6]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935545">
</A>
8</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935547">
</A>
X7</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935549">
</A>
Q[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935551">
</A>
Q[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935553">
</A>
Q[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935555">
</A>
Q[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935557">
</A>
Q[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935559">
</A>
Q[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935561">
</A>
Q[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935563">
</A>
Q[7]</P>
</TD>
</TR>
</TABLE>
<br>
<TABLE BORDER="2">
<TR>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935604">
</A>
Cont[2,10,11,12]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935606">
</A>
Y</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935608">
</A>
Y[0]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935610">
</A>
Y[1]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935612">
</A>
Y[2]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935614">
</A>
Y[3]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935616">
</A>
Y[4]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935618">
</A>
Y[5]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935620">
</A>
Y[6]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=935622">
</A>
Y[7]</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935624">
</A>
9</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935626">
</A>
Y0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935628">
</A>
R[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935630">
</A>
A[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935632">
</A>
A[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935634">
</A>
A[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935636">
</A>
A[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935638">
</A>
A[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935640">
</A>
A[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935642">
</A>
A[6]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935644">
</A>
0-7,10</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935646">
</A>
Y1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935648">
</A>
R[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935650">
</A>
R[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935652">
</A>
A[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935654">
</A>
A[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935656">
</A>
A[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935658">
</A>
A[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935660">
</A>
A[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935662">
</A>
A[5]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935664">
</A>
11</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935666">
</A>
Y2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935668">
</A>
R[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935670">
</A>
R[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935672">
</A>
R[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935674">
</A>
A[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935676">
</A>
A[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935678">
</A>
A[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935680">
</A>
A[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935682">
</A>
A[4]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935684">
</A>
12</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935686">
</A>
Y3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935688">
</A>
R[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935690">
</A>
R[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935692">
</A>
R[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935694">
</A>
R[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935696">
</A>
A[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935698">
</A>
A[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935700">
</A>
A[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935702">
</A>
A[3]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935704">
</A>
13</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935706">
</A>
Y4</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935708">
</A>
R[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935710">
</A>
R[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935712">
</A>
R[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935714">
</A>
R[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935716">
</A>
R[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935718">
</A>
A[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935720">
</A>
A[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935722">
</A>
A[2]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935724">
</A>
14</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935726">
</A>
Y5</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935728">
</A>
R[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935730">
</A>
R[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935732">
</A>
R[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935734">
</A>
R[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935736">
</A>
R[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935738">
</A>
R[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935740">
</A>
A[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935742">
</A>
A[1]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935744">
</A>
15</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935746">
</A>
Y6</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935748">
</A>
R[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935750">
</A>
R[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935752">
</A>
R[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935754">
</A>
R[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935756">
</A>
R[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935758">
</A>
R[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935760">
</A>
R[7]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935762">
</A>
A[0]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935764">
</A>
8</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935766">
</A>
Y7</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935768">
</A>
R[0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935770">
</A>
R[1]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935772">
</A>
R[2]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935774">
</A>
R[3]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935776">
</A>
R[4]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935778">
</A>
R[5]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935780">
</A>
R[6]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=935782">
</A>
R[7]</P>
</TD>
</TR>
</TABLE>
<br>
<HR>
<B>Module M9</B>
<DIV>
<IMG SRC="c3540-8.gif">
</DIV>
<P>
This is a relatively small module that appears to calculate some special-purpose logic functions of the input buses A and B. Five control inputs to this module are Cont[6] and Cont[3:0]. The select inputs of the 3:1 multiplexer Mux3_1c are calculated by</P>
<UL>
<LI CLASS="Bulleted">
<A NAME="pgfId=932000">
</A>
CHi = !(Cont[0]. !Cont[1]. Cont[2]. Cont[3])</LI>
<LI CLASS="Bulleted">
<A NAME="pgfId=932014">
</A>
CLo = !(Cont[0]. !Cont[1]. Cont[2]. !Cont[3])</LI>
</UL>
<br>
<TABLE BORDER="2">
<TR>
<TH ROWSPAN="1" COLSPAN="2">
<P CLASS="CellHeading">
<A NAME="pgfId=930931">
</A>
Select inputs</P>
</TH>
<TH ROWSPAN="2" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=930935">
</A>
Mux output H[3:0]</P>
</TH>
</TR>
<TR>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=930937">
</A>
CHi</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=930939">
</A>
CLo</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=930943">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=930945">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=930947">
</A>
(not possible)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=930949">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=930951">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=930953">
</A>
T1[3:0]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=930955">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=930957">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=930959">
</A>
{ 2'b00, T2[1:0] }</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=930961">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=930963">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=930965">
</A>
A[3:0]</P>
</TD>
</TR>
</TABLE>
<P CLASS="Paragraph">
<A NAME="pgfId=935885">
</A>
The details of LogicBlockM9 are shown below. It seems to calculate a non-standard function. It may be some type of code translation or encryption. The authors will be glad to know if you have any insight into the function of this particular block. Please contact us if you have any information.</P>
<br>
<DIV>
<IMG SRC="c3540-9.gif" USEMAP="#c3540-1">
</DIV>
<br>
<HR>
<B>Module M10</B>
<P CLASS="Paragraph">
<A NAME="pgfId=920243">
</A>
This module contains a set of eight 3:1 multiplexers of type Mux3_1c. As with the other multiplexers, the lower and upper digits of the output are selected differently. The control signals Cont[7],Cont[3:0] are decoded into three select signals CHi, CLo1, CLo2 as follows.</P>
<UL>
<LI CLASS="Bulleted">
<A NAME="pgfId=932214">
</A>
CHi = !(Cont[0]. Cont[1]. (!Cont[2] + Cont[7]))</LI>
<LI CLASS="Bulleted">
<A NAME="pgfId=932218">
</A>
CLo1 = Cont[1]+Cont[2]+Cont[3]</LI>
<LI CLASS="Bulleted">
<A NAME="pgfId=932225">
</A>
CLo2 = Cont[1]+Cont[3]</LI>
</UL>
<br>
<TABLE BORDER="2">
<TR>
<TH ROWSPAN="1" COLSPAN="2">
<P CLASS="CellHeading">
<A NAME="pgfId=932324">
</A>
Select inputs</P>
</TH>
<TH ROWSPAN="2" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=932328">
</A>
Mux output W[3:0]</P>
</TH>
<TH ROWSPAN="1" COLSPAN="2">
<P CLASS="CellHeading">
<A NAME="pgfId=932405">
</A>
Select inputs</P>
</TH>
<TH ROWSPAN="2" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=932409">
</A>
Mux output W[7:4]</P>
</TH>
</TR>
<TR>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=932330">
</A>
CHi</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=932332">
</A>
CLo1</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=932413">
</A>
CHi</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=932415">
</A>
CLo2</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932336">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932338">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932340">
</A>
(not possible)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932378">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932380">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932417">
</A>
(not possible)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932342">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932344">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932346">
</A>
S[3:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932384">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932386">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932421">
</A>
S[7:4]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932348">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932350">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932352">
</A>
XP[3:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932390">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932392">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932423">
</A>
XP[7:4]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932354">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932356">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932358">
</A>
H[3:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932396">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932398">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932425">
</A>
H[7:4]</P>
</TD>
</TR>
</TABLE>
<br>
<HR>
<B>Module M11</B>
<P CLASS="Paragraph">
<A NAME="pgfId=932477">
</A>
This module consists of eight 3:1 multiplexers of type Mux3_1c. Unlike M10, its lower and upper digits are selected by the same two signals which are decoded from the control signals Cont[6:5], Cont[2:0] as follows.</P>
<UL>
<LI CLASS="Bulleted">
<A NAME="pgfId=932489">
</A>
CHi = Cont[0]. !(Cont[1]. !Cont[2]. Cont[6])</LI>
<LI CLASS="Bulleted">
<A NAME="pgfId=932490">
</A>
CLo = !(Cont[0]. !Cont[1]. Cont[2]. !Cont[5])</LI>
</UL>
<br>
<TABLE BORDER="2">
<TR>
<TH ROWSPAN="1" COLSPAN="2">
<P CLASS="CellHeading">
<A NAME="pgfId=932518">
</A>
Select inputs</P>
</TH>
<TH ROWSPAN="2" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=932522">
</A>
Mux output Z[7:0]</P>
</TH>
</TR>
<TR>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=932524">
</A>
CHi</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=932526">
</A>
CLo</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932530">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932532">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932534">
</A>
(not possible)</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932536">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932538">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932540">
</A>
F[7:0]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932542">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932544">
</A>
0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932546">
</A>
F_BCD[7:0]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932548">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932550">
</A>
1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=932552">
</A>
W[7:0]</P>
</TD>
</TR>
</TABLE>
<br>
<HR>
<B>Module M12 (Flags)</B>
<DIV>
<IMG SRC="c3540-10.gif">
</DIV>
<P CLASS="Paragraph">
<A NAME="pgfId=933007">
</A>
This module generates two zero flags and four parity outputs. As shown above, the parities are calculated from the input buses A and B, and the output bus Z. The zero flags are calculated from the output bus Z only. Three control inputs to M12 are Cont[13] and Cont[9:8]. Paralleling the type of masking used in ALU_Core by Mask7_6, this module can mask out Z[7:6] for the OddParZ_Cont and ZeroZ_Cont outputs using an internally generated ContFlag signal.</P>
<br>
<HR>
<br>
<A NAME="pgfId=934023">
</A>
<TABLE BORDER="1">
<TR>
<TH ROWSPAN="1" COLSPAN="1">
<P>
Input</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=934025">
</A>
Netlist numbers</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934027">
</A>
A[7:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934029">
</A>
50, 58, 68, 77, 87, 97, 107, 116</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934031">
</A>
B[7:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934033">
</A>
226, 232, 238, 244, 250, 257, 264, 270</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934035">
</A>
Q[7:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934037">
</A>
124, 125, 128, 132, 137, 143, 150, 159</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934039">
</A>
R[7:0)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934041">
</A>
283, 294, 303, 311, 317, 322, 326, 329</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934043">
</A>
T[1:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934045">
</A>
222, 223</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934047">
</A>
Cin</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934049">
</A>
330</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934051">
</A>
K</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934053">
</A>
274</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934055">
</A>
Cont[13:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934057">
</A>
2897, 200, 190, 179, 343, 213, 169, 45, 41, 1698, 33, 20, 13, 1</P>
</TD>
</TR>
</TABLE>
<br>
<br>
<TABLE BORDER=1">
<TR>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=934574">
</A>
Output</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=934576">
</A>
Netlist numbers</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934610">
</A>
Z[7:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934612">
</A>
375, 378, 381, 384, 387, 390, 393, 396</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934614">
</A>
OddParZ, OddParZ_Cont</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934616">
</A>
402, 405</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934618">
</A>
OddParA</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934620">
</A>
351</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934622">
</A>
OddParB</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934624">
</A>
358</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934626">
</A>
NotZeroZ, ZeroZ_Cont</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934628">
</A>
407, 409</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934630">
</A>
XCarry2, Cout_in0</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934632">
</A>
399, 369</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934634">
</A>
PropThru</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934636">
</A>
372</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934638">
</A>
MiscOuts[4:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBody">
<A NAME="pgfId=934640">
</A>
353, 355, 361, 364, 367</P>
</TD>
</TR>
</TABLE>
<br>
<P>
<A HREF="#pgfId=933994">
Go to top of this file</A></P>
<P>
<A HREF="../benchmark.html">
Go back to the Benchmark List</A></P>
</DIV>
</BODY>
</HTML>
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Added c3540/c3540.isc.
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 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895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 | # combinational logic example "c3540" #------------------------------------------------------------- # # # total number of lines in the netlist .............. 3540 # simplistically reduced equivalent fault set size = 3428 # lines from primary input gates ....... 50 # lines from primary output gates ....... 22 # lines from interior gate outputs ...... 1647 # lines from ** 579 ** fanout stems ... 1821 # # avg_fanin = 1.76, max_fanin = 8 # avg_fanout = 3.15, max_fanout = 16 # # # # # INPUT(1) #... primary input INPUT(13) #... primary input INPUT(20) #... primary input INPUT(33) #... primary input INPUT(41) #... primary input INPUT(45) #... primary input INPUT(50) #... primary input INPUT(58) #... primary input INPUT(68) #... primary input INPUT(77) #... primary input INPUT(87) #... primary input INPUT(97) #... primary input INPUT(107) #... primary input INPUT(116) #... primary input INPUT(124) #... primary input INPUT(125) #... primary input INPUT(128) #... primary input INPUT(132) #... primary input INPUT(137) #... primary input INPUT(143) #... primary input INPUT(150) #... primary input INPUT(159) #... primary input INPUT(169) #... primary input INPUT(179) #... primary input INPUT(190) #... primary input INPUT(200) #... primary input INPUT(213) #... primary input INPUT(222) #... primary input INPUT(223) #... primary input INPUT(226) #... primary input INPUT(232) #... primary input INPUT(238) #... primary input INPUT(244) #... primary input INPUT(250) #... primary input INPUT(257) #... primary input INPUT(264) #... primary input INPUT(270) #... primary input INPUT(274) #... primary input INPUT(283) #... primary input INPUT(294) #... primary input INPUT(303) #... primary input INPUT(311) #... primary input INPUT(317) #... primary input INPUT(322) #... primary input INPUT(326) #... primary input INPUT(329) #... primary input INPUT(330) #... primary input INPUT(343) #... primary input INPUT(1698) #... primary input INPUT(2897) #... primary input # # OUTPUT(353) #... primary output OUTPUT(355) #... primary output OUTPUT(361) #... primary output OUTPUT(358) #... primary output OUTPUT(351) #... primary output OUTPUT(372) #... primary output OUTPUT(369) #... primary output OUTPUT(399) #... primary output OUTPUT(364) #... primary output OUTPUT(396) #... primary output OUTPUT(384) #... primary output OUTPUT(367) #... primary output OUTPUT(387) #... primary output OUTPUT(393) #... primary output OUTPUT(390) #... primary output OUTPUT(378) #... primary output OUTPUT(375) #... primary output OUTPUT(381) #... primary output OUTPUT(407) #... primary output OUTPUT(409) #... primary output OUTPUT(405) #... primary output OUTPUT(402) #... primary output # # # Output Type Inputs... # ------ ---- --------- 432 = buff( 50) 442 = not( 50) 447 = buff( 58) 456 = not( 58) 460 = buff( 68) 463 = not( 68) 467 = buff( 68) 476 = buff( 77) 479 = not( 77) 483 = buff( 77) 492 = buff( 87) 501 = not( 87) 504 = buff( 97) 513 = not( 97) 517 = buff( 107) 526 = not( 107) 530 = buff( 116) 540 = not( 116) 587 = or( 257, 264) 704 = not( 1) 707 = buff( 1) 714 = not( 1) 717 = buff( 13) 724 = not( 13) 731 = and( 13, 20) 732 = not( 20) 736 = buff( 20) 741 = not( 20) 758 = not( 33) 776 = buff( 33) 780 = not( 33) 788 = and( 33, 41) 791 = not( 41) 798 = or( 41, 45) 799 = buff( 45) 802 = not( 45) 826 = not( 50) 828 = buff( 58) 831 = not( 58) 833 = buff( 68) 836 = not( 68) 839 = buff( 87) 842 = not( 87) 845 = buff( 97) 848 = not( 97) 851 = not( 107) 890 = buff( 1) 898 = buff( 68) 907 = buff( 107) 1032 = not( 20) 1035 = buff( 190) 1048 = not( 200) 1049 = and( 20, 200) 1050 = nand( 20, 200) 1051 = and( 20, 179) 1540 = not( 20) 1699 = or( 1698, 33) 1826 = nand( 1, 13) 1827 = nand( 1, 20, 33) 1828 = not( 20) 2051 = not( 33) 2478 = buff( 179) 2865 = not( 213) 2868 = buff( 343) 2931 = buff( 226) 2934 = buff( 232) 2939 = buff( 238) 2942 = buff( 244) 2947 = buff( 250) 2950 = buff( 257) 2957 = buff( 264) 2960 = buff( 270) 3007 = buff( 50) 3079 = buff( 58) 3087 = buff( 58) 3095 = buff( 97) 3103 = buff( 97) 3419 = buff( 330) 588 = and( 250, 587) 759 = or( 758, 20) 1541 = or( 1540, 169) 1772 = not( 731) 1829 = or( 1828, 1) 1834 = and( 1826, 1827) 2052 = or( 2051, 1) 625 = and( 826, 831, 836) 545 = nand( 226, 432) 546 = nand( 232, 447) 547 = nand( 238, 467) 548 = nand( 244, 483) 549 = nand( 250, 492) 550 = nand( 257, 504) 551 = nand( 264, 517) 552 = nand( 270, 530) 2937 = not( 2931) 2938 = not( 2934) 2945 = not( 2939) 2946 = not( 2942) 621 = nand( 456, 463) 626 = nand( 513, 526) 635 = nand( 460, 476) 636 = buff( 442) 3085 = not( 3079) 3101 = not( 3095) 657 = buff( 802) 675 = buff( 802) 721 = buff( 717) 784 = buff( 780) 794 = buff( 791) 807 = and( 714, 798) 816 = and( 714, 799, 791) 823 = and( 704, 799) 860 = and( 707, 724, 736) 861 = nand( 707, 724, 736) 864 = nand( 707, 724) 893 = buff( 890) 896 = nand( 717, 732, 45) 897 = nand( 826, 831, 836) 3093 = not( 3087) 905 = and( 842, 848, 851) 906 = nand( 842, 848, 851) 3109 = not( 3103) 973 = not( 741) 980 = not( 741) 987 = not( 741) 994 = not( 741) 1001 = not( 741) 1008 = not( 741) 1015 = not( 741) 1022 = not( 741) 1038 = or( 1032, 1035) 1043 = nor( 1032, 1035) 1054 = buff( 1051) 1057 = not( 1051) 1512 = buff( 776) 1681 = buff( 780) 1717 = not( 1699) 1724 = not( 1699) 1731 = not( 1699) 1738 = not( 1699) 1745 = not( 1699) 1752 = not( 1699) 1759 = not( 1699) 1766 = not( 1699) 1773 = or( 1, 1772) 1790 = not( 788) 1808 = not( 788) 2278 = and( 704, 717, 732) 2481 = not( 2478) 3425 = not( 3419) 2871 = or( 2865, 2868) 2874 = nor( 2865, 2868) 2953 = not( 2947) 2954 = not( 2950) 2963 = not( 2957) 2964 = not( 2960) 3010 = buff( 456) 3013 = not( 3007) 3017 = buff( 463) 3020 = buff( 479) 3027 = buff( 501) 3030 = buff( 513) 3037 = buff( 526) 3040 = buff( 540) 3082 = buff( 898) 3090 = buff( 898) 3098 = buff( 907) 3106 = buff( 907) 352 = nand( 479, 625) 553 = and( 545, 546, 547, 548) 554 = and( 549, 550, 551, 552) 555 = nand( 2934, 2937) 556 = nand( 2931, 2938) 560 = nand( 2942, 2945) 561 = nand( 2939, 2946) 650 = and( 432, 621) 956 = and( 890, 896) 974 = not( 759) 975 = and( 741, 759) 976 = and( 897, 973) 981 = not( 759) 982 = and( 741, 759) 988 = not( 759) 989 = and( 741, 759) 990 = and( 836, 987) 995 = not( 759) 996 = and( 741, 759) 997 = and( 77, 994) 1002 = not( 759) 1003 = and( 741, 759) 1004 = and( 906, 1001) 1009 = not( 759) 1010 = and( 741, 759) 1016 = not( 759) 1017 = and( 741, 759) 1018 = and( 851, 1015) 1023 = not( 759) 1024 = and( 741, 759) 1025 = and( 116, 1022) 1720 = and( 222, 1717) 1727 = and( 223, 1724) 1734 = and( 226, 1731) 1741 = and( 232, 1738) 1748 = and( 238, 1745) 1755 = and( 244, 1752) 1762 = and( 250, 1759) 1769 = and( 257, 1766) 1791 = and( 1, 13, 1790) 1809 = and( 1, 13, 1808) 1851 = not( 1834) 1901 = not( 1834) 1952 = not( 1834) 2002 = not( 1834) 2057 = not( 1834) 2109 = not( 1834) 2162 = not( 1834) 2214 = not( 1834) 2955 = nand( 2950, 2953) 2956 = nand( 2947, 2954) 2965 = nand( 2960, 2963) 2966 = nand( 2957, 2964) 353 = not( 352) 354 = and( 87, 626) 557 = nand( 555, 556) 562 = nand( 560, 561) 586 = nand( 553, 554) 630 = and( 540, 905) 634 = nand( 540, 905) 639 = not( 636) 642 = nand( 3082, 3085) 3086 = not( 3082) 644 = and( 460, 636) 646 = nand( 3098, 3101) 3102 = not( 3098) 654 = nand( 87, 626) 660 = not( 657) 678 = not( 675) 804 = nand( 860, 776) 806 = nand( 860, 780) 855 = nand( 707, 721, 736) 867 = nand( 707, 724, 736, 794) 903 = nand( 3090, 3093) 3094 = not( 3090) 912 = nand( 3106, 3109) 3110 = not( 3106) 915 = not( 861) 927 = not( 893) 941 = not( 864) 977 = and( 828, 974) 978 = and( 150, 975) 984 = and( 833, 981) 985 = and( 159, 982) 991 = and( 77, 988) 992 = and( 50, 989) 998 = and( 839, 995) 999 = and( 828, 996) 1005 = and( 845, 1002) 1006 = and( 833, 1003) 1012 = and( 107, 1009) 1013 = and( 77, 1010) 1019 = and( 116, 1016) 1020 = and( 839, 1017) 1026 = and( 283, 1023) 1027 = and( 845, 1024) 1060 = and( 200, 1054) 1063 = and( 1048, 1054) 1066 = and( 1049, 1057) 1069 = and( 1050, 1057) 1527 = nand( 784, 794) 1530 = nand( 776, 794) 1542 = nand( 707, 721, 1541) 1563 = nand( 724, 732, 784) 1572 = nand( 724, 784) 1581 = not( 1512) 1585 = not( 1512) 1589 = not( 1512) 1593 = not( 1512) 1597 = not( 1512) 1601 = not( 1512) 1605 = not( 1512) 1716 = not( 1681) 1718 = and( 1681, 1699) 1723 = not( 1681) 1725 = and( 1681, 1699) 1730 = not( 1681) 1732 = and( 1681, 1699) 1737 = not( 1681) 1739 = and( 1681, 1699) 1744 = not( 1681) 1746 = and( 1681, 1699) 1751 = not( 1681) 1753 = and( 1681, 1699) 1758 = not( 1681) 1760 = and( 1681, 1699) 1765 = not( 1681) 1767 = and( 1681, 1699) 1852 = and( 1834, 1773) 1856 = nor( 50, 1773) 1870 = not( 807) 1902 = and( 1834, 1773) 1906 = nor( 58, 1773) 1920 = not( 807) 1953 = and( 1834, 1773) 1957 = nor( 68, 1773) 1971 = not( 807) 2003 = and( 1834, 1773) 2007 = nor( 77, 1773) 2021 = not( 807) 2058 = and( 1834, 1773) 2062 = nor( 87, 1773) 2076 = not( 823) 2110 = and( 1834, 1773) 2114 = nor( 97, 1773) 2128 = not( 816) 2163 = and( 1834, 1773) 2167 = nor( 107, 1773) 2181 = not( 816) 2215 = and( 1834, 1773) 2219 = nor( 116, 1773) 2233 = not( 816) 2285 = and( 2278, 213) 2288 = nand( 2278, 213) 2289 = and( 2278, 213, 343) 2293 = nand( 2278, 213, 343) 2298 = and( 2278, 213, 343) 2302 = nand( 2278, 213, 343) 2877 = buff( 2874) 2983 = nand( 2955, 2956) 2986 = nand( 2965, 2966) 3014 = not( 3010) 3015 = nand( 3010, 3013) 3023 = not( 3017) 3024 = not( 3020) 3033 = not( 3027) 3034 = not( 3030) 3043 = not( 3037) 3044 = not( 3040) 355 = not( 354) 643 = nand( 3079, 3086) 647 = nand( 3095, 3102) 680 = and( 650, 675) 904 = nand( 3087, 3094) 913 = nand( 3103, 3110) 920 = and( 588, 915) 979 = or( 976, 977, 978) 993 = or( 990, 991, 992) 1000 = or( 997, 998, 999) 1007 = or( 1004, 1005, 1006) 1021 = or( 1018, 1019, 1020) 1028 = or( 1025, 1026, 1027) 1719 = and( 77, 1716) 1721 = and( 223, 1718) 1726 = and( 87, 1723) 1728 = and( 226, 1725) 1733 = and( 97, 1730) 1735 = and( 232, 1732) 1740 = and( 107, 1737) 1742 = and( 238, 1739) 1747 = and( 116, 1744) 1749 = and( 244, 1746) 1754 = and( 283, 1751) 1756 = and( 250, 1753) 1761 = and( 294, 1758) 1763 = and( 257, 1760) 1768 = and( 303, 1765) 1770 = and( 264, 1767) 1794 = buff( 1791) 1799 = not( 1791) 1812 = buff( 1809) 1817 = not( 1809) 1859 = and( 50, 1829, 1852) 1909 = and( 58, 1829, 1902) 1960 = and( 68, 1829, 1953) 2010 = and( 77, 1829, 2003) 2065 = and( 87, 2052, 2058) 2117 = and( 97, 2052, 2110) 2170 = and( 107, 2052, 2163) 2222 = and( 116, 2052, 2215) 2678 = not( 956) 2697 = not( 956) 2716 = not( 956) 2733 = not( 956) 2751 = not( 956) 2768 = not( 956) 2785 = not( 956) 2802 = not( 956) 3016 = nand( 3007, 3014) 3025 = nand( 3020, 3023) 3026 = nand( 3017, 3024) 3035 = nand( 3030, 3033) 3036 = nand( 3027, 3034) 3045 = nand( 3040, 3043) 3046 = nand( 3037, 3044) 2989 = not( 2983) 2990 = not( 2986) 610 = not( 804) 613 = and( 804, 806) 616 = not( 806) 640 = nand( 642, 643) 648 = nand( 646, 647) 655 = and( 630, 635, 442, 58) 665 = not( 804) 668 = and( 804, 806) 671 = not( 806) 683 = not( 804) 685 = not( 806) 688 = and( 804, 806) 694 = not( 804) 696 = not( 806) 699 = and( 804, 806) 870 = buff( 867) 887 = buff( 867) 901 = nand( 903, 904) 910 = nand( 912, 913) 914 = not( 855) 916 = and( 855, 861) 942 = not( 855) 943 = and( 864, 855) 1072 = nand( 1043, 1069) 1084 = nand( 1043, 1066) 1096 = nand( 1038, 1069) 1108 = nand( 1038, 1066) 1120 = nand( 1043, 1063) 1132 = nand( 1043, 1060) 1144 = nand( 1038, 1063) 1156 = nand( 1038, 1060) 1533 = not( 1527) 1534 = not( 1530) 1535 = and( 1527, 1530) 1545 = buff( 1542) 1554 = buff( 1542) 1610 = not( 1572) 1619 = not( 1572) 1628 = not( 1572) 1637 = not( 1572) 1646 = not( 1563) 1655 = not( 1563) 1664 = not( 1563) 1673 = not( 1563) 1722 = or( 1719, 1720, 1721) 1729 = or( 1726, 1727, 1728) 1736 = or( 1733, 1734, 1735) 1743 = or( 1740, 1741, 1742) 1750 = or( 1747, 1748, 1749) 1757 = or( 1754, 1755, 1756) 1764 = or( 1761, 1762, 1763) 1771 = or( 1768, 1769, 1770) 1853 = and( 979, 1851) 1954 = and( 993, 1952) 2004 = and( 1000, 2002) 2059 = and( 1007, 2057) 2164 = and( 1021, 2162) 2216 = and( 1028, 2214) 2485 = buff( 2293) 2900 = and( 2877, 2897) 2903 = nand( 2877, 2897) 2967 = buff( 557) 2970 = buff( 562) 2975 = buff( 557) 2978 = buff( 562) 3047 = nand( 3015, 3016) 3050 = nand( 3025, 3026) 3055 = nand( 3035, 3036) 3058 = nand( 3045, 3046) 574 = nand( 2986, 2989) 575 = nand( 2983, 2990) 617 = and( 501, 613) 641 = and( 640, 476, 639) 649 = and( 530, 648) 662 = and( 655, 657) 672 = and( 513, 668) 690 = and( 654, 685) 691 = and( 540, 688) 701 = and( 634, 696) 702 = and( 526, 699) 902 = not( 901) 911 = not( 910) 917 = and( 650, 914) 923 = and( 586, 916) 1538 = and( 442, 1535) 1871 = and( 1817, 226, 1870) 1872 = and( 1817, 274, 807) 1873 = and( 1812, 1722) 1921 = and( 1817, 232, 1920) 1922 = and( 1817, 274, 807) 1923 = and( 1812, 1729) 1972 = and( 1817, 238, 1971) 1973 = and( 1817, 274, 807) 1974 = and( 1812, 1736) 2022 = and( 1817, 244, 2021) 2023 = and( 1817, 274, 807) 2024 = and( 1812, 1743) 2077 = and( 1799, 250, 2076) 2078 = and( 1799, 274, 823) 2079 = and( 1794, 1750) 2129 = and( 1799, 257, 2128) 2130 = and( 1799, 274, 816) 2131 = and( 1794, 1757) 2182 = and( 1799, 264, 2181) 2183 = and( 1799, 274, 816) 2184 = and( 1794, 1764) 2234 = and( 1799, 270, 2233) 2235 = and( 1799, 274, 816) 2236 = and( 1794, 1771) 2973 = not( 2967) 2974 = not( 2970) 2981 = not( 2975) 2982 = not( 2978) 576 = nand( 574, 575) 3053 = not( 3047) 3054 = not( 3050) 3061 = not( 3055) 3062 = not( 3058) 645 = or( 641, 644) 926 = not( 887) 928 = and( 887, 893) 947 = and( 649, 942) 983 = and( 902, 980) 1011 = and( 911, 1008) 1075 = buff( 1072) 1087 = buff( 1084) 1099 = buff( 1096) 1111 = buff( 1108) 1123 = buff( 1120) 1135 = buff( 1132) 1147 = buff( 1144) 1159 = buff( 1156) 1168 = buff( 1072) 1177 = buff( 1084) 1186 = buff( 1096) 1195 = buff( 1108) 1204 = buff( 1120) 1213 = buff( 1132) 1222 = buff( 1144) 1231 = buff( 1156) 1609 = not( 1545) 1611 = and( 1545, 1572) 1618 = not( 1545) 1620 = and( 1545, 1572) 1627 = not( 1545) 1629 = and( 1545, 1572) 1636 = not( 1545) 1638 = and( 1545, 1572) 1645 = not( 1554) 1647 = and( 1554, 1563) 1654 = not( 1554) 1656 = and( 1554, 1563) 1663 = not( 1554) 1665 = and( 1554, 1563) 1672 = not( 1554) 1674 = and( 1554, 1563) 1862 = or( 1853, 1856, 1859) 1866 = nor( 1853, 1856, 1859) 1874 = or( 1871, 1872, 1873) 1924 = or( 1921, 1922, 1923) 1963 = or( 1954, 1957, 1960) 1967 = nor( 1954, 1957, 1960) 1975 = or( 1972, 1973, 1974) 2013 = or( 2004, 2007, 2010) 2017 = nor( 2004, 2007, 2010) 2025 = or( 2022, 2023, 2024) 2068 = or( 2059, 2062, 2065) 2072 = nor( 2059, 2062, 2065) 2080 = or( 2077, 2078, 2079) 2132 = or( 2129, 2130, 2131) 2173 = or( 2164, 2167, 2170) 2177 = nor( 2164, 2167, 2170) 2185 = or( 2182, 2183, 2184) 2225 = or( 2216, 2219, 2222) 2229 = nor( 2216, 2219, 2222) 2237 = or( 2234, 2235, 2236) 2488 = not( 2485) 2679 = not( 870) 2680 = and( 956, 870) 2698 = not( 870) 2699 = and( 956, 870) 2717 = not( 870) 2718 = and( 956, 870) 2734 = not( 870) 2735 = and( 956, 870) 2752 = not( 870) 2753 = and( 956, 870) 2769 = not( 870) 2770 = and( 956, 870) 2786 = not( 870) 2787 = and( 956, 870) 2803 = not( 870) 2804 = and( 956, 870) 359 = or( 917, 920, 923) 1029 = nor( 917, 920, 923) 565 = nand( 2970, 2973) 566 = nand( 2967, 2974) 569 = nand( 2978, 2981) 570 = nand( 2975, 2982) 589 = nand( 3050, 3053) 590 = nand( 3047, 3054) 595 = nand( 3058, 3061) 596 = nand( 3055, 3062) 929 = and( 650, 926) 938 = and( 630, 928) 944 = and( 645, 941) 986 = or( 983, 984, 985) 1014 = or( 1011, 1012, 1013) 1616 = and( 442, 1611) 1625 = and( 456, 1620) 1634 = and( 463, 1629) 1643 = and( 479, 1638) 360 = not( 1029) 567 = nand( 565, 566) 571 = nand( 569, 570) 579 = buff( 576) 591 = nand( 589, 590) 597 = nand( 595, 596) 614 = and( 576, 610) 1240 = not( 1075) 1241 = not( 1087) 1242 = not( 1099) 1243 = not( 1111) 1244 = not( 1123) 1245 = not( 1135) 1246 = not( 1147) 1247 = not( 1159) 1257 = not( 1075) 1258 = not( 1087) 1259 = not( 1099) 1260 = not( 1111) 1261 = not( 1123) 1262 = not( 1135) 1263 = not( 1147) 1264 = not( 1159) 1274 = not( 1075) 1275 = not( 1087) 1276 = not( 1099) 1277 = not( 1111) 1278 = not( 1123) 1279 = not( 1135) 1280 = not( 1147) 1281 = not( 1159) 1291 = not( 1075) 1292 = not( 1087) 1293 = not( 1099) 1294 = not( 1111) 1295 = not( 1123) 1296 = not( 1135) 1297 = not( 1147) 1298 = not( 1159) 1308 = not( 1075) 1309 = not( 1087) 1310 = not( 1099) 1311 = not( 1111) 1312 = not( 1123) 1313 = not( 1135) 1314 = not( 1147) 1315 = not( 1159) 1325 = not( 1075) 1326 = not( 1087) 1327 = not( 1099) 1328 = not( 1111) 1329 = not( 1123) 1330 = not( 1135) 1331 = not( 1147) 1332 = not( 1159) 1342 = not( 1075) 1343 = not( 1087) 1344 = not( 1099) 1345 = not( 1111) 1346 = not( 1123) 1347 = not( 1135) 1348 = not( 1147) 1349 = not( 1159) 1359 = not( 1075) 1360 = not( 1087) 1361 = not( 1099) 1362 = not( 1111) 1363 = not( 1123) 1364 = not( 1135) 1365 = not( 1147) 1366 = not( 1159) 1376 = not( 1168) 1377 = not( 1177) 1378 = not( 1186) 1379 = not( 1195) 1380 = not( 1204) 1381 = not( 1213) 1382 = not( 1222) 1383 = not( 1231) 1393 = not( 1168) 1394 = not( 1177) 1395 = not( 1186) 1396 = not( 1195) 1397 = not( 1204) 1398 = not( 1213) 1399 = not( 1222) 1400 = not( 1231) 1410 = not( 1168) 1411 = not( 1177) 1412 = not( 1186) 1413 = not( 1195) 1414 = not( 1204) 1415 = not( 1213) 1416 = not( 1222) 1417 = not( 1231) 1427 = not( 1168) 1428 = not( 1177) 1429 = not( 1186) 1430 = not( 1195) 1431 = not( 1204) 1432 = not( 1213) 1433 = not( 1222) 1434 = not( 1231) 1444 = not( 1168) 1445 = not( 1177) 1446 = not( 1186) 1447 = not( 1195) 1448 = not( 1204) 1449 = not( 1213) 1450 = not( 1222) 1451 = not( 1231) 1461 = not( 1168) 1462 = not( 1177) 1463 = not( 1186) 1464 = not( 1195) 1465 = not( 1204) 1466 = not( 1213) 1467 = not( 1222) 1468 = not( 1231) 1478 = not( 1168) 1479 = not( 1177) 1480 = not( 1186) 1481 = not( 1195) 1482 = not( 1204) 1483 = not( 1213) 1484 = not( 1222) 1485 = not( 1231) 1495 = not( 1168) 1496 = not( 1177) 1497 = not( 1186) 1498 = not( 1195) 1499 = not( 1204) 1500 = not( 1213) 1501 = not( 1222) 1502 = not( 1231) 1877 = buff( 1874) 1880 = not( 1874) 1891 = not( 1866) 1903 = and( 986, 1901) 1927 = buff( 1924) 1930 = not( 1924) 1978 = buff( 1975) 1981 = not( 1975) 1992 = not( 1967) 2028 = buff( 2025) 2031 = not( 2025) 2042 = not( 2017) 2085 = buff( 2080) 2088 = not( 2080) 2099 = not( 2072) 2111 = and( 1014, 2109) 2137 = buff( 2132) 2140 = not( 2132) 2190 = buff( 2185) 2193 = not( 2185) 2204 = not( 2177) 2242 = buff( 2237) 2245 = not( 2237) 2256 = not( 2229) 2320 = and( 2285, 1862) 2341 = and( 2289, 1963) 2354 = and( 2289, 2013) 2367 = and( 2289, 2068) 2383 = and( 2298, 2173) 2391 = and( 2298, 2225) 2474 = not( 2080) 2475 = not( 2132) 2476 = not( 2185) 2477 = not( 2237) 2482 = and( 2080, 2132, 2185, 2237, 2481) 361 = nand( 359, 360) 568 = not( 567) 618 = or( 614, 616, 617) 1248 = and( 124, 1240) 1249 = and( 159, 1241) 1250 = and( 150, 1242) 1251 = and( 143, 1243) 1252 = and( 137, 1244) 1253 = and( 132, 1245) 1254 = and( 128, 1246) 1255 = and( 125, 1247) 1265 = and( 125, 1257) 1266 = and( 432, 1258) 1267 = and( 159, 1259) 1268 = and( 150, 1260) 1269 = and( 143, 1261) 1270 = and( 137, 1262) 1271 = and( 132, 1263) 1272 = and( 128, 1264) 1282 = and( 128, 1274) 1283 = and( 447, 1275) 1284 = and( 432, 1276) 1285 = and( 159, 1277) 1286 = and( 150, 1278) 1287 = and( 143, 1279) 1288 = and( 137, 1280) 1289 = and( 132, 1281) 1299 = and( 132, 1291) 1300 = and( 467, 1292) 1301 = and( 447, 1293) 1302 = and( 432, 1294) 1303 = and( 159, 1295) 1304 = and( 150, 1296) 1305 = and( 143, 1297) 1306 = and( 137, 1298) 1316 = and( 137, 1308) 1317 = and( 483, 1309) 1318 = and( 467, 1310) 1319 = and( 447, 1311) 1320 = and( 432, 1312) 1321 = and( 159, 1313) 1322 = and( 150, 1314) 1323 = and( 143, 1315) 1333 = and( 143, 1325) 1334 = and( 492, 1326) 1335 = and( 483, 1327) 1336 = and( 467, 1328) 1337 = and( 447, 1329) 1338 = and( 432, 1330) 1339 = and( 159, 1331) 1340 = and( 150, 1332) 1350 = and( 150, 1342) 1351 = and( 504, 1343) 1352 = and( 492, 1344) 1353 = and( 483, 1345) 1354 = and( 467, 1346) 1355 = and( 447, 1347) 1356 = and( 432, 1348) 1357 = and( 159, 1349) 1367 = and( 159, 1359) 1368 = and( 517, 1360) 1369 = and( 504, 1361) 1370 = and( 492, 1362) 1371 = and( 483, 1363) 1372 = and( 467, 1364) 1373 = and( 447, 1365) 1374 = and( 432, 1366) 1384 = and( 283, 1376) 1385 = and( 447, 1377) 1386 = and( 467, 1378) 1387 = and( 483, 1379) 1388 = and( 492, 1380) 1389 = and( 504, 1381) 1390 = and( 517, 1382) 1391 = and( 530, 1383) 1401 = and( 294, 1393) 1402 = and( 467, 1394) 1403 = and( 483, 1395) 1404 = and( 492, 1396) 1405 = and( 504, 1397) 1406 = and( 517, 1398) 1407 = and( 530, 1399) 1408 = and( 283, 1400) 1418 = and( 303, 1410) 1419 = and( 483, 1411) 1420 = and( 492, 1412) 1421 = and( 504, 1413) 1422 = and( 517, 1414) 1423 = and( 530, 1415) 1424 = and( 283, 1416) 1425 = and( 294, 1417) 1435 = and( 311, 1427) 1436 = and( 492, 1428) 1437 = and( 504, 1429) 1438 = and( 517, 1430) 1439 = and( 530, 1431) 1440 = and( 283, 1432) 1441 = and( 294, 1433) 1442 = and( 303, 1434) 1452 = and( 317, 1444) 1453 = and( 504, 1445) 1454 = and( 517, 1446) 1455 = and( 530, 1447) 1456 = and( 283, 1448) 1457 = and( 294, 1449) 1458 = and( 303, 1450) 1459 = and( 311, 1451) 1469 = and( 322, 1461) 1470 = and( 517, 1462) 1471 = and( 530, 1463) 1472 = and( 283, 1464) 1473 = and( 294, 1465) 1474 = and( 303, 1466) 1475 = and( 311, 1467) 1476 = and( 317, 1468) 1486 = and( 326, 1478) 1487 = and( 530, 1479) 1488 = and( 283, 1480) 1489 = and( 294, 1481) 1490 = and( 303, 1482) 1491 = and( 311, 1483) 1492 = and( 317, 1484) 1493 = and( 322, 1485) 1503 = and( 329, 1495) 1504 = and( 283, 1496) 1505 = and( 294, 1497) 1506 = and( 303, 1498) 1507 = and( 311, 1499) 1508 = and( 317, 1500) 1509 = and( 322, 1501) 1510 = and( 326, 1502) 2483 = and( 2474, 2475, 2476, 2477, 2478) 600 = buff( 597) 661 = and( 568, 660) 669 = and( 597, 665) 679 = and( 591, 678) 1256 = nor( 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255) 1273 = nor( 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272) 1290 = nor( 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289) 1307 = nor( 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306) 1324 = nor( 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323) 1341 = nor( 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340) 1358 = nor( 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357) 1375 = nor( 1367, 1368, 1369, 1370, 1371, 1372, 1373, 1374) 1392 = nor( 1384, 1385, 1386, 1387, 1388, 1389, 1390, 1391) 1409 = nor( 1401, 1402, 1403, 1404, 1405, 1406, 1407, 1408) 1426 = nor( 1418, 1419, 1420, 1421, 1422, 1423, 1424, 1425) 1443 = nor( 1435, 1436, 1437, 1438, 1439, 1440, 1441, 1442) 1460 = nor( 1452, 1453, 1454, 1455, 1456, 1457, 1458, 1459) 1477 = nor( 1469, 1470, 1471, 1472, 1473, 1474, 1475, 1476) 1494 = nor( 1486, 1487, 1488, 1489, 1490, 1491, 1492, 1493) 1511 = nor( 1503, 1504, 1505, 1506, 1507, 1508, 1509, 1510) 1652 = and( 618, 1647) 1883 = and( 169, 1862, 1877) 1886 = and( 179, 1862, 1880) 1889 = and( 190, 1866, 1880) 1890 = and( 200, 1866, 1877) 1912 = or( 1903, 1906, 1909) 1916 = nor( 1903, 1906, 1909) 1984 = and( 169, 1963, 1978) 1987 = and( 179, 1963, 1981) 1990 = and( 190, 1967, 1981) 1991 = and( 200, 1967, 1978) 2034 = and( 169, 2013, 2028) 2037 = and( 179, 2013, 2031) 2040 = and( 190, 2017, 2031) 2041 = and( 200, 2017, 2028) 2091 = and( 169, 2068, 2085) 2094 = and( 179, 2068, 2088) 2097 = and( 190, 2072, 2088) 2098 = and( 200, 2072, 2085) 2120 = or( 2111, 2114, 2117) 2124 = nor( 2111, 2114, 2117) 2196 = and( 169, 2173, 2190) 2199 = and( 179, 2173, 2193) 2202 = and( 190, 2177, 2193) 2203 = and( 200, 2177, 2190) 2248 = and( 169, 2225, 2242) 2251 = and( 179, 2225, 2245) 2254 = and( 190, 2229, 2245) 2255 = and( 200, 2229, 2242) 2484 = or( 2482, 2483) 2991 = buff( 571) 2994 = buff( 579) 2999 = buff( 571) 3002 = buff( 579) 3063 = buff( 591) 3071 = buff( 591) 3124 = buff( 2320) 3134 = buff( 2320) 3158 = buff( 2341) 3166 = buff( 2341) 3174 = buff( 2354) 3182 = buff( 2354) 3190 = buff( 2367) 3200 = buff( 2367) 3224 = buff( 2383) 3232 = buff( 2383) 3240 = buff( 2391) 3248 = buff( 2391) 663 = nor( 661, 662) 673 = or( 669, 671, 672) 681 = nor( 679, 680) 1536 = and( 1256, 1533) 1537 = and( 1392, 1534) 1582 = and( 1273, 1581) 1583 = and( 1409, 1512) 1586 = and( 1290, 1585) 1587 = and( 1426, 1512) 1590 = and( 1307, 1589) 1591 = and( 1443, 1512) 1594 = and( 1324, 1593) 1595 = and( 1460, 1512) 1598 = and( 1341, 1597) 1599 = and( 1477, 1512) 1602 = and( 1358, 1601) 1603 = and( 1494, 1512) 1606 = and( 1375, 1605) 1607 = and( 1511, 1512) 1894 = or( 1889, 1890, 1891) 1997 = or( 1990, 1991, 1992) 2047 = or( 2040, 2041, 2042) 2102 = or( 2097, 2098, 2099) 2209 = or( 2202, 2203, 2204) 2261 = or( 2254, 2255, 2256) 2489 = and( 2484, 2488) 3005 = not( 2999) 3006 = not( 3002) 3077 = not( 3071) 3069 = not( 3063) 2997 = not( 2991) 2998 = not( 2994) 689 = and( 681, 683) 700 = and( 663, 694) 1539 = or( 1536, 1537, 1538) 1584 = or( 1582, 1583) 1588 = or( 1586, 1587) 1592 = or( 1590, 1591) 1596 = or( 1594, 1595) 1600 = or( 1598, 1599) 1604 = or( 1602, 1603) 1608 = or( 1606, 1607) 1661 = and( 673, 1656) 1892 = or( 1883, 1886) 1893 = nor( 1883, 1886) 1933 = and( 169, 1912, 1927) 1936 = and( 179, 1912, 1930) 1939 = and( 190, 1916, 1930) 1940 = and( 200, 1916, 1927) 1941 = not( 1916) 1993 = or( 1984, 1987) 1996 = nor( 1984, 1987) 2043 = or( 2034, 2037) 2046 = nor( 2034, 2037) 2100 = or( 2091, 2094) 2101 = nor( 2091, 2094) 2143 = and( 169, 2120, 2137) 2146 = and( 179, 2120, 2140) 2149 = and( 190, 2124, 2140) 2150 = and( 200, 2124, 2137) 2151 = not( 2124) 2205 = or( 2196, 2199) 2208 = nor( 2196, 2199) 2257 = or( 2248, 2251) 2260 = nor( 2248, 2251) 3138 = not( 3134) 2328 = and( 2285, 1912) 3162 = not( 3158) 3170 = not( 3166) 3178 = not( 3174) 3186 = not( 3182) 3204 = not( 3200) 2375 = and( 2298, 2120) 3236 = not( 3232) 3244 = not( 3240) 3252 = not( 3248) 3228 = not( 3224) 3066 = buff( 600) 3074 = buff( 600) 3128 = not( 3124) 3194 = not( 3190) 619 = nand( 2994, 2997) 620 = nand( 2991, 2998) 582 = nand( 3002, 3005) 583 = nand( 2999, 3006) 692 = or( 689, 690, 691) 703 = or( 700, 701, 702) 1612 = and( 1539, 1609) 1621 = and( 1584, 1618) 1630 = and( 1588, 1627) 1639 = and( 1592, 1636) 1648 = and( 1596, 1645) 1657 = and( 1600, 1654) 1666 = and( 1604, 1663) 1675 = and( 1608, 1672) 1895 = and( 1893, 1894) 1946 = or( 1939, 1940, 1941) 1998 = and( 1996, 1997) 2048 = and( 2046, 2047) 2103 = and( 2101, 2102) 2156 = or( 2149, 2150, 2151) 2210 = and( 2208, 2209) 2262 = and( 2260, 2261) 2271 = not( 1892) 2311 = not( 2100) 356 = nand( 619, 620) 357 = nand( 582, 583) 603 = nand( 3074, 3077) 3078 = not( 3074) 606 = nand( 3066, 3069) 3070 = not( 3066) 1670 = and( 703, 1665) 1679 = and( 692, 1674) 1942 = or( 1933, 1936) 1945 = nor( 1933, 1936) 2152 = or( 2143, 2146) 2155 = nor( 2143, 2146) 2445 = and( 1993, 2293) 2448 = and( 2043, 2293) 2455 = and( 2205, 2302) 2458 = and( 2257, 2302) 3142 = buff( 2328) 3150 = buff( 2328) 3208 = buff( 2375) 3216 = buff( 2375) 358 = nand( 356, 357) 604 = nand( 3071, 3078) 607 = nand( 3063, 3070) 1947 = and( 1945, 1946) 2157 = and( 2155, 2156) 2317 = buff( 1895) 2338 = buff( 1998) 2351 = buff( 2048) 2364 = buff( 2103) 2380 = buff( 2210) 2388 = buff( 2262) 605 = nand( 603, 604) 608 = nand( 606, 607) 2272 = nand( 1895, 1942) 2312 = nand( 2103, 2152) 3146 = not( 3142) 3154 = not( 3150) 3220 = not( 3216) 3212 = not( 3208) 2444 = and( 1942, 2288) 2451 = buff( 2448) 2454 = and( 2152, 2293) 2461 = buff( 2458) 2530 = not( 2445) 3323 = buff( 2458) 349 = not( 605) 350 = not( 608) 2265 = and( 1895, 1947, 1998, 2048) 2273 = nand( 1895, 1947, 1993) 2274 = nand( 2043, 1947, 1998, 1895) 2309 = and( 2103, 2157, 2210, 2262) 2313 = nand( 2103, 2157, 2205) 2314 = nand( 2257, 2157, 2210, 2103) 2325 = buff( 1947) 2372 = buff( 2157) 2523 = not( 2444) 2533 = not( 2454) 3121 = buff( 2317) 3131 = buff( 2317) 3155 = buff( 2338) 3163 = buff( 2338) 3171 = buff( 2351) 3179 = buff( 2351) 3187 = buff( 2364) 3197 = buff( 2364) 3221 = buff( 2380) 3229 = buff( 2380) 3237 = buff( 2388) 3245 = buff( 2388) 351 = nand( 349, 350) 2275 = nand( 2271, 2272, 2273, 2274) 2315 = nand( 2311, 2312, 2313, 2314) 3329 = not( 3323) 372 = and( 2309, 2265) 2324 = nand( 3131, 3138) 2350 = nand( 3163, 3170) 2363 = nand( 3179, 3186) 2371 = nand( 3197, 3204) 2387 = nand( 3229, 3236) 2400 = nand( 3245, 3252) 2268 = buff( 2265) 3137 = not( 3131) 3161 = not( 3155) 2345 = nand( 3155, 3162) 3169 = not( 3163) 3177 = not( 3171) 2358 = nand( 3171, 3178) 3185 = not( 3179) 3203 = not( 3197) 3235 = not( 3229) 3243 = not( 3237) 2395 = nand( 3237, 3244) 3251 = not( 3245) 3227 = not( 3221) 2432 = nand( 3221, 3228) 2490 = and( 2309, 2485) 3127 = not( 3121) 3130 = nand( 3121, 3128) 3139 = buff( 2325) 3147 = buff( 2325) 3193 = not( 3187) 3196 = nand( 3187, 3194) 3205 = buff( 2372) 3213 = buff( 2372) 2307 = nand( 2265, 2315) 2308 = not( 2275) 2323 = nand( 3134, 3137) 2349 = nand( 3166, 3169) 2362 = nand( 3182, 3185) 2370 = nand( 3200, 3203) 2386 = nand( 3232, 3235) 2399 = nand( 3248, 3251) 2344 = nand( 3158, 3161) 2357 = nand( 3174, 3177) 2394 = nand( 3240, 3243) 2431 = nand( 3224, 3227) 2464 = and( 2315, 2302) 2491 = or( 2489, 2490) 3129 = nand( 3124, 3127) 3195 = nand( 3190, 3193) 368 = and( 2307, 2308) 1615 = nand( 2323, 2324) 2337 = nand( 3147, 3154) 1633 = nand( 2349, 2350) 1642 = nand( 2362, 2363) 1651 = nand( 2370, 2371) 2379 = nand( 3213, 3220) 1669 = nand( 2386, 2387) 1678 = nand( 2399, 2400) 3145 = not( 3139) 2332 = nand( 3139, 3146) 3153 = not( 3147) 2346 = nand( 2344, 2345) 2359 = nand( 2357, 2358) 3219 = not( 3213) 2396 = nand( 2394, 2395) 3211 = not( 3205) 2425 = nand( 3205, 3212) 2433 = nand( 2431, 2432) 3272 = nand( 3129, 3130) 3308 = nand( 3195, 3196) 369 = not( 368) 1613 = not( 1615) 2336 = nand( 3150, 3153) 1631 = not( 1633) 1640 = not( 1642) 1649 = not( 1651) 2378 = nand( 3216, 3219) 1667 = not( 1669) 1676 = not( 1678) 2331 = nand( 3142, 3145) 2424 = nand( 3208, 3211) 2467 = buff( 2464) 2495 = buff( 2491) 3295 = buff( 2464) 3374 = and( 330, 2491) 1614 = and( 1613, 1610) 1624 = nand( 2336, 2337) 1632 = and( 1631, 1628) 1641 = and( 1640, 1637) 1650 = and( 1649, 1646) 1660 = nand( 2378, 2379) 1668 = and( 1667, 1664) 1677 = and( 1676, 1673) 2333 = nand( 2331, 2332) 2406 = buff( 2346) 2409 = buff( 2346) 2415 = buff( 2359) 2419 = buff( 2359) 2426 = nand( 2424, 2425) 2439 = buff( 2396) 2518 = and( 2433, 2461) 3276 = not( 3272) 3312 = not( 3308) 2612 = and( 330, 2396) 3326 = buff( 2433) 1617 = nor( 1612, 1614, 1616) 1622 = not( 1624) 1635 = nor( 1630, 1632, 1634) 1644 = nor( 1639, 1641, 1643) 1653 = nor( 1648, 1650, 1652) 1658 = not( 1660) 1671 = nor( 1666, 1668, 1670) 1680 = nor( 1675, 1677, 1679) 2500 = and( 2467, 2268) 2505 = and( 2495, 2268) 2519 = or( 2455, 2518) 3378 = not( 3374) 2642 = not( 2467) 2645 = buff( 2467) 3301 = not( 3295) 1623 = and( 1622, 1619) 1659 = and( 1658, 1655) 2401 = buff( 2333) 2501 = or( 2275, 2500) 2511 = and( 2495, 2419, 2409) 2512 = and( 2495, 2415) 2513 = and( 2439, 2433, 2426) 2514 = and( 2439, 2433) 2517 = and( 2467, 2415) 2531 = nand( 2409, 2451) 2532 = nand( 2409, 2419, 2467) 2534 = nand( 2426, 2455) 2535 = nand( 2426, 2433, 2461) 2607 = nand( 3326, 3329) 3330 = not( 3326) 2643 = and( 330, 2491, 2642) 2687 = and( 1617, 2680) 2725 = and( 1635, 2718) 2742 = and( 1644, 2735) 2760 = and( 1653, 2753) 2794 = and( 1671, 2787) 2811 = and( 1680, 2804) 3280 = buff( 2333) 3290 = buff( 2409) 3298 = buff( 2415) 3316 = buff( 2426) 3406 = buff( 2612) 3414 = buff( 2612) 3422 = and( 2439, 2439) 1626 = nor( 1621, 1623, 1625) 1662 = nor( 1657, 1659, 1661) 2567 = and( 330, 2512) 2589 = and( 330, 2513) 2608 = nand( 3323, 3330) 2654 = buff( 2519) 3253 = buff( 2505) 3277 = nand( 2530, 2531, 2532) 3287 = or( 2448, 2517) 3305 = nand( 2533, 2534, 2535) 3313 = buff( 2519) 3350 = and( 330, 2511) 932 = or( 2643, 2645) 2508 = and( 2495, 2401, 2409, 2419) 2524 = nand( 2401, 2445) 2525 = nand( 2401, 2406, 2451) 2526 = nand( 2401, 2406, 2419, 2467) 3294 = not( 3290) 2609 = nand( 2607, 2608) 3410 = not( 3406) 3418 = not( 3414) 2624 = nand( 3422, 3425) 3426 = not( 3422) 2629 = buff( 2501) 2647 = nor( 2643, 2645) 2706 = and( 1626, 2699) 2777 = and( 1662, 2770) 3264 = buff( 2501) 3284 = not( 3280) 3302 = not( 3298) 3303 = nand( 3298, 3301) 3320 = not( 3316) 3398 = and( 330, 2514) 2657 = not( 2654) 398 = and( 2519, 2654) 933 = and( 932, 927) 2527 = nand( 2523, 2524, 2525, 2526) 3259 = not( 3253) 3354 = not( 3350) 3293 = not( 3287) 2563 = nand( 3287, 3294) 3311 = not( 3305) 2585 = nand( 3305, 3312) 2625 = nand( 3419, 3426) 3283 = not( 3277) 3286 = nand( 3277, 3284) 3304 = nand( 3295, 3302) 3319 = not( 3313) 3322 = nand( 3313, 3320) 3358 = buff( 2567) 3366 = buff( 2567) 3382 = buff( 2589) 3390 = buff( 2589) 397 = and( 330, 2514, 2657) 2544 = and( 330, 2508) 2562 = nand( 3290, 3293) 2584 = nand( 3308, 3311) 3402 = not( 3398) 2626 = nand( 2624, 2625) 2632 = not( 2629) 2634 = and( 2501, 2629) 2650 = buff( 2647) 3268 = not( 3264) 3256 = buff( 2508) 3285 = nand( 3280, 3283) 3321 = nand( 3316, 3319) 3371 = nand( 3303, 3304) 3403 = buff( 2609) 3411 = buff( 2609) 362 = or( 929, 933, 938) 1030 = nor( 929, 933, 938) 399 = or( 397, 398) 2564 = nand( 2562, 2563) 3362 = not( 3358) 3370 = not( 3366) 2586 = nand( 2584, 2585) 3386 = not( 3382) 3394 = not( 3390) 2633 = and( 330, 2505, 2632) 3261 = buff( 2527) 3269 = buff( 2527) 3347 = nand( 3285, 3286) 3395 = nand( 3321, 3322) 363 = not( 1030) 2536 = nand( 3256, 3259) 3260 = not( 3256) 3377 = not( 3371) 2580 = nand( 3371, 3378) 3409 = not( 3403) 2616 = nand( 3403, 3410) 3417 = not( 3411) 2622 = nand( 3411, 3418) 2635 = nor( 2633, 2634) 2805 = and( 2626, 2802) 2808 = and( 2626, 2803) 3334 = buff( 2544) 3342 = buff( 2544) 3454 = buff( 2650) 364 = and( 362, 363) 2537 = nand( 3253, 3260) 3275 = not( 3269) 2540 = nand( 3269, 3276) 3353 = not( 3347) 2557 = nand( 3347, 3354) 2579 = nand( 3374, 3377) 3401 = not( 3395) 2602 = nand( 3395, 3402) 2615 = nand( 3406, 3409) 2621 = nand( 3414, 3417) 3267 = not( 3261) 3112 = nand( 3261, 3268) 3355 = buff( 2564) 3363 = buff( 2564) 3379 = buff( 2586) 3387 = buff( 2586) 2538 = nand( 2536, 2537) 2539 = nand( 3272, 3275) 3338 = not( 3334) 3346 = not( 3342) 2556 = nand( 3350, 3353) 2581 = nand( 2579, 2580) 2601 = nand( 3398, 3401) 2617 = nand( 2615, 2616) 2623 = nand( 2621, 2622) 2638 = buff( 2635) 3458 = not( 3454) 2814 = or( 2805, 2808, 2811) 2816 = nor( 2805, 2808, 2811) 3111 = nand( 3264, 3267) 2541 = nand( 2539, 2540) 2558 = nand( 2556, 2557) 3361 = not( 3355) 2571 = nand( 3355, 3362) 3369 = not( 3363) 2577 = nand( 3363, 3370) 3385 = not( 3379) 2593 = nand( 3379, 3386) 3393 = not( 3387) 2598 = nand( 3387, 3394) 2603 = nand( 2601, 2602) 3113 = nand( 3111, 3112) 3116 = and( 330, 2538) 3451 = not( 2623) 395 = not( 2816) 2570 = nand( 3358, 3361) 2576 = nand( 3366, 3369) 2592 = nand( 3382, 3385) 2597 = nand( 3390, 3393) 2736 = and( 2581, 2733) 2739 = and( 2581, 2734) 2788 = and( 2617, 2785) 3438 = buff( 2638) 3446 = and( 2617, 2647) 3459 = buff( 2814) 396 = and( 2814, 395) 3119 = not( 3113) 3120 = not( 3116) 2572 = nand( 2570, 2571) 2578 = nand( 2576, 2577) 2594 = nand( 2592, 2593) 2599 = nand( 2597, 2598) 2677 = nand( 3451, 3458) 3457 = not( 3451) 2700 = and( 2558, 2697) 2771 = and( 2603, 2768) 3331 = buff( 2541) 3339 = buff( 2541) 3427 = buff( 2558) 3443 = buff( 2603) 954 = nand( 3116, 3119) 955 = nand( 3113, 3120) 2600 = not( 2599) 3442 = not( 3438) 3450 = not( 3446) 2676 = nand( 3454, 3457) 2745 = or( 2736, 2739, 2742) 2748 = nor( 2736, 2739, 2742) 3465 = not( 3459) 3435 = not( 2578) 950 = nand( 954, 955) 3337 = not( 3331) 2548 = nand( 3331, 3338) 3345 = not( 3339) 2553 = nand( 3339, 3346) 2661 = nor( 2600, 2650) 2662 = and( 2617, 2603, 2594, 2650) 3433 = not( 3427) 3449 = not( 3443) 2672 = nand( 3443, 3450) 2674 = nand( 2676, 2677) 2719 = and( 2572, 2716) 2754 = and( 2594, 2751) 3430 = and( 2572, 2635) 383 = not( 2748) 951 = and( 950, 943) 2547 = nand( 3334, 3337) 2552 = nand( 3342, 3345) 2663 = or( 2661, 2662) 2670 = nand( 3435, 3442) 3441 = not( 3435) 2671 = nand( 3446, 3449) 2675 = not( 2674) 3491 = buff( 2745) 3499 = buff( 2745) 384 = and( 2745, 383) 2549 = nand( 2547, 2548) 2554 = nand( 2552, 2553) 2664 = nand( 3430, 3433) 3434 = not( 3430) 2669 = nand( 3438, 3441) 2673 = nand( 2671, 2672) 2757 = and( 2663, 2752) 2791 = and( 2675, 2786) 365 = or( 944, 947, 951) 1031 = nor( 944, 947, 951) 2555 = not( 2554) 2665 = nand( 3427, 3434) 2667 = nand( 2669, 2670) 2774 = and( 2673, 2769) 3497 = not( 3491) 3505 = not( 3499) 366 = not( 1031) 2658 = nor( 2555, 2638) 2659 = and( 2572, 2558, 2549, 2638) 2666 = nand( 2664, 2665) 2668 = not( 2667) 2681 = and( 2549, 2678) 2763 = or( 2754, 2757, 2760) 2765 = nor( 2754, 2757, 2760) 2797 = or( 2788, 2791, 2794) 2799 = nor( 2788, 2791, 2794) 367 = and( 365, 366) 2660 = or( 2658, 2659) 2703 = and( 2666, 2698) 2722 = and( 2668, 2717) 2780 = or( 2771, 2774, 2777) 2782 = nor( 2771, 2774, 2777) 386 = not( 2765) 392 = not( 2799) 2684 = and( 2660, 2679) 3462 = buff( 2797) 3470 = buff( 2763) 387 = and( 2763, 386) 389 = not( 2782) 393 = and( 2797, 392) 2709 = or( 2700, 2703, 2706) 2713 = nor( 2700, 2703, 2706) 2728 = or( 2719, 2722, 2725) 2730 = nor( 2719, 2722, 2725) 2922 = and( 2816, 2799, 2782, 2765) 3467 = buff( 2780) 390 = and( 2780, 389) 2690 = or( 2681, 2684, 2687) 2694 = nor( 2681, 2684, 2687) 2821 = nand( 3462, 3465) 3466 = not( 3462) 3474 = not( 3470) 378 = and( 2709, 2709) 380 = not( 2730) 2822 = nand( 3459, 3466) 3473 = not( 3467) 2827 = nand( 3467, 3474) 2839 = buff( 2728) 2883 = and( 2709, 2871) 3507 = buff( 2709) 375 = and( 2690, 2690) 381 = and( 2728, 380) 2823 = nand( 2821, 2822) 2826 = nand( 3470, 3473) 2880 = and( 2871, 2690) 2925 = and( 2748, 2730, 2713, 2694) 2928 = and( 2713, 2694, 2874) 3510 = buff( 2690) 2828 = nand( 2826, 2827) 3494 = buff( 2839) 3502 = buff( 2839) 3513 = not( 3507) 3544 = buff( 2883) 3552 = buff( 2883) 406 = and( 2922, 2925) 2929 = and( 2922, 2925) 3475 = buff( 2823) 3483 = buff( 2823) 3514 = not( 3510) 3515 = nand( 3510, 3513) 3541 = buff( 2880) 3549 = buff( 2880) 407 = not( 406) 2930 = nor( 2928, 2929) 2842 = nand( 3494, 3497) 3498 = not( 3494) 2852 = nand( 3502, 3505) 3506 = not( 3502) 3548 = not( 3544) 3556 = not( 3552) 3478 = buff( 2828) 3486 = buff( 2828) 3516 = nand( 3507, 3514) 408 = and( 213, 2930) 3481 = not( 3475) 3489 = not( 3483) 2843 = nand( 3491, 3498) 2853 = nand( 3499, 3506) 3547 = not( 3541) 2887 = nand( 3541, 3548) 2896 = nand( 3549, 3556) 3555 = not( 3549) 3520 = nand( 3515, 3516) 409 = not( 408) 2831 = nand( 3478, 3481) 3482 = not( 3478) 2836 = nand( 3486, 3489) 3490 = not( 3486) 2844 = nand( 2842, 2843) 2848 = nand( 2852, 2853) 2886 = nand( 3544, 3547) 2895 = nand( 3552, 3555) 2832 = nand( 3475, 3482) 2837 = nand( 3483, 3490) 2849 = not( 2848) 3524 = not( 3520) 2888 = nand( 2886, 2887) 2891 = nand( 2895, 2896) 2833 = nand( 2831, 2832) 2838 = nand( 2836, 2837) 2892 = not( 2891) 3517 = buff( 2844) 2906 = and( 2844, 2888, 2900) 2908 = and( 2849, 2888, 2903) 2913 = not( 2838) 3523 = not( 3517) 2855 = nand( 3517, 3524) 2907 = and( 2844, 2892, 2903) 2909 = and( 2849, 2892, 2900) 3525 = buff( 2833) 3533 = buff( 2833) 2854 = nand( 3520, 3523) 2910 = or( 2906, 2907, 2908, 2909) 3560 = buff( 2913) 3568 = buff( 2913) 2856 = nand( 2854, 2855) 3539 = not( 3533) 3531 = not( 3525) 3572 = not( 3568) 3564 = not( 3560) 3557 = buff( 2910) 3565 = buff( 2910) 3528 = buff( 2856) 3536 = buff( 2856) 2921 = nand( 3557, 3564) 2917 = nand( 3565, 3572) 3571 = not( 3565) 3563 = not( 3557) 2863 = nand( 3528, 3531) 2859 = nand( 3536, 3539) 2920 = nand( 3560, 3563) 2916 = nand( 3568, 3571) 3540 = not( 3536) 3532 = not( 3528) 2864 = nand( 3525, 3532) 2860 = nand( 3533, 3540) 403 = nand( 2920, 2921) 404 = nand( 2916, 2917) 400 = nand( 2863, 2864) 401 = nand( 2859, 2860) 405 = and( 403, 404) 402 = nand( 400, 401) |
Added c3540/c3540gate.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 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922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 |
/****************************************************************************
* *
* VERILOG VERSION of ORIGINAL NETLIST for c3540 *
* *
* *
* Generated by: Hakan Yalcin (hyalcin@cadence.com) *
* *
* Sep 16, 1998 *
* *
****************************************************************************/
module c3540g (
L50, L58, L68, L77, L87, L97, L107,
L116, L226, L232, L238, L244, L250, L257, L264,
L270, L124, L125, L128, L132, L137, L143, L150,
L159, L283, L294, L303, L311, L317, L322, L326,
L329, L222, L223, L330, L274, L2897, L200, L190,
L179, L343, L213, L169, L45, L41, L1698, L33,
L20, L13, L1,
L375, L378, L381, L384, L387, L390, L393,
L396, L407, L409, L402, L351, L358, L405, L399,
L369, L372, L353, L355, L361, L364, L367);
input
L50, L58, L68, L77, L87, L97, L107,
L116, L226, L232, L238, L244, L250, L257, L264,
L270, L124, L125, L128, L132, L137, L143, L150,
L159, L283, L294, L303, L311, L317, L322, L326,
L329, L222, L223, L330, L274, L2897, L200, L190,
L179, L343, L213, L169, L45, L41, L1698, L33,
L20, L13, L1;
output
L375, L378, L381, L384, L387, L390, L393,
L396, L407, L409, L402, L351, L358, L405, L399,
L369, L372, L353, L355, L361, L364, L367;
buffer U1 ( L50, L432 );
inv U2 ( L50, L442 );
buffer U3 ( L58, L447 );
inv U4 ( L58, L456 );
buffer U5 ( L68, L460 );
inv U6 ( L68, L463 );
buffer U7 ( L68, L467 );
buffer U8 ( L77, L476 );
inv U9 ( L77, L479 );
buffer U10 ( L77, L483 );
buffer U11 ( L87, L492 );
inv U12 ( L87, L501 );
buffer U13 ( L97, L504 );
inv U14 ( L97, L513 );
buffer U15 ( L107, L517 );
inv U16 ( L107, L526 );
buffer U17 ( L116, L530 );
inv U18 ( L116, L540 );
or2 U19 ( L257, L264, L587 );
inv U20 ( L1, L704 );
buffer U21 ( L1, L707 );
inv U22 ( L1, L714 );
buffer U23 ( L13, L717 );
inv U24 ( L13, L724 );
and2 U25 ( L13, L20, L731 );
inv U26 ( L20, L732 );
buffer U27 ( L20, L736 );
inv U28 ( L20, L741 );
inv U29 ( L33, L758 );
buffer U30 ( L33, L776 );
inv U31 ( L33, L780 );
and2 U32 ( L33, L41, L788 );
inv U33 ( L41, L791 );
or2 U34 ( L41, L45, L798 );
buffer U35 ( L45, L799 );
inv U36 ( L45, L802 );
inv U37 ( L50, L826 );
buffer U38 ( L58, L828 );
inv U39 ( L58, L831 );
buffer U40 ( L68, L833 );
inv U41 ( L68, L836 );
buffer U42 ( L87, L839 );
inv U43 ( L87, L842 );
buffer U44 ( L97, L845 );
inv U45 ( L97, L848 );
inv U46 ( L107, L851 );
buffer U47 ( L1, L890 );
buffer U48 ( L68, L898 );
buffer U49 ( L107, L907 );
inv U50 ( L20, L1032 );
buffer U51 ( L190, L1035 );
inv U52 ( L200, L1048 );
and2 U53 ( L20, L200, L1049 );
nand2 U54 ( L20, L200, L1050 );
and2 U55 ( L20, L179, L1051 );
inv U56 ( L20, L1540 );
or2 U57 ( L1698, L33, L1699 );
nand2 U58 ( L1, L13, L1826 );
nand3 U59 ( L1, L20, L33, L1827 );
inv U60 ( L20, L1828 );
inv U61 ( L33, L2051 );
buffer U62 ( L179, L2478 );
inv U63 ( L213, L2865 );
buffer U64 ( L343, L2868 );
buffer U65 ( L226, L2931 );
buffer U66 ( L232, L2934 );
buffer U67 ( L238, L2939 );
buffer U68 ( L244, L2942 );
buffer U69 ( L250, L2947 );
buffer U70 ( L257, L2950 );
buffer U71 ( L264, L2957 );
buffer U72 ( L270, L2960 );
buffer U73 ( L50, L3007 );
buffer U74 ( L58, L3079 );
buffer U75 ( L58, L3087 );
buffer U76 ( L97, L3095 );
buffer U77 ( L97, L3103 );
buffer U78 ( L330, L3419 );
and2 U79 ( L250, L587, L588 );
or2 U80 ( L758, L20, L759 );
or2 U81 ( L1540, L169, L1541 );
inv U82 ( L731, L1772 );
or2 U83 ( L1828, L1, L1829 );
and2 U84 ( L1826, L1827, L1834 );
or2 U85 ( L2051, L1, L2052 );
and3 U86 ( L826, L831, L836, L625 );
nand2 U87 ( L226, L432, L545 );
nand2 U88 ( L232, L447, L546 );
nand2 U89 ( L238, L467, L547 );
nand2 U90 ( L244, L483, L548 );
nand2 U91 ( L250, L492, L549 );
nand2 U92 ( L257, L504, L550 );
nand2 U93 ( L264, L517, L551 );
nand2 U94 ( L270, L530, L552 );
inv U95 ( L2931, L2937 );
inv U96 ( L2934, L2938 );
inv U97 ( L2939, L2945 );
inv U98 ( L2942, L2946 );
nand2 U99 ( L456, L463, L621 );
nand2 U100 ( L513, L526, L626 );
nand2 U101 ( L460, L476, L635 );
buffer U102 ( L442, L636 );
inv U103 ( L3079, L3085 );
inv U104 ( L3095, L3101 );
buffer U105 ( L802, L657 );
buffer U106 ( L802, L675 );
buffer U107 ( L717, L721 );
buffer U108 ( L780, L784 );
buffer U109 ( L791, L794 );
and2 U110 ( L714, L798, L807 );
and3 U111 ( L714, L799, L791, L816 );
and2 U112 ( L704, L799, L823 );
and3 U113 ( L707, L724, L736, L860 );
nand3 U114 ( L707, L724, L736, L861 );
nand2 U115 ( L707, L724, L864 );
buffer U116 ( L890, L893 );
nand3 U117 ( L717, L732, L45, L896 );
nand3 U118 ( L826, L831, L836, L897 );
inv U119 ( L3087, L3093 );
and3 U120 ( L842, L848, L851, L905 );
nand3 U121 ( L842, L848, L851, L906 );
inv U122 ( L3103, L3109 );
inv U123 ( L741, L973 );
inv U124 ( L741, L980 );
inv U125 ( L741, L987 );
inv U126 ( L741, L994 );
inv U127 ( L741, L1001 );
inv U128 ( L741, L1008 );
inv U129 ( L741, L1015 );
inv U130 ( L741, L1022 );
or2 U131 ( L1032, L1035, L1038 );
nor2 U132 ( L1032, L1035, L1043 );
buffer U133 ( L1051, L1054 );
inv U134 ( L1051, L1057 );
buffer U135 ( L776, L1512 );
buffer U136 ( L780, L1681 );
inv U137 ( L1699, L1717 );
inv U138 ( L1699, L1724 );
inv U139 ( L1699, L1731 );
inv U140 ( L1699, L1738 );
inv U141 ( L1699, L1745 );
inv U142 ( L1699, L1752 );
inv U143 ( L1699, L1759 );
inv U144 ( L1699, L1766 );
or2 U145 ( L1, L1772, L1773 );
inv U146 ( L788, L1790 );
inv U147 ( L788, L1808 );
and3 U148 ( L704, L717, L732, L2278 );
inv U149 ( L2478, L2481 );
inv U150 ( L3419, L3425 );
or2 U151 ( L2865, L2868, L2871 );
nor2 U152 ( L2865, L2868, L2874 );
inv U153 ( L2947, L2953 );
inv U154 ( L2950, L2954 );
inv U155 ( L2957, L2963 );
inv U156 ( L2960, L2964 );
buffer U157 ( L456, L3010 );
inv U158 ( L3007, L3013 );
buffer U159 ( L463, L3017 );
buffer U160 ( L479, L3020 );
buffer U161 ( L501, L3027 );
buffer U162 ( L513, L3030 );
buffer U163 ( L526, L3037 );
buffer U164 ( L540, L3040 );
buffer U165 ( L898, L3082 );
buffer U166 ( L898, L3090 );
buffer U167 ( L907, L3098 );
buffer U168 ( L907, L3106 );
nand2 U169 ( L479, L625, L352 );
and4 U170 ( L545, L546, L547, L548, L553 );
and4 U171 ( L549, L550, L551, L552, L554 );
nand2 U172 ( L2934, L2937, L555 );
nand2 U173 ( L2931, L2938, L556 );
nand2 U174 ( L2942, L2945, L560 );
nand2 U175 ( L2939, L2946, L561 );
and2 U176 ( L432, L621, L650 );
and2 U177 ( L890, L896, L956 );
inv U178 ( L759, L974 );
and2 U179 ( L741, L759, L975 );
and2 U180 ( L897, L973, L976 );
inv U181 ( L759, L981 );
and2 U182 ( L741, L759, L982 );
inv U183 ( L759, L988 );
and2 U184 ( L741, L759, L989 );
and2 U185 ( L836, L987, L990 );
inv U186 ( L759, L995 );
and2 U187 ( L741, L759, L996 );
and2 U188 ( L77, L994, L997 );
inv U189 ( L759, L1002 );
and2 U190 ( L741, L759, L1003 );
and2 U191 ( L906, L1001, L1004 );
inv U192 ( L759, L1009 );
and2 U193 ( L741, L759, L1010 );
inv U194 ( L759, L1016 );
and2 U195 ( L741, L759, L1017 );
and2 U196 ( L851, L1015, L1018 );
inv U197 ( L759, L1023 );
and2 U198 ( L741, L759, L1024 );
and2 U199 ( L116, L1022, L1025 );
and2 U200 ( L222, L1717, L1720 );
and2 U201 ( L223, L1724, L1727 );
and2 U202 ( L226, L1731, L1734 );
and2 U203 ( L232, L1738, L1741 );
and2 U204 ( L238, L1745, L1748 );
and2 U205 ( L244, L1752, L1755 );
and2 U206 ( L250, L1759, L1762 );
and2 U207 ( L257, L1766, L1769 );
and3 U208 ( L1, L13, L1790, L1791 );
and3 U209 ( L1, L13, L1808, L1809 );
inv U210 ( L1834, L1851 );
inv U211 ( L1834, L1901 );
inv U212 ( L1834, L1952 );
inv U213 ( L1834, L2002 );
inv U214 ( L1834, L2057 );
inv U215 ( L1834, L2109 );
inv U216 ( L1834, L2162 );
inv U217 ( L1834, L2214 );
nand2 U218 ( L2950, L2953, L2955 );
nand2 U219 ( L2947, L2954, L2956 );
nand2 U220 ( L2960, L2963, L2965 );
nand2 U221 ( L2957, L2964, L2966 );
inv U222 ( L352, L353 );
and2 U223 ( L87, L626, L354 );
nand2 U224 ( L555, L556, L557 );
nand2 U225 ( L560, L561, L562 );
nand2 U226 ( L553, L554, L586 );
and2 U227 ( L540, L905, L630 );
nand2 U228 ( L540, L905, L634 );
inv U229 ( L636, L639 );
nand2 U230 ( L3082, L3085, L642 );
inv U231 ( L3082, L3086 );
and2 U232 ( L460, L636, L644 );
nand2 U233 ( L3098, L3101, L646 );
inv U234 ( L3098, L3102 );
nand2 U235 ( L87, L626, L654 );
inv U236 ( L657, L660 );
inv U237 ( L675, L678 );
nand2 U238 ( L860, L776, L804 );
nand2 U239 ( L860, L780, L806 );
nand3 U240 ( L707, L721, L736, L855 );
nand4 U241 ( L707, L724, L736, L794, L867 );
nand2 U242 ( L3090, L3093, L903 );
inv U243 ( L3090, L3094 );
nand2 U244 ( L3106, L3109, L912 );
inv U245 ( L3106, L3110 );
inv U246 ( L861, L915 );
inv U247 ( L893, L927 );
inv U248 ( L864, L941 );
and2 U249 ( L828, L974, L977 );
and2 U250 ( L150, L975, L978 );
and2 U251 ( L833, L981, L984 );
and2 U252 ( L159, L982, L985 );
and2 U253 ( L77, L988, L991 );
and2 U254 ( L50, L989, L992 );
and2 U255 ( L839, L995, L998 );
and2 U256 ( L828, L996, L999 );
and2 U257 ( L845, L1002, L1005 );
and2 U258 ( L833, L1003, L1006 );
and2 U259 ( L107, L1009, L1012 );
and2 U260 ( L77, L1010, L1013 );
and2 U261 ( L116, L1016, L1019 );
and2 U262 ( L839, L1017, L1020 );
and2 U263 ( L283, L1023, L1026 );
and2 U264 ( L845, L1024, L1027 );
and2 U265 ( L200, L1054, L1060 );
and2 U266 ( L1048, L1054, L1063 );
and2 U267 ( L1049, L1057, L1066 );
and2 U268 ( L1050, L1057, L1069 );
nand2 U269 ( L784, L794, L1527 );
nand2 U270 ( L776, L794, L1530 );
nand3 U271 ( L707, L721, L1541, L1542 );
nand3 U272 ( L724, L732, L784, L1563 );
nand2 U273 ( L724, L784, L1572 );
inv U274 ( L1512, L1581 );
inv U275 ( L1512, L1585 );
inv U276 ( L1512, L1589 );
inv U277 ( L1512, L1593 );
inv U278 ( L1512, L1597 );
inv U279 ( L1512, L1601 );
inv U280 ( L1512, L1605 );
inv U281 ( L1681, L1716 );
and2 U282 ( L1681, L1699, L1718 );
inv U283 ( L1681, L1723 );
and2 U284 ( L1681, L1699, L1725 );
inv U285 ( L1681, L1730 );
and2 U286 ( L1681, L1699, L1732 );
inv U287 ( L1681, L1737 );
and2 U288 ( L1681, L1699, L1739 );
inv U289 ( L1681, L1744 );
and2 U290 ( L1681, L1699, L1746 );
inv U291 ( L1681, L1751 );
and2 U292 ( L1681, L1699, L1753 );
inv U293 ( L1681, L1758 );
and2 U294 ( L1681, L1699, L1760 );
inv U295 ( L1681, L1765 );
and2 U296 ( L1681, L1699, L1767 );
and2 U297 ( L1834, L1773, L1852 );
nor2 U298 ( L50, L1773, L1856 );
inv U299 ( L807, L1870 );
and2 U300 ( L1834, L1773, L1902 );
nor2 U301 ( L58, L1773, L1906 );
inv U302 ( L807, L1920 );
and2 U303 ( L1834, L1773, L1953 );
nor2 U304 ( L68, L1773, L1957 );
inv U305 ( L807, L1971 );
and2 U306 ( L1834, L1773, L2003 );
nor2 U307 ( L77, L1773, L2007 );
inv U308 ( L807, L2021 );
and2 U309 ( L1834, L1773, L2058 );
nor2 U310 ( L87, L1773, L2062 );
inv U311 ( L823, L2076 );
and2 U312 ( L1834, L1773, L2110 );
nor2 U313 ( L97, L1773, L2114 );
inv U314 ( L816, L2128 );
and2 U315 ( L1834, L1773, L2163 );
nor2 U316 ( L107, L1773, L2167 );
inv U317 ( L816, L2181 );
and2 U318 ( L1834, L1773, L2215 );
nor2 U319 ( L116, L1773, L2219 );
inv U320 ( L816, L2233 );
and2 U321 ( L2278, L213, L2285 );
nand2 U322 ( L2278, L213, L2288 );
and3 U323 ( L2278, L213, L343, L2289 );
nand3 U324 ( L2278, L213, L343, L2293 );
and3 U325 ( L2278, L213, L343, L2298 );
nand3 U326 ( L2278, L213, L343, L2302 );
buffer U327 ( L2874, L2877 );
nand2 U328 ( L2955, L2956, L2983 );
nand2 U329 ( L2965, L2966, L2986 );
inv U330 ( L3010, L3014 );
nand2 U331 ( L3010, L3013, L3015 );
inv U332 ( L3017, L3023 );
inv U333 ( L3020, L3024 );
inv U334 ( L3027, L3033 );
inv U335 ( L3030, L3034 );
inv U336 ( L3037, L3043 );
inv U337 ( L3040, L3044 );
inv U338 ( L354, L355 );
nand2 U339 ( L3079, L3086, L643 );
nand2 U340 ( L3095, L3102, L647 );
and2 U341 ( L650, L675, L680 );
nand2 U342 ( L3087, L3094, L904 );
nand2 U343 ( L3103, L3110, L913 );
and2 U344 ( L588, L915, L920 );
or3 U345 ( L976, L977, L978, L979 );
or3 U346 ( L990, L991, L992, L993 );
or3 U347 ( L997, L998, L999, L1000 );
or3 U348 ( L1004, L1005, L1006, L1007 );
or3 U349 ( L1018, L1019, L1020, L1021 );
or3 U350 ( L1025, L1026, L1027, L1028 );
and2 U351 ( L77, L1716, L1719 );
and2 U352 ( L223, L1718, L1721 );
and2 U353 ( L87, L1723, L1726 );
and2 U354 ( L226, L1725, L1728 );
and2 U355 ( L97, L1730, L1733 );
and2 U356 ( L232, L1732, L1735 );
and2 U357 ( L107, L1737, L1740 );
and2 U358 ( L238, L1739, L1742 );
and2 U359 ( L116, L1744, L1747 );
and2 U360 ( L244, L1746, L1749 );
and2 U361 ( L283, L1751, L1754 );
and2 U362 ( L250, L1753, L1756 );
and2 U363 ( L294, L1758, L1761 );
and2 U364 ( L257, L1760, L1763 );
and2 U365 ( L303, L1765, L1768 );
and2 U366 ( L264, L1767, L1770 );
buffer U367 ( L1791, L1794 );
inv U368 ( L1791, L1799 );
buffer U369 ( L1809, L1812 );
inv U370 ( L1809, L1817 );
and3 U371 ( L50, L1829, L1852, L1859 );
and3 U372 ( L58, L1829, L1902, L1909 );
and3 U373 ( L68, L1829, L1953, L1960 );
and3 U374 ( L77, L1829, L2003, L2010 );
and3 U375 ( L87, L2052, L2058, L2065 );
and3 U376 ( L97, L2052, L2110, L2117 );
and3 U377 ( L107, L2052, L2163, L2170 );
and3 U378 ( L116, L2052, L2215, L2222 );
inv U379 ( L956, L2678 );
inv U380 ( L956, L2697 );
inv U381 ( L956, L2716 );
inv U382 ( L956, L2733 );
inv U383 ( L956, L2751 );
inv U384 ( L956, L2768 );
inv U385 ( L956, L2785 );
inv U386 ( L956, L2802 );
nand2 U387 ( L3007, L3014, L3016 );
nand2 U388 ( L3020, L3023, L3025 );
nand2 U389 ( L3017, L3024, L3026 );
nand2 U390 ( L3030, L3033, L3035 );
nand2 U391 ( L3027, L3034, L3036 );
nand2 U392 ( L3040, L3043, L3045 );
nand2 U393 ( L3037, L3044, L3046 );
inv U394 ( L2983, L2989 );
inv U395 ( L2986, L2990 );
inv U396 ( L804, L610 );
and2 U397 ( L804, L806, L613 );
inv U398 ( L806, L616 );
nand2 U399 ( L642, L643, L640 );
nand2 U400 ( L646, L647, L648 );
and4 U401 ( L630, L635, L442, L58, L655 );
inv U402 ( L804, L665 );
and2 U403 ( L804, L806, L668 );
inv U404 ( L806, L671 );
inv U405 ( L804, L683 );
inv U406 ( L806, L685 );
and2 U407 ( L804, L806, L688 );
inv U408 ( L804, L694 );
inv U409 ( L806, L696 );
and2 U410 ( L804, L806, L699 );
buffer U411 ( L867, L870 );
buffer U412 ( L867, L887 );
nand2 U413 ( L903, L904, L901 );
nand2 U414 ( L912, L913, L910 );
inv U415 ( L855, L914 );
and2 U416 ( L855, L861, L916 );
inv U417 ( L855, L942 );
and2 U418 ( L864, L855, L943 );
nand2 U419 ( L1043, L1069, L1072 );
nand2 U420 ( L1043, L1066, L1084 );
nand2 U421 ( L1038, L1069, L1096 );
nand2 U422 ( L1038, L1066, L1108 );
nand2 U423 ( L1043, L1063, L1120 );
nand2 U424 ( L1043, L1060, L1132 );
nand2 U425 ( L1038, L1063, L1144 );
nand2 U426 ( L1038, L1060, L1156 );
inv U427 ( L1527, L1533 );
inv U428 ( L1530, L1534 );
and2 U429 ( L1527, L1530, L1535 );
buffer U430 ( L1542, L1545 );
buffer U431 ( L1542, L1554 );
inv U432 ( L1572, L1610 );
inv U433 ( L1572, L1619 );
inv U434 ( L1572, L1628 );
inv U435 ( L1572, L1637 );
inv U436 ( L1563, L1646 );
inv U437 ( L1563, L1655 );
inv U438 ( L1563, L1664 );
inv U439 ( L1563, L1673 );
or3 U440 ( L1719, L1720, L1721, L1722 );
or3 U441 ( L1726, L1727, L1728, L1729 );
or3 U442 ( L1733, L1734, L1735, L1736 );
or3 U443 ( L1740, L1741, L1742, L1743 );
or3 U444 ( L1747, L1748, L1749, L1750 );
or3 U445 ( L1754, L1755, L1756, L1757 );
or3 U446 ( L1761, L1762, L1763, L1764 );
or3 U447 ( L1768, L1769, L1770, L1771 );
and2 U448 ( L979, L1851, L1853 );
and2 U449 ( L993, L1952, L1954 );
and2 U450 ( L1000, L2002, L2004 );
and2 U451 ( L1007, L2057, L2059 );
and2 U452 ( L1021, L2162, L2164 );
and2 U453 ( L1028, L2214, L2216 );
buffer U454 ( L2293, L2485 );
and2 U455 ( L2877, L2897, L2900 );
nand2 U456 ( L2877, L2897, L2903 );
buffer U457 ( L557, L2967 );
buffer U458 ( L562, L2970 );
buffer U459 ( L557, L2975 );
buffer U460 ( L562, L2978 );
nand2 U461 ( L3015, L3016, L3047 );
nand2 U462 ( L3025, L3026, L3050 );
nand2 U463 ( L3035, L3036, L3055 );
nand2 U464 ( L3045, L3046, L3058 );
nand2 U465 ( L2986, L2989, L574 );
nand2 U466 ( L2983, L2990, L575 );
and2 U467 ( L501, L613, L617 );
and3 U468 ( L640, L476, L639, L641 );
and2 U469 ( L530, L648, L649 );
and2 U470 ( L655, L657, L662 );
and2 U471 ( L513, L668, L672 );
and2 U472 ( L654, L685, L690 );
and2 U473 ( L540, L688, L691 );
and2 U474 ( L634, L696, L701 );
and2 U475 ( L526, L699, L702 );
inv U476 ( L901, L902 );
inv U477 ( L910, L911 );
and2 U478 ( L650, L914, L917 );
and2 U479 ( L586, L916, L923 );
and2 U480 ( L442, L1535, L1538 );
and3 U481 ( L1817, L226, L1870, L1871 );
and3 U482 ( L1817, L274, L807, L1872 );
and2 U483 ( L1812, L1722, L1873 );
and3 U484 ( L1817, L232, L1920, L1921 );
and3 U485 ( L1817, L274, L807, L1922 );
and2 U486 ( L1812, L1729, L1923 );
and3 U487 ( L1817, L238, L1971, L1972 );
and3 U488 ( L1817, L274, L807, L1973 );
and2 U489 ( L1812, L1736, L1974 );
and3 U490 ( L1817, L244, L2021, L2022 );
and3 U491 ( L1817, L274, L807, L2023 );
and2 U492 ( L1812, L1743, L2024 );
and3 U493 ( L1799, L250, L2076, L2077 );
and3 U494 ( L1799, L274, L823, L2078 );
and2 U495 ( L1794, L1750, L2079 );
and3 U496 ( L1799, L257, L2128, L2129 );
and3 U497 ( L1799, L274, L816, L2130 );
and2 U498 ( L1794, L1757, L2131 );
and3 U499 ( L1799, L264, L2181, L2182 );
and3 U500 ( L1799, L274, L816, L2183 );
and2 U501 ( L1794, L1764, L2184 );
and3 U502 ( L1799, L270, L2233, L2234 );
and3 U503 ( L1799, L274, L816, L2235 );
and2 U504 ( L1794, L1771, L2236 );
inv U505 ( L2967, L2973 );
inv U506 ( L2970, L2974 );
inv U507 ( L2975, L2981 );
inv U508 ( L2978, L2982 );
nand2 U509 ( L574, L575, L576 );
inv U510 ( L3047, L3053 );
inv U511 ( L3050, L3054 );
inv U512 ( L3055, L3061 );
inv U513 ( L3058, L3062 );
or2 U514 ( L641, L644, L645 );
inv U515 ( L887, L926 );
and2 U516 ( L887, L893, L928 );
and2 U517 ( L649, L942, L947 );
and2 U518 ( L902, L980, L983 );
and2 U519 ( L911, L1008, L1011 );
buffer U520 ( L1072, L1075 );
buffer U521 ( L1084, L1087 );
buffer U522 ( L1096, L1099 );
buffer U523 ( L1108, L1111 );
buffer U524 ( L1120, L1123 );
buffer U525 ( L1132, L1135 );
buffer U526 ( L1144, L1147 );
buffer U527 ( L1156, L1159 );
buffer U528 ( L1072, L1168 );
buffer U529 ( L1084, L1177 );
buffer U530 ( L1096, L1186 );
buffer U531 ( L1108, L1195 );
buffer U532 ( L1120, L1204 );
buffer U533 ( L1132, L1213 );
buffer U534 ( L1144, L1222 );
buffer U535 ( L1156, L1231 );
inv U536 ( L1545, L1609 );
and2 U537 ( L1545, L1572, L1611 );
inv U538 ( L1545, L1618 );
and2 U539 ( L1545, L1572, L1620 );
inv U540 ( L1545, L1627 );
and2 U541 ( L1545, L1572, L1629 );
inv U542 ( L1545, L1636 );
and2 U543 ( L1545, L1572, L1638 );
inv U544 ( L1554, L1645 );
and2 U545 ( L1554, L1563, L1647 );
inv U546 ( L1554, L1654 );
and2 U547 ( L1554, L1563, L1656 );
inv U548 ( L1554, L1663 );
and2 U549 ( L1554, L1563, L1665 );
inv U550 ( L1554, L1672 );
and2 U551 ( L1554, L1563, L1674 );
or3 U552 ( L1853, L1856, L1859, L1862 );
nor3 U553 ( L1853, L1856, L1859, L1866 );
or3 U554 ( L1871, L1872, L1873, L1874 );
or3 U555 ( L1921, L1922, L1923, L1924 );
or3 U556 ( L1954, L1957, L1960, L1963 );
nor3 U557 ( L1954, L1957, L1960, L1967 );
or3 U558 ( L1972, L1973, L1974, L1975 );
or3 U559 ( L2004, L2007, L2010, L2013 );
nor3 U560 ( L2004, L2007, L2010, L2017 );
or3 U561 ( L2022, L2023, L2024, L2025 );
or3 U562 ( L2059, L2062, L2065, L2068 );
nor3 U563 ( L2059, L2062, L2065, L2072 );
or3 U564 ( L2077, L2078, L2079, L2080 );
or3 U565 ( L2129, L2130, L2131, L2132 );
or3 U566 ( L2164, L2167, L2170, L2173 );
nor3 U567 ( L2164, L2167, L2170, L2177 );
or3 U568 ( L2182, L2183, L2184, L2185 );
or3 U569 ( L2216, L2219, L2222, L2225 );
nor3 U570 ( L2216, L2219, L2222, L2229 );
or3 U571 ( L2234, L2235, L2236, L2237 );
inv U572 ( L2485, L2488 );
inv U573 ( L870, L2679 );
and2 U574 ( L956, L870, L2680 );
inv U575 ( L870, L2698 );
and2 U576 ( L956, L870, L2699 );
inv U577 ( L870, L2717 );
and2 U578 ( L956, L870, L2718 );
inv U579 ( L870, L2734 );
and2 U580 ( L956, L870, L2735 );
inv U581 ( L870, L2752 );
and2 U582 ( L956, L870, L2753 );
inv U583 ( L870, L2769 );
and2 U584 ( L956, L870, L2770 );
inv U585 ( L870, L2786 );
and2 U586 ( L956, L870, L2787 );
inv U587 ( L870, L2803 );
and2 U588 ( L956, L870, L2804 );
or3 U589 ( L917, L920, L923, L359 );
nor3 U590 ( L917, L920, L923, L1029 );
nand2 U591 ( L2970, L2973, L565 );
nand2 U592 ( L2967, L2974, L566 );
nand2 U593 ( L2978, L2981, L569 );
nand2 U594 ( L2975, L2982, L570 );
nand2 U595 ( L3050, L3053, L589 );
nand2 U596 ( L3047, L3054, L590 );
nand2 U597 ( L3058, L3061, L595 );
nand2 U598 ( L3055, L3062, L596 );
and2 U599 ( L650, L926, L929 );
and2 U600 ( L630, L928, L938 );
and2 U601 ( L645, L941, L944 );
or3 U602 ( L983, L984, L985, L986 );
or3 U603 ( L1011, L1012, L1013, L1014 );
and2 U604 ( L442, L1611, L1616 );
and2 U605 ( L456, L1620, L1625 );
and2 U606 ( L463, L1629, L1634 );
and2 U607 ( L479, L1638, L1643 );
inv U608 ( L1029, L360 );
nand2 U609 ( L565, L566, L567 );
nand2 U610 ( L569, L570, L571 );
buffer U611 ( L576, L579 );
nand2 U612 ( L589, L590, L591 );
nand2 U613 ( L595, L596, L597 );
and2 U614 ( L576, L610, L614 );
inv U615 ( L1075, L1240 );
inv U616 ( L1087, L1241 );
inv U617 ( L1099, L1242 );
inv U618 ( L1111, L1243 );
inv U619 ( L1123, L1244 );
inv U620 ( L1135, L1245 );
inv U621 ( L1147, L1246 );
inv U622 ( L1159, L1247 );
inv U623 ( L1075, L1257 );
inv U624 ( L1087, L1258 );
inv U625 ( L1099, L1259 );
inv U626 ( L1111, L1260 );
inv U627 ( L1123, L1261 );
inv U628 ( L1135, L1262 );
inv U629 ( L1147, L1263 );
inv U630 ( L1159, L1264 );
inv U631 ( L1075, L1274 );
inv U632 ( L1087, L1275 );
inv U633 ( L1099, L1276 );
inv U634 ( L1111, L1277 );
inv U635 ( L1123, L1278 );
inv U636 ( L1135, L1279 );
inv U637 ( L1147, L1280 );
inv U638 ( L1159, L1281 );
inv U639 ( L1075, L1291 );
inv U640 ( L1087, L1292 );
inv U641 ( L1099, L1293 );
inv U642 ( L1111, L1294 );
inv U643 ( L1123, L1295 );
inv U644 ( L1135, L1296 );
inv U645 ( L1147, L1297 );
inv U646 ( L1159, L1298 );
inv U647 ( L1075, L1308 );
inv U648 ( L1087, L1309 );
inv U649 ( L1099, L1310 );
inv U650 ( L1111, L1311 );
inv U651 ( L1123, L1312 );
inv U652 ( L1135, L1313 );
inv U653 ( L1147, L1314 );
inv U654 ( L1159, L1315 );
inv U655 ( L1075, L1325 );
inv U656 ( L1087, L1326 );
inv U657 ( L1099, L1327 );
inv U658 ( L1111, L1328 );
inv U659 ( L1123, L1329 );
inv U660 ( L1135, L1330 );
inv U661 ( L1147, L1331 );
inv U662 ( L1159, L1332 );
inv U663 ( L1075, L1342 );
inv U664 ( L1087, L1343 );
inv U665 ( L1099, L1344 );
inv U666 ( L1111, L1345 );
inv U667 ( L1123, L1346 );
inv U668 ( L1135, L1347 );
inv U669 ( L1147, L1348 );
inv U670 ( L1159, L1349 );
inv U671 ( L1075, L1359 );
inv U672 ( L1087, L1360 );
inv U673 ( L1099, L1361 );
inv U674 ( L1111, L1362 );
inv U675 ( L1123, L1363 );
inv U676 ( L1135, L1364 );
inv U677 ( L1147, L1365 );
inv U678 ( L1159, L1366 );
inv U679 ( L1168, L1376 );
inv U680 ( L1177, L1377 );
inv U681 ( L1186, L1378 );
inv U682 ( L1195, L1379 );
inv U683 ( L1204, L1380 );
inv U684 ( L1213, L1381 );
inv U685 ( L1222, L1382 );
inv U686 ( L1231, L1383 );
inv U687 ( L1168, L1393 );
inv U688 ( L1177, L1394 );
inv U689 ( L1186, L1395 );
inv U690 ( L1195, L1396 );
inv U691 ( L1204, L1397 );
inv U692 ( L1213, L1398 );
inv U693 ( L1222, L1399 );
inv U694 ( L1231, L1400 );
inv U695 ( L1168, L1410 );
inv U696 ( L1177, L1411 );
inv U697 ( L1186, L1412 );
inv U698 ( L1195, L1413 );
inv U699 ( L1204, L1414 );
inv U700 ( L1213, L1415 );
inv U701 ( L1222, L1416 );
inv U702 ( L1231, L1417 );
inv U703 ( L1168, L1427 );
inv U704 ( L1177, L1428 );
inv U705 ( L1186, L1429 );
inv U706 ( L1195, L1430 );
inv U707 ( L1204, L1431 );
inv U708 ( L1213, L1432 );
inv U709 ( L1222, L1433 );
inv U710 ( L1231, L1434 );
inv U711 ( L1168, L1444 );
inv U712 ( L1177, L1445 );
inv U713 ( L1186, L1446 );
inv U714 ( L1195, L1447 );
inv U715 ( L1204, L1448 );
inv U716 ( L1213, L1449 );
inv U717 ( L1222, L1450 );
inv U718 ( L1231, L1451 );
inv U719 ( L1168, L1461 );
inv U720 ( L1177, L1462 );
inv U721 ( L1186, L1463 );
inv U722 ( L1195, L1464 );
inv U723 ( L1204, L1465 );
inv U724 ( L1213, L1466 );
inv U725 ( L1222, L1467 );
inv U726 ( L1231, L1468 );
inv U727 ( L1168, L1478 );
inv U728 ( L1177, L1479 );
inv U729 ( L1186, L1480 );
inv U730 ( L1195, L1481 );
inv U731 ( L1204, L1482 );
inv U732 ( L1213, L1483 );
inv U733 ( L1222, L1484 );
inv U734 ( L1231, L1485 );
inv U735 ( L1168, L1495 );
inv U736 ( L1177, L1496 );
inv U737 ( L1186, L1497 );
inv U738 ( L1195, L1498 );
inv U739 ( L1204, L1499 );
inv U740 ( L1213, L1500 );
inv U741 ( L1222, L1501 );
inv U742 ( L1231, L1502 );
buffer U743 ( L1874, L1877 );
inv U744 ( L1874, L1880 );
inv U745 ( L1866, L1891 );
and2 U746 ( L986, L1901, L1903 );
buffer U747 ( L1924, L1927 );
inv U748 ( L1924, L1930 );
buffer U749 ( L1975, L1978 );
inv U750 ( L1975, L1981 );
inv U751 ( L1967, L1992 );
buffer U752 ( L2025, L2028 );
inv U753 ( L2025, L2031 );
inv U754 ( L2017, L2042 );
buffer U755 ( L2080, L2085 );
inv U756 ( L2080, L2088 );
inv U757 ( L2072, L2099 );
and2 U758 ( L1014, L2109, L2111 );
buffer U759 ( L2132, L2137 );
inv U760 ( L2132, L2140 );
buffer U761 ( L2185, L2190 );
inv U762 ( L2185, L2193 );
inv U763 ( L2177, L2204 );
buffer U764 ( L2237, L2242 );
inv U765 ( L2237, L2245 );
inv U766 ( L2229, L2256 );
and2 U767 ( L2285, L1862, L2320 );
and2 U768 ( L2289, L1963, L2341 );
and2 U769 ( L2289, L2013, L2354 );
and2 U770 ( L2289, L2068, L2367 );
and2 U771 ( L2298, L2173, L2383 );
and2 U772 ( L2298, L2225, L2391 );
inv U773 ( L2080, L2474 );
inv U774 ( L2132, L2475 );
inv U775 ( L2185, L2476 );
inv U776 ( L2237, L2477 );
and5 U777 ( L2080, L2132, L2185, L2237, L2481, L2482 );
nand2 U778 ( L359, L360, L361 );
inv U779 ( L567, L568 );
or3 U780 ( L614, L616, L617, L618 );
and2 U781 ( L124, L1240, L1248 );
and2 U782 ( L159, L1241, L1249 );
and2 U783 ( L150, L1242, L1250 );
and2 U784 ( L143, L1243, L1251 );
and2 U785 ( L137, L1244, L1252 );
and2 U786 ( L132, L1245, L1253 );
and2 U787 ( L128, L1246, L1254 );
and2 U788 ( L125, L1247, L1255 );
and2 U789 ( L125, L1257, L1265 );
and2 U790 ( L432, L1258, L1266 );
and2 U791 ( L159, L1259, L1267 );
and2 U792 ( L150, L1260, L1268 );
and2 U793 ( L143, L1261, L1269 );
and2 U794 ( L137, L1262, L1270 );
and2 U795 ( L132, L1263, L1271 );
and2 U796 ( L128, L1264, L1272 );
and2 U797 ( L128, L1274, L1282 );
and2 U798 ( L447, L1275, L1283 );
and2 U799 ( L432, L1276, L1284 );
and2 U800 ( L159, L1277, L1285 );
and2 U801 ( L150, L1278, L1286 );
and2 U802 ( L143, L1279, L1287 );
and2 U803 ( L137, L1280, L1288 );
and2 U804 ( L132, L1281, L1289 );
and2 U805 ( L132, L1291, L1299 );
and2 U806 ( L467, L1292, L1300 );
and2 U807 ( L447, L1293, L1301 );
and2 U808 ( L432, L1294, L1302 );
and2 U809 ( L159, L1295, L1303 );
and2 U810 ( L150, L1296, L1304 );
and2 U811 ( L143, L1297, L1305 );
and2 U812 ( L137, L1298, L1306 );
and2 U813 ( L137, L1308, L1316 );
and2 U814 ( L483, L1309, L1317 );
and2 U815 ( L467, L1310, L1318 );
and2 U816 ( L447, L1311, L1319 );
and2 U817 ( L432, L1312, L1320 );
and2 U818 ( L159, L1313, L1321 );
and2 U819 ( L150, L1314, L1322 );
and2 U820 ( L143, L1315, L1323 );
and2 U821 ( L143, L1325, L1333 );
and2 U822 ( L492, L1326, L1334 );
and2 U823 ( L483, L1327, L1335 );
and2 U824 ( L467, L1328, L1336 );
and2 U825 ( L447, L1329, L1337 );
and2 U826 ( L432, L1330, L1338 );
and2 U827 ( L159, L1331, L1339 );
and2 U828 ( L150, L1332, L1340 );
and2 U829 ( L150, L1342, L1350 );
and2 U830 ( L504, L1343, L1351 );
and2 U831 ( L492, L1344, L1352 );
and2 U832 ( L483, L1345, L1353 );
and2 U833 ( L467, L1346, L1354 );
and2 U834 ( L447, L1347, L1355 );
and2 U835 ( L432, L1348, L1356 );
and2 U836 ( L159, L1349, L1357 );
and2 U837 ( L159, L1359, L1367 );
and2 U838 ( L517, L1360, L1368 );
and2 U839 ( L504, L1361, L1369 );
and2 U840 ( L492, L1362, L1370 );
and2 U841 ( L483, L1363, L1371 );
and2 U842 ( L467, L1364, L1372 );
and2 U843 ( L447, L1365, L1373 );
and2 U844 ( L432, L1366, L1374 );
and2 U845 ( L283, L1376, L1384 );
and2 U846 ( L447, L1377, L1385 );
and2 U847 ( L467, L1378, L1386 );
and2 U848 ( L483, L1379, L1387 );
and2 U849 ( L492, L1380, L1388 );
and2 U850 ( L504, L1381, L1389 );
and2 U851 ( L517, L1382, L1390 );
and2 U852 ( L530, L1383, L1391 );
and2 U853 ( L294, L1393, L1401 );
and2 U854 ( L467, L1394, L1402 );
and2 U855 ( L483, L1395, L1403 );
and2 U856 ( L492, L1396, L1404 );
and2 U857 ( L504, L1397, L1405 );
and2 U858 ( L517, L1398, L1406 );
and2 U859 ( L530, L1399, L1407 );
and2 U860 ( L283, L1400, L1408 );
and2 U861 ( L303, L1410, L1418 );
and2 U862 ( L483, L1411, L1419 );
and2 U863 ( L492, L1412, L1420 );
and2 U864 ( L504, L1413, L1421 );
and2 U865 ( L517, L1414, L1422 );
and2 U866 ( L530, L1415, L1423 );
and2 U867 ( L283, L1416, L1424 );
and2 U868 ( L294, L1417, L1425 );
and2 U869 ( L311, L1427, L1435 );
and2 U870 ( L492, L1428, L1436 );
and2 U871 ( L504, L1429, L1437 );
and2 U872 ( L517, L1430, L1438 );
and2 U873 ( L530, L1431, L1439 );
and2 U874 ( L283, L1432, L1440 );
and2 U875 ( L294, L1433, L1441 );
and2 U876 ( L303, L1434, L1442 );
and2 U877 ( L317, L1444, L1452 );
and2 U878 ( L504, L1445, L1453 );
and2 U879 ( L517, L1446, L1454 );
and2 U880 ( L530, L1447, L1455 );
and2 U881 ( L283, L1448, L1456 );
and2 U882 ( L294, L1449, L1457 );
and2 U883 ( L303, L1450, L1458 );
and2 U884 ( L311, L1451, L1459 );
and2 U885 ( L322, L1461, L1469 );
and2 U886 ( L517, L1462, L1470 );
and2 U887 ( L530, L1463, L1471 );
and2 U888 ( L283, L1464, L1472 );
and2 U889 ( L294, L1465, L1473 );
and2 U890 ( L303, L1466, L1474 );
and2 U891 ( L311, L1467, L1475 );
and2 U892 ( L317, L1468, L1476 );
and2 U893 ( L326, L1478, L1486 );
and2 U894 ( L530, L1479, L1487 );
and2 U895 ( L283, L1480, L1488 );
and2 U896 ( L294, L1481, L1489 );
and2 U897 ( L303, L1482, L1490 );
and2 U898 ( L311, L1483, L1491 );
and2 U899 ( L317, L1484, L1492 );
and2 U900 ( L322, L1485, L1493 );
and2 U901 ( L329, L1495, L1503 );
and2 U902 ( L283, L1496, L1504 );
and2 U903 ( L294, L1497, L1505 );
and2 U904 ( L303, L1498, L1506 );
and2 U905 ( L311, L1499, L1507 );
and2 U906 ( L317, L1500, L1508 );
and2 U907 ( L322, L1501, L1509 );
and2 U908 ( L326, L1502, L1510 );
and5 U909 ( L2474, L2475, L2476, L2477, L2478, L2483 );
buffer U910 ( L597, L600 );
and2 U911 ( L568, L660, L661 );
and2 U912 ( L597, L665, L669 );
and2 U913 ( L591, L678, L679 );
nor8 U914 ( L1248, L1249, L1250, L1251, L1252, L1253, L1254, L1255, L1256 );
nor8 U915 ( L1265, L1266, L1267, L1268, L1269, L1270, L1271, L1272, L1273 );
nor8 U916 ( L1282, L1283, L1284, L1285, L1286, L1287, L1288, L1289, L1290 );
nor8 U917 ( L1299, L1300, L1301, L1302, L1303, L1304, L1305, L1306, L1307 );
nor8 U918 ( L1316, L1317, L1318, L1319, L1320, L1321, L1322, L1323, L1324 );
nor8 U919 ( L1333, L1334, L1335, L1336, L1337, L1338, L1339, L1340, L1341 );
nor8 U920 ( L1350, L1351, L1352, L1353, L1354, L1355, L1356, L1357, L1358 );
nor8 U921 ( L1367, L1368, L1369, L1370, L1371, L1372, L1373, L1374, L1375 );
nor8 U922 ( L1384, L1385, L1386, L1387, L1388, L1389, L1390, L1391, L1392 );
nor8 U923 ( L1401, L1402, L1403, L1404, L1405, L1406, L1407, L1408, L1409 );
nor8 U924 ( L1418, L1419, L1420, L1421, L1422, L1423, L1424, L1425, L1426 );
nor8 U925 ( L1435, L1436, L1437, L1438, L1439, L1440, L1441, L1442, L1443 );
nor8 U926 ( L1452, L1453, L1454, L1455, L1456, L1457, L1458, L1459, L1460 );
nor8 U927 ( L1469, L1470, L1471, L1472, L1473, L1474, L1475, L1476, L1477 );
nor8 U928 ( L1486, L1487, L1488, L1489, L1490, L1491, L1492, L1493, L1494 );
nor8 U929 ( L1503, L1504, L1505, L1506, L1507, L1508, L1509, L1510, L1511 );
and2 U930 ( L618, L1647, L1652 );
and3 U931 ( L169, L1862, L1877, L1883 );
and3 U932 ( L179, L1862, L1880, L1886 );
and3 U933 ( L190, L1866, L1880, L1889 );
and3 U934 ( L200, L1866, L1877, L1890 );
or3 U935 ( L1903, L1906, L1909, L1912 );
nor3 U936 ( L1903, L1906, L1909, L1916 );
and3 U937 ( L169, L1963, L1978, L1984 );
and3 U938 ( L179, L1963, L1981, L1987 );
and3 U939 ( L190, L1967, L1981, L1990 );
and3 U940 ( L200, L1967, L1978, L1991 );
and3 U941 ( L169, L2013, L2028, L2034 );
and3 U942 ( L179, L2013, L2031, L2037 );
and3 U943 ( L190, L2017, L2031, L2040 );
and3 U944 ( L200, L2017, L2028, L2041 );
and3 U945 ( L169, L2068, L2085, L2091 );
and3 U946 ( L179, L2068, L2088, L2094 );
and3 U947 ( L190, L2072, L2088, L2097 );
and3 U948 ( L200, L2072, L2085, L2098 );
or3 U949 ( L2111, L2114, L2117, L2120 );
nor3 U950 ( L2111, L2114, L2117, L2124 );
and3 U951 ( L169, L2173, L2190, L2196 );
and3 U952 ( L179, L2173, L2193, L2199 );
and3 U953 ( L190, L2177, L2193, L2202 );
and3 U954 ( L200, L2177, L2190, L2203 );
and3 U955 ( L169, L2225, L2242, L2248 );
and3 U956 ( L179, L2225, L2245, L2251 );
and3 U957 ( L190, L2229, L2245, L2254 );
and3 U958 ( L200, L2229, L2242, L2255 );
or2 U959 ( L2482, L2483, L2484 );
buffer U960 ( L571, L2991 );
buffer U961 ( L579, L2994 );
buffer U962 ( L571, L2999 );
buffer U963 ( L579, L3002 );
buffer U964 ( L591, L3063 );
buffer U965 ( L591, L3071 );
buffer U966 ( L2320, L3124 );
buffer U967 ( L2320, L3134 );
buffer U968 ( L2341, L3158 );
buffer U969 ( L2341, L3166 );
buffer U970 ( L2354, L3174 );
buffer U971 ( L2354, L3182 );
buffer U972 ( L2367, L3190 );
buffer U973 ( L2367, L3200 );
buffer U974 ( L2383, L3224 );
buffer U975 ( L2383, L3232 );
buffer U976 ( L2391, L3240 );
buffer U977 ( L2391, L3248 );
nor2 U978 ( L661, L662, L663 );
or3 U979 ( L669, L671, L672, L673 );
nor2 U980 ( L679, L680, L681 );
and2 U981 ( L1256, L1533, L1536 );
and2 U982 ( L1392, L1534, L1537 );
and2 U983 ( L1273, L1581, L1582 );
and2 U984 ( L1409, L1512, L1583 );
and2 U985 ( L1290, L1585, L1586 );
and2 U986 ( L1426, L1512, L1587 );
and2 U987 ( L1307, L1589, L1590 );
and2 U988 ( L1443, L1512, L1591 );
and2 U989 ( L1324, L1593, L1594 );
and2 U990 ( L1460, L1512, L1595 );
and2 U991 ( L1341, L1597, L1598 );
and2 U992 ( L1477, L1512, L1599 );
and2 U993 ( L1358, L1601, L1602 );
and2 U994 ( L1494, L1512, L1603 );
and2 U995 ( L1375, L1605, L1606 );
and2 U996 ( L1511, L1512, L1607 );
or3 U997 ( L1889, L1890, L1891, L1894 );
or3 U998 ( L1990, L1991, L1992, L1997 );
or3 U999 ( L2040, L2041, L2042, L2047 );
or3 U1000 ( L2097, L2098, L2099, L2102 );
or3 U1001 ( L2202, L2203, L2204, L2209 );
or3 U1002 ( L2254, L2255, L2256, L2261 );
and2 U1003 ( L2484, L2488, L2489 );
inv U1004 ( L2999, L3005 );
inv U1005 ( L3002, L3006 );
inv U1006 ( L3071, L3077 );
inv U1007 ( L3063, L3069 );
inv U1008 ( L2991, L2997 );
inv U1009 ( L2994, L2998 );
and2 U1010 ( L681, L683, L689 );
and2 U1011 ( L663, L694, L700 );
or3 U1012 ( L1536, L1537, L1538, L1539 );
or2 U1013 ( L1582, L1583, L1584 );
or2 U1014 ( L1586, L1587, L1588 );
or2 U1015 ( L1590, L1591, L1592 );
or2 U1016 ( L1594, L1595, L1596 );
or2 U1017 ( L1598, L1599, L1600 );
or2 U1018 ( L1602, L1603, L1604 );
or2 U1019 ( L1606, L1607, L1608 );
and2 U1020 ( L673, L1656, L1661 );
or2 U1021 ( L1883, L1886, L1892 );
nor2 U1022 ( L1883, L1886, L1893 );
and3 U1023 ( L169, L1912, L1927, L1933 );
and3 U1024 ( L179, L1912, L1930, L1936 );
and3 U1025 ( L190, L1916, L1930, L1939 );
and3 U1026 ( L200, L1916, L1927, L1940 );
inv U1027 ( L1916, L1941 );
or2 U1028 ( L1984, L1987, L1993 );
nor2 U1029 ( L1984, L1987, L1996 );
or2 U1030 ( L2034, L2037, L2043 );
nor2 U1031 ( L2034, L2037, L2046 );
or2 U1032 ( L2091, L2094, L2100 );
nor2 U1033 ( L2091, L2094, L2101 );
and3 U1034 ( L169, L2120, L2137, L2143 );
and3 U1035 ( L179, L2120, L2140, L2146 );
and3 U1036 ( L190, L2124, L2140, L2149 );
and3 U1037 ( L200, L2124, L2137, L2150 );
inv U1038 ( L2124, L2151 );
or2 U1039 ( L2196, L2199, L2205 );
nor2 U1040 ( L2196, L2199, L2208 );
or2 U1041 ( L2248, L2251, L2257 );
nor2 U1042 ( L2248, L2251, L2260 );
inv U1043 ( L3134, L3138 );
and2 U1044 ( L2285, L1912, L2328 );
inv U1045 ( L3158, L3162 );
inv U1046 ( L3166, L3170 );
inv U1047 ( L3174, L3178 );
inv U1048 ( L3182, L3186 );
inv U1049 ( L3200, L3204 );
and2 U1050 ( L2298, L2120, L2375 );
inv U1051 ( L3232, L3236 );
inv U1052 ( L3240, L3244 );
inv U1053 ( L3248, L3252 );
inv U1054 ( L3224, L3228 );
buffer U1055 ( L600, L3066 );
buffer U1056 ( L600, L3074 );
inv U1057 ( L3124, L3128 );
inv U1058 ( L3190, L3194 );
nand2 U1059 ( L2994, L2997, L619 );
nand2 U1060 ( L2991, L2998, L620 );
nand2 U1061 ( L3002, L3005, L582 );
nand2 U1062 ( L2999, L3006, L583 );
or3 U1063 ( L689, L690, L691, L692 );
or3 U1064 ( L700, L701, L702, L703 );
and2 U1065 ( L1539, L1609, L1612 );
and2 U1066 ( L1584, L1618, L1621 );
and2 U1067 ( L1588, L1627, L1630 );
and2 U1068 ( L1592, L1636, L1639 );
and2 U1069 ( L1596, L1645, L1648 );
and2 U1070 ( L1600, L1654, L1657 );
and2 U1071 ( L1604, L1663, L1666 );
and2 U1072 ( L1608, L1672, L1675 );
and2 U1073 ( L1893, L1894, L1895 );
or3 U1074 ( L1939, L1940, L1941, L1946 );
and2 U1075 ( L1996, L1997, L1998 );
and2 U1076 ( L2046, L2047, L2048 );
and2 U1077 ( L2101, L2102, L2103 );
or3 U1078 ( L2149, L2150, L2151, L2156 );
and2 U1079 ( L2208, L2209, L2210 );
and2 U1080 ( L2260, L2261, L2262 );
inv U1081 ( L1892, L2271 );
inv U1082 ( L2100, L2311 );
nand2 U1083 ( L619, L620, L356 );
nand2 U1084 ( L582, L583, L357 );
nand2 U1085 ( L3074, L3077, L603 );
inv U1086 ( L3074, L3078 );
nand2 U1087 ( L3066, L3069, L606 );
inv U1088 ( L3066, L3070 );
and2 U1089 ( L703, L1665, L1670 );
and2 U1090 ( L692, L1674, L1679 );
or2 U1091 ( L1933, L1936, L1942 );
nor2 U1092 ( L1933, L1936, L1945 );
or2 U1093 ( L2143, L2146, L2152 );
nor2 U1094 ( L2143, L2146, L2155 );
and2 U1095 ( L1993, L2293, L2445 );
and2 U1096 ( L2043, L2293, L2448 );
and2 U1097 ( L2205, L2302, L2455 );
and2 U1098 ( L2257, L2302, L2458 );
buffer U1099 ( L2328, L3142 );
buffer U1100 ( L2328, L3150 );
buffer U1101 ( L2375, L3208 );
buffer U1102 ( L2375, L3216 );
nand2 U1103 ( L356, L357, L358 );
nand2 U1104 ( L3071, L3078, L604 );
nand2 U1105 ( L3063, L3070, L607 );
and2 U1106 ( L1945, L1946, L1947 );
and2 U1107 ( L2155, L2156, L2157 );
buffer U1108 ( L1895, L2317 );
buffer U1109 ( L1998, L2338 );
buffer U1110 ( L2048, L2351 );
buffer U1111 ( L2103, L2364 );
buffer U1112 ( L2210, L2380 );
buffer U1113 ( L2262, L2388 );
nand2 U1114 ( L603, L604, L605 );
nand2 U1115 ( L606, L607, L608 );
nand2 U1116 ( L1895, L1942, L2272 );
nand2 U1117 ( L2103, L2152, L2312 );
inv U1118 ( L3142, L3146 );
inv U1119 ( L3150, L3154 );
inv U1120 ( L3216, L3220 );
inv U1121 ( L3208, L3212 );
and2 U1122 ( L1942, L2288, L2444 );
buffer U1123 ( L2448, L2451 );
and2 U1124 ( L2152, L2293, L2454 );
buffer U1125 ( L2458, L2461 );
inv U1126 ( L2445, L2530 );
buffer U1127 ( L2458, L3323 );
inv U1128 ( L605, L349 );
inv U1129 ( L608, L350 );
and4 U1130 ( L1895, L1947, L1998, L2048, L2265 );
nand3 U1131 ( L1895, L1947, L1993, L2273 );
nand4 U1132 ( L2043, L1947, L1998, L1895, L2274 );
and4 U1133 ( L2103, L2157, L2210, L2262, L2309 );
nand3 U1134 ( L2103, L2157, L2205, L2313 );
nand4 U1135 ( L2257, L2157, L2210, L2103, L2314 );
buffer U1136 ( L1947, L2325 );
buffer U1137 ( L2157, L2372 );
inv U1138 ( L2444, L2523 );
inv U1139 ( L2454, L2533 );
buffer U1140 ( L2317, L3121 );
buffer U1141 ( L2317, L3131 );
buffer U1142 ( L2338, L3155 );
buffer U1143 ( L2338, L3163 );
buffer U1144 ( L2351, L3171 );
buffer U1145 ( L2351, L3179 );
buffer U1146 ( L2364, L3187 );
buffer U1147 ( L2364, L3197 );
buffer U1148 ( L2380, L3221 );
buffer U1149 ( L2380, L3229 );
buffer U1150 ( L2388, L3237 );
buffer U1151 ( L2388, L3245 );
nand2 U1152 ( L349, L350, L351 );
nand4 U1153 ( L2271, L2272, L2273, L2274, L2275 );
nand4 U1154 ( L2311, L2312, L2313, L2314, L2315 );
inv U1155 ( L3323, L3329 );
and2 U1156 ( L2309, L2265, L372 );
nand2 U1157 ( L3131, L3138, L2324 );
nand2 U1158 ( L3163, L3170, L2350 );
nand2 U1159 ( L3179, L3186, L2363 );
nand2 U1160 ( L3197, L3204, L2371 );
nand2 U1161 ( L3229, L3236, L2387 );
nand2 U1162 ( L3245, L3252, L2400 );
buffer U1163 ( L2265, L2268 );
inv U1164 ( L3131, L3137 );
inv U1165 ( L3155, L3161 );
nand2 U1166 ( L3155, L3162, L2345 );
inv U1167 ( L3163, L3169 );
inv U1168 ( L3171, L3177 );
nand2 U1169 ( L3171, L3178, L2358 );
inv U1170 ( L3179, L3185 );
inv U1171 ( L3197, L3203 );
inv U1172 ( L3229, L3235 );
inv U1173 ( L3237, L3243 );
nand2 U1174 ( L3237, L3244, L2395 );
inv U1175 ( L3245, L3251 );
inv U1176 ( L3221, L3227 );
nand2 U1177 ( L3221, L3228, L2432 );
and2 U1178 ( L2309, L2485, L2490 );
inv U1179 ( L3121, L3127 );
nand2 U1180 ( L3121, L3128, L3130 );
buffer U1181 ( L2325, L3139 );
buffer U1182 ( L2325, L3147 );
inv U1183 ( L3187, L3193 );
nand2 U1184 ( L3187, L3194, L3196 );
buffer U1185 ( L2372, L3205 );
buffer U1186 ( L2372, L3213 );
nand2 U1187 ( L2265, L2315, L2307 );
inv U1188 ( L2275, L2308 );
nand2 U1189 ( L3134, L3137, L2323 );
nand2 U1190 ( L3166, L3169, L2349 );
nand2 U1191 ( L3182, L3185, L2362 );
nand2 U1192 ( L3200, L3203, L2370 );
nand2 U1193 ( L3232, L3235, L2386 );
nand2 U1194 ( L3248, L3251, L2399 );
nand2 U1195 ( L3158, L3161, L2344 );
nand2 U1196 ( L3174, L3177, L2357 );
nand2 U1197 ( L3240, L3243, L2394 );
nand2 U1198 ( L3224, L3227, L2431 );
and2 U1199 ( L2315, L2302, L2464 );
or2 U1200 ( L2489, L2490, L2491 );
nand2 U1201 ( L3124, L3127, L3129 );
nand2 U1202 ( L3190, L3193, L3195 );
and2 U1203 ( L2307, L2308, L368 );
nand2 U1204 ( L2323, L2324, L1615 );
nand2 U1205 ( L3147, L3154, L2337 );
nand2 U1206 ( L2349, L2350, L1633 );
nand2 U1207 ( L2362, L2363, L1642 );
nand2 U1208 ( L2370, L2371, L1651 );
nand2 U1209 ( L3213, L3220, L2379 );
nand2 U1210 ( L2386, L2387, L1669 );
nand2 U1211 ( L2399, L2400, L1678 );
inv U1212 ( L3139, L3145 );
nand2 U1213 ( L3139, L3146, L2332 );
inv U1214 ( L3147, L3153 );
nand2 U1215 ( L2344, L2345, L2346 );
nand2 U1216 ( L2357, L2358, L2359 );
inv U1217 ( L3213, L3219 );
nand2 U1218 ( L2394, L2395, L2396 );
inv U1219 ( L3205, L3211 );
nand2 U1220 ( L3205, L3212, L2425 );
nand2 U1221 ( L2431, L2432, L2433 );
nand2 U1222 ( L3129, L3130, L3272 );
nand2 U1223 ( L3195, L3196, L3308 );
inv U1224 ( L368, L369 );
inv U1225 ( L1615, L1613 );
nand2 U1226 ( L3150, L3153, L2336 );
inv U1227 ( L1633, L1631 );
inv U1228 ( L1642, L1640 );
inv U1229 ( L1651, L1649 );
nand2 U1230 ( L3216, L3219, L2378 );
inv U1231 ( L1669, L1667 );
inv U1232 ( L1678, L1676 );
nand2 U1233 ( L3142, L3145, L2331 );
nand2 U1234 ( L3208, L3211, L2424 );
buffer U1235 ( L2464, L2467 );
buffer U1236 ( L2491, L2495 );
buffer U1237 ( L2464, L3295 );
and2 U1238 ( L330, L2491, L3374 );
and2 U1239 ( L1613, L1610, L1614 );
nand2 U1240 ( L2336, L2337, L1624 );
and2 U1241 ( L1631, L1628, L1632 );
and2 U1242 ( L1640, L1637, L1641 );
and2 U1243 ( L1649, L1646, L1650 );
nand2 U1244 ( L2378, L2379, L1660 );
and2 U1245 ( L1667, L1664, L1668 );
and2 U1246 ( L1676, L1673, L1677 );
nand2 U1247 ( L2331, L2332, L2333 );
buffer U1248 ( L2346, L2406 );
buffer U1249 ( L2346, L2409 );
buffer U1250 ( L2359, L2415 );
buffer U1251 ( L2359, L2419 );
nand2 U1252 ( L2424, L2425, L2426 );
buffer U1253 ( L2396, L2439 );
and2 U1254 ( L2433, L2461, L2518 );
inv U1255 ( L3272, L3276 );
inv U1256 ( L3308, L3312 );
and2 U1257 ( L330, L2396, L2612 );
buffer U1258 ( L2433, L3326 );
nor3 U1259 ( L1612, L1614, L1616, L1617 );
inv U1260 ( L1624, L1622 );
nor3 U1261 ( L1630, L1632, L1634, L1635 );
nor3 U1262 ( L1639, L1641, L1643, L1644 );
nor3 U1263 ( L1648, L1650, L1652, L1653 );
inv U1264 ( L1660, L1658 );
nor3 U1265 ( L1666, L1668, L1670, L1671 );
nor3 U1266 ( L1675, L1677, L1679, L1680 );
and2 U1267 ( L2467, L2268, L2500 );
and2 U1268 ( L2495, L2268, L2505 );
or2 U1269 ( L2455, L2518, L2519 );
inv U1270 ( L3374, L3378 );
inv U1271 ( L2467, L2642 );
buffer U1272 ( L2467, L2645 );
inv U1273 ( L3295, L3301 );
and2 U1274 ( L1622, L1619, L1623 );
and2 U1275 ( L1658, L1655, L1659 );
buffer U1276 ( L2333, L2401 );
or2 U1277 ( L2275, L2500, L2501 );
and3 U1278 ( L2495, L2419, L2409, L2511 );
and2 U1279 ( L2495, L2415, L2512 );
and3 U1280 ( L2439, L2433, L2426, L2513 );
and2 U1281 ( L2439, L2433, L2514 );
and2 U1282 ( L2467, L2415, L2517 );
nand2 U1283 ( L2409, L2451, L2531 );
nand3 U1284 ( L2409, L2419, L2467, L2532 );
nand2 U1285 ( L2426, L2455, L2534 );
nand3 U1286 ( L2426, L2433, L2461, L2535 );
nand2 U1287 ( L3326, L3329, L2607 );
inv U1288 ( L3326, L3330 );
and3 U1289 ( L330, L2491, L2642, L2643 );
and2 U1290 ( L1617, L2680, L2687 );
and2 U1291 ( L1635, L2718, L2725 );
and2 U1292 ( L1644, L2735, L2742 );
and2 U1293 ( L1653, L2753, L2760 );
and2 U1294 ( L1671, L2787, L2794 );
and2 U1295 ( L1680, L2804, L2811 );
buffer U1296 ( L2333, L3280 );
buffer U1297 ( L2409, L3290 );
buffer U1298 ( L2415, L3298 );
buffer U1299 ( L2426, L3316 );
buffer U1300 ( L2612, L3406 );
buffer U1301 ( L2612, L3414 );
buffer U1302 ( L2439, L3422 );
nor3 U1303 ( L1621, L1623, L1625, L1626 );
nor3 U1304 ( L1657, L1659, L1661, L1662 );
and2 U1305 ( L330, L2512, L2567 );
and2 U1306 ( L330, L2513, L2589 );
nand2 U1307 ( L3323, L3330, L2608 );
buffer U1308 ( L2519, L2654 );
buffer U1309 ( L2505, L3253 );
nand3 U1310 ( L2530, L2531, L2532, L3277 );
or2 U1311 ( L2448, L2517, L3287 );
nand3 U1312 ( L2533, L2534, L2535, L3305 );
buffer U1313 ( L2519, L3313 );
and2 U1314 ( L330, L2511, L3350 );
or2 U1315 ( L2643, L2645, L932 );
and4 U1316 ( L2495, L2401, L2409, L2419, L2508 );
nand2 U1317 ( L2401, L2445, L2524 );
nand3 U1318 ( L2401, L2406, L2451, L2525 );
nand4 U1319 ( L2401, L2406, L2419, L2467, L2526 );
inv U1320 ( L3290, L3294 );
nand2 U1321 ( L2607, L2608, L2609 );
inv U1322 ( L3406, L3410 );
inv U1323 ( L3414, L3418 );
nand2 U1324 ( L3422, L3425, L2624 );
inv U1325 ( L3422, L3426 );
buffer U1326 ( L2501, L2629 );
nor2 U1327 ( L2643, L2645, L2647 );
and2 U1328 ( L1626, L2699, L2706 );
and2 U1329 ( L1662, L2770, L2777 );
buffer U1330 ( L2501, L3264 );
inv U1331 ( L3280, L3284 );
inv U1332 ( L3298, L3302 );
nand2 U1333 ( L3298, L3301, L3303 );
inv U1334 ( L3316, L3320 );
and2 U1335 ( L330, L2514, L3398 );
inv U1336 ( L2654, L2657 );
and2 U1337 ( L2519, L2654, L398 );
and2 U1338 ( L932, L927, L933 );
nand4 U1339 ( L2523, L2524, L2525, L2526, L2527 );
inv U1340 ( L3253, L3259 );
inv U1341 ( L3350, L3354 );
inv U1342 ( L3287, L3293 );
nand2 U1343 ( L3287, L3294, L2563 );
inv U1344 ( L3305, L3311 );
nand2 U1345 ( L3305, L3312, L2585 );
nand2 U1346 ( L3419, L3426, L2625 );
inv U1347 ( L3277, L3283 );
nand2 U1348 ( L3277, L3284, L3286 );
nand2 U1349 ( L3295, L3302, L3304 );
inv U1350 ( L3313, L3319 );
nand2 U1351 ( L3313, L3320, L3322 );
buffer U1352 ( L2567, L3358 );
buffer U1353 ( L2567, L3366 );
buffer U1354 ( L2589, L3382 );
buffer U1355 ( L2589, L3390 );
and3 U1356 ( L330, L2514, L2657, L397 );
and2 U1357 ( L330, L2508, L2544 );
nand2 U1358 ( L3290, L3293, L2562 );
nand2 U1359 ( L3308, L3311, L2584 );
inv U1360 ( L3398, L3402 );
nand2 U1361 ( L2624, L2625, L2626 );
inv U1362 ( L2629, L2632 );
and2 U1363 ( L2501, L2629, L2634 );
buffer U1364 ( L2647, L2650 );
inv U1365 ( L3264, L3268 );
buffer U1366 ( L2508, L3256 );
nand2 U1367 ( L3280, L3283, L3285 );
nand2 U1368 ( L3316, L3319, L3321 );
nand2 U1369 ( L3303, L3304, L3371 );
buffer U1370 ( L2609, L3403 );
buffer U1371 ( L2609, L3411 );
or3 U1372 ( L929, L933, L938, L362 );
nor3 U1373 ( L929, L933, L938, L1030 );
or2 U1374 ( L397, L398, L399 );
nand2 U1375 ( L2562, L2563, L2564 );
inv U1376 ( L3358, L3362 );
inv U1377 ( L3366, L3370 );
nand2 U1378 ( L2584, L2585, L2586 );
inv U1379 ( L3382, L3386 );
inv U1380 ( L3390, L3394 );
and3 U1381 ( L330, L2505, L2632, L2633 );
buffer U1382 ( L2527, L3261 );
buffer U1383 ( L2527, L3269 );
nand2 U1384 ( L3285, L3286, L3347 );
nand2 U1385 ( L3321, L3322, L3395 );
inv U1386 ( L1030, L363 );
nand2 U1387 ( L3256, L3259, L2536 );
inv U1388 ( L3256, L3260 );
inv U1389 ( L3371, L3377 );
nand2 U1390 ( L3371, L3378, L2580 );
inv U1391 ( L3403, L3409 );
nand2 U1392 ( L3403, L3410, L2616 );
inv U1393 ( L3411, L3417 );
nand2 U1394 ( L3411, L3418, L2622 );
nor2 U1395 ( L2633, L2634, L2635 );
and2 U1396 ( L2626, L2802, L2805 );
and2 U1397 ( L2626, L2803, L2808 );
buffer U1398 ( L2544, L3334 );
buffer U1399 ( L2544, L3342 );
buffer U1400 ( L2650, L3454 );
and2 U1401 ( L362, L363, L364 );
nand2 U1402 ( L3253, L3260, L2537 );
inv U1403 ( L3269, L3275 );
nand2 U1404 ( L3269, L3276, L2540 );
inv U1405 ( L3347, L3353 );
nand2 U1406 ( L3347, L3354, L2557 );
nand2 U1407 ( L3374, L3377, L2579 );
inv U1408 ( L3395, L3401 );
nand2 U1409 ( L3395, L3402, L2602 );
nand2 U1410 ( L3406, L3409, L2615 );
nand2 U1411 ( L3414, L3417, L2621 );
inv U1412 ( L3261, L3267 );
nand2 U1413 ( L3261, L3268, L3112 );
buffer U1414 ( L2564, L3355 );
buffer U1415 ( L2564, L3363 );
buffer U1416 ( L2586, L3379 );
buffer U1417 ( L2586, L3387 );
nand2 U1418 ( L2536, L2537, L2538 );
nand2 U1419 ( L3272, L3275, L2539 );
inv U1420 ( L3334, L3338 );
inv U1421 ( L3342, L3346 );
nand2 U1422 ( L3350, L3353, L2556 );
nand2 U1423 ( L2579, L2580, L2581 );
nand2 U1424 ( L3398, L3401, L2601 );
nand2 U1425 ( L2615, L2616, L2617 );
nand2 U1426 ( L2621, L2622, L2623 );
buffer U1427 ( L2635, L2638 );
inv U1428 ( L3454, L3458 );
or3 U1429 ( L2805, L2808, L2811, L2814 );
nor3 U1430 ( L2805, L2808, L2811, L2816 );
nand2 U1431 ( L3264, L3267, L3111 );
nand2 U1432 ( L2539, L2540, L2541 );
nand2 U1433 ( L2556, L2557, L2558 );
inv U1434 ( L3355, L3361 );
nand2 U1435 ( L3355, L3362, L2571 );
inv U1436 ( L3363, L3369 );
nand2 U1437 ( L3363, L3370, L2577 );
inv U1438 ( L3379, L3385 );
nand2 U1439 ( L3379, L3386, L2593 );
inv U1440 ( L3387, L3393 );
nand2 U1441 ( L3387, L3394, L2598 );
nand2 U1442 ( L2601, L2602, L2603 );
nand2 U1443 ( L3111, L3112, L3113 );
and2 U1444 ( L330, L2538, L3116 );
inv U1445 ( L2623, L3451 );
inv U1446 ( L2816, L395 );
nand2 U1447 ( L3358, L3361, L2570 );
nand2 U1448 ( L3366, L3369, L2576 );
nand2 U1449 ( L3382, L3385, L2592 );
nand2 U1450 ( L3390, L3393, L2597 );
and2 U1451 ( L2581, L2733, L2736 );
and2 U1452 ( L2581, L2734, L2739 );
and2 U1453 ( L2617, L2785, L2788 );
buffer U1454 ( L2638, L3438 );
and2 U1455 ( L2617, L2647, L3446 );
buffer U1456 ( L2814, L3459 );
and2 U1457 ( L2814, L395, L396 );
inv U1458 ( L3113, L3119 );
inv U1459 ( L3116, L3120 );
nand2 U1460 ( L2570, L2571, L2572 );
nand2 U1461 ( L2576, L2577, L2578 );
nand2 U1462 ( L2592, L2593, L2594 );
nand2 U1463 ( L2597, L2598, L2599 );
nand2 U1464 ( L3451, L3458, L2677 );
inv U1465 ( L3451, L3457 );
and2 U1466 ( L2558, L2697, L2700 );
and2 U1467 ( L2603, L2768, L2771 );
buffer U1468 ( L2541, L3331 );
buffer U1469 ( L2541, L3339 );
buffer U1470 ( L2558, L3427 );
buffer U1471 ( L2603, L3443 );
nand2 U1472 ( L3116, L3119, L954 );
nand2 U1473 ( L3113, L3120, L955 );
inv U1474 ( L2599, L2600 );
inv U1475 ( L3438, L3442 );
inv U1476 ( L3446, L3450 );
nand2 U1477 ( L3454, L3457, L2676 );
or3 U1478 ( L2736, L2739, L2742, L2745 );
nor3 U1479 ( L2736, L2739, L2742, L2748 );
inv U1480 ( L3459, L3465 );
inv U1481 ( L2578, L3435 );
nand2 U1482 ( L954, L955, L950 );
inv U1483 ( L3331, L3337 );
nand2 U1484 ( L3331, L3338, L2548 );
inv U1485 ( L3339, L3345 );
nand2 U1486 ( L3339, L3346, L2553 );
nor2 U1487 ( L2600, L2650, L2661 );
and4 U1488 ( L2617, L2603, L2594, L2650, L2662 );
inv U1489 ( L3427, L3433 );
inv U1490 ( L3443, L3449 );
nand2 U1491 ( L3443, L3450, L2672 );
nand2 U1492 ( L2676, L2677, L2674 );
and2 U1493 ( L2572, L2716, L2719 );
and2 U1494 ( L2594, L2751, L2754 );
and2 U1495 ( L2572, L2635, L3430 );
inv U1496 ( L2748, L383 );
and2 U1497 ( L950, L943, L951 );
nand2 U1498 ( L3334, L3337, L2547 );
nand2 U1499 ( L3342, L3345, L2552 );
or2 U1500 ( L2661, L2662, L2663 );
nand2 U1501 ( L3435, L3442, L2670 );
inv U1502 ( L3435, L3441 );
nand2 U1503 ( L3446, L3449, L2671 );
inv U1504 ( L2674, L2675 );
buffer U1505 ( L2745, L3491 );
buffer U1506 ( L2745, L3499 );
and2 U1507 ( L2745, L383, L384 );
nand2 U1508 ( L2547, L2548, L2549 );
nand2 U1509 ( L2552, L2553, L2554 );
nand2 U1510 ( L3430, L3433, L2664 );
inv U1511 ( L3430, L3434 );
nand2 U1512 ( L3438, L3441, L2669 );
nand2 U1513 ( L2671, L2672, L2673 );
and2 U1514 ( L2663, L2752, L2757 );
and2 U1515 ( L2675, L2786, L2791 );
or3 U1516 ( L944, L947, L951, L365 );
nor3 U1517 ( L944, L947, L951, L1031 );
inv U1518 ( L2554, L2555 );
nand2 U1519 ( L3427, L3434, L2665 );
nand2 U1520 ( L2669, L2670, L2667 );
and2 U1521 ( L2673, L2769, L2774 );
inv U1522 ( L3491, L3497 );
inv U1523 ( L3499, L3505 );
inv U1524 ( L1031, L366 );
nor2 U1525 ( L2555, L2638, L2658 );
and4 U1526 ( L2572, L2558, L2549, L2638, L2659 );
nand2 U1527 ( L2664, L2665, L2666 );
inv U1528 ( L2667, L2668 );
and2 U1529 ( L2549, L2678, L2681 );
or3 U1530 ( L2754, L2757, L2760, L2763 );
nor3 U1531 ( L2754, L2757, L2760, L2765 );
or3 U1532 ( L2788, L2791, L2794, L2797 );
nor3 U1533 ( L2788, L2791, L2794, L2799 );
and2 U1534 ( L365, L366, L367 );
or2 U1535 ( L2658, L2659, L2660 );
and2 U1536 ( L2666, L2698, L2703 );
and2 U1537 ( L2668, L2717, L2722 );
or3 U1538 ( L2771, L2774, L2777, L2780 );
nor3 U1539 ( L2771, L2774, L2777, L2782 );
inv U1540 ( L2765, L386 );
inv U1541 ( L2799, L392 );
and2 U1542 ( L2660, L2679, L2684 );
buffer U1543 ( L2797, L3462 );
buffer U1544 ( L2763, L3470 );
and2 U1545 ( L2763, L386, L387 );
inv U1546 ( L2782, L389 );
and2 U1547 ( L2797, L392, L393 );
or3 U1548 ( L2700, L2703, L2706, L2709 );
nor3 U1549 ( L2700, L2703, L2706, L2713 );
or3 U1550 ( L2719, L2722, L2725, L2728 );
nor3 U1551 ( L2719, L2722, L2725, L2730 );
and4 U1552 ( L2816, L2799, L2782, L2765, L2922 );
buffer U1553 ( L2780, L3467 );
and2 U1554 ( L2780, L389, L390 );
or3 U1555 ( L2681, L2684, L2687, L2690 );
nor3 U1556 ( L2681, L2684, L2687, L2694 );
nand2 U1557 ( L3462, L3465, L2821 );
inv U1558 ( L3462, L3466 );
inv U1559 ( L3470, L3474 );
buffer U1560 ( L2709, L378 );
inv U1561 ( L2730, L380 );
nand2 U1562 ( L3459, L3466, L2822 );
inv U1563 ( L3467, L3473 );
nand2 U1564 ( L3467, L3474, L2827 );
buffer U1565 ( L2728, L2839 );
and2 U1566 ( L2709, L2871, L2883 );
buffer U1567 ( L2709, L3507 );
buffer U1568 ( L2690, L375 );
and2 U1569 ( L2728, L380, L381 );
nand2 U1570 ( L2821, L2822, L2823 );
nand2 U1571 ( L3470, L3473, L2826 );
and2 U1572 ( L2871, L2690, L2880 );
and4 U1573 ( L2748, L2730, L2713, L2694, L2925 );
and3 U1574 ( L2713, L2694, L2874, L2928 );
buffer U1575 ( L2690, L3510 );
nand2 U1576 ( L2826, L2827, L2828 );
buffer U1577 ( L2839, L3494 );
buffer U1578 ( L2839, L3502 );
inv U1579 ( L3507, L3513 );
buffer U1580 ( L2883, L3544 );
buffer U1581 ( L2883, L3552 );
and2 U1582 ( L2922, L2925, L406 );
and2 U1583 ( L2922, L2925, L2929 );
buffer U1584 ( L2823, L3475 );
buffer U1585 ( L2823, L3483 );
inv U1586 ( L3510, L3514 );
nand2 U1587 ( L3510, L3513, L3515 );
buffer U1588 ( L2880, L3541 );
buffer U1589 ( L2880, L3549 );
inv U1590 ( L406, L407 );
nor2 U1591 ( L2928, L2929, L2930 );
nand2 U1592 ( L3494, L3497, L2842 );
inv U1593 ( L3494, L3498 );
nand2 U1594 ( L3502, L3505, L2852 );
inv U1595 ( L3502, L3506 );
inv U1596 ( L3544, L3548 );
inv U1597 ( L3552, L3556 );
buffer U1598 ( L2828, L3478 );
buffer U1599 ( L2828, L3486 );
nand2 U1600 ( L3507, L3514, L3516 );
and2 U1601 ( L213, L2930, L408 );
inv U1602 ( L3475, L3481 );
inv U1603 ( L3483, L3489 );
nand2 U1604 ( L3491, L3498, L2843 );
nand2 U1605 ( L3499, L3506, L2853 );
inv U1606 ( L3541, L3547 );
nand2 U1607 ( L3541, L3548, L2887 );
nand2 U1608 ( L3549, L3556, L2896 );
inv U1609 ( L3549, L3555 );
nand2 U1610 ( L3515, L3516, L3520 );
inv U1611 ( L408, L409 );
nand2 U1612 ( L3478, L3481, L2831 );
inv U1613 ( L3478, L3482 );
nand2 U1614 ( L3486, L3489, L2836 );
inv U1615 ( L3486, L3490 );
nand2 U1616 ( L2842, L2843, L2844 );
nand2 U1617 ( L2852, L2853, L2848 );
nand2 U1618 ( L3544, L3547, L2886 );
nand2 U1619 ( L3552, L3555, L2895 );
nand2 U1620 ( L3475, L3482, L2832 );
nand2 U1621 ( L3483, L3490, L2837 );
inv U1622 ( L2848, L2849 );
inv U1623 ( L3520, L3524 );
nand2 U1624 ( L2886, L2887, L2888 );
nand2 U1625 ( L2895, L2896, L2891 );
nand2 U1626 ( L2831, L2832, L2833 );
nand2 U1627 ( L2836, L2837, L2838 );
inv U1628 ( L2891, L2892 );
buffer U1629 ( L2844, L3517 );
and3 U1630 ( L2844, L2888, L2900, L2906 );
and3 U1631 ( L2849, L2888, L2903, L2908 );
inv U1632 ( L2838, L2913 );
inv U1633 ( L3517, L3523 );
nand2 U1634 ( L3517, L3524, L2855 );
and3 U1635 ( L2844, L2892, L2903, L2907 );
and3 U1636 ( L2849, L2892, L2900, L2909 );
buffer U1637 ( L2833, L3525 );
buffer U1638 ( L2833, L3533 );
nand2 U1639 ( L3520, L3523, L2854 );
or4 U1640 ( L2906, L2907, L2908, L2909, L2910 );
buffer U1641 ( L2913, L3560 );
buffer U1642 ( L2913, L3568 );
nand2 U1643 ( L2854, L2855, L2856 );
inv U1644 ( L3533, L3539 );
inv U1645 ( L3525, L3531 );
inv U1646 ( L3568, L3572 );
inv U1647 ( L3560, L3564 );
buffer U1648 ( L2910, L3557 );
buffer U1649 ( L2910, L3565 );
buffer U1650 ( L2856, L3528 );
buffer U1651 ( L2856, L3536 );
nand2 U1652 ( L3557, L3564, L2921 );
nand2 U1653 ( L3565, L3572, L2917 );
inv U1654 ( L3565, L3571 );
inv U1655 ( L3557, L3563 );
nand2 U1656 ( L3528, L3531, L2863 );
nand2 U1657 ( L3536, L3539, L2859 );
nand2 U1658 ( L3560, L3563, L2920 );
nand2 U1659 ( L3568, L3571, L2916 );
inv U1660 ( L3536, L3540 );
inv U1661 ( L3528, L3532 );
nand2 U1662 ( L3525, L3532, L2864 );
nand2 U1663 ( L3533, L3540, L2860 );
nand2 U1664 ( L2920, L2921, L403 );
nand2 U1665 ( L2916, L2917, L404 );
nand2 U1666 ( L2863, L2864, L400 );
nand2 U1667 ( L2859, L2860, L401 );
and2 U1668 ( L403, L404, L405 );
nand2 U1669 ( L400, L401, L402 );
endmodule
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Added c3540/c3540high.v.
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/****************************************************************************
* *
* VERILOG HIGH-LEVEL DESCRIPTION OF THE ISCAS-85 BENCHMARK CIRCUIT c3540 *
* *
* *
* Written by : Hakan Yalcin (hyalcin@cadence.com) *
* Verified by : Jonathan David Hauke (jhauke@eecs.umich.edu) *
* *
* First created: Feb 11, 1997 *
* Last modified: May 9, 1998 *
* *
****************************************************************************/
module Circuit3540(
in50, in58, in68, in77, in87, in97, in107,
in116, in226, in232, in238, in244, in250, in257, in264,
in270, in124, in125, in128, in132, in137, in143, in150,
in159, in283, in294, in303, in311, in317, in322, in326,
in329, in222, in223, in330, in274, in2897, in200, in190,
in179, in343, in213, in169, in45, in41, in1698, in33,
in20, in13, in1,
out375, out378, out381, out384, out387, out390, out393,
out396, out407, out409, out402, out351, out358, out405, out399,
out369, out372, out353, out355, out361, out364, out367);
input
in50, in58, in68, in77, in87, in97, in107,
in116, in226, in232, in238, in244, in250, in257, in264,
in270, in124, in125, in128, in132, in137, in143, in150,
in159, in283, in294, in303, in311, in317, in322, in326,
in329, in222, in223, in330, in274, in2897, in200, in190,
in179, in343, in213, in169, in45, in41, in1698, in33,
in20, in13, in1;
output
out375, out378, out381, out384, out387, out390, out393,
out396, out407, out409, out402, out351, out358, out405, out399,
out369, out372, out353, out355, out361, out364, out367;
/************************/
wire [7:0] Abus, Bbus;
wire [7:0] Qbus, Rbus;
wire [1:0] Tbus;
wire K;
wire Cin;
wire [13:0] ContIn;
wire [7:0] Zbus;
wire Not_ZeroZ, ZeroZ_Cont;
wire OddParZ, OddParA, OddParB, OddParZ_Cont;
wire XCarry2, Cout_in0, PropThru;
wire [4:0] MiscOuts;
/************************/
// inputs
assign
Abus[7:0] = { in50, in58, in68, in77,
in87, in97, in107, in116 },
Bbus[7:0] = { in226, in232, in238, in244,
in250, in257, in264, in270 },
Qbus[7:0] = { in124, in125, in128, in132,
in137, in143, in150, in159 },
Rbus[7:0] = { in283, in294, in303, in311,
in317, in322, in326, in329 },
Tbus[1:0] = { in222, in223 },
Cin = in330, K = in274,
ContIn[13:0] = { in2897, in200, in190, in179, in343, in213, in169,
in45, in41, in1698, in33, in20, in13, in1 };
// outputs
assign
{ out375, out378, out381, out384,
out387, out390, out393, out396 } = Zbus[7:0];
assign
out407 = Not_ZeroZ, out409 = ZeroZ_Cont,
out402 = OddParZ, out351 = OddParA, out358 = OddParB,
out405 = OddParZ_Cont,
out399 = XCarry2, out369 = Cout_in0, out372 = PropThru;
assign
{ out353, out355, out361, out364, out367 } = MiscOuts[4:0];
/* instantiate top level circuit */
TopLevel3540 Ckt3540( Abus, Bbus, Qbus, Rbus, Tbus, Cin, K, ContIn,
Zbus, Not_ZeroZ, ZeroZ_Cont,
OddParZ, OddParA, OddParB, OddParZ_Cont,
XCarry2, Cout_in0, PropThru, MiscOuts );
endmodule // Circuit3540
/***************************************************************************/
/***************************************************************************/
module TopLevel3540( Abus, Bbus, Qbus, Rbus, Tbus, Cin, K, ContIn,
Zbus, Not_ZeroZ, ZeroZ_Cont,
OddParZ, OddParA, OddParB, OddParZ_Cont,
XCarry2, Cout_in0, PropThru, MiscOuts );
input [7:0] Abus, Bbus;
input [7:0] Qbus, Rbus;
input [1:0] Tbus;
input K;
input Cin;
input [13:0] ContIn;
output [7:0] Zbus;
output Not_ZeroZ, ZeroZ_Cont;
output OddParZ, OddParA, OddParB, OddParZ_Cont;
output XCarry2, Cout_in0, PropThru;
output [4:0] MiscOuts;
wire [7:0] A_BCDbus, Not_Abus;
wire [7:0] MAbus, MBbus;
wire [7:0] XPbus, XCarrybus, Funcbus;
wire [7:0] F_BCDbus, Hbus, Shiftbus, Wbus;
BCD_add6 M1( Abus, A_BCDbus );
Invert8 M2( Abus, Not_Abus );
MainMux1_A M3( Abus, Not_Abus, 8'h00, { Qbus[1:0], Abus[7:2] },
{ Abus[6:0], Rbus[7] }, A_BCDbus,
ContIn[3:0], MAbus );
MainMux2_B M4( Bbus, K, { Tbus[1:0], Bbus[7:2] },
{ Tbus[0], Bbus[7:1] }, { Abus[4:0], Rbus[7:5] },
ContIn, MBbus );
ALU_Core M5( MAbus, MBbus, Cin, ContIn,
XPbus, XCarrybus, XCarry2, Carry4, Cout,
Cout_in0, PropThru, Overflow );
XOR8bit M6( XPbus, XCarrybus, Funcbus );
BCD_sub6 M7( Funcbus, Carry4, Cout, F_BCDbus );
// various muxes
Shifter M8( Abus, Qbus, Rbus, ContIn, Shiftbus );
MuxModule9 M9( Abus, Bbus, ContIn, Hbus );
MuxModule10 M10( Shiftbus, Hbus, XPbus, ContIn, Wbus );
MuxModule11 M11( Funcbus, F_BCDbus, Wbus, ContIn, Zbus );
// flags
Flags M12( Zbus, Abus, Bbus, ContIn, Not_ZeroZ, ZeroZ_Cont,
OddParZ, OddParA, OddParB, OddParZ_Cont);
// Miscellaneous logic
MiscLogic M13( Abus, Bbus, Carry4, Overflow, ContIn, MiscOuts );
endmodule // TopLevel3540
/***************************************************************************
* Module 1: BCD_add6
*
* Function: adds '6' to each digit for performing BCD addition with
* an adder based on 2's complement arithmetic.
*
***************************************************************************/
module BCD_add6( Inbus, Outbus );
input [7:0] Inbus;
output [7:0] Outbus;
BCD_add6_digit UM1_0( Inbus[3:0], Outbus[3:0] ),
UM1_1( Inbus[7:4], Outbus[7:4] );
endmodule // BCD_add6
/********************************************/
module BCD_add6_digit( Inbus, Outbus );
input [3:0] Inbus;
output [3:0] Outbus;
assign Outbus[0] = Inbus[0];
inv BaD0( .A(Inbus[1]), .Y(Outbus[1]) );
XOR2a BaD1( .A(Inbus[2]), .B(Inbus[1]), .Y(line1) );
inv BaD2( .A(line1), .Y(Outbus[2]) ),
BaD3( .A(Inbus[2]), .Y(line3) ),
BaD4( .A(Inbus[3]), .Y(line4) );
nand3 BaD5( .A(Outbus[1]), .B(line3), .C(line4), .Y(Outbus[3]) );
endmodule // BCD_add6_digit
/***************************************************************************
* Module 3: MainMux1_A
*
* Function: selection of 6 input buses including Abus.
*
***************************************************************************/
module MainMux1_A( In0, In1, In2, In3, In4, In5, Sel, Out );
input [7:0] In0, In1, In2, In3, In4, In5;
input [3:0] Sel;
output [7:0] Out;
wire [7:0] temp;
wire MSel0, MSel1a, MSel1b;
wire MSel2, MSel3a, MSel3b;
Mux8bit3_1a UM3_0( In3[7:0], In4[7:0], In5[7:0],
Sel[2], Sel[3], temp[7:0] );
// some control logic to generate multiplexer control signals
nand2 UM3_1( .A(Sel[0]), .B(Sel[1]), .Y(line1) );
nand3 UM3_2( .A(Sel[0]), .B(Sel[2]), .C(Sel[3]), .Y(line2) );
and2 UM3_3( .A(line1), .B(line2), .Y(line3) ); // gamma
inv UM3_4( .A(line3), .Y(MSel0) );
and2 UM3_5( .A(Sel[1]), .B(Sel[2]), .Y(line5) );
inv UM3_6( .A(line5), .Y(line6) );
or2 UM3_7( .A(Sel[0]), .B(line6), .Y(line7) ); // lambda
inv UM3_8( .A(line7), .Y(MSel2) ),
UM3_9( .A(Sel[3]), .Y(line9) ), // !C6
UM3_10( .A(Sel[2]), .Y(line10) ); // !C9
or2 UM3_11( .A(line9), .B(Sel[0]), .Y(line11) ), // A1+!C6
UM3_12( .A(line10), .B(Sel[0]), .Y(line12) ); // A1+!C6
and3 UM3_13( .A(line3), .B(line7), .C(line11), .Y(MSel1a) ),
UM3_14( .A(line3), .B(line7), .C(line12), .Y(MSel1b) );
inv UM3_15( .A(line11), .Y(line15) ), // !(A1+!C6)
UM3_16( .A(line12), .Y(line16) ); // !(A1+!C9)
and3 UM3_17( .A(line3), .B(line7), .C(line15), .Y(MSel3a) ),
UM3_18( .A(line3), .B(line7), .C(line16), .Y(MSel3b) );
Mux4bit4_1a UM3_19( temp[3:0], In0[3:0], In1[3:0], In2[3:0],
{MSel3a, MSel2, MSel1a, MSel0}, Out[3:0] ),
UM3_20( temp[7:4], In0[7:4], In1[7:4], In2[7:4],
{MSel3b, MSel2, MSel1b, MSel0}, Out[7:4] );
endmodule // MainMux1_A
/***************************************************************************
* Module 4: MainMux2_B
*
* Function: selection of 5 input buses including Bbus.
*
***************************************************************************/
module MainMux2_B( In0, K, In2, In3, In4, ContIn, Out );
input [7:0] In0;
input K;
input [7:0] In2, In3, In4;
input [13:0] ContIn;
output [7:0] Out;
wire [7:0] temp, In1;
wire MSelHi, MSelLo1, MSelLo2, MSelLo3;
assign In1[7:0] = { K, K, K, K, K, K, K, K };
Mux8bit3_1a UM4_0( In2[7:0], In3[7:0], In4[7:0],
ContIn[3], ContIn[4], temp[7:0] );
// some control logic to generate multiplexer control signals
and2 UM4_1( .A(ContIn[3]), .B(ContIn[5]), .Y(line1) );
inv UM4_2( .A(line1), .Y(line2) );
and3 UM4_3( .A(ContIn[0]), .B(ContIn[1]), .C(line2),
.Y(MSelHi) ); // Epsilon
inv UM4_4( .A(ContIn[0]), .Y(line4) ), // !A1
UM4_5( .A(ContIn[5]), .Y(line5) ); // !C3
and3 UM4_6( .A(line4), .B(ContIn[6]), .C(line5), .Y(MSelLo1) );
and2 UM4_7( .A(line4), .B(ContIn[6]), .Y(MSelLo2) );
or2 UM4_8( .A(ContIn[5]), .B(ContIn[6]), .Y(line8) );
and2 UM4_9( .A(line4), .B(line8), .Y(MSelLo3) );
Mux3_1b UM4_11( In0[0], In1[0], temp[0],
MSelHi, MSelLo1, Out[0] ),
UM4_12( In0[1], In1[1], temp[1],
MSelHi, MSelLo1, Out[1] ),
UM4_13( In0[2], In1[2], temp[2],
MSelHi, MSelLo1, Out[2] ),
UM4_14( In0[3], In1[3], temp[3],
MSelHi, MSelLo2, Out[3] );
Mux4bit3_1b UM4_15( In0[7:4], In1[7:4], temp[7:4],
MSelHi, MSelLo3, Out[7:4] );
endmodule // MainMux2_B
/***************************************************************************
* Module 5: ALU_Core
*
* Function: performs arithmetic/logic operations
*
* - the result is obtained by XORing XPbus and XCarrybus (module M6).
* - The Mode signal, generated from the ContIn bus, specifies
* whether a logical or arithmetic operation is to be performed.
* - The 4-bit ContSel bus specifies the logical operations and
* what operands to use for the arithmetic operations.
* Example:
* ContSel=1000 => XP = InA AND InB (logical)
* XP XOR Carry = (InA AND InB) plus InBbus (arithmetic)
*
***************************************************************************/
module ALU_Core( InAbus, InBbus, Cin, ContIn,
XPbus, XCarrybus, XCarry2, Carry4, Cout,
Cout_in0, PropThru, Overflow );
input [7:0] InAbus, InBbus;
input Cin;
input [13:0] ContIn;
output [7:0] XPbus, XCarrybus;
output XCarry2, Carry4, Cout;
output Cout_in0, PropThru, Overflow;
wire [7:0] Pbus, Gbus, XGbus;
wire [3:0] ContSel;
// first: create Mode and Mask7_6 signals
// Mode = !Cont0. Cont1. !Cont2. Cont8. Cont9
// Mask7_6 = !Cont0. Cont1. !Cont2. Cont8
inv UM5_0( .A(ContIn[0]), .Y(NotCont0) ),
UM5_1( .A(ContIn[2]), .Y(NotCont2) );
and3 UM5_2( .A(NotCont0), .B(ContIn[1]), .C(NotCont2), .Y(ModeAux) ),
UM5_3( .A(ModeAux), .B(ContIn[8]), .C(ContIn[9]), .Y(Mode) );
and2 UM5_4( .A(ModeAux), .B(ContIn[8]), .Y(Mask7_6) );
// Mode=1: LOGIC MODE (Mask7_6 is also 1)
// Mode=0: ARITHMETIC MODE
// ( In this mode, if Mask7_6=1, then the 7th and 6th bits
// of InAbus are masked, i.e., they are assumed 0 )
assign ContSel[3:0] = { ContIn[7], ContIn[10], ContIn[12:11] };
Logic_and_GP8bit UM5_5( InAbus, InBbus, ContSel, Mode, Mask7_6,
Pbus, Gbus, XPbus, XGbus );
CalcCarry UM5_6( InBbus[3:0], Pbus, Gbus, XPbus, XGbus, Cin, Mode,
ContIn[10], XCarrybus, Carry4, Cout,
Cout_in0, PropThru, Overflow );
assign XCarry2 = XCarrybus[2];
endmodule // ALU_Core
/********************************************/
module Logic_and_GP8bit( InAbus, InBbus, ContSel, Mode, Mask7_6,
Pbus, Gbus, XPbus, XGbus );
input [7:0] InAbus, InBbus;
input [3:0] ContSel;
input Mode, Mask7_6;
output [7:0] Pbus, Gbus, XPbus, XGbus;
Logic_and_GP LGP8_0( InAbus[0], InBbus[0], ContSel, Mode,
Pbus[0], Gbus[0], XPbus[0], XGbus[0] ),
LGP8_1( InAbus[1], InBbus[1], ContSel, Mode,
Pbus[1], Gbus[1], XPbus[1], XGbus[1] ),
LGP8_2( InAbus[2], InBbus[2], ContSel, Mode,
Pbus[2], Gbus[2], XPbus[2], XGbus[2] ),
LGP8_3( InAbus[3], InBbus[3], ContSel, Mode,
Pbus[3], Gbus[3], XPbus[3], XGbus[3] ),
LGP8_4( InAbus[4], InBbus[4], ContSel, Mode,
Pbus[4], Gbus[4], XPbus[4], XGbus[4] ),
LGP8_5( InAbus[5], InBbus[5], ContSel, Mode,
Pbus[5], Gbus[5], XPbus[5], XGbus[5] ),
LGP8_6( InAbus[6], InBbus[6], ContSel, Mask7_6,
Pbus[6], Gbus[6], XPbus[6], XGbus[6] ),
LGP8_7( InAbus[7], InBbus[7], ContSel, Mask7_6,
Pbus[7], Gbus[7], XPbus[7], XGbus[7] );
endmodule // Logic_and_GP8
/********************************************
* Module: Logic_and_GP
*
* Function: generate the P, G, XP, XG signals
* used for addition and logic operations.
*
* - All 16 functions of (InA,InB) are generated
* as selected by ContSel
* - If Mask=1, XP=P xor InA (*), and XG=0
* If Mask=0, XP=P, and XG=G
*
* (*) the xor modifies P and creates a different
* function for XP.
*
********************************************/
module Logic_and_GP( InA, InB, ContSel, Mask,
P, G, XP, XG );
input InA, InB;
input [3:0] ContSel;
input Mask;
output P, G, XP, XG;
Mux2_1 LGP0( ContSel[0], ContSel[1], InB, Mx0 ),
LGP1( ContSel[2], ContSel[3], InB, Mx1 );
and2 LGP2( .A(InA), .B(Mx1), .Y(G) );
or2 LGP3( .A(InA), .B(Mx0), .Y(InAMx0) );
nand2 LGP4( .A(InA), .B(Mx1), .Y(InAMx1) );
and2 LGP5( .A(InAMx0), .B(InAMx1), .Y(P) );
and2 LGP6( .A(Mask), .B(InA), .Y(InAMask) );
XOR2a LGP7( .A(InAMask), .B(P), .Y(XP) );
inv LGP8( .A(Mask), .Y(NotMask) );
and2 LGP9( .A(G), .B(NotMask), .Y(XG) );
endmodule // Logic_and_GP
/*****************************************************
* Module: CalcCarry
*
* Function: calculate the carry signals (XCarrybus)
* and a few other outputs (Carry4, Cout, Cout_in0,
* PropThru, Overflow)
*
* Note: XCarrybus[i]: carry from bit (i-1) into bit i
******************************************************/
module CalcCarry( InBLo, Pbus, Gbus, XPbus, XGbus, Cin, Mode,
InBpropSel, XCarrybus, Carry4, Cout,
Cout_in0, PropThru, Overflow );
input [3:0] InBLo;
input [7:0] Pbus, Gbus, XPbus, XGbus;
input Cin, Mode, InBpropSel;
output [7:0] XCarrybus;
output Carry4, Cout;
output Cout_in0, PropThru, Overflow;
// first take care of PropThru
and4 CC0( .A(Pbus[0]), .B(Pbus[1]), .C(Pbus[2]), .D(Pbus[3]),
.Y(PropLo) ),
CC1( .A(Pbus[4]), .B(Pbus[5]), .C(Pbus[6]), .D(Pbus[7]),
.Y(PropHi) );
and2 CC2( .A(PropLo), .B(PropHi), .Y(PropThru) );
inv CC3( .A(Mode), .Y(NotMode) );
// CinPropLo: indicates whether Cin propagates to the upper half
CalcCinPropLo CC4( InBLo, PropLo, Cin, Mode, InBpropSel, CinPropLo);
AND_OR4a CC5( Gbus[3], Pbus[3], Gbus[2], Pbus[2], Gbus[1], Pbus[1],
Gbus[0], LocalC0Lo );
AND_OR4a CC6( Gbus[7], Pbus[7], Gbus[6], Pbus[6], Gbus[5], Pbus[5],
Gbus[4], LocalC0Hi );
and2 CC7( .A(LocalC0Lo), .B(NotMode), .Y(LoC0_M) );
CLAblock CC8( XPbus[3:0], XGbus[3:0], 1'b0, Cin, XCarrybus[3:0] ),
CC9( XPbus[7:4], XGbus[7:4], LoC0_M, CinPropLo, XCarrybus[7:4] );
// Cout_in0, Carry4, Cout
AND_OR2 CC10( LocalC0Hi, LocalC0Lo, PropHi, Cout_in0 );
or2 CC11( .A(CinPropLo), .B(LoC0_M), .Y(Carry4) );
and2 CC12( .A(CinPropLo), .B(PropHi), .Y(line12) );
or2 CC13( .A(Cout_in0), .B(line12), .Y(Cout) );
// Overflow = Ovf_Carry8 XOR XCarrybus[7]
//
AND_OR2 CC14( LocalC0Hi, LoC0_M, PropHi, Cout_M_in0);
XOR2a CC15( .A(Cout_M_in0), .B(line12), .Y(Ovf_Carry8) );
XOR2a CC16( .A(Ovf_Carry8), .B(XCarrybus[7]), .Y(Overflow) );
endmodule // CalcCarry
/********************************************
* Submodule: CalcCinPropLo
*
* Function: the CinPropLo line indicates whether
* Cin propagates to the upper half.
*
* In Arithmetic Mode, it's (Cin.PropLo)
* In Logic mode (Mode=1), it's either
* (InB[0].InB[1].InB[2].InB[3]).Cin or
* (!InB[0].!InB[1].!InB[2].!InB[3]).Cin
* as selected by InBpropSel.
* !!! I have no idea about its use in Logic mode.
* It may be a special feature.
********************************************/
module CalcCinPropLo( InBLo, PropLo, Cin, Mode, InBpropSel, CinPropLo);
input [3:0] InBLo;
input PropLo, Cin, Mode, InBpropSel;
output CinPropLo;
and4 CCP0( .A(InBLo[0]), .B(InBLo[1]), .C(InBLo[2]),
.D(InBLo[3]), .Y(InBLoAND) );
nor4 CCP1( .A(InBLo[0]), .B(InBLo[1]), .C(InBLo[2]),
.D(InBLo[3]), .Y(InBLoNOR) );
Mux2_1 CCP2( InBLoAND, InBLoNOR, InBpropSel, InBprop ),
CCP3( PropLo, InBprop, Mode, Pr );
and2 CCP4( .A(Cin), .B(Pr), .Y(CinPropLo) );
endmodule // CalcCinPropLo
/******************************************************/
module CLAblock( Pbus, Gbus, Cin1, Cin2, Cybus);
input [3:0] Pbus, Gbus;
input Cin1, Cin2;
output [3:0] Cybus;
wire [3:0] Cy1bus, Cy2bus;
// Note 1: Cybus[i]: carry from bit (i-1) into bit i
CLA4 Cb0( Pbus, Gbus, Cin1, Cy1bus );
CarryProp4 Cb1( Pbus, Cin2, Cy2bus );
// Note 2: Both OR and XOR will work below
XOR4bit Cb2( Cy1bus, Cy2bus, Cybus );
endmodule // CLABlock
/******************************************************/
module CLA4( Pbus, Gbus, Cin, Cybus );
input [3:0] Pbus, Gbus;
input Cin;
output [3:0] Cybus;
assign Cybus[0]=Cin;
AND_OR2 Cla4_0( Gbus[0], Pbus[0], Cin, Cybus[1] );
AND_OR3a Cla4_1( Gbus[1], Pbus[1], Gbus[0], Pbus[0], Cin, Cybus[2] );
AND_OR4a Cla4_2( Gbus[2], Pbus[2], Gbus[1], Pbus[1],
Gbus[0], Pbus[0], Cin, Cybus[3] );
endmodule
/******************************************************/
module CarryProp4( Pbus, Cin, Cybus );
input [3:0] Pbus;
input Cin;
output [3:0] Cybus;
assign Cybus[0]=Cin;
and2 CP0( .A(Pbus[0]), .B(Cin), .Y(Cybus[1]) );
and3 CP1( .A(Pbus[1]), .B(Pbus[0]), .C(Cin), .Y(Cybus[2]) );
and4 CP2( .A(Pbus[2]), .B(Pbus[1]), .C(Pbus[0]),
.D(Cin), .Y(Cybus[3]) );
endmodule // CarryProp4
/***************************************************************************
* Module 7: BCD_sub6
*
* Function: conversion back to BCD by subtracting 6 from each digit
* if no carry is generated by that digit.
*
***************************************************************************/
module BCD_sub6( Inbus, Carry4, Cout, Outbus );
input [7:0] Inbus;
input Carry4, Cout;
output [7:0] Outbus;
BCD_sub6_digit UM7_0( Inbus[3:0], Carry4, Outbus[3:0] ),
UM7_1( Inbus[7:4], Cout, Outbus[7:4] );
endmodule // BCD_sub6
/******************************************************/
module BCD_sub6_digit( Inbus, Carry, Outbus );
input [3:0] Inbus;
input Carry;
output [3:0] Outbus;
assign Outbus[0] = Inbus[0];
inv Bsd0( .A(Carry), .Y(NotCarry) );
XOR2a Bsd1( .A(Inbus[1]), .B(NotCarry), .Y(Outbus[1]) );
and2 Bsd2( .A(Inbus[1]), .B(NotCarry), .Y(line2) );
XOR2a Bsd3( .A(Inbus[2]), .B(line2), .Y(Outbus[2]) );
and4 Bsd4( .A(Inbus[3]), .B(Inbus[2]), .C(Inbus[1]),
.D(NotCarry), .Y(line4) );
and2 Bsd5( .A(Inbus[3]), .B(Carry), .Y(line5) );
or2 Bsd6( .A(line4), .B(line5), .Y(Outbus[3]) );
endmodule // BCD_sub6_digit
/***************************************************************************
* Module M8: Shifter
*
* Function: Abus is shifted both left and right by 1 to 8 bits.
* The Q and R buses fill the empty positions.
*
***************************************************************************/
module Shifter( Abus, Qbus, Rbus, ContIn, Sbus );
input [7:0] Abus, Qbus, Rbus;
input [13:0] ContIn;
output [7:0] Sbus;
wire [7:0] ContShift;
wire [7:0] ShiftQ0bus, ShiftQ1bus, ShiftQ2bus, ShiftQ3bus,
ShiftQ4bus, ShiftQ5bus, ShiftQ6bus, ShiftQ7bus,
ShiftR0bus, ShiftR1bus, ShiftR2bus, ShiftR3bus,
ShiftR4bus, ShiftR5bus, ShiftR6bus, ShiftR7bus,
ShiftQout, ShiftRout;
DecodeContSignals UM8_0( {ContIn[12:10],ContIn[2]}, ContShift );
assign
ShiftQ0bus[7:0]={ Qbus[0], Abus[7:1] },
ShiftQ1bus[7:0]={ Qbus[1:0], Abus[7:2] },
ShiftQ2bus[7:0]={ Qbus[2:0], Abus[7:3] },
ShiftQ3bus[7:0]={ Qbus[3:0], Abus[7:4] },
ShiftQ4bus[7:0]={ Qbus[4:0], Abus[7:5] },
ShiftQ5bus[7:0]={ Qbus[5:0], Abus[7:6] },
ShiftQ6bus[7:0]={ Qbus[6:0], Abus[7] },
ShiftQ7bus[7:0]={ Qbus[7:0] },
ShiftR0bus[7:0]={ Abus[6:0], Rbus[7] },
ShiftR1bus[7:0]={ Abus[5:0], Rbus[7:6] },
ShiftR2bus[7:0]={ Abus[4:0], Rbus[7:5] },
ShiftR3bus[7:0]={ Abus[3:0], Rbus[7:4] },
ShiftR4bus[7:0]={ Abus[2:0], Rbus[7:3] },
ShiftR5bus[7:0]={ Abus[1:0], Rbus[7:2] },
ShiftR6bus[7:0]={ Abus[0], Rbus[7:1] },
ShiftR7bus[7:0]={ Rbus[7:0] };
Mux8bit8_1 UM8_1( ShiftQ0bus, ShiftQ1bus, ShiftQ2bus, ShiftQ3bus,
ShiftQ4bus, ShiftQ5bus, ShiftQ6bus, ShiftQ7bus,
ContShift, ShiftQout ),
UM8_2( ShiftR0bus, ShiftR1bus, ShiftR2bus, ShiftR3bus,
ShiftR4bus, ShiftR5bus, ShiftR6bus, ShiftR7bus,
ContShift, ShiftRout );
Mux2_1 UM8_3( ShiftQout[0], ShiftRout[0], ContIn[3], Sbus[0] ),
UM8_4( ShiftQout[1], ShiftRout[1], ContIn[3], Sbus[1] ),
UM8_5( ShiftQout[2], ShiftRout[2], ContIn[3], Sbus[2] ),
UM8_6( ShiftQout[3], ShiftRout[3], ContIn[3], Sbus[3] ),
UM8_7( ShiftQout[4], ShiftRout[4], ContIn[3], Sbus[4] ),
UM8_8( ShiftQout[5], ShiftRout[5], ContIn[3], Sbus[5] ),
UM8_9( ShiftQout[6], ShiftRout[6], ContIn[3], Sbus[6] );
// there is an additional mux for Sbus[7]
Mux2_1 UM8_10( ShiftQout[7], ShiftRout[7], ContIn[3], Sbus7_0 ),
UM8_11( Sbus7_0, Abus[7], ContIn[5], Sbus[7] );
endmodule // Shifter
/******************************************************/
module DecodeContSignals( CodeIn, CodeOut );
input [3:0] CodeIn;
output [7:0] CodeOut;
and2 DCS0( .A(CodeIn[0]), .B(CodeIn[1]), .Y(tmp0) );
inv DCS1( .A(tmp0), .Y(tmp1) ),
DCS2( .A(CodeIn[0]), .Y(tmp2) );
nand2 DCS3( .A(CodeIn[0]), .B(CodeIn[3]), .Y(tmp3) );
and2 DCS4( .A(CodeIn[0]), .B(CodeIn[3]), .Y(tmp4) );
nor2 DCS5( .A(tmp2), .B(CodeIn[2]), .Y(tmp5) );
and2 DCS6( .A(tmp3), .B(tmp1), .Y(tmp6) ),
DCS7( .A(tmp4), .B(tmp1), .Y(tmp7) );
or2 DCS8( .A(tmp2), .B(CodeIn[2]), .Y(tmp8) );
inv DCS9( .A(CodeIn[3]), .Y(tmp9) );
and2 DCS10( .A(tmp9), .B(tmp0), .Y(tmp10) ),
DCS11( .A(CodeIn[3]), .B(tmp0), .Y(tmp11) );
and2 DCS13( .A(tmp5), .B(tmp7), .Y(CodeOut[0]) ),
DCS14( .A(tmp6), .B(tmp8), .Y(CodeOut[1]) ),
DCS15( .A(tmp8), .B(tmp7), .Y(CodeOut[2]) ),
DCS16( .A(tmp5), .B(tmp10), .Y(CodeOut[3]) ),
DCS17( .A(tmp5), .B(tmp11), .Y(CodeOut[4]) ),
DCS18( .A(tmp8), .B(tmp10), .Y(CodeOut[5]) ),
DCS19( .A(tmp8), .B(tmp11), .Y(CodeOut[6]) ),
DCS12( .A(tmp5), .B(tmp6), .Y(CodeOut[7]) );
endmodule // DecodeContSignals
/***************************************************************************
* Module 9: MuxModule9
*
* Function: computes some logic functions of A and B buses.
* Also includes a 3:1 mux.
*
***************************************************************************/
module MuxModule9( Abus, Bbus, ContIn, SLbus );
input [7:0] Abus, Bbus;
input [13:0] ContIn;
output [7:0] SLbus;
wire [3:0] temp1bus;
wire [1:0] temp2bus;
wire temp3;
assign SLbus[7:4] = Abus[7:4];
LogicBlockM9 UM9_0( Abus, Bbus, ContIn[6], temp1bus, temp2bus );
// Mux select inputs:
// ContHi = !(Cont0. !Cont1. Cont2. Cont3)
// ContLo = !(Cont0. !Cont1. Cont2. !Cont3)
inv UM9_1( .A(ContIn[1]), .Y(NotCont1) ),
UM9_2( .A(ContIn[3]), .Y(NotCont3) );
and3 UM9_3( .A(ContIn[0]), .B(NotCont1), .C(ContIn[2]), .Y(temp3) );
nand2 UM9_4( .A(temp3), .B(ContIn[3]), .Y(ContHi) ),
UM9_5( .A(temp3), .B(NotCont3), .Y(ContLo) );
Mux4bit3_1c UM9_6( temp1bus, {2'b00, temp2bus}, Abus[3:0],
ContHi, ContLo, SLbus[3:0] );
endmodule // MuxModule9
/******************************************************/
module LogicBlockM9( Abus, Bbus, ContInp, T1bus, T2bus );
input [7:0] Abus, Bbus;
input ContInp;
output [3:0] T1bus;
output [1:0] T2bus;
wire [7:0] NotAbus, NotBbus;
// T1[0] = T1[0]_0, T1[0]_1
// T1[0]_0 = A[7].(A[5]+[6])
// T1[0]_1 = XNOR( A[7], A[6], A[5], A[4])
Invert8 BM0( Abus, NotAbus );
nand2 BM1( .A(NotAbus[6]), .B(NotAbus[5]), .Y(NotA6_5) );
and2 BM2( .A(Abus[7]), .B(NotA6_5), .Y(T1_0_0) );
XOR2a BM3( .A(NotAbus[4]), .B(NotAbus[5]), .Y(XA5_4) ),
BM4( .A(NotAbus[6]), .B(Abus[7]), .Y(NotXA7_6) ),
BM5( .A(XA5_4), .B(NotXA7_6), .Y(T1_0_1) );
Mux2_1 BM6( T1_0_0, T1_0_1, ContInp, T1bus[0] );
// T1[1] = T1[1]_0, T1[1]_1
// T1[1]_0 = !A[7].A[6].(!A[5]+!A[4]).!A[3].!A[2].!A[1].!A[0]
// (check for patterns 8'h40, 8'h50, 8'h60)
// T1[1]_1 = XNOR( B[7], B[6], B[5], B[4])
and3 BM7( .A(NotAbus[3]), .B(NotAbus[2]), .C(NotAbus[1]),
.Y(NotA3_1) );
and2 BM8( .A(NotAbus[0]), .B(NotA3_1), .Y(NotA3_0) );
nand2 BM9( .A(Abus[4]), .B(Abus[5]), .Y(NdA5_4) );
and4 BM10( .A(NotA3_0), .B(NdA5_4), .C(NotAbus[7]),
.D(Abus[6]), .Y(T1_1_0) );
XOR2a BM11( .A(Bbus[4]), .B(Bbus[5]), .Y(XB5_4) ),
BM12( .A(Bbus[7]), .B(Bbus[6]), .Y(XB7_6) ),
BM13( .A(XB5_4), .B(XB7_6), .Y(XB7_4) );
inv BM14( .A(XB7_4), .Y(T1_1_1) );
Mux2_1 BM15( T1_1_0, T1_1_1, ContInp, T1bus[1] );
// T1[2] = XNOR( A[0], A[1], A[2], A[3])
XOR2a BM16( .A(NotAbus[0]), .B(NotAbus[1]), .Y(XA1_0) ),
BM17( .A(NotAbus[2]), .B(NotAbus[3]), .Y(XA3_2) ),
BM18( .A(XA1_0), .B(XA3_2), .Y(XA3_0) );
inv BM19( .A(XA3_0), .Y(T1bus[2]) );
// T1[3] = XNOR( B[0], B[1], B[2], B[3])
XOR2a BM20( .A(Bbus[0]), .B(Bbus[1]), .Y(XB1_0) ),
BM21( .A(Bbus[2]), .B(Bbus[3]), .Y(XB3_2) ),
BM22( .A(XB1_0), .B(XB3_2), .Y(XB3_0) );
inv BM23( .A(XB3_0), .Y(T1bus[3]) );
// T2[0] = A[3]+A[2].A[1]
nand2 BM24( .A(NotAbus[2]), .B(NotAbus[1]), .Y(NotA1_0) );
and2 BM25( .A(Abus[3]), .B(NotA1_0), .Y(T2bus[0]) );
// T2[1] = !(A[3]+A[2]+A[1]+A[0])
and2 BM26( .A(NotAbus[0]), .B(NotA3_1), .Y(T2bus[1]) );
endmodule // LogicBlockM9
/***************************************************************************
* Module 10: MuxModule10
*
* Function: a 3:1 mux with inputs Sbus (from Shifter),
* Hbus (from MuxModule9), and XPbus (from ALU_Core).
*
***************************************************************************/
module MuxModule10( Sbus, Hbus, XPbus, ContIn, Wbus );
input [7:0] Sbus, Hbus, XPbus;
input [13:0] ContIn;
output [7:0] Wbus;
// Mux select inputs:
// ContHi = !(Cont0. Cont1. (!Cont2+Cont7))
// ContLo1= !(!Cont1. !Cont2. !Cont3) = Cont1+Cont2+Cont3
// ContLo2= !(!Cont1. !Cont3) = Cont1+Cont3
inv UM10_0( .A(ContIn[1]), .Y(NotCont1) ),
UM10_1( .A(ContIn[2]), .Y(NotCont2) ),
UM10_2( .A(ContIn[3]), .Y(NotCont3) );
or2 UM10_3( .A(NotCont2), .B(ContIn[7]), .Y(tmp0) );
nand3 UM10_4( .A(ContIn[0]), .B(ContIn[1]), .C(tmp0), .Y(ContHi) );
nand3 UM10_5( .A(NotCont1), .B(NotCont2), .C(NotCont3), .Y(ContLo1) );
nand2 UM10_6( .A(NotCont1), .B(NotCont3), .Y(ContLo2) );
Mux4bit3_1c UM10_7( Sbus[3:0], XPbus[3:0], Hbus[3:0],
ContHi, ContLo1, Wbus[3:0]),
UM10_8( Sbus[7:4], XPbus[7:4], Hbus[7:4],
ContHi, ContLo2, Wbus[7:4]);
endmodule // MuxModule10
/***************************************************************************
* Module 11: MuxModule11
*
* Function: a 3:1 mux with inputs Wbus (from MuxModule10), Funcbus
* (from the XOR of XP and XCarry) and F_BCDbus (from BCD_sub).
*
***************************************************************************/
module MuxModule11( Wbus, Funcbus, F_BCDbus, ContIn, Zbus );
input [7:0] Wbus, Funcbus, F_BCDbus;
input [13:0] ContIn;
output [7:0] Zbus;
// Mux select inputs:
// ContHi = Cont0. !(Cont1. !Cont2. Cont6)
// ContLo = !(Cont0. !Cont1. Cont2. !Cont5)
inv UM11_0( .A(ContIn[1]), .Y(NotCont1) ),
UM11_1( .A(ContIn[2]), .Y(NotCont2) ),
UM11_2( .A(ContIn[5]), .Y(NotCont5) );
nand3 UM11_3( .A(ContIn[1]), .B(NotCont2), .C(ContIn[6]), .Y(tmp0) );
and2 UM11_4( .A(ContIn[0]), .B(tmp0), .Y(ContHi) );
nand4 UM11_5( .A(ContIn[0]), .B(NotCont1), .C(ContIn[2]),
.D(NotCont5), .Y(ContLo) );
Mux8bit3_1c UM11_7( Wbus, Funcbus, F_BCDbus, ContHi, ContLo, Zbus);
endmodule // MuxModule11
/***************************************************************************
* Module 12: Flags
*
* Function: computes some zero flags for Zbus, and parities for Abus,
* Bbus and Zbus.
*
***************************************************************************/
module Flags( Zbus, Abus, Bbus, ContIn, Not_ZeroZ, ZeroZ_Cont,
OddParZ, OddParA, OddParB, OddParZ_Cont );
input [7:0] Zbus, Abus, Bbus;
input [13:0] ContIn;
output Not_ZeroZ, ZeroZ_Cont;
output OddParZ, OddParA, OddParB, OddParZ_Cont;
wire [7:0] Not_Zbus;
Invert8 UM12_0( Zbus, Not_Zbus );
and4 UM12_1( .A(Not_Zbus[0]), .B(Not_Zbus[1]), .C(Not_Zbus[2]),
.D(Not_Zbus[3]), .Y(ZeroZ_Lo) ),
UM12_2( .A(Not_Zbus[4]), .B(Not_Zbus[5]), .C(Not_Zbus[6]),
.D(Not_Zbus[7]), .Y(ZeroZ_Hi) );
and2 UM12_3( .A(ZeroZ_Lo), .B(ZeroZ_Hi), .Y(ZeroZ) );
// Not_ZeroZ= Z0+Z1+...Z7
inv UM12_4( .A(ZeroZ), .Y(Not_ZeroZ) );
// An intermediate control signal: ContFlag = !Cont0+Cont1
inv UM12_5( .A(ContIn[8]), .Y(NotCont8) );
or2 UM12_6( .A(NotCont8), .B(ContIn[9]), .Y(ContFlag) );
inv UM12_7( .A(ContFlag), .Y(NotContFlag) );
// ZeroZ_Cont = !Cont0 + ZeroZ + !Z6.!Z7. !ContFlag
// (Note: ContFlag masks top two bits Z6 and Z7 for ZeroZ_Cont)
and3 UM12_8( .A(Not_Zbus[6]), .B(Not_Zbus[7]), .C(NotContFlag), .Y(tmp0) );
nor2 UM12_9( .A(tmp0), .B(ZeroZ), .Y(tmp1) );
nand2 UM12_10( .A(ContIn[8]), .B(tmp1), .Y(ZeroZ_Cont) );
// OddParA = Xnor(A0,A1,...,A7)
// OddParB = Xnor(B0,B1,...,B7)
// OddParZ = Xnor(Z0,Z1,...,Z7)
// OddParZ_Cont = Xnor(Z0,Z1,..,Z5,ContFlag.Z6,ContFlag.Z7, Cont13.!ContFlag)
// (Note: ContFlag masks top two bits Z6 and Z7 for OddParZ_Cont)
ParityTree8bit UM12_11( Abus, EvenParA ),
UM12_12( Bbus, EvenParB ),
UM12_13( Zbus, EvenParZ );
and2 UM12_14( .A(NotContFlag), .B(ContIn[13]), .Y(ContPar) ),
UM12_15( .A(ContFlag), .B(Zbus[7]), .Y(PZ7) ),
UM12_16( .A(ContFlag), .B(Zbus[6]), .Y(PZ6) );
ParityTree9bit UM12_17( {ContPar,PZ7,PZ6,Zbus[5:0]}, EvenParZ_Cont );
inv UM12_18( .A(EvenParA), .Y(OddParA) ),
UM12_19( .A(EvenParB), .Y(OddParB) ),
UM12_20( .A(EvenParZ), .Y(OddParZ) ),
UM12_21( .A(EvenParZ_Cont), .Y(OddParZ_Cont) );
endmodule // Flags
/***************************************************************************
* Module 13: MiscLogic
*
* Function: miscellaneous logic with 3:1 muxes
*
***************************************************************************/
module MiscLogic( Abus, Bbus, Carry4, Overflow, ContIn, MiscOuts );
input [7:0] Abus, Bbus;
input Carry4, Overflow;
input [13:0] ContIn;
output [4:0] MiscOuts;
wire [7:0] Not_Abus;
wire Misc0_0, Misc0_1, Misc0_2,
Misc1_0, Misc1_1, Misc1_2,
Misc2_0, Misc2_1, Misc2_2;
wire ContHi_Misc0, ContLo_Misc0,
ContHi_Misc1, ContLo_Misc1,
ContHi_Misc2, ContLo_Misc2;
Invert8 UM13_0( Abus, Not_Abus );
//---------------------------
// Misc_0 = (A5 xor A6).A4.A7 + A5.!A7
XOR2a UM13_1( .A(Abus[5]), .B(Abus[6]), .Y(tmp0) );
and3 UM13_2( .A(tmp0), .B(Abus[4]), .C(Abus[7]), .Y(tmp1) );
and2 UM13_3( .A(Abus[5]), .B(Not_Abus[7]), .Y(tmp2) );
or2 UM13_4( .A(tmp1), .B(tmp2), .Y(Misc0_0) );
// Misc0_1 = A0. (A1 xor A2)
XOR2a UM13_5( .A(Abus[1]), .B(Abus[2]), .Y(tmp3) );
and2 UM13_6( .A(Abus[0]), .B(tmp3), .Y(Misc0_1) );
assign Misc0_2 = Overflow;
inv UM13_7( .A(ContIn[1]), .Y(NotCont1) ),
UM13_8( .A(ContIn[5]), .Y(NotCont5) );
nand2 UM13_9( .A(ContIn[0]), .B(NotCont1), .Y(ContHi_Misc0) );
nand3 UM13_10( .A(ContIn[0]), .B(ContIn[1]), .C(ContIn[2]),
.Y(ContLo_Misc0) );
Mux3_1c UM13_11( Misc0_0, Misc0_1, Misc0_2,
ContHi_Misc0, ContLo_Misc0, MiscOuts[0] );
//---------------------------
// Misc1_0 = A7.(A5+A6)
or2 UM13_12( .A(Abus[5]), .B(Abus[6]), .Y(tmp4) );
and2 UM13_13( .A(Abus[7]), .B(tmp4), .Y(Misc1_0) );
assign Misc1_1 = Carry4;
// Misc1_2 = !A0.!A1.!A2.!A3
and4 UM13_14( .A(Not_Abus[0]), .B(Not_Abus[1]), .C(Not_Abus[2]),
.D(Not_Abus[3]), .Y(Misc1_2) );
nand4 UM13_27( .A(ContIn[0]), .B(NotCont1), .C(ContIn[2]),
.D(NotCont5), .Y(ContHi_Misc1) );
assign ContLo_Misc1 = ContIn[0];
Mux3_1c UM13_28( Misc1_0, Misc1_1, Misc1_2,
ContHi_Misc1, ContLo_Misc1, MiscOuts[1] );
//---------------------------
assign Misc2_0 = Misc1_0;
// Misc2_1 = B3.(B1+B2)
or2 UM13_29( .A(Bbus[1]), .B(Bbus[2]), .Y(tmp5) );
and2 UM13_30( .A(Bbus[3]), .B(tmp5), .Y(Misc2_1) );
// Misc2_2 = A0.B0+A1.B1+...+A7.B7
nand2 UM13_31( .A(Abus[0]), .B(Bbus[0]), .Y(pr0) ),
UM13_32( .A(Abus[1]), .B(Bbus[1]), .Y(pr1) ),
UM13_33( .A(Abus[2]), .B(Bbus[2]), .Y(pr2) ),
UM13_34( .A(Abus[3]), .B(Bbus[3]), .Y(pr3) ),
UM13_35( .A(Abus[4]), .B(Bbus[4]), .Y(pr4) ),
UM13_36( .A(Abus[5]), .B(Bbus[5]), .Y(pr5) ),
UM13_37( .A(Abus[6]), .B(Bbus[6]), .Y(pr6) ),
UM13_38( .A(Abus[7]), .B(Bbus[7]), .Y(pr7) );
and4 UM13_39( .A(pr0), .B(pr1), .C(pr2), .D(pr3), .Y(pr3_0) ),
UM13_40( .A(pr4), .B(pr5), .C(pr6), .D(pr7), .Y(pr7_4) );
nand2 UM13_41( .A(pr3_0), .B(pr7_4), .Y(Misc2_2) );
assign ContHi_Misc2 = ContLo_Misc0;
nand3 UM13_42( .A(ContIn[0]), .B(NotCont1), .C(ContIn[2]),
.Y(ContLo_Misc2) );
Mux3_1c UM13_43( Misc2_0, Misc2_1, Misc2_2,
ContHi_Misc2, ContLo_Misc2, NotMiscOuts2 );
inv UM13_43_1( .A(NotMiscOuts2), .Y(MiscOuts[2]) );
//---------------------------
// MiscOuts[3] = !(A3.(A2+A1))
or2 UM13_44( .A(Abus[1]), .B(Abus[2]), .Y(tmp6) );
and2 UM13_45( .A(Abus[3]), .B(tmp6), .Y(tmp7) );
inv UM13_46( .A(tmp7), .Y(MiscOuts[3]) );
// MiscOuts[4] = !A4.!A5. !A6. !A7
and4 UM13_47( .A(Not_Abus[4]), .B(Not_Abus[5]), .C(Not_Abus[6]),
.D(Not_Abus[7]), .Y(MiscOuts[4]) );
endmodule // MiscLogic
/***************************************************************************
* Definition of non-standard multiplexers of c3540
***************************************************************************/
module Mux8bit3_1a( In0, In1, In2, ContHi, ContLo, Out );
input [7:0] In0, In1, In2;
input ContHi, ContLo;
output [7:0] Out;
Mux3_1a M8b3a_0( In0[0], In1[0], In2[0], ContHi, ContLo, Out[0] ),
M8b3a_1( In0[1], In1[1], In2[1], ContHi, ContLo, Out[1] ),
M8b3a_2( In0[2], In1[2], In2[2], ContHi, ContLo, Out[2] ),
M8b3a_3( In0[3], In1[3], In2[3], ContHi, ContLo, Out[3] ),
M8b3a_4( In0[4], In1[4], In2[4], ContHi, ContLo, Out[4] ),
M8b3a_5( In0[5], In1[5], In2[5], ContHi, ContLo, Out[5] ),
M8b3a_6( In0[6], In1[6], In2[6], ContHi, ContLo, Out[6] ),
M8b3a_7( In0[7], In1[7], In2[7], ContHi, ContLo, Out[7] );
endmodule // Mux8bit3_1a
/********************************************
* Module: Mux3_1a
*
* Function:
* ContLo: 0 1 0 1
* ContHi: 0 0 1 1
* Out : In0 In1 In2 In2
*
********************************************/
module Mux3_1a( In0, In1, In2, ContHi, ContLo, Out );
input In0, In1, In2, ContHi, ContLo;
output Out;
// the structure reflects the gate-level description
or2 Mux3a_0( .A(ContHi), .B(ContLo), .Y(ContOr) );
inv Mux3a_1( .A(ContHi), .Y(NotContHi) ),
Mux3a_2( .A(ContOr), .Y(Cont00) );
and2 Mux3a_3( .A(NotContHi), .B(ContOr), .Y(Cont01) );
and2 Mux3a_4( .A(In0), .B(Cont00), .Y(line4) ),
Mux3a_5( .A(In1), .B(Cont01), .Y(line5) ),
Mux3a_6( .A(In2), .B(ContHi), .Y(line6) );
or3 Mux3a_7( .A(line4), .B(line5), .C(line6), .Y(Out) );
endmodule // Mux3_1a
/********************************************/
module Mux4bit3_1b( In0, In1, In2, ContHi, ContLo, Out );
input [3:0] In0, In1, In2;
input ContHi, ContLo;
output [3:0] Out;
Mux3_1b M4b3b_0( In0[0], In1[0], In2[0], ContHi, ContLo, Out[0] ),
M4b3b_1( In0[1], In1[1], In2[1], ContHi, ContLo, Out[1] ),
M4b3b_2( In0[2], In1[2], In2[2], ContHi, ContLo, Out[2] ),
M4b3b_3( In0[3], In1[3], In2[3], ContHi, ContLo, Out[3] );
endmodule // Mux4bit3_1b
/****************************************************
* Module: Mux3_1b
*
* Function:
* ContLo: 0 1 0 1
* ContHi: 0 0 1 1
* Out : In0 In1 In2 +
*
* (+: not possible--guaranteed by ContHi and ContLo)
*****************************************************/
module Mux3_1b( In0, In1, In2, ContHi, ContLo, Out );
input In0, In1, In2, ContHi, ContLo;
output Out;
// the structure reflects the gate-level description
inv Mux3b_0( .A(ContHi), .Y(NotContHi) ),
Mux3b_1( .A(ContLo), .Y(NotContLo) );
and3 Mux3b_2( .A(In0), .B(NotContHi), .C(NotContLo), .Y(line2) ),
Mux3b_3( .A(In1), .B(NotContHi), .C(ContLo), .Y(line3) );
and2 Mux3b_4( .A(In2), .B(ContHi), .Y(line4) );
or3 Mux3b_5( .A(line2), .B(line3), .C(line4), .Y(Out) );
endmodule // Mux3_1b
/********************************************/
module Mux8bit3_1c( In0, In1, In2, ContHi, ContLo, Out );
input [7:0] In0, In1, In2;
input ContHi, ContLo;
output [7:0] Out;
Mux4bit3_1c M8b3c_0( In0[3:0], In1[3:0], In2[3:0],
ContHi, ContLo, Out[3:0] ),
M8b3c_1( In0[7:4], In1[7:4], In2[7:4],
ContHi, ContLo, Out[7:4] );
endmodule // Mux8bit3_1c
/********************************************/
module Mux4bit3_1c( In0, In1, In2, ContHi, ContLo, Out );
input [3:0] In0, In1, In2;
input ContHi, ContLo;
output [3:0] Out;
Mux3_1c M4b3c_0( In0[0], In1[0], In2[0], ContHi, ContLo, Out[0] ),
M4b3c_1( In0[1], In1[1], In2[1], ContHi, ContLo, Out[1] ),
M4b3c_2( In0[2], In1[2], In2[2], ContHi, ContLo, Out[2] ),
M4b3c_3( In0[3], In1[3], In2[3], ContHi, ContLo, Out[3] );
endmodule // Mux4bit3_1c
/****************************************************
* Module: Mux3_1c
*
* Function:
* ContLo: 0 1 0 1
* ContHi: 0 0 1 1
* Out : + In0 In1 In2
*
* (+: not possible--guaranteed by ContHi and ContLo)
*****************************************************/
module Mux3_1c( In0, In1, In2, ContHi, ContLo, Out );
input In0, In1, In2, ContHi, ContLo;
output Out;
// the structure reflects the gate-level description
inv Mux3c_0( .A(ContHi), .Y(NotContHi) ),
Mux3c_1( .A(ContLo), .Y(NotContLo) );
and2 Mux3c_2( .A(In0), .B(NotContHi), .Y(line2) ),
Mux3c_3( .A(In1), .B(NotContLo), .Y(line3) ),
Mux3c_4( .A(ContHi), .B(ContLo), .Y(line4) ),
Mux3c_5( .A(line4), .B(In2), .Y(line5) );
or3 Mux3c_6( .A(line2), .B(line3), .C(line5), .Y(Out) );
endmodule // Mux3_1c
/****************************************************/
module Mux4bit4_1a( In0, In1, In2, In3, Sel, Out );
input [3:0] In0, In1, In2, In3;
input [3:0] Sel;
output [3:0] Out;
Mux4_1a M4b4a_0( In0[0], In1[0], In2[0], In3[0], Sel[3:0], Out[0] ),
M4b4a_1( In0[1], In1[1], In2[1], In3[1], Sel[3:0], Out[1] ),
M4b4a_2( In0[2], In1[2], In2[2], In3[2], Sel[3:0], Out[2] ),
M4b4a_3( In0[3], In1[3], In2[3], In3[3], Sel[3:0], Out[3] );
endmodule // Mux4_1a
/****************************************************
* Module: Mux4_1a
*
* Function:
* Sel: 0 1 2 3
* Out: In0 In1 In2 In3
*****************************************************/
module Mux4_1a( In0, In1, In2, In3, Sel, Out );
input In0, In1, In2, In3;
input [3:0] Sel;
output Out;
and2 Mux4a_0( .A(In0), .B(Sel[0]), .Y(line0) ),
Mux4a_1( .A(In1), .B(Sel[1]), .Y(line1) ),
Mux4a_2( .A(In2), .B(Sel[2]), .Y(line2) ),
Mux4a_3( .A(In3), .B(Sel[3]), .Y(line3) );
or4 Mux4a_4( .A(line0), .B(line1), .C(line2), .D(line3), .Y(Out) );
endmodule // Mux4_1a
/******************************************************/
module Mux8bit8_1( In0, In1, In2, In3, In4, In5, In6, In7,
Sel, Out );
input [7:0] In0, In1, In2, In3, In4, In5, In6, In7;
input [7:0] Sel;
output [7:0] Out;
Mux8_1 M8_0( In0[0], In1[0], In2[0], In3[0],
In4[0], In5[0], In6[0], In7[0], Sel, Out[0] ),
M8_1( In0[1], In1[1], In2[1], In3[1],
In4[1], In5[1], In6[1], In7[1], Sel, Out[1] ),
M8_2( In0[2], In1[2], In2[2], In3[2],
In4[2], In5[2], In6[2], In7[2], Sel, Out[2] ),
M8_3( In0[3], In1[3], In2[3], In3[3],
In4[3], In5[3], In6[3], In7[3], Sel, Out[3] ),
M8_4( In0[4], In1[4], In2[4], In3[4],
In4[4], In5[4], In6[4], In7[4], Sel, Out[4] ),
M8_5( In0[5], In1[5], In2[5], In3[5],
In4[5], In5[5], In6[5], In7[5], Sel, Out[5] ),
M8_6( In0[6], In1[6], In2[6], In3[6],
In4[6], In5[6], In6[6], In7[6], Sel, Out[6] ),
M8_7( In0[7], In1[7], In2[7], In3[7],
In4[7], In5[7], In6[7], In7[7], Sel, Out[7] );
endmodule // Mux8bit8_1
/******************************************************/
module Mux8_1( In0, In1, In2, In3, In4, In5, In6, In7,
Sel, Out );
input In0, In1, In2, In3, In4, In5, In6, In7;
input [7:0] Sel;
output Out;
and2 M0( .A(In0), .B(Sel[0]), .Y(t0) ),
M1( .A(In1), .B(Sel[1]), .Y(t1) ),
M2( .A(In2), .B(Sel[2]), .Y(t2) ),
M3( .A(In3), .B(Sel[3]), .Y(t3) ),
M4( .A(In4), .B(Sel[4]), .Y(t4) ),
M5( .A(In5), .B(Sel[5]), .Y(t5) ),
M6( .A(In6), .B(Sel[6]), .Y(t6) ),
M7( .A(In7), .B(Sel[7]), .Y(t7) );
or8 M8( .A(t0), .B(t1), .C(t2), .D(t3), .E(t4),
.F(t5), .G(t6), .H(t7), .Y(Out) );
endmodule // Mux8_1
/***************************************************************************
* Description of some basic gates/modules
***************************************************************************/
module ParityTree8bit( Inbus, ParOut );
input [7:0] Inbus;
output ParOut;
XOR2a PT1( .A(Inbus[0]), .B(Inbus[1]), .Y(line1) ),
PT2( .A(Inbus[2]), .B(Inbus[3]), .Y(line2) ),
PT3( .A(Inbus[4]), .B(Inbus[5]), .Y(line3) ),
PT4( .A(Inbus[6]), .B(Inbus[7]), .Y(line4) ),
PT5( .A(line1), .B(line2), .Y(line5) ),
PT6( .A(line3), .B(line4), .Y(line6) ),
PT7( .A(line5), .B(line6), .Y(ParOut) );
endmodule // ParityTree8bit
/********************************************/
module ParityTree9bit( Inbus, ParOut );
input [8:0] Inbus;
output ParOut;
XOR2a PT1( .A(Inbus[0]), .B(Inbus[1]), .Y(line1) ),
PT2( .A(Inbus[2]), .B(Inbus[3]), .Y(line2) ),
PT3( .A(Inbus[4]), .B(Inbus[5]), .Y(line3) ),
PT4( .A(Inbus[6]), .B(Inbus[7]), .Y(line4) ),
PT5( .A(line1), .B(line2), .Y(line5) );
XOR3a PT6( .A(line3), .B(line4), .C(Inbus[8]), .Y(line6) );
XOR2a PT7( .A(line5), .B(line6), .Y(ParOut) );
endmodule // ParityTree9bit
/********************************************/
module Invert4( Inbus, Outbus );
input [3:0] Inbus;
output [3:0] Outbus;
inv Inv4_0( .A(Inbus[0]), .Y(Outbus[0]) ),
Inv4_1( .A(Inbus[1]), .Y(Outbus[1]) ),
Inv4_2( .A(Inbus[2]), .Y(Outbus[2]) ),
Inv4_3( .A(Inbus[3]), .Y(Outbus[3]) );
endmodule // Invert4
/********************************************/
module Invert8( Inbus, Outbus );
input [7:0] Inbus;
output [7:0] Outbus;
Invert4 Inv8_0( Inbus[3:0], Outbus[3:0] ),
Inv8_1( Inbus[7:4], Outbus[7:4] );
endmodule // Invert8
/********************************************/
module XOR8bit( In1bus, In2bus, Outbus );
input [7:0] In1bus, In2bus;
output [7:0] Outbus;
XOR4bit X8_0( In1bus[3:0], In2bus[3:0], Outbus[3:0] ),
X8_1( In1bus[7:4], In2bus[7:4], Outbus[7:4] );
endmodule // XOR8bit
/********************************************/
module XOR4bit( In1bus, In2bus, Outbus );
input [3:0] In1bus, In2bus;
output [3:0] Outbus;
XOR2a X4_0( .A(In1bus[0]), .B(In2bus[0]), .Y(Outbus[0]) ),
X4_1( .A(In1bus[1]), .B(In2bus[1]), .Y(Outbus[1]) ),
X4_2( .A(In1bus[2]), .B(In2bus[2]), .Y(Outbus[2]) ),
X4_3( .A(In1bus[3]), .B(In2bus[3]), .Y(Outbus[3]) );
endmodule // XOR4bit
/********************************************/
module Mux2_1( In0, In1, ContIn, Out );
input In0, In1, ContIn;
output Out;
inv Mux2_0( .A(ContIn), .Y(Not_ContIn) );
and2 Mux2_1( .A(In0), .B(Not_ContIn), .Y(line1) ),
Mux2_2( .A(In1), .B(ContIn), .Y(line2) );
or2 Mux2_3( .A(line1), .B(line2), .Y(Out) );
endmodule // Mux2_1
/******************************************************/
module AND_OR2( O, P, Q, Y);
input O, P, Q;
output Y;
and2 Ao2_0( .A(P), .B(Q), .Y(line0) );
or2 Ao2_1( .A(O), .B(line0), .Y(Y) );
endmodule // AND_OR2
/******************************************************/
module AND_OR3a( O, P, Q, R, S, Y);
input O, P, Q, R, S;
output Y;
and2 Ao3a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao3a_1( .A(P), .B(R), .C(S), .Y(line1) );
or3 Ao3a_2( .A(O), .B(line0), .C(line1), .Y(Y) );
endmodule // AND_OR3a
/******************************************************/
module AND_OR3b( O, P, Q, R, Y);
input O, P, Q, R;
output Y;
and2 Ao3a_0( .A(P), .B(Q), .Y(line0) );
and2 Ao3a_1( .A(P), .B(R), .Y(line1) );
or3 Ao3a_2( .A(O), .B(line0), .C(line1), .Y(Y) );
endmodule // AND_OR3b
/******************************************************/
module AND_OR4a( O, P, Q, R, S, T, U, Y);
input O, P, Q, R, S, T, U;
output Y;
and2 Ao4a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao4a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao4a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
or4 Ao4a_3( .A(O), .B(line0), .C(line1), .D(line2), .Y(Y) );
endmodule // AND_OR4a
/******************************************************/
module AND_OR4b( O, P, Q, R, S, T, Y);
input O, P, Q, R, S, T;
output Y;
and2 Ao4a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao4a_1( .A(P), .B(R), .C(S), .Y(line1) );
and3 Ao4a_2( .A(P), .B(R), .C(T), .Y(line2) );
or4 Ao4a_3( .A(O), .B(line0), .C(line1), .D(line2), .Y(Y) );
endmodule // AND_OR4a
/******************************************************/
module AND_OR5a( O, P, Q, R, S, T, U, V, W, Y);
input O, P, Q, R, S, T, U, V, W;
output Y;
and2 Ao5a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao5a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao5a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
and5 Ao5a_3( .A(P), .B(R), .C(T), .D(V), .E(W), .Y(line3) );
or5 Ao5a_4( .A(O), .B(line0), .C(line1), .D(line2), .E(line3), .Y(Y) );
endmodule // AND_OR5a
/******************************************************/
module AND_OR5b( O, P, Q, R, S, T, U, V, Y);
input O, P, Q, R, S, T, U, V;
output Y;
and2 Ao5a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao5a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao5a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
and4 Ao5a_3( .A(P), .B(R), .C(T), .D(V), .Y(line3) );
or5 Ao5a_4( .A(O), .B(line0), .C(line1), .D(line2), .E(line3), .Y(Y) );
endmodule // AND_OR5b
/******************************************************/
module AND_OR6a( O, P, Q, R, S, T, U, V, W, X, XX, Y);
input O, P, Q, R, S, T, U, V, W, X, XX;
output Y;
and2 Ao6a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao6a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao6a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
and5 Ao6a_3( .A(P), .B(R), .C(T), .D(V), .E(W), .Y(line3) );
and6 Ao6a_4( .A(P), .B(R), .C(T), .D(V), .E(X), .F(XX), .Y(line4) );
or6 Ao6a_5( .A(O), .B(line0), .C(line1), .D(line2), .E(line3),
.F(line4), .Y(Y) );
endmodule // AND_OR6a
/******************************************************/
module AND_OR6b( O, P, Q, R, S, T, U, V, W, X, Y);
input O, P, Q, R, S, T, U, V, W, X;
output Y;
and2 Ao6a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao6a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao6a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
and5 Ao6a_3( .A(P), .B(R), .C(T), .D(V), .E(W), .Y(line3) );
and5 Ao6a_4( .A(P), .B(R), .C(T), .D(V), .E(X), .Y(line4) );
or6 Ao6a_5( .A(O), .B(line0), .C(line1), .D(line2), .E(line3),
.F(line4), .Y(Y) );
endmodule // AND_OR6b
/******************************************************/
module XOR2a ( A, B, Y);
input A, B;
output Y;
inv Xo0( .A(A), .Y(NotA) ),
Xo1( .A(B), .Y(NotB) );
nand2 Xo2( .A(NotA), .B(B), .Y(line2) ),
Xo3( .A(NotB), .B(A), .Y(line3) ),
Xo4( .A(line2), .B(line3), .Y(Y) );
endmodule // XOR2a
/********************************************/
module XOR3a( A, B, C, Y);
input A, B, C;
output Y;
inv Xo3_0( .A(A), .Y(NotA) ),
Xo3_1( .A(B), .Y(NotB) ),
Xo3_2( .A(C), .Y(NotC) );
and3 Xo3_3( .A(NotA), .B(NotB), .C(C), .Y(line3) ),
Xo3_4( .A(NotA), .B(B), .C(NotC), .Y(line4) ),
Xo3_5( .A(A), .B(NotB), .C(NotC), .Y(line5) ),
Xo3_6( .A(A), .B(B), .C(C), .Y(line6) );
nor2 Xo3_7( .A(line3), .B(line4), .Y(line7) ),
Xo3_8( .A(line5), .B(line6), .Y(line8) );
nand2 Xo3_9( .A(line7), .B(line8), .Y(Y) );
endmodule // XOR3a
|
Added c3540/flat3540.v.
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1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 | /**************************************************************************** * * * FLAT VERSION of HIGH-LEVEL MODEL for c3540 * * * * * * Generated by: Hakan Yalcin (hyalcin@cadence.com) * * Verified by: Jonathan David Hauke (jhauke@eecs.umich.edu) * * * * Oct 20, 1998 * * * ****************************************************************************/ // Flat Verilog File module c3540g ( in50, in58, in68, in77, in87, in97, in107, in116, in226, in232, in238, in244, in250, in257, in264, in270, in124, in125, in128, in132, in137, in143, in150, in159, in283, in294, in303, in311, in317, in322, in326, in329, in222, in223, in330, in274, in2897, in200, in190, in179, in343, in213, in169, in45, in41, in1698, in33, in20, in13, in1, out375, out378, out381, out384, out387, out390, out393, out396, out407, out409, out402, out351, out358, out405, out399, out369, out372, out353, out355, out361, out364, out367); input in50, in58, in68, in77, in87, in97, in107, in116, in226, in232, in238, in244, in250, in257, in264, in270, in124, in125, in128, in132, in137, in143, in150, in159, in283, in294, in303, in311, in317, in322, in326, in329, in222, in223, in330, in274, in2897, in200, in190, in179, in343, in213, in169, in45, in41, in1698, in33, in20, in13, in1; output out375, out378, out381, out384, out387, out390, out393, out396, out407, out409, out402, out351, out358, out405, out399, out369, out372, out353, out355, out361, out364, out367; inv M1_UM1_0_BaD0(in107, A_BCDbus_1); inv M1_UM1_0_BaD1_Xo0(in97, M1_UM1_0_BaD1_NotA); inv M1_UM1_0_BaD1_Xo1(in107, M1_UM1_0_BaD1_NotB); nand2 M1_UM1_0_BaD1_Xo2(M1_UM1_0_BaD1_NotA, in107, M1_UM1_0_BaD1_line2); nand2 M1_UM1_0_BaD1_Xo3(M1_UM1_0_BaD1_NotB, in97, M1_UM1_0_BaD1_line3); nand2 M1_UM1_0_BaD1_Xo4(M1_UM1_0_BaD1_line2, M1_UM1_0_BaD1_line3, M1_UM1_0_line1); inv M1_UM1_0_BaD2(M1_UM1_0_line1, A_BCDbus_2); inv M1_UM1_0_BaD3(in97, M1_UM1_0_line3); inv M1_UM1_0_BaD4(in87, M1_UM1_0_line4); nand3 M1_UM1_0_BaD5(A_BCDbus_1, M1_UM1_0_line3, M1_UM1_0_line4, A_BCDbus_3); inv M1_UM1_1_BaD0(in68, A_BCDbus_5); inv M1_UM1_1_BaD1_Xo0(in58, M1_UM1_1_BaD1_NotA); inv M1_UM1_1_BaD1_Xo1(in68, M1_UM1_1_BaD1_NotB); nand2 M1_UM1_1_BaD1_Xo2(M1_UM1_1_BaD1_NotA, in68, M1_UM1_1_BaD1_line2); nand2 M1_UM1_1_BaD1_Xo3(M1_UM1_1_BaD1_NotB, in58, M1_UM1_1_BaD1_line3); nand2 M1_UM1_1_BaD1_Xo4(M1_UM1_1_BaD1_line2, M1_UM1_1_BaD1_line3, M1_UM1_1_line1); inv M1_UM1_1_BaD2(M1_UM1_1_line1, A_BCDbus_6); inv M1_UM1_1_BaD3(in58, M1_UM1_1_line3); inv M1_UM1_1_BaD4(in50, M1_UM1_1_line4); nand3 M1_UM1_1_BaD5(A_BCDbus_5, M1_UM1_1_line3, M1_UM1_1_line4, A_BCDbus_7); inv M2_Inv8_0_Inv4_0(in116, Not_Abus_0); inv M2_Inv8_0_Inv4_1(in107, Not_Abus_1); inv M2_Inv8_0_Inv4_2(in97, Not_Abus_2); inv M2_Inv8_0_Inv4_3(in87, Not_Abus_3); inv M2_Inv8_1_Inv4_0(in77, Not_Abus_4); inv M2_Inv8_1_Inv4_1(in68, Not_Abus_5); inv M2_Inv8_1_Inv4_2(in58, Not_Abus_6); inv M2_Inv8_1_Inv4_3(in50, Not_Abus_7); or2 M3_UM3_0_M8b3a_0_Mux3a_0(in20, in33, M3_UM3_0_M8b3a_0_ContOr); inv M3_UM3_0_M8b3a_0_Mux3a_1(in20, M3_UM3_0_M8b3a_0_NotContHi); inv M3_UM3_0_M8b3a_0_Mux3a_2(M3_UM3_0_M8b3a_0_ContOr, M3_UM3_0_M8b3a_0_Cont00); and2 M3_UM3_0_M8b3a_0_Mux3a_3(M3_UM3_0_M8b3a_0_NotContHi, M3_UM3_0_M8b3a_0_ContOr, M3_UM3_0_M8b3a_0_Cont01); and2 M3_UM3_0_M8b3a_0_Mux3a_4(in97, M3_UM3_0_M8b3a_0_Cont00, M3_UM3_0_M8b3a_0_line4); and2 M3_UM3_0_M8b3a_0_Mux3a_5(in283, M3_UM3_0_M8b3a_0_Cont01, M3_UM3_0_M8b3a_0_line5); and2 M3_UM3_0_M8b3a_0_Mux3a_6(in116, in20, M3_UM3_0_M8b3a_0_line6); or3 M3_UM3_0_M8b3a_0_Mux3a_7(M3_UM3_0_M8b3a_0_line4, M3_UM3_0_M8b3a_0_line5, M3_UM3_0_M8b3a_0_line6, M3_temp_0); or2 M3_UM3_0_M8b3a_1_Mux3a_0(in20, in33, M3_UM3_0_M8b3a_1_ContOr); inv M3_UM3_0_M8b3a_1_Mux3a_1(in20, M3_UM3_0_M8b3a_1_NotContHi); inv M3_UM3_0_M8b3a_1_Mux3a_2(M3_UM3_0_M8b3a_1_ContOr, M3_UM3_0_M8b3a_1_Cont00); and2 M3_UM3_0_M8b3a_1_Mux3a_3(M3_UM3_0_M8b3a_1_NotContHi, M3_UM3_0_M8b3a_1_ContOr, M3_UM3_0_M8b3a_1_Cont01); and2 M3_UM3_0_M8b3a_1_Mux3a_4(in87, M3_UM3_0_M8b3a_1_Cont00, M3_UM3_0_M8b3a_1_line4); and2 M3_UM3_0_M8b3a_1_Mux3a_5(in116, M3_UM3_0_M8b3a_1_Cont01, M3_UM3_0_M8b3a_1_line5); and2 M3_UM3_0_M8b3a_1_Mux3a_6(A_BCDbus_1, in20, M3_UM3_0_M8b3a_1_line6); or3 M3_UM3_0_M8b3a_1_Mux3a_7(M3_UM3_0_M8b3a_1_line4, M3_UM3_0_M8b3a_1_line5, M3_UM3_0_M8b3a_1_line6, M3_temp_1); or2 M3_UM3_0_M8b3a_2_Mux3a_0(in20, in33, M3_UM3_0_M8b3a_2_ContOr); inv M3_UM3_0_M8b3a_2_Mux3a_1(in20, M3_UM3_0_M8b3a_2_NotContHi); inv M3_UM3_0_M8b3a_2_Mux3a_2(M3_UM3_0_M8b3a_2_ContOr, M3_UM3_0_M8b3a_2_Cont00); and2 M3_UM3_0_M8b3a_2_Mux3a_3(M3_UM3_0_M8b3a_2_NotContHi, M3_UM3_0_M8b3a_2_ContOr, M3_UM3_0_M8b3a_2_Cont01); and2 M3_UM3_0_M8b3a_2_Mux3a_4(in77, M3_UM3_0_M8b3a_2_Cont00, M3_UM3_0_M8b3a_2_line4); and2 M3_UM3_0_M8b3a_2_Mux3a_5(in107, M3_UM3_0_M8b3a_2_Cont01, M3_UM3_0_M8b3a_2_line5); and2 M3_UM3_0_M8b3a_2_Mux3a_6(A_BCDbus_2, in20, M3_UM3_0_M8b3a_2_line6); or3 M3_UM3_0_M8b3a_2_Mux3a_7(M3_UM3_0_M8b3a_2_line4, M3_UM3_0_M8b3a_2_line5, M3_UM3_0_M8b3a_2_line6, M3_temp_2); or2 M3_UM3_0_M8b3a_3_Mux3a_0(in20, in33, M3_UM3_0_M8b3a_3_ContOr); inv M3_UM3_0_M8b3a_3_Mux3a_1(in20, M3_UM3_0_M8b3a_3_NotContHi); inv M3_UM3_0_M8b3a_3_Mux3a_2(M3_UM3_0_M8b3a_3_ContOr, M3_UM3_0_M8b3a_3_Cont00); and2 M3_UM3_0_M8b3a_3_Mux3a_3(M3_UM3_0_M8b3a_3_NotContHi, M3_UM3_0_M8b3a_3_ContOr, M3_UM3_0_M8b3a_3_Cont01); and2 M3_UM3_0_M8b3a_3_Mux3a_4(in68, M3_UM3_0_M8b3a_3_Cont00, M3_UM3_0_M8b3a_3_line4); and2 M3_UM3_0_M8b3a_3_Mux3a_5(in97, M3_UM3_0_M8b3a_3_Cont01, M3_UM3_0_M8b3a_3_line5); and2 M3_UM3_0_M8b3a_3_Mux3a_6(A_BCDbus_3, in20, M3_UM3_0_M8b3a_3_line6); or3 M3_UM3_0_M8b3a_3_Mux3a_7(M3_UM3_0_M8b3a_3_line4, M3_UM3_0_M8b3a_3_line5, M3_UM3_0_M8b3a_3_line6, M3_temp_3); or2 M3_UM3_0_M8b3a_4_Mux3a_0(in20, in33, M3_UM3_0_M8b3a_4_ContOr); inv M3_UM3_0_M8b3a_4_Mux3a_1(in20, M3_UM3_0_M8b3a_4_NotContHi); inv M3_UM3_0_M8b3a_4_Mux3a_2(M3_UM3_0_M8b3a_4_ContOr, M3_UM3_0_M8b3a_4_Cont00); and2 M3_UM3_0_M8b3a_4_Mux3a_3(M3_UM3_0_M8b3a_4_NotContHi, M3_UM3_0_M8b3a_4_ContOr, M3_UM3_0_M8b3a_4_Cont01); and2 M3_UM3_0_M8b3a_4_Mux3a_4(in58, M3_UM3_0_M8b3a_4_Cont00, M3_UM3_0_M8b3a_4_line4); and2 M3_UM3_0_M8b3a_4_Mux3a_5(in87, M3_UM3_0_M8b3a_4_Cont01, M3_UM3_0_M8b3a_4_line5); and2 M3_UM3_0_M8b3a_4_Mux3a_6(in77, in20, M3_UM3_0_M8b3a_4_line6); or3 M3_UM3_0_M8b3a_4_Mux3a_7(M3_UM3_0_M8b3a_4_line4, M3_UM3_0_M8b3a_4_line5, M3_UM3_0_M8b3a_4_line6, M3_temp_4); or2 M3_UM3_0_M8b3a_5_Mux3a_0(in20, in33, M3_UM3_0_M8b3a_5_ContOr); inv M3_UM3_0_M8b3a_5_Mux3a_1(in20, M3_UM3_0_M8b3a_5_NotContHi); inv M3_UM3_0_M8b3a_5_Mux3a_2(M3_UM3_0_M8b3a_5_ContOr, M3_UM3_0_M8b3a_5_Cont00); and2 M3_UM3_0_M8b3a_5_Mux3a_3(M3_UM3_0_M8b3a_5_NotContHi, M3_UM3_0_M8b3a_5_ContOr, M3_UM3_0_M8b3a_5_Cont01); and2 M3_UM3_0_M8b3a_5_Mux3a_4(in50, M3_UM3_0_M8b3a_5_Cont00, M3_UM3_0_M8b3a_5_line4); and2 M3_UM3_0_M8b3a_5_Mux3a_5(in77, M3_UM3_0_M8b3a_5_Cont01, M3_UM3_0_M8b3a_5_line5); and2 M3_UM3_0_M8b3a_5_Mux3a_6(A_BCDbus_5, in20, M3_UM3_0_M8b3a_5_line6); or3 M3_UM3_0_M8b3a_5_Mux3a_7(M3_UM3_0_M8b3a_5_line4, M3_UM3_0_M8b3a_5_line5, M3_UM3_0_M8b3a_5_line6, M3_temp_5); or2 M3_UM3_0_M8b3a_6_Mux3a_0(in20, in33, M3_UM3_0_M8b3a_6_ContOr); inv M3_UM3_0_M8b3a_6_Mux3a_1(in20, M3_UM3_0_M8b3a_6_NotContHi); inv M3_UM3_0_M8b3a_6_Mux3a_2(M3_UM3_0_M8b3a_6_ContOr, M3_UM3_0_M8b3a_6_Cont00); and2 M3_UM3_0_M8b3a_6_Mux3a_3(M3_UM3_0_M8b3a_6_NotContHi, M3_UM3_0_M8b3a_6_ContOr, M3_UM3_0_M8b3a_6_Cont01); and2 M3_UM3_0_M8b3a_6_Mux3a_4(in159, M3_UM3_0_M8b3a_6_Cont00, M3_UM3_0_M8b3a_6_line4); and2 M3_UM3_0_M8b3a_6_Mux3a_5(in68, M3_UM3_0_M8b3a_6_Cont01, M3_UM3_0_M8b3a_6_line5); and2 M3_UM3_0_M8b3a_6_Mux3a_6(A_BCDbus_6, in20, M3_UM3_0_M8b3a_6_line6); or3 M3_UM3_0_M8b3a_6_Mux3a_7(M3_UM3_0_M8b3a_6_line4, M3_UM3_0_M8b3a_6_line5, M3_UM3_0_M8b3a_6_line6, M3_temp_6); or2 M3_UM3_0_M8b3a_7_Mux3a_0(in20, in33, M3_UM3_0_M8b3a_7_ContOr); inv M3_UM3_0_M8b3a_7_Mux3a_1(in20, M3_UM3_0_M8b3a_7_NotContHi); inv M3_UM3_0_M8b3a_7_Mux3a_2(M3_UM3_0_M8b3a_7_ContOr, M3_UM3_0_M8b3a_7_Cont00); and2 M3_UM3_0_M8b3a_7_Mux3a_3(M3_UM3_0_M8b3a_7_NotContHi, M3_UM3_0_M8b3a_7_ContOr, M3_UM3_0_M8b3a_7_Cont01); and2 M3_UM3_0_M8b3a_7_Mux3a_4(in150, M3_UM3_0_M8b3a_7_Cont00, M3_UM3_0_M8b3a_7_line4); and2 M3_UM3_0_M8b3a_7_Mux3a_5(in58, M3_UM3_0_M8b3a_7_Cont01, M3_UM3_0_M8b3a_7_line5); and2 M3_UM3_0_M8b3a_7_Mux3a_6(A_BCDbus_7, in20, M3_UM3_0_M8b3a_7_line6); or3 M3_UM3_0_M8b3a_7_Mux3a_7(M3_UM3_0_M8b3a_7_line4, M3_UM3_0_M8b3a_7_line5, M3_UM3_0_M8b3a_7_line6, M3_temp_7); nand2 M3_UM3_1(in1, in13, M3_line1); nand3 M3_UM3_2(in1, in20, in33, M3_line2); and2 M3_UM3_3(M3_line1, M3_line2, M3_line3); inv M3_UM3_4(M3_line3, M3_MSel0); and2 M3_UM3_5(in13, in20, M3_line5); inv M3_UM3_6(M3_line5, M3_line6); or2 M3_UM3_7(in1, M3_line6, M3_line7); inv M3_UM3_8(M3_line7, M3_MSel2); inv M3_UM3_9(in33, M3_line9); inv M3_UM3_10(in20, M3_line10); or2 M3_UM3_11(M3_line9, in1, M3_line11); or2 M3_UM3_12(M3_line10, in1, M3_line12); and3 M3_UM3_13(M3_line3, M3_line7, M3_line11, M3_MSel1a); and3 M3_UM3_14(M3_line3, M3_line7, M3_line12, M3_MSel1b); inv M3_UM3_15(M3_line11, M3_line15); inv M3_UM3_16(M3_line12, M3_line16); and3 M3_UM3_17(M3_line3, M3_line7, M3_line15, M3_MSel3a); and3 M3_UM3_18(M3_line3, M3_line7, M3_line16, M3_MSel3b); and2 M3_UM3_19_M4b4a_0_Mux4a_0(M3_temp_0, M3_MSel0, M3_UM3_19_M4b4a_0_line0); and2 M3_UM3_19_M4b4a_0_Mux4a_1(in116, M3_MSel1a, M3_UM3_19_M4b4a_0_line1); and2 M3_UM3_19_M4b4a_0_Mux4a_2(Not_Abus_0, M3_MSel2, M3_UM3_19_M4b4a_0_line2); and2 M3_UM3_19_M4b4a_0_Mux4a_3(gnd, M3_MSel3a, M3_UM3_19_M4b4a_0_line3); or4 M3_UM3_19_M4b4a_0_Mux4a_4(M3_UM3_19_M4b4a_0_line0, M3_UM3_19_M4b4a_0_line1, M3_UM3_19_M4b4a_0_line2, M3_UM3_19_M4b4a_0_line3, MAbus_0); and2 M3_UM3_19_M4b4a_1_Mux4a_0(M3_temp_1, M3_MSel0, M3_UM3_19_M4b4a_1_line0); and2 M3_UM3_19_M4b4a_1_Mux4a_1(in107, M3_MSel1a, M3_UM3_19_M4b4a_1_line1); and2 M3_UM3_19_M4b4a_1_Mux4a_2(Not_Abus_1, M3_MSel2, M3_UM3_19_M4b4a_1_line2); and2 M3_UM3_19_M4b4a_1_Mux4a_3(gnd, M3_MSel3a, M3_UM3_19_M4b4a_1_line3); or4 M3_UM3_19_M4b4a_1_Mux4a_4(M3_UM3_19_M4b4a_1_line0, M3_UM3_19_M4b4a_1_line1, M3_UM3_19_M4b4a_1_line2, M3_UM3_19_M4b4a_1_line3, MAbus_1); and2 M3_UM3_19_M4b4a_2_Mux4a_0(M3_temp_2, M3_MSel0, M3_UM3_19_M4b4a_2_line0); and2 M3_UM3_19_M4b4a_2_Mux4a_1(in97, M3_MSel1a, M3_UM3_19_M4b4a_2_line1); and2 M3_UM3_19_M4b4a_2_Mux4a_2(Not_Abus_2, M3_MSel2, M3_UM3_19_M4b4a_2_line2); and2 M3_UM3_19_M4b4a_2_Mux4a_3(gnd, M3_MSel3a, M3_UM3_19_M4b4a_2_line3); or4 M3_UM3_19_M4b4a_2_Mux4a_4(M3_UM3_19_M4b4a_2_line0, M3_UM3_19_M4b4a_2_line1, M3_UM3_19_M4b4a_2_line2, M3_UM3_19_M4b4a_2_line3, MAbus_2); and2 M3_UM3_19_M4b4a_3_Mux4a_0(M3_temp_3, M3_MSel0, M3_UM3_19_M4b4a_3_line0); and2 M3_UM3_19_M4b4a_3_Mux4a_1(in87, M3_MSel1a, M3_UM3_19_M4b4a_3_line1); and2 M3_UM3_19_M4b4a_3_Mux4a_2(Not_Abus_3, M3_MSel2, M3_UM3_19_M4b4a_3_line2); and2 M3_UM3_19_M4b4a_3_Mux4a_3(gnd, M3_MSel3a, M3_UM3_19_M4b4a_3_line3); or4 M3_UM3_19_M4b4a_3_Mux4a_4(M3_UM3_19_M4b4a_3_line0, M3_UM3_19_M4b4a_3_line1, M3_UM3_19_M4b4a_3_line2, M3_UM3_19_M4b4a_3_line3, MAbus_3); and2 M3_UM3_20_M4b4a_0_Mux4a_0(M3_temp_4, M3_MSel0, M3_UM3_20_M4b4a_0_line0); and2 M3_UM3_20_M4b4a_0_Mux4a_1(in77, M3_MSel1b, M3_UM3_20_M4b4a_0_line1); and2 M3_UM3_20_M4b4a_0_Mux4a_2(Not_Abus_4, M3_MSel2, M3_UM3_20_M4b4a_0_line2); and2 M3_UM3_20_M4b4a_0_Mux4a_3(gnd, M3_MSel3b, M3_UM3_20_M4b4a_0_line3); or4 M3_UM3_20_M4b4a_0_Mux4a_4(M3_UM3_20_M4b4a_0_line0, M3_UM3_20_M4b4a_0_line1, M3_UM3_20_M4b4a_0_line2, M3_UM3_20_M4b4a_0_line3, MAbus_4); and2 M3_UM3_20_M4b4a_1_Mux4a_0(M3_temp_5, M3_MSel0, M3_UM3_20_M4b4a_1_line0); and2 M3_UM3_20_M4b4a_1_Mux4a_1(in68, M3_MSel1b, M3_UM3_20_M4b4a_1_line1); and2 M3_UM3_20_M4b4a_1_Mux4a_2(Not_Abus_5, M3_MSel2, M3_UM3_20_M4b4a_1_line2); and2 M3_UM3_20_M4b4a_1_Mux4a_3(gnd, M3_MSel3b, M3_UM3_20_M4b4a_1_line3); or4 M3_UM3_20_M4b4a_1_Mux4a_4(M3_UM3_20_M4b4a_1_line0, M3_UM3_20_M4b4a_1_line1, M3_UM3_20_M4b4a_1_line2, M3_UM3_20_M4b4a_1_line3, MAbus_5); and2 M3_UM3_20_M4b4a_2_Mux4a_0(M3_temp_6, M3_MSel0, M3_UM3_20_M4b4a_2_line0); and2 M3_UM3_20_M4b4a_2_Mux4a_1(in58, M3_MSel1b, M3_UM3_20_M4b4a_2_line1); and2 M3_UM3_20_M4b4a_2_Mux4a_2(Not_Abus_6, M3_MSel2, M3_UM3_20_M4b4a_2_line2); and2 M3_UM3_20_M4b4a_2_Mux4a_3(gnd, M3_MSel3b, M3_UM3_20_M4b4a_2_line3); or4 M3_UM3_20_M4b4a_2_Mux4a_4(M3_UM3_20_M4b4a_2_line0, M3_UM3_20_M4b4a_2_line1, M3_UM3_20_M4b4a_2_line2, M3_UM3_20_M4b4a_2_line3, MAbus_6); and2 M3_UM3_20_M4b4a_3_Mux4a_0(M3_temp_7, M3_MSel0, M3_UM3_20_M4b4a_3_line0); and2 M3_UM3_20_M4b4a_3_Mux4a_1(in50, M3_MSel1b, M3_UM3_20_M4b4a_3_line1); and2 M3_UM3_20_M4b4a_3_Mux4a_2(Not_Abus_7, M3_MSel2, M3_UM3_20_M4b4a_3_line2); and2 M3_UM3_20_M4b4a_3_Mux4a_3(gnd, M3_MSel3b, M3_UM3_20_M4b4a_3_line3); or4 M3_UM3_20_M4b4a_3_Mux4a_4(M3_UM3_20_M4b4a_3_line0, M3_UM3_20_M4b4a_3_line1, M3_UM3_20_M4b4a_3_line2, M3_UM3_20_M4b4a_3_line3, MAbus_7); or2 M4_UM4_0_M8b3a_0_Mux3a_0(in33, in1698, M4_UM4_0_M8b3a_0_ContOr); inv M4_UM4_0_M8b3a_0_Mux3a_1(in33, M4_UM4_0_M8b3a_0_NotContHi); inv M4_UM4_0_M8b3a_0_Mux3a_2(M4_UM4_0_M8b3a_0_ContOr, M4_UM4_0_M8b3a_0_Cont00); and2 M4_UM4_0_M8b3a_0_Mux3a_3(M4_UM4_0_M8b3a_0_NotContHi, M4_UM4_0_M8b3a_0_ContOr, M4_UM4_0_M8b3a_0_Cont01); and2 M4_UM4_0_M8b3a_0_Mux3a_4(in257, M4_UM4_0_M8b3a_0_Cont00, M4_UM4_0_M8b3a_0_line4); and2 M4_UM4_0_M8b3a_0_Mux3a_5(in264, M4_UM4_0_M8b3a_0_Cont01, M4_UM4_0_M8b3a_0_line5); and2 M4_UM4_0_M8b3a_0_Mux3a_6(in303, in33, M4_UM4_0_M8b3a_0_line6); or3 M4_UM4_0_M8b3a_0_Mux3a_7(M4_UM4_0_M8b3a_0_line4, M4_UM4_0_M8b3a_0_line5, M4_UM4_0_M8b3a_0_line6, M4_temp_0); or2 M4_UM4_0_M8b3a_1_Mux3a_0(in33, in1698, M4_UM4_0_M8b3a_1_ContOr); inv M4_UM4_0_M8b3a_1_Mux3a_1(in33, M4_UM4_0_M8b3a_1_NotContHi); inv M4_UM4_0_M8b3a_1_Mux3a_2(M4_UM4_0_M8b3a_1_ContOr, M4_UM4_0_M8b3a_1_Cont00); and2 M4_UM4_0_M8b3a_1_Mux3a_3(M4_UM4_0_M8b3a_1_NotContHi, M4_UM4_0_M8b3a_1_ContOr, M4_UM4_0_M8b3a_1_Cont01); and2 M4_UM4_0_M8b3a_1_Mux3a_4(in250, M4_UM4_0_M8b3a_1_Cont00, M4_UM4_0_M8b3a_1_line4); and2 M4_UM4_0_M8b3a_1_Mux3a_5(in257, M4_UM4_0_M8b3a_1_Cont01, M4_UM4_0_M8b3a_1_line5); and2 M4_UM4_0_M8b3a_1_Mux3a_6(in294, in33, M4_UM4_0_M8b3a_1_line6); or3 M4_UM4_0_M8b3a_1_Mux3a_7(M4_UM4_0_M8b3a_1_line4, M4_UM4_0_M8b3a_1_line5, M4_UM4_0_M8b3a_1_line6, M4_temp_1); or2 M4_UM4_0_M8b3a_2_Mux3a_0(in33, in1698, M4_UM4_0_M8b3a_2_ContOr); inv M4_UM4_0_M8b3a_2_Mux3a_1(in33, M4_UM4_0_M8b3a_2_NotContHi); inv M4_UM4_0_M8b3a_2_Mux3a_2(M4_UM4_0_M8b3a_2_ContOr, M4_UM4_0_M8b3a_2_Cont00); and2 M4_UM4_0_M8b3a_2_Mux3a_3(M4_UM4_0_M8b3a_2_NotContHi, M4_UM4_0_M8b3a_2_ContOr, M4_UM4_0_M8b3a_2_Cont01); and2 M4_UM4_0_M8b3a_2_Mux3a_4(in244, M4_UM4_0_M8b3a_2_Cont00, M4_UM4_0_M8b3a_2_line4); and2 M4_UM4_0_M8b3a_2_Mux3a_5(in250, M4_UM4_0_M8b3a_2_Cont01, M4_UM4_0_M8b3a_2_line5); and2 M4_UM4_0_M8b3a_2_Mux3a_6(in283, in33, M4_UM4_0_M8b3a_2_line6); or3 M4_UM4_0_M8b3a_2_Mux3a_7(M4_UM4_0_M8b3a_2_line4, M4_UM4_0_M8b3a_2_line5, M4_UM4_0_M8b3a_2_line6, M4_temp_2); or2 M4_UM4_0_M8b3a_3_Mux3a_0(in33, in1698, M4_UM4_0_M8b3a_3_ContOr); inv M4_UM4_0_M8b3a_3_Mux3a_1(in33, M4_UM4_0_M8b3a_3_NotContHi); inv M4_UM4_0_M8b3a_3_Mux3a_2(M4_UM4_0_M8b3a_3_ContOr, M4_UM4_0_M8b3a_3_Cont00); and2 M4_UM4_0_M8b3a_3_Mux3a_3(M4_UM4_0_M8b3a_3_NotContHi, M4_UM4_0_M8b3a_3_ContOr, M4_UM4_0_M8b3a_3_Cont01); and2 M4_UM4_0_M8b3a_3_Mux3a_4(in238, M4_UM4_0_M8b3a_3_Cont00, M4_UM4_0_M8b3a_3_line4); and2 M4_UM4_0_M8b3a_3_Mux3a_5(in244, M4_UM4_0_M8b3a_3_Cont01, M4_UM4_0_M8b3a_3_line5); and2 M4_UM4_0_M8b3a_3_Mux3a_6(in116, in33, M4_UM4_0_M8b3a_3_line6); or3 M4_UM4_0_M8b3a_3_Mux3a_7(M4_UM4_0_M8b3a_3_line4, M4_UM4_0_M8b3a_3_line5, M4_UM4_0_M8b3a_3_line6, M4_temp_3); or2 M4_UM4_0_M8b3a_4_Mux3a_0(in33, in1698, M4_UM4_0_M8b3a_4_ContOr); inv M4_UM4_0_M8b3a_4_Mux3a_1(in33, M4_UM4_0_M8b3a_4_NotContHi); inv M4_UM4_0_M8b3a_4_Mux3a_2(M4_UM4_0_M8b3a_4_ContOr, M4_UM4_0_M8b3a_4_Cont00); and2 M4_UM4_0_M8b3a_4_Mux3a_3(M4_UM4_0_M8b3a_4_NotContHi, M4_UM4_0_M8b3a_4_ContOr, M4_UM4_0_M8b3a_4_Cont01); and2 M4_UM4_0_M8b3a_4_Mux3a_4(in232, M4_UM4_0_M8b3a_4_Cont00, M4_UM4_0_M8b3a_4_line4); and2 M4_UM4_0_M8b3a_4_Mux3a_5(in238, M4_UM4_0_M8b3a_4_Cont01, M4_UM4_0_M8b3a_4_line5); and2 M4_UM4_0_M8b3a_4_Mux3a_6(in107, in33, M4_UM4_0_M8b3a_4_line6); or3 M4_UM4_0_M8b3a_4_Mux3a_7(M4_UM4_0_M8b3a_4_line4, M4_UM4_0_M8b3a_4_line5, M4_UM4_0_M8b3a_4_line6, M4_temp_4); or2 M4_UM4_0_M8b3a_5_Mux3a_0(in33, in1698, M4_UM4_0_M8b3a_5_ContOr); inv M4_UM4_0_M8b3a_5_Mux3a_1(in33, M4_UM4_0_M8b3a_5_NotContHi); inv M4_UM4_0_M8b3a_5_Mux3a_2(M4_UM4_0_M8b3a_5_ContOr, M4_UM4_0_M8b3a_5_Cont00); and2 M4_UM4_0_M8b3a_5_Mux3a_3(M4_UM4_0_M8b3a_5_NotContHi, M4_UM4_0_M8b3a_5_ContOr, M4_UM4_0_M8b3a_5_Cont01); and2 M4_UM4_0_M8b3a_5_Mux3a_4(in226, M4_UM4_0_M8b3a_5_Cont00, M4_UM4_0_M8b3a_5_line4); and2 M4_UM4_0_M8b3a_5_Mux3a_5(in232, M4_UM4_0_M8b3a_5_Cont01, M4_UM4_0_M8b3a_5_line5); and2 M4_UM4_0_M8b3a_5_Mux3a_6(in97, in33, M4_UM4_0_M8b3a_5_line6); or3 M4_UM4_0_M8b3a_5_Mux3a_7(M4_UM4_0_M8b3a_5_line4, M4_UM4_0_M8b3a_5_line5, M4_UM4_0_M8b3a_5_line6, M4_temp_5); or2 M4_UM4_0_M8b3a_6_Mux3a_0(in33, in1698, M4_UM4_0_M8b3a_6_ContOr); inv M4_UM4_0_M8b3a_6_Mux3a_1(in33, M4_UM4_0_M8b3a_6_NotContHi); inv M4_UM4_0_M8b3a_6_Mux3a_2(M4_UM4_0_M8b3a_6_ContOr, M4_UM4_0_M8b3a_6_Cont00); and2 M4_UM4_0_M8b3a_6_Mux3a_3(M4_UM4_0_M8b3a_6_NotContHi, M4_UM4_0_M8b3a_6_ContOr, M4_UM4_0_M8b3a_6_Cont01); and2 M4_UM4_0_M8b3a_6_Mux3a_4(in223, M4_UM4_0_M8b3a_6_Cont00, M4_UM4_0_M8b3a_6_line4); and2 M4_UM4_0_M8b3a_6_Mux3a_5(in226, M4_UM4_0_M8b3a_6_Cont01, M4_UM4_0_M8b3a_6_line5); and2 M4_UM4_0_M8b3a_6_Mux3a_6(in87, in33, M4_UM4_0_M8b3a_6_line6); or3 M4_UM4_0_M8b3a_6_Mux3a_7(M4_UM4_0_M8b3a_6_line4, M4_UM4_0_M8b3a_6_line5, M4_UM4_0_M8b3a_6_line6, M4_temp_6); or2 M4_UM4_0_M8b3a_7_Mux3a_0(in33, in1698, M4_UM4_0_M8b3a_7_ContOr); inv M4_UM4_0_M8b3a_7_Mux3a_1(in33, M4_UM4_0_M8b3a_7_NotContHi); inv M4_UM4_0_M8b3a_7_Mux3a_2(M4_UM4_0_M8b3a_7_ContOr, M4_UM4_0_M8b3a_7_Cont00); and2 M4_UM4_0_M8b3a_7_Mux3a_3(M4_UM4_0_M8b3a_7_NotContHi, M4_UM4_0_M8b3a_7_ContOr, M4_UM4_0_M8b3a_7_Cont01); and2 M4_UM4_0_M8b3a_7_Mux3a_4(in222, M4_UM4_0_M8b3a_7_Cont00, M4_UM4_0_M8b3a_7_line4); and2 M4_UM4_0_M8b3a_7_Mux3a_5(in223, M4_UM4_0_M8b3a_7_Cont01, M4_UM4_0_M8b3a_7_line5); and2 M4_UM4_0_M8b3a_7_Mux3a_6(in77, in33, M4_UM4_0_M8b3a_7_line6); or3 M4_UM4_0_M8b3a_7_Mux3a_7(M4_UM4_0_M8b3a_7_line4, M4_UM4_0_M8b3a_7_line5, M4_UM4_0_M8b3a_7_line6, M4_temp_7); and2 M4_UM4_1(in33, in41, M4_line1); inv M4_UM4_2(M4_line1, M4_line2); and3 M4_UM4_3(in1, in13, M4_line2, M4_MSelHi); inv M4_UM4_4(in1, M4_line4); inv M4_UM4_5(in41, M4_line5); and3 M4_UM4_6(M4_line4, in45, M4_line5, M4_MSelLo1); and2 M4_UM4_7(M4_line4, in45, M4_MSelLo2); or2 M4_UM4_8(in41, in45, M4_line8); and2 M4_UM4_9(M4_line4, M4_line8, M4_MSelLo3); inv M4_UM4_11_Mux3b_0(M4_MSelHi, M4_UM4_11_NotContHi); inv M4_UM4_11_Mux3b_1(M4_MSelLo1, M4_UM4_11_NotContLo); and3 M4_UM4_11_Mux3b_2(in270, M4_UM4_11_NotContHi, M4_UM4_11_NotContLo, M4_UM4_11_line2); and3 M4_UM4_11_Mux3b_3(in274, M4_UM4_11_NotContHi, M4_MSelLo1, M4_UM4_11_line3); and2 M4_UM4_11_Mux3b_4(M4_temp_0, M4_MSelHi, M4_UM4_11_line4); or3 M4_UM4_11_Mux3b_5(M4_UM4_11_line2, M4_UM4_11_line3, M4_UM4_11_line4, MBbus_0); inv M4_UM4_12_Mux3b_0(M4_MSelHi, M4_UM4_12_NotContHi); inv M4_UM4_12_Mux3b_1(M4_MSelLo1, M4_UM4_12_NotContLo); and3 M4_UM4_12_Mux3b_2(in264, M4_UM4_12_NotContHi, M4_UM4_12_NotContLo, M4_UM4_12_line2); and3 M4_UM4_12_Mux3b_3(in274, M4_UM4_12_NotContHi, M4_MSelLo1, M4_UM4_12_line3); and2 M4_UM4_12_Mux3b_4(M4_temp_1, M4_MSelHi, M4_UM4_12_line4); or3 M4_UM4_12_Mux3b_5(M4_UM4_12_line2, M4_UM4_12_line3, M4_UM4_12_line4, MBbus_1); inv M4_UM4_13_Mux3b_0(M4_MSelHi, M4_UM4_13_NotContHi); inv M4_UM4_13_Mux3b_1(M4_MSelLo1, M4_UM4_13_NotContLo); and3 M4_UM4_13_Mux3b_2(in257, M4_UM4_13_NotContHi, M4_UM4_13_NotContLo, M4_UM4_13_line2); and3 M4_UM4_13_Mux3b_3(in274, M4_UM4_13_NotContHi, M4_MSelLo1, M4_UM4_13_line3); and2 M4_UM4_13_Mux3b_4(M4_temp_2, M4_MSelHi, M4_UM4_13_line4); or3 M4_UM4_13_Mux3b_5(M4_UM4_13_line2, M4_UM4_13_line3, M4_UM4_13_line4, MBbus_2); inv M4_UM4_14_Mux3b_0(M4_MSelHi, M4_UM4_14_NotContHi); inv M4_UM4_14_Mux3b_1(M4_MSelLo2, M4_UM4_14_NotContLo); and3 M4_UM4_14_Mux3b_2(in250, M4_UM4_14_NotContHi, M4_UM4_14_NotContLo, M4_UM4_14_line2); and3 M4_UM4_14_Mux3b_3(in274, M4_UM4_14_NotContHi, M4_MSelLo2, M4_UM4_14_line3); and2 M4_UM4_14_Mux3b_4(M4_temp_3, M4_MSelHi, M4_UM4_14_line4); or3 M4_UM4_14_Mux3b_5(M4_UM4_14_line2, M4_UM4_14_line3, M4_UM4_14_line4, MBbus_3); inv M4_UM4_15_M4b3b_0_Mux3b_0(M4_MSelHi, M4_UM4_15_M4b3b_0_NotContHi); inv M4_UM4_15_M4b3b_0_Mux3b_1(M4_MSelLo3, M4_UM4_15_M4b3b_0_NotContLo); and3 M4_UM4_15_M4b3b_0_Mux3b_2(in244, M4_UM4_15_M4b3b_0_NotContHi, M4_UM4_15_M4b3b_0_NotContLo, M4_UM4_15_M4b3b_0_line2); and3 M4_UM4_15_M4b3b_0_Mux3b_3(in274, M4_UM4_15_M4b3b_0_NotContHi, M4_MSelLo3, M4_UM4_15_M4b3b_0_line3); and2 M4_UM4_15_M4b3b_0_Mux3b_4(M4_temp_4, M4_MSelHi, M4_UM4_15_M4b3b_0_line4); or3 M4_UM4_15_M4b3b_0_Mux3b_5(M4_UM4_15_M4b3b_0_line2, M4_UM4_15_M4b3b_0_line3, M4_UM4_15_M4b3b_0_line4, MBbus_4); inv M4_UM4_15_M4b3b_1_Mux3b_0(M4_MSelHi, M4_UM4_15_M4b3b_1_NotContHi); inv M4_UM4_15_M4b3b_1_Mux3b_1(M4_MSelLo3, M4_UM4_15_M4b3b_1_NotContLo); and3 M4_UM4_15_M4b3b_1_Mux3b_2(in238, M4_UM4_15_M4b3b_1_NotContHi, M4_UM4_15_M4b3b_1_NotContLo, M4_UM4_15_M4b3b_1_line2); and3 M4_UM4_15_M4b3b_1_Mux3b_3(in274, M4_UM4_15_M4b3b_1_NotContHi, M4_MSelLo3, M4_UM4_15_M4b3b_1_line3); and2 M4_UM4_15_M4b3b_1_Mux3b_4(M4_temp_5, M4_MSelHi, M4_UM4_15_M4b3b_1_line4); or3 M4_UM4_15_M4b3b_1_Mux3b_5(M4_UM4_15_M4b3b_1_line2, M4_UM4_15_M4b3b_1_line3, M4_UM4_15_M4b3b_1_line4, MBbus_5); inv M4_UM4_15_M4b3b_2_Mux3b_0(M4_MSelHi, M4_UM4_15_M4b3b_2_NotContHi); inv M4_UM4_15_M4b3b_2_Mux3b_1(M4_MSelLo3, M4_UM4_15_M4b3b_2_NotContLo); and3 M4_UM4_15_M4b3b_2_Mux3b_2(in232, M4_UM4_15_M4b3b_2_NotContHi, M4_UM4_15_M4b3b_2_NotContLo, M4_UM4_15_M4b3b_2_line2); and3 M4_UM4_15_M4b3b_2_Mux3b_3(in274, M4_UM4_15_M4b3b_2_NotContHi, M4_MSelLo3, M4_UM4_15_M4b3b_2_line3); and2 M4_UM4_15_M4b3b_2_Mux3b_4(M4_temp_6, M4_MSelHi, M4_UM4_15_M4b3b_2_line4); or3 M4_UM4_15_M4b3b_2_Mux3b_5(M4_UM4_15_M4b3b_2_line2, M4_UM4_15_M4b3b_2_line3, M4_UM4_15_M4b3b_2_line4, MBbus_6); inv M4_UM4_15_M4b3b_3_Mux3b_0(M4_MSelHi, M4_UM4_15_M4b3b_3_NotContHi); inv M4_UM4_15_M4b3b_3_Mux3b_1(M4_MSelLo3, M4_UM4_15_M4b3b_3_NotContLo); and3 M4_UM4_15_M4b3b_3_Mux3b_2(in226, M4_UM4_15_M4b3b_3_NotContHi, M4_UM4_15_M4b3b_3_NotContLo, M4_UM4_15_M4b3b_3_line2); and3 M4_UM4_15_M4b3b_3_Mux3b_3(in274, M4_UM4_15_M4b3b_3_NotContHi, M4_MSelLo3, M4_UM4_15_M4b3b_3_line3); and2 M4_UM4_15_M4b3b_3_Mux3b_4(M4_temp_7, M4_MSelHi, M4_UM4_15_M4b3b_3_line4); or3 M4_UM4_15_M4b3b_3_Mux3b_5(M4_UM4_15_M4b3b_3_line2, M4_UM4_15_M4b3b_3_line3, M4_UM4_15_M4b3b_3_line4, MBbus_7); inv M5_UM5_0(in1, M5_NotCont0); inv M5_UM5_1(in20, M5_NotCont2); and3 M5_UM5_2(M5_NotCont0, in13, M5_NotCont2, M5_ModeAux); and3 M5_UM5_3(M5_ModeAux, in213, in343, M5_Mode); and2 M5_UM5_4(M5_ModeAux, in213, M5_Mask7_6); inv M5_UM5_5_LGP8_0_LGP0_Mux2_0(MBbus_0, M5_UM5_5_LGP8_0_LGP0_Not_ContIn); and2 M5_UM5_5_LGP8_0_LGP0_Mux2_1(in190, M5_UM5_5_LGP8_0_LGP0_Not_ContIn, M5_UM5_5_LGP8_0_LGP0_line1); and2 M5_UM5_5_LGP8_0_LGP0_Mux2_2(in200, MBbus_0, M5_UM5_5_LGP8_0_LGP0_line2); or2 M5_UM5_5_LGP8_0_LGP0_Mux2_3(M5_UM5_5_LGP8_0_LGP0_line1, M5_UM5_5_LGP8_0_LGP0_line2, M5_UM5_5_LGP8_0_Mx0); inv M5_UM5_5_LGP8_0_LGP1_Mux2_0(MBbus_0, M5_UM5_5_LGP8_0_LGP1_Not_ContIn); and2 M5_UM5_5_LGP8_0_LGP1_Mux2_1(in179, M5_UM5_5_LGP8_0_LGP1_Not_ContIn, M5_UM5_5_LGP8_0_LGP1_line1); and2 M5_UM5_5_LGP8_0_LGP1_Mux2_2(in169, MBbus_0, M5_UM5_5_LGP8_0_LGP1_line2); or2 M5_UM5_5_LGP8_0_LGP1_Mux2_3(M5_UM5_5_LGP8_0_LGP1_line1, M5_UM5_5_LGP8_0_LGP1_line2, M5_UM5_5_LGP8_0_Mx1); and2 M5_UM5_5_LGP8_0_LGP2(MAbus_0, M5_UM5_5_LGP8_0_Mx1, M5_Gbus_0); or2 M5_UM5_5_LGP8_0_LGP3(MAbus_0, M5_UM5_5_LGP8_0_Mx0, M5_UM5_5_LGP8_0_InAMx0); nand2 M5_UM5_5_LGP8_0_LGP4(MAbus_0, M5_UM5_5_LGP8_0_Mx1, M5_UM5_5_LGP8_0_InAMx1); and2 M5_UM5_5_LGP8_0_LGP5(M5_UM5_5_LGP8_0_InAMx0, M5_UM5_5_LGP8_0_InAMx1, M5_Pbus_0); and2 M5_UM5_5_LGP8_0_LGP6(M5_Mode, MAbus_0, M5_UM5_5_LGP8_0_InAMask); inv M5_UM5_5_LGP8_0_LGP7_Xo0(M5_UM5_5_LGP8_0_InAMask, M5_UM5_5_LGP8_0_LGP7_NotA); inv M5_UM5_5_LGP8_0_LGP7_Xo1(M5_Pbus_0, M5_UM5_5_LGP8_0_LGP7_NotB); nand2 M5_UM5_5_LGP8_0_LGP7_Xo2(M5_UM5_5_LGP8_0_LGP7_NotA, M5_Pbus_0, M5_UM5_5_LGP8_0_LGP7_line2); nand2 M5_UM5_5_LGP8_0_LGP7_Xo3(M5_UM5_5_LGP8_0_LGP7_NotB, M5_UM5_5_LGP8_0_InAMask, M5_UM5_5_LGP8_0_LGP7_line3); nand2 M5_UM5_5_LGP8_0_LGP7_Xo4(M5_UM5_5_LGP8_0_LGP7_line2, M5_UM5_5_LGP8_0_LGP7_line3, XPbus_0); inv M5_UM5_5_LGP8_0_LGP8(M5_Mode, M5_UM5_5_LGP8_0_NotMask); and2 M5_UM5_5_LGP8_0_LGP9(M5_Gbus_0, M5_UM5_5_LGP8_0_NotMask, M5_XGbus_0); inv M5_UM5_5_LGP8_1_LGP0_Mux2_0(MBbus_1, M5_UM5_5_LGP8_1_LGP0_Not_ContIn); and2 M5_UM5_5_LGP8_1_LGP0_Mux2_1(in190, M5_UM5_5_LGP8_1_LGP0_Not_ContIn, M5_UM5_5_LGP8_1_LGP0_line1); and2 M5_UM5_5_LGP8_1_LGP0_Mux2_2(in200, MBbus_1, M5_UM5_5_LGP8_1_LGP0_line2); or2 M5_UM5_5_LGP8_1_LGP0_Mux2_3(M5_UM5_5_LGP8_1_LGP0_line1, M5_UM5_5_LGP8_1_LGP0_line2, M5_UM5_5_LGP8_1_Mx0); inv M5_UM5_5_LGP8_1_LGP1_Mux2_0(MBbus_1, M5_UM5_5_LGP8_1_LGP1_Not_ContIn); and2 M5_UM5_5_LGP8_1_LGP1_Mux2_1(in179, M5_UM5_5_LGP8_1_LGP1_Not_ContIn, M5_UM5_5_LGP8_1_LGP1_line1); and2 M5_UM5_5_LGP8_1_LGP1_Mux2_2(in169, MBbus_1, M5_UM5_5_LGP8_1_LGP1_line2); or2 M5_UM5_5_LGP8_1_LGP1_Mux2_3(M5_UM5_5_LGP8_1_LGP1_line1, M5_UM5_5_LGP8_1_LGP1_line2, M5_UM5_5_LGP8_1_Mx1); and2 M5_UM5_5_LGP8_1_LGP2(MAbus_1, M5_UM5_5_LGP8_1_Mx1, M5_Gbus_1); or2 M5_UM5_5_LGP8_1_LGP3(MAbus_1, M5_UM5_5_LGP8_1_Mx0, M5_UM5_5_LGP8_1_InAMx0); nand2 M5_UM5_5_LGP8_1_LGP4(MAbus_1, M5_UM5_5_LGP8_1_Mx1, M5_UM5_5_LGP8_1_InAMx1); and2 M5_UM5_5_LGP8_1_LGP5(M5_UM5_5_LGP8_1_InAMx0, M5_UM5_5_LGP8_1_InAMx1, M5_Pbus_1); and2 M5_UM5_5_LGP8_1_LGP6(M5_Mode, MAbus_1, M5_UM5_5_LGP8_1_InAMask); inv M5_UM5_5_LGP8_1_LGP7_Xo0(M5_UM5_5_LGP8_1_InAMask, M5_UM5_5_LGP8_1_LGP7_NotA); inv M5_UM5_5_LGP8_1_LGP7_Xo1(M5_Pbus_1, M5_UM5_5_LGP8_1_LGP7_NotB); nand2 M5_UM5_5_LGP8_1_LGP7_Xo2(M5_UM5_5_LGP8_1_LGP7_NotA, M5_Pbus_1, M5_UM5_5_LGP8_1_LGP7_line2); nand2 M5_UM5_5_LGP8_1_LGP7_Xo3(M5_UM5_5_LGP8_1_LGP7_NotB, M5_UM5_5_LGP8_1_InAMask, M5_UM5_5_LGP8_1_LGP7_line3); nand2 M5_UM5_5_LGP8_1_LGP7_Xo4(M5_UM5_5_LGP8_1_LGP7_line2, M5_UM5_5_LGP8_1_LGP7_line3, XPbus_1); inv M5_UM5_5_LGP8_1_LGP8(M5_Mode, M5_UM5_5_LGP8_1_NotMask); and2 M5_UM5_5_LGP8_1_LGP9(M5_Gbus_1, M5_UM5_5_LGP8_1_NotMask, M5_XGbus_1); inv M5_UM5_5_LGP8_2_LGP0_Mux2_0(MBbus_2, M5_UM5_5_LGP8_2_LGP0_Not_ContIn); and2 M5_UM5_5_LGP8_2_LGP0_Mux2_1(in190, M5_UM5_5_LGP8_2_LGP0_Not_ContIn, M5_UM5_5_LGP8_2_LGP0_line1); and2 M5_UM5_5_LGP8_2_LGP0_Mux2_2(in200, MBbus_2, M5_UM5_5_LGP8_2_LGP0_line2); or2 M5_UM5_5_LGP8_2_LGP0_Mux2_3(M5_UM5_5_LGP8_2_LGP0_line1, M5_UM5_5_LGP8_2_LGP0_line2, M5_UM5_5_LGP8_2_Mx0); inv M5_UM5_5_LGP8_2_LGP1_Mux2_0(MBbus_2, M5_UM5_5_LGP8_2_LGP1_Not_ContIn); and2 M5_UM5_5_LGP8_2_LGP1_Mux2_1(in179, M5_UM5_5_LGP8_2_LGP1_Not_ContIn, M5_UM5_5_LGP8_2_LGP1_line1); and2 M5_UM5_5_LGP8_2_LGP1_Mux2_2(in169, MBbus_2, M5_UM5_5_LGP8_2_LGP1_line2); or2 M5_UM5_5_LGP8_2_LGP1_Mux2_3(M5_UM5_5_LGP8_2_LGP1_line1, M5_UM5_5_LGP8_2_LGP1_line2, M5_UM5_5_LGP8_2_Mx1); and2 M5_UM5_5_LGP8_2_LGP2(MAbus_2, M5_UM5_5_LGP8_2_Mx1, M5_Gbus_2); or2 M5_UM5_5_LGP8_2_LGP3(MAbus_2, M5_UM5_5_LGP8_2_Mx0, M5_UM5_5_LGP8_2_InAMx0); nand2 M5_UM5_5_LGP8_2_LGP4(MAbus_2, M5_UM5_5_LGP8_2_Mx1, M5_UM5_5_LGP8_2_InAMx1); and2 M5_UM5_5_LGP8_2_LGP5(M5_UM5_5_LGP8_2_InAMx0, M5_UM5_5_LGP8_2_InAMx1, M5_Pbus_2); and2 M5_UM5_5_LGP8_2_LGP6(M5_Mode, MAbus_2, M5_UM5_5_LGP8_2_InAMask); inv M5_UM5_5_LGP8_2_LGP7_Xo0(M5_UM5_5_LGP8_2_InAMask, M5_UM5_5_LGP8_2_LGP7_NotA); inv M5_UM5_5_LGP8_2_LGP7_Xo1(M5_Pbus_2, M5_UM5_5_LGP8_2_LGP7_NotB); nand2 M5_UM5_5_LGP8_2_LGP7_Xo2(M5_UM5_5_LGP8_2_LGP7_NotA, M5_Pbus_2, M5_UM5_5_LGP8_2_LGP7_line2); nand2 M5_UM5_5_LGP8_2_LGP7_Xo3(M5_UM5_5_LGP8_2_LGP7_NotB, M5_UM5_5_LGP8_2_InAMask, M5_UM5_5_LGP8_2_LGP7_line3); nand2 M5_UM5_5_LGP8_2_LGP7_Xo4(M5_UM5_5_LGP8_2_LGP7_line2, M5_UM5_5_LGP8_2_LGP7_line3, XPbus_2); inv M5_UM5_5_LGP8_2_LGP8(M5_Mode, M5_UM5_5_LGP8_2_NotMask); and2 M5_UM5_5_LGP8_2_LGP9(M5_Gbus_2, M5_UM5_5_LGP8_2_NotMask, M5_XGbus_2); inv M5_UM5_5_LGP8_3_LGP0_Mux2_0(MBbus_3, M5_UM5_5_LGP8_3_LGP0_Not_ContIn); and2 M5_UM5_5_LGP8_3_LGP0_Mux2_1(in190, M5_UM5_5_LGP8_3_LGP0_Not_ContIn, M5_UM5_5_LGP8_3_LGP0_line1); and2 M5_UM5_5_LGP8_3_LGP0_Mux2_2(in200, MBbus_3, M5_UM5_5_LGP8_3_LGP0_line2); or2 M5_UM5_5_LGP8_3_LGP0_Mux2_3(M5_UM5_5_LGP8_3_LGP0_line1, M5_UM5_5_LGP8_3_LGP0_line2, M5_UM5_5_LGP8_3_Mx0); inv M5_UM5_5_LGP8_3_LGP1_Mux2_0(MBbus_3, M5_UM5_5_LGP8_3_LGP1_Not_ContIn); and2 M5_UM5_5_LGP8_3_LGP1_Mux2_1(in179, M5_UM5_5_LGP8_3_LGP1_Not_ContIn, M5_UM5_5_LGP8_3_LGP1_line1); and2 M5_UM5_5_LGP8_3_LGP1_Mux2_2(in169, MBbus_3, M5_UM5_5_LGP8_3_LGP1_line2); or2 M5_UM5_5_LGP8_3_LGP1_Mux2_3(M5_UM5_5_LGP8_3_LGP1_line1, M5_UM5_5_LGP8_3_LGP1_line2, M5_UM5_5_LGP8_3_Mx1); and2 M5_UM5_5_LGP8_3_LGP2(MAbus_3, M5_UM5_5_LGP8_3_Mx1, M5_Gbus_3); or2 M5_UM5_5_LGP8_3_LGP3(MAbus_3, M5_UM5_5_LGP8_3_Mx0, M5_UM5_5_LGP8_3_InAMx0); nand2 M5_UM5_5_LGP8_3_LGP4(MAbus_3, M5_UM5_5_LGP8_3_Mx1, M5_UM5_5_LGP8_3_InAMx1); and2 M5_UM5_5_LGP8_3_LGP5(M5_UM5_5_LGP8_3_InAMx0, M5_UM5_5_LGP8_3_InAMx1, M5_Pbus_3); and2 M5_UM5_5_LGP8_3_LGP6(M5_Mode, MAbus_3, M5_UM5_5_LGP8_3_InAMask); inv M5_UM5_5_LGP8_3_LGP7_Xo0(M5_UM5_5_LGP8_3_InAMask, M5_UM5_5_LGP8_3_LGP7_NotA); inv M5_UM5_5_LGP8_3_LGP7_Xo1(M5_Pbus_3, M5_UM5_5_LGP8_3_LGP7_NotB); nand2 M5_UM5_5_LGP8_3_LGP7_Xo2(M5_UM5_5_LGP8_3_LGP7_NotA, M5_Pbus_3, M5_UM5_5_LGP8_3_LGP7_line2); nand2 M5_UM5_5_LGP8_3_LGP7_Xo3(M5_UM5_5_LGP8_3_LGP7_NotB, M5_UM5_5_LGP8_3_InAMask, M5_UM5_5_LGP8_3_LGP7_line3); nand2 M5_UM5_5_LGP8_3_LGP7_Xo4(M5_UM5_5_LGP8_3_LGP7_line2, M5_UM5_5_LGP8_3_LGP7_line3, XPbus_3); inv M5_UM5_5_LGP8_3_LGP8(M5_Mode, M5_UM5_5_LGP8_3_NotMask); and2 M5_UM5_5_LGP8_3_LGP9(M5_Gbus_3, M5_UM5_5_LGP8_3_NotMask, M5_XGbus_3); inv M5_UM5_5_LGP8_4_LGP0_Mux2_0(MBbus_4, M5_UM5_5_LGP8_4_LGP0_Not_ContIn); and2 M5_UM5_5_LGP8_4_LGP0_Mux2_1(in190, M5_UM5_5_LGP8_4_LGP0_Not_ContIn, M5_UM5_5_LGP8_4_LGP0_line1); and2 M5_UM5_5_LGP8_4_LGP0_Mux2_2(in200, MBbus_4, M5_UM5_5_LGP8_4_LGP0_line2); or2 M5_UM5_5_LGP8_4_LGP0_Mux2_3(M5_UM5_5_LGP8_4_LGP0_line1, M5_UM5_5_LGP8_4_LGP0_line2, M5_UM5_5_LGP8_4_Mx0); inv M5_UM5_5_LGP8_4_LGP1_Mux2_0(MBbus_4, M5_UM5_5_LGP8_4_LGP1_Not_ContIn); and2 M5_UM5_5_LGP8_4_LGP1_Mux2_1(in179, M5_UM5_5_LGP8_4_LGP1_Not_ContIn, M5_UM5_5_LGP8_4_LGP1_line1); and2 M5_UM5_5_LGP8_4_LGP1_Mux2_2(in169, MBbus_4, M5_UM5_5_LGP8_4_LGP1_line2); or2 M5_UM5_5_LGP8_4_LGP1_Mux2_3(M5_UM5_5_LGP8_4_LGP1_line1, M5_UM5_5_LGP8_4_LGP1_line2, M5_UM5_5_LGP8_4_Mx1); and2 M5_UM5_5_LGP8_4_LGP2(MAbus_4, M5_UM5_5_LGP8_4_Mx1, M5_Gbus_4); or2 M5_UM5_5_LGP8_4_LGP3(MAbus_4, M5_UM5_5_LGP8_4_Mx0, M5_UM5_5_LGP8_4_InAMx0); nand2 M5_UM5_5_LGP8_4_LGP4(MAbus_4, M5_UM5_5_LGP8_4_Mx1, M5_UM5_5_LGP8_4_InAMx1); and2 M5_UM5_5_LGP8_4_LGP5(M5_UM5_5_LGP8_4_InAMx0, M5_UM5_5_LGP8_4_InAMx1, M5_Pbus_4); and2 M5_UM5_5_LGP8_4_LGP6(M5_Mode, MAbus_4, M5_UM5_5_LGP8_4_InAMask); inv M5_UM5_5_LGP8_4_LGP7_Xo0(M5_UM5_5_LGP8_4_InAMask, M5_UM5_5_LGP8_4_LGP7_NotA); inv M5_UM5_5_LGP8_4_LGP7_Xo1(M5_Pbus_4, M5_UM5_5_LGP8_4_LGP7_NotB); nand2 M5_UM5_5_LGP8_4_LGP7_Xo2(M5_UM5_5_LGP8_4_LGP7_NotA, M5_Pbus_4, M5_UM5_5_LGP8_4_LGP7_line2); nand2 M5_UM5_5_LGP8_4_LGP7_Xo3(M5_UM5_5_LGP8_4_LGP7_NotB, M5_UM5_5_LGP8_4_InAMask, M5_UM5_5_LGP8_4_LGP7_line3); nand2 M5_UM5_5_LGP8_4_LGP7_Xo4(M5_UM5_5_LGP8_4_LGP7_line2, M5_UM5_5_LGP8_4_LGP7_line3, XPbus_4); inv M5_UM5_5_LGP8_4_LGP8(M5_Mode, M5_UM5_5_LGP8_4_NotMask); and2 M5_UM5_5_LGP8_4_LGP9(M5_Gbus_4, M5_UM5_5_LGP8_4_NotMask, M5_XGbus_4); inv M5_UM5_5_LGP8_5_LGP0_Mux2_0(MBbus_5, M5_UM5_5_LGP8_5_LGP0_Not_ContIn); and2 M5_UM5_5_LGP8_5_LGP0_Mux2_1(in190, M5_UM5_5_LGP8_5_LGP0_Not_ContIn, M5_UM5_5_LGP8_5_LGP0_line1); and2 M5_UM5_5_LGP8_5_LGP0_Mux2_2(in200, MBbus_5, M5_UM5_5_LGP8_5_LGP0_line2); or2 M5_UM5_5_LGP8_5_LGP0_Mux2_3(M5_UM5_5_LGP8_5_LGP0_line1, M5_UM5_5_LGP8_5_LGP0_line2, M5_UM5_5_LGP8_5_Mx0); inv M5_UM5_5_LGP8_5_LGP1_Mux2_0(MBbus_5, M5_UM5_5_LGP8_5_LGP1_Not_ContIn); and2 M5_UM5_5_LGP8_5_LGP1_Mux2_1(in179, M5_UM5_5_LGP8_5_LGP1_Not_ContIn, M5_UM5_5_LGP8_5_LGP1_line1); and2 M5_UM5_5_LGP8_5_LGP1_Mux2_2(in169, MBbus_5, M5_UM5_5_LGP8_5_LGP1_line2); or2 M5_UM5_5_LGP8_5_LGP1_Mux2_3(M5_UM5_5_LGP8_5_LGP1_line1, M5_UM5_5_LGP8_5_LGP1_line2, M5_UM5_5_LGP8_5_Mx1); and2 M5_UM5_5_LGP8_5_LGP2(MAbus_5, M5_UM5_5_LGP8_5_Mx1, M5_Gbus_5); or2 M5_UM5_5_LGP8_5_LGP3(MAbus_5, M5_UM5_5_LGP8_5_Mx0, M5_UM5_5_LGP8_5_InAMx0); nand2 M5_UM5_5_LGP8_5_LGP4(MAbus_5, M5_UM5_5_LGP8_5_Mx1, M5_UM5_5_LGP8_5_InAMx1); and2 M5_UM5_5_LGP8_5_LGP5(M5_UM5_5_LGP8_5_InAMx0, M5_UM5_5_LGP8_5_InAMx1, M5_Pbus_5); and2 M5_UM5_5_LGP8_5_LGP6(M5_Mode, MAbus_5, M5_UM5_5_LGP8_5_InAMask); inv M5_UM5_5_LGP8_5_LGP7_Xo0(M5_UM5_5_LGP8_5_InAMask, M5_UM5_5_LGP8_5_LGP7_NotA); inv M5_UM5_5_LGP8_5_LGP7_Xo1(M5_Pbus_5, M5_UM5_5_LGP8_5_LGP7_NotB); nand2 M5_UM5_5_LGP8_5_LGP7_Xo2(M5_UM5_5_LGP8_5_LGP7_NotA, M5_Pbus_5, M5_UM5_5_LGP8_5_LGP7_line2); nand2 M5_UM5_5_LGP8_5_LGP7_Xo3(M5_UM5_5_LGP8_5_LGP7_NotB, M5_UM5_5_LGP8_5_InAMask, M5_UM5_5_LGP8_5_LGP7_line3); nand2 M5_UM5_5_LGP8_5_LGP7_Xo4(M5_UM5_5_LGP8_5_LGP7_line2, M5_UM5_5_LGP8_5_LGP7_line3, XPbus_5); inv M5_UM5_5_LGP8_5_LGP8(M5_Mode, M5_UM5_5_LGP8_5_NotMask); and2 M5_UM5_5_LGP8_5_LGP9(M5_Gbus_5, M5_UM5_5_LGP8_5_NotMask, M5_XGbus_5); inv M5_UM5_5_LGP8_6_LGP0_Mux2_0(MBbus_6, M5_UM5_5_LGP8_6_LGP0_Not_ContIn); and2 M5_UM5_5_LGP8_6_LGP0_Mux2_1(in190, M5_UM5_5_LGP8_6_LGP0_Not_ContIn, M5_UM5_5_LGP8_6_LGP0_line1); and2 M5_UM5_5_LGP8_6_LGP0_Mux2_2(in200, MBbus_6, M5_UM5_5_LGP8_6_LGP0_line2); or2 M5_UM5_5_LGP8_6_LGP0_Mux2_3(M5_UM5_5_LGP8_6_LGP0_line1, M5_UM5_5_LGP8_6_LGP0_line2, M5_UM5_5_LGP8_6_Mx0); inv M5_UM5_5_LGP8_6_LGP1_Mux2_0(MBbus_6, M5_UM5_5_LGP8_6_LGP1_Not_ContIn); and2 M5_UM5_5_LGP8_6_LGP1_Mux2_1(in179, M5_UM5_5_LGP8_6_LGP1_Not_ContIn, M5_UM5_5_LGP8_6_LGP1_line1); and2 M5_UM5_5_LGP8_6_LGP1_Mux2_2(in169, MBbus_6, M5_UM5_5_LGP8_6_LGP1_line2); or2 M5_UM5_5_LGP8_6_LGP1_Mux2_3(M5_UM5_5_LGP8_6_LGP1_line1, M5_UM5_5_LGP8_6_LGP1_line2, M5_UM5_5_LGP8_6_Mx1); and2 M5_UM5_5_LGP8_6_LGP2(MAbus_6, M5_UM5_5_LGP8_6_Mx1, M5_Gbus_6); or2 M5_UM5_5_LGP8_6_LGP3(MAbus_6, M5_UM5_5_LGP8_6_Mx0, M5_UM5_5_LGP8_6_InAMx0); nand2 M5_UM5_5_LGP8_6_LGP4(MAbus_6, M5_UM5_5_LGP8_6_Mx1, M5_UM5_5_LGP8_6_InAMx1); and2 M5_UM5_5_LGP8_6_LGP5(M5_UM5_5_LGP8_6_InAMx0, M5_UM5_5_LGP8_6_InAMx1, M5_Pbus_6); and2 M5_UM5_5_LGP8_6_LGP6(M5_Mask7_6, MAbus_6, M5_UM5_5_LGP8_6_InAMask); inv M5_UM5_5_LGP8_6_LGP7_Xo0(M5_UM5_5_LGP8_6_InAMask, M5_UM5_5_LGP8_6_LGP7_NotA); inv M5_UM5_5_LGP8_6_LGP7_Xo1(M5_Pbus_6, M5_UM5_5_LGP8_6_LGP7_NotB); nand2 M5_UM5_5_LGP8_6_LGP7_Xo2(M5_UM5_5_LGP8_6_LGP7_NotA, M5_Pbus_6, M5_UM5_5_LGP8_6_LGP7_line2); nand2 M5_UM5_5_LGP8_6_LGP7_Xo3(M5_UM5_5_LGP8_6_LGP7_NotB, M5_UM5_5_LGP8_6_InAMask, M5_UM5_5_LGP8_6_LGP7_line3); nand2 M5_UM5_5_LGP8_6_LGP7_Xo4(M5_UM5_5_LGP8_6_LGP7_line2, M5_UM5_5_LGP8_6_LGP7_line3, XPbus_6); inv M5_UM5_5_LGP8_6_LGP8(M5_Mask7_6, M5_UM5_5_LGP8_6_NotMask); and2 M5_UM5_5_LGP8_6_LGP9(M5_Gbus_6, M5_UM5_5_LGP8_6_NotMask, M5_XGbus_6); inv M5_UM5_5_LGP8_7_LGP0_Mux2_0(MBbus_7, M5_UM5_5_LGP8_7_LGP0_Not_ContIn); and2 M5_UM5_5_LGP8_7_LGP0_Mux2_1(in190, M5_UM5_5_LGP8_7_LGP0_Not_ContIn, M5_UM5_5_LGP8_7_LGP0_line1); and2 M5_UM5_5_LGP8_7_LGP0_Mux2_2(in200, MBbus_7, M5_UM5_5_LGP8_7_LGP0_line2); or2 M5_UM5_5_LGP8_7_LGP0_Mux2_3(M5_UM5_5_LGP8_7_LGP0_line1, M5_UM5_5_LGP8_7_LGP0_line2, M5_UM5_5_LGP8_7_Mx0); inv M5_UM5_5_LGP8_7_LGP1_Mux2_0(MBbus_7, M5_UM5_5_LGP8_7_LGP1_Not_ContIn); and2 M5_UM5_5_LGP8_7_LGP1_Mux2_1(in179, M5_UM5_5_LGP8_7_LGP1_Not_ContIn, M5_UM5_5_LGP8_7_LGP1_line1); and2 M5_UM5_5_LGP8_7_LGP1_Mux2_2(in169, MBbus_7, M5_UM5_5_LGP8_7_LGP1_line2); or2 M5_UM5_5_LGP8_7_LGP1_Mux2_3(M5_UM5_5_LGP8_7_LGP1_line1, M5_UM5_5_LGP8_7_LGP1_line2, M5_UM5_5_LGP8_7_Mx1); and2 M5_UM5_5_LGP8_7_LGP2(MAbus_7, M5_UM5_5_LGP8_7_Mx1, M5_Gbus_7); or2 M5_UM5_5_LGP8_7_LGP3(MAbus_7, M5_UM5_5_LGP8_7_Mx0, M5_UM5_5_LGP8_7_InAMx0); nand2 M5_UM5_5_LGP8_7_LGP4(MAbus_7, M5_UM5_5_LGP8_7_Mx1, M5_UM5_5_LGP8_7_InAMx1); and2 M5_UM5_5_LGP8_7_LGP5(M5_UM5_5_LGP8_7_InAMx0, M5_UM5_5_LGP8_7_InAMx1, M5_Pbus_7); and2 M5_UM5_5_LGP8_7_LGP6(M5_Mask7_6, MAbus_7, M5_UM5_5_LGP8_7_InAMask); inv M5_UM5_5_LGP8_7_LGP7_Xo0(M5_UM5_5_LGP8_7_InAMask, M5_UM5_5_LGP8_7_LGP7_NotA); inv M5_UM5_5_LGP8_7_LGP7_Xo1(M5_Pbus_7, M5_UM5_5_LGP8_7_LGP7_NotB); nand2 M5_UM5_5_LGP8_7_LGP7_Xo2(M5_UM5_5_LGP8_7_LGP7_NotA, M5_Pbus_7, M5_UM5_5_LGP8_7_LGP7_line2); nand2 M5_UM5_5_LGP8_7_LGP7_Xo3(M5_UM5_5_LGP8_7_LGP7_NotB, M5_UM5_5_LGP8_7_InAMask, M5_UM5_5_LGP8_7_LGP7_line3); nand2 M5_UM5_5_LGP8_7_LGP7_Xo4(M5_UM5_5_LGP8_7_LGP7_line2, M5_UM5_5_LGP8_7_LGP7_line3, XPbus_7); inv M5_UM5_5_LGP8_7_LGP8(M5_Mask7_6, M5_UM5_5_LGP8_7_NotMask); and2 M5_UM5_5_LGP8_7_LGP9(M5_Gbus_7, M5_UM5_5_LGP8_7_NotMask, M5_XGbus_7); and4 M5_UM5_6_CC0(M5_Pbus_0, M5_Pbus_1, M5_Pbus_2, M5_Pbus_3, M5_UM5_6_PropLo); and4 M5_UM5_6_CC1(M5_Pbus_4, M5_Pbus_5, M5_Pbus_6, M5_Pbus_7, M5_UM5_6_PropHi); and2 M5_UM5_6_CC2(M5_UM5_6_PropLo, M5_UM5_6_PropHi, out372); inv M5_UM5_6_CC3(M5_Mode, M5_UM5_6_NotMode); and4 M5_UM5_6_CC4_CCP0(MBbus_0, MBbus_1, MBbus_2, MBbus_3, M5_UM5_6_CC4_InBLoAND); nor4 M5_UM5_6_CC4_CCP1(MBbus_0, MBbus_1, MBbus_2, MBbus_3, M5_UM5_6_CC4_InBLoNOR); inv M5_UM5_6_CC4_CCP2_Mux2_0(in179, M5_UM5_6_CC4_CCP2_Not_ContIn); and2 M5_UM5_6_CC4_CCP2_Mux2_1(M5_UM5_6_CC4_InBLoAND, M5_UM5_6_CC4_CCP2_Not_ContIn, M5_UM5_6_CC4_CCP2_line1); and2 M5_UM5_6_CC4_CCP2_Mux2_2(M5_UM5_6_CC4_InBLoNOR, in179, M5_UM5_6_CC4_CCP2_line2); or2 M5_UM5_6_CC4_CCP2_Mux2_3(M5_UM5_6_CC4_CCP2_line1, M5_UM5_6_CC4_CCP2_line2, M5_UM5_6_CC4_InBprop); inv M5_UM5_6_CC4_CCP3_Mux2_0(M5_Mode, M5_UM5_6_CC4_CCP3_Not_ContIn); and2 M5_UM5_6_CC4_CCP3_Mux2_1(M5_UM5_6_PropLo, M5_UM5_6_CC4_CCP3_Not_ContIn, M5_UM5_6_CC4_CCP3_line1); and2 M5_UM5_6_CC4_CCP3_Mux2_2(M5_UM5_6_CC4_InBprop, M5_Mode, M5_UM5_6_CC4_CCP3_line2); or2 M5_UM5_6_CC4_CCP3_Mux2_3(M5_UM5_6_CC4_CCP3_line1, M5_UM5_6_CC4_CCP3_line2, M5_UM5_6_CC4_Pr); and2 M5_UM5_6_CC4_CCP4(in330, M5_UM5_6_CC4_Pr, M5_UM5_6_CinPropLo); and2 M5_UM5_6_CC5_Ao4a_0(M5_Pbus_3, M5_Gbus_2, M5_UM5_6_CC5_line0); and3 M5_UM5_6_CC5_Ao4a_1(M5_Pbus_3, M5_Pbus_2, M5_Gbus_1, M5_UM5_6_CC5_line1); and4 M5_UM5_6_CC5_Ao4a_2(M5_Pbus_3, M5_Pbus_2, M5_Pbus_1, M5_Gbus_0, M5_UM5_6_CC5_line2); or4 M5_UM5_6_CC5_Ao4a_3(M5_Gbus_3, M5_UM5_6_CC5_line0, M5_UM5_6_CC5_line1, M5_UM5_6_CC5_line2, M5_UM5_6_LocalC0Lo); and2 M5_UM5_6_CC6_Ao4a_0(M5_Pbus_7, M5_Gbus_6, M5_UM5_6_CC6_line0); and3 M5_UM5_6_CC6_Ao4a_1(M5_Pbus_7, M5_Pbus_6, M5_Gbus_5, M5_UM5_6_CC6_line1); and4 M5_UM5_6_CC6_Ao4a_2(M5_Pbus_7, M5_Pbus_6, M5_Pbus_5, M5_Gbus_4, M5_UM5_6_CC6_line2); or4 M5_UM5_6_CC6_Ao4a_3(M5_Gbus_7, M5_UM5_6_CC6_line0, M5_UM5_6_CC6_line1, M5_UM5_6_CC6_line2, M5_UM5_6_LocalC0Hi); and2 M5_UM5_6_CC7(M5_UM5_6_LocalC0Lo, M5_UM5_6_NotMode, M5_UM5_6_LoC0_M); and2 M5_UM5_6_CC8_Cb0_Cla4_0_Ao2_0(XPbus_0, gnd, M5_UM5_6_CC8_Cb0_Cla4_0_line0); or2 M5_UM5_6_CC8_Cb0_Cla4_0_Ao2_1(M5_XGbus_0, M5_UM5_6_CC8_Cb0_Cla4_0_line0, M5_UM5_6_CC8_Cy1bus_1); and2 M5_UM5_6_CC8_Cb0_Cla4_1_Ao3a_0(XPbus_1, M5_XGbus_0, M5_UM5_6_CC8_Cb0_Cla4_1_line0); and3 M5_UM5_6_CC8_Cb0_Cla4_1_Ao3a_1(XPbus_1, XPbus_0, gnd, M5_UM5_6_CC8_Cb0_Cla4_1_line1); or3 M5_UM5_6_CC8_Cb0_Cla4_1_Ao3a_2(M5_XGbus_1, M5_UM5_6_CC8_Cb0_Cla4_1_line0, M5_UM5_6_CC8_Cb0_Cla4_1_line1, M5_UM5_6_CC8_Cy1bus_2); and2 M5_UM5_6_CC8_Cb0_Cla4_2_Ao4a_0(XPbus_2, M5_XGbus_1, M5_UM5_6_CC8_Cb0_Cla4_2_line0); and3 M5_UM5_6_CC8_Cb0_Cla4_2_Ao4a_1(XPbus_2, XPbus_1, M5_XGbus_0, M5_UM5_6_CC8_Cb0_Cla4_2_line1); and4 M5_UM5_6_CC8_Cb0_Cla4_2_Ao4a_2(XPbus_2, XPbus_1, XPbus_0, gnd, M5_UM5_6_CC8_Cb0_Cla4_2_line2); or4 M5_UM5_6_CC8_Cb0_Cla4_2_Ao4a_3(M5_XGbus_2, M5_UM5_6_CC8_Cb0_Cla4_2_line0, M5_UM5_6_CC8_Cb0_Cla4_2_line1, M5_UM5_6_CC8_Cb0_Cla4_2_line2, M5_UM5_6_CC8_Cy1bus_3); and2 M5_UM5_6_CC8_Cb1_CP0(XPbus_0, in330, M5_UM5_6_CC8_Cy2bus_1); and3 M5_UM5_6_CC8_Cb1_CP1(XPbus_1, XPbus_0, in330, M5_UM5_6_CC8_Cy2bus_2); and4 M5_UM5_6_CC8_Cb1_CP2(XPbus_2, XPbus_1, XPbus_0, in330, M5_UM5_6_CC8_Cy2bus_3); inv M5_UM5_6_CC8_Cb2_X4_0_Xo0(gnd, M5_UM5_6_CC8_Cb2_X4_0_NotA); inv M5_UM5_6_CC8_Cb2_X4_0_Xo1(in330, M5_UM5_6_CC8_Cb2_X4_0_NotB); nand2 M5_UM5_6_CC8_Cb2_X4_0_Xo2(M5_UM5_6_CC8_Cb2_X4_0_NotA, in330, M5_UM5_6_CC8_Cb2_X4_0_line2); nand2 M5_UM5_6_CC8_Cb2_X4_0_Xo3(M5_UM5_6_CC8_Cb2_X4_0_NotB, gnd, M5_UM5_6_CC8_Cb2_X4_0_line3); nand2 M5_UM5_6_CC8_Cb2_X4_0_Xo4(M5_UM5_6_CC8_Cb2_X4_0_line2, M5_UM5_6_CC8_Cb2_X4_0_line3, XCarrybus_0); inv M5_UM5_6_CC8_Cb2_X4_1_Xo0(M5_UM5_6_CC8_Cy1bus_1, M5_UM5_6_CC8_Cb2_X4_1_NotA); inv M5_UM5_6_CC8_Cb2_X4_1_Xo1(M5_UM5_6_CC8_Cy2bus_1, M5_UM5_6_CC8_Cb2_X4_1_NotB); nand2 M5_UM5_6_CC8_Cb2_X4_1_Xo2(M5_UM5_6_CC8_Cb2_X4_1_NotA, M5_UM5_6_CC8_Cy2bus_1, M5_UM5_6_CC8_Cb2_X4_1_line2); nand2 M5_UM5_6_CC8_Cb2_X4_1_Xo3(M5_UM5_6_CC8_Cb2_X4_1_NotB, M5_UM5_6_CC8_Cy1bus_1, M5_UM5_6_CC8_Cb2_X4_1_line3); nand2 M5_UM5_6_CC8_Cb2_X4_1_Xo4(M5_UM5_6_CC8_Cb2_X4_1_line2, M5_UM5_6_CC8_Cb2_X4_1_line3, XCarrybus_1); inv M5_UM5_6_CC8_Cb2_X4_2_Xo0(M5_UM5_6_CC8_Cy1bus_2, M5_UM5_6_CC8_Cb2_X4_2_NotA); inv M5_UM5_6_CC8_Cb2_X4_2_Xo1(M5_UM5_6_CC8_Cy2bus_2, M5_UM5_6_CC8_Cb2_X4_2_NotB); nand2 M5_UM5_6_CC8_Cb2_X4_2_Xo2(M5_UM5_6_CC8_Cb2_X4_2_NotA, M5_UM5_6_CC8_Cy2bus_2, M5_UM5_6_CC8_Cb2_X4_2_line2); nand2 M5_UM5_6_CC8_Cb2_X4_2_Xo3(M5_UM5_6_CC8_Cb2_X4_2_NotB, M5_UM5_6_CC8_Cy1bus_2, M5_UM5_6_CC8_Cb2_X4_2_line3); nand2 M5_UM5_6_CC8_Cb2_X4_2_Xo4(M5_UM5_6_CC8_Cb2_X4_2_line2, M5_UM5_6_CC8_Cb2_X4_2_line3, XCarrybus_2); inv M5_UM5_6_CC8_Cb2_X4_3_Xo0(M5_UM5_6_CC8_Cy1bus_3, M5_UM5_6_CC8_Cb2_X4_3_NotA); inv M5_UM5_6_CC8_Cb2_X4_3_Xo1(M5_UM5_6_CC8_Cy2bus_3, M5_UM5_6_CC8_Cb2_X4_3_NotB); nand2 M5_UM5_6_CC8_Cb2_X4_3_Xo2(M5_UM5_6_CC8_Cb2_X4_3_NotA, M5_UM5_6_CC8_Cy2bus_3, M5_UM5_6_CC8_Cb2_X4_3_line2); nand2 M5_UM5_6_CC8_Cb2_X4_3_Xo3(M5_UM5_6_CC8_Cb2_X4_3_NotB, M5_UM5_6_CC8_Cy1bus_3, M5_UM5_6_CC8_Cb2_X4_3_line3); nand2 M5_UM5_6_CC8_Cb2_X4_3_Xo4(M5_UM5_6_CC8_Cb2_X4_3_line2, M5_UM5_6_CC8_Cb2_X4_3_line3, XCarrybus_3); and2 M5_UM5_6_CC9_Cb0_Cla4_0_Ao2_0(XPbus_4, M5_UM5_6_LoC0_M, M5_UM5_6_CC9_Cb0_Cla4_0_line0); or2 M5_UM5_6_CC9_Cb0_Cla4_0_Ao2_1(M5_XGbus_4, M5_UM5_6_CC9_Cb0_Cla4_0_line0, M5_UM5_6_CC9_Cy1bus_1); and2 M5_UM5_6_CC9_Cb0_Cla4_1_Ao3a_0(XPbus_5, M5_XGbus_4, M5_UM5_6_CC9_Cb0_Cla4_1_line0); and3 M5_UM5_6_CC9_Cb0_Cla4_1_Ao3a_1(XPbus_5, XPbus_4, M5_UM5_6_LoC0_M, M5_UM5_6_CC9_Cb0_Cla4_1_line1); or3 M5_UM5_6_CC9_Cb0_Cla4_1_Ao3a_2(M5_XGbus_5, M5_UM5_6_CC9_Cb0_Cla4_1_line0, M5_UM5_6_CC9_Cb0_Cla4_1_line1, M5_UM5_6_CC9_Cy1bus_2); and2 M5_UM5_6_CC9_Cb0_Cla4_2_Ao4a_0(XPbus_6, M5_XGbus_5, M5_UM5_6_CC9_Cb0_Cla4_2_line0); and3 M5_UM5_6_CC9_Cb0_Cla4_2_Ao4a_1(XPbus_6, XPbus_5, M5_XGbus_4, M5_UM5_6_CC9_Cb0_Cla4_2_line1); and4 M5_UM5_6_CC9_Cb0_Cla4_2_Ao4a_2(XPbus_6, XPbus_5, XPbus_4, M5_UM5_6_LoC0_M, M5_UM5_6_CC9_Cb0_Cla4_2_line2); or4 M5_UM5_6_CC9_Cb0_Cla4_2_Ao4a_3(M5_XGbus_6, M5_UM5_6_CC9_Cb0_Cla4_2_line0, M5_UM5_6_CC9_Cb0_Cla4_2_line1, M5_UM5_6_CC9_Cb0_Cla4_2_line2, M5_UM5_6_CC9_Cy1bus_3); and2 M5_UM5_6_CC9_Cb1_CP0(XPbus_4, M5_UM5_6_CinPropLo, M5_UM5_6_CC9_Cy2bus_1); and3 M5_UM5_6_CC9_Cb1_CP1(XPbus_5, XPbus_4, M5_UM5_6_CinPropLo, M5_UM5_6_CC9_Cy2bus_2); and4 M5_UM5_6_CC9_Cb1_CP2(XPbus_6, XPbus_5, XPbus_4, M5_UM5_6_CinPropLo, M5_UM5_6_CC9_Cy2bus_3); inv M5_UM5_6_CC9_Cb2_X4_0_Xo0(M5_UM5_6_LoC0_M, M5_UM5_6_CC9_Cb2_X4_0_NotA); inv M5_UM5_6_CC9_Cb2_X4_0_Xo1(M5_UM5_6_CinPropLo, M5_UM5_6_CC9_Cb2_X4_0_NotB); nand2 M5_UM5_6_CC9_Cb2_X4_0_Xo2(M5_UM5_6_CC9_Cb2_X4_0_NotA, M5_UM5_6_CinPropLo, M5_UM5_6_CC9_Cb2_X4_0_line2); nand2 M5_UM5_6_CC9_Cb2_X4_0_Xo3(M5_UM5_6_CC9_Cb2_X4_0_NotB, M5_UM5_6_LoC0_M, M5_UM5_6_CC9_Cb2_X4_0_line3); nand2 M5_UM5_6_CC9_Cb2_X4_0_Xo4(M5_UM5_6_CC9_Cb2_X4_0_line2, M5_UM5_6_CC9_Cb2_X4_0_line3, XCarrybus_4); inv M5_UM5_6_CC9_Cb2_X4_1_Xo0(M5_UM5_6_CC9_Cy1bus_1, M5_UM5_6_CC9_Cb2_X4_1_NotA); inv M5_UM5_6_CC9_Cb2_X4_1_Xo1(M5_UM5_6_CC9_Cy2bus_1, M5_UM5_6_CC9_Cb2_X4_1_NotB); nand2 M5_UM5_6_CC9_Cb2_X4_1_Xo2(M5_UM5_6_CC9_Cb2_X4_1_NotA, M5_UM5_6_CC9_Cy2bus_1, M5_UM5_6_CC9_Cb2_X4_1_line2); nand2 M5_UM5_6_CC9_Cb2_X4_1_Xo3(M5_UM5_6_CC9_Cb2_X4_1_NotB, M5_UM5_6_CC9_Cy1bus_1, M5_UM5_6_CC9_Cb2_X4_1_line3); nand2 M5_UM5_6_CC9_Cb2_X4_1_Xo4(M5_UM5_6_CC9_Cb2_X4_1_line2, M5_UM5_6_CC9_Cb2_X4_1_line3, XCarrybus_5); inv M5_UM5_6_CC9_Cb2_X4_2_Xo0(M5_UM5_6_CC9_Cy1bus_2, M5_UM5_6_CC9_Cb2_X4_2_NotA); inv M5_UM5_6_CC9_Cb2_X4_2_Xo1(M5_UM5_6_CC9_Cy2bus_2, M5_UM5_6_CC9_Cb2_X4_2_NotB); nand2 M5_UM5_6_CC9_Cb2_X4_2_Xo2(M5_UM5_6_CC9_Cb2_X4_2_NotA, M5_UM5_6_CC9_Cy2bus_2, M5_UM5_6_CC9_Cb2_X4_2_line2); nand2 M5_UM5_6_CC9_Cb2_X4_2_Xo3(M5_UM5_6_CC9_Cb2_X4_2_NotB, M5_UM5_6_CC9_Cy1bus_2, M5_UM5_6_CC9_Cb2_X4_2_line3); nand2 M5_UM5_6_CC9_Cb2_X4_2_Xo4(M5_UM5_6_CC9_Cb2_X4_2_line2, M5_UM5_6_CC9_Cb2_X4_2_line3, XCarrybus_6); inv M5_UM5_6_CC9_Cb2_X4_3_Xo0(M5_UM5_6_CC9_Cy1bus_3, M5_UM5_6_CC9_Cb2_X4_3_NotA); inv M5_UM5_6_CC9_Cb2_X4_3_Xo1(M5_UM5_6_CC9_Cy2bus_3, M5_UM5_6_CC9_Cb2_X4_3_NotB); nand2 M5_UM5_6_CC9_Cb2_X4_3_Xo2(M5_UM5_6_CC9_Cb2_X4_3_NotA, M5_UM5_6_CC9_Cy2bus_3, M5_UM5_6_CC9_Cb2_X4_3_line2); nand2 M5_UM5_6_CC9_Cb2_X4_3_Xo3(M5_UM5_6_CC9_Cb2_X4_3_NotB, M5_UM5_6_CC9_Cy1bus_3, M5_UM5_6_CC9_Cb2_X4_3_line3); nand2 M5_UM5_6_CC9_Cb2_X4_3_Xo4(M5_UM5_6_CC9_Cb2_X4_3_line2, M5_UM5_6_CC9_Cb2_X4_3_line3, XCarrybus_7); and2 M5_UM5_6_CC10_Ao2_0(M5_UM5_6_LocalC0Lo, M5_UM5_6_PropHi, M5_UM5_6_CC10_line0); or2 M5_UM5_6_CC10_Ao2_1(M5_UM5_6_LocalC0Hi, M5_UM5_6_CC10_line0, out369); or2 M5_UM5_6_CC11(M5_UM5_6_CinPropLo, M5_UM5_6_LoC0_M, Carry4); and2 M5_UM5_6_CC12(M5_UM5_6_CinPropLo, M5_UM5_6_PropHi, M5_UM5_6_line12); or2 M5_UM5_6_CC13(out369, M5_UM5_6_line12, Cout); and2 M5_UM5_6_CC14_Ao2_0(M5_UM5_6_LoC0_M, M5_UM5_6_PropHi, M5_UM5_6_CC14_line0); or2 M5_UM5_6_CC14_Ao2_1(M5_UM5_6_LocalC0Hi, M5_UM5_6_CC14_line0, M5_UM5_6_Cout_M_in0); inv M5_UM5_6_CC15_Xo0(M5_UM5_6_Cout_M_in0, M5_UM5_6_CC15_NotA); inv M5_UM5_6_CC15_Xo1(M5_UM5_6_line12, M5_UM5_6_CC15_NotB); nand2 M5_UM5_6_CC15_Xo2(M5_UM5_6_CC15_NotA, M5_UM5_6_line12, M5_UM5_6_CC15_line2); nand2 M5_UM5_6_CC15_Xo3(M5_UM5_6_CC15_NotB, M5_UM5_6_Cout_M_in0, M5_UM5_6_CC15_line3); nand2 M5_UM5_6_CC15_Xo4(M5_UM5_6_CC15_line2, M5_UM5_6_CC15_line3, M5_UM5_6_Ovf_Carry8); inv M5_UM5_6_CC16_Xo0(M5_UM5_6_Ovf_Carry8, M5_UM5_6_CC16_NotA); inv M5_UM5_6_CC16_Xo1(XCarrybus_7, M5_UM5_6_CC16_NotB); nand2 M5_UM5_6_CC16_Xo2(M5_UM5_6_CC16_NotA, XCarrybus_7, M5_UM5_6_CC16_line2); nand2 M5_UM5_6_CC16_Xo3(M5_UM5_6_CC16_NotB, M5_UM5_6_Ovf_Carry8, M5_UM5_6_CC16_line3); nand2 M5_UM5_6_CC16_Xo4(M5_UM5_6_CC16_line2, M5_UM5_6_CC16_line3, Overflow); inv M6_X8_0_X4_0_Xo0(XPbus_0, M6_X8_0_X4_0_NotA); inv M6_X8_0_X4_0_Xo1(XCarrybus_0, M6_X8_0_X4_0_NotB); nand2 M6_X8_0_X4_0_Xo2(M6_X8_0_X4_0_NotA, XCarrybus_0, M6_X8_0_X4_0_line2); nand2 M6_X8_0_X4_0_Xo3(M6_X8_0_X4_0_NotB, XPbus_0, M6_X8_0_X4_0_line3); nand2 M6_X8_0_X4_0_Xo4(M6_X8_0_X4_0_line2, M6_X8_0_X4_0_line3, Funcbus_0); inv M6_X8_0_X4_1_Xo0(XPbus_1, M6_X8_0_X4_1_NotA); inv M6_X8_0_X4_1_Xo1(XCarrybus_1, M6_X8_0_X4_1_NotB); nand2 M6_X8_0_X4_1_Xo2(M6_X8_0_X4_1_NotA, XCarrybus_1, M6_X8_0_X4_1_line2); nand2 M6_X8_0_X4_1_Xo3(M6_X8_0_X4_1_NotB, XPbus_1, M6_X8_0_X4_1_line3); nand2 M6_X8_0_X4_1_Xo4(M6_X8_0_X4_1_line2, M6_X8_0_X4_1_line3, Funcbus_1); inv M6_X8_0_X4_2_Xo0(XPbus_2, M6_X8_0_X4_2_NotA); inv M6_X8_0_X4_2_Xo1(XCarrybus_2, M6_X8_0_X4_2_NotB); nand2 M6_X8_0_X4_2_Xo2(M6_X8_0_X4_2_NotA, XCarrybus_2, M6_X8_0_X4_2_line2); nand2 M6_X8_0_X4_2_Xo3(M6_X8_0_X4_2_NotB, XPbus_2, M6_X8_0_X4_2_line3); nand2 M6_X8_0_X4_2_Xo4(M6_X8_0_X4_2_line2, M6_X8_0_X4_2_line3, Funcbus_2); inv M6_X8_0_X4_3_Xo0(XPbus_3, M6_X8_0_X4_3_NotA); inv M6_X8_0_X4_3_Xo1(XCarrybus_3, M6_X8_0_X4_3_NotB); nand2 M6_X8_0_X4_3_Xo2(M6_X8_0_X4_3_NotA, XCarrybus_3, M6_X8_0_X4_3_line2); nand2 M6_X8_0_X4_3_Xo3(M6_X8_0_X4_3_NotB, XPbus_3, M6_X8_0_X4_3_line3); nand2 M6_X8_0_X4_3_Xo4(M6_X8_0_X4_3_line2, M6_X8_0_X4_3_line3, Funcbus_3); inv M6_X8_1_X4_0_Xo0(XPbus_4, M6_X8_1_X4_0_NotA); inv M6_X8_1_X4_0_Xo1(XCarrybus_4, M6_X8_1_X4_0_NotB); nand2 M6_X8_1_X4_0_Xo2(M6_X8_1_X4_0_NotA, XCarrybus_4, M6_X8_1_X4_0_line2); nand2 M6_X8_1_X4_0_Xo3(M6_X8_1_X4_0_NotB, XPbus_4, M6_X8_1_X4_0_line3); nand2 M6_X8_1_X4_0_Xo4(M6_X8_1_X4_0_line2, M6_X8_1_X4_0_line3, Funcbus_4); inv M6_X8_1_X4_1_Xo0(XPbus_5, M6_X8_1_X4_1_NotA); inv M6_X8_1_X4_1_Xo1(XCarrybus_5, M6_X8_1_X4_1_NotB); nand2 M6_X8_1_X4_1_Xo2(M6_X8_1_X4_1_NotA, XCarrybus_5, M6_X8_1_X4_1_line2); nand2 M6_X8_1_X4_1_Xo3(M6_X8_1_X4_1_NotB, XPbus_5, M6_X8_1_X4_1_line3); nand2 M6_X8_1_X4_1_Xo4(M6_X8_1_X4_1_line2, M6_X8_1_X4_1_line3, Funcbus_5); inv M6_X8_1_X4_2_Xo0(XPbus_6, M6_X8_1_X4_2_NotA); inv M6_X8_1_X4_2_Xo1(XCarrybus_6, M6_X8_1_X4_2_NotB); nand2 M6_X8_1_X4_2_Xo2(M6_X8_1_X4_2_NotA, XCarrybus_6, M6_X8_1_X4_2_line2); nand2 M6_X8_1_X4_2_Xo3(M6_X8_1_X4_2_NotB, XPbus_6, M6_X8_1_X4_2_line3); nand2 M6_X8_1_X4_2_Xo4(M6_X8_1_X4_2_line2, M6_X8_1_X4_2_line3, Funcbus_6); inv M6_X8_1_X4_3_Xo0(XPbus_7, M6_X8_1_X4_3_NotA); inv M6_X8_1_X4_3_Xo1(XCarrybus_7, M6_X8_1_X4_3_NotB); nand2 M6_X8_1_X4_3_Xo2(M6_X8_1_X4_3_NotA, XCarrybus_7, M6_X8_1_X4_3_line2); nand2 M6_X8_1_X4_3_Xo3(M6_X8_1_X4_3_NotB, XPbus_7, M6_X8_1_X4_3_line3); nand2 M6_X8_1_X4_3_Xo4(M6_X8_1_X4_3_line2, M6_X8_1_X4_3_line3, Funcbus_7); inv M7_UM7_0_Bsd0(Carry4, M7_UM7_0_NotCarry); inv M7_UM7_0_Bsd1_Xo0(Funcbus_1, M7_UM7_0_Bsd1_NotA); inv M7_UM7_0_Bsd1_Xo1(M7_UM7_0_NotCarry, M7_UM7_0_Bsd1_NotB); nand2 M7_UM7_0_Bsd1_Xo2(M7_UM7_0_Bsd1_NotA, M7_UM7_0_NotCarry, M7_UM7_0_Bsd1_line2); nand2 M7_UM7_0_Bsd1_Xo3(M7_UM7_0_Bsd1_NotB, Funcbus_1, M7_UM7_0_Bsd1_line3); nand2 M7_UM7_0_Bsd1_Xo4(M7_UM7_0_Bsd1_line2, M7_UM7_0_Bsd1_line3, F_BCDbus_1); and2 M7_UM7_0_Bsd2(Funcbus_1, M7_UM7_0_NotCarry, M7_UM7_0_line2); inv M7_UM7_0_Bsd3_Xo0(Funcbus_2, M7_UM7_0_Bsd3_NotA); inv M7_UM7_0_Bsd3_Xo1(M7_UM7_0_line2, M7_UM7_0_Bsd3_NotB); nand2 M7_UM7_0_Bsd3_Xo2(M7_UM7_0_Bsd3_NotA, M7_UM7_0_line2, M7_UM7_0_Bsd3_line2); nand2 M7_UM7_0_Bsd3_Xo3(M7_UM7_0_Bsd3_NotB, Funcbus_2, M7_UM7_0_Bsd3_line3); nand2 M7_UM7_0_Bsd3_Xo4(M7_UM7_0_Bsd3_line2, M7_UM7_0_Bsd3_line3, F_BCDbus_2); and4 M7_UM7_0_Bsd4(Funcbus_3, Funcbus_2, Funcbus_1, M7_UM7_0_NotCarry, M7_UM7_0_line4); and2 M7_UM7_0_Bsd5(Funcbus_3, Carry4, M7_UM7_0_line5); or2 M7_UM7_0_Bsd6(M7_UM7_0_line4, M7_UM7_0_line5, F_BCDbus_3); inv M7_UM7_1_Bsd0(Cout, M7_UM7_1_NotCarry); inv M7_UM7_1_Bsd1_Xo0(Funcbus_5, M7_UM7_1_Bsd1_NotA); inv M7_UM7_1_Bsd1_Xo1(M7_UM7_1_NotCarry, M7_UM7_1_Bsd1_NotB); nand2 M7_UM7_1_Bsd1_Xo2(M7_UM7_1_Bsd1_NotA, M7_UM7_1_NotCarry, M7_UM7_1_Bsd1_line2); nand2 M7_UM7_1_Bsd1_Xo3(M7_UM7_1_Bsd1_NotB, Funcbus_5, M7_UM7_1_Bsd1_line3); nand2 M7_UM7_1_Bsd1_Xo4(M7_UM7_1_Bsd1_line2, M7_UM7_1_Bsd1_line3, F_BCDbus_5); and2 M7_UM7_1_Bsd2(Funcbus_5, M7_UM7_1_NotCarry, M7_UM7_1_line2); inv M7_UM7_1_Bsd3_Xo0(Funcbus_6, M7_UM7_1_Bsd3_NotA); inv M7_UM7_1_Bsd3_Xo1(M7_UM7_1_line2, M7_UM7_1_Bsd3_NotB); nand2 M7_UM7_1_Bsd3_Xo2(M7_UM7_1_Bsd3_NotA, M7_UM7_1_line2, M7_UM7_1_Bsd3_line2); nand2 M7_UM7_1_Bsd3_Xo3(M7_UM7_1_Bsd3_NotB, Funcbus_6, M7_UM7_1_Bsd3_line3); nand2 M7_UM7_1_Bsd3_Xo4(M7_UM7_1_Bsd3_line2, M7_UM7_1_Bsd3_line3, F_BCDbus_6); and4 M7_UM7_1_Bsd4(Funcbus_7, Funcbus_6, Funcbus_5, M7_UM7_1_NotCarry, M7_UM7_1_line4); and2 M7_UM7_1_Bsd5(Funcbus_7, Cout, M7_UM7_1_line5); or2 M7_UM7_1_Bsd6(M7_UM7_1_line4, M7_UM7_1_line5, F_BCDbus_7); and2 M8_UM8_0_DCS0(in20, in179, M8_UM8_0_tmp0); inv M8_UM8_0_DCS1(M8_UM8_0_tmp0, M8_UM8_0_tmp1); inv M8_UM8_0_DCS2(in20, M8_UM8_0_tmp2); nand2 M8_UM8_0_DCS3(in20, in200, M8_UM8_0_tmp3); and2 M8_UM8_0_DCS4(in20, in200, M8_UM8_0_tmp4); nor2 M8_UM8_0_DCS5(M8_UM8_0_tmp2, in190, M8_UM8_0_tmp5); and2 M8_UM8_0_DCS6(M8_UM8_0_tmp3, M8_UM8_0_tmp1, M8_UM8_0_tmp6); and2 M8_UM8_0_DCS7(M8_UM8_0_tmp4, M8_UM8_0_tmp1, M8_UM8_0_tmp7); or2 M8_UM8_0_DCS8(M8_UM8_0_tmp2, in190, M8_UM8_0_tmp8); inv M8_UM8_0_DCS9(in200, M8_UM8_0_tmp9); and2 M8_UM8_0_DCS10(M8_UM8_0_tmp9, M8_UM8_0_tmp0, M8_UM8_0_tmp10); and2 M8_UM8_0_DCS11(in200, M8_UM8_0_tmp0, M8_UM8_0_tmp11); and2 M8_UM8_0_DCS13(M8_UM8_0_tmp5, M8_UM8_0_tmp7, M8_ContShift_0); and2 M8_UM8_0_DCS14(M8_UM8_0_tmp6, M8_UM8_0_tmp8, M8_ContShift_1); and2 M8_UM8_0_DCS15(M8_UM8_0_tmp8, M8_UM8_0_tmp7, M8_ContShift_2); and2 M8_UM8_0_DCS16(M8_UM8_0_tmp5, M8_UM8_0_tmp10, M8_ContShift_3); and2 M8_UM8_0_DCS17(M8_UM8_0_tmp5, M8_UM8_0_tmp11, M8_ContShift_4); and2 M8_UM8_0_DCS18(M8_UM8_0_tmp8, M8_UM8_0_tmp10, M8_ContShift_5); and2 M8_UM8_0_DCS19(M8_UM8_0_tmp8, M8_UM8_0_tmp11, M8_ContShift_6); and2 M8_UM8_0_DCS12(M8_UM8_0_tmp5, M8_UM8_0_tmp6, M8_ContShift_7); and2 M8_UM8_1_M8_0_M0(in107, M8_ContShift_0, M8_UM8_1_M8_0_t0); and2 M8_UM8_1_M8_0_M1(in97, M8_ContShift_1, M8_UM8_1_M8_0_t1); and2 M8_UM8_1_M8_0_M2(in87, M8_ContShift_2, M8_UM8_1_M8_0_t2); and2 M8_UM8_1_M8_0_M3(in77, M8_ContShift_3, M8_UM8_1_M8_0_t3); and2 M8_UM8_1_M8_0_M4(in68, M8_ContShift_4, M8_UM8_1_M8_0_t4); and2 M8_UM8_1_M8_0_M5(in58, M8_ContShift_5, M8_UM8_1_M8_0_t5); and2 M8_UM8_1_M8_0_M6(in50, M8_ContShift_6, M8_UM8_1_M8_0_t6); and2 M8_UM8_1_M8_0_M7(in159, M8_ContShift_7, M8_UM8_1_M8_0_t7); or8 M8_UM8_1_M8_0_M8(M8_UM8_1_M8_0_t0, M8_UM8_1_M8_0_t1, M8_UM8_1_M8_0_t2, M8_UM8_1_M8_0_t3, M8_UM8_1_M8_0_t4, M8_UM8_1_M8_0_t5, M8_UM8_1_M8_0_t6, M8_UM8_1_M8_0_t7, M8_ShiftQout_0); and2 M8_UM8_1_M8_1_M0(in97, M8_ContShift_0, M8_UM8_1_M8_1_t0); and2 M8_UM8_1_M8_1_M1(in87, M8_ContShift_1, M8_UM8_1_M8_1_t1); and2 M8_UM8_1_M8_1_M2(in77, M8_ContShift_2, M8_UM8_1_M8_1_t2); and2 M8_UM8_1_M8_1_M3(in68, M8_ContShift_3, M8_UM8_1_M8_1_t3); and2 M8_UM8_1_M8_1_M4(in58, M8_ContShift_4, M8_UM8_1_M8_1_t4); and2 M8_UM8_1_M8_1_M5(in50, M8_ContShift_5, M8_UM8_1_M8_1_t5); and2 M8_UM8_1_M8_1_M6(in159, M8_ContShift_6, M8_UM8_1_M8_1_t6); and2 M8_UM8_1_M8_1_M7(in150, M8_ContShift_7, M8_UM8_1_M8_1_t7); or8 M8_UM8_1_M8_1_M8(M8_UM8_1_M8_1_t0, M8_UM8_1_M8_1_t1, M8_UM8_1_M8_1_t2, M8_UM8_1_M8_1_t3, M8_UM8_1_M8_1_t4, M8_UM8_1_M8_1_t5, M8_UM8_1_M8_1_t6, M8_UM8_1_M8_1_t7, M8_ShiftQout_1); and2 M8_UM8_1_M8_2_M0(in87, M8_ContShift_0, M8_UM8_1_M8_2_t0); and2 M8_UM8_1_M8_2_M1(in77, M8_ContShift_1, M8_UM8_1_M8_2_t1); and2 M8_UM8_1_M8_2_M2(in68, M8_ContShift_2, M8_UM8_1_M8_2_t2); and2 M8_UM8_1_M8_2_M3(in58, M8_ContShift_3, M8_UM8_1_M8_2_t3); and2 M8_UM8_1_M8_2_M4(in50, M8_ContShift_4, M8_UM8_1_M8_2_t4); and2 M8_UM8_1_M8_2_M5(in159, M8_ContShift_5, M8_UM8_1_M8_2_t5); and2 M8_UM8_1_M8_2_M6(in150, M8_ContShift_6, M8_UM8_1_M8_2_t6); and2 M8_UM8_1_M8_2_M7(in143, M8_ContShift_7, M8_UM8_1_M8_2_t7); or8 M8_UM8_1_M8_2_M8(M8_UM8_1_M8_2_t0, M8_UM8_1_M8_2_t1, M8_UM8_1_M8_2_t2, M8_UM8_1_M8_2_t3, M8_UM8_1_M8_2_t4, M8_UM8_1_M8_2_t5, M8_UM8_1_M8_2_t6, M8_UM8_1_M8_2_t7, M8_ShiftQout_2); and2 M8_UM8_1_M8_3_M0(in77, M8_ContShift_0, M8_UM8_1_M8_3_t0); and2 M8_UM8_1_M8_3_M1(in68, M8_ContShift_1, M8_UM8_1_M8_3_t1); and2 M8_UM8_1_M8_3_M2(in58, M8_ContShift_2, M8_UM8_1_M8_3_t2); and2 M8_UM8_1_M8_3_M3(in50, M8_ContShift_3, M8_UM8_1_M8_3_t3); and2 M8_UM8_1_M8_3_M4(in159, M8_ContShift_4, M8_UM8_1_M8_3_t4); and2 M8_UM8_1_M8_3_M5(in150, M8_ContShift_5, M8_UM8_1_M8_3_t5); and2 M8_UM8_1_M8_3_M6(in143, M8_ContShift_6, M8_UM8_1_M8_3_t6); and2 M8_UM8_1_M8_3_M7(in137, M8_ContShift_7, M8_UM8_1_M8_3_t7); or8 M8_UM8_1_M8_3_M8(M8_UM8_1_M8_3_t0, M8_UM8_1_M8_3_t1, M8_UM8_1_M8_3_t2, M8_UM8_1_M8_3_t3, M8_UM8_1_M8_3_t4, M8_UM8_1_M8_3_t5, M8_UM8_1_M8_3_t6, M8_UM8_1_M8_3_t7, M8_ShiftQout_3); and2 M8_UM8_1_M8_4_M0(in68, M8_ContShift_0, M8_UM8_1_M8_4_t0); and2 M8_UM8_1_M8_4_M1(in58, M8_ContShift_1, M8_UM8_1_M8_4_t1); and2 M8_UM8_1_M8_4_M2(in50, M8_ContShift_2, M8_UM8_1_M8_4_t2); and2 M8_UM8_1_M8_4_M3(in159, M8_ContShift_3, M8_UM8_1_M8_4_t3); and2 M8_UM8_1_M8_4_M4(in150, M8_ContShift_4, M8_UM8_1_M8_4_t4); and2 M8_UM8_1_M8_4_M5(in143, M8_ContShift_5, M8_UM8_1_M8_4_t5); and2 M8_UM8_1_M8_4_M6(in137, M8_ContShift_6, M8_UM8_1_M8_4_t6); and2 M8_UM8_1_M8_4_M7(in132, M8_ContShift_7, M8_UM8_1_M8_4_t7); or8 M8_UM8_1_M8_4_M8(M8_UM8_1_M8_4_t0, M8_UM8_1_M8_4_t1, M8_UM8_1_M8_4_t2, M8_UM8_1_M8_4_t3, M8_UM8_1_M8_4_t4, M8_UM8_1_M8_4_t5, M8_UM8_1_M8_4_t6, M8_UM8_1_M8_4_t7, M8_ShiftQout_4); and2 M8_UM8_1_M8_5_M0(in58, M8_ContShift_0, M8_UM8_1_M8_5_t0); and2 M8_UM8_1_M8_5_M1(in50, M8_ContShift_1, M8_UM8_1_M8_5_t1); and2 M8_UM8_1_M8_5_M2(in159, M8_ContShift_2, M8_UM8_1_M8_5_t2); and2 M8_UM8_1_M8_5_M3(in150, M8_ContShift_3, M8_UM8_1_M8_5_t3); and2 M8_UM8_1_M8_5_M4(in143, M8_ContShift_4, M8_UM8_1_M8_5_t4); and2 M8_UM8_1_M8_5_M5(in137, M8_ContShift_5, M8_UM8_1_M8_5_t5); and2 M8_UM8_1_M8_5_M6(in132, M8_ContShift_6, M8_UM8_1_M8_5_t6); and2 M8_UM8_1_M8_5_M7(in128, M8_ContShift_7, M8_UM8_1_M8_5_t7); or8 M8_UM8_1_M8_5_M8(M8_UM8_1_M8_5_t0, M8_UM8_1_M8_5_t1, M8_UM8_1_M8_5_t2, M8_UM8_1_M8_5_t3, M8_UM8_1_M8_5_t4, M8_UM8_1_M8_5_t5, M8_UM8_1_M8_5_t6, M8_UM8_1_M8_5_t7, M8_ShiftQout_5); and2 M8_UM8_1_M8_6_M0(in50, M8_ContShift_0, M8_UM8_1_M8_6_t0); and2 M8_UM8_1_M8_6_M1(in159, M8_ContShift_1, M8_UM8_1_M8_6_t1); and2 M8_UM8_1_M8_6_M2(in150, M8_ContShift_2, M8_UM8_1_M8_6_t2); and2 M8_UM8_1_M8_6_M3(in143, M8_ContShift_3, M8_UM8_1_M8_6_t3); and2 M8_UM8_1_M8_6_M4(in137, M8_ContShift_4, M8_UM8_1_M8_6_t4); and2 M8_UM8_1_M8_6_M5(in132, M8_ContShift_5, M8_UM8_1_M8_6_t5); and2 M8_UM8_1_M8_6_M6(in128, M8_ContShift_6, M8_UM8_1_M8_6_t6); and2 M8_UM8_1_M8_6_M7(in125, M8_ContShift_7, M8_UM8_1_M8_6_t7); or8 M8_UM8_1_M8_6_M8(M8_UM8_1_M8_6_t0, M8_UM8_1_M8_6_t1, M8_UM8_1_M8_6_t2, M8_UM8_1_M8_6_t3, M8_UM8_1_M8_6_t4, M8_UM8_1_M8_6_t5, M8_UM8_1_M8_6_t6, M8_UM8_1_M8_6_t7, M8_ShiftQout_6); and2 M8_UM8_1_M8_7_M0(in159, M8_ContShift_0, M8_UM8_1_M8_7_t0); and2 M8_UM8_1_M8_7_M1(in150, M8_ContShift_1, M8_UM8_1_M8_7_t1); and2 M8_UM8_1_M8_7_M2(in143, M8_ContShift_2, M8_UM8_1_M8_7_t2); and2 M8_UM8_1_M8_7_M3(in137, M8_ContShift_3, M8_UM8_1_M8_7_t3); and2 M8_UM8_1_M8_7_M4(in132, M8_ContShift_4, M8_UM8_1_M8_7_t4); and2 M8_UM8_1_M8_7_M5(in128, M8_ContShift_5, M8_UM8_1_M8_7_t5); and2 M8_UM8_1_M8_7_M6(in125, M8_ContShift_6, M8_UM8_1_M8_7_t6); and2 M8_UM8_1_M8_7_M7(in124, M8_ContShift_7, M8_UM8_1_M8_7_t7); or8 M8_UM8_1_M8_7_M8(M8_UM8_1_M8_7_t0, M8_UM8_1_M8_7_t1, M8_UM8_1_M8_7_t2, M8_UM8_1_M8_7_t3, M8_UM8_1_M8_7_t4, M8_UM8_1_M8_7_t5, M8_UM8_1_M8_7_t6, M8_UM8_1_M8_7_t7, M8_ShiftQout_7); and2 M8_UM8_2_M8_0_M0(in283, M8_ContShift_0, M8_UM8_2_M8_0_t0); and2 M8_UM8_2_M8_0_M1(in294, M8_ContShift_1, M8_UM8_2_M8_0_t1); and2 M8_UM8_2_M8_0_M2(in303, M8_ContShift_2, M8_UM8_2_M8_0_t2); and2 M8_UM8_2_M8_0_M3(in311, M8_ContShift_3, M8_UM8_2_M8_0_t3); and2 M8_UM8_2_M8_0_M4(in317, M8_ContShift_4, M8_UM8_2_M8_0_t4); and2 M8_UM8_2_M8_0_M5(in322, M8_ContShift_5, M8_UM8_2_M8_0_t5); and2 M8_UM8_2_M8_0_M6(in326, M8_ContShift_6, M8_UM8_2_M8_0_t6); and2 M8_UM8_2_M8_0_M7(in329, M8_ContShift_7, M8_UM8_2_M8_0_t7); or8 M8_UM8_2_M8_0_M8(M8_UM8_2_M8_0_t0, M8_UM8_2_M8_0_t1, M8_UM8_2_M8_0_t2, M8_UM8_2_M8_0_t3, M8_UM8_2_M8_0_t4, M8_UM8_2_M8_0_t5, M8_UM8_2_M8_0_t6, M8_UM8_2_M8_0_t7, M8_ShiftRout_0); and2 M8_UM8_2_M8_1_M0(in116, M8_ContShift_0, M8_UM8_2_M8_1_t0); and2 M8_UM8_2_M8_1_M1(in283, M8_ContShift_1, M8_UM8_2_M8_1_t1); and2 M8_UM8_2_M8_1_M2(in294, M8_ContShift_2, M8_UM8_2_M8_1_t2); and2 M8_UM8_2_M8_1_M3(in303, M8_ContShift_3, M8_UM8_2_M8_1_t3); and2 M8_UM8_2_M8_1_M4(in311, M8_ContShift_4, M8_UM8_2_M8_1_t4); and2 M8_UM8_2_M8_1_M5(in317, M8_ContShift_5, M8_UM8_2_M8_1_t5); and2 M8_UM8_2_M8_1_M6(in322, M8_ContShift_6, M8_UM8_2_M8_1_t6); and2 M8_UM8_2_M8_1_M7(in326, M8_ContShift_7, M8_UM8_2_M8_1_t7); or8 M8_UM8_2_M8_1_M8(M8_UM8_2_M8_1_t0, M8_UM8_2_M8_1_t1, M8_UM8_2_M8_1_t2, M8_UM8_2_M8_1_t3, M8_UM8_2_M8_1_t4, M8_UM8_2_M8_1_t5, M8_UM8_2_M8_1_t6, M8_UM8_2_M8_1_t7, M8_ShiftRout_1); and2 M8_UM8_2_M8_2_M0(in107, M8_ContShift_0, M8_UM8_2_M8_2_t0); and2 M8_UM8_2_M8_2_M1(in116, M8_ContShift_1, M8_UM8_2_M8_2_t1); and2 M8_UM8_2_M8_2_M2(in283, M8_ContShift_2, M8_UM8_2_M8_2_t2); and2 M8_UM8_2_M8_2_M3(in294, M8_ContShift_3, M8_UM8_2_M8_2_t3); and2 M8_UM8_2_M8_2_M4(in303, M8_ContShift_4, M8_UM8_2_M8_2_t4); and2 M8_UM8_2_M8_2_M5(in311, M8_ContShift_5, M8_UM8_2_M8_2_t5); and2 M8_UM8_2_M8_2_M6(in317, M8_ContShift_6, M8_UM8_2_M8_2_t6); and2 M8_UM8_2_M8_2_M7(in322, M8_ContShift_7, M8_UM8_2_M8_2_t7); or8 M8_UM8_2_M8_2_M8(M8_UM8_2_M8_2_t0, M8_UM8_2_M8_2_t1, M8_UM8_2_M8_2_t2, M8_UM8_2_M8_2_t3, M8_UM8_2_M8_2_t4, M8_UM8_2_M8_2_t5, M8_UM8_2_M8_2_t6, M8_UM8_2_M8_2_t7, M8_ShiftRout_2); and2 M8_UM8_2_M8_3_M0(in97, M8_ContShift_0, M8_UM8_2_M8_3_t0); and2 M8_UM8_2_M8_3_M1(in107, M8_ContShift_1, M8_UM8_2_M8_3_t1); and2 M8_UM8_2_M8_3_M2(in116, M8_ContShift_2, M8_UM8_2_M8_3_t2); and2 M8_UM8_2_M8_3_M3(in283, M8_ContShift_3, M8_UM8_2_M8_3_t3); and2 M8_UM8_2_M8_3_M4(in294, M8_ContShift_4, M8_UM8_2_M8_3_t4); and2 M8_UM8_2_M8_3_M5(in303, M8_ContShift_5, M8_UM8_2_M8_3_t5); and2 M8_UM8_2_M8_3_M6(in311, M8_ContShift_6, M8_UM8_2_M8_3_t6); and2 M8_UM8_2_M8_3_M7(in317, M8_ContShift_7, M8_UM8_2_M8_3_t7); or8 M8_UM8_2_M8_3_M8(M8_UM8_2_M8_3_t0, M8_UM8_2_M8_3_t1, M8_UM8_2_M8_3_t2, M8_UM8_2_M8_3_t3, M8_UM8_2_M8_3_t4, M8_UM8_2_M8_3_t5, M8_UM8_2_M8_3_t6, M8_UM8_2_M8_3_t7, M8_ShiftRout_3); and2 M8_UM8_2_M8_4_M0(in87, M8_ContShift_0, M8_UM8_2_M8_4_t0); and2 M8_UM8_2_M8_4_M1(in97, M8_ContShift_1, M8_UM8_2_M8_4_t1); and2 M8_UM8_2_M8_4_M2(in107, M8_ContShift_2, M8_UM8_2_M8_4_t2); and2 M8_UM8_2_M8_4_M3(in116, M8_ContShift_3, M8_UM8_2_M8_4_t3); and2 M8_UM8_2_M8_4_M4(in283, M8_ContShift_4, M8_UM8_2_M8_4_t4); and2 M8_UM8_2_M8_4_M5(in294, M8_ContShift_5, M8_UM8_2_M8_4_t5); and2 M8_UM8_2_M8_4_M6(in303, M8_ContShift_6, M8_UM8_2_M8_4_t6); and2 M8_UM8_2_M8_4_M7(in311, M8_ContShift_7, M8_UM8_2_M8_4_t7); or8 M8_UM8_2_M8_4_M8(M8_UM8_2_M8_4_t0, M8_UM8_2_M8_4_t1, M8_UM8_2_M8_4_t2, M8_UM8_2_M8_4_t3, M8_UM8_2_M8_4_t4, M8_UM8_2_M8_4_t5, M8_UM8_2_M8_4_t6, M8_UM8_2_M8_4_t7, M8_ShiftRout_4); and2 M8_UM8_2_M8_5_M0(in77, M8_ContShift_0, M8_UM8_2_M8_5_t0); and2 M8_UM8_2_M8_5_M1(in87, M8_ContShift_1, M8_UM8_2_M8_5_t1); and2 M8_UM8_2_M8_5_M2(in97, M8_ContShift_2, M8_UM8_2_M8_5_t2); and2 M8_UM8_2_M8_5_M3(in107, M8_ContShift_3, M8_UM8_2_M8_5_t3); and2 M8_UM8_2_M8_5_M4(in116, M8_ContShift_4, M8_UM8_2_M8_5_t4); and2 M8_UM8_2_M8_5_M5(in283, M8_ContShift_5, M8_UM8_2_M8_5_t5); and2 M8_UM8_2_M8_5_M6(in294, M8_ContShift_6, M8_UM8_2_M8_5_t6); and2 M8_UM8_2_M8_5_M7(in303, M8_ContShift_7, M8_UM8_2_M8_5_t7); or8 M8_UM8_2_M8_5_M8(M8_UM8_2_M8_5_t0, M8_UM8_2_M8_5_t1, M8_UM8_2_M8_5_t2, M8_UM8_2_M8_5_t3, M8_UM8_2_M8_5_t4, M8_UM8_2_M8_5_t5, M8_UM8_2_M8_5_t6, M8_UM8_2_M8_5_t7, M8_ShiftRout_5); and2 M8_UM8_2_M8_6_M0(in68, M8_ContShift_0, M8_UM8_2_M8_6_t0); and2 M8_UM8_2_M8_6_M1(in77, M8_ContShift_1, M8_UM8_2_M8_6_t1); and2 M8_UM8_2_M8_6_M2(in87, M8_ContShift_2, M8_UM8_2_M8_6_t2); and2 M8_UM8_2_M8_6_M3(in97, M8_ContShift_3, M8_UM8_2_M8_6_t3); and2 M8_UM8_2_M8_6_M4(in107, M8_ContShift_4, M8_UM8_2_M8_6_t4); and2 M8_UM8_2_M8_6_M5(in116, M8_ContShift_5, M8_UM8_2_M8_6_t5); and2 M8_UM8_2_M8_6_M6(in283, M8_ContShift_6, M8_UM8_2_M8_6_t6); and2 M8_UM8_2_M8_6_M7(in294, M8_ContShift_7, M8_UM8_2_M8_6_t7); or8 M8_UM8_2_M8_6_M8(M8_UM8_2_M8_6_t0, M8_UM8_2_M8_6_t1, M8_UM8_2_M8_6_t2, M8_UM8_2_M8_6_t3, M8_UM8_2_M8_6_t4, M8_UM8_2_M8_6_t5, M8_UM8_2_M8_6_t6, M8_UM8_2_M8_6_t7, M8_ShiftRout_6); and2 M8_UM8_2_M8_7_M0(in58, M8_ContShift_0, M8_UM8_2_M8_7_t0); and2 M8_UM8_2_M8_7_M1(in68, M8_ContShift_1, M8_UM8_2_M8_7_t1); and2 M8_UM8_2_M8_7_M2(in77, M8_ContShift_2, M8_UM8_2_M8_7_t2); and2 M8_UM8_2_M8_7_M3(in87, M8_ContShift_3, M8_UM8_2_M8_7_t3); and2 M8_UM8_2_M8_7_M4(in97, M8_ContShift_4, M8_UM8_2_M8_7_t4); and2 M8_UM8_2_M8_7_M5(in107, M8_ContShift_5, M8_UM8_2_M8_7_t5); and2 M8_UM8_2_M8_7_M6(in116, M8_ContShift_6, M8_UM8_2_M8_7_t6); and2 M8_UM8_2_M8_7_M7(in283, M8_ContShift_7, M8_UM8_2_M8_7_t7); or8 M8_UM8_2_M8_7_M8(M8_UM8_2_M8_7_t0, M8_UM8_2_M8_7_t1, M8_UM8_2_M8_7_t2, M8_UM8_2_M8_7_t3, M8_UM8_2_M8_7_t4, M8_UM8_2_M8_7_t5, M8_UM8_2_M8_7_t6, M8_UM8_2_M8_7_t7, M8_ShiftRout_7); inv M8_UM8_3_Mux2_0(in33, M8_UM8_3_Not_ContIn); and2 M8_UM8_3_Mux2_1(M8_ShiftQout_0, M8_UM8_3_Not_ContIn, M8_UM8_3_line1); and2 M8_UM8_3_Mux2_2(M8_ShiftRout_0, in33, M8_UM8_3_line2); or2 M8_UM8_3_Mux2_3(M8_UM8_3_line1, M8_UM8_3_line2, Shiftbus_0); inv M8_UM8_4_Mux2_0(in33, M8_UM8_4_Not_ContIn); and2 M8_UM8_4_Mux2_1(M8_ShiftQout_1, M8_UM8_4_Not_ContIn, M8_UM8_4_line1); and2 M8_UM8_4_Mux2_2(M8_ShiftRout_1, in33, M8_UM8_4_line2); or2 M8_UM8_4_Mux2_3(M8_UM8_4_line1, M8_UM8_4_line2, Shiftbus_1); inv M8_UM8_5_Mux2_0(in33, M8_UM8_5_Not_ContIn); and2 M8_UM8_5_Mux2_1(M8_ShiftQout_2, M8_UM8_5_Not_ContIn, M8_UM8_5_line1); and2 M8_UM8_5_Mux2_2(M8_ShiftRout_2, in33, M8_UM8_5_line2); or2 M8_UM8_5_Mux2_3(M8_UM8_5_line1, M8_UM8_5_line2, Shiftbus_2); inv M8_UM8_6_Mux2_0(in33, M8_UM8_6_Not_ContIn); and2 M8_UM8_6_Mux2_1(M8_ShiftQout_3, M8_UM8_6_Not_ContIn, M8_UM8_6_line1); and2 M8_UM8_6_Mux2_2(M8_ShiftRout_3, in33, M8_UM8_6_line2); or2 M8_UM8_6_Mux2_3(M8_UM8_6_line1, M8_UM8_6_line2, Shiftbus_3); inv M8_UM8_7_Mux2_0(in33, M8_UM8_7_Not_ContIn); and2 M8_UM8_7_Mux2_1(M8_ShiftQout_4, M8_UM8_7_Not_ContIn, M8_UM8_7_line1); and2 M8_UM8_7_Mux2_2(M8_ShiftRout_4, in33, M8_UM8_7_line2); or2 M8_UM8_7_Mux2_3(M8_UM8_7_line1, M8_UM8_7_line2, Shiftbus_4); inv M8_UM8_8_Mux2_0(in33, M8_UM8_8_Not_ContIn); and2 M8_UM8_8_Mux2_1(M8_ShiftQout_5, M8_UM8_8_Not_ContIn, M8_UM8_8_line1); and2 M8_UM8_8_Mux2_2(M8_ShiftRout_5, in33, M8_UM8_8_line2); or2 M8_UM8_8_Mux2_3(M8_UM8_8_line1, M8_UM8_8_line2, Shiftbus_5); inv M8_UM8_9_Mux2_0(in33, M8_UM8_9_Not_ContIn); and2 M8_UM8_9_Mux2_1(M8_ShiftQout_6, M8_UM8_9_Not_ContIn, M8_UM8_9_line1); and2 M8_UM8_9_Mux2_2(M8_ShiftRout_6, in33, M8_UM8_9_line2); or2 M8_UM8_9_Mux2_3(M8_UM8_9_line1, M8_UM8_9_line2, Shiftbus_6); inv M8_UM8_10_Mux2_0(in33, M8_UM8_10_Not_ContIn); and2 M8_UM8_10_Mux2_1(M8_ShiftQout_7, M8_UM8_10_Not_ContIn, M8_UM8_10_line1); and2 M8_UM8_10_Mux2_2(M8_ShiftRout_7, in33, M8_UM8_10_line2); or2 M8_UM8_10_Mux2_3(M8_UM8_10_line1, M8_UM8_10_line2, M8_Sbus7_0); inv M8_UM8_11_Mux2_0(in41, M8_UM8_11_Not_ContIn); and2 M8_UM8_11_Mux2_1(M8_Sbus7_0, M8_UM8_11_Not_ContIn, M8_UM8_11_line1); and2 M8_UM8_11_Mux2_2(in50, in41, M8_UM8_11_line2); or2 M8_UM8_11_Mux2_3(M8_UM8_11_line1, M8_UM8_11_line2, Shiftbus_7); inv M9_UM9_0_BM0_Inv8_0_Inv4_0(in116, M9_UM9_0_NotAbus_0); inv M9_UM9_0_BM0_Inv8_0_Inv4_1(in107, M9_UM9_0_NotAbus_1); inv M9_UM9_0_BM0_Inv8_0_Inv4_2(in97, M9_UM9_0_NotAbus_2); inv M9_UM9_0_BM0_Inv8_0_Inv4_3(in87, M9_UM9_0_NotAbus_3); inv M9_UM9_0_BM0_Inv8_1_Inv4_0(in77, M9_UM9_0_NotAbus_4); inv M9_UM9_0_BM0_Inv8_1_Inv4_1(in68, M9_UM9_0_NotAbus_5); inv M9_UM9_0_BM0_Inv8_1_Inv4_2(in58, M9_UM9_0_NotAbus_6); inv M9_UM9_0_BM0_Inv8_1_Inv4_3(in50, M9_UM9_0_NotAbus_7); nand2 M9_UM9_0_BM1(M9_UM9_0_NotAbus_6, M9_UM9_0_NotAbus_5, M9_UM9_0_NotA6_5); and2 M9_UM9_0_BM2(in50, M9_UM9_0_NotA6_5, M9_UM9_0_T1_0_0); inv M9_UM9_0_BM3_Xo0(M9_UM9_0_NotAbus_4, M9_UM9_0_BM3_NotA); inv M9_UM9_0_BM3_Xo1(M9_UM9_0_NotAbus_5, M9_UM9_0_BM3_NotB); nand2 M9_UM9_0_BM3_Xo2(M9_UM9_0_BM3_NotA, M9_UM9_0_NotAbus_5, M9_UM9_0_BM3_line2); nand2 M9_UM9_0_BM3_Xo3(M9_UM9_0_BM3_NotB, M9_UM9_0_NotAbus_4, M9_UM9_0_BM3_line3); nand2 M9_UM9_0_BM3_Xo4(M9_UM9_0_BM3_line2, M9_UM9_0_BM3_line3, M9_UM9_0_XA5_4); inv M9_UM9_0_BM4_Xo0(M9_UM9_0_NotAbus_6, M9_UM9_0_BM4_NotA); inv M9_UM9_0_BM4_Xo1(in50, M9_UM9_0_BM4_NotB); nand2 M9_UM9_0_BM4_Xo2(M9_UM9_0_BM4_NotA, in50, M9_UM9_0_BM4_line2); nand2 M9_UM9_0_BM4_Xo3(M9_UM9_0_BM4_NotB, M9_UM9_0_NotAbus_6, M9_UM9_0_BM4_line3); nand2 M9_UM9_0_BM4_Xo4(M9_UM9_0_BM4_line2, M9_UM9_0_BM4_line3, M9_UM9_0_NotXA7_6); inv M9_UM9_0_BM5_Xo0(M9_UM9_0_XA5_4, M9_UM9_0_BM5_NotA); inv M9_UM9_0_BM5_Xo1(M9_UM9_0_NotXA7_6, M9_UM9_0_BM5_NotB); nand2 M9_UM9_0_BM5_Xo2(M9_UM9_0_BM5_NotA, M9_UM9_0_NotXA7_6, M9_UM9_0_BM5_line2); nand2 M9_UM9_0_BM5_Xo3(M9_UM9_0_BM5_NotB, M9_UM9_0_XA5_4, M9_UM9_0_BM5_line3); nand2 M9_UM9_0_BM5_Xo4(M9_UM9_0_BM5_line2, M9_UM9_0_BM5_line3, M9_UM9_0_T1_0_1); inv M9_UM9_0_BM6_Mux2_0(in45, M9_UM9_0_BM6_Not_ContIn); and2 M9_UM9_0_BM6_Mux2_1(M9_UM9_0_T1_0_0, M9_UM9_0_BM6_Not_ContIn, M9_UM9_0_BM6_line1); and2 M9_UM9_0_BM6_Mux2_2(M9_UM9_0_T1_0_1, in45, M9_UM9_0_BM6_line2); or2 M9_UM9_0_BM6_Mux2_3(M9_UM9_0_BM6_line1, M9_UM9_0_BM6_line2, M9_temp1bus_0); and3 M9_UM9_0_BM7(M9_UM9_0_NotAbus_3, M9_UM9_0_NotAbus_2, M9_UM9_0_NotAbus_1, M9_UM9_0_NotA3_1); and2 M9_UM9_0_BM8(M9_UM9_0_NotAbus_0, M9_UM9_0_NotA3_1, M9_UM9_0_NotA3_0); nand2 M9_UM9_0_BM9(in77, in68, M9_UM9_0_NdA5_4); and4 M9_UM9_0_BM10(M9_UM9_0_NotA3_0, M9_UM9_0_NdA5_4, M9_UM9_0_NotAbus_7, in58, M9_UM9_0_T1_1_0); inv M9_UM9_0_BM11_Xo0(in244, M9_UM9_0_BM11_NotA); inv M9_UM9_0_BM11_Xo1(in238, M9_UM9_0_BM11_NotB); nand2 M9_UM9_0_BM11_Xo2(M9_UM9_0_BM11_NotA, in238, M9_UM9_0_BM11_line2); nand2 M9_UM9_0_BM11_Xo3(M9_UM9_0_BM11_NotB, in244, M9_UM9_0_BM11_line3); nand2 M9_UM9_0_BM11_Xo4(M9_UM9_0_BM11_line2, M9_UM9_0_BM11_line3, M9_UM9_0_XB5_4); inv M9_UM9_0_BM12_Xo0(in226, M9_UM9_0_BM12_NotA); inv M9_UM9_0_BM12_Xo1(in232, M9_UM9_0_BM12_NotB); nand2 M9_UM9_0_BM12_Xo2(M9_UM9_0_BM12_NotA, in232, M9_UM9_0_BM12_line2); nand2 M9_UM9_0_BM12_Xo3(M9_UM9_0_BM12_NotB, in226, M9_UM9_0_BM12_line3); nand2 M9_UM9_0_BM12_Xo4(M9_UM9_0_BM12_line2, M9_UM9_0_BM12_line3, M9_UM9_0_XB7_6); inv M9_UM9_0_BM13_Xo0(M9_UM9_0_XB5_4, M9_UM9_0_BM13_NotA); inv M9_UM9_0_BM13_Xo1(M9_UM9_0_XB7_6, M9_UM9_0_BM13_NotB); nand2 M9_UM9_0_BM13_Xo2(M9_UM9_0_BM13_NotA, M9_UM9_0_XB7_6, M9_UM9_0_BM13_line2); nand2 M9_UM9_0_BM13_Xo3(M9_UM9_0_BM13_NotB, M9_UM9_0_XB5_4, M9_UM9_0_BM13_line3); nand2 M9_UM9_0_BM13_Xo4(M9_UM9_0_BM13_line2, M9_UM9_0_BM13_line3, M9_UM9_0_XB7_4); inv M9_UM9_0_BM14(M9_UM9_0_XB7_4, M9_UM9_0_T1_1_1); inv M9_UM9_0_BM15_Mux2_0(in45, M9_UM9_0_BM15_Not_ContIn); and2 M9_UM9_0_BM15_Mux2_1(M9_UM9_0_T1_1_0, M9_UM9_0_BM15_Not_ContIn, M9_UM9_0_BM15_line1); and2 M9_UM9_0_BM15_Mux2_2(M9_UM9_0_T1_1_1, in45, M9_UM9_0_BM15_line2); or2 M9_UM9_0_BM15_Mux2_3(M9_UM9_0_BM15_line1, M9_UM9_0_BM15_line2, M9_temp1bus_1); inv M9_UM9_0_BM16_Xo0(M9_UM9_0_NotAbus_0, M9_UM9_0_BM16_NotA); inv M9_UM9_0_BM16_Xo1(M9_UM9_0_NotAbus_1, M9_UM9_0_BM16_NotB); nand2 M9_UM9_0_BM16_Xo2(M9_UM9_0_BM16_NotA, M9_UM9_0_NotAbus_1, M9_UM9_0_BM16_line2); nand2 M9_UM9_0_BM16_Xo3(M9_UM9_0_BM16_NotB, M9_UM9_0_NotAbus_0, M9_UM9_0_BM16_line3); nand2 M9_UM9_0_BM16_Xo4(M9_UM9_0_BM16_line2, M9_UM9_0_BM16_line3, M9_UM9_0_XA1_0); inv M9_UM9_0_BM17_Xo0(M9_UM9_0_NotAbus_2, M9_UM9_0_BM17_NotA); inv M9_UM9_0_BM17_Xo1(M9_UM9_0_NotAbus_3, M9_UM9_0_BM17_NotB); nand2 M9_UM9_0_BM17_Xo2(M9_UM9_0_BM17_NotA, M9_UM9_0_NotAbus_3, M9_UM9_0_BM17_line2); nand2 M9_UM9_0_BM17_Xo3(M9_UM9_0_BM17_NotB, M9_UM9_0_NotAbus_2, M9_UM9_0_BM17_line3); nand2 M9_UM9_0_BM17_Xo4(M9_UM9_0_BM17_line2, M9_UM9_0_BM17_line3, M9_UM9_0_XA3_2); inv M9_UM9_0_BM18_Xo0(M9_UM9_0_XA1_0, M9_UM9_0_BM18_NotA); inv M9_UM9_0_BM18_Xo1(M9_UM9_0_XA3_2, M9_UM9_0_BM18_NotB); nand2 M9_UM9_0_BM18_Xo2(M9_UM9_0_BM18_NotA, M9_UM9_0_XA3_2, M9_UM9_0_BM18_line2); nand2 M9_UM9_0_BM18_Xo3(M9_UM9_0_BM18_NotB, M9_UM9_0_XA1_0, M9_UM9_0_BM18_line3); nand2 M9_UM9_0_BM18_Xo4(M9_UM9_0_BM18_line2, M9_UM9_0_BM18_line3, M9_UM9_0_XA3_0); inv M9_UM9_0_BM19(M9_UM9_0_XA3_0, M9_temp1bus_2); inv M9_UM9_0_BM20_Xo0(in270, M9_UM9_0_BM20_NotA); inv M9_UM9_0_BM20_Xo1(in264, M9_UM9_0_BM20_NotB); nand2 M9_UM9_0_BM20_Xo2(M9_UM9_0_BM20_NotA, in264, M9_UM9_0_BM20_line2); nand2 M9_UM9_0_BM20_Xo3(M9_UM9_0_BM20_NotB, in270, M9_UM9_0_BM20_line3); nand2 M9_UM9_0_BM20_Xo4(M9_UM9_0_BM20_line2, M9_UM9_0_BM20_line3, M9_UM9_0_XB1_0); inv M9_UM9_0_BM21_Xo0(in257, M9_UM9_0_BM21_NotA); inv M9_UM9_0_BM21_Xo1(in250, M9_UM9_0_BM21_NotB); nand2 M9_UM9_0_BM21_Xo2(M9_UM9_0_BM21_NotA, in250, M9_UM9_0_BM21_line2); nand2 M9_UM9_0_BM21_Xo3(M9_UM9_0_BM21_NotB, in257, M9_UM9_0_BM21_line3); nand2 M9_UM9_0_BM21_Xo4(M9_UM9_0_BM21_line2, M9_UM9_0_BM21_line3, M9_UM9_0_XB3_2); inv M9_UM9_0_BM22_Xo0(M9_UM9_0_XB1_0, M9_UM9_0_BM22_NotA); inv M9_UM9_0_BM22_Xo1(M9_UM9_0_XB3_2, M9_UM9_0_BM22_NotB); nand2 M9_UM9_0_BM22_Xo2(M9_UM9_0_BM22_NotA, M9_UM9_0_XB3_2, M9_UM9_0_BM22_line2); nand2 M9_UM9_0_BM22_Xo3(M9_UM9_0_BM22_NotB, M9_UM9_0_XB1_0, M9_UM9_0_BM22_line3); nand2 M9_UM9_0_BM22_Xo4(M9_UM9_0_BM22_line2, M9_UM9_0_BM22_line3, M9_UM9_0_XB3_0); inv M9_UM9_0_BM23(M9_UM9_0_XB3_0, M9_temp1bus_3); nand2 M9_UM9_0_BM24(M9_UM9_0_NotAbus_2, M9_UM9_0_NotAbus_1, M9_UM9_0_NotA1_0); and2 M9_UM9_0_BM25(in87, M9_UM9_0_NotA1_0, M9_temp2bus_0); and2 M9_UM9_0_BM26(M9_UM9_0_NotAbus_0, M9_UM9_0_NotA3_1, M9_temp2bus_1); inv M9_UM9_1(in13, M9_NotCont1); inv M9_UM9_2(in33, M9_NotCont3); and3 M9_UM9_3(in1, M9_NotCont1, in20, M9_temp3); nand2 M9_UM9_4(M9_temp3, in33, M9_ContHi); nand2 M9_UM9_5(M9_temp3, M9_NotCont3, M9_ContLo); inv M9_UM9_6_M4b3c_0_Mux3c_0(M9_ContHi, M9_UM9_6_M4b3c_0_NotContHi); inv M9_UM9_6_M4b3c_0_Mux3c_1(M9_ContLo, M9_UM9_6_M4b3c_0_NotContLo); and2 M9_UM9_6_M4b3c_0_Mux3c_2(M9_temp1bus_0, M9_UM9_6_M4b3c_0_NotContHi, M9_UM9_6_M4b3c_0_line2); and2 M9_UM9_6_M4b3c_0_Mux3c_3(M9_temp2bus_0, M9_UM9_6_M4b3c_0_NotContLo, M9_UM9_6_M4b3c_0_line3); and2 M9_UM9_6_M4b3c_0_Mux3c_4(M9_ContHi, M9_ContLo, M9_UM9_6_M4b3c_0_line4); and2 M9_UM9_6_M4b3c_0_Mux3c_5(M9_UM9_6_M4b3c_0_line4, in116, M9_UM9_6_M4b3c_0_line5); or3 M9_UM9_6_M4b3c_0_Mux3c_6(M9_UM9_6_M4b3c_0_line2, M9_UM9_6_M4b3c_0_line3, M9_UM9_6_M4b3c_0_line5, Hbus_0); inv M9_UM9_6_M4b3c_1_Mux3c_0(M9_ContHi, M9_UM9_6_M4b3c_1_NotContHi); inv M9_UM9_6_M4b3c_1_Mux3c_1(M9_ContLo, M9_UM9_6_M4b3c_1_NotContLo); and2 M9_UM9_6_M4b3c_1_Mux3c_2(M9_temp1bus_1, M9_UM9_6_M4b3c_1_NotContHi, M9_UM9_6_M4b3c_1_line2); and2 M9_UM9_6_M4b3c_1_Mux3c_3(M9_temp2bus_1, M9_UM9_6_M4b3c_1_NotContLo, M9_UM9_6_M4b3c_1_line3); and2 M9_UM9_6_M4b3c_1_Mux3c_4(M9_ContHi, M9_ContLo, M9_UM9_6_M4b3c_1_line4); and2 M9_UM9_6_M4b3c_1_Mux3c_5(M9_UM9_6_M4b3c_1_line4, in107, M9_UM9_6_M4b3c_1_line5); or3 M9_UM9_6_M4b3c_1_Mux3c_6(M9_UM9_6_M4b3c_1_line2, M9_UM9_6_M4b3c_1_line3, M9_UM9_6_M4b3c_1_line5, Hbus_1); inv M9_UM9_6_M4b3c_2_Mux3c_0(M9_ContHi, M9_UM9_6_M4b3c_2_NotContHi); inv M9_UM9_6_M4b3c_2_Mux3c_1(M9_ContLo, M9_UM9_6_M4b3c_2_NotContLo); and2 M9_UM9_6_M4b3c_2_Mux3c_2(M9_temp1bus_2, M9_UM9_6_M4b3c_2_NotContHi, M9_UM9_6_M4b3c_2_line2); and2 M9_UM9_6_M4b3c_2_Mux3c_3(gnd, M9_UM9_6_M4b3c_2_NotContLo, M9_UM9_6_M4b3c_2_line3); and2 M9_UM9_6_M4b3c_2_Mux3c_4(M9_ContHi, M9_ContLo, M9_UM9_6_M4b3c_2_line4); and2 M9_UM9_6_M4b3c_2_Mux3c_5(M9_UM9_6_M4b3c_2_line4, in97, M9_UM9_6_M4b3c_2_line5); or3 M9_UM9_6_M4b3c_2_Mux3c_6(M9_UM9_6_M4b3c_2_line2, M9_UM9_6_M4b3c_2_line3, M9_UM9_6_M4b3c_2_line5, Hbus_2); inv M9_UM9_6_M4b3c_3_Mux3c_0(M9_ContHi, M9_UM9_6_M4b3c_3_NotContHi); inv M9_UM9_6_M4b3c_3_Mux3c_1(M9_ContLo, M9_UM9_6_M4b3c_3_NotContLo); and2 M9_UM9_6_M4b3c_3_Mux3c_2(M9_temp1bus_3, M9_UM9_6_M4b3c_3_NotContHi, M9_UM9_6_M4b3c_3_line2); and2 M9_UM9_6_M4b3c_3_Mux3c_3(gnd, M9_UM9_6_M4b3c_3_NotContLo, M9_UM9_6_M4b3c_3_line3); and2 M9_UM9_6_M4b3c_3_Mux3c_4(M9_ContHi, M9_ContLo, M9_UM9_6_M4b3c_3_line4); and2 M9_UM9_6_M4b3c_3_Mux3c_5(M9_UM9_6_M4b3c_3_line4, in87, M9_UM9_6_M4b3c_3_line5); or3 M9_UM9_6_M4b3c_3_Mux3c_6(M9_UM9_6_M4b3c_3_line2, M9_UM9_6_M4b3c_3_line3, M9_UM9_6_M4b3c_3_line5, Hbus_3); inv M10_UM10_0(in13, M10_NotCont1); inv M10_UM10_1(in20, M10_NotCont2); inv M10_UM10_2(in33, M10_NotCont3); or2 M10_UM10_3(M10_NotCont2, in169, M10_tmp0); nand3 M10_UM10_4(in1, in13, M10_tmp0, M10_ContHi); nand3 M10_UM10_5(M10_NotCont1, M10_NotCont2, M10_NotCont3, M10_ContLo1); nand2 M10_UM10_6(M10_NotCont1, M10_NotCont3, M10_ContLo2); inv M10_UM10_7_M4b3c_0_Mux3c_0(M10_ContHi, M10_UM10_7_M4b3c_0_NotContHi); inv M10_UM10_7_M4b3c_0_Mux3c_1(M10_ContLo1, M10_UM10_7_M4b3c_0_NotContLo); and2 M10_UM10_7_M4b3c_0_Mux3c_2(Shiftbus_0, M10_UM10_7_M4b3c_0_NotContHi, M10_UM10_7_M4b3c_0_line2); and2 M10_UM10_7_M4b3c_0_Mux3c_3(XPbus_0, M10_UM10_7_M4b3c_0_NotContLo, M10_UM10_7_M4b3c_0_line3); and2 M10_UM10_7_M4b3c_0_Mux3c_4(M10_ContHi, M10_ContLo1, M10_UM10_7_M4b3c_0_line4); and2 M10_UM10_7_M4b3c_0_Mux3c_5(M10_UM10_7_M4b3c_0_line4, Hbus_0, M10_UM10_7_M4b3c_0_line5); or3 M10_UM10_7_M4b3c_0_Mux3c_6(M10_UM10_7_M4b3c_0_line2, M10_UM10_7_M4b3c_0_line3, M10_UM10_7_M4b3c_0_line5, Wbus_0); inv M10_UM10_7_M4b3c_1_Mux3c_0(M10_ContHi, M10_UM10_7_M4b3c_1_NotContHi); inv M10_UM10_7_M4b3c_1_Mux3c_1(M10_ContLo1, M10_UM10_7_M4b3c_1_NotContLo); and2 M10_UM10_7_M4b3c_1_Mux3c_2(Shiftbus_1, M10_UM10_7_M4b3c_1_NotContHi, M10_UM10_7_M4b3c_1_line2); and2 M10_UM10_7_M4b3c_1_Mux3c_3(XPbus_1, M10_UM10_7_M4b3c_1_NotContLo, M10_UM10_7_M4b3c_1_line3); and2 M10_UM10_7_M4b3c_1_Mux3c_4(M10_ContHi, M10_ContLo1, M10_UM10_7_M4b3c_1_line4); and2 M10_UM10_7_M4b3c_1_Mux3c_5(M10_UM10_7_M4b3c_1_line4, Hbus_1, M10_UM10_7_M4b3c_1_line5); or3 M10_UM10_7_M4b3c_1_Mux3c_6(M10_UM10_7_M4b3c_1_line2, M10_UM10_7_M4b3c_1_line3, M10_UM10_7_M4b3c_1_line5, Wbus_1); inv M10_UM10_7_M4b3c_2_Mux3c_0(M10_ContHi, M10_UM10_7_M4b3c_2_NotContHi); inv M10_UM10_7_M4b3c_2_Mux3c_1(M10_ContLo1, M10_UM10_7_M4b3c_2_NotContLo); and2 M10_UM10_7_M4b3c_2_Mux3c_2(Shiftbus_2, M10_UM10_7_M4b3c_2_NotContHi, M10_UM10_7_M4b3c_2_line2); and2 M10_UM10_7_M4b3c_2_Mux3c_3(XPbus_2, M10_UM10_7_M4b3c_2_NotContLo, M10_UM10_7_M4b3c_2_line3); and2 M10_UM10_7_M4b3c_2_Mux3c_4(M10_ContHi, M10_ContLo1, M10_UM10_7_M4b3c_2_line4); and2 M10_UM10_7_M4b3c_2_Mux3c_5(M10_UM10_7_M4b3c_2_line4, Hbus_2, M10_UM10_7_M4b3c_2_line5); or3 M10_UM10_7_M4b3c_2_Mux3c_6(M10_UM10_7_M4b3c_2_line2, M10_UM10_7_M4b3c_2_line3, M10_UM10_7_M4b3c_2_line5, Wbus_2); inv M10_UM10_7_M4b3c_3_Mux3c_0(M10_ContHi, M10_UM10_7_M4b3c_3_NotContHi); inv M10_UM10_7_M4b3c_3_Mux3c_1(M10_ContLo1, M10_UM10_7_M4b3c_3_NotContLo); and2 M10_UM10_7_M4b3c_3_Mux3c_2(Shiftbus_3, M10_UM10_7_M4b3c_3_NotContHi, M10_UM10_7_M4b3c_3_line2); and2 M10_UM10_7_M4b3c_3_Mux3c_3(XPbus_3, M10_UM10_7_M4b3c_3_NotContLo, M10_UM10_7_M4b3c_3_line3); and2 M10_UM10_7_M4b3c_3_Mux3c_4(M10_ContHi, M10_ContLo1, M10_UM10_7_M4b3c_3_line4); and2 M10_UM10_7_M4b3c_3_Mux3c_5(M10_UM10_7_M4b3c_3_line4, Hbus_3, M10_UM10_7_M4b3c_3_line5); or3 M10_UM10_7_M4b3c_3_Mux3c_6(M10_UM10_7_M4b3c_3_line2, M10_UM10_7_M4b3c_3_line3, M10_UM10_7_M4b3c_3_line5, Wbus_3); inv M10_UM10_8_M4b3c_0_Mux3c_0(M10_ContHi, M10_UM10_8_M4b3c_0_NotContHi); inv M10_UM10_8_M4b3c_0_Mux3c_1(M10_ContLo2, M10_UM10_8_M4b3c_0_NotContLo); and2 M10_UM10_8_M4b3c_0_Mux3c_2(Shiftbus_4, M10_UM10_8_M4b3c_0_NotContHi, M10_UM10_8_M4b3c_0_line2); and2 M10_UM10_8_M4b3c_0_Mux3c_3(XPbus_4, M10_UM10_8_M4b3c_0_NotContLo, M10_UM10_8_M4b3c_0_line3); and2 M10_UM10_8_M4b3c_0_Mux3c_4(M10_ContHi, M10_ContLo2, M10_UM10_8_M4b3c_0_line4); and2 M10_UM10_8_M4b3c_0_Mux3c_5(M10_UM10_8_M4b3c_0_line4, in77, M10_UM10_8_M4b3c_0_line5); or3 M10_UM10_8_M4b3c_0_Mux3c_6(M10_UM10_8_M4b3c_0_line2, M10_UM10_8_M4b3c_0_line3, M10_UM10_8_M4b3c_0_line5, Wbus_4); inv M10_UM10_8_M4b3c_1_Mux3c_0(M10_ContHi, M10_UM10_8_M4b3c_1_NotContHi); inv M10_UM10_8_M4b3c_1_Mux3c_1(M10_ContLo2, M10_UM10_8_M4b3c_1_NotContLo); and2 M10_UM10_8_M4b3c_1_Mux3c_2(Shiftbus_5, M10_UM10_8_M4b3c_1_NotContHi, M10_UM10_8_M4b3c_1_line2); and2 M10_UM10_8_M4b3c_1_Mux3c_3(XPbus_5, M10_UM10_8_M4b3c_1_NotContLo, M10_UM10_8_M4b3c_1_line3); and2 M10_UM10_8_M4b3c_1_Mux3c_4(M10_ContHi, M10_ContLo2, M10_UM10_8_M4b3c_1_line4); and2 M10_UM10_8_M4b3c_1_Mux3c_5(M10_UM10_8_M4b3c_1_line4, in68, M10_UM10_8_M4b3c_1_line5); or3 M10_UM10_8_M4b3c_1_Mux3c_6(M10_UM10_8_M4b3c_1_line2, M10_UM10_8_M4b3c_1_line3, M10_UM10_8_M4b3c_1_line5, Wbus_5); inv M10_UM10_8_M4b3c_2_Mux3c_0(M10_ContHi, M10_UM10_8_M4b3c_2_NotContHi); inv M10_UM10_8_M4b3c_2_Mux3c_1(M10_ContLo2, M10_UM10_8_M4b3c_2_NotContLo); and2 M10_UM10_8_M4b3c_2_Mux3c_2(Shiftbus_6, M10_UM10_8_M4b3c_2_NotContHi, M10_UM10_8_M4b3c_2_line2); and2 M10_UM10_8_M4b3c_2_Mux3c_3(XPbus_6, M10_UM10_8_M4b3c_2_NotContLo, M10_UM10_8_M4b3c_2_line3); and2 M10_UM10_8_M4b3c_2_Mux3c_4(M10_ContHi, M10_ContLo2, M10_UM10_8_M4b3c_2_line4); and2 M10_UM10_8_M4b3c_2_Mux3c_5(M10_UM10_8_M4b3c_2_line4, in58, M10_UM10_8_M4b3c_2_line5); or3 M10_UM10_8_M4b3c_2_Mux3c_6(M10_UM10_8_M4b3c_2_line2, M10_UM10_8_M4b3c_2_line3, M10_UM10_8_M4b3c_2_line5, Wbus_6); inv M10_UM10_8_M4b3c_3_Mux3c_0(M10_ContHi, M10_UM10_8_M4b3c_3_NotContHi); inv M10_UM10_8_M4b3c_3_Mux3c_1(M10_ContLo2, M10_UM10_8_M4b3c_3_NotContLo); and2 M10_UM10_8_M4b3c_3_Mux3c_2(Shiftbus_7, M10_UM10_8_M4b3c_3_NotContHi, M10_UM10_8_M4b3c_3_line2); and2 M10_UM10_8_M4b3c_3_Mux3c_3(XPbus_7, M10_UM10_8_M4b3c_3_NotContLo, M10_UM10_8_M4b3c_3_line3); and2 M10_UM10_8_M4b3c_3_Mux3c_4(M10_ContHi, M10_ContLo2, M10_UM10_8_M4b3c_3_line4); and2 M10_UM10_8_M4b3c_3_Mux3c_5(M10_UM10_8_M4b3c_3_line4, in50, M10_UM10_8_M4b3c_3_line5); or3 M10_UM10_8_M4b3c_3_Mux3c_6(M10_UM10_8_M4b3c_3_line2, M10_UM10_8_M4b3c_3_line3, M10_UM10_8_M4b3c_3_line5, Wbus_7); inv M11_UM11_0(in13, M11_NotCont1); inv M11_UM11_1(in20, M11_NotCont2); inv M11_UM11_2(in41, M11_NotCont5); nand3 M11_UM11_3(in13, M11_NotCont2, in45, M11_tmp0); and2 M11_UM11_4(in1, M11_tmp0, M11_ContHi); nand4 M11_UM11_5(in1, M11_NotCont1, in20, M11_NotCont5, M11_ContLo); inv M11_UM11_7_M8b3c_0_M4b3c_0_Mux3c_0(M11_ContHi, M11_UM11_7_M8b3c_0_M4b3c_0_NotContHi); inv M11_UM11_7_M8b3c_0_M4b3c_0_Mux3c_1(M11_ContLo, M11_UM11_7_M8b3c_0_M4b3c_0_NotContLo); and2 M11_UM11_7_M8b3c_0_M4b3c_0_Mux3c_2(Funcbus_0, M11_UM11_7_M8b3c_0_M4b3c_0_NotContHi, M11_UM11_7_M8b3c_0_M4b3c_0_line2); and2 M11_UM11_7_M8b3c_0_M4b3c_0_Mux3c_3(Funcbus_0, M11_UM11_7_M8b3c_0_M4b3c_0_NotContLo, M11_UM11_7_M8b3c_0_M4b3c_0_line3); and2 M11_UM11_7_M8b3c_0_M4b3c_0_Mux3c_4(M11_ContHi, M11_ContLo, M11_UM11_7_M8b3c_0_M4b3c_0_line4); and2 M11_UM11_7_M8b3c_0_M4b3c_0_Mux3c_5(M11_UM11_7_M8b3c_0_M4b3c_0_line4, Wbus_0, M11_UM11_7_M8b3c_0_M4b3c_0_line5); or3 M11_UM11_7_M8b3c_0_M4b3c_0_Mux3c_6(M11_UM11_7_M8b3c_0_M4b3c_0_line2, M11_UM11_7_M8b3c_0_M4b3c_0_line3, M11_UM11_7_M8b3c_0_M4b3c_0_line5, out396); inv M11_UM11_7_M8b3c_0_M4b3c_1_Mux3c_0(M11_ContHi, M11_UM11_7_M8b3c_0_M4b3c_1_NotContHi); inv M11_UM11_7_M8b3c_0_M4b3c_1_Mux3c_1(M11_ContLo, M11_UM11_7_M8b3c_0_M4b3c_1_NotContLo); and2 M11_UM11_7_M8b3c_0_M4b3c_1_Mux3c_2(Funcbus_1, M11_UM11_7_M8b3c_0_M4b3c_1_NotContHi, M11_UM11_7_M8b3c_0_M4b3c_1_line2); and2 M11_UM11_7_M8b3c_0_M4b3c_1_Mux3c_3(F_BCDbus_1, M11_UM11_7_M8b3c_0_M4b3c_1_NotContLo, M11_UM11_7_M8b3c_0_M4b3c_1_line3); and2 M11_UM11_7_M8b3c_0_M4b3c_1_Mux3c_4(M11_ContHi, M11_ContLo, M11_UM11_7_M8b3c_0_M4b3c_1_line4); and2 M11_UM11_7_M8b3c_0_M4b3c_1_Mux3c_5(M11_UM11_7_M8b3c_0_M4b3c_1_line4, Wbus_1, M11_UM11_7_M8b3c_0_M4b3c_1_line5); or3 M11_UM11_7_M8b3c_0_M4b3c_1_Mux3c_6(M11_UM11_7_M8b3c_0_M4b3c_1_line2, M11_UM11_7_M8b3c_0_M4b3c_1_line3, M11_UM11_7_M8b3c_0_M4b3c_1_line5, out393); inv M11_UM11_7_M8b3c_0_M4b3c_2_Mux3c_0(M11_ContHi, M11_UM11_7_M8b3c_0_M4b3c_2_NotContHi); inv M11_UM11_7_M8b3c_0_M4b3c_2_Mux3c_1(M11_ContLo, M11_UM11_7_M8b3c_0_M4b3c_2_NotContLo); and2 M11_UM11_7_M8b3c_0_M4b3c_2_Mux3c_2(Funcbus_2, M11_UM11_7_M8b3c_0_M4b3c_2_NotContHi, M11_UM11_7_M8b3c_0_M4b3c_2_line2); and2 M11_UM11_7_M8b3c_0_M4b3c_2_Mux3c_3(F_BCDbus_2, M11_UM11_7_M8b3c_0_M4b3c_2_NotContLo, M11_UM11_7_M8b3c_0_M4b3c_2_line3); and2 M11_UM11_7_M8b3c_0_M4b3c_2_Mux3c_4(M11_ContHi, M11_ContLo, M11_UM11_7_M8b3c_0_M4b3c_2_line4); and2 M11_UM11_7_M8b3c_0_M4b3c_2_Mux3c_5(M11_UM11_7_M8b3c_0_M4b3c_2_line4, Wbus_2, M11_UM11_7_M8b3c_0_M4b3c_2_line5); or3 M11_UM11_7_M8b3c_0_M4b3c_2_Mux3c_6(M11_UM11_7_M8b3c_0_M4b3c_2_line2, M11_UM11_7_M8b3c_0_M4b3c_2_line3, M11_UM11_7_M8b3c_0_M4b3c_2_line5, out390); inv M11_UM11_7_M8b3c_0_M4b3c_3_Mux3c_0(M11_ContHi, M11_UM11_7_M8b3c_0_M4b3c_3_NotContHi); inv M11_UM11_7_M8b3c_0_M4b3c_3_Mux3c_1(M11_ContLo, M11_UM11_7_M8b3c_0_M4b3c_3_NotContLo); and2 M11_UM11_7_M8b3c_0_M4b3c_3_Mux3c_2(Funcbus_3, M11_UM11_7_M8b3c_0_M4b3c_3_NotContHi, M11_UM11_7_M8b3c_0_M4b3c_3_line2); and2 M11_UM11_7_M8b3c_0_M4b3c_3_Mux3c_3(F_BCDbus_3, M11_UM11_7_M8b3c_0_M4b3c_3_NotContLo, M11_UM11_7_M8b3c_0_M4b3c_3_line3); and2 M11_UM11_7_M8b3c_0_M4b3c_3_Mux3c_4(M11_ContHi, M11_ContLo, M11_UM11_7_M8b3c_0_M4b3c_3_line4); and2 M11_UM11_7_M8b3c_0_M4b3c_3_Mux3c_5(M11_UM11_7_M8b3c_0_M4b3c_3_line4, Wbus_3, M11_UM11_7_M8b3c_0_M4b3c_3_line5); or3 M11_UM11_7_M8b3c_0_M4b3c_3_Mux3c_6(M11_UM11_7_M8b3c_0_M4b3c_3_line2, M11_UM11_7_M8b3c_0_M4b3c_3_line3, M11_UM11_7_M8b3c_0_M4b3c_3_line5, out387); inv M11_UM11_7_M8b3c_1_M4b3c_0_Mux3c_0(M11_ContHi, M11_UM11_7_M8b3c_1_M4b3c_0_NotContHi); inv M11_UM11_7_M8b3c_1_M4b3c_0_Mux3c_1(M11_ContLo, M11_UM11_7_M8b3c_1_M4b3c_0_NotContLo); and2 M11_UM11_7_M8b3c_1_M4b3c_0_Mux3c_2(Funcbus_4, M11_UM11_7_M8b3c_1_M4b3c_0_NotContHi, M11_UM11_7_M8b3c_1_M4b3c_0_line2); and2 M11_UM11_7_M8b3c_1_M4b3c_0_Mux3c_3(Funcbus_4, M11_UM11_7_M8b3c_1_M4b3c_0_NotContLo, M11_UM11_7_M8b3c_1_M4b3c_0_line3); and2 M11_UM11_7_M8b3c_1_M4b3c_0_Mux3c_4(M11_ContHi, M11_ContLo, M11_UM11_7_M8b3c_1_M4b3c_0_line4); and2 M11_UM11_7_M8b3c_1_M4b3c_0_Mux3c_5(M11_UM11_7_M8b3c_1_M4b3c_0_line4, Wbus_4, M11_UM11_7_M8b3c_1_M4b3c_0_line5); or3 M11_UM11_7_M8b3c_1_M4b3c_0_Mux3c_6(M11_UM11_7_M8b3c_1_M4b3c_0_line2, M11_UM11_7_M8b3c_1_M4b3c_0_line3, M11_UM11_7_M8b3c_1_M4b3c_0_line5, out384); inv M11_UM11_7_M8b3c_1_M4b3c_1_Mux3c_0(M11_ContHi, M11_UM11_7_M8b3c_1_M4b3c_1_NotContHi); inv M11_UM11_7_M8b3c_1_M4b3c_1_Mux3c_1(M11_ContLo, M11_UM11_7_M8b3c_1_M4b3c_1_NotContLo); and2 M11_UM11_7_M8b3c_1_M4b3c_1_Mux3c_2(Funcbus_5, M11_UM11_7_M8b3c_1_M4b3c_1_NotContHi, M11_UM11_7_M8b3c_1_M4b3c_1_line2); and2 M11_UM11_7_M8b3c_1_M4b3c_1_Mux3c_3(F_BCDbus_5, M11_UM11_7_M8b3c_1_M4b3c_1_NotContLo, M11_UM11_7_M8b3c_1_M4b3c_1_line3); and2 M11_UM11_7_M8b3c_1_M4b3c_1_Mux3c_4(M11_ContHi, M11_ContLo, M11_UM11_7_M8b3c_1_M4b3c_1_line4); and2 M11_UM11_7_M8b3c_1_M4b3c_1_Mux3c_5(M11_UM11_7_M8b3c_1_M4b3c_1_line4, Wbus_5, M11_UM11_7_M8b3c_1_M4b3c_1_line5); or3 M11_UM11_7_M8b3c_1_M4b3c_1_Mux3c_6(M11_UM11_7_M8b3c_1_M4b3c_1_line2, M11_UM11_7_M8b3c_1_M4b3c_1_line3, M11_UM11_7_M8b3c_1_M4b3c_1_line5, out381); inv M11_UM11_7_M8b3c_1_M4b3c_2_Mux3c_0(M11_ContHi, M11_UM11_7_M8b3c_1_M4b3c_2_NotContHi); inv M11_UM11_7_M8b3c_1_M4b3c_2_Mux3c_1(M11_ContLo, M11_UM11_7_M8b3c_1_M4b3c_2_NotContLo); and2 M11_UM11_7_M8b3c_1_M4b3c_2_Mux3c_2(Funcbus_6, M11_UM11_7_M8b3c_1_M4b3c_2_NotContHi, M11_UM11_7_M8b3c_1_M4b3c_2_line2); and2 M11_UM11_7_M8b3c_1_M4b3c_2_Mux3c_3(F_BCDbus_6, M11_UM11_7_M8b3c_1_M4b3c_2_NotContLo, M11_UM11_7_M8b3c_1_M4b3c_2_line3); and2 M11_UM11_7_M8b3c_1_M4b3c_2_Mux3c_4(M11_ContHi, M11_ContLo, M11_UM11_7_M8b3c_1_M4b3c_2_line4); and2 M11_UM11_7_M8b3c_1_M4b3c_2_Mux3c_5(M11_UM11_7_M8b3c_1_M4b3c_2_line4, Wbus_6, M11_UM11_7_M8b3c_1_M4b3c_2_line5); or3 M11_UM11_7_M8b3c_1_M4b3c_2_Mux3c_6(M11_UM11_7_M8b3c_1_M4b3c_2_line2, M11_UM11_7_M8b3c_1_M4b3c_2_line3, M11_UM11_7_M8b3c_1_M4b3c_2_line5, out378); inv M11_UM11_7_M8b3c_1_M4b3c_3_Mux3c_0(M11_ContHi, M11_UM11_7_M8b3c_1_M4b3c_3_NotContHi); inv M11_UM11_7_M8b3c_1_M4b3c_3_Mux3c_1(M11_ContLo, M11_UM11_7_M8b3c_1_M4b3c_3_NotContLo); and2 M11_UM11_7_M8b3c_1_M4b3c_3_Mux3c_2(Funcbus_7, M11_UM11_7_M8b3c_1_M4b3c_3_NotContHi, M11_UM11_7_M8b3c_1_M4b3c_3_line2); and2 M11_UM11_7_M8b3c_1_M4b3c_3_Mux3c_3(F_BCDbus_7, M11_UM11_7_M8b3c_1_M4b3c_3_NotContLo, M11_UM11_7_M8b3c_1_M4b3c_3_line3); and2 M11_UM11_7_M8b3c_1_M4b3c_3_Mux3c_4(M11_ContHi, M11_ContLo, M11_UM11_7_M8b3c_1_M4b3c_3_line4); and2 M11_UM11_7_M8b3c_1_M4b3c_3_Mux3c_5(M11_UM11_7_M8b3c_1_M4b3c_3_line4, Wbus_7, M11_UM11_7_M8b3c_1_M4b3c_3_line5); or3 M11_UM11_7_M8b3c_1_M4b3c_3_Mux3c_6(M11_UM11_7_M8b3c_1_M4b3c_3_line2, M11_UM11_7_M8b3c_1_M4b3c_3_line3, M11_UM11_7_M8b3c_1_M4b3c_3_line5, out375); inv M12_UM12_0_Inv8_0_Inv4_0(out396, M12_Not_Zbus_0); inv M12_UM12_0_Inv8_0_Inv4_1(out393, M12_Not_Zbus_1); inv M12_UM12_0_Inv8_0_Inv4_2(out390, M12_Not_Zbus_2); inv M12_UM12_0_Inv8_0_Inv4_3(out387, M12_Not_Zbus_3); inv M12_UM12_0_Inv8_1_Inv4_0(out384, M12_Not_Zbus_4); inv M12_UM12_0_Inv8_1_Inv4_1(out381, M12_Not_Zbus_5); inv M12_UM12_0_Inv8_1_Inv4_2(out378, M12_Not_Zbus_6); inv M12_UM12_0_Inv8_1_Inv4_3(out375, M12_Not_Zbus_7); and4 M12_UM12_1(M12_Not_Zbus_0, M12_Not_Zbus_1, M12_Not_Zbus_2, M12_Not_Zbus_3, M12_ZeroZ_Lo); and4 M12_UM12_2(M12_Not_Zbus_4, M12_Not_Zbus_5, M12_Not_Zbus_6, M12_Not_Zbus_7, M12_ZeroZ_Hi); and2 M12_UM12_3(M12_ZeroZ_Lo, M12_ZeroZ_Hi, M12_ZeroZ); inv M12_UM12_4(M12_ZeroZ, out407); inv M12_UM12_5(in213, M12_NotCont8); or2 M12_UM12_6(M12_NotCont8, in343, M12_ContFlag); inv M12_UM12_7(M12_ContFlag, M12_NotContFlag); and3 M12_UM12_8(M12_Not_Zbus_6, M12_Not_Zbus_7, M12_NotContFlag, M12_tmp0); nor2 M12_UM12_9(M12_tmp0, M12_ZeroZ, M12_tmp1); nand2 M12_UM12_10(in213, M12_tmp1, out409); inv M12_UM12_11_PT1_Xo0(in116, M12_UM12_11_PT1_NotA); inv M12_UM12_11_PT1_Xo1(in107, M12_UM12_11_PT1_NotB); nand2 M12_UM12_11_PT1_Xo2(M12_UM12_11_PT1_NotA, in107, M12_UM12_11_PT1_line2); nand2 M12_UM12_11_PT1_Xo3(M12_UM12_11_PT1_NotB, in116, M12_UM12_11_PT1_line3); nand2 M12_UM12_11_PT1_Xo4(M12_UM12_11_PT1_line2, M12_UM12_11_PT1_line3, M12_UM12_11_line1); inv M12_UM12_11_PT2_Xo0(in97, M12_UM12_11_PT2_NotA); inv M12_UM12_11_PT2_Xo1(in87, M12_UM12_11_PT2_NotB); nand2 M12_UM12_11_PT2_Xo2(M12_UM12_11_PT2_NotA, in87, M12_UM12_11_PT2_line2); nand2 M12_UM12_11_PT2_Xo3(M12_UM12_11_PT2_NotB, in97, M12_UM12_11_PT2_line3); nand2 M12_UM12_11_PT2_Xo4(M12_UM12_11_PT2_line2, M12_UM12_11_PT2_line3, M12_UM12_11_line2); inv M12_UM12_11_PT3_Xo0(in77, M12_UM12_11_PT3_NotA); inv M12_UM12_11_PT3_Xo1(in68, M12_UM12_11_PT3_NotB); nand2 M12_UM12_11_PT3_Xo2(M12_UM12_11_PT3_NotA, in68, M12_UM12_11_PT3_line2); nand2 M12_UM12_11_PT3_Xo3(M12_UM12_11_PT3_NotB, in77, M12_UM12_11_PT3_line3); nand2 M12_UM12_11_PT3_Xo4(M12_UM12_11_PT3_line2, M12_UM12_11_PT3_line3, M12_UM12_11_line3); inv M12_UM12_11_PT4_Xo0(in58, M12_UM12_11_PT4_NotA); inv M12_UM12_11_PT4_Xo1(in50, M12_UM12_11_PT4_NotB); nand2 M12_UM12_11_PT4_Xo2(M12_UM12_11_PT4_NotA, in50, M12_UM12_11_PT4_line2); nand2 M12_UM12_11_PT4_Xo3(M12_UM12_11_PT4_NotB, in58, M12_UM12_11_PT4_line3); nand2 M12_UM12_11_PT4_Xo4(M12_UM12_11_PT4_line2, M12_UM12_11_PT4_line3, M12_UM12_11_line4); inv M12_UM12_11_PT5_Xo0(M12_UM12_11_line1, M12_UM12_11_PT5_NotA); inv M12_UM12_11_PT5_Xo1(M12_UM12_11_line2, M12_UM12_11_PT5_NotB); nand2 M12_UM12_11_PT5_Xo2(M12_UM12_11_PT5_NotA, M12_UM12_11_line2, M12_UM12_11_PT5_line2); nand2 M12_UM12_11_PT5_Xo3(M12_UM12_11_PT5_NotB, M12_UM12_11_line1, M12_UM12_11_PT5_line3); nand2 M12_UM12_11_PT5_Xo4(M12_UM12_11_PT5_line2, M12_UM12_11_PT5_line3, M12_UM12_11_line5); inv M12_UM12_11_PT6_Xo0(M12_UM12_11_line3, M12_UM12_11_PT6_NotA); inv M12_UM12_11_PT6_Xo1(M12_UM12_11_line4, M12_UM12_11_PT6_NotB); nand2 M12_UM12_11_PT6_Xo2(M12_UM12_11_PT6_NotA, M12_UM12_11_line4, M12_UM12_11_PT6_line2); nand2 M12_UM12_11_PT6_Xo3(M12_UM12_11_PT6_NotB, M12_UM12_11_line3, M12_UM12_11_PT6_line3); nand2 M12_UM12_11_PT6_Xo4(M12_UM12_11_PT6_line2, M12_UM12_11_PT6_line3, M12_UM12_11_line6); inv M12_UM12_11_PT7_Xo0(M12_UM12_11_line5, M12_UM12_11_PT7_NotA); inv M12_UM12_11_PT7_Xo1(M12_UM12_11_line6, M12_UM12_11_PT7_NotB); nand2 M12_UM12_11_PT7_Xo2(M12_UM12_11_PT7_NotA, M12_UM12_11_line6, M12_UM12_11_PT7_line2); nand2 M12_UM12_11_PT7_Xo3(M12_UM12_11_PT7_NotB, M12_UM12_11_line5, M12_UM12_11_PT7_line3); nand2 M12_UM12_11_PT7_Xo4(M12_UM12_11_PT7_line2, M12_UM12_11_PT7_line3, M12_EvenParA); inv M12_UM12_12_PT1_Xo0(in270, M12_UM12_12_PT1_NotA); inv M12_UM12_12_PT1_Xo1(in264, M12_UM12_12_PT1_NotB); nand2 M12_UM12_12_PT1_Xo2(M12_UM12_12_PT1_NotA, in264, M12_UM12_12_PT1_line2); nand2 M12_UM12_12_PT1_Xo3(M12_UM12_12_PT1_NotB, in270, M12_UM12_12_PT1_line3); nand2 M12_UM12_12_PT1_Xo4(M12_UM12_12_PT1_line2, M12_UM12_12_PT1_line3, M12_UM12_12_line1); inv M12_UM12_12_PT2_Xo0(in257, M12_UM12_12_PT2_NotA); inv M12_UM12_12_PT2_Xo1(in250, M12_UM12_12_PT2_NotB); nand2 M12_UM12_12_PT2_Xo2(M12_UM12_12_PT2_NotA, in250, M12_UM12_12_PT2_line2); nand2 M12_UM12_12_PT2_Xo3(M12_UM12_12_PT2_NotB, in257, M12_UM12_12_PT2_line3); nand2 M12_UM12_12_PT2_Xo4(M12_UM12_12_PT2_line2, M12_UM12_12_PT2_line3, M12_UM12_12_line2); inv M12_UM12_12_PT3_Xo0(in244, M12_UM12_12_PT3_NotA); inv M12_UM12_12_PT3_Xo1(in238, M12_UM12_12_PT3_NotB); nand2 M12_UM12_12_PT3_Xo2(M12_UM12_12_PT3_NotA, in238, M12_UM12_12_PT3_line2); nand2 M12_UM12_12_PT3_Xo3(M12_UM12_12_PT3_NotB, in244, M12_UM12_12_PT3_line3); nand2 M12_UM12_12_PT3_Xo4(M12_UM12_12_PT3_line2, M12_UM12_12_PT3_line3, M12_UM12_12_line3); inv M12_UM12_12_PT4_Xo0(in232, M12_UM12_12_PT4_NotA); inv M12_UM12_12_PT4_Xo1(in226, M12_UM12_12_PT4_NotB); nand2 M12_UM12_12_PT4_Xo2(M12_UM12_12_PT4_NotA, in226, M12_UM12_12_PT4_line2); nand2 M12_UM12_12_PT4_Xo3(M12_UM12_12_PT4_NotB, in232, M12_UM12_12_PT4_line3); nand2 M12_UM12_12_PT4_Xo4(M12_UM12_12_PT4_line2, M12_UM12_12_PT4_line3, M12_UM12_12_line4); inv M12_UM12_12_PT5_Xo0(M12_UM12_12_line1, M12_UM12_12_PT5_NotA); inv M12_UM12_12_PT5_Xo1(M12_UM12_12_line2, M12_UM12_12_PT5_NotB); nand2 M12_UM12_12_PT5_Xo2(M12_UM12_12_PT5_NotA, M12_UM12_12_line2, M12_UM12_12_PT5_line2); nand2 M12_UM12_12_PT5_Xo3(M12_UM12_12_PT5_NotB, M12_UM12_12_line1, M12_UM12_12_PT5_line3); nand2 M12_UM12_12_PT5_Xo4(M12_UM12_12_PT5_line2, M12_UM12_12_PT5_line3, M12_UM12_12_line5); inv M12_UM12_12_PT6_Xo0(M12_UM12_12_line3, M12_UM12_12_PT6_NotA); inv M12_UM12_12_PT6_Xo1(M12_UM12_12_line4, M12_UM12_12_PT6_NotB); nand2 M12_UM12_12_PT6_Xo2(M12_UM12_12_PT6_NotA, M12_UM12_12_line4, M12_UM12_12_PT6_line2); nand2 M12_UM12_12_PT6_Xo3(M12_UM12_12_PT6_NotB, M12_UM12_12_line3, M12_UM12_12_PT6_line3); nand2 M12_UM12_12_PT6_Xo4(M12_UM12_12_PT6_line2, M12_UM12_12_PT6_line3, M12_UM12_12_line6); inv M12_UM12_12_PT7_Xo0(M12_UM12_12_line5, M12_UM12_12_PT7_NotA); inv M12_UM12_12_PT7_Xo1(M12_UM12_12_line6, M12_UM12_12_PT7_NotB); nand2 M12_UM12_12_PT7_Xo2(M12_UM12_12_PT7_NotA, M12_UM12_12_line6, M12_UM12_12_PT7_line2); nand2 M12_UM12_12_PT7_Xo3(M12_UM12_12_PT7_NotB, M12_UM12_12_line5, M12_UM12_12_PT7_line3); nand2 M12_UM12_12_PT7_Xo4(M12_UM12_12_PT7_line2, M12_UM12_12_PT7_line3, M12_EvenParB); inv M12_UM12_13_PT1_Xo0(out396, M12_UM12_13_PT1_NotA); inv M12_UM12_13_PT1_Xo1(out393, M12_UM12_13_PT1_NotB); nand2 M12_UM12_13_PT1_Xo2(M12_UM12_13_PT1_NotA, out393, M12_UM12_13_PT1_line2); nand2 M12_UM12_13_PT1_Xo3(M12_UM12_13_PT1_NotB, out396, M12_UM12_13_PT1_line3); nand2 M12_UM12_13_PT1_Xo4(M12_UM12_13_PT1_line2, M12_UM12_13_PT1_line3, M12_UM12_13_line1); inv M12_UM12_13_PT2_Xo0(out390, M12_UM12_13_PT2_NotA); inv M12_UM12_13_PT2_Xo1(out387, M12_UM12_13_PT2_NotB); nand2 M12_UM12_13_PT2_Xo2(M12_UM12_13_PT2_NotA, out387, M12_UM12_13_PT2_line2); nand2 M12_UM12_13_PT2_Xo3(M12_UM12_13_PT2_NotB, out390, M12_UM12_13_PT2_line3); nand2 M12_UM12_13_PT2_Xo4(M12_UM12_13_PT2_line2, M12_UM12_13_PT2_line3, M12_UM12_13_line2); inv M12_UM12_13_PT3_Xo0(out384, M12_UM12_13_PT3_NotA); inv M12_UM12_13_PT3_Xo1(out381, M12_UM12_13_PT3_NotB); nand2 M12_UM12_13_PT3_Xo2(M12_UM12_13_PT3_NotA, out381, M12_UM12_13_PT3_line2); nand2 M12_UM12_13_PT3_Xo3(M12_UM12_13_PT3_NotB, out384, M12_UM12_13_PT3_line3); nand2 M12_UM12_13_PT3_Xo4(M12_UM12_13_PT3_line2, M12_UM12_13_PT3_line3, M12_UM12_13_line3); inv M12_UM12_13_PT4_Xo0(out378, M12_UM12_13_PT4_NotA); inv M12_UM12_13_PT4_Xo1(out375, M12_UM12_13_PT4_NotB); nand2 M12_UM12_13_PT4_Xo2(M12_UM12_13_PT4_NotA, out375, M12_UM12_13_PT4_line2); nand2 M12_UM12_13_PT4_Xo3(M12_UM12_13_PT4_NotB, out378, M12_UM12_13_PT4_line3); nand2 M12_UM12_13_PT4_Xo4(M12_UM12_13_PT4_line2, M12_UM12_13_PT4_line3, M12_UM12_13_line4); inv M12_UM12_13_PT5_Xo0(M12_UM12_13_line1, M12_UM12_13_PT5_NotA); inv M12_UM12_13_PT5_Xo1(M12_UM12_13_line2, M12_UM12_13_PT5_NotB); nand2 M12_UM12_13_PT5_Xo2(M12_UM12_13_PT5_NotA, M12_UM12_13_line2, M12_UM12_13_PT5_line2); nand2 M12_UM12_13_PT5_Xo3(M12_UM12_13_PT5_NotB, M12_UM12_13_line1, M12_UM12_13_PT5_line3); nand2 M12_UM12_13_PT5_Xo4(M12_UM12_13_PT5_line2, M12_UM12_13_PT5_line3, M12_UM12_13_line5); inv M12_UM12_13_PT6_Xo0(M12_UM12_13_line3, M12_UM12_13_PT6_NotA); inv M12_UM12_13_PT6_Xo1(M12_UM12_13_line4, M12_UM12_13_PT6_NotB); nand2 M12_UM12_13_PT6_Xo2(M12_UM12_13_PT6_NotA, M12_UM12_13_line4, M12_UM12_13_PT6_line2); nand2 M12_UM12_13_PT6_Xo3(M12_UM12_13_PT6_NotB, M12_UM12_13_line3, M12_UM12_13_PT6_line3); nand2 M12_UM12_13_PT6_Xo4(M12_UM12_13_PT6_line2, M12_UM12_13_PT6_line3, M12_UM12_13_line6); inv M12_UM12_13_PT7_Xo0(M12_UM12_13_line5, M12_UM12_13_PT7_NotA); inv M12_UM12_13_PT7_Xo1(M12_UM12_13_line6, M12_UM12_13_PT7_NotB); nand2 M12_UM12_13_PT7_Xo2(M12_UM12_13_PT7_NotA, M12_UM12_13_line6, M12_UM12_13_PT7_line2); nand2 M12_UM12_13_PT7_Xo3(M12_UM12_13_PT7_NotB, M12_UM12_13_line5, M12_UM12_13_PT7_line3); nand2 M12_UM12_13_PT7_Xo4(M12_UM12_13_PT7_line2, M12_UM12_13_PT7_line3, M12_EvenParZ); and2 M12_UM12_14(M12_NotContFlag, in2897, M12_ContPar); and2 M12_UM12_15(M12_ContFlag, out375, M12_PZ7); and2 M12_UM12_16(M12_ContFlag, out378, M12_PZ6); inv M12_UM12_17_PT1_Xo0(out396, M12_UM12_17_PT1_NotA); inv M12_UM12_17_PT1_Xo1(out393, M12_UM12_17_PT1_NotB); nand2 M12_UM12_17_PT1_Xo2(M12_UM12_17_PT1_NotA, out393, M12_UM12_17_PT1_line2); nand2 M12_UM12_17_PT1_Xo3(M12_UM12_17_PT1_NotB, out396, M12_UM12_17_PT1_line3); nand2 M12_UM12_17_PT1_Xo4(M12_UM12_17_PT1_line2, M12_UM12_17_PT1_line3, M12_UM12_17_line1); inv M12_UM12_17_PT2_Xo0(out390, M12_UM12_17_PT2_NotA); inv M12_UM12_17_PT2_Xo1(out387, M12_UM12_17_PT2_NotB); nand2 M12_UM12_17_PT2_Xo2(M12_UM12_17_PT2_NotA, out387, M12_UM12_17_PT2_line2); nand2 M12_UM12_17_PT2_Xo3(M12_UM12_17_PT2_NotB, out390, M12_UM12_17_PT2_line3); nand2 M12_UM12_17_PT2_Xo4(M12_UM12_17_PT2_line2, M12_UM12_17_PT2_line3, M12_UM12_17_line2); inv M12_UM12_17_PT3_Xo0(out384, M12_UM12_17_PT3_NotA); inv M12_UM12_17_PT3_Xo1(out381, M12_UM12_17_PT3_NotB); nand2 M12_UM12_17_PT3_Xo2(M12_UM12_17_PT3_NotA, out381, M12_UM12_17_PT3_line2); nand2 M12_UM12_17_PT3_Xo3(M12_UM12_17_PT3_NotB, out384, M12_UM12_17_PT3_line3); nand2 M12_UM12_17_PT3_Xo4(M12_UM12_17_PT3_line2, M12_UM12_17_PT3_line3, M12_UM12_17_line3); inv M12_UM12_17_PT4_Xo0(M12_PZ6, M12_UM12_17_PT4_NotA); inv M12_UM12_17_PT4_Xo1(M12_PZ7, M12_UM12_17_PT4_NotB); nand2 M12_UM12_17_PT4_Xo2(M12_UM12_17_PT4_NotA, M12_PZ7, M12_UM12_17_PT4_line2); nand2 M12_UM12_17_PT4_Xo3(M12_UM12_17_PT4_NotB, M12_PZ6, M12_UM12_17_PT4_line3); nand2 M12_UM12_17_PT4_Xo4(M12_UM12_17_PT4_line2, M12_UM12_17_PT4_line3, M12_UM12_17_line4); inv M12_UM12_17_PT5_Xo0(M12_UM12_17_line1, M12_UM12_17_PT5_NotA); inv M12_UM12_17_PT5_Xo1(M12_UM12_17_line2, M12_UM12_17_PT5_NotB); nand2 M12_UM12_17_PT5_Xo2(M12_UM12_17_PT5_NotA, M12_UM12_17_line2, M12_UM12_17_PT5_line2); nand2 M12_UM12_17_PT5_Xo3(M12_UM12_17_PT5_NotB, M12_UM12_17_line1, M12_UM12_17_PT5_line3); nand2 M12_UM12_17_PT5_Xo4(M12_UM12_17_PT5_line2, M12_UM12_17_PT5_line3, M12_UM12_17_line5); inv M12_UM12_17_PT6_Xo3_0(M12_UM12_17_line3, M12_UM12_17_PT6_NotA); inv M12_UM12_17_PT6_Xo3_1(M12_UM12_17_line4, M12_UM12_17_PT6_NotB); inv M12_UM12_17_PT6_Xo3_2(M12_ContPar, M12_UM12_17_PT6_NotC); and3 M12_UM12_17_PT6_Xo3_3(M12_UM12_17_PT6_NotA, M12_UM12_17_PT6_NotB, M12_ContPar, M12_UM12_17_PT6_line3); and3 M12_UM12_17_PT6_Xo3_4(M12_UM12_17_PT6_NotA, M12_UM12_17_line4, M12_UM12_17_PT6_NotC, M12_UM12_17_PT6_line4); and3 M12_UM12_17_PT6_Xo3_5(M12_UM12_17_line3, M12_UM12_17_PT6_NotB, M12_UM12_17_PT6_NotC, M12_UM12_17_PT6_line5); and3 M12_UM12_17_PT6_Xo3_6(M12_UM12_17_line3, M12_UM12_17_line4, M12_ContPar, M12_UM12_17_PT6_line6); nor2 M12_UM12_17_PT6_Xo3_7(M12_UM12_17_PT6_line3, M12_UM12_17_PT6_line4, M12_UM12_17_PT6_line7); nor2 M12_UM12_17_PT6_Xo3_8(M12_UM12_17_PT6_line5, M12_UM12_17_PT6_line6, M12_UM12_17_PT6_line8); nand2 M12_UM12_17_PT6_Xo3_9(M12_UM12_17_PT6_line7, M12_UM12_17_PT6_line8, M12_UM12_17_line6); inv M12_UM12_17_PT7_Xo0(M12_UM12_17_line5, M12_UM12_17_PT7_NotA); inv M12_UM12_17_PT7_Xo1(M12_UM12_17_line6, M12_UM12_17_PT7_NotB); nand2 M12_UM12_17_PT7_Xo2(M12_UM12_17_PT7_NotA, M12_UM12_17_line6, M12_UM12_17_PT7_line2); nand2 M12_UM12_17_PT7_Xo3(M12_UM12_17_PT7_NotB, M12_UM12_17_line5, M12_UM12_17_PT7_line3); nand2 M12_UM12_17_PT7_Xo4(M12_UM12_17_PT7_line2, M12_UM12_17_PT7_line3, M12_EvenParZ_Cont); inv M12_UM12_18(M12_EvenParA, out351); inv M12_UM12_19(M12_EvenParB, out358); inv M12_UM12_20(M12_EvenParZ, out402); inv M12_UM12_21(M12_EvenParZ_Cont, out405); inv M13_UM13_0_Inv8_0_Inv4_0(in116, M13_Not_Abus_0); inv M13_UM13_0_Inv8_0_Inv4_1(in107, M13_Not_Abus_1); inv M13_UM13_0_Inv8_0_Inv4_2(in97, M13_Not_Abus_2); inv M13_UM13_0_Inv8_0_Inv4_3(in87, M13_Not_Abus_3); inv M13_UM13_0_Inv8_1_Inv4_0(in77, M13_Not_Abus_4); inv M13_UM13_0_Inv8_1_Inv4_1(in68, M13_Not_Abus_5); inv M13_UM13_0_Inv8_1_Inv4_2(in58, M13_Not_Abus_6); inv M13_UM13_0_Inv8_1_Inv4_3(in50, M13_Not_Abus_7); inv M13_UM13_1_Xo0(in68, M13_UM13_1_NotA); inv M13_UM13_1_Xo1(in58, M13_UM13_1_NotB); nand2 M13_UM13_1_Xo2(M13_UM13_1_NotA, in58, M13_UM13_1_line2); nand2 M13_UM13_1_Xo3(M13_UM13_1_NotB, in68, M13_UM13_1_line3); nand2 M13_UM13_1_Xo4(M13_UM13_1_line2, M13_UM13_1_line3, M13_tmp0); and3 M13_UM13_2(M13_tmp0, in77, in50, M13_tmp1); and2 M13_UM13_3(in68, M13_Not_Abus_7, M13_tmp2); or2 M13_UM13_4(M13_tmp1, M13_tmp2, M13_Misc0_0); inv M13_UM13_5_Xo0(in107, M13_UM13_5_NotA); inv M13_UM13_5_Xo1(in97, M13_UM13_5_NotB); nand2 M13_UM13_5_Xo2(M13_UM13_5_NotA, in97, M13_UM13_5_line2); nand2 M13_UM13_5_Xo3(M13_UM13_5_NotB, in107, M13_UM13_5_line3); nand2 M13_UM13_5_Xo4(M13_UM13_5_line2, M13_UM13_5_line3, M13_tmp3); and2 M13_UM13_6(in116, M13_tmp3, M13_Misc0_1); inv M13_UM13_7(in13, M13_NotCont1); inv M13_UM13_8(in41, M13_NotCont5); nand2 M13_UM13_9(in1, M13_NotCont1, M13_ContHi_Misc0); nand3 M13_UM13_10(in1, in13, in20, M13_ContLo_Misc0); inv M13_UM13_11_Mux3c_0(M13_ContHi_Misc0, M13_UM13_11_NotContHi); inv M13_UM13_11_Mux3c_1(M13_ContLo_Misc0, M13_UM13_11_NotContLo); and2 M13_UM13_11_Mux3c_2(M13_Misc0_0, M13_UM13_11_NotContHi, M13_UM13_11_line2); and2 M13_UM13_11_Mux3c_3(M13_Misc0_1, M13_UM13_11_NotContLo, M13_UM13_11_line3); and2 M13_UM13_11_Mux3c_4(M13_ContHi_Misc0, M13_ContLo_Misc0, M13_UM13_11_line4); and2 M13_UM13_11_Mux3c_5(M13_UM13_11_line4, Overflow, M13_UM13_11_line5); or3 M13_UM13_11_Mux3c_6(M13_UM13_11_line2, M13_UM13_11_line3, M13_UM13_11_line5, out367); or2 M13_UM13_12(in68, in58, M13_tmp4); and2 M13_UM13_13(in50, M13_tmp4, M13_Misc1_0); and4 M13_UM13_14(M13_Not_Abus_0, M13_Not_Abus_1, M13_Not_Abus_2, M13_Not_Abus_3, M13_Misc1_2); nand4 M13_UM13_27(in1, M13_NotCont1, in20, M13_NotCont5, M13_ContHi_Misc1); inv M13_UM13_28_Mux3c_0(M13_ContHi_Misc1, M13_UM13_28_NotContHi); inv M13_UM13_28_Mux3c_1(in1, M13_UM13_28_NotContLo); and2 M13_UM13_28_Mux3c_2(M13_Misc1_0, M13_UM13_28_NotContHi, M13_UM13_28_line2); and2 M13_UM13_28_Mux3c_3(Carry4, M13_UM13_28_NotContLo, M13_UM13_28_line3); and2 M13_UM13_28_Mux3c_4(M13_ContHi_Misc1, in1, M13_UM13_28_line4); and2 M13_UM13_28_Mux3c_5(M13_UM13_28_line4, M13_Misc1_2, M13_UM13_28_line5); or3 M13_UM13_28_Mux3c_6(M13_UM13_28_line2, M13_UM13_28_line3, M13_UM13_28_line5, out364); or2 M13_UM13_29(in264, in257, M13_tmp5); and2 M13_UM13_30(in250, M13_tmp5, M13_Misc2_1); nand2 M13_UM13_31(in116, in270, M13_pr0); nand2 M13_UM13_32(in107, in264, M13_pr1); nand2 M13_UM13_33(in97, in257, M13_pr2); nand2 M13_UM13_34(in87, in250, M13_pr3); nand2 M13_UM13_35(in77, in244, M13_pr4); nand2 M13_UM13_36(in68, in238, M13_pr5); nand2 M13_UM13_37(in58, in232, M13_pr6); nand2 M13_UM13_38(in50, in226, M13_pr7); and4 M13_UM13_39(M13_pr0, M13_pr1, M13_pr2, M13_pr3, M13_pr3_0); and4 M13_UM13_40(M13_pr4, M13_pr5, M13_pr6, M13_pr7, M13_pr7_4); nand2 M13_UM13_41(M13_pr3_0, M13_pr7_4, M13_Misc2_2); nand3 M13_UM13_42(in1, M13_NotCont1, in20, M13_ContLo_Misc2); inv M13_UM13_43_Mux3c_0(M13_ContLo_Misc0, M13_UM13_43_NotContHi); inv M13_UM13_43_Mux3c_1(M13_ContLo_Misc2, M13_UM13_43_NotContLo); and2 M13_UM13_43_Mux3c_2(M13_Misc1_0, M13_UM13_43_NotContHi, M13_UM13_43_line2); and2 M13_UM13_43_Mux3c_3(M13_Misc2_1, M13_UM13_43_NotContLo, M13_UM13_43_line3); and2 M13_UM13_43_Mux3c_4(M13_ContLo_Misc0, M13_ContLo_Misc2, M13_UM13_43_line4); and2 M13_UM13_43_Mux3c_5(M13_UM13_43_line4, M13_Misc2_2, M13_UM13_43_line5); or3 M13_UM13_43_Mux3c_6(M13_UM13_43_line2, M13_UM13_43_line3, M13_UM13_43_line5, M13_NotMiscOuts2); inv M13_UM13_43_1(M13_NotMiscOuts2, out361); or2 M13_UM13_44(in107, in97, M13_tmp6); and2 M13_UM13_45(in87, M13_tmp6, M13_tmp7); inv M13_UM13_46(M13_tmp7, out355); and4 M13_UM13_47(M13_Not_Abus_4, M13_Not_Abus_5, M13_Not_Abus_6, M13_Not_Abus_7, out353); assign out399 = XCarrybus_2; assign gnd = 1'b0; endmodule |
Added c432.gif.
cannot compute difference between binary files
Added c432.html.
> > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C432 27-channel interrupt controller</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="c432.gif" WIDTH=469 HEIGHT=394></P> <B><P>Statistics: </B>36 inputs; 7 outputs; 160 gates; <A HREF="c432bus.html">bus translations</A></P> <B><P>Function: </B>c432 is a 27-channel interrupt controller. The input channels are grouped into three 9-bit buses (we call them A, B and C), where the bit position within each bus determines the interrupt request priority. A forth 9-bit input bus (called E) enables and disables interrupt requests within the respective bit positions. The figure above concisely represents the circuit. The figure above contains the modules labeled <A HREF="c432m1.html">M1</A>, <A HREF="c432m2.html">M2</A>, <A HREF="c432m3.html">M3</A>, <A HREF="c432m4.html">M4</A>, and <A HREF="c432m5.html">M5</A>, which contain the underlying logic. </P> <P>The interrupt controller has three interrupt request buses A, B and C, each having nine bits or channels, and one channel-enable bus E. The following priority rules apply: A[i] > B[j] > C[k], for any i, j, k; i.e., bus A has the highest priority and bus C the lowest. Within each bus, a channel with a higher index has priority over one with a lower index; for example, A[i] > A[j], if i > j. If E[i] = 0, then the A[i], B[i], and C[i] inputs are disregarded.</P> <P>The seven outputs PA, PB, PC and Chan[3:0] specify which channels have acknowledged interrupt requests. Only the channel of highest priority in the requesting bus of highest priority is acknowledged. One exception is that if two or more interrupts produce requests on the channel that is acknowledged, each bus is acknowledged. For example, if A[4], A[2], B[6] and C[4] have requests pending, A[4] and C[4] are acknowledged. Module M5 is a 9-line-to-4-line priority encoder. The output line numbered 421 actually produces the inverted Chan[3] response of that shown in the <A HREF="c432m5tt.html">truth table</A>. We have taken the liberty of adding an inverter to output 421 to form Chan[3] for this table (but not in the models). </P> <B><P>Models:</P> <UL> </B><LI><A HREF="c432.isc">c432 ISCAS-85 netlist</A><B> </LI> </B><LI><A HREF="c432.v">c432 Verilog hierarchical structural model</A><B> </LI> </B><LI><A HREF="c432b.v">c432 Verilog hierarchical behavioral model</A> </LI> <LI><A HREF="c432.tests">c432 complete gate-level tests</A></LI></UL> <B><P> </P> </B><P> </P></BODY> </HTML> |
Added c432.isc.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 |
* combinational logic example "c432"
*-------------------------------------------------------------
*
*
* total number of lines in the netlist .............. 432
* simplistically reduced equivalent fault set size = 524
* lines from primary input gates ....... 36
* lines from primary output gates ....... 7
* lines from interior gate outputs ...... 153
* lines from ** 89 ** fanout stems ... 236
*
* avg_fanin = 2.10, max_fanin = 9
* avg_fanout = 2.65, max_fanout = 9
*
*
*
*
*
1 1gat inpt 2 0 >sa0 >sa1
2 1f01 from 1gat
3 1f02 from 1gat >sa1
4 4gat inpt 3 0 >sa0 >sa1
5 4f01 from 4gat >sa1
6 4f02 from 4gat
7 4f03 from 4gat >sa1
8 8gat inpt 2 0 >sa0 >sa1
9 8f01 from 8gat >sa0
10 8f02 from 8gat >sa1
11 11gat inpt 2 0 >sa0 >sa1
12 11f01 from 11gat
13 11f02 from 11gat >sa1
14 14gat inpt 2 0 >sa0 >sa1
15 14f01 from 14gat >sa0
16 14f02 from 14gat >sa1
17 17gat inpt 3 0 >sa0 >sa1
18 17f01 from 17gat >sa1
19 17f02 from 17gat
20 17f03 from 17gat >sa1
21 21gat inpt 2 0 >sa0 >sa1
22 21f01 from 21gat >sa0
23 21f02 from 21gat >sa1
24 24gat inpt 2 0 >sa0 >sa1
25 24f01 from 24gat
26 24f02 from 24gat >sa1
27 27gat inpt 2 0 >sa0 >sa1
28 27f01 from 27gat >sa0
29 27f02 from 27gat >sa1
30 30gat inpt 3 0 >sa0 >sa1
31 30f01 from 30gat >sa1
32 30f02 from 30gat
33 30f03 from 30gat >sa1
34 34gat inpt 2 0 >sa0 >sa1
35 34f01 from 34gat >sa0
36 34f02 from 34gat >sa1
37 37gat inpt 2 0 >sa0 >sa1
38 37f01 from 37gat
39 37f02 from 37gat >sa1
40 40gat inpt 2 0 >sa0 >sa1
41 40f01 from 40gat >sa0
42 40f02 from 40gat >sa1
43 43gat inpt 3 0 >sa0 >sa1
44 43f01 from 43gat >sa1
45 43f02 from 43gat
46 43f03 from 43gat >sa1
47 47gat inpt 2 0 >sa0 >sa1
48 47f01 from 47gat >sa0
49 47f02 from 47gat >sa1
50 50gat inpt 2 0 >sa0 >sa1
51 50f01 from 50gat
52 50f02 from 50gat >sa1
53 53gat inpt 2 0 >sa0 >sa1
54 53f01 from 53gat >sa0
55 53f02 from 53gat >sa1
56 56gat inpt 3 0 >sa0 >sa1
57 56f01 from 56gat >sa1
58 56f02 from 56gat
59 56f03 from 56gat >sa1
60 60gat inpt 2 0 >sa0 >sa1
61 60f01 from 60gat >sa0
62 60f02 from 60gat >sa1
63 63gat inpt 2 0 >sa0 >sa1
64 63f01 from 63gat
65 63f02 from 63gat >sa1
66 66gat inpt 2 0 >sa0 >sa1
67 66f01 from 66gat >sa0
68 66f02 from 66gat >sa1
69 69gat inpt 3 0 >sa0 >sa1
70 69f01 from 69gat >sa1
71 69f02 from 69gat
72 69f03 from 69gat >sa1
73 73gat inpt 2 0 >sa0 >sa1
74 73f01 from 73gat >sa0
75 73f02 from 73gat >sa1
76 76gat inpt 2 0 >sa0 >sa1
77 76f01 from 76gat
78 76f02 from 76gat >sa1
79 79gat inpt 2 0 >sa0 >sa1
80 79f01 from 79gat >sa0
81 79f02 from 79gat >sa1
82 82gat inpt 3 0 >sa0 >sa1
83 82f01 from 82gat >sa1
84 82f02 from 82gat
85 82f03 from 82gat >sa1
86 86gat inpt 2 0 >sa0 >sa1
87 86f01 from 86gat >sa0
88 86f02 from 86gat >sa1
89 89gat inpt 2 0 >sa0 >sa1
90 89f01 from 89gat
91 89f02 from 89gat >sa1
92 92gat inpt 2 0 >sa0 >sa1
93 92f01 from 92gat >sa0
94 92f02 from 92gat >sa1
95 95gat inpt 3 0 >sa0 >sa1
96 95f01 from 95gat >sa1
97 95f02 from 95gat
98 95f03 from 95gat >sa1
99 99gat inpt 2 0 >sa0 >sa1
100 99f01 from 99gat >sa0
101 99f02 from 99gat >sa1
102 102gat inpt 2 0 >sa0 >sa1
103 102f01 from 102gat
104 102f02 from 102gat >sa1
105 105gat inpt 2 0 >sa0 >sa1
106 105f01 from 105gat >sa0
107 105f02 from 105gat >sa1
108 108gat inpt 3 0 >sa0 >sa1
109 108f01 from 108gat >sa1
110 108f02 from 108gat
111 108f03 from 108gat >sa1
112 112gat inpt 2 0 >sa0 >sa1
113 112f01 from 112gat >sa0
114 112f02 from 112gat >sa1
115 115gat inpt 2 0 >sa0 >sa1
116 115f01 from 115gat >sa0
117 115f02 from 115gat >sa1
118 118gat not 1 1 >sa1
2
119 119gat not 2 1 >sa0 >sa1
6
120 119f01 from 119gat >sa0
121 119f02 from 119gat >sa0
122 122gat not 1 1 >sa1
12
123 123gat not 2 1 >sa0 >sa1
19
124 123f01 from 123gat >sa0
125 123f02 from 123gat >sa0
126 126gat not 1 1 >sa1
25
127 127gat not 2 1 >sa0 >sa1
32
128 127f01 from 127gat >sa0
129 127f02 from 127gat >sa0
130 130gat not 1 1 >sa1
38
131 131gat not 2 1 >sa0 >sa1
45
132 131f01 from 131gat >sa0
133 131f02 from 131gat >sa0
134 134gat not 1 1 >sa1
51
135 135gat not 2 1 >sa0 >sa1
58
136 135f01 from 135gat >sa0
137 135f02 from 135gat >sa0
138 138gat not 1 1 >sa1
64
139 139gat not 2 1 >sa0 >sa1
71
140 139f01 from 139gat >sa0
141 139f02 from 139gat >sa0
142 142gat not 1 1 >sa1
77
143 143gat not 2 1 >sa0 >sa1
84
144 143f01 from 143gat >sa0
145 143f02 from 143gat >sa0
146 146gat not 1 1 >sa1
90
147 147gat not 2 1 >sa0 >sa1
97
148 147f01 from 147gat >sa0
149 147f02 from 147gat >sa0
150 150gat not 1 1 >sa1
103
151 151gat not 2 1 >sa0 >sa1
110
152 151f01 from 151gat >sa0
153 151f02 from 151gat >sa0
154 154gat nand 2 2 >sa0 >sa1
118 5
155 154f01 from 154gat >sa1
156 154f02 from 154gat >sa0 >sa1
157 157gat nor 1 2 >sa1
9 120
158 158gat nor 1 2 >sa1
15 121
159 159gat nand 2 2 >sa0 >sa1
122 18
160 159f01 from 159gat >sa1
161 159f02 from 159gat >sa0 >sa1
162 162gat nand 2 2 >sa0 >sa1
126 31
163 162f01 from 162gat >sa1
164 162f02 from 162gat >sa0 >sa1
165 165gat nand 2 2 >sa0 >sa1
130 44
166 165f01 from 165gat >sa1
167 165f02 from 165gat >sa0 >sa1
168 168gat nand 2 2 >sa0 >sa1
134 57
169 168f01 from 168gat >sa1
170 168f02 from 168gat >sa0 >sa1
171 171gat nand 2 2 >sa0 >sa1
138 70
172 171f01 from 171gat >sa1
173 171f02 from 171gat >sa0 >sa1
174 174gat nand 2 2 >sa0 >sa1
142 83
175 174f01 from 174gat >sa1
176 174f02 from 174gat >sa0 >sa1
177 177gat nand 2 2 >sa0 >sa1
146 96
178 177f01 from 177gat >sa1
179 177f02 from 177gat >sa0 >sa1
180 180gat nand 2 2 >sa0 >sa1
150 109
181 180f01 from 180gat >sa1
182 180f02 from 180gat >sa0 >sa1
183 183gat nor 1 2 >sa1
22 124
184 184gat nor 1 2 >sa1
28 125
185 185gat nor 1 2 >sa1
35 128
186 186gat nor 1 2 >sa1
41 129
187 187gat nor 1 2 >sa1
48 132
188 188gat nor 1 2 >sa1
54 133
189 189gat nor 1 2 >sa1
61 136
190 190gat nor 1 2 >sa1
67 137
191 191gat nor 1 2 >sa1
74 140
192 192gat nor 1 2 >sa1
80 141
193 193gat nor 1 2 >sa1
87 144
194 194gat nor 1 2 >sa1
93 145
195 195gat nor 1 2 >sa1
100 148
196 196gat nor 1 2 >sa1
106 149
197 197gat nor 1 2 >sa1
113 152
198 198gat nor 1 2 >sa1
116 153
199 199gat and 3 9 >sa0 >sa1
155 160 163 166 169 172 175 178 181
200 199f01 from 199gat
201 199f02 from 199gat
202 199f03 from 199gat
203 203gat not 9 1 >sa0 >sa1
200
204 203f01 from 203gat >sa0 >sa1
205 203f02 from 203gat >sa0 >sa1
206 203f03 from 203gat >sa0 >sa1
207 203f04 from 203gat >sa0 >sa1
208 203f05 from 203gat >sa0 >sa1
209 203f06 from 203gat >sa0 >sa1
210 203f07 from 203gat >sa0 >sa1
211 203f08 from 203gat >sa0 >sa1
212 203f09 from 203gat >sa0 >sa1
213 213gat not 9 1 >sa0 >sa1
201
214 213f01 from 213gat >sa1
215 213f02 from 213gat >sa1
216 213f03 from 213gat >sa1
217 213f04 from 213gat >sa1
218 213f05 from 213gat >sa1
219 213f06 from 213gat >sa1
220 213f07 from 213gat >sa1
221 213f08 from 213gat >sa1
222 213f09 from 213gat >sa1
223 223gat not 0 1 >sa0 >sa1
202
224 224gat xor 2 2 >sa0 >sa1
204 156
225 224f01 from 224gat >sa1
226 224f02 from 224gat >sa1
227 227gat xor 2 2 >sa0 >sa1
205 161
228 227f01 from 227gat >sa1
229 227f02 from 227gat >sa1
230 230gat xor 2 2 >sa0 >sa1
206 164
231 230f01 from 230gat >sa1
232 230f02 from 230gat >sa1
233 233gat xor 2 2 >sa0 >sa1
207 167
234 233f01 from 233gat >sa1
235 233f02 from 233gat >sa1
236 236gat xor 2 2 >sa0 >sa1
208 170
237 236f01 from 236gat >sa1
238 236f02 from 236gat >sa1
239 239gat xor 2 2 >sa0 >sa1
209 173
240 239f01 from 239gat >sa1
241 239f02 from 239gat >sa1
242 242gat nand 1 2 >sa1
3 214
243 243gat xor 2 2 >sa0 >sa1
210 176
244 243f01 from 243gat >sa1
245 243f02 from 243gat >sa1
246 246gat nand 1 2 >sa1
215 13
247 247gat xor 2 2 >sa0 >sa1
211 179
248 247f01 from 247gat >sa1
249 247f02 from 247gat >sa1
250 250gat nand 1 2 >sa1
216 26
251 251gat xor 2 2 >sa0 >sa1
212 182
252 251f01 from 251gat >sa1
253 251f02 from 251gat >sa1
254 254gat nand 1 2 >sa1
217 39
255 255gat nand 1 2 >sa1
218 52
256 256gat nand 1 2 >sa1
219 65
257 257gat nand 1 2 >sa1
220 78
258 258gat nand 1 2 >sa1
221 91
259 259gat nand 1 2 >sa1
222 104
260 260gat nand 2 2 >sa0 >sa1
225 157
261 260f01 from 260gat >sa1
262 260f02 from 260gat >sa0 >sa1
263 263gat nand 1 2
226 158
264 264gat nand 2 2 >sa0 >sa1
228 183
265 264f01 from 264gat >sa1
266 264f02 from 264gat >sa0 >sa1
267 267gat nand 2 2 >sa0 >sa1
231 185
268 267f01 from 267gat >sa1
269 267f02 from 267gat >sa0 >sa1
270 270gat nand 2 2 >sa0 >sa1
234 187
271 270f01 from 270gat >sa1
272 270f02 from 270gat >sa0 >sa1
273 273gat nand 2 2 >sa0 >sa1
237 189
274 273f01 from 273gat >sa1
275 273f02 from 273gat >sa0 >sa1
276 276gat nand 2 2 >sa0 >sa1
240 191
277 276f01 from 276gat >sa1
278 276f02 from 276gat >sa0 >sa1
279 279gat nand 2 2 >sa0 >sa1
244 193
280 279f01 from 279gat >sa1
281 279f02 from 279gat >sa0 >sa1
282 282gat nand 2 2 >sa0 >sa1
248 195
283 282f01 from 282gat >sa1
284 282f02 from 282gat >sa0 >sa1
285 285gat nand 2 2 >sa0 >sa1
252 197
286 285f01 from 285gat >sa1
287 285f02 from 285gat >sa0 >sa1
288 288gat nand 1 2
229 184
289 289gat nand 1 2
232 186
290 290gat nand 1 2
235 188
291 291gat nand 1 2
238 190
292 292gat nand 1 2
241 192
293 293gat nand 1 2
245 194
294 294gat nand 1 2
249 196
295 295gat nand 1 2
253 198
296 296gat and 3 9 >sa0 >sa1
261 265 268 271 274 277 280 283 286
297 296f01 from 296gat
298 296f02 from 296gat
299 296f03 from 296gat
300 300gat not 1 1 >sa1
263
301 301gat not 1 1 >sa1
288
302 302gat not 1 1 >sa1
289
303 303gat not 1 1 >sa1
290
304 304gat not 1 1 >sa1
291
305 305gat not 1 1 >sa1
292
306 306gat not 1 1 >sa1
293
307 307gat not 1 1 >sa1
294
308 308gat not 1 1 >sa1
295
309 309gat not 9 1 >sa0 >sa1
297
310 309f01 from 309gat >sa0 >sa1
311 309f02 from 309gat >sa0 >sa1
312 309f03 from 309gat >sa0 >sa1
313 309f04 from 309gat >sa0 >sa1
314 309f05 from 309gat >sa0 >sa1
315 309f06 from 309gat >sa0 >sa1
316 309f07 from 309gat >sa0 >sa1
317 309f08 from 309gat >sa0 >sa1
318 309f09 from 309gat >sa0 >sa1
319 319gat not 9 1 >sa0 >sa1
298
320 319f01 from 319gat >sa1
321 319f02 from 319gat >sa1
322 319f03 from 319gat >sa1
323 319f04 from 319gat >sa1
324 319f05 from 319gat >sa1
325 319f06 from 319gat >sa1
326 319f07 from 319gat >sa1
327 319f08 from 319gat >sa1
328 319f09 from 319gat >sa1
329 329gat not 0 1 >sa0 >sa1
299
330 330gat xor 1 2 >sa1
310 262
331 331gat xor 1 2 >sa1
311 266
332 332gat xor 1 2 >sa1
312 269
333 333gat xor 1 2 >sa1
313 272
334 334gat nand 1 2 >sa1
10 320
335 335gat xor 1 2 >sa1
314 275
336 336gat nand 1 2 >sa1
321 23
337 337gat xor 1 2 >sa1
315 278
338 338gat nand 1 2 >sa1
322 36
339 339gat xor 1 2 >sa1
316 281
340 340gat nand 1 2 >sa1
323 49
341 341gat xor 1 2 >sa1
317 284
342 342gat nand 1 2 >sa1
324 62
343 343gat xor 1 2 >sa1
318 287
344 344gat nand 1 2 >sa1
325 75
345 345gat nand 1 2 >sa1
326 88
346 346gat nand 1 2 >sa1
327 101
347 347gat nand 1 2 >sa1
328 114
348 348gat nand 1 2 >sa1
330 300
349 349gat nand 1 2 >sa1
331 301
350 350gat nand 1 2 >sa1
332 302
351 351gat nand 1 2 >sa1
333 303
352 352gat nand 1 2 >sa1
335 304
353 353gat nand 1 2 >sa1
337 305
354 354gat nand 1 2 >sa1
339 306
355 355gat nand 1 2 >sa1
341 307
356 356gat nand 1 2 >sa1
343 308
357 357gat and 2 9 >sa0 >sa1
348 349 350 351 352 353 354 355 356
358 357f01 from 357gat
359 357f02 from 357gat
360 360gat not 9 1 >sa0 >sa1
358
361 360f01 from 360gat >sa1
362 360f02 from 360gat >sa1
363 360f03 from 360gat >sa1
364 360f04 from 360gat >sa1
365 360f05 from 360gat >sa1
366 360f06 from 360gat >sa1
367 360f07 from 360gat >sa1
368 360f08 from 360gat >sa1
369 360f09 from 360gat >sa1
370 370gat not 0 1 >sa0 >sa1
359
371 371gat nand 1 2 >sa1
16 361
372 372gat nand 1 2 >sa1
362 29
373 373gat nand 1 2 >sa1
363 42
374 374gat nand 1 2 >sa1
364 55
375 375gat nand 1 2 >sa1
365 68
376 376gat nand 1 2 >sa1
366 81
377 377gat nand 1 2 >sa1
367 94
378 378gat nand 1 2 >sa1
368 107
379 379gat nand 1 2 >sa1
369 117
380 380gat nand 1 4
7 242 334 371
381 381gat nand 4 4 >sa0 >sa1
246 336 372 20
382 381f01 from 381gat >sa1
383 381f02 from 381gat >sa1
384 381f03 from 381gat >sa1
385 381f04 from 381gat >sa1
386 386gat nand 6 4 >sa0 >sa1
250 338 373 33
387 386f01 from 386gat >sa1
388 386f02 from 386gat >sa1
389 386f03 from 386gat >sa1
390 386f04 from 386gat >sa1
391 386f05 from 386gat >sa1
392 386f06 from 386gat >sa1
393 393gat nand 5 4 >sa0 >sa1
254 340 374 46
394 393f01 from 393gat >sa1
395 393f02 from 393gat
396 393f03 from 393gat >sa1
397 393f04 from 393gat >sa1
398 393f05 from 393gat >sa1
399 399gat nand 4 4 >sa0 >sa1
255 342 375 59
400 399f01 from 399gat >sa1
401 399f02 from 399gat >sa1
402 399f03 from 399gat >sa1
403 399f04 from 399gat >sa1
404 404gat nand 2 4 >sa0 >sa1
256 344 376 72
405 404f01 from 404gat >sa1
406 404f02 from 404gat
407 407gat nand 3 4 >sa0 >sa1
257 345 377 85
408 407f01 from 407gat >sa1
409 407f02 from 407gat
410 407f03 from 407gat >sa1
411 411gat nand 2 4 >sa0 >sa1
258 346 378 98
412 411f01 from 411gat >sa1
413 411f02 from 411gat
414 414gat nand 1 4 >sa1
259 347 379 111
415 415gat not 1 1 >sa0
380
416 416gat and 1 8 >sa0
382 387 394 400 405 408 412 414
417 417gat not 1 1 >sa1
395
418 418gat not 1 1 >sa1
406
419 419gat not 1 1 >sa1
409
420 420gat not 1 1 >sa1
413
421 421gat nor 0 2 >sa0 >sa1
415 416
422 422gat nand 2 2 >sa0 >sa1
388 417
423 422f01 from 422gat >sa1
424 422f02 from 422gat >sa1
425 425gat nand 2 4 >sa0 >sa1
389 396 418 401
426 425f01 from 425gat >sa1
427 425f02 from 425gat >sa1
428 428gat nand 1 3 >sa1
402 397 419
429 429gat nand 1 4 >sa1
391 398 410 420
430 430gat nand 0 4 >sa0 >sa1
383 390 423 403
431 431gat nand 0 4 >sa0 >sa1
384 392 426 428
432 432gat nand 0 4 >sa0 >sa1
385 424 427 429
|
Added c432.tests.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 | 111111111011111111011111111011111111 111111111101111111101111111101111111 111111111110111111110111111110111111 111111111111011111111011111111011111 111111111111101111111101111111101111 111111111111110111111110111111110111 111111111111111011111111011111111011 111111111111111101111111101111111101 111111111111111110111111110111111110 111111111111111111010011111101111111 111111111111111111101111111010000000 111111111111111111110110101111111111 111111111111111111111010111111111111 111111111111111111111100111111111111 111111111111111111111110111111111111 111111111111111111111111011111111111 111111111111111111111111101111111111 111111111111111111111111110111111111 111111111111111111111111111011111111 111111111111111111111111111101111111 111111111111111111111111111110111111 111111111111111111111111111111011111 111111111111111111111111111111101111 111111111111111111111111111111110111 111111111111111111111111111111111011 100000010100000010100000010100000000 011111101011111101011111101011111100 111111111111011011000100100000100100 111111111111101001111111111111111111 111111111011111111100000000100000000 111111111001111111111111111001111111 000000000000000000000000000000000000 |
Added c432.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 |
/****************************************************************************
* *
* VERILOG HIGH-LEVEL DESCRIPTION OF THE ISCAS-85 BENCHMARK CIRCUIT c432 *
* *
* Function: 27-channel interrupt controller *
* *
* Written by: Mark C. Hansen *
* *
* Last modified: Oct 17, 1997 *
* *
****************************************************************************/
module Circuit432 (in4, in17, in30, in43, in56, in69, in82, in95, in108,
in1, in11, in24, in37, in50, in63, in76, in89, in102,
in8, in21, in34, in47, in60, in73, in86, in99, in112,
in14, in27, in40, in53, in66, in79, in92, in105, in115,
out223, out329, out370,
out421, out430, out431, out432);
input in4, in17, in30, in43, in56, in69, in82, in95, in108,
in1, in11, in24, in37, in50, in63, in76, in89, in102,
in8, in21, in34, in47, in60, in73, in86, in99, in112,
in14, in27, in40, in53, in66, in79, in92, in105, in115;
output out223, out329, out370,
out421, out430, out431, out432;
wire [8:0] A, B, C, E;
wire PA, PB, PC;
wire [3:0] Chan;
assign
E[8:0] = { in4, in17, in30, in43, in56, in69, in82, in95, in108 },
A[8:0] = { in1, in11, in24, in37, in50, in63, in76, in89, in102 },
B[8:0] = { in8, in21, in34, in47, in60, in73, in86, in99, in112 },
C[8:0] = { in14, in27, in40, in53, in66, in79, in92, in105, in115 },
PA = out223,
PB = out329,
PC = out370,
Chan[3:0] = { out421, out430, out431, out432 };
TopLevel432 Ckt432 (E, A, B, C, PA, PB, PC, Chan);
endmodule /* Circuit432 */
/*************************************************************************/
module TopLevel432 (E, A, B, C, PA, PB, PC, Chan);
input[8:0] E, A, B, C;
output PA, PB, PC;
output[3:0] Chan;
wire[8:0] X1, X2, I;
PriorityA M1(E, A, PA, X1);
PriorityB M2(E, X1, B, PB, X2);
PriorityC M3(E, X1, X2, C, PC);
EncodeChan M4(E, A, B, C, PA, PB, PC, I);
DecodeChan M5(I, Chan);
endmodule /* TopLevel432 */
/*************************************************************************/
module PriorityA(E, A, PA, X1);
input[8:0] E, A;
output PA;
output[8:0] X1;
wire [8:0] Ab, EAb;
not Ab0(Ab[0], A[0]);
not Ab1(Ab[1], A[1]);
not Ab2(Ab[2], A[2]);
not Ab3(Ab[3], A[3]);
not Ab4(Ab[4], A[4]);
not Ab5(Ab[5], A[5]);
not Ab6(Ab[6], A[6]);
not Ab7(Ab[7], A[7]);
not Ab8(Ab[8], A[8]);
nand EAb0(EAb[0], Ab[0], E[0]);
nand EAb1(EAb[1], Ab[1], E[1]);
nand EAb2(EAb[2], Ab[2], E[2]);
nand EAb3(EAb[3], Ab[3], E[3]);
nand EAb4(EAb[4], Ab[4], E[4]);
nand EAb5(EAb[5], Ab[5], E[5]);
nand EAb6(EAb[6], Ab[6], E[6]);
nand EAb7(EAb[7], Ab[7], E[7]);
nand EAb8(EAb[8], Ab[8], E[8]);
and PAigate(PAi,EAb[0],EAb[1],EAb[2],EAb[3],EAb[4],EAb[5],EAb[6],EAb[7]);
nand PAgate(PA,PAi,EAb[8]);
xor X10(X1[0], PA, EAb[0]);
xor X11(X1[1], PA, EAb[1]);
xor X12(X1[2], PA, EAb[2]);
xor X13(X1[3], PA, EAb[3]);
xor X14(X1[4], PA, EAb[4]);
xor X15(X1[5], PA, EAb[5]);
xor X16(X1[6], PA, EAb[6]);
xor X17(X1[7], PA, EAb[7]);
xor X18(X1[8], PA, EAb[8]);
endmodule /* PriorityA */
/*************************************************************************/
module PriorityB(E, X1, B, PB, X2);
input[8:0] E, X1, B;
output PB;
output[8:0] X2;
wire [8:0] Eb, EbB, XEB;
not Eb0(Eb[0], E[0]);
not Eb1(Eb[1], E[1]);
not Eb2(Eb[2], E[2]);
not Eb3(Eb[3], E[3]);
not Eb4(Eb[4], E[4]);
not Eb5(Eb[5], E[5]);
not Eb6(Eb[6], E[6]);
not Eb7(Eb[7], E[7]);
not Eb8(Eb[8], E[8]);
nor EbB0(EbB[0], Eb[0], B[0]);
nor EbB1(EbB[1], Eb[1], B[1]);
nor EbB2(EbB[2], Eb[2], B[2]);
nor EbB3(EbB[3], Eb[3], B[3]);
nor EbB4(EbB[4], Eb[4], B[4]);
nor EbB5(EbB[5], Eb[5], B[5]);
nor EbB6(EbB[6], Eb[6], B[6]);
nor EbB7(EbB[7], Eb[7], B[7]);
nor EbB8(EbB[8], Eb[8], B[8]);
nand XEB0(XEB[0], EbB[0], X1[0]);
nand XEB1(XEB[1], EbB[1], X1[1]);
nand XEB2(XEB[2], EbB[2], X1[2]);
nand XEB3(XEB[3], EbB[3], X1[3]);
nand XEB4(XEB[4], EbB[4], X1[4]);
nand XEB5(XEB[5], EbB[5], X1[5]);
nand XEB6(XEB[6], EbB[6], X1[6]);
nand XEB7(XEB[7], EbB[7], X1[7]);
nand XEB8(XEB[8], EbB[8], X1[8]);
and PBigate(PBi,XEB[0],XEB[1],XEB[2],XEB[3],XEB[4],XEB[5],XEB[6],XEB[7]);
nand PBgate(PB,PBi,XEB[8]);
xor X20(X2[0], PB, XEB[0]);
xor X21(X2[1], PB, XEB[1]);
xor X22(X2[2], PB, XEB[2]);
xor X23(X2[3], PB, XEB[3]);
xor X24(X2[4], PB, XEB[4]);
xor X25(X2[5], PB, XEB[5]);
xor X26(X2[6], PB, XEB[6]);
xor X27(X2[7], PB, XEB[7]);
xor X28(X2[8], PB, XEB[8]);
endmodule /* PriorityB */
/*************************************************************************/
module PriorityC(E, X1, X2, C, PC);
input[8:0] E, X1, X2, C;
output PC;
wire [8:0] Eb, EbC, XEC;
not Eb0(Eb[0], E[0]);
not Eb1(Eb[1], E[1]);
not Eb2(Eb[2], E[2]);
not Eb3(Eb[3], E[3]);
not Eb4(Eb[4], E[4]);
not Eb5(Eb[5], E[5]);
not Eb6(Eb[6], E[6]);
not Eb7(Eb[7], E[7]);
not Eb8(Eb[8], E[8]);
nor EbC0(EbC[0], Eb[0], C[0]);
nor EbC1(EbC[1], Eb[1], C[1]);
nor EbC2(EbC[2], Eb[2], C[2]);
nor EbC3(EbC[3], Eb[3], C[3]);
nor EbC4(EbC[4], Eb[4], C[4]);
nor EbC5(EbC[5], Eb[5], C[5]);
nor EbC6(EbC[6], Eb[6], C[6]);
nor EbC7(EbC[7], Eb[7], C[7]);
nor EbC8(EbC[8], Eb[8], C[8]);
nand XEC0(XEC[0], EbC[0], X1[0], X2[0]);
nand XEC1(XEC[1], EbC[1], X1[1], X2[1]);
nand XEC2(XEC[2], EbC[2], X1[2], X2[2]);
nand XEC3(XEC[3], EbC[3], X1[3], X2[3]);
nand XEC4(XEC[4], EbC[4], X1[4], X2[4]);
nand XEC5(XEC[5], EbC[5], X1[5], X2[5]);
nand XEC6(XEC[6], EbC[6], X1[6], X2[6]);
nand XEC7(XEC[7], EbC[7], X1[7], X2[7]);
nand XEC8(XEC[8], EbC[8], X1[8], X2[8]);
and PCigate(PCi, XEC[0],XEC[1],XEC[2],XEC[3],XEC[4],XEC[5],XEC[6],XEC[7]);
nand PCgate(PC, PCi, XEC[8]);
endmodule /*PriorityC */
/*************************************************************************/
module EncodeChan(E, A, B, C, PA, PB, PC, I);
input[8:0] E, A, B, C;
input PA, PB, PC;
output[8:0] I;
wire [8:0] APA, BPB, CPC;
nand APA0(APA[0], A[0], PA);
nand APA1(APA[1], A[1], PA);
nand APA2(APA[2], A[2], PA);
nand APA3(APA[3], A[3], PA);
nand APA4(APA[4], A[4], PA);
nand APA5(APA[5], A[5], PA);
nand APA6(APA[6], A[6], PA);
nand APA7(APA[7], A[7], PA);
nand APA8(APA[8], A[8], PA);
nand BPB0(BPB[0], B[0], PB);
nand BPB1(BPB[1], B[1], PB);
nand BPB2(BPB[2], B[2], PB);
nand BPB3(BPB[3], B[3], PB);
nand BPB4(BPB[4], B[4], PB);
nand BPB5(BPB[5], B[5], PB);
nand BPB6(BPB[6], B[6], PB);
nand BPB7(BPB[7], B[7], PB);
nand BPB8(BPB[8], B[8], PB);
nand CPC0(CPC[0], C[0], PC);
nand CPC1(CPC[1], C[1], PC);
nand CPC2(CPC[2], C[2], PC);
nand CPC3(CPC[3], C[3], PC);
nand CPC4(CPC[4], C[4], PC);
nand CPC5(CPC[5], C[5], PC);
nand CPC6(CPC[6], C[6], PC);
nand CPC7(CPC[7], C[7], PC);
nand CPC8(CPC[8], C[8], PC);
nand I0(I[0], E[0], APA[0], BPB[0], CPC[0]);
nand I1(I[1], E[1], APA[1], BPB[1], CPC[1]);
nand I2(I[2], E[2], APA[2], BPB[2], CPC[2]);
nand I3(I[3], E[3], APA[3], BPB[3], CPC[3]);
nand I4(I[4], E[4], APA[4], BPB[4], CPC[4]);
nand I5(I[5], E[5], APA[5], BPB[5], CPC[5]);
nand I6(I[6], E[6], APA[6], BPB[6], CPC[6]);
nand I7(I[7], E[7], APA[7], BPB[7], CPC[7]);
nand I8(I[8], E[8], APA[8], BPB[8], CPC[8]);
endmodule /* EncodeChan */
/*************************************************************************/
module DecodeChan(I, Chan);
input[8:0] I;
output[3:0] Chan;
wire Iand, Ib8, Ib1, Ib2, Ib3, Ib5, I56, I245, I3456, I1256;
and Iandgate(Iand, I[0], I[1], I[2], I[3], I[4], I[5], I[6], I[7]);
not Ib8gate(Ib8, I[8]);
nor Chan3(Chan[3], Iand, Ib8);
not Ib1gate(Ib1, I[1]);
not Ib2gate(Ib2, I[2]);
not Ib3gate(Ib3, I[3]);
not Ib5gate(Ib5, I[5]);
nand I56gate(I56, Ib5, I[6]);
nand I245gate(I245, Ib2, I[4], I[5]);
nand I3456gate(I3456, Ib3, I[4], I[5], I[6]);
nand I1256gate(I1256, Ib1, I[2], I[5], I[6]);
nand Chan2(Chan[2], I[4], I[6], I[7], I56);
nand Chan1(Chan[1], I[6], I[7], I245, I3456);
nand Chan0(Chan[0], I[7], I56, I1256, I3456);
endmodule /* DecodeChan */
|
Added c432b.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 |
/****************************************************************************
* *
* VERILOG BEHAVIORAL DESCRIPTION OF THE ISCAS-85 BENCHMARK CIRCUIT c432 *
* *
* Function: 27-channel interrupt controller *
* *
* Written by: Mark C. Hansen *
* *
* Last modified: Oct 17, 1997 *
* *
****************************************************************************/
module Circuit432 (in4, in17, in30, in43, in56, in69, in82, in95, in108,
in1, in11, in24, in37, in50, in63, in76, in89, in102,
in8, in21, in34, in47, in60, in73, in86, in99, in112,
in14, in27, in40, in53, in66, in79, in92, in105, in115,
out223, out329, out370,
out421, out430, out431, out432);
input in4, in17, in30, in43, in56, in69, in82, in95, in108,
in1, in11, in24, in37, in50, in63, in76, in89, in102,
in8, in21, in34, in47, in60, in73, in86, in99, in112,
in14, in27, in40, in53, in66, in79, in92, in105, in115;
output out223, out329, out370,
out421, out430, out431, out432;
wire [8:0] A, B, C, E;
wire PA, PB, PC;
wire [3:0] Chan;
assign
E[8:0] = { in4, in17, in30, in43, in56, in69, in82, in95, in108 },
A[8:0] = { in1, in11, in24, in37, in50, in63, in76, in89, in102 },
B[8:0] = { in8, in21, in34, in47, in60, in73, in86, in99, in112 },
C[8:0] = { in14, in27, in40, in53, in66, in79, in92, in105, in115 },
PA = out223,
PB = out329,
PC = out370,
Chan[3:0] = { out421, out430, out431, out432 };
TopLevel432b Ckt432 (E, A, B, C, PA, PB, PC, Chan);
endmodule /* Circuit432 */
/*************************************************************************/
module TopLevel432b (E, A, B, C, PA, PB, PC, Chan);
input[8:0] E, A, B, C;
output PA, PB, PC;
output[3:0] Chan;
wire[8:0] X1, X2, I;
PriorityA M1(E, A, PA, X1);
PriorityB M2(E, X1, B, PB, X2);
PriorityC M3(E, X1, X2, C, PC);
EncodeChan M4(E, A, B, C, PA, PB, PC, I);
DecodeChan M5(I, Chan);
endmodule /* TopLevel432b */
/*************************************************************************/
module PriorityA(E, A, PA, X1);
input[8:0] E, A;
output PA;
output[8:0] X1;
wire [8:0] Ab, EAb;
assign Ab = ~A;
assign EAb = ~(Ab & E);
assign PA = ~&EAb;
assign X1 = EAb ^ {9{PA}};
endmodule /* PriorityA */
/*************************************************************************/
module PriorityB(E, X1, B, PB, X2);
input[8:0] E, X1, B;
output PB;
output[8:0] X2;
wire [8:0] Eb, EbB, XEB;
assign Eb = ~E;
assign EbB = ~(Eb | B);
assign XEB = ~(X1 & EbB);
assign PB = ~&XEB;
assign X2 = XEB ^ {9{PB}};
endmodule /* PriorityB */
/*************************************************************************/
module PriorityC(E, X1, X2, C, PC);
input[8:0] E, X1, X2, C;
output PC;
wire [8:0] Eb, EbC, XEC;
assign Eb = ~E;
assign EbC = ~(Eb | C);
assign XEC = ~(X1 & X2 & EbC);
assign PC = ~&XEC;
endmodule /*PriorityC */
/*************************************************************************/
module EncodeChan(E, A, B, C, PA, PB, PC, I);
input[8:0] E, A, B, C;
input PA, PB, PC;
output[8:0] I;
wire [8:0] APA, BPB, CPC;
assign APA = ~(A & {9{PA}});
assign BPB = ~(B & {9{PB}});
assign CPC = ~(C & {9{PC}});
assign I = ~(E & APA & BPB & CPC);
endmodule /* EncodeChan */
/*************************************************************************/
module DecodeChan(I, Chan);
input[8:0] I;
output[3:0] Chan;
wire Iand, I8b, I1b, I2b, I3b, I5b, I56, I245, I3456, I1256;
assign I8b = ~I[8];
assign Iand = &I[7:0];
assign Chan[3] = ~(I8b | Iand);
assign I1b = ~I[1];
assign I2b = ~I[2];
assign I3b = ~I[3];
assign I5b = ~I[5];
assign I56 = ~(I5b & I[6]);
assign I245 = ~(I2b & I[4] & I[5]);
assign I3456 = ~(I3b & I[4] & I[5] & I[6]);
assign I1256 = ~(I1b & I[2] & I[5] & I[6]);
assign Chan[2] = ~(I[4] & I[6] & I[7] & I56);
assign Chan[1] = ~(I[6] & I[7] & I245 & I3456);
assign Chan[0] = ~(I[7] & I56 & I1256 & I3456);
endmodule /* DecodeChan */
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Added c432bus.html.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c432bus</TITLE> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C432 27-channel interrupt controller</P> <P ALIGN="CENTER">Bus Translations</P> </FONT><FONT SIZE=4><P ALIGN="CENTER"> </P></B></FONT> <TABLE BORDER CELLSPACING=2 BORDERCOLOR="#000000" CELLPADDING=9 WIDTH=679> <TR><TD WIDTH="16%" VALIGN="TOP" HEIGHT=17> <B><P ALIGN="CENTER">I/O Bus</B></TD> <TD WIDTH="43%" VALIGN="TOP" HEIGHT=17> <B><P ALIGN="CENTER">Function</B></TD> <TD WIDTH="41%" VALIGN="TOP" HEIGHT=17> <B><P ALIGN="CENTER">ISCAS-85 Netlist numbers</B></TD> </TR> <TR><TD WIDTH="16%" VALIGN="TOP" HEIGHT=17> <B><FONT SIZE=2><P ALIGN="CENTER">A[8:0]</B></FONT></TD> <TD WIDTH="43%" VALIGN="TOP" HEIGHT=17> <B><FONT FACE="Times" SIZE=2><P ALIGN="CENTER">Highest priority input bus</B></FONT></TD> <TD WIDTH="41%" VALIGN="TOP" HEIGHT=17> <B><FONT FACE="Times" SIZE=2><P ALIGN="CENTER">1, 11, 24, 37, 50, 63, 76, 89, 102</B></FONT></TD> </TR> <TR><TD WIDTH="16%" VALIGN="TOP" HEIGHT=25> <B><FONT SIZE=2><P ALIGN="CENTER">B[8:0]</B></FONT></TD> <TD WIDTH="43%" VALIGN="TOP" HEIGHT=25> <B><FONT FACE="Times" SIZE=2><P ALIGN="CENTER">Middle priority input bus</B></FONT></TD> <TD WIDTH="41%" VALIGN="TOP" HEIGHT=25> <B><FONT FACE="Times" SIZE=2><P ALIGN="CENTER">8, 21, 34, 47, 60, 73, 86, 99, 112</B></FONT></TD> </TR> <TR><TD WIDTH="16%" VALIGN="TOP" HEIGHT=19> <B><FONT SIZE=2><P ALIGN="CENTER">C[8:0]</B></FONT></TD> <TD WIDTH="43%" VALIGN="TOP" HEIGHT=19> <B><FONT FACE="Times" SIZE=2><P ALIGN="CENTER">Lowest priority input bus</B></FONT></TD> <TD WIDTH="41%" VALIGN="TOP" HEIGHT=19> <B><FONT FACE="Times" SIZE=2><P ALIGN="CENTER">14, 27, 40, 53, 66, 79, 92, 105, 115</B></FONT></TD> </TR> <TR><TD WIDTH="16%" VALIGN="TOP" HEIGHT=26> <B><FONT SIZE=2><P ALIGN="CENTER">E[8:0]</B></FONT></TD> <TD WIDTH="43%" VALIGN="TOP" HEIGHT=26> <B><FONT FACE="Times" SIZE=2><P ALIGN="CENTER">Channel enable input bus</B></FONT></TD> <TD WIDTH="41%" VALIGN="TOP" HEIGHT=26> <B><FONT FACE="Times" SIZE=2><P ALIGN="CENTER">4, 17, 30, 43, 56, 69, 82, 95, 108</B></FONT></TD> </TR> <TR><TD WIDTH="16%" VALIGN="TOP" HEIGHT=20> <B><FONT SIZE=2><P ALIGN="CENTER">PA,PB,PC</B></FONT></TD> <TD WIDTH="43%" VALIGN="TOP" HEIGHT=20> <B><FONT FACE="Times" SIZE=2><P ALIGN="CENTER">Requesting bus output</B></FONT></TD> <TD WIDTH="41%" VALIGN="TOP" HEIGHT=20> <B><FONT FACE="Times" SIZE=2><P ALIGN="CENTER">223, 329, 370</B></FONT></TD> </TR> <TR><TD WIDTH="16%" VALIGN="TOP" HEIGHT=22> <B><FONT SIZE=2><P ALIGN="CENTER">Chan[3:0]</B></FONT></TD> <TD WIDTH="43%" VALIGN="TOP" HEIGHT=22> <B><FONT FACE="Times" SIZE=2><P ALIGN="CENTER">Requesting channel output</B></FONT></TD> <TD WIDTH="41%" VALIGN="TOP" HEIGHT=22> <B><FONT FACE="Times" SIZE=2><P ALIGN="CENTER">421, 430, 431, 432</B></FONT></TD> </TR> </TABLE> <FONT SIZE=2><P ALIGN="CENTER"> </P></FONT></BODY> </HTML> |
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> > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c432m1</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY TEXT="#000000" LINK="#0000ff" VLINK="#800080" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C432 Module M1</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="c432m1.gif" WIDTH=469 HEIGHT=172> </P></BODY> </HTML> |
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> > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c432m2</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY TEXT="#000000" LINK="#0000ff" VLINK="#800080" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C432 Module M2</P> </B></FONT><P ALIGN="CENTER"> <IMG SRC="c432m2.gif" WIDTH=469 HEIGHT=154></P></BODY> </HTML> |
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> > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c432m3</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY TEXT="#000000" LINK="#0000ff" VLINK="#800080" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C432 Module M3</P> </B></FONT><P ALIGN="CENTER"> <IMG SRC="c432m3.gif" WIDTH=469 HEIGHT=181></P></BODY> </HTML> |
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> > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c432m4</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY TEXT="#000000" LINK="#0000ff" VLINK="#800080" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C432 Module M4</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="c432m4.gif" WIDTH=469 HEIGHT=244> </P></BODY> </HTML> |
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> > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c432m5</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY TEXT="#000000" LINK="#0000ff" VLINK="#800080" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C432 Module M5</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="c432m5.gif" WIDTH=469 HEIGHT=397></P> <P ALIGN="CENTER"> </P></BODY> </HTML> |
Added c432m5tt.html.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c432m5tt</TITLE> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080"> <B><FONT SIZE=4><P ALIGN="CENTER">ISCAS-85 C432 27-channel interrupt controller</P> <P ALIGN="CENTER">Module M5 input/output truth table</P> <P ALIGN="CENTER"> </P></B></FONT> <TABLE BORDER CELLSPACING=2 BORDERCOLOR="#000000" CELLPADDING=9 WIDTH=810> <TR><TD WIDTH="26%" VALIGN="TOP" HEIGHT=17> <P ALIGN="CENTER"><B>Requesting channel number</B></TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P ALIGN="CENTER">none</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P ALIGN="CENTER">8</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P ALIGN="CENTER">7</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P ALIGN="CENTER">6</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P ALIGN="CENTER">5</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P ALIGN="CENTER">4</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P ALIGN="CENTER">3</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P ALIGN="CENTER">2</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P ALIGN="CENTER">1</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P ALIGN="CENTER">0</TD> </TR> <TR><TD WIDTH="26%" VALIGN="TOP" HEIGHT=17> <B><P ALIGN="CENTER">Requesting channel output</B></TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P>1111</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P>1000</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P>0111</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P>0110</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P>0101</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P>0100</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P>0011</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P>0010</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P>0001</TD> <TD WIDTH="7%" VALIGN="TOP" HEIGHT=17> <P>0000</TD> </TR> </TABLE> <FONT SIZE=2><P> </P></FONT></BODY> </HTML> |
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> > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c499</TITLE> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C499/C1355 32-Bit Single-Error-Correcting Circuit</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="c499.gif" WIDTH=433 HEIGHT=186></P> <B><P>Statistics: </B>41 inputs; 32 outputs; 202/546 gates; <A HREF="c499bus.html">bus translations</A></P> <B><P>Function: </B>c499 was found to be a single-error-correcting circuit as shown above. The 41 inputs are combined to form an 8-bit internal bus S, which then combines with 32 primary inputs to form the 32 primary outputs. The <A HREF="c499sequ.html">boolean expressions defining S</A> form the <A HREF="c499hmatrix.html">H matrix for a (40,32) Hamming code </A>[See C. L. Chen and M. Y. Hsiao. Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review. IBM Journal of Research & Development, vol. 28, pp. 124-134, March 1984]. If H_ij (the element in row i and column j) is 1, then ID_j (or IC_j-32 if j > 31) is used in S_i . Module M2 contains the necessary correcting logic, so c499 can correct single-bit errors; however, no error-detection logic is present. The S lines are formulated to generate a unique syndrome for each input line in error. The syndromes are the column vectors of H. If syndrome i is seen, output OD_i is inverted. This is specified by the <A HREF="c499oequ.html">32 output equations</A> realized by M2.</P> <P>The c1355 circuit has the same overall function as c499; it differs in that all XOR primitives of c499 are expanded to their four-NAND-gate equivalents.</P> <FONT SIZE=2><P> </FONT><B>Models:</P> <UL> </B><LI><A HREF="c499.isc">c499 ISCAS-85 netlist</A><B> </LI> </B><LI><A HREF="c499.v">c499 Verilog hierarchical structural model</A><B> </LI> </B><LI><A HREF="c499b.v">c499/1355 Verilog hierarchical behavioral model</A> </LI> <LI><A HREF="c499.tests">c499 complete gate-level tests</A> </LI> <LI><A HREF="c1355.isc">c1355 ISCAS-85 netlist</A><B> </LI> </B><LI><A HREF="c1355.v">c1355 Verilog hierarchical structural model</A><B> </LI> </B><LI><A HREF="c1355.tests">c1355 complete gate-level tests</A></LI></UL> <FONT SIZE=2><P> </P></FONT></BODY> </HTML> |
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* combinational logic example "c499"
*-------------------------------------------------------------
*
*
* total number of lines in the netlist .............. 499
* simplistically reduced equivalent fault set size = 758
* lines from primary input gates ....... 41
* lines from primary output gates ....... 32
* lines from interior gate outputs ...... 170
* lines from ** 59 ** fanout stems ... 256
*
* avg_fanin = 2.02, max_fanin = 5
* avg_fanout = 4.34, max_fanout = 12
*
*
*
*
*
1 id0 inpt 3 0 >sa0 >sa1
146 d0a from id0 >sa0 >sa1
147 d0b from id0 >sa0 >sa1
148 d0c from id0 >sa0 >sa1
5 id1 inpt 3 0 >sa0 >sa1
149 d1a from id1 >sa0 >sa1
150 d1b from id1 >sa0 >sa1
151 d1c from id1 >sa0 >sa1
9 id2 inpt 3 0 >sa0 >sa1
152 d2a from id2 >sa0 >sa1
153 d2b from id2 >sa0 >sa1
154 d2c from id2 >sa0 >sa1
13 id3 inpt 3 0 >sa0 >sa1
155 d3a from id3 >sa0 >sa1
156 d3b from id3 >sa0 >sa1
157 d3c from id3 >sa0 >sa1
17 id4 inpt 3 0 >sa0 >sa1
158 d4a from id4 >sa0 >sa1
159 d4b from id4 >sa0 >sa1
160 d4c from id4 >sa0 >sa1
21 id5 inpt 3 0 >sa0 >sa1
161 d5a from id5 >sa0 >sa1
162 d5b from id5 >sa0 >sa1
163 d5c from id5 >sa0 >sa1
25 id6 inpt 3 0 >sa0 >sa1
164 d6a from id6 >sa0 >sa1
165 d6b from id6 >sa0 >sa1
166 d6c from id6 >sa0 >sa1
29 id7 inpt 3 0 >sa0 >sa1
167 d7a from id7 >sa0 >sa1
168 d7b from id7 >sa0 >sa1
169 d7c from id7 >sa0 >sa1
33 id8 inpt 3 0 >sa0 >sa1
170 d8a from id8 >sa0 >sa1
171 d8b from id8 >sa0 >sa1
172 d8c from id8 >sa0 >sa1
37 id9 inpt 3 0 >sa0 >sa1
173 d9a from id9 >sa0 >sa1
174 d9b from id9 >sa0 >sa1
175 d9c from id9 >sa0 >sa1
41 id10 inpt 3 0 >sa0 >sa1
176 d10a from id10 >sa0 >sa1
177 d10b from id10 >sa0 >sa1
178 d10c from id10 >sa0 >sa1
45 id11 inpt 3 0 >sa0 >sa1
179 d11a from id11 >sa0 >sa1
180 d11b from id11 >sa0 >sa1
181 d11c from id11 >sa0 >sa1
49 id12 inpt 3 0 >sa0 >sa1
182 d12a from id12 >sa0 >sa1
183 d12b from id12 >sa0 >sa1
184 d12c from id12 >sa0 >sa1
53 id13 inpt 3 0 >sa0 >sa1
185 d13a from id13 >sa0 >sa1
186 d13b from id13 >sa0 >sa1
187 d13c from id13 >sa0 >sa1
57 id14 inpt 3 0 >sa0 >sa1
188 d14a from id14 >sa0 >sa1
189 d14b from id14 >sa0 >sa1
190 d14c from id14 >sa0 >sa1
61 id15 inpt 3 0 >sa0 >sa1
191 d15a from id15 >sa0 >sa1
192 d15b from id15 >sa0 >sa1
193 d15c from id15 >sa0 >sa1
65 id16 inpt 3 0 >sa0 >sa1
194 d16a from id16 >sa0 >sa1
195 d16b from id16 >sa0 >sa1
196 d16c from id16 >sa0 >sa1
69 id17 inpt 3 0 >sa0 >sa1
197 d17a from id17 >sa0 >sa1
198 d17b from id17 >sa0 >sa1
199 d17c from id17 >sa0 >sa1
73 id18 inpt 3 0 >sa0 >sa1
200 d18a from id18 >sa0 >sa1
201 d18b from id18 >sa0 >sa1
202 d18c from id18 >sa0 >sa1
77 id19 inpt 3 0 >sa0 >sa1
203 d19a from id19 >sa0 >sa1
204 d19b from id19 >sa0 >sa1
205 d19c from id19 >sa0 >sa1
81 id20 inpt 3 0 >sa0 >sa1
206 d20a from id20 >sa0 >sa1
207 d20b from id20 >sa0 >sa1
208 d20c from id20 >sa0 >sa1
85 id21 inpt 3 0 >sa0 >sa1
209 d21a from id21 >sa0 >sa1
210 d21b from id21 >sa0 >sa1
211 d21c from id21 >sa0 >sa1
89 id22 inpt 3 0 >sa0 >sa1
212 d22a from id22 >sa0 >sa1
213 d22b from id22 >sa0 >sa1
214 d22c from id22 >sa0 >sa1
93 id23 inpt 3 0 >sa0 >sa1
215 d23a from id23 >sa0 >sa1
216 d23b from id23 >sa0 >sa1
217 d23c from id23 >sa0 >sa1
97 id24 inpt 3 0 >sa0 >sa1
218 d24a from id24 >sa0 >sa1
219 d24b from id24 >sa0 >sa1
220 d24c from id24 >sa0 >sa1
101 id25 inpt 3 0 >sa0 >sa1
221 d25a from id25 >sa0 >sa1
222 d25b from id25 >sa0 >sa1
223 d25c from id25 >sa0 >sa1
105 id26 inpt 3 0 >sa0 >sa1
224 d26a from id26 >sa0 >sa1
225 d26b from id26 >sa0 >sa1
226 d26c from id26 >sa0 >sa1
109 id27 inpt 3 0 >sa0 >sa1
227 d27a from id27 >sa0 >sa1
228 d27b from id27 >sa0 >sa1
229 d27c from id27 >sa0 >sa1
113 id28 inpt 3 0 >sa0 >sa1
230 d28a from id28 >sa0 >sa1
231 d28b from id28 >sa0 >sa1
232 d28c from id28 >sa0 >sa1
117 id29 inpt 3 0 >sa0 >sa1
233 d29a from id29 >sa0 >sa1
234 d29b from id29 >sa0 >sa1
235 d29c from id29 >sa0 >sa1
121 id30 inpt 3 0 >sa0 >sa1
236 d30a from id30 >sa0 >sa1
237 d30b from id30 >sa0 >sa1
238 d30c from id30 >sa0 >sa1
125 id31 inpt 3 0 >sa0 >sa1
239 d31a from id31 >sa0 >sa1
240 d31b from id31 >sa0 >sa1
241 d31c from id31 >sa0 >sa1
129 ic0 inpt 1 0 >sa1
130 ic1 inpt 1 0 >sa1
131 ic2 inpt 1 0 >sa1
132 ic3 inpt 1 0 >sa1
133 ic4 inpt 1 0 >sa1
134 ic5 inpt 1 0 >sa1
135 ic6 inpt 1 0 >sa1
136 ic7 inpt 1 0 >sa1
137 r inpt 8 0 >sa0 >sa1
242 r0 from r >sa1
243 r1 from r >sa1
244 r2 from r >sa1
245 r3 from r >sa1
246 r4 from r >sa1
247 r5 from r >sa1
248 r6 from r >sa1
249 r7 from r >sa1
250 xa0 xor 1 2 >sa0 >sa1
146 149
251 xa1 xor 1 2 >sa0 >sa1
152 155
252 xa2 xor 1 2 >sa0 >sa1
158 161
253 xa3 xor 1 2 >sa0 >sa1
164 167
254 xa4 xor 1 2 >sa0 >sa1
170 173
255 xa5 xor 1 2 >sa0 >sa1
176 179
256 xa6 xor 1 2 >sa0 >sa1
182 185
257 xa7 xor 1 2 >sa0 >sa1
188 191
258 xa8 xor 1 2 >sa0 >sa1
194 197
259 xa9 xor 1 2 >sa0 >sa1
200 203
260 xa10 xor 1 2 >sa0 >sa1
206 209
261 xa11 xor 1 2 >sa0 >sa1
212 215
262 xa12 xor 1 2 >sa0 >sa1
218 221
263 xa13 xor 1 2 >sa0 >sa1
224 227
264 xa14 xor 1 2 >sa0 >sa1
230 233
265 xa15 xor 1 2 >sa0 >sa1
236 239
266 h0 and 1 2 >sa0 >sa1
129 242
267 h1 and 1 2 >sa0 >sa1
130 243
268 h2 and 1 2 >sa0 >sa1
131 244
269 h3 and 1 2 >sa0 >sa1
132 245
270 h4 and 1 2 >sa0 >sa1
133 246
271 h5 and 1 2 >sa0 >sa1
134 247
272 h6 and 1 2 >sa0 >sa1
135 248
273 h7 and 1 2 >sa0 >sa1
136 249
274 xb0 xor 1 2 >sa0 >sa1
147 159
275 xc0 xor 1 2 >sa0 >sa1
171 183
276 xb1 xor 1 2 >sa0 >sa1
150 162
277 xc1 xor 1 2 >sa0 >sa1
174 186
278 xb2 xor 1 2 >sa0 >sa1
153 165
279 xc2 xor 1 2 >sa0 >sa1
177 189
280 xb3 xor 1 2 >sa0 >sa1
156 168
281 xc3 xor 1 2 >sa0 >sa1
180 192
282 xb4 xor 1 2 >sa0 >sa1
195 207
283 xc4 xor 1 2 >sa0 >sa1
219 231
284 xb5 xor 1 2 >sa0 >sa1
198 210
285 xc5 xor 1 2 >sa0 >sa1
222 234
286 xb6 xor 1 2 >sa0 >sa1
201 213
287 xc6 xor 1 2 >sa0 >sa1
225 237
288 xb7 xor 1 2 >sa0 >sa1
204 216
289 xc7 xor 1 2 >sa0 >sa1
228 240
290 f0 xor 2 2 >sa0 >sa1
250 251
322 f0a from f0 >sa0 >sa1
323 f0b from f0 >sa0 >sa1
293 f1 xor 2 2 >sa0 >sa1
252 253
324 f1a from f1 >sa0 >sa1
325 f1b from f1 >sa0 >sa1
296 f2 xor 2 2 >sa0 >sa1
254 255
326 f2a from f2 >sa0 >sa1
327 f2b from f2 >sa0 >sa1
299 f3 xor 2 2 >sa0 >sa1
256 257
328 f3a from f3 >sa0 >sa1
329 f3b from f3 >sa0 >sa1
302 f4 xor 2 2 >sa0 >sa1
258 259
330 f4a from f4 >sa0 >sa1
331 f4b from f4 >sa0 >sa1
305 f5 xor 2 2 >sa0 >sa1
260 261
332 f5a from f5 >sa0 >sa1
333 f5b from f5 >sa0 >sa1
308 f6 xor 2 2 >sa0 >sa1
262 263
334 f6a from f6 >sa0 >sa1
335 f6b from f6 >sa0 >sa1
311 f7 xor 2 2 >sa0 >sa1
264 265
336 f7a from f7 >sa0 >sa1
337 f7b from f7 >sa0 >sa1
314 xe0 xor 1 2 >sa0 >sa1
274 275
315 xe1 xor 1 2 >sa0 >sa1
276 277
316 xe2 xor 1 2 >sa0 >sa1
278 279
317 xe3 xor 1 2 >sa0 >sa1
280 281
318 xe4 xor 1 2 >sa0 >sa1
282 283
319 xe5 xor 1 2 >sa0 >sa1
284 285
320 xe6 xor 1 2 >sa0 >sa1
286 287
321 xe7 xor 1 2 >sa0 >sa1
288 289
338 g0 xor 1 2 >sa0 >sa1
322 324
339 g1 xor 1 2 >sa0 >sa1
326 328
340 g2 xor 1 2 >sa0 >sa1
323 327
341 g3 xor 1 2 >sa0 >sa1
325 329
342 g4 xor 1 2 >sa0 >sa1
330 332
343 g5 xor 1 2 >sa0 >sa1
334 336
344 g6 xor 1 2 >sa0 >sa1
331 335
345 g7 xor 1 2 >sa0 >sa1
333 337
346 xd0 xor 1 2 >sa0 >sa1
266 342
347 xd1 xor 1 2 >sa0 >sa1
267 343
348 xd2 xor 1 2 >sa0 >sa1
268 344
349 xd3 xor 1 2 >sa0 >sa1
269 345
350 xd4 xor 1 2 >sa0 >sa1
270 338
351 xd5 xor 1 2 >sa0 >sa1
271 339
352 xd6 xor 1 2 >sa0 >sa1
272 340
353 xd7 xor 1 2 >sa0 >sa1
273 341
354 s0 xor 12 2 >sa0 >sa1
314 346
458 s0a from s0
459 s0b from s0
460 s0c from s0
461 s0d from s0 >sa1
462 s0e from s0 >sa1
463 s0f from s0 >sa1
464 s0g from s0 >sa1
465 s0h from s0 >sa1
466 s0i from s0 >sa1
467 s0j from s0 >sa1
468 s0k from s0
469 s0l from s0
367 s1 xor 12 2 >sa0 >sa1
315 347
470 s1a from s1
471 s1b from s1
472 s1c from s1 >sa1
473 s1d from s1
474 s1e from s1 >sa1
475 s1f from s1 >sa1
476 s1g from s1 >sa1
477 s1h from s1 >sa1
478 s1i from s1
479 s1j from s1
480 s1k from s1 >sa1
481 s1l from s1 >sa1
380 s2 xor 12 2 >sa0 >sa1
316 348
482 s2a from s2
483 s2b from s2 >sa1
484 s2c from s2
485 s2d from s2
486 s2e from s2 >sa1
487 s2f from s2 >sa1
488 s2g from s2 >sa1
489 s2h from s2 >sa1
490 s2i from s2 >sa1
491 s2j from s2
492 s2k from s2 >sa1
493 s2l from s2
393 s3 xor 12 2 >sa0 >sa1
317 349
494 s3a from s3 >sa1
495 s3b from s3
496 s3c from s3
497 s3d from s3
498 s3e from s3 >sa1
499 s3f from s3 >sa1
500 s3g from s3 >sa1
501 s3h from s3 >sa1
502 s3i from s3
503 s3j from s3 >sa1
504 s3k from s3
505 s3l from s3 >sa1
406 s4 xor 12 2 >sa0 >sa1
318 350
506 s4a from s4
507 s4b from s4
508 s4c from s4
509 s4d from s4 >sa1
510 s4e from s4 >sa1
511 s4f from s4 >sa1
512 s4g from s4 >sa1
513 s4h from s4 >sa1
514 s4i from s4 >sa1
515 s4j from s4 >sa1
516 s4k from s4
517 s4l from s4
419 s5 xor 12 2 >sa0 >sa1
319 351
518 s5a from s5
519 s5b from s5
520 s5c from s5 >sa1
521 s5d from s5
522 s5e from s5 >sa1
523 s5f from s5 >sa1
524 s5g from s5 >sa1
525 s5h from s5 >sa1
526 s5i from s5
527 s5j from s5
528 s5k from s5 >sa1
529 s5l from s5 >sa1
432 s6 xor 12 2 >sa0 >sa1
320 352
530 s6a from s6
531 s6b from s6 >sa1
532 s6c from s6
533 s6d from s6
534 s6e from s6 >sa1
535 s6f from s6 >sa1
536 s6g from s6 >sa1
537 s6h from s6 >sa1
538 s6i from s6 >sa1
539 s6j from s6
540 s6k from s6 >sa1
541 s6l from s6
445 s7 xor 12 2 >sa0 >sa1
321 353
542 s7a from s7 >sa1
543 s7b from s7
544 s7c from s7
545 s7d from s7
546 s7e from s7 >sa1
547 s7f from s7 >sa1
548 s7g from s7 >sa1
549 s7h from s7 >sa1
550 s7i from s7
551 s7j from s7 >sa1
552 s7k from s7
553 s7l from s7 >sa1
554 y0a not 1 1 >sa1
458
555 y1a not 1 1 >sa1
470
556 y2a not 1 1 >sa1
482
557 y0b not 1 1 >sa1
459
558 y1b not 1 1 >sa1
471
559 y3b not 1 1 >sa1
495
560 y0c not 1 1 >sa1
460
561 y2c not 1 1 >sa1
484
562 y3c not 1 1 >sa1
496
563 y1d not 1 1 >sa1
473
564 y2d not 1 1 >sa1
485
565 y3d not 1 1 >sa1
497
566 y5i not 1 1 >sa1
526
567 y7i not 1 1 >sa1
550
568 y5j not 1 1 >sa1
527
569 y6j not 1 1 >sa1
539
570 y4k not 1 1 >sa1
516
571 y7k not 1 1 >sa1
552
572 y4l not 1 1 >sa1
517
573 y6l not 1 1 >sa1
541
574 y4a not 1 1 >sa1
506
575 y5a not 1 1 >sa1
518
576 y6a not 1 1 >sa1
530
577 y4b not 1 1 >sa1
507
578 y5b not 1 1 >sa1
519
579 y7b not 1 1 >sa1
543
580 y4c not 1 1 >sa1
508
581 y6c not 1 1 >sa1
532
582 y7c not 1 1 >sa1
544
583 y5d not 1 1 >sa1
521
584 y6d not 1 1 >sa1
533
585 y7d not 1 1 >sa1
545
586 y1i not 1 1 >sa1
478
587 y3i not 1 1 >sa1
502
588 y1j not 1 1 >sa1
479
589 y2j not 1 1 >sa1
491
590 y0k not 1 1 >sa1
468
591 y3k not 1 1 >sa1
504
592 y0l not 1 1 >sa1
469
593 y2l not 1 1 >sa1
493
594 t0 and 1 4 >sa0
554 555 556 494
595 t1 and 1 4 >sa0
557 558 483 559
596 t2 and 1 4 >sa0
560 472 561 562
597 t3 and 1 4 >sa0
461 563 564 565
598 t4 and 1 4 >sa0
574 575 576 542
599 t5 and 1 4 >sa0
577 578 531 579
600 t6 and 1 4 >sa0
580 520 581 582
601 t7 and 1 4 >sa0
509 583 584 585
602 u0 or 4 4 >sa0 >sa1
594 595 596 597
612 va from u0 >sa1
613 vb from u0 >sa1
614 vc from u0 >sa1
615 vd from u0 >sa1
607 u1 or 4 4 >sa0 >sa1
598 599 600 601
616 ve from u1 >sa1
617 vf from u1 >sa1
618 vg from u1 >sa1
619 vh from u1 >sa1
620 wa and 4 5 >sa0 >sa1
514 566 538 567 612
660 wa0 from wa >sa1
661 wa1 from wa >sa1
662 wa2 from wa >sa1
663 wa3 from wa >sa1
625 wb and 4 5 >sa0 >sa1
515 568 569 551 613
664 wb0 from wb >sa1
665 wb1 from wb >sa1
666 wb2 from wb >sa1
667 wb3 from wb >sa1
630 wc and 4 5 >sa0 >sa1
570 528 540 571 614
668 wc0 from wc >sa1
669 wc1 from wc >sa1
670 wc2 from wc >sa1
671 wc3 from wc >sa1
635 wd and 4 5 >sa0 >sa1
572 529 573 553 615
672 wd0 from wd >sa1
673 wd1 from wd >sa1
674 wd2 from wd >sa1
675 wd3 from wd >sa1
640 we and 4 5 >sa0 >sa1
466 586 490 587 616
676 we0 from we >sa1
677 we1 from we >sa1
678 we2 from we >sa1
679 we3 from we >sa1
645 wf and 4 5 >sa0 >sa1
467 588 589 503 617
680 wf0 from wf >sa1
681 wf1 from wf >sa1
682 wf2 from wf >sa1
683 wf3 from wf >sa1
650 wg and 4 5 >sa0 >sa1
590 480 492 591 618
684 wg0 from wg >sa1
685 wg1 from wg >sa1
686 wg2 from wg >sa1
687 wg3 from wg >sa1
655 wh and 4 5 >sa0 >sa1
592 481 593 505 619
688 wh0 from wh >sa1
689 wh1 from wh >sa1
690 wh2 from wh >sa1
691 wh3 from wh >sa1
692 e0 and 1 2 >sa0 >sa1
462 660
693 e1 and 1 2 >sa0 >sa1
474 661
694 e2 and 1 2 >sa0 >sa1
486 662
695 e3 and 1 2 >sa0 >sa1
498 663
696 e4 and 1 2 >sa0 >sa1
463 664
697 e5 and 1 2 >sa0 >sa1
475 665
698 e6 and 1 2 >sa0 >sa1
487 666
699 e7 and 1 2 >sa0 >sa1
499 667
700 e8 and 1 2 >sa0 >sa1
464 668
701 e9 and 1 2 >sa0 >sa1
476 669
702 e10 and 1 2 >sa0 >sa1
488 670
703 e11 and 1 2 >sa0 >sa1
500 671
704 e12 and 1 2 >sa0 >sa1
465 672
705 e13 and 1 2 >sa0 >sa1
477 673
706 e14 and 1 2 >sa0 >sa1
489 674
707 e15 and 1 2 >sa0 >sa1
501 675
708 e16 and 1 2 >sa0 >sa1
510 676
709 e17 and 1 2 >sa0 >sa1
522 677
710 e18 and 1 2 >sa0 >sa1
534 678
711 e19 and 1 2 >sa0 >sa1
546 679
712 e20 and 1 2 >sa0 >sa1
511 680
713 e21 and 1 2 >sa0 >sa1
523 681
714 e22 and 1 2 >sa0 >sa1
535 682
715 e23 and 1 2 >sa0 >sa1
547 683
716 e24 and 1 2 >sa0 >sa1
512 684
717 e25 and 1 2 >sa0 >sa1
524 685
718 e26 and 1 2 >sa0 >sa1
536 686
719 e27 and 1 2 >sa0 >sa1
548 687
720 e28 and 1 2 >sa0 >sa1
513 688
721 e29 and 1 2 >sa0 >sa1
525 689
722 e30 and 1 2 >sa0 >sa1
537 690
723 e31 and 1 2 >sa0 >sa1
549 691
724 od0 xor 0 2 >sa0 >sa1
148 692
725 od1 xor 0 2 >sa0 >sa1
151 693
726 od2 xor 0 2 >sa0 >sa1
154 694
727 od3 xor 0 2 >sa0 >sa1
157 695
728 od4 xor 0 2 >sa0 >sa1
160 696
729 od5 xor 0 2 >sa0 >sa1
163 697
730 od6 xor 0 2 >sa0 >sa1
166 698
731 od7 xor 0 2 >sa0 >sa1
169 699
732 od8 xor 0 2 >sa0 >sa1
172 700
733 od9 xor 0 2 >sa0 >sa1
175 701
734 od10 xor 0 2 >sa0 >sa1
178 702
735 od11 xor 0 2 >sa0 >sa1
181 703
736 od12 xor 0 2 >sa0 >sa1
184 704
737 od13 xor 0 2 >sa0 >sa1
187 705
738 od14 xor 0 2 >sa0 >sa1
190 706
739 od15 xor 0 2 >sa0 >sa1
193 707
740 od16 xor 0 2 >sa0 >sa1
196 708
741 od17 xor 0 2 >sa0 >sa1
199 709
742 od18 xor 0 2 >sa0 >sa1
202 710
743 od19 xor 0 2 >sa0 >sa1
205 711
744 od20 xor 0 2 >sa0 >sa1
208 712
745 od21 xor 0 2 >sa0 >sa1
211 713
746 od22 xor 0 2 >sa0 >sa1
214 714
747 od23 xor 0 2 >sa0 >sa1
217 715
748 od24 xor 0 2 >sa0 >sa1
220 716
749 od25 xor 0 2 >sa0 >sa1
223 717
750 od26 xor 0 2 >sa0 >sa1
226 718
751 od27 xor 0 2 >sa0 >sa1
229 719
752 od28 xor 0 2 >sa0 >sa1
232 720
753 od29 xor 0 2 >sa0 >sa1
235 721
754 od30 xor 0 2 >sa0 >sa1
238 722
755 od31 xor 0 2 >sa0 >sa1
241 723
|
Added c499.tests.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 | 10001000000000000000000000000000100010011 01000000000000000000000000000000111111110 00100000000000000000000000000000000000001 00010000000000000000000000000000000000001 00001000000000000000000000000000000000001 00000100000000000000000000000000000000001 00000010000000000000000000000000000000001 00000001000000000000000000000000000000001 00000000100000000000000000000000000000001 00000000010000000000000000000000000000001 00000000001000000000000000000000000000001 00000000000100000000000000000000000000001 00000000000010000000000000000000000000001 00000000000001000000000000000000000000001 00000000000000100000000000000000000000001 00000000000000010000000000000000000000001 00000000000000001000000000000000000000001 00000000000000000100000000000000000000001 00000000000000000010000000000000000000001 00000000000000000001000000000000000000001 00000000000000000000100000000000000000001 00000000000000000000010000000000000000001 00000000000000000000001000000000000000001 00000000000000000000000100000000000000001 00000000000000000000000010000000000000001 00000000000000000000000001000000000000001 00000000000000000000000000100000000000001 00000000000000000000000000010000000000001 00000000000000000000000000001000000000001 00000000000000000000000000000100000000001 00000000000000000000000000000010000000001 00000000000000000000000000000001000000001 11111111111111111111111111111111100010001 11111111111111111111111111111111010001001 11111111111111111111111111111111001000101 11111111111111111111111111111111000100011 11111111111111111111111111111111101010101 11111111111111111111111111111111100110011 11111111111111111111111111111111011001101 11111111111111111111111111111111010101011 11111111111111111111111111111111100001111 11111111111111111111111111111111010010111 11111111111111111111111111111111001011011 11111111111111111111111111111111000111101 11111111111111111111111111111111011110001 11111111111111111111111111111111101101001 11111111111111111111111111111111110100101 11111111111111111111111111111111111000011 11111111111111111111111111111111110010101 11111111111111111111111111111111001110101 11111111111111111111111111111111101011001 11111111111111111111111111111111101000111 |
Added c499.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 |
/****************************************************************************
* *
* VERILOG HIGH-LEVEL DESCRIPTION OF THE ISCAS-85 BENCHMARK CIRCUIT c499 *
* *
* Function: Single-Error-Correcting Circuit *
* *
* Written by: Mark C. Hansen *
* *
* Last modified: Jan 12, 1998 *
* *
****************************************************************************/
module Circuit499 (in1, in5, in9, in13, in17, in21, in25, in29,
in33, in37, in41, in45, in49, in53, in57, in61,
in65, in69, in73, in77, in81, in85, in89, in93,
in97, in101, in105, in109, in113, in117, in121, in125,
in129, in130, in131, in132, in133, in134, in135, in136,
in137,
out724, out725, out726, out727, out728, out729, out730, out731,
out732, out733, out734, out735, out736, out737, out738, out739,
out740, out741, out742, out743, out744, out745, out746, out747,
out748, out749, out750, out751, out752, out753, out754, out755);
input in1, in5, in9, in13, in17, in21, in25, in29,
in33, in37, in41, in45, in49, in53, in57, in61,
in65, in69, in73, in77, in81, in85, in89, in93,
in97, in101, in105, in109, in113, in117, in121, in125,
in129, in130, in131, in132, in133, in134, in135, in136,
in137;
output out724, out725, out726, out727, out728, out729, out730, out731,
out732, out733, out734, out735, out736, out737, out738, out739,
out740, out741, out742, out743, out744, out745, out746, out747,
out748, out749, out750, out751, out752, out753, out754, out755;
wire [0:31] ID, OD;
wire [0:7] IC;
wire R;
assign
ID[0:31] = { in1, in5, in9, in13, in17, in21, in25, in29,
in33, in37, in41, in45, in49, in53, in57, in61,
in65, in69, in73, in77, in81, in85, in89, in93,
in97, in101, in105, in109, in113, in117, in121, in125},
IC[0:7] = { in129, in130, in131, in132, in133, in134, in135, in136},
R = in137,
OD[0:31] = {
out724, out725, out726, out727, out728, out729, out730, out731,
out732, out733, out734, out735, out736, out737, out738, out739,
out740, out741, out742, out743, out744, out745, out746, out747,
out748, out749, out750, out751, out752, out753, out754, out755};
TopLevel499 Ckt499 (ID, IC, R, OD);
endmodule /* Circuit499 */
/*************************************************************************/
module TopLevel499 (ID, IC, R, OD);
input[0:31] ID;
input[0:7] IC;
input R;
output[0:31] OD;
wire[0:7] S;
Syndrome M1(S, R, IC, ID);
Correction M2(OD, S, ID);
endmodule /* TopLevel499 */
/*************************************************************************/
module Syndrome (S, R, IC, ID);
input[0:31] ID;
input[0:7] IC;
input R;
output[0:7] S;
wire[0:15] XA;
wire[0:7] XB, XC, XD, XE, F, G, H;
xor XA0(XA[0], ID[0], ID[1]);
xor XA1(XA[1], ID[2], ID[3]);
xor XA2(XA[2], ID[4], ID[5]);
xor XA3(XA[3], ID[6], ID[7]);
xor XA4(XA[4], ID[8], ID[9]);
xor XA5(XA[5], ID[10], ID[11]);
xor XA6(XA[6], ID[12], ID[13]);
xor XA7(XA[7], ID[14], ID[15]);
xor XA8(XA[8], ID[16], ID[17]);
xor XA9(XA[9], ID[18], ID[19]);
xor XA10(XA[10], ID[20], ID[21]);
xor XA11(XA[11], ID[22], ID[23]);
xor XA12(XA[12], ID[24], ID[25]);
xor XA13(XA[13], ID[26], ID[27]);
xor XA14(XA[14], ID[28], ID[29]);
xor XA15(XA[15], ID[30], ID[31]);
xor F0(F[0], XA[0], XA[1]);
xor F1(F[1], XA[2], XA[3]);
xor F2(F[2], XA[4], XA[5]);
xor F3(F[3], XA[6], XA[7]);
xor F4(F[4], XA[8], XA[9]);
xor F5(F[5], XA[10], XA[11]);
xor F6(F[6], XA[12], XA[13]);
xor F7(F[7], XA[14], XA[15]);
and H0(H[0], IC[0], R);
and H1(H[1], IC[1], R);
and H2(H[2], IC[2], R);
and H3(H[3], IC[3], R);
and H4(H[4], IC[4], R);
and H5(H[5], IC[5], R);
and H6(H[6], IC[6], R);
and H7(H[7], IC[7], R);
xor XB0(XB[0], ID[0], ID[4]);
xor XB1(XB[1], ID[1], ID[5]);
xor XB2(XB[2], ID[2], ID[6]);
xor XB3(XB[3], ID[3], ID[7]);
xor XB4(XB[4], ID[16], ID[20]);
xor XB5(XB[5], ID[17], ID[21]);
xor XB6(XB[6], ID[18], ID[22]);
xor XB7(XB[7], ID[19], ID[23]);
xor XC0(XC[0], ID[8], ID[12]);
xor XC1(XC[1], ID[9], ID[13]);
xor XC2(XC[2], ID[10], ID[14]);
xor XC3(XC[3], ID[11], ID[15]);
xor XC4(XC[4], ID[24], ID[28]);
xor XC5(XC[5], ID[25], ID[29]);
xor XC6(XC[6], ID[26], ID[30]);
xor XC7(XC[7], ID[27], ID[31]);
xor XE0(XE[0], XB[0], XC[0]);
xor XE1(XE[1], XB[1], XC[1]);
xor XE2(XE[2], XB[2], XC[2]);
xor XE3(XE[3], XB[3], XC[3]);
xor XE4(XE[4], XB[4], XC[4]);
xor XE5(XE[5], XB[5], XC[5]);
xor XE6(XE[6], XB[6], XC[6]);
xor XE7(XE[7], XB[7], XC[7]);
xor G0(G[0], F[0], F[1]);
xor G1(G[1], F[2], F[3]);
xor G2(G[2], F[0], F[2]);
xor G3(G[3], F[1], F[3]);
xor G4(G[4], F[4], F[5]);
xor G5(G[5], F[6], F[7]);
xor G6(G[6], F[4], F[6]);
xor G7(G[7], F[5], F[7]);
xor XD0(XD[0], G[4], H[0]);
xor XD1(XD[1], G[5], H[1]);
xor XD2(XD[2], G[6], H[2]);
xor XD3(XD[3], G[7], H[3]);
xor XD4(XD[4], G[0], H[4]);
xor XD5(XD[5], G[1], H[5]);
xor XD6(XD[6], G[2], H[6]);
xor XD7(XD[7], G[3], H[7]);
xor S0(S[0], XD[0], XE[0]);
xor S1(S[1], XD[1], XE[1]);
xor S2(S[2], XD[2], XE[2]);
xor S3(S[3], XD[3], XE[3]);
xor S4(S[4], XD[4], XE[4]);
xor S5(S[5], XD[5], XE[5]);
xor S6(S[6], XD[6], XE[6]);
xor S7(S[7], XD[7], XE[7]);
endmodule /* Syndrome */
/*************************************************************************/
module Correction (OD, S, ID);
input[0:31] ID;
input[0:7] S;
output[0:31] OD;
wire[0:31] E;
wire[0:15] XA;
wire[0:7] XB, XC, XD, XE, F, G, H, T, W;
wire[0:4] S0B, S1B, S2B, S3B, S4B, S5B, S6B, S7B;
wire[0:1] U;
not S0B0(S0B[0], S[0]);
not S0B1(S0B[1], S[0]);
not S0B2(S0B[2], S[0]);
not S0B3(S0B[3], S[0]);
not S0B4(S0B[4], S[0]);
not S1B0(S1B[0], S[1]);
not S1B1(S1B[1], S[1]);
not S1B2(S1B[2], S[1]);
not S1B3(S1B[3], S[1]);
not S1B4(S1B[4], S[1]);
not S2B0(S2B[0], S[2]);
not S2B1(S2B[1], S[2]);
not S2B2(S2B[2], S[2]);
not S2B3(S2B[3], S[2]);
not S2B4(S2B[4], S[2]);
not S3B0(S3B[0], S[3]);
not S3B1(S3B[1], S[3]);
not S3B2(S3B[2], S[3]);
not S3B3(S3B[3], S[3]);
not S3B4(S3B[4], S[3]);
not S4B0(S4B[0], S[4]);
not S4B1(S4B[1], S[4]);
not S4B2(S4B[2], S[4]);
not S4B3(S4B[3], S[4]);
not S4B4(S4B[4], S[4]);
not S5B0(S5B[0], S[5]);
not S5B1(S5B[1], S[5]);
not S5B2(S5B[2], S[5]);
not S5B3(S5B[3], S[5]);
not S5B4(S5B[4], S[5]);
not S6B0(S6B[0], S[6]);
not S6B1(S6B[1], S[6]);
not S6B2(S6B[2], S[6]);
not S6B3(S6B[3], S[6]);
not S6B4(S6B[4], S[6]);
not S7B0(S7B[0], S[7]);
not S7B1(S7B[1], S[7]);
not S7B2(S7B[2], S[7]);
not S7B3(S7B[3], S[7]);
not S7B4(S7B[4], S[7]);
and T0(T[0], S0B[0], S1B[0], S2B[0], S[3]);
and T1(T[1], S0B[1], S1B[1], S[2], S3B[0]);
and T2(T[2], S0B[2], S[1], S2B[1], S3B[1]);
and T3(T[3], S[0], S1B[2], S2B[2], S3B[2]);
and T4(T[4], S4B[0], S5B[0], S6B[0], S[7]);
and T5(T[5], S4B[1], S5B[1], S[6], S7B[0]);
and T6(T[6], S4B[2], S[5], S6B[1], S7B[1]);
and T7(T[7], S[4], S5B[2], S6B[2], S7B[2]);
or U0(U[0], T[0], T[1], T[2], T[3]);
or U1(U[1], T[4], T[5], T[6], T[7]);
and W0(W[0], S[4], S5B[3], S[6], S7B[3], U[0]);
and W1(W[1], S[4], S5B[4], S6B[3], S[7], U[0]);
and W2(W[2], S4B[3], S[5], S[6], S7B[4], U[0]);
and W3(W[3], S4B[4], S[5], S6B[4], S[7], U[0]);
and W4(W[4], S[0], S1B[3], S[2], S3B[3], U[1]);
and W5(W[5], S[0], S1B[4], S2B[3], S[3], U[1]);
and W6(W[6], S0B[3], S[1], S[2], S3B[4], U[1]);
and W7(W[7], S0B[4], S[1], S2B[4], S[3], U[1]);
and E0(E[0], W[0], S[0]);
and E1(E[1], W[0], S[1]);
and E2(E[2], W[0], S[2]);
and E3(E[3], W[0], S[3]);
and E4(E[4], W[1], S[0]);
and E5(E[5], W[1], S[1]);
and E6(E[6], W[1], S[2]);
and E7(E[7], W[1], S[3]);
and E8(E[8], W[2], S[0]);
and E9(E[9], W[2], S[1]);
and E10(E[10], W[2], S[2]);
and E11(E[11], W[2], S[3]);
and E12(E[12], W[3], S[0]);
and E13(E[13], W[3], S[1]);
and E14(E[14], W[3], S[2]);
and E15(E[15], W[3], S[3]);
and E16(E[16], W[4], S[4]);
and E17(E[17], W[4], S[5]);
and E18(E[18], W[4], S[6]);
and E19(E[19], W[4], S[7]);
and E20(E[20], W[5], S[4]);
and E21(E[21], W[5], S[5]);
and E22(E[22], W[5], S[6]);
and E23(E[23], W[5], S[7]);
and E24(E[24], W[6], S[4]);
and E25(E[25], W[6], S[5]);
and E26(E[26], W[6], S[6]);
and E27(E[27], W[6], S[7]);
and E28(E[28], W[7], S[4]);
and E29(E[29], W[7], S[5]);
and E30(E[30], W[7], S[6]);
and E31(E[31], W[7], S[7]);
xor OD0(OD[0], ID[0], E[0]);
xor OD1(OD[1], ID[1], E[1]);
xor OD2(OD[2], ID[2], E[2]);
xor OD3(OD[3], ID[3], E[3]);
xor OD4(OD[4], ID[4], E[4]);
xor OD5(OD[5], ID[5], E[5]);
xor OD6(OD[6], ID[6], E[6]);
xor OD7(OD[7], ID[7], E[7]);
xor OD8(OD[8], ID[8], E[8]);
xor OD9(OD[9], ID[9], E[9]);
xor OD10(OD[10], ID[10], E[10]);
xor OD11(OD[11], ID[11], E[11]);
xor OD12(OD[12], ID[12], E[12]);
xor OD13(OD[13], ID[13], E[13]);
xor OD14(OD[14], ID[14], E[14]);
xor OD15(OD[15], ID[15], E[15]);
xor OD16(OD[16], ID[16], E[16]);
xor OD17(OD[17], ID[17], E[17]);
xor OD18(OD[18], ID[18], E[18]);
xor OD19(OD[19], ID[19], E[19]);
xor OD20(OD[20], ID[20], E[20]);
xor OD21(OD[21], ID[21], E[21]);
xor OD22(OD[22], ID[22], E[22]);
xor OD23(OD[23], ID[23], E[23]);
xor OD24(OD[24], ID[24], E[24]);
xor OD25(OD[25], ID[25], E[25]);
xor OD26(OD[26], ID[26], E[26]);
xor OD27(OD[27], ID[27], E[27]);
xor OD28(OD[28], ID[28], E[28]);
xor OD29(OD[29], ID[29], E[29]);
xor OD30(OD[30], ID[30], E[30]);
xor OD31(OD[31], ID[31], E[31]);
endmodule /* Correction */
|
Added c499b.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 |
/****************************************************************************
* *
* VERILOG BEHAVIORAL DESCRIPTION OF THE ISCAS-85 BENCHMARK CIRCUIT c499 *
* *
* Function: Single-Error-Correcting Circuit *
* *
* Written by: Mark C. Hansen *
* *
* Last modified: Jan 12, 1998 *
* *
****************************************************************************/
module Circuit499 (in1, in5, in9, in13, in17, in21, in25, in29,
in33, in37, in41, in45, in49, in53, in57, in61,
in65, in69, in73, in77, in81, in85, in89, in93,
in97, in101, in105, in109, in113, in117, in121, in125,
in129, in130, in131, in132, in133, in134, in135, in136,
in137,
out724, out725, out726, out727, out728, out729, out730, out731,
out732, out733, out734, out735, out736, out737, out738, out739,
out740, out741, out742, out743, out744, out745, out746, out747,
out748, out749, out750, out751, out752, out753, out754, out755);
input in1, in5, in9, in13, in17, in21, in25, in29,
in33, in37, in41, in45, in49, in53, in57, in61,
in65, in69, in73, in77, in81, in85, in89, in93,
in97, in101, in105, in109, in113, in117, in121, in125,
in129, in130, in131, in132, in133, in134, in135, in136,
in137;
output out724, out725, out726, out727, out728, out729, out730, out731,
out732, out733, out734, out735, out736, out737, out738, out739,
out740, out741, out742, out743, out744, out745, out746, out747,
out748, out749, out750, out751, out752, out753, out754, out755;
wire [0:31] ID, OD;
wire [0:7] IC;
wire R;
assign
ID[0:31] = { in1, in5, in9, in13, in17, in21, in25, in29,
in33, in37, in41, in45, in49, in53, in57, in61,
in65, in69, in73, in77, in81, in85, in89, in93,
in97, in101, in105, in109, in113, in117, in121, in125},
IC[0:7] = { in129, in130, in131, in132, in133, in134, in135, in136},
R = in137,
OD[0:31] = {
out724, out725, out726, out727, out728, out729, out730, out731,
out732, out733, out734, out735, out736, out737, out738, out739,
out740, out741, out742, out743, out744, out745, out746, out747,
out748, out749, out750, out751, out752, out753, out754, out755};
TopLevel499b Ckt499b (ID, IC, R, OD);
endmodule /* Circuit499 */
/*************************************************************************/
module TopLevel499b (ID, IC, R, OD);
input[0:31] ID;
input[0:7] IC;
input R;
output[0:31] OD;
wire[0:7] S;
Syndrome M1(S, R, IC, ID);
Correction M2(OD, S, ID);
endmodule /* TopLevel499b */
/*************************************************************************/
module Syndrome (S, R, IC, ID);
input[0:31] ID;
input[0:7] IC;
input R;
output[0:7] S;
assign S[0] = (ID[0] ^ ID[4] ^ ID[8] ^ ID[12]) ^
(ID[16] ^ ID[17] ^ ID[18] ^ ID[19]) ^
(ID[20] ^ ID[21] ^ ID[22] ^ ID[23]) ^
(R & IC[0]);
assign S[1] = (ID[1] ^ ID[5] ^ ID[9] ^ ID[13]) ^
(ID[24] ^ ID[25] ^ ID[26] ^ ID[27]) ^
(ID[28] ^ ID[29] ^ ID[30] ^ ID[31]) ^
(R & IC[1]);
assign S[2] = (ID[2] ^ ID[6] ^ ID[10] ^ ID[14]) ^
(ID[16] ^ ID[17] ^ ID[18] ^ ID[19]) ^
(ID[24] ^ ID[25] ^ ID[26] ^ ID[27]) ^
(R & IC[2]);
assign S[3] = (ID[3] ^ ID[7] ^ ID[11] ^ ID[15]) ^
(ID[20] ^ ID[21] ^ ID[22] ^ ID[23]) ^
(ID[28] ^ ID[29] ^ ID[30] ^ ID[31]) ^
(R & IC[3]);
assign S[4] = (ID[16] ^ ID[20] ^ ID[24] ^ ID[28]) ^
(ID[0] ^ ID[1] ^ ID[2] ^ ID[3]) ^
(ID[4] ^ ID[5] ^ ID[6] ^ ID[7]) ^
(R & IC[4]);
assign S[5] = (ID[17] ^ ID[21] ^ ID[25] ^ ID[29]) ^
(ID[8] ^ ID[9] ^ ID[10] ^ ID[11]) ^
(ID[12] ^ ID[13] ^ ID[14] ^ ID[15]) ^
(R & IC[5]);
assign S[6] = (ID[18] ^ ID[22] ^ ID[26] ^ ID[30]) ^
(ID[0] ^ ID[1] ^ ID[2] ^ ID[3]) ^
(ID[8] ^ ID[9] ^ ID[10] ^ ID[11]) ^
(R & IC[6]);
assign S[7] = (ID[19] ^ ID[23] ^ ID[27] ^ ID[31]) ^
(ID[4] ^ ID[5] ^ ID[6] ^ ID[7]) ^
(ID[12] ^ ID[13] ^ ID[14] ^ ID[15]) ^
(R & IC[7]);
endmodule /* Syndrome */
/*************************************************************************/
module Correction (OD, S, ID);
input[0:31] ID;
input[0:7] S;
output[0:31] OD;
assign OD[0] = (S[0] & ~S[1] & ~S[2] & ~S[3] & S[4] & ~S[5] & S[6] & ~S[7])
^ ID[0];
assign OD[1] = (~S[0] & S[1] & ~S[2] & ~S[3] & S[4] & ~S[5] & S[6] & ~S[7])
^ ID[1];
assign OD[2] = (~S[0] & ~S[1] & S[2] & ~S[3] & S[4] & ~S[5] & S[6] & ~S[7])
^ ID[2];
assign OD[3] = (~S[0] & ~S[1] & ~S[2] & S[3] & S[4] & ~S[5] & S[6] & ~S[7])
^ ID[3];
assign OD[4] = (S[0] & ~S[1] & ~S[2] & ~S[3] & S[4] & ~S[5] & ~S[6] & S[7])
^ ID[4];
assign OD[5] = (~S[0] & S[1] & ~S[2] & ~S[3] & S[4] & ~S[5] & ~S[6] & S[7])
^ ID[5];
assign OD[6] = (~S[0] & ~S[1] & S[2] & ~S[3] & S[4] & ~S[5] & ~S[6] & S[7])
^ ID[6];
assign OD[7] = (~S[0] & ~S[1] & ~S[2] & S[3] & S[4] & ~S[5] & ~S[6] & S[7])
^ ID[7];
assign OD[8] = (S[0] & ~S[1] & ~S[2] & ~S[3] & ~S[4] & S[5] & S[6] & ~S[7])
^ ID[8];
assign OD[9] = (~S[0] & S[1] & ~S[2] & ~S[3] & ~S[4] & S[5] & S[6] & ~S[7])
^ ID[9];
assign OD[10] = (~S[0] & ~S[1] & S[2] & ~S[3] & ~S[4] & S[5] & S[6] & ~S[7])
^ ID[10];
assign OD[11] = (~S[0] & ~S[1] & ~S[2] & S[3] & ~S[4] & S[5] & S[6] & ~S[7])
^ ID[11];
assign OD[12] = (S[0] & ~S[1] & ~S[2] & ~S[3] & ~S[4] & S[5] & ~S[6] & S[7])
^ ID[12];
assign OD[13] = (~S[0] & S[1] & ~S[2] & ~S[3] & ~S[4] & S[5] & ~S[6] & S[7])
^ ID[13];
assign OD[14] = (~S[0] & ~S[1] & S[2] & ~S[3] & ~S[4] & S[5] & ~S[6] & S[7])
^ ID[14];
assign OD[15] = (~S[0] & ~S[1] & ~S[2] & S[3] & ~S[4] & S[5] & ~S[6] & S[7])
^ ID[15];
assign OD[16] = (S[4] & ~S[5] & ~S[6] & ~S[7] & S[0] & ~S[1] & S[2] & ~S[3])
^ ID[16];
assign OD[17] = (~S[4] & S[5] & ~S[6] & ~S[7] & S[0] & ~S[1] & S[2] & ~S[3])
^ ID[17];
assign OD[18] = (~S[4] & ~S[5] & S[6] & ~S[7] & S[0] & ~S[1] & S[2] & ~S[3])
^ ID[18];
assign OD[19] = (~S[4] & ~S[5] & ~S[6] & S[7] & S[0] & ~S[1] & S[2] & ~S[3])
^ ID[19];
assign OD[20] = (S[4] & ~S[5] & ~S[6] & ~S[7] & S[0] & ~S[1] & ~S[2] & S[3])
^ ID[20];
assign OD[21] = (~S[4] & S[5] & ~S[6] & ~S[7] & S[0] & ~S[1] & ~S[2] & S[3])
^ ID[21];
assign OD[22] = (~S[4] & ~S[5] & S[6] & ~S[7] & S[0] & ~S[1] & ~S[2] & S[3])
^ ID[22];
assign OD[23] = (~S[4] & ~S[5] & ~S[6] & S[7] & S[0] & ~S[1] & ~S[2] & S[3])
^ ID[23];
assign OD[24] = (S[4] & ~S[5] & ~S[6] & ~S[7] & ~S[0] & S[1] & S[2] & ~S[3])
^ ID[24];
assign OD[25] = (~S[4] & S[5] & ~S[6] & ~S[7] & ~S[0] & S[1] & S[2] & ~S[3])
^ ID[25];
assign OD[26] = (~S[4] & ~S[5] & S[6] & ~S[7] & ~S[0] & S[1] & S[2] & ~S[3])
^ ID[26];
assign OD[27] = (~S[4] & ~S[5] & ~S[6] & S[7] & ~S[0] & S[1] & S[2] & ~S[3])
^ ID[27];
assign OD[28] = (S[4] & ~S[5] & ~S[6] & ~S[7] & ~S[0] & S[1] & ~S[2] & S[3])
^ ID[28];
assign OD[29] = (~S[4] & S[5] & ~S[6] & ~S[7] & ~S[0] & S[1] & ~S[2] & S[3])
^ ID[29];
assign OD[30] = (~S[4] & ~S[5] & S[6] & ~S[7] & ~S[0] & S[1] & ~S[2] & S[3])
^ ID[30];
assign OD[31] = (~S[4] & ~S[5] & ~S[6] & S[7] & ~S[0] & S[1] & ~S[2] & S[3])
^ ID[31];
endmodule /* Correction */
|
Added c499bus.html.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c499bus</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\Program Files\Microsoft Office\Office\HTML.DOT"> </HEAD> <BODY TEXT="#000000" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C499/C1355 32-Bit Single-Error Correcting Circuit</P> <P ALIGN="CENTER">Bus Translations</P> </B></FONT><P> </P> <TABLE BORDER CELLSPACING=1 WIDTH=810> <TR><TD WIDTH="12%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997553"></A><B>I/O buses</B></TD> <TD WIDTH="24%" VALIGN="MIDDLE"> <B><P ALIGN="CENTER"><A NAME="pgfId_997555"></A>Function</B></TD> <TD WIDTH="65%" VALIGN="MIDDLE"> <B><P ALIGN="CENTER"><A NAME="pgfId_997560"></A>ISCAS-85 Netlist numbers </B></TD> </TR> <TR><TD WIDTH="12%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997562"></A>ID[0:31]</TD> <TD WIDTH="24%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997564"></A>Input data</TD> <TD WIDTH="65%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997566"></A>1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69,</P> <P ALIGN="CENTER"><A NAME="pgfId_997567"></A>73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125</TD> </TR> <TR><TD WIDTH="12%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997569"></A>IC[0:8]</TD> <TD WIDTH="24%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997571"></A>Input code</TD> <TD WIDTH="65%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997573"></A>129, 130, 131, 132, 133, 134, 135, 136</TD> </TR> <TR><TD WIDTH="12%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997575"></A>R</TD> <TD WIDTH="24%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997577"></A>Read line</TD> <TD WIDTH="65%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997579"></A>137</TD> </TR> <TR><TD WIDTH="12%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997581"></A>OD[0:31]</TD> <TD WIDTH="24%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997583"></A>Corrected output data</TD> <TD WIDTH="65%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997585"></A>724-755</TD> </TR> </TABLE> <P><A NAME="pgfId_997381"></A> </P></BODY> </HTML> |
Added c499hmatrix.html.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c499hmatrix</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\Program Files\Microsoft Office\Office\HTML.DOT"> </HEAD> <BODY TEXT="#000000" LINK="#0000ff" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P>ISCAS-85 C499/C1355 32-Bit Single-Error Correcting Circuit</P> <P ALIGN="CENTER">H matrix for a (40,32) Hamming code</P> </B></FONT><P> </P> <TABLE BORDER CELLSPACING=1 WIDTH=630> <TR><TD WIDTH="13%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><B> </B></TD> <TD WIDTH="63%" VALIGN="MIDDLE"> <B><P ALIGN="CENTER">ID 00 - ID 31 </B></TD> <TD WIDTH="24%" VALIGN="MIDDLE"> <B><P ALIGN="CENTER">IC 0 - IC 8 </B></TD> </TR> <TR><TD WIDTH="13%" VALIGN="MIDDLE"> <B><P ALIGN="CENTER">S7 - S0</B></TD> <TD WIDTH="63%" VALIGN="MIDDLE"> <P ALIGN="CENTER">1000 1000 1000 1000 1111 1111 0000 0000</P> <P ALIGN="CENTER">0100 0100 0100 0100 0000 0000 1111 1111</P> <P ALIGN="CENTER">0010 0010 0010 0010 1111 0000 1111 0000</P> <P ALIGN="CENTER">0001 0001 0001 0001 0000 1111 0000 1111</P> <P ALIGN="CENTER">1111 1111 0000 0000 1000 1000 1000 1000</P> <P ALIGN="CENTER">0000 0000 1111 1111 0100 0100 0100 0100</P> <P ALIGN="CENTER">1111 0000 1111 0000 0010 0010 0010 0010</P> <P ALIGN="CENTER">0000 1111 0000 1111 0001 0001 0001 0001</TD> <TD WIDTH="24%" VALIGN="MIDDLE"> <P ALIGN="CENTER">1000 0000</P> <P ALIGN="CENTER">0100 0000</P> <P ALIGN="CENTER">0010 0000</P> <P ALIGN="CENTER">0001 0000</P> <P ALIGN="CENTER">0000 1000</P> <P ALIGN="CENTER">0000 0100</P> <P ALIGN="CENTER">0000 0010</P> <P ALIGN="CENTER">0000 0001</TD> </TR> </TABLE> <P> </P></BODY> </HTML> |
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> > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c499oequ</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\Program Files\Microsoft Office\Office\HTML.DOT"> </HEAD> <BODY TEXT="#000000" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C499/C1355 Output Equations</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="c499oequ-1.gif" WIDTH=478 HEIGHT=673></P> <P ALIGN="CENTER"><IMG SRC="c499oequ-2.gif" WIDTH=478 HEIGHT=590></P></BODY> </HTML> |
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> > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c499sequ</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\Program Files\Microsoft Office\Office\HTML.DOT"> </HEAD> <BODY TEXT="#000000" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C499/C1355 Syndrome Equations</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="c499sequ.gif" WIDTH=499 HEIGHT=608></P></BODY> </HTML> |
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 | <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML EXPERIMENTAL 970324//EN"> <HTML> <HEAD> <META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter"> <LINK REL="STYLESHEET" HREF="c5315.css"> <TITLE> High-Level Model of c5315 </TITLE> </HEAD> <BODY BGCOLOR="#ffffff"> <DIV> <H1 CLASS="Title"> <A NAME="pgfId=1009569"> </A> High-Level Model of c5315</H1> <br> <B>Statistics: </B> 178 inputs; 123 outputs; 2406 gates</P> <P CLASS="Body"> <A NAME="pgfId=1009574"> </A> <B> Function: </B> 9-bit ALU</P> <P CLASS="Body"> <A NAME="pgfId=1013855"> </A> This benchmark is an ALU that performs arithmetic and logic operations simultaneously on two 9-bit input data words, and also computes the parity of the results. Modules M6 and M7 each compute an arithmetic or logic operation specified by the control input bus CF[7:0]. Module M5 consists of multiplexers that route the results of M6 and M7 and four input buses to its four outputs. Output buses OF1 and OF2 can also be set to <B>logic 0</B> by MuxSel[8]. Modules M3 and M4 compute the parity of the result of the operation given by CP=CF[7:4]. Module M5 contains four multiplexers which direct the parity results and an additional set of four inputs to its outputs. The adders in M6 and M7 as well as the parity logic for the arithmetic operations in M3 and M4 use a carry-select scheme with 4-bit (low-order) and 5-bit (high-order) blocks. The circuit also includes logic for calculating various zero and parity flags of the input buses.</P> <br> <A HREF="#pgfId=1008955"> <B>Inputs/Outputs vs. Netlist numbers</B></A> <HR> <B><P>Models:</P></B> <UL> <LI>I. Original ISCAS gate-level netlist <UL> <LI><A HREF="c5315.isc">in ISCAS-89 format</A> </LI> <LI><A HREF="c5315gate.v">in Verilog</A></LI> </UL> </LI> <LI>II. <A HREF="c5315high.v">Verilog hierarchical netlist</A> (functionally equivalent to I) </LI> <LI>III. <A HREF="flat5315.v">Verilog flat netlist </A> (flat version of II; functionally equivalent to I, but with minor structural differences) </LI> </UL> <HR> <br> <DIV> <IMG SRC="c5315-1.gif" USEMAP="#c5315-7"> </DIV> <br> <DIV> <IMG SRC="c5315-2.gif" USEMAP="#c5315-7"> </DIV> <br> <DIV> <IMG SRC="c5315-3.gif" USEMAP="#c5315-7"> </DIV> <br> <DIV> <IMG SRC="c5315-4.gif" USEMAP="#c5315-7"> </DIV> <br> <DIV> <IMG SRC="c5315-5.gif" USEMAP="#c5315-7"> </DIV> <br> <DIV> <IMG SRC="c5315-6.gif" USEMAP="#c5315-7"> </DIV> <br> <DIV> <MAP NAME="c5315-7"> </MAP> <IMG SRC="c5315-7.gif" USEMAP="#c5315-7"> </DIV> <br> <DIV> <IMG SRC="c5315-8.gif" USEMAP="#c5315-7"> </DIV> <br> <DIV> <IMG SRC="c5315-9.gif" USEMAP="#c5315-7"> </DIV> <br> <DIV> <IMG SRC="c5315-10.gif" USEMAP="#c5315-7"> </DIV> <br> <br> <A NAME="pgfId=1008955"> </A> <TABLE BORDER="1"> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1008956"> </A> Input</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1008958"> </A> Line number</P> </TH> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1008960"> </A> X0[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1008962"> </A> 293, 302, 308, 316, 324, <B>logic 1</B>, 341, 351, 361</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1008964"> </A> X1[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1008966"> </A> 299, 307, 315, 323, 331, 338, 348, 358, 366</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009239"> </A> MuxSelX</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009241"> </A> 332</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1008968"> </A> A[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1008970"> </A> <B>logic 1</B>, <B>logic 1</B>, 479, 490, 503, 514, 523, 534, <B>logic 1</B></P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1008984"> </A> Y0[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1008986"> </A> 206, 210, 218, 226, 234, 257, 265, 273, 281</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1008988"> </A> Y1[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1008990"> </A> 209, 217, 225, 233, 241, 264, 272, 280, 288</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009243"> </A> MuxSelY</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009245"> </A> 335</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1008992"> </A> B[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1008994"> </A> 446, 457, 468, 422, 435, 389, 400, 411, 374</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009031"> </A> CinFX, CinFY</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009033"> </A> 54, 4</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013443"> </A> CinPX,CinPY</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013445"> </A> 2174, 1497</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009019"> </A> WpX[1:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009039"> </A> 120, 94</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009015"> </A> WpY[1:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009041"> </A> 118, 97</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013470"> </A> QP1,QP2,QP3,QP4</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013472"> </A> 176, 179, 14, 64</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009055"> </A> Q1[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009043"> </A> 191, 194, 197, 203, 200, 149, 155, 188, 182</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009057"> </A> Q2[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009045"> </A> 161, 164, 167, 173, 170, 146, 152, 158, 185</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009059"> </A> Q3[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009005"> </A> 109, 46, 100, 91, 43, 76, 73, 67, 11</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009061"> </A> Q4[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1008998"> </A> 106, 49, 103, 40, 37, 20, 17, 70, 61</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009099"> </A> WFX[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009101"> </A> 123, 121, 116, 112, 52, 130, 119, 129, 131</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009095"> </A> WFY[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009097"> </A> 115, 114, 53, 113, 122, 128, 127, 126, 117</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009091"> </A> MuxSel[10:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009093"> </A> 4091, 4092, 137, 4090, 4089, 4087, 4088, 1694, 1691, 1690, 1689</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013462"> </A> CF[7:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013464"> </A> 248, 251, 242, 254, 3552, 3550, 3546, 3548</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013458"> </A> CP[3:0]=CF[7:4]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013460"> </A> 248, 251, 242, 254</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013439"> </A> ParYin= MuxSelY ? ParYin0 : ParYin1</P> <P CLASS="CellBody"> <A NAME="pgfId=1013835"> </A> (ParYin0, ParYin1)</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013441"> </A> </P> <P CLASS="CellBody"> <A NAME="pgfId=1013838"> </A> 289, 292</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013435"> </A> ParXin= MuxSelX ? ParXin0 : ParXin1</P> <P CLASS="CellBody"> <A NAME="pgfId=1013839"> </A> (ParXin0, ParXin1)</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013437"> </A> </P> <P CLASS="CellBody"> <A NAME="pgfId=1013842"> </A> 369, 372</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013476"> </A> ContParChk[5:0]<EM CLASS="no-overline"> </EM> </P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013478"> </A> 562, 245, 552, 556, 559, 386</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013480"> </A> MiscMuxIn[17:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013482"> </A> 123 (=WFX[8]), 132, 23, 80, 25, 81, 79, 82, 24, 26, 86, 83, 88, 88, 87, 83, 34, 34</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013495"> </A> MiscContIn[7:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013497"> </A> 4115, 135, 3717, 3724, 141, 2358, 31, 27</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013501"> </A> MiscIn[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013503"> </A> 545, 549, 3173, 136, 1, 373, 145, 2824, 140</P> </TD> </TR> </TABLE> <P CLASS="Body"> <A NAME="pgfId=1008948"> </A> </P> <TABLE BORDER="1"> <TR> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1009282"> </A> Output</P> </TH> <TH ROWSPAN="1" COLSPAN="1"> <P CLASS="CellHeading"> <A NAME="pgfId=1009284"> </A> Line number</P> </TH> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009434"> </A> OP1,OP2,OP3,OP4</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009436"> </A> 658, 690, 767, 807</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009438"> </A> OF1[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009440"> </A> 654, 642, 651, 648, 645, 670, 667, 664, 661</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009442"> </A> OF2[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009444"> </A> 688, 676, 685, 682, 679, 702, 699, 696, 693</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009446"> </A> OF3[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009448"> </A> 727, 747, 732, 737, 742, 752, 757, 762, 722</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009450"> </A> OF4[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009452"> </A> 712, 787, 772, 777, 782, 792, 797, 802, 859</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009454"> </A> NXF[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009456"> </A> 824, 826, 828, 830, 832, 834, 836, 838, 822</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009458"> </A> NYF[8:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009460"> </A> 863, 865, 867, 869, 871, 873, 875, 877, 861</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009462"> </A> CoX,CoY</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009464"> </A> (629, 618)<A HREF="#pgfId=1013809" CLASS="footnote"> *</A> , (591, 621)<A HREF="#pgfId=1013809" CLASS="footnote"> *</A> </P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009466"> </A> PoX,PoY</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009468"> </A> 843, 882</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009470"> </A> ParityChk[4:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009472"> </A> 998, 1002, 1000, 1004, 854</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009474"> </A> ZeroFlagOut[3:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1009476"> </A> 585, 575, 598, 610</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013536"> </A> MiscMuxOut[10:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013538"> </A> 623, 813, 818, 707, 715, 639, 673, 636, 820, 717, 704</P> </TD> </TR> <TR> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013555"> </A> MiscOut[25:0]</P> </TD> <TD ROWSPAN="1" COLSPAN="1"> <P CLASS="CellBody"> <A NAME="pgfId=1013602"> </A> 593, 594, 602, 809, 611, 599, 612, 600, 850, 848, 849, 851, 887, 298, 926, 892, 973, 993, 144, 601, 847, 815, 634, 810, 845, 656</P> </TD> </TR> </TABLE> <P CLASS="TableFootnote"> <SPAN CLASS="footnoteNumber"> *.</SPAN> <A NAME="pgfId=1013809"> </A> (a,b): a,b are identical outputs.</P> <br> <P> <A HREF="#pgfId=1009569"> Go to top of this file</A></P> <P> <A HREF="../benchmark.html"> Go back to the Benchmark List</A></P> </DIV> </DIV> </BODY> </HTML> |
Added c5315/c5315.isc.
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2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 | # combinational logic example "c5315" #------------------------------------------------------------- # # # total number of lines in the netlist .............. 5315 # simplistically reduced equivalent fault set size = 5350 # lines from primary input gates ....... 178 # lines from primary output gates ....... 123 # lines from interior gate outputs ...... 2184 # lines from ** 806 ** fanout stems ... 2830 # # avg_fanin = 1.90, max_fanin = 9 # avg_fanout = 3.51, max_fanout = 15 # # # # # INPUT(1) #... primary input INPUT(4) #... primary input INPUT(11) #... primary input INPUT(14) #... primary input INPUT(17) #... primary input INPUT(20) #... primary input INPUT(23) #... primary input INPUT(24) #... primary input INPUT(25) #... primary input INPUT(26) #... primary input INPUT(27) #... primary input INPUT(31) #... primary input INPUT(34) #... primary input INPUT(37) #... primary input INPUT(40) #... primary input INPUT(43) #... primary input INPUT(46) #... primary input INPUT(49) #... primary input INPUT(52) #... primary input INPUT(53) #... primary input INPUT(54) #... primary input INPUT(61) #... primary input INPUT(64) #... primary input INPUT(67) #... primary input INPUT(70) #... primary input INPUT(73) #... primary input INPUT(76) #... primary input INPUT(79) #... primary input INPUT(80) #... primary input INPUT(81) #... primary input INPUT(82) #... primary input INPUT(83) #... primary input INPUT(86) #... primary input INPUT(87) #... primary input INPUT(88) #... primary input INPUT(91) #... primary input INPUT(94) #... primary input INPUT(97) #... primary input INPUT(100) #... primary input INPUT(103) #... primary input INPUT(106) #... primary input INPUT(109) #... primary input INPUT(112) #... primary input INPUT(113) #... primary input INPUT(114) #... primary input INPUT(115) #... primary input INPUT(116) #... primary input INPUT(117) #... primary input INPUT(118) #... primary input INPUT(119) #... primary input INPUT(120) #... primary input INPUT(121) #... primary input INPUT(122) #... primary input INPUT(123) #... primary input INPUT(126) #... primary input INPUT(127) #... primary input INPUT(128) #... primary input INPUT(129) #... primary input INPUT(130) #... primary input INPUT(131) #... primary input INPUT(132) #... primary input INPUT(135) #... primary input INPUT(136) #... primary input INPUT(137) #... primary input INPUT(140) #... primary input INPUT(141) #... primary input INPUT(145) #... primary input INPUT(146) #... primary input INPUT(149) #... primary input INPUT(152) #... primary input INPUT(155) #... primary input INPUT(158) #... primary input INPUT(161) #... primary input INPUT(164) #... primary input INPUT(167) #... primary input INPUT(170) #... primary input INPUT(173) #... primary input INPUT(176) #... primary input INPUT(179) #... primary input INPUT(182) #... primary input INPUT(185) #... primary input INPUT(188) #... primary input INPUT(191) #... primary input INPUT(194) #... primary input INPUT(197) #... primary input INPUT(200) #... primary input INPUT(203) #... primary input INPUT(206) #... primary input INPUT(209) #... primary input INPUT(210) #... primary input INPUT(217) #... primary input INPUT(218) #... primary input INPUT(225) #... primary input INPUT(226) #... primary input INPUT(233) #... primary input INPUT(234) #... primary input INPUT(241) #... primary input INPUT(242) #... primary input INPUT(245) #... primary input INPUT(248) #... primary input INPUT(251) #... primary input INPUT(254) #... primary input INPUT(257) #... primary input INPUT(264) #... primary input INPUT(265) #... primary input INPUT(272) #... primary input INPUT(273) #... primary input INPUT(280) #... primary input INPUT(281) #... primary input INPUT(288) #... primary input INPUT(289) #... primary input INPUT(292) #... primary input INPUT(293) #... primary input INPUT(299) #... primary input INPUT(302) #... primary input INPUT(307) #... primary input INPUT(308) #... primary input INPUT(315) #... primary input INPUT(316) #... primary input INPUT(323) #... primary input INPUT(324) #... primary input INPUT(331) #... primary input INPUT(332) #... primary input INPUT(335) #... primary input INPUT(338) #... primary input INPUT(341) #... primary input INPUT(348) #... primary input INPUT(351) #... primary input INPUT(358) #... primary input INPUT(361) #... primary input INPUT(366) #... primary input INPUT(369) #... primary input INPUT(372) #... primary input INPUT(373) #... primary input INPUT(374) #... primary input INPUT(386) #... primary input INPUT(389) #... primary input INPUT(400) #... primary input INPUT(411) #... primary input INPUT(422) #... primary input INPUT(435) #... primary input INPUT(446) #... primary input INPUT(457) #... primary input INPUT(468) #... primary input INPUT(479) #... primary input INPUT(490) #... primary input INPUT(503) #... primary input INPUT(514) #... primary input INPUT(523) #... primary input INPUT(534) #... primary input INPUT(545) #... primary input INPUT(549) #... primary input INPUT(552) #... primary input INPUT(556) #... primary input INPUT(559) #... primary input INPUT(562) #... primary input INPUT(1497) #... primary input INPUT(1689) #... primary input INPUT(1690) #... primary input INPUT(1691) #... primary input INPUT(1694) #... primary input INPUT(2174) #... primary input INPUT(2358) #... primary input INPUT(2824) #... primary input INPUT(3173) #... primary input INPUT(3546) #... primary input INPUT(3548) #... primary input INPUT(3550) #... primary input INPUT(3552) #... primary input INPUT(3717) #... primary input INPUT(3724) #... primary input INPUT(4087) #... primary input INPUT(4088) #... primary input INPUT(4089) #... primary input INPUT(4090) #... primary input INPUT(4091) #... primary input INPUT(4092) #... primary input INPUT(4115) #... primary input # # OUTPUT(144) #... primary output OUTPUT(298) #... primary output OUTPUT(973) #... primary output OUTPUT(594) #... primary output OUTPUT(599) #... primary output OUTPUT(600) #... primary output OUTPUT(601) #... primary output OUTPUT(602) #... primary output OUTPUT(603) #... primary output OUTPUT(604) #... primary output OUTPUT(611) #... primary output OUTPUT(612) #... primary output OUTPUT(810) #... primary output OUTPUT(848) #... primary output OUTPUT(849) #... primary output OUTPUT(850) #... primary output OUTPUT(851) #... primary output OUTPUT(634) #... primary output OUTPUT(815) #... primary output OUTPUT(845) #... primary output OUTPUT(847) #... primary output OUTPUT(926) #... primary output OUTPUT(923) #... primary output OUTPUT(921) #... primary output OUTPUT(892) #... primary output OUTPUT(887) #... primary output OUTPUT(606) #... primary output OUTPUT(656) #... primary output OUTPUT(809) #... primary output OUTPUT(993) #... primary output OUTPUT(978) #... primary output OUTPUT(949) #... primary output OUTPUT(939) #... primary output OUTPUT(889) #... primary output OUTPUT(593) #... primary output OUTPUT(636) #... primary output OUTPUT(704) #... primary output OUTPUT(717) #... primary output OUTPUT(820) #... primary output OUTPUT(639) #... primary output OUTPUT(673) #... primary output OUTPUT(707) #... primary output OUTPUT(715) #... primary output OUTPUT(598) #... primary output OUTPUT(610) #... primary output OUTPUT(588) #... primary output OUTPUT(615) #... primary output OUTPUT(626) #... primary output OUTPUT(632) #... primary output OUTPUT(1002) #... primary output OUTPUT(1004) #... primary output OUTPUT(591) #... primary output OUTPUT(618) #... primary output OUTPUT(621) #... primary output OUTPUT(629) #... primary output OUTPUT(822) #... primary output OUTPUT(838) #... primary output OUTPUT(861) #... primary output OUTPUT(623) #... primary output OUTPUT(722) #... primary output OUTPUT(832) #... primary output OUTPUT(834) #... primary output OUTPUT(836) #... primary output OUTPUT(859) #... primary output OUTPUT(871) #... primary output OUTPUT(873) #... primary output OUTPUT(875) #... primary output OUTPUT(877) #... primary output OUTPUT(998) #... primary output OUTPUT(1000) #... primary output OUTPUT(575) #... primary output OUTPUT(585) #... primary output OUTPUT(661) #... primary output OUTPUT(693) #... primary output OUTPUT(747) #... primary output OUTPUT(752) #... primary output OUTPUT(757) #... primary output OUTPUT(762) #... primary output OUTPUT(787) #... primary output OUTPUT(792) #... primary output OUTPUT(797) #... primary output OUTPUT(802) #... primary output OUTPUT(642) #... primary output OUTPUT(664) #... primary output OUTPUT(667) #... primary output OUTPUT(670) #... primary output OUTPUT(676) #... primary output OUTPUT(696) #... primary output OUTPUT(699) #... primary output OUTPUT(702) #... primary output OUTPUT(818) #... primary output OUTPUT(813) #... primary output OUTPUT(824) #... primary output OUTPUT(826) #... primary output OUTPUT(828) #... primary output OUTPUT(830) #... primary output OUTPUT(854) #... primary output OUTPUT(863) #... primary output OUTPUT(865) #... primary output OUTPUT(867) #... primary output OUTPUT(869) #... primary output OUTPUT(712) #... primary output OUTPUT(727) #... primary output OUTPUT(732) #... primary output OUTPUT(737) #... primary output OUTPUT(742) #... primary output OUTPUT(772) #... primary output OUTPUT(777) #... primary output OUTPUT(782) #... primary output OUTPUT(645) #... primary output OUTPUT(648) #... primary output OUTPUT(651) #... primary output OUTPUT(654) #... primary output OUTPUT(679) #... primary output OUTPUT(682) #... primary output OUTPUT(685) #... primary output OUTPUT(688) #... primary output OUTPUT(843) #... primary output OUTPUT(882) #... primary output OUTPUT(767) #... primary output OUTPUT(807) #... primary output OUTPUT(658) #... primary output OUTPUT(690) #... primary output # # # Output Type Inputs... # ------ ---- --------- 144 = buff( 141) 298 = buff( 293) 4114 = and( 135, 4115) 2825 = not( 2824) 973 = buff( 3173) 3547 = not( 3546) 3549 = not( 3548) 3551 = not( 3550) 3553 = not( 3552) 594 = not( 545) 599 = not( 348) 600 = not( 366) 601 = and( 552, 562) 602 = not( 549) 603 = not( 545) 604 = not( 545) 611 = not( 338) 612 = not( 358) 633 = nand( 373, 1) 810 = and( 141, 145) 814 = not( 3173) 816 = not( 4114) 844 = and( 2825, 27) 846 = and( 386, 556) 848 = not( 245) 849 = not( 552) 850 = not( 562) 851 = not( 559) 852 = and( 386, 559, 556, 552) 1502 = not( 1497) 1528 = buff( 1689) 1552 = buff( 1690) 1609 = buff( 1689) 1633 = buff( 1690) 1697 = buff( 137) 1698 = buff( 137) 1701 = buff( 141) 2179 = not( 2174) 2203 = buff( 1691) 2226 = buff( 1694) 2281 = buff( 1691) 2304 = buff( 1694) 2361 = buff( 254) 2370 = buff( 251) 2382 = buff( 251) 2393 = buff( 248) 2405 = buff( 248) 2418 = buff( 4088) 2442 = buff( 4087) 2476 = buff( 4089) 2500 = buff( 4090) 2533 = buff( 210) 2537 = buff( 210) 2541 = buff( 218) 2545 = buff( 218) 2549 = buff( 226) 2553 = buff( 226) 2557 = buff( 234) 2561 = buff( 234) 2627 = buff( 257) 2631 = buff( 257) 2635 = buff( 265) 2639 = buff( 265) 2643 = buff( 273) 2647 = buff( 273) 2651 = buff( 281) 2655 = buff( 281) 2721 = buff( 335) 2734 = buff( 335) 2816 = buff( 206) 2822 = and( 27, 31) 2826 = buff( 1) 2828 = buff( 2358) 2882 = buff( 293) 2886 = buff( 302) 2890 = buff( 308) 2894 = buff( 308) 2898 = buff( 316) 2902 = buff( 316) 2948 = buff( 324) 2952 = buff( 324) 2956 = buff( 341) 2960 = buff( 341) 2964 = buff( 351) 2968 = buff( 351) 3024 = buff( 257) 3028 = buff( 257) 3032 = buff( 265) 3036 = buff( 265) 3040 = buff( 273) 3044 = buff( 273) 3048 = buff( 281) 3052 = buff( 281) 3092 = buff( 332) 3105 = buff( 332) 3175 = buff( 549) 3176 = and( 31, 27) 3181 = not( 2358) 3204 = buff( 324) 3208 = buff( 324) 3212 = buff( 341) 3216 = buff( 341) 3220 = buff( 351) 3224 = buff( 351) 3256 = buff( 293) 3260 = buff( 302) 3264 = buff( 308) 3268 = buff( 308) 3272 = buff( 316) 3276 = buff( 316) 3302 = buff( 361) 3314 = buff( 361) 3354 = buff( 210) 3358 = buff( 210) 3362 = buff( 218) 3366 = buff( 218) 3370 = buff( 226) 3374 = buff( 226) 3378 = buff( 234) 3382 = buff( 234) 3440 = not( 324) 3554 = buff( 242) 3555 = buff( 242) 3556 = buff( 254) 3558 = buff( 4088) 3582 = buff( 4087) 3616 = buff( 4092) 3628 = buff( 4091) 3660 = buff( 4089) 3684 = buff( 4090) 3721 = not( 3717) 3728 = not( 3724) 3737 = buff( 4091) 3757 = buff( 4092) 3795 = buff( 4091) 3815 = buff( 4092) 3972 = buff( 4091) 3991 = buff( 4092) 4030 = buff( 4091) 4049 = buff( 4092) 4110 = buff( 299) 4119 = buff( 446) 4127 = buff( 457) 4135 = buff( 468) 4143 = buff( 422) 4151 = buff( 435) 4159 = buff( 389) 4167 = buff( 400) 4175 = buff( 411) 4183 = buff( 374) 4188 = buff( 4) 4276 = buff( 446) 4284 = buff( 457) 4292 = buff( 468) 4300 = buff( 435) 4308 = buff( 389) 4316 = buff( 400) 4324 = buff( 411) 4332 = buff( 422) 4340 = buff( 374) 4631 = buff( 479) 4639 = buff( 490) 4647 = buff( 503) 4655 = buff( 514) 4663 = buff( 523) 4671 = buff( 534) 4676 = buff( 54) 4764 = buff( 479) 4772 = buff( 503) 4780 = buff( 514) 4788 = buff( 523) 4796 = buff( 534) 4804 = buff( 490) 5082 = buff( 361) 5085 = buff( 369) 5090 = buff( 341) 5093 = buff( 351) 5098 = buff( 308) 5101 = buff( 316) 5108 = buff( 293) 5111 = buff( 302) 5332 = buff( 281) 5335 = buff( 289) 5340 = buff( 265) 5343 = buff( 273) 5348 = buff( 234) 5351 = buff( 257) 5356 = buff( 218) 5359 = buff( 226) 5369 = buff( 210) 634 = not( 633) 815 = and( 136, 814) 845 = not( 844) 847 = not( 846) 926 = buff( 1697) 923 = buff( 1701) 921 = buff( 2826) 2979 = and( 3553, 514) 2999 = or( 3547, 514) 892 = buff( 3175) 887 = buff( 4110) 606 = not( 3175) 1580 = and( 170, 1528, 1552) 1586 = and( 173, 1528, 1552) 1592 = and( 167, 1528, 1552) 1598 = and( 164, 1528, 1552) 1604 = and( 161, 1528, 1552) 656 = nand( 2822, 140) 1668 = and( 185, 1609, 1633) 1674 = and( 158, 1609, 1633) 1680 = and( 152, 1609, 1633) 1686 = and( 146, 1609, 1633) 2254 = and( 170, 2203, 2226) 2260 = and( 173, 2203, 2226) 2266 = and( 167, 2203, 2226) 2272 = and( 164, 2203, 2226) 2278 = and( 161, 2203, 2226) 2339 = and( 185, 2281, 2304) 2345 = and( 158, 2281, 2304) 2351 = and( 152, 2281, 2304) 2357 = and( 146, 2281, 2304) 711 = and( 106, 3660, 3684) 721 = and( 61, 2418, 2442) 726 = and( 106, 3558, 3582) 731 = and( 49, 3558, 3582) 736 = and( 103, 3558, 3582) 741 = and( 40, 3558, 3582) 746 = and( 37, 3558, 3582) 751 = and( 20, 2418, 2442) 756 = and( 17, 2418, 2442) 761 = and( 70, 2418, 2442) 766 = and( 64, 2418, 2442) 771 = and( 49, 3660, 3684) 776 = and( 103, 3660, 3684) 781 = and( 40, 3660, 3684) 786 = and( 37, 3660, 3684) 791 = and( 20, 2476, 2500) 796 = and( 17, 2476, 2500) 801 = and( 70, 2476, 2500) 806 = and( 64, 2476, 2500) 809 = not( 2822) 3734 = and( 123, 3728, 3717) 842 = and( 3795, 3815) 858 = and( 61, 2476, 2500) 881 = and( 3737, 3757) 4123 = not( 4119) 4131 = not( 4127) 4139 = not( 4135) 4147 = not( 4143) 4155 = not( 4151) 4163 = not( 4159) 4171 = not( 4167) 4179 = not( 4175) 4187 = not( 4183) 4194 = not( 4188) 4282 = not( 4276) 4290 = not( 4284) 4298 = not( 4292) 4306 = not( 4300) 4314 = not( 4308) 4322 = not( 4316) 4330 = not( 4324) 4338 = not( 4332) 4346 = not( 4340) 1526 = buff( 1697) 1540 = not( 1528) 1564 = not( 1552) 1606 = buff( 1697) 1621 = not( 1609) 1645 = not( 1633) 1661 = and( 179, 1609, 1633) 1688 = buff( 2826) 4635 = not( 4631) 4643 = not( 4639) 4651 = not( 4647) 4659 = not( 4655) 4667 = not( 4663) 4675 = not( 4671) 4682 = not( 4676) 4770 = not( 4764) 4778 = not( 4772) 4786 = not( 4780) 4794 = not( 4788) 4802 = not( 4796) 4810 = not( 4804) 2202 = buff( 1698) 2215 = not( 2203) 2238 = not( 2226) 2279 = buff( 1698) 2293 = not( 2281) 2316 = not( 2304) 2332 = and( 179, 2281, 2304) 2430 = not( 2418) 2454 = not( 2442) 2488 = not( 2476) 2512 = not( 2500) 2536 = not( 2533) 2540 = not( 2537) 2544 = not( 2541) 2548 = not( 2545) 2552 = not( 2549) 2556 = not( 2553) 2560 = not( 2557) 2564 = not( 2561) 2566 = and( 3553, 457, 2537) 2572 = and( 3553, 468, 2545) 2578 = and( 3553, 422, 2553) 2584 = and( 3553, 435, 2561) 2590 = and( 3547, 2533) 2595 = and( 3547, 2541) 2600 = and( 3547, 2549) 2605 = and( 3547, 2557) 2630 = not( 2627) 2634 = not( 2631) 2638 = not( 2635) 2642 = not( 2639) 2646 = not( 2643) 2650 = not( 2647) 2654 = not( 2651) 2658 = not( 2655) 2660 = and( 3553, 389, 2631) 2666 = and( 3553, 400, 2639) 2672 = and( 3553, 411, 2647) 2678 = and( 3553, 374, 2655) 2684 = and( 3547, 2627) 2689 = and( 3547, 2635) 2694 = and( 3547, 2643) 2699 = and( 3547, 2651) 2728 = not( 2721) 2741 = not( 2734) 2748 = and( 292, 2721) 2750 = and( 288, 2721) 2752 = and( 280, 2721) 2754 = and( 272, 2721) 2756 = and( 264, 2721) 2758 = and( 241, 2734) 2760 = and( 233, 2734) 2762 = and( 225, 2734) 2764 = and( 217, 2734) 2766 = and( 209, 2734) 2827 = buff( 1701) 2838 = not( 2828) 2847 = not( 2822) 2885 = not( 2882) 2889 = not( 2886) 2893 = not( 2890) 2897 = not( 2894) 2901 = not( 2898) 2905 = not( 2902) 2906 = and( 2393, 2886) 2909 = and( 2393, 479, 2894) 2913 = and( 2393, 490, 2902) 2918 = and( 3554, 2882) 2922 = and( 3554, 2890) 2927 = and( 3554, 2898) 2951 = not( 2948) 2955 = not( 2952) 2959 = not( 2956) 2963 = not( 2960) 2967 = not( 2964) 2971 = not( 2968) 2973 = and( 3553, 503, 2952) 2980 = not( 2979) 2982 = and( 3553, 523, 2960) 2988 = and( 3553, 534, 2968) 2994 = and( 3547, 2948) 3001 = and( 3547, 2956) 3006 = and( 3547, 2964) 3027 = not( 3024) 3031 = not( 3028) 3035 = not( 3032) 3039 = not( 3036) 3043 = not( 3040) 3047 = not( 3044) 3051 = not( 3048) 3055 = not( 3052) 3056 = and( 2393, 389, 3028) 3060 = and( 2393, 400, 3036) 3064 = and( 2393, 411, 3044) 3068 = and( 2393, 374, 3052) 3073 = and( 3554, 3024) 3078 = and( 3554, 3032) 3083 = and( 3554, 3040) 3088 = and( 3554, 3048) 3099 = not( 3092) 3112 = not( 3105) 3119 = and( 372, 3092) 3121 = and( 366, 3092) 3123 = and( 358, 3092) 3125 = and( 348, 3092) 3126 = and( 338, 3092) 3128 = and( 331, 3105) 3130 = and( 323, 3105) 3132 = and( 315, 3105) 3134 = and( 307, 3105) 3136 = and( 299, 3105) 3187 = not( 3181) 3193 = and( 83, 3181) 3196 = and( 86, 3181) 3199 = and( 88, 3181) 3202 = and( 88, 3181) 3207 = not( 3204) 3211 = not( 3208) 3215 = not( 3212) 3219 = not( 3216) 3223 = not( 3220) 3227 = not( 3224) 3228 = and( 2405, 503, 3208) 3232 = and( 2405, 514) 3234 = and( 2405, 523, 3216) 3238 = and( 2405, 534, 3224) 3243 = and( 3555, 3204) 3247 = or( 3555, 514) 3249 = and( 3555, 3212) 3253 = and( 3555, 3220) 3259 = not( 3256) 3263 = not( 3260) 3267 = not( 3264) 3271 = not( 3268) 3275 = not( 3272) 3279 = not( 3276) 3280 = and( 2405, 3260) 3283 = and( 2405, 479, 3268) 3287 = and( 2405, 490, 3276) 3292 = and( 3555, 3256) 3295 = and( 3555, 3264) 3299 = and( 3555, 3272) 3305 = not( 3302) 3306 = buff( 2816) 3310 = buff( 2816) 3317 = not( 3314) 3318 = buff( 2816) 3322 = buff( 2816) 3326 = and( 2405, 3302) 3333 = and( 2405, 3314) 3357 = not( 3354) 3361 = not( 3358) 3365 = not( 3362) 3369 = not( 3366) 3373 = not( 3370) 3377 = not( 3374) 3381 = not( 3378) 3385 = not( 3382) 3386 = and( 2393, 457, 3358) 3390 = and( 2393, 468, 3366) 3394 = and( 2393, 422, 3374) 3398 = and( 2393, 435, 3382) 3403 = and( 3554, 3354) 3408 = and( 3554, 3362) 3413 = and( 3554, 3370) 3418 = and( 3554, 3378) 5088 = not( 5082) 5089 = not( 5085) 5096 = not( 5090) 5097 = not( 5093) 3489 = buff( 3440) 3493 = buff( 3440) 3570 = not( 3558) 3594 = not( 3582) 3622 = not( 3616) 3632 = not( 3628) 3637 = and( 97, 3616) 3640 = and( 94, 3616) 3643 = and( 97, 3616) 3646 = and( 94, 3616) 3672 = not( 3660) 3696 = not( 3684) 3745 = not( 3737) 3765 = not( 3757) 3803 = not( 3795) 3823 = not( 3815) 5338 = not( 5332) 5339 = not( 5335) 5346 = not( 5340) 5347 = not( 5343) 5354 = not( 5348) 5355 = not( 5351) 3979 = not( 3972) 3998 = not( 3991) 4037 = not( 4030) 4056 = not( 4049) 4094 = buff( 4110) 5104 = not( 5098) 5105 = not( 5101) 5114 = not( 5108) 5115 = not( 5111) 5362 = not( 5356) 5363 = not( 5359) 5366 = buff( 2816) 5373 = not( 5369) 993 = buff( 1688) 978 = buff( 1688) 949 = buff( 1688) 939 = buff( 1688) 2568 = and( 457, 3551, 2540) 2574 = and( 468, 3551, 2548) 2580 = and( 422, 3551, 2556) 2586 = and( 435, 3551, 2564) 2592 = and( 3549, 2536) 2597 = and( 3549, 2544) 2602 = and( 3549, 2552) 2607 = and( 3549, 2560) 2662 = and( 389, 3551, 2634) 2668 = and( 400, 3551, 2642) 2674 = and( 411, 3551, 2650) 2680 = and( 374, 3551, 2658) 2686 = and( 3549, 2630) 2691 = and( 3549, 2638) 2696 = and( 3549, 2646) 2701 = and( 3549, 2654) 2907 = and( 2370, 2889) 2910 = and( 479, 2370, 2897) 2914 = and( 490, 2370, 2905) 2920 = and( 3556, 2885) 2924 = and( 3556, 2893) 2929 = and( 3556, 2901) 2975 = and( 503, 3551, 2955) 2984 = and( 523, 3551, 2963) 2990 = and( 534, 3551, 2971) 2996 = and( 3549, 2951) 3003 = and( 3549, 2959) 3008 = and( 3549, 2967) 3015 = and( 2980, 2999) 3057 = and( 389, 2370, 3031) 3061 = and( 400, 2370, 3039) 3065 = and( 411, 2370, 3047) 3069 = and( 374, 2370, 3055) 3075 = and( 3556, 3027) 3080 = and( 3556, 3035) 3085 = and( 3556, 3043) 3090 = and( 3556, 3051) 3229 = and( 503, 2382, 3211) 3233 = not( 3232) 3235 = and( 523, 2382, 3219) 3239 = and( 534, 2382, 3227) 3244 = and( 2361, 3207) 3250 = and( 2361, 3215) 3254 = and( 2361, 3223) 3281 = and( 2382, 3263) 3284 = and( 479, 2382, 3271) 3288 = and( 490, 2382, 3279) 3293 = and( 2361, 3259) 3296 = and( 2361, 3267) 3300 = and( 2361, 3275) 3327 = and( 2382, 3305) 3334 = and( 2382, 3317) 3387 = and( 457, 2370, 3361) 3391 = and( 468, 2370, 3369) 3395 = and( 422, 2370, 3377) 3399 = and( 435, 2370, 3385) 3405 = and( 3556, 3357) 3410 = and( 3556, 3365) 3415 = and( 3556, 3373) 3420 = and( 3556, 3381) 3422 = nand( 5085, 5088) 3423 = nand( 5082, 5089) 3431 = nand( 5093, 5096) 3432 = nand( 5090, 5097) 3895 = nand( 5335, 5338) 3896 = nand( 5332, 5339) 3904 = nand( 5343, 5346) 3905 = nand( 5340, 5347) 3913 = nand( 5351, 5354) 3914 = nand( 5348, 5355) 889 = buff( 4094) 5106 = nand( 5101, 5104) 5107 = nand( 5098, 5105) 5116 = nand( 5111, 5114) 5117 = nand( 5108, 5115) 5364 = nand( 5359, 5362) 5365 = nand( 5356, 5363) 593 = not( 4094) 2880 = and( 2838, 2847) 2881 = and( 2828, 2847) 1579 = and( 200, 1540, 1552) 1585 = and( 203, 1540, 1552) 1591 = and( 197, 1540, 1552) 1597 = and( 194, 1540, 1552) 1603 = and( 191, 1540, 1552) 1667 = and( 182, 1621, 1633) 1673 = and( 188, 1621, 1633) 1679 = and( 155, 1621, 1633) 1685 = and( 149, 1621, 1633) 2876 = and( 2838, 2847) 2877 = and( 2828, 2847) 2253 = and( 200, 2215, 2226) 2259 = and( 203, 2215, 2226) 2265 = and( 197, 2215, 2226) 2271 = and( 194, 2215, 2226) 2277 = and( 191, 2215, 2226) 2338 = and( 182, 2293, 2304) 2344 = and( 188, 2293, 2304) 2350 = and( 155, 2293, 2304) 2356 = and( 149, 2293, 2304) 2868 = and( 2838, 2847) 2869 = and( 2828, 2847) 710 = and( 109, 3672, 3684) 2872 = and( 2838, 2847) 2873 = and( 2828, 2847) 720 = and( 11, 2430, 2442) 725 = and( 109, 3570, 3582) 730 = and( 46, 3570, 3582) 735 = and( 100, 3570, 3582) 740 = and( 91, 3570, 3582) 745 = and( 43, 3570, 3582) 750 = and( 76, 2430, 2442) 755 = and( 73, 2430, 2442) 760 = and( 67, 2430, 2442) 765 = and( 14, 2430, 2442) 770 = and( 46, 3672, 3684) 775 = and( 100, 3672, 3684) 780 = and( 91, 3672, 3684) 785 = and( 43, 3672, 3684) 790 = and( 76, 2488, 2500) 795 = and( 73, 2488, 2500) 800 = and( 67, 2488, 2500) 805 = and( 14, 2488, 2500) 841 = and( 120, 3803, 3815) 857 = and( 11, 2488, 2500) 880 = and( 118, 3745, 3757) 1660 = and( 176, 1621, 1633) 2331 = and( 176, 2293, 2304) 2569 = or( 2566, 2568) 2575 = or( 2572, 2574) 2581 = or( 2578, 2580) 2587 = or( 2584, 2586) 2593 = or( 2590, 2592, 457) 2598 = or( 2595, 2597, 468) 2603 = or( 2600, 2602, 422) 2608 = or( 2605, 2607, 435) 2663 = or( 2660, 2662) 2669 = or( 2666, 2668) 2675 = or( 2672, 2674) 2681 = or( 2678, 2680) 2687 = or( 2684, 2686, 389) 2692 = or( 2689, 2691, 400) 2697 = or( 2694, 2696, 411) 2702 = or( 2699, 2701, 374) 2747 = and( 289, 2728) 2749 = and( 281, 2728) 2751 = and( 273, 2728) 2753 = and( 265, 2728) 2755 = and( 257, 2728) 2757 = and( 234, 2741) 2759 = and( 226, 2741) 2761 = and( 218, 2741) 2763 = and( 210, 2741) 2765 = and( 206, 2741) 2857 = not( 2847) 2908 = or( 2906, 2907) 2911 = or( 2909, 2910) 2915 = or( 2913, 2914) 2925 = or( 2922, 2924, 479) 2930 = or( 2927, 2929, 490) 2933 = or( 2918, 2920) 2976 = or( 2973, 2975) 2985 = or( 2982, 2984) 2991 = or( 2988, 2990) 2997 = or( 2994, 2996, 503) 3004 = or( 3001, 3003, 523) 3009 = or( 3006, 3008, 534) 3058 = or( 3056, 3057) 3062 = or( 3060, 3061) 3066 = or( 3064, 3065) 3070 = or( 3068, 3069) 3076 = or( 3073, 3075, 389) 3081 = or( 3078, 3080, 400) 3086 = or( 3083, 3085, 411) 3091 = or( 3088, 3090, 374) 3118 = and( 369, 3099) 3120 = and( 361, 3099) 3122 = and( 351, 3099) 3124 = and( 341, 3099) 3127 = and( 324, 3112) 3129 = and( 316, 3112) 3131 = and( 308, 3112) 3133 = and( 302, 3112) 3135 = and( 293, 3112) 3147 = or( 3099, 3126) 3192 = and( 83, 3187) 3195 = and( 87, 3187) 3198 = and( 34, 3187) 3201 = and( 34, 3187) 3230 = or( 3228, 3229) 3236 = or( 3234, 3235) 3240 = or( 3238, 3239) 3245 = or( 3243, 3244, 503) 3251 = or( 3249, 3250, 523) 3255 = or( 3253, 3254, 534) 3282 = or( 3280, 3281) 3285 = or( 3283, 3284) 3289 = or( 3287, 3288) 3297 = or( 3295, 3296, 479) 3301 = or( 3299, 3300, 490) 3309 = not( 3306) 3313 = not( 3310) 3321 = not( 3318) 3325 = not( 3322) 3328 = or( 3326, 3327) 3329 = and( 2405, 446, 3310) 3335 = or( 3333, 3334) 3336 = and( 2405, 446, 3322) 3341 = and( 3555, 3306) 3345 = and( 3555, 3318) 3388 = or( 3386, 3387) 3392 = or( 3390, 3391) 3396 = or( 3394, 3395) 3400 = or( 3398, 3399) 3406 = or( 3403, 3405, 457) 3411 = or( 3408, 3410, 468) 3416 = or( 3413, 3415, 422) 3421 = or( 3418, 3420, 435) 3424 = nand( 3422, 3423) 3433 = nand( 3431, 3432) 3492 = not( 3489) 3496 = not( 3493) 3780 = and( 117, 3745, 3757) 3783 = and( 126, 3745, 3757) 3786 = and( 127, 3745, 3757) 3789 = and( 128, 3745, 3757) 3838 = and( 131, 3803, 3815) 3841 = and( 129, 3803, 3815) 3844 = and( 119, 3803, 3815) 3847 = and( 130, 3803, 3815) 3897 = nand( 3895, 3896) 3906 = nand( 3904, 3905) 3915 = nand( 3913, 3914) 4011 = and( 122, 3979, 3991) 4014 = and( 113, 3979, 3991) 4017 = and( 53, 3979, 3991) 4020 = and( 114, 3979, 3991) 4023 = and( 115, 3979, 3991) 4069 = and( 52, 4037, 4049) 4072 = and( 112, 4037, 4049) 4075 = and( 116, 4037, 4049) 4078 = and( 121, 4037, 4049) 4081 = and( 123, 4037, 4049) 5206 = nand( 5116, 5117) 5209 = nand( 5106, 5107) 5307 = and( 3233, 3247) 5322 = or( 3292, 3293) 5372 = not( 5366) 5375 = nand( 5366, 5373) 5399 = nand( 5364, 5365) 2813 = not( 3015) 3197 = or( 3195, 3196) 3200 = or( 3198, 3199) 3203 = or( 3201, 3202) 3194 = or( 3192, 3193) 2570 = not( 2569) 2576 = not( 2575) 2582 = not( 2581) 2588 = not( 2587) 2664 = not( 2663) 2670 = not( 2669) 2676 = not( 2675) 2682 = not( 2681) 2767 = or( 2749, 2750) 2772 = or( 2751, 2752) 2776 = or( 2753, 2754) 2780 = or( 2755, 2756) 2784 = or( 2757, 2758) 2788 = or( 2759, 2760) 2794 = or( 2761, 2762) 2798 = or( 2763, 2764) 2802 = or( 2765, 2766) 2912 = not( 2911) 2916 = not( 2915) 2936 = not( 2908) 2977 = not( 2976) 2986 = not( 2985) 2992 = not( 2991) 3059 = not( 3058) 3063 = not( 3062) 3067 = not( 3066) 3071 = not( 3070) 3137 = or( 3120, 3121) 3139 = or( 3122, 3123) 3143 = or( 3124, 3125) 3151 = or( 3127, 3128) 3155 = or( 3129, 3130) 3161 = or( 3131, 3132) 3165 = or( 3133, 3134) 3167 = or( 3135, 3136) 3231 = not( 3230) 3237 = not( 3236) 3241 = not( 3240) 3286 = not( 3285) 3290 = not( 3289) 3330 = and( 446, 2382, 3313) 3337 = and( 446, 2382, 3325) 3342 = and( 2361, 3309) 3346 = and( 2361, 3321) 3348 = not( 3328) 3352 = not( 3335) 3389 = not( 3388) 3393 = not( 3392) 3397 = not( 3396) 3401 = not( 3400) 3845 = and( 3015, 3803, 3823) 5126 = or( 3118, 3119) 5178 = or( 2747, 2748) 5325 = not( 3282) 5374 = nand( 5369, 5372) 2810 = not( 2933) 635 = and( 3197, 3176) 2878 = and( 24, 2838, 2857) 2879 = and( 25, 2828, 2857) 2874 = and( 26, 2838, 2857) 2875 = and( 81, 2828, 2857) 703 = and( 3200, 3176) 2866 = and( 79, 2838, 2857) 2867 = and( 23, 2828, 2857) 2870 = and( 82, 2838, 2857) 2871 = and( 80, 2828, 2857) 716 = and( 3203, 3176) 819 = and( 3194, 3176) 1789 = and( 3147, 514) 2036 = and( 514, 3147) 2611 = and( 2570, 2593) 2615 = and( 2576, 2598) 2619 = and( 2582, 2603) 2623 = and( 2588, 2608) 2705 = and( 2664, 2687) 2709 = and( 2670, 2692) 2713 = and( 2676, 2697) 2717 = and( 2682, 2702) 2939 = and( 2912, 2925) 2942 = and( 2916, 2930) 2945 = buff( 2933) 3012 = and( 2977, 2997) 3018 = and( 2986, 3004) 3021 = and( 2992, 3009) 3331 = or( 3329, 3330) 3338 = or( 3336, 3337) 3343 = or( 3341, 3342, 446) 3347 = or( 3345, 3346, 446) 3428 = not( 3424) 3437 = not( 3433) 3514 = and( 3433, 3424, 3489) 3836 = and( 3352, 3803, 3823) 3852 = and( 3071, 3091) 5311 = not( 5307) 3901 = not( 3897) 3910 = not( 3906) 3934 = buff( 3915) 3938 = buff( 3915) 4652 = buff( 3147) 4783 = buff( 3147) 5137 = buff( 3147) 5212 = not( 5206) 5213 = not( 5209) 5260 = and( 3063, 3081) 5263 = and( 3067, 3086) 5268 = and( 3401, 3421) 5271 = and( 3059, 3076) 5276 = and( 3393, 3411) 5279 = and( 3397, 3416) 5289 = and( 3389, 3406) 5296 = and( 3237, 3251) 5299 = and( 3241, 3255) 5304 = and( 3231, 3245) 5312 = and( 3286, 3297) 5315 = and( 3290, 3301) 5328 = not( 5322) 5396 = nand( 5374, 5375) 5403 = not( 5399) 1286 = and( 446, 2802) 2809 = not( 2936) 597 = not( 3348) 1031 = and( 2802, 446) 636 = not( 635) 637 = or( 2878, 2879, 2880, 2881) 671 = or( 2874, 2875, 2876, 2877) 704 = not( 703) 705 = or( 2866, 2867, 2868, 2869) 713 = or( 2870, 2871, 2872, 2873) 717 = not( 716) 820 = not( 819) 1046 = and( 2798, 457) 1064 = and( 2794, 468) 1071 = and( 422, 2788) 1097 = and( 2784, 435) 1111 = and( 2780, 389) 1128 = and( 2776, 400) 1145 = and( 2772, 411) 1160 = and( 2767, 374) 1301 = and( 457, 2798) 1318 = and( 468, 2794) 1324 = and( 422, 2788) 1341 = and( 435, 2784) 1359 = and( 389, 2780) 1382 = and( 400, 2776) 1404 = and( 411, 2772) 1412 = and( 374, 2767) 1704 = not( 3167) 1712 = not( 3165) 1724 = buff( 3165) 1742 = and( 3161, 479) 1749 = and( 490, 3155) 1775 = and( 3151, 503) 1806 = and( 3143, 523) 1823 = and( 3139, 534) 1829 = not( 3137) 1837 = buff( 3137) 1958 = not( 3167) 1966 = not( 3165) 1978 = buff( 3165) 1995 = and( 479, 3161) 2001 = and( 490, 3155) 2018 = and( 503, 3151) 2059 = and( 523, 3143) 2081 = and( 534, 3139) 2089 = buff( 3137) 2106 = not( 3137) 3170 = buff( 3167) 3332 = not( 3331) 3339 = not( 3338) 5132 = not( 5126) 5184 = not( 5178) 3853 = not( 3852) 3874 = not( 3348) 4076 = and( 2936, 4037, 4056) 4116 = buff( 2802) 4124 = buff( 2798) 4132 = buff( 2794) 4140 = buff( 2788) 4148 = buff( 2784) 4156 = buff( 2780) 4164 = buff( 2776) 4172 = buff( 2772) 4180 = buff( 2767) 4228 = nor( 422, 2788) 4279 = buff( 2802) 4287 = buff( 2798) 4295 = buff( 2794) 4303 = buff( 2784) 4311 = buff( 2780) 4319 = buff( 2776) 4327 = buff( 2772) 4335 = buff( 2788) 4343 = buff( 2767) 4348 = nor( 422, 2788) 4464 = nor( 374, 2767) 4628 = buff( 3161) 4636 = buff( 3155) 4644 = buff( 3151) 4660 = buff( 3143) 4668 = buff( 3139) 4716 = nor( 490, 3155) 4767 = buff( 3161) 4775 = buff( 3151) 4791 = buff( 3143) 4799 = buff( 3139) 4807 = buff( 3155) 4812 = nor( 490, 3155) 5118 = buff( 3139) 5121 = buff( 3143) 5129 = buff( 3137) 5134 = buff( 3151) 5142 = buff( 3161) 5145 = buff( 3155) 5152 = buff( 3167) 5155 = buff( 3165) 5162 = buff( 2788) 5165 = buff( 2784) 5170 = buff( 2798) 5173 = buff( 2794) 5181 = buff( 2802) 5186 = buff( 2772) 5189 = buff( 2767) 5196 = buff( 2780) 5199 = buff( 2776) 5214 = nand( 5209, 5212) 5215 = nand( 5206, 5213) 5329 = not( 5325) 5330 = nand( 5325, 5328) 2807 = not( 2942) 2808 = not( 2939) 2811 = not( 3021) 2812 = not( 3018) 2814 = not( 3012) 2626 = not( 2623) 2622 = not( 2619) 2618 = not( 2615) 2614 = not( 2611) 2720 = not( 2717) 2716 = not( 2713) 2712 = not( 2709) 2708 = not( 2705) 639 = and( 637, 2827) 673 = and( 671, 2827) 707 = and( 705, 2827) 715 = and( 713, 2827) 3731 = and( 2945, 3728, 3721) 4658 = not( 4652) 1777 = nand( 4652, 4659) 2019 = nand( 4783, 4786) 4787 = not( 4783) 3350 = and( 3332, 3343) 3353 = and( 3339, 3347) 5141 = not( 5137) 3513 = and( 3428, 3433, 3492) 3516 = and( 3424, 3437, 3496) 3517 = and( 3437, 3428, 3493) 3778 = and( 2717, 3745, 3765) 3781 = and( 2713, 3745, 3765) 3784 = and( 2709, 3745, 3765) 3787 = and( 2705, 3745, 3765) 3839 = and( 3021, 3803, 3823) 3842 = and( 3018, 3803, 3823) 5266 = not( 5260) 5267 = not( 5263) 5274 = not( 5268) 5275 = not( 5271) 5302 = not( 5296) 5303 = not( 5299) 5310 = not( 5304) 3891 = nand( 5304, 5311) 3937 = not( 3934) 3941 = not( 3938) 3955 = and( 3906, 3897, 3934) 3958 = and( 3910, 3901, 3938) 4009 = and( 2623, 3979, 3998) 4012 = and( 2619, 3979, 3998) 4015 = and( 2615, 3979, 3998) 4018 = and( 2611, 3979, 3998) 4067 = and( 3012, 4037, 4056) 4070 = and( 2942, 4037, 4056) 4073 = and( 2939, 4037, 4056) 4079 = and( 2945, 4037, 4056) 5239 = nand( 5214, 5215) 5282 = not( 5276) 5283 = not( 5279) 5293 = not( 5289) 5318 = not( 5312) 5319 = not( 5315) 5331 = nand( 5322, 5329) 5402 = not( 5396) 5405 = nand( 5396, 5403) 595 = and( 2807, 2808, 2809, 2810) 596 = and( 2811, 2812, 2813, 2814) 607 = and( 2626, 2622, 2618, 2614) 608 = and( 2720, 2716, 2712, 2708) 1845 = and( 1704, 1724) 1846 = and( 1712, 1704, 1742) 2115 = and( 1958, 1978) 2116 = and( 1966, 1958, 1995) 4122 = not( 4116) 1022 = nand( 4116, 4123) 4130 = not( 4124) 1033 = nand( 4124, 4131) 4138 = not( 4132) 1051 = nand( 4132, 4139) 4146 = not( 4140) 1079 = nand( 4140, 4147) 4154 = not( 4148) 1088 = nand( 4148, 4155) 4162 = not( 4156) 1099 = nand( 4156, 4163) 4170 = not( 4164) 1115 = nand( 4164, 4171) 4178 = not( 4172) 1133 = nand( 4172, 4179) 4186 = not( 4180) 1151 = nand( 4180, 4187) 4234 = not( 4228) 1276 = nand( 4279, 4282) 4283 = not( 4279) 1287 = nand( 4287, 4290) 4291 = not( 4287) 1305 = nand( 4295, 4298) 4299 = not( 4295) 1330 = nand( 4303, 4306) 4307 = not( 4303) 1342 = nand( 4311, 4314) 4315 = not( 4311) 1363 = nand( 4319, 4322) 4323 = not( 4319) 1388 = nand( 4327, 4330) 4331 = not( 4327) 1420 = nand( 4335, 4338) 4339 = not( 4335) 1428 = nand( 4343, 4346) 4347 = not( 4343) 4634 = not( 4628) 1729 = nand( 4628, 4635) 4642 = not( 4636) 1757 = nand( 4636, 4643) 4650 = not( 4644) 1766 = nand( 4644, 4651) 1776 = nand( 4655, 4658) 4666 = not( 4660) 1793 = nand( 4660, 4667) 4674 = not( 4668) 1811 = nand( 4668, 4675) 1849 = and( 1712, 1742) 1852 = and( 1712, 1742) 1875 = and( 54, 1829) 4722 = not( 4716) 1982 = nand( 4767, 4770) 4771 = not( 4767) 2007 = nand( 4775, 4778) 4779 = not( 4775) 2020 = nand( 4780, 4787) 2040 = nand( 4791, 4794) 4795 = not( 4791) 2065 = nand( 4799, 4802) 4803 = not( 4799) 2097 = nand( 4807, 4810) 4811 = not( 4807) 2119 = and( 1966, 1995) 2122 = and( 1966, 1995) 5124 = not( 5118) 5125 = not( 5121) 3452 = nand( 5129, 5132) 5133 = not( 5129) 5140 = not( 5134) 3462 = nand( 5134, 5141) 5168 = not( 5162) 5169 = not( 5165) 5176 = not( 5170) 5177 = not( 5173) 3484 = nand( 5181, 5184) 5185 = not( 5181) 3515 = nor( 3513, 3514) 3518 = nor( 3516, 3517) 3857 = not( 3853) 3860 = nand( 5263, 5266) 3861 = nand( 5260, 5267) 3869 = nand( 5271, 5274) 3870 = nand( 5268, 5275) 3878 = not( 3874) 3881 = nand( 5299, 5302) 3882 = nand( 5296, 5303) 3890 = nand( 5307, 5310) 3954 = and( 3901, 3906, 3937) 3957 = and( 3897, 3910, 3941) 4021 = and( 3353, 3979, 3998) 4099 = not( 3170) 4236 = buff( 1071) 4354 = not( 4348) 4406 = buff( 1324) 4470 = not( 4464) 4552 = buff( 1412) 4679 = buff( 1829) 4687 = buff( 1704) 4695 = buff( 1704) 4703 = buff( 1712) 4711 = buff( 1712) 4724 = buff( 1749) 4818 = not( 4812) 4855 = buff( 1958) 4865 = buff( 1966) 4870 = buff( 2001) 4913 = buff( 1958) 4923 = buff( 1966) 4951 = buff( 2106) 5006 = buff( 2089) 5039 = buff( 2106) 5148 = not( 5142) 5149 = not( 5145) 5158 = not( 5152) 5159 = not( 5155) 5192 = not( 5186) 5193 = not( 5189) 5202 = not( 5196) 5203 = not( 5199) 5284 = nand( 5279, 5282) 5285 = nand( 5276, 5283) 5320 = nand( 5315, 5318) 5321 = nand( 5312, 5319) 5386 = nand( 5330, 5331) 5404 = nand( 5399, 5402) 598 = and( 595, 596, 597) 609 = not( 3350) 1021 = nand( 4119, 4122) 1032 = nand( 4127, 4130) 1050 = nand( 4135, 4138) 1078 = nand( 4143, 4146) 1087 = nand( 4151, 4154) 1098 = nand( 4159, 4162) 1114 = nand( 4167, 4170) 1132 = nand( 4175, 4178) 1150 = nand( 4183, 4186) 1277 = nand( 4276, 4283) 1288 = nand( 4284, 4291) 1306 = nand( 4292, 4299) 1331 = nand( 4300, 4307) 1343 = nand( 4308, 4315) 1364 = nand( 4316, 4323) 1389 = nand( 4324, 4331) 1421 = nand( 4332, 4339) 1429 = nand( 4340, 4347) 1728 = nand( 4631, 4634) 1756 = nand( 4639, 4642) 1765 = nand( 4647, 4650) 1778 = nand( 1776, 1777) 1792 = nand( 4663, 4666) 1810 = nand( 4671, 4674) 1983 = nand( 4764, 4771) 2008 = nand( 4772, 4779) 2021 = nand( 2019, 2020) 2041 = nand( 4788, 4795) 2066 = nand( 4796, 4803) 2098 = nand( 4804, 4811) 3443 = nand( 5121, 5124) 3444 = nand( 5118, 5125) 3453 = nand( 5126, 5133) 3461 = nand( 5137, 5140) 3466 = nand( 5165, 5168) 3467 = nand( 5162, 5169) 3475 = nand( 5173, 5176) 3476 = nand( 5170, 5177) 3485 = nand( 5178, 5185) 5243 = not( 5239) 3862 = nand( 3860, 3861) 3871 = nand( 3869, 3870) 3883 = nand( 3881, 3882) 3892 = nand( 3890, 3891) 3956 = nor( 3954, 3955) 3959 = nor( 3957, 3958) 4756 = or( 1837, 1875) 5150 = nand( 5145, 5148) 5151 = nand( 5142, 5149) 5160 = nand( 5155, 5158) 5161 = nand( 5152, 5159) 5194 = nand( 5189, 5192) 5195 = nand( 5186, 5193) 5204 = nand( 5199, 5202) 5205 = nand( 5196, 5203) 5236 = nand( 3518, 3515) 5286 = buff( 3350) 5379 = nand( 5284, 5285) 5389 = nand( 5320, 5321) 5425 = nand( 5404, 5405) 610 = and( 607, 608, 609) 1023 = nand( 1021, 1022) 1034 = nand( 1032, 1033) 1052 = nand( 1050, 1051) 1080 = nand( 1078, 1079) 1089 = nand( 1087, 1088) 1100 = nand( 1098, 1099) 1116 = nand( 1114, 1115) 1134 = nand( 1132, 1133) 1152 = nand( 1150, 1151) 4242 = not( 4236) 1278 = nand( 1276, 1277) 1289 = nand( 1287, 1288) 1307 = nand( 1305, 1306) 1332 = nand( 1330, 1331) 1344 = nand( 1342, 1343) 1365 = nand( 1363, 1364) 1390 = nand( 1388, 1389) 1422 = nand( 1420, 1421) 1430 = nand( 1428, 1429) 1730 = nand( 1728, 1729) 1758 = nand( 1756, 1757) 1767 = nand( 1765, 1766) 1794 = nand( 1792, 1793) 1812 = nand( 1810, 1811) 1876 = nand( 4679, 4682) 4683 = not( 4679) 4691 = not( 4687) 4699 = not( 4695) 4707 = not( 4703) 4715 = not( 4711) 4730 = not( 4724) 1984 = nand( 1982, 1983) 2009 = nand( 2007, 2008) 2042 = nand( 2040, 2041) 2067 = nand( 2065, 2066) 2099 = nand( 2097, 2098) 4869 = not( 4865) 4927 = not( 4923) 3445 = nand( 3443, 3444) 3454 = nand( 3452, 3453) 3463 = nand( 3461, 3462) 3468 = nand( 3466, 3467) 3477 = nand( 3475, 3476) 3486 = nand( 3484, 3485) 4103 = and( 4099, 3170) 4412 = not( 4406) 4558 = not( 4552) 4859 = not( 4855) 4876 = not( 4870) 4917 = not( 4913) 4955 = not( 4951) 5012 = not( 5006) 5043 = not( 5039) 5216 = nand( 5160, 5161) 5219 = nand( 5150, 5151) 5226 = nand( 5204, 5205) 5229 = nand( 5194, 5195) 5392 = not( 5386) 5422 = nand( 3959, 3956) 1866 = and( 1778, 1806) 1877 = nand( 4676, 4683) 4762 = not( 4756) 2142 = and( 2021, 2059) 2146 = and( 2021, 2059) 5242 = not( 5236) 3532 = nand( 5236, 5243) 3866 = not( 3862) 3887 = not( 3883) 3918 = buff( 3871) 3922 = buff( 3871) 3926 = buff( 3892) 3930 = buff( 3892) 5429 = not( 5425) 4104 = or( 4099, 4103) 4743 = buff( 1778) 4991 = buff( 2021) 5001 = buff( 2021) 5292 = not( 5286) 5295 = nand( 5286, 5293) 5383 = not( 5379) 5393 = not( 5389) 5394 = nand( 5389, 5392) 1439 = and( 1278, 1301) 1440 = and( 1289, 1278, 1318) 1441 = and( 1307, 1278, 1324, 1289) 1847 = and( 1730, 1704, 1749, 1712) 1168 = and( 1023, 1046) 1169 = and( 1034, 1023, 1064) 1170 = and( 1052, 1023, 1071, 1034) 2117 = and( 1984, 1958, 2001, 1966) 1086 = not( 1080) 1166 = and( 1034, 1080, 1052, 1023) 1171 = and( 1034, 1064) 1172 = and( 1052, 1071, 1034) 1173 = and( 1080, 1052, 1034) 1174 = and( 1034, 1064) 1175 = and( 1071, 1052, 1034) 1176 = and( 1052, 1071) 1177 = and( 1080, 1052) 1178 = and( 1052, 1071) 1179 = and( 1100, 1152, 1116, 1089, 1134) 1181 = and( 1089, 1111) 1182 = and( 1100, 1089, 1128) 1183 = and( 1116, 1089, 1145, 1100) 1184 = and( 1134, 1116, 1089, 1160, 1100) 1188 = and( 1100, 1128) 1189 = and( 1116, 1145, 1100) 1190 = and( 1134, 1116, 1160, 1100) 1191 = and( 4, 1152, 1116, 1134, 1100) 1192 = and( 1145, 1116) 1193 = and( 1134, 1116, 1160) 1194 = and( 4, 1152, 1116, 1134) 1195 = and( 1134, 1160) 1196 = and( 4, 1152, 1134) 1197 = and( 4, 1152) 1437 = and( 1422, 1307, 1289, 1278) 1442 = and( 1289, 1318) 1443 = and( 1307, 1324, 1289) 1444 = and( 1422, 1307, 1289) 1445 = and( 1289, 1318) 1446 = and( 1307, 1324, 1289) 1447 = and( 1307, 1324) 1451 = and( 1430, 1390, 1365, 1344, 1332) 1454 = and( 1332, 1359) 1455 = and( 1344, 1332, 1382) 1456 = and( 1365, 1332, 1404, 1344) 1457 = and( 1390, 1365, 1332, 1412, 1344) 1465 = and( 1344, 1382) 1466 = and( 1365, 1404, 1344) 1467 = and( 1390, 1365, 1412, 1344) 1468 = and( 1430, 1365, 1344, 1390) 1469 = and( 1344, 1382) 1470 = and( 1365, 1404, 1344) 1471 = and( 1390, 1365, 1412, 1344) 1472 = and( 1365, 1404) 1473 = and( 1390, 1365, 1412) 1474 = and( 1430, 1365, 1390) 1475 = and( 1365, 1404) 1476 = and( 1390, 1365, 1412) 1477 = and( 1390, 1412) 1481 = and( 1422, 1307) 1482 = and( 1430, 1390) 1764 = not( 1758) 1843 = and( 1712, 1758, 1730, 1704) 1850 = and( 1730, 1749, 1712) 1851 = and( 1758, 1730, 1712) 1853 = and( 1749, 1730, 1712) 1854 = and( 1730, 1749) 1855 = and( 1758, 1730) 1856 = and( 1730, 1749) 1857 = and( 1778, 1829, 1794, 1767, 1812) 1859 = and( 1767, 1789) 1860 = and( 1778, 1767, 1806) 1861 = and( 1794, 1767, 1823, 1778) 1862 = and( 1812, 1794, 1767, 1837, 1778) 1867 = and( 1794, 1823, 1778) 1868 = and( 1812, 1794, 1837, 1778) 1869 = and( 54, 1829, 1794, 1812, 1778) 1870 = and( 1823, 1794) 1871 = and( 1812, 1794, 1837) 1872 = and( 54, 1829, 1794, 1812) 1873 = and( 1812, 1837) 1874 = and( 54, 1829, 1812) 1878 = nand( 1876, 1877) 2113 = and( 2099, 1984, 1966, 1958) 2120 = and( 1984, 2001, 1966) 2121 = and( 2099, 1984, 1966) 2123 = and( 1984, 2001, 1966) 2124 = and( 1984, 2001) 2128 = and( 2106, 2067, 2042, 2021, 2009) 2131 = and( 2009, 2036) 2132 = and( 2021, 2009, 2059) 2133 = and( 2042, 2009, 2081, 2021) 2134 = and( 2067, 2042, 2009, 2089, 2021) 2143 = and( 2042, 2081, 2021) 2144 = and( 2067, 2042, 2089, 2021) 2145 = and( 2106, 2042, 2021, 2067) 2147 = and( 2042, 2081, 2021) 2148 = and( 2067, 2042, 2089, 2021) 2149 = and( 2042, 2081) 2150 = and( 2067, 2042, 2089) 2151 = and( 2106, 2042, 2067) 2152 = and( 2042, 2081) 2153 = and( 2067, 2042, 2089) 2154 = and( 2067, 2089) 2158 = and( 2099, 1984) 2159 = and( 2106, 2067) 3449 = not( 3445) 3458 = not( 3454) 3472 = not( 3468) 3481 = not( 3477) 3497 = buff( 3463) 3501 = buff( 3463) 3505 = buff( 3486) 3509 = buff( 3486) 3531 = nand( 5239, 5242) 5428 = not( 5422) 3967 = nand( 5422, 5429) 4191 = buff( 1152) 4199 = buff( 1023) 4207 = buff( 1023) 4215 = buff( 1034) 4223 = buff( 1034) 4231 = buff( 1052) 4239 = buff( 1052) 4247 = buff( 1089) 4255 = buff( 1100) 4263 = buff( 1116) 4271 = buff( 1134) 4371 = buff( 1422) 4381 = buff( 1307) 4391 = buff( 1278) 4401 = buff( 1289) 4429 = buff( 1422) 4439 = buff( 1307) 4449 = buff( 1278) 4459 = buff( 1289) 4497 = buff( 1430) 4507 = buff( 1390) 4517 = buff( 1332) 4527 = buff( 1365) 4537 = buff( 1344) 4547 = buff( 1344) 4585 = buff( 1430) 4595 = buff( 1390) 4605 = buff( 1332) 4615 = buff( 1365) 4719 = buff( 1730) 4727 = buff( 1730) 4735 = buff( 1767) 4751 = buff( 1794) 4759 = buff( 1812) 4835 = buff( 2099) 4845 = buff( 1984) 4893 = buff( 2099) 4903 = buff( 1984) 4961 = buff( 2067) 4971 = buff( 2009) 4981 = buff( 2042) 5049 = buff( 2067) 5059 = buff( 2009) 5069 = buff( 2042) 5222 = not( 5216) 5223 = not( 5219) 5232 = not( 5226) 5233 = not( 5229) 5294 = nand( 5289, 5292) 5395 = nand( 5386, 5393) 589 = or( 1286, 1439, 1440, 1441) 616 = or( 3167, 1845, 1846, 1847) 619 = or( 1031, 1168, 1169, 1170) 627 = or( 3167, 2115, 2116, 2117) 1185 = or( 1097, 1181, 1182, 1183, 1184) 1448 = or( 1318, 1447) 1458 = or( 1341, 1454, 1455, 1456, 1457) 1478 = or( 1404, 1477) 1863 = or( 1775, 1859, 1860, 1861, 1862) 4747 = not( 4743) 2125 = or( 1995, 2124) 2135 = or( 2018, 2131, 2132, 2133, 2134) 2155 = or( 2081, 2154) 4995 = not( 4991) 5005 = not( 5001) 3533 = nand( 3531, 3532) 3921 = not( 3918) 3925 = not( 3922) 3929 = not( 3926) 3933 = not( 3930) 3943 = and( 3862, 3853, 3918) 3946 = and( 3866, 3857, 3922) 3949 = and( 3883, 3874, 3926) 3952 = and( 3887, 3878, 3930) 3966 = nand( 5425, 5428) 4107 = nand( 4104, 132) 4196 = or( 1046, 1171, 1172, 1173) 4204 = nor( 1046, 1174, 1175) 4212 = or( 1064, 1176, 1177) 4220 = nor( 1064, 1178) 4244 = or( 1111, 1188, 1189, 1190, 1191) 4252 = or( 1128, 1192, 1193, 1194) 4260 = or( 1145, 1195, 1196) 4268 = or( 1160, 1197) 4361 = or( 1301, 1442, 1443, 1444) 4419 = nor( 1301, 1445, 1446) 4467 = or( 1382, 1472, 1473, 1474) 4487 = or( 1359, 1465, 1466, 1467, 1468) 4555 = nor( 1382, 1475, 1476) 4575 = nor( 1359, 1469, 1470, 1471) 4684 = or( 1724, 1849, 1850, 1851) 4692 = nor( 1724, 1852, 1853) 4700 = or( 1742, 1854, 1855) 4708 = nor( 1742, 1856) 4732 = or( 1789, 1866, 1867, 1868, 1869) 4740 = or( 1806, 1870, 1871, 1872) 4748 = or( 1823, 1873, 1874) 4825 = or( 1978, 2119, 2120, 2121) 4883 = nor( 1978, 2122, 2123) 4928 = or( 2059, 2149, 2150, 2151) 4941 = or( 2036, 2142, 2143, 2144, 2145) 5009 = nor( 2059, 2152, 2153) 5029 = nor( 2036, 2146, 2147, 2148) 5224 = nand( 5219, 5222) 5225 = nand( 5216, 5223) 5234 = nand( 5229, 5232) 5235 = nand( 5226, 5233) 5376 = nand( 5294, 5295) 5417 = nand( 5394, 5395) 576 = not( 1878) 588 = and( 1437, 1451) 615 = and( 1843, 1857) 626 = and( 2113, 2128) 632 = and( 1166, 1179) 1198 = nand( 4191, 4194) 4195 = not( 4191) 4203 = not( 4199) 4211 = not( 4207) 4219 = not( 4215) 4227 = not( 4223) 1217 = nand( 4231, 4234) 4235 = not( 4231) 1221 = nand( 4239, 4242) 4243 = not( 4239) 1224 = and( 1179, 4) 4251 = not( 4247) 4259 = not( 4255) 4267 = not( 4263) 4275 = not( 4271) 1453 = not( 1451) 4405 = not( 4401) 4463 = not( 4459) 4541 = not( 4537) 4551 = not( 4547) 1895 = nand( 4719, 4722) 4723 = not( 4719) 1899 = nand( 4727, 4730) 4731 = not( 4727) 1902 = and( 1857, 54) 4739 = not( 4735) 4755 = not( 4751) 1929 = nand( 4759, 4762) 4763 = not( 4759) 2130 = not( 2128) 3500 = not( 3497) 3504 = not( 3501) 3508 = not( 3505) 3512 = not( 3509) 3520 = and( 3454, 3445, 3497) 3523 = and( 3458, 3449, 3501) 3526 = and( 3477, 3468, 3505) 3529 = and( 3481, 3472, 3509) 1002 = buff( 3533) 3837 = and( 1878, 3795, 3823) 3942 = and( 3857, 3862, 3921) 3945 = and( 3853, 3866, 3925) 3948 = and( 3878, 3883, 3929) 3951 = and( 3874, 3887, 3933) 3968 = nand( 3966, 3967) 4375 = not( 4371) 4385 = not( 4381) 4395 = not( 4391) 4433 = not( 4429) 4443 = not( 4439) 4453 = not( 4449) 4501 = not( 4497) 4511 = not( 4507) 4521 = not( 4517) 4531 = not( 4527) 4619 = not( 4615) 4589 = not( 4585) 4599 = not( 4595) 4609 = not( 4605) 4839 = not( 4835) 4849 = not( 4845) 4897 = not( 4893) 4907 = not( 4903) 4965 = not( 4961) 4975 = not( 4971) 4985 = not( 4981) 5073 = not( 5069) 5053 = not( 5049) 5063 = not( 5059) 5247 = nand( 5224, 5225) 5255 = nand( 5234, 5235) 590 = and( 1437, 1458) 617 = and( 1863, 1843) 620 = and( 1185, 1166) 628 = and( 2113, 2135) 3535 = not( 3533) 1199 = nand( 4188, 4195) 4202 = not( 4196) 1204 = nand( 4196, 4203) 4210 = not( 4204) 1207 = nand( 4204, 4211) 4218 = not( 4212) 1211 = nand( 4212, 4219) 4226 = not( 4220) 1214 = nand( 4220, 4227) 1218 = nand( 4228, 4235) 1222 = nand( 4236, 4243) 1225 = or( 1185, 1224) 4250 = not( 4244) 1237 = nand( 4244, 4251) 4258 = not( 4252) 1242 = nand( 4252, 4259) 4266 = not( 4260) 1247 = nand( 4260, 4267) 4274 = not( 4268) 1252 = nand( 4268, 4275) 1462 = not( 1458) 4690 = not( 4684) 1882 = nand( 4684, 4691) 4698 = not( 4692) 1885 = nand( 4692, 4699) 4706 = not( 4700) 1889 = nand( 4700, 4707) 4714 = not( 4708) 1892 = nand( 4708, 4715) 1896 = nand( 4716, 4723) 1900 = nand( 4724, 4731) 1903 = or( 1863, 1902) 4738 = not( 4732) 1915 = nand( 4732, 4739) 4746 = not( 4740) 1920 = nand( 4740, 4747) 4754 = not( 4748) 1925 = nand( 4748, 4755) 1930 = nand( 4756, 4763) 2139 = not( 2135) 3519 = and( 3449, 3454, 3500) 3522 = and( 3445, 3458, 3504) 3525 = and( 3472, 3477, 3508) 3528 = and( 3468, 3481, 3512) 3848 = or( 3836, 3837, 3838) 3944 = nor( 3942, 3943) 3947 = nor( 3945, 3946) 3950 = nor( 3948, 3949) 3953 = nor( 3951, 3952) 5421 = not( 5417) 1004 = buff( 3968) 4111 = and( 4104, 4107) 4112 = and( 4107, 132) 4351 = or( 1448, 1481) 4365 = not( 4361) 4409 = not( 1448) 4423 = not( 4419) 4471 = not( 4467) 4472 = nand( 4467, 4470) 4477 = or( 1478, 1482) 4491 = not( 4487) 4559 = not( 4555) 4560 = nand( 4555, 4558) 4565 = not( 1478) 4579 = not( 4575) 4815 = or( 2125, 2158) 4829 = not( 4825) 4873 = not( 2125) 4887 = not( 4883) 4931 = or( 2155, 2159) 4934 = not( 4928) 4945 = not( 4941) 5013 = not( 5009) 5014 = nand( 5009, 5012) 5019 = not( 2155) 5033 = not( 5029) 5382 = not( 5376) 5385 = nand( 5376, 5383) 591 = or( 589, 590) 618 = or( 616, 617) 621 = or( 619, 620) 629 = or( 627, 628) 3970 = not( 3968) 1200 = nand( 1198, 1199) 1203 = nand( 4199, 4202) 1206 = nand( 4207, 4210) 1210 = nand( 4215, 4218) 1213 = nand( 4223, 4226) 1219 = nand( 1217, 1218) 1223 = nand( 1221, 1222) 1236 = nand( 4247, 4250) 1241 = nand( 4255, 4258) 1246 = nand( 4263, 4266) 1251 = nand( 4271, 4274) 1881 = nand( 4687, 4690) 1884 = nand( 4695, 4698) 1888 = nand( 4703, 4706) 1891 = nand( 4711, 4714) 1897 = nand( 1895, 1896) 1901 = nand( 1899, 1900) 1914 = nand( 4735, 4738) 1919 = nand( 4743, 4746) 1924 = nand( 4751, 4754) 1931 = nand( 1929, 1930) 3521 = nor( 3519, 3520) 3524 = nor( 3522, 3523) 3527 = nor( 3525, 3526) 3530 = nor( 3528, 3529) 5251 = not( 5247) 5259 = not( 5255) 4113 = or( 4111, 4112) 4473 = nand( 4464, 4471) 4561 = nand( 4552, 4559) 5015 = nand( 5006, 5013) 5384 = nand( 5379, 5382) 5406 = nand( 3947, 3944) 5414 = nand( 3953, 3950) 1664 = and( 3848, 1621, 1645) 2335 = and( 3848, 2293, 2316) 718 = and( 3848, 2430, 2454) 822 = not( 3848) 855 = and( 3848, 2488, 2512) 1205 = nand( 1203, 1204) 1208 = nand( 1206, 1207) 1212 = nand( 1210, 1211) 1215 = nand( 1213, 1214) 1220 = not( 1219) 1231 = not( 1225) 1238 = nand( 1236, 1237) 1243 = nand( 1241, 1242) 1248 = nand( 1246, 1247) 1253 = nand( 1251, 1252) 1272 = and( 1225, 1086) 1483 = and( 1462, 1453) 1883 = nand( 1881, 1882) 1886 = nand( 1884, 1885) 1890 = nand( 1888, 1889) 1893 = nand( 1891, 1892) 1898 = not( 1897) 1909 = not( 1903) 1916 = nand( 1914, 1915) 1921 = nand( 1919, 1920) 1926 = nand( 1924, 1925) 1953 = and( 1903, 1764) 2160 = and( 2139, 2130) 4355 = not( 4351) 4356 = nand( 4351, 4354) 4413 = not( 4409) 4414 = nand( 4409, 4412) 4474 = nand( 4472, 4473) 4481 = not( 4477) 4562 = nand( 4560, 4561) 4569 = not( 4565) 4819 = not( 4815) 4820 = nand( 4815, 4818) 4877 = not( 4873) 4878 = nand( 4873, 4876) 4935 = not( 4931) 4936 = nand( 4931, 4934) 5016 = nand( 5014, 5015) 5023 = not( 5019) 5244 = nand( 3524, 3521) 5252 = nand( 3530, 3527) 5409 = nand( 5384, 5385) 566 = not( 1200) 577 = not( 1931) 3733 = and( 4113, 3724, 3721) 1209 = not( 1208) 1216 = not( 1215) 1257 = and( 1225, 1205) 1262 = and( 1225, 1212) 1267 = and( 1225, 1220) 1887 = not( 1886) 1894 = not( 1893) 1935 = and( 1903, 1883) 1943 = and( 1903, 1890) 1948 = and( 1903, 1898) 3779 = and( 1200, 3737, 3765) 3840 = and( 1931, 3795, 3823) 5412 = not( 5406) 5420 = not( 5414) 3964 = nand( 5414, 5421) 4357 = nand( 4348, 4355) 4415 = nand( 4406, 4413) 4821 = nand( 4812, 4819) 4879 = nand( 4870, 4877) 4937 = nand( 4928, 4935) 567 = not( 1253) 568 = not( 1248) 569 = not( 1243) 570 = not( 1238) 578 = not( 1926) 579 = not( 1921) 580 = not( 1916) 1256 = and( 1209, 1231) 1261 = and( 1216, 1231) 1266 = and( 1223, 1231) 1271 = and( 1080, 1231) 1486 = not( 1483) 1934 = and( 1887, 1909) 1942 = and( 1894, 1909) 1947 = and( 1901, 1909) 1952 = and( 1758, 1909) 2163 = not( 2160) 5250 = not( 5244) 3537 = nand( 5244, 5251) 5258 = not( 5252) 3542 = nand( 5252, 5259) 3782 = and( 1253, 3737, 3765) 3785 = and( 1248, 3737, 3765) 3788 = and( 1243, 3737, 3765) 3790 = or( 3778, 3779, 3780) 3843 = and( 1926, 3795, 3823) 3846 = and( 1921, 3795, 3823) 3849 = or( 3839, 3840, 3841) 3960 = nand( 5409, 5412) 5413 = not( 5409) 3963 = nand( 5417, 5420) 4010 = and( 1238, 3972, 3998) 4068 = and( 1916, 4030, 4056) 4358 = nand( 4356, 4357) 4416 = nand( 4414, 4415) 4480 = not( 4474) 4483 = nand( 4474, 4481) 4568 = not( 4562) 4571 = nand( 4562, 4569) 4822 = nand( 4820, 4821) 4880 = nand( 4878, 4879) 4938 = nand( 4936, 4937) 5022 = not( 5016) 5025 = nand( 5016, 5023) 1258 = or( 1256, 1257) 1263 = or( 1261, 1262) 1268 = or( 1266, 1267) 1273 = or( 1271, 1272) 1936 = or( 1934, 1935) 1944 = or( 1942, 1943) 1949 = or( 1947, 1948) 1954 = or( 1952, 1953) 3536 = nand( 5247, 5250) 3541 = nand( 5255, 5258) 3791 = or( 3781, 3782, 3783) 3792 = or( 3784, 3785, 3786) 3793 = or( 3787, 3788, 3789) 3850 = or( 3842, 3843, 3844) 3851 = or( 3845, 3846, 3847) 3961 = nand( 5406, 5413) 3965 = nand( 3963, 3964) 4024 = or( 4009, 4010, 4011) 4082 = or( 4067, 4068, 4069) 4482 = nand( 4477, 4480) 4570 = nand( 4565, 4568) 5024 = nand( 5019, 5022) 1666 = and( 3790, 1609, 1645) 1670 = and( 3849, 1621, 1645) 2337 = and( 3790, 2281, 2316) 2341 = and( 3849, 2293, 2316) 719 = and( 3790, 2418, 2454) 758 = and( 3849, 2430, 2454) 798 = and( 3849, 2488, 2512) 838 = not( 3849) 856 = and( 3790, 2476, 2512) 861 = not( 3790) 3538 = nand( 3536, 3537) 3543 = nand( 3541, 3542) 3962 = nand( 3960, 3961) 4364 = not( 4358) 4367 = nand( 4358, 4365) 4422 = not( 4416) 4425 = nand( 4416, 4423) 4484 = nand( 4482, 4483) 4572 = nand( 4570, 4571) 4828 = not( 4822) 4831 = nand( 4822, 4829) 4886 = not( 4880) 4889 = nand( 4880, 4887) 4944 = not( 4938) 4947 = nand( 4938, 4945) 5026 = nand( 5024, 5025) 571 = not( 1273) 572 = not( 1268) 573 = not( 1263) 574 = not( 1258) 581 = not( 1954) 582 = not( 1949) 583 = not( 1944) 584 = not( 1936) 623 = not( 1936) 1576 = and( 4082, 1540, 1564) 1578 = and( 4024, 1528, 1564) 659 = or( 1664, 1666, 1667, 1668) 1672 = and( 3791, 1609, 1645) 1676 = and( 3850, 1621, 1645) 1678 = and( 3792, 1609, 1645) 1682 = and( 3851, 1621, 1645) 1684 = and( 3793, 1609, 1645) 2250 = and( 4082, 2215, 2238) 2252 = and( 4024, 2203, 2238) 691 = or( 2335, 2337, 2338, 2339) 2343 = and( 3791, 2281, 2316) 2347 = and( 3850, 2293, 2316) 2349 = and( 3792, 2281, 2316) 2353 = and( 3851, 2293, 2316) 2355 = and( 3793, 2281, 2316) 722 = or( 718, 719, 720, 721) 743 = and( 4082, 3570, 3594) 744 = and( 4024, 3558, 3594) 748 = and( 3851, 2430, 2454) 749 = and( 3793, 2418, 2454) 753 = and( 3850, 2430, 2454) 754 = and( 3792, 2418, 2454) 759 = and( 3791, 2418, 2454) 783 = and( 4082, 3672, 3696) 784 = and( 4024, 3660, 3696) 788 = and( 3851, 2488, 2512) 789 = and( 3793, 2476, 2512) 793 = and( 3850, 2488, 2512) 794 = and( 3792, 2476, 2512) 799 = and( 3791, 2476, 2512) 3735 = and( 1936, 3724, 3717) 832 = not( 4082) 834 = not( 3851) 836 = not( 3850) 3835 = not( 3965) 859 = or( 855, 856, 857, 858) 871 = not( 4024) 873 = not( 3793) 875 = not( 3792) 877 = not( 3791) 998 = buff( 3538) 1000 = buff( 3543) 3651 = and( 3965, 3632) 4013 = and( 1273, 3972, 3998) 4016 = and( 1268, 3972, 3998) 4019 = and( 1263, 3972, 3998) 4022 = and( 1258, 3972, 3998) 4071 = and( 1954, 4030, 4056) 4074 = and( 1949, 4030, 4056) 4077 = and( 1944, 4030, 4056) 4080 = and( 1936, 4030, 4056) 4096 = nand( 4113, 1936) 4366 = nand( 4361, 4364) 4424 = nand( 4419, 4422) 4830 = nand( 4825, 4828) 4888 = nand( 4883, 4886) 4946 = nand( 4941, 4944) 575 = and( 566, 567, 568, 569, 570, 571, 572, 573, 574) 585 = and( 576, 577, 578, 579, 580, 581, 582, 583, 584) 640 = or( 1576, 1578, 1579, 1580) 661 = and( 659, 1606) 662 = or( 1670, 1672, 1673, 1674) 665 = or( 1676, 1678, 1679, 1680) 668 = or( 1682, 1684, 1685, 1686) 674 = or( 2250, 2252, 2253, 2254) 693 = and( 691, 2279) 694 = or( 2341, 2343, 2344, 2345) 697 = or( 2347, 2349, 2350, 2351) 700 = or( 2353, 2355, 2356, 2357) 747 = or( 743, 744, 745, 746) 752 = or( 748, 749, 750, 751) 757 = or( 753, 754, 755, 756) 762 = or( 758, 759, 760, 761) 787 = or( 783, 784, 785, 786) 792 = or( 788, 789, 790, 791) 797 = or( 793, 794, 795, 796) 802 = or( 798, 799, 800, 801) 817 = or( 3731, 3733, 3734, 3735) 839 = and( 3835, 3803, 3823) 3540 = not( 3538) 3545 = not( 3543) 3777 = not( 3962) 3648 = and( 3962, 3632) 4025 = or( 4012, 4013, 4014) 4026 = or( 4015, 4016, 4017) 4027 = or( 4018, 4019, 4020) 4028 = or( 4021, 4022, 4023) 4083 = or( 4070, 4071, 4072) 4084 = or( 4073, 4074, 4075) 4085 = or( 4076, 4077, 4078) 4086 = or( 4079, 4080, 4081) 4368 = nand( 4366, 4367) 4426 = nand( 4424, 4425) 4490 = not( 4484) 4493 = nand( 4484, 4491) 4578 = not( 4572) 4581 = nand( 4572, 4579) 4832 = nand( 4830, 4831) 4890 = nand( 4888, 4889) 4948 = nand( 4946, 4947) 5032 = not( 5026) 5035 = nand( 5026, 5033) 642 = and( 640, 1526) 664 = and( 662, 1606) 667 = and( 665, 1606) 670 = and( 668, 1606) 676 = and( 674, 2202) 696 = and( 694, 2279) 699 = and( 697, 2279) 702 = and( 700, 2279) 811 = and( 4113, 4096) 812 = and( 4096, 1936) 818 = and( 816, 817) 853 = and( 562, 3540, 3545, 3535, 3970) 878 = and( 3777, 3745, 3765) 4492 = nand( 4487, 4490) 4580 = nand( 4575, 4578) 5034 = nand( 5029, 5032) 1582 = and( 4083, 1540, 1564) 1584 = and( 4025, 1528, 1564) 1588 = and( 4084, 1540, 1564) 1590 = and( 4026, 1528, 1564) 1594 = and( 4085, 1540, 1564) 1596 = and( 4027, 1528, 1564) 1600 = and( 4086, 1540, 1564) 1602 = and( 4028, 1528, 1564) 2256 = and( 4083, 2215, 2238) 2258 = and( 4025, 2203, 2238) 2262 = and( 4084, 2215, 2238) 2264 = and( 4026, 2203, 2238) 2268 = and( 4085, 2215, 2238) 2270 = and( 4027, 2203, 2238) 2274 = and( 4086, 2215, 2238) 2276 = and( 4028, 2203, 2238) 708 = and( 4086, 3672, 3696) 709 = and( 4028, 3660, 3696) 723 = and( 4086, 3570, 3594) 724 = and( 4028, 3558, 3594) 728 = and( 4085, 3570, 3594) 729 = and( 4027, 3558, 3594) 733 = and( 4084, 3570, 3594) 734 = and( 4026, 3558, 3594) 738 = and( 4083, 3570, 3594) 739 = and( 4025, 3558, 3594) 768 = and( 4085, 3672, 3696) 769 = and( 4027, 3660, 3696) 773 = and( 4084, 3672, 3696) 774 = and( 4026, 3660, 3696) 778 = and( 4083, 3672, 3696) 779 = and( 4025, 3660, 3696) 813 = or( 811, 812) 824 = not( 4086) 826 = not( 4085) 828 = not( 4084) 830 = not( 4083) 854 = and( 852, 853, 245) 863 = not( 4028) 865 = not( 4027) 867 = not( 4026) 869 = not( 4025) 4374 = not( 4368) 4377 = nand( 4368, 4375) 4432 = not( 4426) 4435 = nand( 4426, 4433) 4494 = nand( 4492, 4493) 4582 = nand( 4580, 4581) 4838 = not( 4832) 4841 = nand( 4832, 4839) 4896 = not( 4890) 4899 = nand( 4890, 4897) 4954 = not( 4948) 4957 = nand( 4948, 4955) 5036 = nand( 5034, 5035) 643 = or( 1582, 1584, 1585, 1586) 646 = or( 1588, 1590, 1591, 1592) 649 = or( 1594, 1596, 1597, 1598) 652 = or( 1600, 1602, 1603, 1604) 677 = or( 2256, 2258, 2259, 2260) 680 = or( 2262, 2264, 2265, 2266) 683 = or( 2268, 2270, 2271, 2272) 686 = or( 2274, 2276, 2277, 2278) 712 = or( 708, 709, 710, 711) 727 = or( 723, 724, 725, 726) 732 = or( 728, 729, 730, 731) 737 = or( 733, 734, 735, 736) 742 = or( 738, 739, 740, 741) 772 = or( 768, 769, 770, 771) 777 = or( 773, 774, 775, 776) 782 = or( 778, 779, 780, 781) 4376 = nand( 4371, 4374) 4434 = nand( 4429, 4432) 4840 = nand( 4835, 4838) 4898 = nand( 4893, 4896) 4956 = nand( 4951, 4954) 645 = and( 643, 1526) 648 = and( 646, 1526) 651 = and( 649, 1526) 654 = and( 652, 1526) 679 = and( 677, 2202) 682 = and( 680, 2202) 685 = and( 683, 2202) 688 = and( 686, 2202) 4378 = nand( 4376, 4377) 4436 = nand( 4434, 4435) 4500 = not( 4494) 4503 = nand( 4494, 4501) 4588 = not( 4582) 4591 = nand( 4582, 4589) 4842 = nand( 4840, 4841) 4900 = nand( 4898, 4899) 4958 = nand( 4956, 4957) 5042 = not( 5036) 5045 = nand( 5036, 5043) 4502 = nand( 4497, 4500) 4590 = nand( 4585, 4588) 5044 = nand( 5039, 5042) 4384 = not( 4378) 4387 = nand( 4378, 4385) 4442 = not( 4436) 4445 = nand( 4436, 4443) 4504 = nand( 4502, 4503) 4592 = nand( 4590, 4591) 4848 = not( 4842) 4851 = nand( 4842, 4849) 4906 = not( 4900) 4909 = nand( 4900, 4907) 4964 = not( 4958) 4967 = nand( 4958, 4965) 5046 = nand( 5044, 5045) 4386 = nand( 4381, 4384) 4444 = nand( 4439, 4442) 4850 = nand( 4845, 4848) 4908 = nand( 4903, 4906) 4966 = nand( 4961, 4964) 4388 = nand( 4386, 4387) 4446 = nand( 4444, 4445) 4510 = not( 4504) 4513 = nand( 4504, 4511) 4598 = not( 4592) 4601 = nand( 4592, 4599) 4852 = nand( 4850, 4851) 4910 = nand( 4908, 4909) 4968 = nand( 4966, 4967) 5052 = not( 5046) 5055 = nand( 5046, 5053) 4512 = nand( 4507, 4510) 4600 = nand( 4595, 4598) 5054 = nand( 5049, 5052) 4394 = not( 4388) 4397 = nand( 4388, 4395) 4452 = not( 4446) 4455 = nand( 4446, 4453) 4514 = nand( 4512, 4513) 4602 = nand( 4600, 4601) 4858 = not( 4852) 4861 = nand( 4852, 4859) 4916 = not( 4910) 4919 = nand( 4910, 4917) 4974 = not( 4968) 4977 = nand( 4968, 4975) 5056 = nand( 5054, 5055) 4396 = nand( 4391, 4394) 4454 = nand( 4449, 4452) 4860 = nand( 4855, 4858) 4918 = nand( 4913, 4916) 4976 = nand( 4971, 4974) 4398 = nand( 4396, 4397) 4456 = nand( 4454, 4455) 4520 = not( 4514) 4523 = nand( 4514, 4521) 4608 = not( 4602) 4611 = nand( 4602, 4609) 4862 = nand( 4860, 4861) 4920 = nand( 4918, 4919) 4978 = nand( 4976, 4977) 5062 = not( 5056) 5065 = nand( 5056, 5063) 4522 = nand( 4517, 4520) 4610 = nand( 4605, 4608) 5064 = nand( 5059, 5062) 4404 = not( 4398) 1488 = nand( 4398, 4405) 4462 = not( 4456) 1493 = nand( 4456, 4463) 4868 = not( 4862) 2165 = nand( 4862, 4869) 4926 = not( 4920) 2170 = nand( 4920, 4927) 4524 = nand( 4522, 4523) 4612 = nand( 4610, 4611) 4984 = not( 4978) 4987 = nand( 4978, 4985) 5066 = nand( 5064, 5065) 1487 = nand( 4401, 4404) 1492 = nand( 4459, 4462) 2164 = nand( 4865, 4868) 2169 = nand( 4923, 4926) 4986 = nand( 4981, 4984) 1489 = nand( 1487, 1488) 1494 = nand( 1492, 1493) 2166 = nand( 2164, 2165) 2171 = nand( 2169, 2170) 4530 = not( 4524) 4533 = nand( 4524, 4531) 4618 = not( 4612) 4543 = nand( 4612, 4619) 4988 = nand( 4986, 4987) 5072 = not( 5066) 4997 = nand( 5066, 5073) 4532 = nand( 4527, 4530) 4542 = nand( 4615, 4618) 4996 = nand( 5069, 5072) 1513 = and( 1494, 1462, 1502) 1514 = and( 1489, 1458, 1502) 1515 = and( 1494, 1483, 1497) 1516 = and( 1489, 1486, 1497) 4994 = not( 4988) 2184 = nand( 4988, 4995) 2190 = and( 2171, 2139, 2179) 2191 = and( 2166, 2135, 2179) 2192 = and( 2171, 2160, 2174) 2193 = and( 2166, 2163, 2174) 4534 = nand( 4532, 4533) 4544 = nand( 4542, 4543) 4998 = nand( 4996, 4997) 2183 = nand( 4991, 4994) 4620 = or( 1513, 1514, 1515, 1516) 5074 = or( 2190, 2191, 2192, 2193) 4540 = not( 4534) 1507 = nand( 4534, 4541) 4550 = not( 4544) 1510 = nand( 4544, 4551) 2185 = nand( 2183, 2184) 5004 = not( 4998) 2187 = nand( 4998, 5005) 1506 = nand( 4537, 4540) 1509 = nand( 4547, 4550) 4626 = not( 4620) 2186 = nand( 5001, 5004) 2195 = and( 2174, 2185) 5080 = not( 5074) 1508 = nand( 1506, 1507) 1511 = nand( 1509, 1510) 2188 = nand( 2186, 2187) 1512 = not( 1511) 1518 = and( 1497, 1508) 2189 = not( 2188) 1517 = and( 1512, 1502) 2194 = and( 2189, 2179) 4623 = or( 1517, 1518) 5077 = or( 2194, 2195) 1519 = nand( 4623, 4626) 4627 = not( 4623) 2196 = nand( 5077, 5080) 5081 = not( 5077) 1520 = nand( 4620, 4627) 2197 = nand( 5074, 5081) 1521 = nand( 1519, 1520) 2198 = nand( 2196, 2197) 840 = and( 2198, 3795, 3823) 879 = and( 1521, 3737, 3765) 1524 = not( 1521) 2201 = not( 2198) 843 = or( 839, 840, 841, 842) 882 = or( 878, 879, 880, 881) 3649 = and( 1524, 3628) 3652 = and( 2201, 3628) 3657 = or( 3648, 3649) 3658 = or( 3651, 3652) 3636 = and( 3657, 3622) 3639 = and( 3658, 3622) 3642 = and( 3657, 3622) 3645 = and( 3658, 3622) 3653 = or( 3636, 3637) 3654 = or( 3639, 3640) 3655 = or( 3642, 3643) 3656 = or( 3645, 3646) 763 = and( 3656, 2430, 2454) 764 = and( 3655, 2418, 2454) 803 = and( 3656, 2488, 2512) 804 = and( 3655, 2476, 2512) 1657 = and( 3654, 1621, 1645) 1659 = and( 3653, 1609, 1645) 2328 = and( 3654, 2293, 2316) 2330 = and( 3653, 2281, 2316) 1662 = or( 1657, 1659, 1660, 1661) 2333 = or( 2328, 2330, 2331, 2332) 767 = or( 763, 764, 765, 766) 807 = or( 803, 804, 805, 806) 657 = and( 1662, 1606) 689 = and( 2333, 2279) 658 = not( 657) 690 = not( 689) |
Added c5315/c5315gate.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 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1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 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2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 |
/****************************************************************************
* *
* VERILOG VERSION of ORIGINAL NETLIST for c5315 *
* *
* *
* Generated by: Hakan Yalcin (hyalcin@cadence.com) *
* *
* Sep 16, 1998 *
* *
****************************************************************************/
module c5315g (
L293, L302, L308, L316, L324, L341, L351,
L361, L299, L307, L315, L323, L331, L338, L348,
L358, L366, L206, L210, L218, L226, L234, L257,
L265, L273, L281, L209, L217, L225, L233, L241,
L264, L272, L280, L288, L54, L4, L2174, L1497,
L332, L335, L479, L490, L503, L514, L523, L534,
L446, L457, L468, L422, L435, L389, L400, L411,
L374, L191, L200, L194, L197, L203, L149, L155,
L188, L182, L161, L170, L164, L167, L173, L146,
L152, L158, L185, L109, L43, L46, L100, L91,
L76, L73, L67, L11, L106, L37, L49, L103,
L40, L20, L17, L70, L61, L123, L52, L121,
L116, L112, L130, L119, L129, L131, L115, L122,
L114, L53, L113, L128, L127, L126, L117, L176,
L179, L14, L64, L248, L251, L242, L254, L3552,
L3550, L3546, L3548, L120, L94, L118, L97, L4091,
L4092, L137, L4090, L4089, L4087, L4088, L1694, L1691,
L1690, L1689, L372, L369, L292, L289, L562, L245,
L552, L556, L559, L386, L132, L23, L80, L25,
L81, L79, L82, L24, L26, L86, L88, L87,
L83, L34, L4115, L135, L3717, L3724, L141, L2358,
L31, L27, L545, L549, L3173, L136, L1, L373,
L145, L2824, L140,
L658, L690, L767, L807, L654, L651, L648,
L645, L642, L670, L667, L664, L661, L688, L685,
L682, L679, L676, L702, L699, L696, L693, L727,
L732, L737, L742, L747, L752, L757, L762, L722,
L712, L772, L777, L782, L787, L792, L797, L802,
L859, L824, L826, L832, L828, L830, L834, L836,
L838, L822, L863, L871, L865, L867, L869, L873,
L875, L877, L861, L629, L591, L618, L615, L621,
L588, L626, L632, L843, L882, L585, L575, L598,
L610, L998, L1002, L1000, L1004, L854, L623, L813,
L818, L707, L715, L639, L673, L636, L820, L717,
L704, L593, L594, L602, L809, L611, L599, L612,
L600, L850, L848, L849, L851, L887, L298, L926,
L892, L973, L993, L144, L601, L847, L815, L634,
L810, L845, L656, L923, L939, L921, L978, L949,
L889, L603, L604, L606);
input
L293, L302, L308, L316, L324, L341, L351,
L361, L299, L307, L315, L323, L331, L338, L348,
L358, L366, L206, L210, L218, L226, L234, L257,
L265, L273, L281, L209, L217, L225, L233, L241,
L264, L272, L280, L288, L54, L4, L2174, L1497,
L332, L335, L479, L490, L503, L514, L523, L534,
L446, L457, L468, L422, L435, L389, L400, L411,
L374, L191, L200, L194, L197, L203, L149, L155,
L188, L182, L161, L170, L164, L167, L173, L146,
L152, L158, L185, L109, L43, L46, L100, L91,
L76, L73, L67, L11, L106, L37, L49, L103,
L40, L20, L17, L70, L61, L123, L52, L121,
L116, L112, L130, L119, L129, L131, L115, L122,
L114, L53, L113, L128, L127, L126, L117, L176,
L179, L14, L64, L248, L251, L242, L254, L3552,
L3550, L3546, L3548, L120, L94, L118, L97, L4091,
L4092, L137, L4090, L4089, L4087, L4088, L1694, L1691,
L1690, L1689, L372, L369, L292, L289, L562, L245,
L552, L556, L559, L386, L132, L23, L80, L25,
L81, L79, L82, L24, L26, L86, L88, L87,
L83, L34, L4115, L135, L3717, L3724, L141, L2358,
L31, L27, L545, L549, L3173, L136, L1, L373,
L145, L2824, L140;
output
L658, L690, L767, L807, L654, L651, L648,
L645, L642, L670, L667, L664, L661, L688, L685,
L682, L679, L676, L702, L699, L696, L693, L727,
L732, L737, L742, L747, L752, L757, L762, L722,
L712, L772, L777, L782, L787, L792, L797, L802,
L859, L824, L826, L832, L828, L830, L834, L836,
L838, L822, L863, L871, L865, L867, L869, L873,
L875, L877, L861, L629, L591, L618, L615, L621,
L588, L626, L632, L843, L882, L585, L575, L598,
L610, L998, L1002, L1000, L1004, L854, L623, L813,
L818, L707, L715, L639, L673, L636, L820, L717,
L704, L593, L594, L602, L809, L611, L599, L612,
L600, L850, L848, L849, L851, L887, L298, L926,
L892, L973, L993, L144, L601, L847, L815, L634,
L810, L845, L656, L923, L939, L921, L978, L949,
L889, L603, L604, L606;
buffer U1 ( L141, L144 );
buffer U2 ( L293, L298 );
and2 U3 ( L135, L4115, L4114 );
inv U4 ( L2824, L2825 );
buffer U5 ( L3173, L973 );
inv U6 ( L3546, L3547 );
inv U7 ( L3548, L3549 );
inv U8 ( L3550, L3551 );
inv U9 ( L3552, L3553 );
inv U10 ( L545, L594 );
inv U11 ( L348, L599 );
inv U12 ( L366, L600 );
and2 U13 ( L552, L562, L601 );
inv U14 ( L549, L602 );
inv U15 ( L545, L603 );
inv U16 ( L545, L604 );
inv U17 ( L338, L611 );
inv U18 ( L358, L612 );
nand2 U19 ( L373, L1, L633 );
and2 U20 ( L141, L145, L810 );
inv U21 ( L3173, L814 );
inv U22 ( L4114, L816 );
and2 U23 ( L2825, L27, L844 );
and2 U24 ( L386, L556, L846 );
inv U25 ( L245, L848 );
inv U26 ( L552, L849 );
inv U27 ( L562, L850 );
inv U28 ( L559, L851 );
and4 U29 ( L386, L559, L556, L552, L852 );
inv U30 ( L1497, L1502 );
buffer U31 ( L1689, L1528 );
buffer U32 ( L1690, L1552 );
buffer U33 ( L1689, L1609 );
buffer U34 ( L1690, L1633 );
buffer U35 ( L137, L1697 );
buffer U36 ( L137, L1698 );
buffer U37 ( L141, L1701 );
inv U38 ( L2174, L2179 );
buffer U39 ( L1691, L2203 );
buffer U40 ( L1694, L2226 );
buffer U41 ( L1691, L2281 );
buffer U42 ( L1694, L2304 );
buffer U43 ( L254, L2361 );
buffer U44 ( L251, L2370 );
buffer U45 ( L251, L2382 );
buffer U46 ( L248, L2393 );
buffer U47 ( L248, L2405 );
buffer U48 ( L4088, L2418 );
buffer U49 ( L4087, L2442 );
buffer U50 ( L4089, L2476 );
buffer U51 ( L4090, L2500 );
buffer U52 ( L210, L2533 );
buffer U53 ( L210, L2537 );
buffer U54 ( L218, L2541 );
buffer U55 ( L218, L2545 );
buffer U56 ( L226, L2549 );
buffer U57 ( L226, L2553 );
buffer U58 ( L234, L2557 );
buffer U59 ( L234, L2561 );
buffer U60 ( L257, L2627 );
buffer U61 ( L257, L2631 );
buffer U62 ( L265, L2635 );
buffer U63 ( L265, L2639 );
buffer U64 ( L273, L2643 );
buffer U65 ( L273, L2647 );
buffer U66 ( L281, L2651 );
buffer U67 ( L281, L2655 );
buffer U68 ( L335, L2721 );
buffer U69 ( L335, L2734 );
buffer U70 ( L206, L2816 );
and2 U71 ( L27, L31, L2822 );
buffer U72 ( L1, L2826 );
buffer U73 ( L2358, L2828 );
buffer U74 ( L293, L2882 );
buffer U75 ( L302, L2886 );
buffer U76 ( L308, L2890 );
buffer U77 ( L308, L2894 );
buffer U78 ( L316, L2898 );
buffer U79 ( L316, L2902 );
buffer U80 ( L324, L2948 );
buffer U81 ( L324, L2952 );
buffer U82 ( L341, L2956 );
buffer U83 ( L341, L2960 );
buffer U84 ( L351, L2964 );
buffer U85 ( L351, L2968 );
buffer U86 ( L257, L3024 );
buffer U87 ( L257, L3028 );
buffer U88 ( L265, L3032 );
buffer U89 ( L265, L3036 );
buffer U90 ( L273, L3040 );
buffer U91 ( L273, L3044 );
buffer U92 ( L281, L3048 );
buffer U93 ( L281, L3052 );
buffer U94 ( L332, L3092 );
buffer U95 ( L332, L3105 );
buffer U96 ( L549, L3175 );
and2 U97 ( L31, L27, L3176 );
inv U98 ( L2358, L3181 );
buffer U99 ( L324, L3204 );
buffer U100 ( L324, L3208 );
buffer U101 ( L341, L3212 );
buffer U102 ( L341, L3216 );
buffer U103 ( L351, L3220 );
buffer U104 ( L351, L3224 );
buffer U105 ( L293, L3256 );
buffer U106 ( L302, L3260 );
buffer U107 ( L308, L3264 );
buffer U108 ( L308, L3268 );
buffer U109 ( L316, L3272 );
buffer U110 ( L316, L3276 );
buffer U111 ( L361, L3302 );
buffer U112 ( L361, L3314 );
buffer U113 ( L210, L3354 );
buffer U114 ( L210, L3358 );
buffer U115 ( L218, L3362 );
buffer U116 ( L218, L3366 );
buffer U117 ( L226, L3370 );
buffer U118 ( L226, L3374 );
buffer U119 ( L234, L3378 );
buffer U120 ( L234, L3382 );
inv U121 ( L324, L3440 );
buffer U122 ( L242, L3554 );
buffer U123 ( L242, L3555 );
buffer U124 ( L254, L3556 );
buffer U125 ( L4088, L3558 );
buffer U126 ( L4087, L3582 );
buffer U127 ( L4092, L3616 );
buffer U128 ( L4091, L3628 );
buffer U129 ( L4089, L3660 );
buffer U130 ( L4090, L3684 );
inv U131 ( L3717, L3721 );
inv U132 ( L3724, L3728 );
buffer U133 ( L4091, L3737 );
buffer U134 ( L4092, L3757 );
buffer U135 ( L4091, L3795 );
buffer U136 ( L4092, L3815 );
buffer U137 ( L4091, L3972 );
buffer U138 ( L4092, L3991 );
buffer U139 ( L4091, L4030 );
buffer U140 ( L4092, L4049 );
buffer U141 ( L299, L4110 );
buffer U142 ( L446, L4119 );
buffer U143 ( L457, L4127 );
buffer U144 ( L468, L4135 );
buffer U145 ( L422, L4143 );
buffer U146 ( L435, L4151 );
buffer U147 ( L389, L4159 );
buffer U148 ( L400, L4167 );
buffer U149 ( L411, L4175 );
buffer U150 ( L374, L4183 );
buffer U151 ( L4, L4188 );
buffer U152 ( L446, L4276 );
buffer U153 ( L457, L4284 );
buffer U154 ( L468, L4292 );
buffer U155 ( L435, L4300 );
buffer U156 ( L389, L4308 );
buffer U157 ( L400, L4316 );
buffer U158 ( L411, L4324 );
buffer U159 ( L422, L4332 );
buffer U160 ( L374, L4340 );
buffer U161 ( L479, L4631 );
buffer U162 ( L490, L4639 );
buffer U163 ( L503, L4647 );
buffer U164 ( L514, L4655 );
buffer U165 ( L523, L4663 );
buffer U166 ( L534, L4671 );
buffer U167 ( L54, L4676 );
buffer U168 ( L479, L4764 );
buffer U169 ( L503, L4772 );
buffer U170 ( L514, L4780 );
buffer U171 ( L523, L4788 );
buffer U172 ( L534, L4796 );
buffer U173 ( L490, L4804 );
buffer U174 ( L361, L5082 );
buffer U175 ( L369, L5085 );
buffer U176 ( L341, L5090 );
buffer U177 ( L351, L5093 );
buffer U178 ( L308, L5098 );
buffer U179 ( L316, L5101 );
buffer U180 ( L293, L5108 );
buffer U181 ( L302, L5111 );
buffer U182 ( L281, L5332 );
buffer U183 ( L289, L5335 );
buffer U184 ( L265, L5340 );
buffer U185 ( L273, L5343 );
buffer U186 ( L234, L5348 );
buffer U187 ( L257, L5351 );
buffer U188 ( L218, L5356 );
buffer U189 ( L226, L5359 );
buffer U190 ( L210, L5369 );
inv U191 ( L633, L634 );
and2 U192 ( L136, L814, L815 );
inv U193 ( L844, L845 );
inv U194 ( L846, L847 );
buffer U195 ( L1697, L926 );
buffer U196 ( L1701, L923 );
buffer U197 ( L2826, L921 );
and2 U198 ( L3553, L514, L2979 );
or2 U199 ( L3547, L514, L2999 );
buffer U200 ( L3175, L892 );
buffer U201 ( L4110, L887 );
inv U202 ( L3175, L606 );
and3 U203 ( L170, L1528, L1552, L1580 );
and3 U204 ( L173, L1528, L1552, L1586 );
and3 U205 ( L167, L1528, L1552, L1592 );
and3 U206 ( L164, L1528, L1552, L1598 );
and3 U207 ( L161, L1528, L1552, L1604 );
nand2 U208 ( L2822, L140, L656 );
and3 U209 ( L185, L1609, L1633, L1668 );
and3 U210 ( L158, L1609, L1633, L1674 );
and3 U211 ( L152, L1609, L1633, L1680 );
and3 U212 ( L146, L1609, L1633, L1686 );
and3 U213 ( L170, L2203, L2226, L2254 );
and3 U214 ( L173, L2203, L2226, L2260 );
and3 U215 ( L167, L2203, L2226, L2266 );
and3 U216 ( L164, L2203, L2226, L2272 );
and3 U217 ( L161, L2203, L2226, L2278 );
and3 U218 ( L185, L2281, L2304, L2339 );
and3 U219 ( L158, L2281, L2304, L2345 );
and3 U220 ( L152, L2281, L2304, L2351 );
and3 U221 ( L146, L2281, L2304, L2357 );
and3 U222 ( L106, L3660, L3684, L711 );
and3 U223 ( L61, L2418, L2442, L721 );
and3 U224 ( L106, L3558, L3582, L726 );
and3 U225 ( L49, L3558, L3582, L731 );
and3 U226 ( L103, L3558, L3582, L736 );
and3 U227 ( L40, L3558, L3582, L741 );
and3 U228 ( L37, L3558, L3582, L746 );
and3 U229 ( L20, L2418, L2442, L751 );
and3 U230 ( L17, L2418, L2442, L756 );
and3 U231 ( L70, L2418, L2442, L761 );
and3 U232 ( L64, L2418, L2442, L766 );
and3 U233 ( L49, L3660, L3684, L771 );
and3 U234 ( L103, L3660, L3684, L776 );
and3 U235 ( L40, L3660, L3684, L781 );
and3 U236 ( L37, L3660, L3684, L786 );
and3 U237 ( L20, L2476, L2500, L791 );
and3 U238 ( L17, L2476, L2500, L796 );
and3 U239 ( L70, L2476, L2500, L801 );
and3 U240 ( L64, L2476, L2500, L806 );
inv U241 ( L2822, L809 );
and3 U242 ( L123, L3728, L3717, L3734 );
and2 U243 ( L3795, L3815, L842 );
and3 U244 ( L61, L2476, L2500, L858 );
and2 U245 ( L3737, L3757, L881 );
inv U246 ( L4119, L4123 );
inv U247 ( L4127, L4131 );
inv U248 ( L4135, L4139 );
inv U249 ( L4143, L4147 );
inv U250 ( L4151, L4155 );
inv U251 ( L4159, L4163 );
inv U252 ( L4167, L4171 );
inv U253 ( L4175, L4179 );
inv U254 ( L4183, L4187 );
inv U255 ( L4188, L4194 );
inv U256 ( L4276, L4282 );
inv U257 ( L4284, L4290 );
inv U258 ( L4292, L4298 );
inv U259 ( L4300, L4306 );
inv U260 ( L4308, L4314 );
inv U261 ( L4316, L4322 );
inv U262 ( L4324, L4330 );
inv U263 ( L4332, L4338 );
inv U264 ( L4340, L4346 );
buffer U265 ( L1697, L1526 );
inv U266 ( L1528, L1540 );
inv U267 ( L1552, L1564 );
buffer U268 ( L1697, L1606 );
inv U269 ( L1609, L1621 );
inv U270 ( L1633, L1645 );
and3 U271 ( L179, L1609, L1633, L1661 );
buffer U272 ( L2826, L1688 );
inv U273 ( L4631, L4635 );
inv U274 ( L4639, L4643 );
inv U275 ( L4647, L4651 );
inv U276 ( L4655, L4659 );
inv U277 ( L4663, L4667 );
inv U278 ( L4671, L4675 );
inv U279 ( L4676, L4682 );
inv U280 ( L4764, L4770 );
inv U281 ( L4772, L4778 );
inv U282 ( L4780, L4786 );
inv U283 ( L4788, L4794 );
inv U284 ( L4796, L4802 );
inv U285 ( L4804, L4810 );
buffer U286 ( L1698, L2202 );
inv U287 ( L2203, L2215 );
inv U288 ( L2226, L2238 );
buffer U289 ( L1698, L2279 );
inv U290 ( L2281, L2293 );
inv U291 ( L2304, L2316 );
and3 U292 ( L179, L2281, L2304, L2332 );
inv U293 ( L2418, L2430 );
inv U294 ( L2442, L2454 );
inv U295 ( L2476, L2488 );
inv U296 ( L2500, L2512 );
inv U297 ( L2533, L2536 );
inv U298 ( L2537, L2540 );
inv U299 ( L2541, L2544 );
inv U300 ( L2545, L2548 );
inv U301 ( L2549, L2552 );
inv U302 ( L2553, L2556 );
inv U303 ( L2557, L2560 );
inv U304 ( L2561, L2564 );
and3 U305 ( L3553, L457, L2537, L2566 );
and3 U306 ( L3553, L468, L2545, L2572 );
and3 U307 ( L3553, L422, L2553, L2578 );
and3 U308 ( L3553, L435, L2561, L2584 );
and2 U309 ( L3547, L2533, L2590 );
and2 U310 ( L3547, L2541, L2595 );
and2 U311 ( L3547, L2549, L2600 );
and2 U312 ( L3547, L2557, L2605 );
inv U313 ( L2627, L2630 );
inv U314 ( L2631, L2634 );
inv U315 ( L2635, L2638 );
inv U316 ( L2639, L2642 );
inv U317 ( L2643, L2646 );
inv U318 ( L2647, L2650 );
inv U319 ( L2651, L2654 );
inv U320 ( L2655, L2658 );
and3 U321 ( L3553, L389, L2631, L2660 );
and3 U322 ( L3553, L400, L2639, L2666 );
and3 U323 ( L3553, L411, L2647, L2672 );
and3 U324 ( L3553, L374, L2655, L2678 );
and2 U325 ( L3547, L2627, L2684 );
and2 U326 ( L3547, L2635, L2689 );
and2 U327 ( L3547, L2643, L2694 );
and2 U328 ( L3547, L2651, L2699 );
inv U329 ( L2721, L2728 );
inv U330 ( L2734, L2741 );
and2 U331 ( L292, L2721, L2748 );
and2 U332 ( L288, L2721, L2750 );
and2 U333 ( L280, L2721, L2752 );
and2 U334 ( L272, L2721, L2754 );
and2 U335 ( L264, L2721, L2756 );
and2 U336 ( L241, L2734, L2758 );
and2 U337 ( L233, L2734, L2760 );
and2 U338 ( L225, L2734, L2762 );
and2 U339 ( L217, L2734, L2764 );
and2 U340 ( L209, L2734, L2766 );
buffer U341 ( L1701, L2827 );
inv U342 ( L2828, L2838 );
inv U343 ( L2822, L2847 );
inv U344 ( L2882, L2885 );
inv U345 ( L2886, L2889 );
inv U346 ( L2890, L2893 );
inv U347 ( L2894, L2897 );
inv U348 ( L2898, L2901 );
inv U349 ( L2902, L2905 );
and2 U350 ( L2393, L2886, L2906 );
and3 U351 ( L2393, L479, L2894, L2909 );
and3 U352 ( L2393, L490, L2902, L2913 );
and2 U353 ( L3554, L2882, L2918 );
and2 U354 ( L3554, L2890, L2922 );
and2 U355 ( L3554, L2898, L2927 );
inv U356 ( L2948, L2951 );
inv U357 ( L2952, L2955 );
inv U358 ( L2956, L2959 );
inv U359 ( L2960, L2963 );
inv U360 ( L2964, L2967 );
inv U361 ( L2968, L2971 );
and3 U362 ( L3553, L503, L2952, L2973 );
inv U363 ( L2979, L2980 );
and3 U364 ( L3553, L523, L2960, L2982 );
and3 U365 ( L3553, L534, L2968, L2988 );
and2 U366 ( L3547, L2948, L2994 );
and2 U367 ( L3547, L2956, L3001 );
and2 U368 ( L3547, L2964, L3006 );
inv U369 ( L3024, L3027 );
inv U370 ( L3028, L3031 );
inv U371 ( L3032, L3035 );
inv U372 ( L3036, L3039 );
inv U373 ( L3040, L3043 );
inv U374 ( L3044, L3047 );
inv U375 ( L3048, L3051 );
inv U376 ( L3052, L3055 );
and3 U377 ( L2393, L389, L3028, L3056 );
and3 U378 ( L2393, L400, L3036, L3060 );
and3 U379 ( L2393, L411, L3044, L3064 );
and3 U380 ( L2393, L374, L3052, L3068 );
and2 U381 ( L3554, L3024, L3073 );
and2 U382 ( L3554, L3032, L3078 );
and2 U383 ( L3554, L3040, L3083 );
and2 U384 ( L3554, L3048, L3088 );
inv U385 ( L3092, L3099 );
inv U386 ( L3105, L3112 );
and2 U387 ( L372, L3092, L3119 );
and2 U388 ( L366, L3092, L3121 );
and2 U389 ( L358, L3092, L3123 );
and2 U390 ( L348, L3092, L3125 );
and2 U391 ( L338, L3092, L3126 );
and2 U392 ( L331, L3105, L3128 );
and2 U393 ( L323, L3105, L3130 );
and2 U394 ( L315, L3105, L3132 );
and2 U395 ( L307, L3105, L3134 );
and2 U396 ( L299, L3105, L3136 );
inv U397 ( L3181, L3187 );
and2 U398 ( L83, L3181, L3193 );
and2 U399 ( L86, L3181, L3196 );
and2 U400 ( L88, L3181, L3199 );
and2 U401 ( L88, L3181, L3202 );
inv U402 ( L3204, L3207 );
inv U403 ( L3208, L3211 );
inv U404 ( L3212, L3215 );
inv U405 ( L3216, L3219 );
inv U406 ( L3220, L3223 );
inv U407 ( L3224, L3227 );
and3 U408 ( L2405, L503, L3208, L3228 );
and2 U409 ( L2405, L514, L3232 );
and3 U410 ( L2405, L523, L3216, L3234 );
and3 U411 ( L2405, L534, L3224, L3238 );
and2 U412 ( L3555, L3204, L3243 );
or2 U413 ( L3555, L514, L3247 );
and2 U414 ( L3555, L3212, L3249 );
and2 U415 ( L3555, L3220, L3253 );
inv U416 ( L3256, L3259 );
inv U417 ( L3260, L3263 );
inv U418 ( L3264, L3267 );
inv U419 ( L3268, L3271 );
inv U420 ( L3272, L3275 );
inv U421 ( L3276, L3279 );
and2 U422 ( L2405, L3260, L3280 );
and3 U423 ( L2405, L479, L3268, L3283 );
and3 U424 ( L2405, L490, L3276, L3287 );
and2 U425 ( L3555, L3256, L3292 );
and2 U426 ( L3555, L3264, L3295 );
and2 U427 ( L3555, L3272, L3299 );
inv U428 ( L3302, L3305 );
buffer U429 ( L2816, L3306 );
buffer U430 ( L2816, L3310 );
inv U431 ( L3314, L3317 );
buffer U432 ( L2816, L3318 );
buffer U433 ( L2816, L3322 );
and2 U434 ( L2405, L3302, L3326 );
and2 U435 ( L2405, L3314, L3333 );
inv U436 ( L3354, L3357 );
inv U437 ( L3358, L3361 );
inv U438 ( L3362, L3365 );
inv U439 ( L3366, L3369 );
inv U440 ( L3370, L3373 );
inv U441 ( L3374, L3377 );
inv U442 ( L3378, L3381 );
inv U443 ( L3382, L3385 );
and3 U444 ( L2393, L457, L3358, L3386 );
and3 U445 ( L2393, L468, L3366, L3390 );
and3 U446 ( L2393, L422, L3374, L3394 );
and3 U447 ( L2393, L435, L3382, L3398 );
and2 U448 ( L3554, L3354, L3403 );
and2 U449 ( L3554, L3362, L3408 );
and2 U450 ( L3554, L3370, L3413 );
and2 U451 ( L3554, L3378, L3418 );
inv U452 ( L5082, L5088 );
inv U453 ( L5085, L5089 );
inv U454 ( L5090, L5096 );
inv U455 ( L5093, L5097 );
buffer U456 ( L3440, L3489 );
buffer U457 ( L3440, L3493 );
inv U458 ( L3558, L3570 );
inv U459 ( L3582, L3594 );
inv U460 ( L3616, L3622 );
inv U461 ( L3628, L3632 );
and2 U462 ( L97, L3616, L3637 );
and2 U463 ( L94, L3616, L3640 );
and2 U464 ( L97, L3616, L3643 );
and2 U465 ( L94, L3616, L3646 );
inv U466 ( L3660, L3672 );
inv U467 ( L3684, L3696 );
inv U468 ( L3737, L3745 );
inv U469 ( L3757, L3765 );
inv U470 ( L3795, L3803 );
inv U471 ( L3815, L3823 );
inv U472 ( L5332, L5338 );
inv U473 ( L5335, L5339 );
inv U474 ( L5340, L5346 );
inv U475 ( L5343, L5347 );
inv U476 ( L5348, L5354 );
inv U477 ( L5351, L5355 );
inv U478 ( L3972, L3979 );
inv U479 ( L3991, L3998 );
inv U480 ( L4030, L4037 );
inv U481 ( L4049, L4056 );
buffer U482 ( L4110, L4094 );
inv U483 ( L5098, L5104 );
inv U484 ( L5101, L5105 );
inv U485 ( L5108, L5114 );
inv U486 ( L5111, L5115 );
inv U487 ( L5356, L5362 );
inv U488 ( L5359, L5363 );
buffer U489 ( L2816, L5366 );
inv U490 ( L5369, L5373 );
buffer U491 ( L1688, L993 );
buffer U492 ( L1688, L978 );
buffer U493 ( L1688, L949 );
buffer U494 ( L1688, L939 );
and3 U495 ( L457, L3551, L2540, L2568 );
and3 U496 ( L468, L3551, L2548, L2574 );
and3 U497 ( L422, L3551, L2556, L2580 );
and3 U498 ( L435, L3551, L2564, L2586 );
and2 U499 ( L3549, L2536, L2592 );
and2 U500 ( L3549, L2544, L2597 );
and2 U501 ( L3549, L2552, L2602 );
and2 U502 ( L3549, L2560, L2607 );
and3 U503 ( L389, L3551, L2634, L2662 );
and3 U504 ( L400, L3551, L2642, L2668 );
and3 U505 ( L411, L3551, L2650, L2674 );
and3 U506 ( L374, L3551, L2658, L2680 );
and2 U507 ( L3549, L2630, L2686 );
and2 U508 ( L3549, L2638, L2691 );
and2 U509 ( L3549, L2646, L2696 );
and2 U510 ( L3549, L2654, L2701 );
and2 U511 ( L2370, L2889, L2907 );
and3 U512 ( L479, L2370, L2897, L2910 );
and3 U513 ( L490, L2370, L2905, L2914 );
and2 U514 ( L3556, L2885, L2920 );
and2 U515 ( L3556, L2893, L2924 );
and2 U516 ( L3556, L2901, L2929 );
and3 U517 ( L503, L3551, L2955, L2975 );
and3 U518 ( L523, L3551, L2963, L2984 );
and3 U519 ( L534, L3551, L2971, L2990 );
and2 U520 ( L3549, L2951, L2996 );
and2 U521 ( L3549, L2959, L3003 );
and2 U522 ( L3549, L2967, L3008 );
and2 U523 ( L2980, L2999, L3015 );
and3 U524 ( L389, L2370, L3031, L3057 );
and3 U525 ( L400, L2370, L3039, L3061 );
and3 U526 ( L411, L2370, L3047, L3065 );
and3 U527 ( L374, L2370, L3055, L3069 );
and2 U528 ( L3556, L3027, L3075 );
and2 U529 ( L3556, L3035, L3080 );
and2 U530 ( L3556, L3043, L3085 );
and2 U531 ( L3556, L3051, L3090 );
and3 U532 ( L503, L2382, L3211, L3229 );
inv U533 ( L3232, L3233 );
and3 U534 ( L523, L2382, L3219, L3235 );
and3 U535 ( L534, L2382, L3227, L3239 );
and2 U536 ( L2361, L3207, L3244 );
and2 U537 ( L2361, L3215, L3250 );
and2 U538 ( L2361, L3223, L3254 );
and2 U539 ( L2382, L3263, L3281 );
and3 U540 ( L479, L2382, L3271, L3284 );
and3 U541 ( L490, L2382, L3279, L3288 );
and2 U542 ( L2361, L3259, L3293 );
and2 U543 ( L2361, L3267, L3296 );
and2 U544 ( L2361, L3275, L3300 );
and2 U545 ( L2382, L3305, L3327 );
and2 U546 ( L2382, L3317, L3334 );
and3 U547 ( L457, L2370, L3361, L3387 );
and3 U548 ( L468, L2370, L3369, L3391 );
and3 U549 ( L422, L2370, L3377, L3395 );
and3 U550 ( L435, L2370, L3385, L3399 );
and2 U551 ( L3556, L3357, L3405 );
and2 U552 ( L3556, L3365, L3410 );
and2 U553 ( L3556, L3373, L3415 );
and2 U554 ( L3556, L3381, L3420 );
nand2 U555 ( L5085, L5088, L3422 );
nand2 U556 ( L5082, L5089, L3423 );
nand2 U557 ( L5093, L5096, L3431 );
nand2 U558 ( L5090, L5097, L3432 );
nand2 U559 ( L5335, L5338, L3895 );
nand2 U560 ( L5332, L5339, L3896 );
nand2 U561 ( L5343, L5346, L3904 );
nand2 U562 ( L5340, L5347, L3905 );
nand2 U563 ( L5351, L5354, L3913 );
nand2 U564 ( L5348, L5355, L3914 );
buffer U565 ( L4094, L889 );
nand2 U566 ( L5101, L5104, L5106 );
nand2 U567 ( L5098, L5105, L5107 );
nand2 U568 ( L5111, L5114, L5116 );
nand2 U569 ( L5108, L5115, L5117 );
nand2 U570 ( L5359, L5362, L5364 );
nand2 U571 ( L5356, L5363, L5365 );
inv U572 ( L4094, L593 );
and2 U573 ( L2838, L2847, L2880 );
and2 U574 ( L2828, L2847, L2881 );
and3 U575 ( L200, L1540, L1552, L1579 );
and3 U576 ( L203, L1540, L1552, L1585 );
and3 U577 ( L197, L1540, L1552, L1591 );
and3 U578 ( L194, L1540, L1552, L1597 );
and3 U579 ( L191, L1540, L1552, L1603 );
and3 U580 ( L182, L1621, L1633, L1667 );
and3 U581 ( L188, L1621, L1633, L1673 );
and3 U582 ( L155, L1621, L1633, L1679 );
and3 U583 ( L149, L1621, L1633, L1685 );
and2 U584 ( L2838, L2847, L2876 );
and2 U585 ( L2828, L2847, L2877 );
and3 U586 ( L200, L2215, L2226, L2253 );
and3 U587 ( L203, L2215, L2226, L2259 );
and3 U588 ( L197, L2215, L2226, L2265 );
and3 U589 ( L194, L2215, L2226, L2271 );
and3 U590 ( L191, L2215, L2226, L2277 );
and3 U591 ( L182, L2293, L2304, L2338 );
and3 U592 ( L188, L2293, L2304, L2344 );
and3 U593 ( L155, L2293, L2304, L2350 );
and3 U594 ( L149, L2293, L2304, L2356 );
and2 U595 ( L2838, L2847, L2868 );
and2 U596 ( L2828, L2847, L2869 );
and3 U597 ( L109, L3672, L3684, L710 );
and2 U598 ( L2838, L2847, L2872 );
and2 U599 ( L2828, L2847, L2873 );
and3 U600 ( L11, L2430, L2442, L720 );
and3 U601 ( L109, L3570, L3582, L725 );
and3 U602 ( L46, L3570, L3582, L730 );
and3 U603 ( L100, L3570, L3582, L735 );
and3 U604 ( L91, L3570, L3582, L740 );
and3 U605 ( L43, L3570, L3582, L745 );
and3 U606 ( L76, L2430, L2442, L750 );
and3 U607 ( L73, L2430, L2442, L755 );
and3 U608 ( L67, L2430, L2442, L760 );
and3 U609 ( L14, L2430, L2442, L765 );
and3 U610 ( L46, L3672, L3684, L770 );
and3 U611 ( L100, L3672, L3684, L775 );
and3 U612 ( L91, L3672, L3684, L780 );
and3 U613 ( L43, L3672, L3684, L785 );
and3 U614 ( L76, L2488, L2500, L790 );
and3 U615 ( L73, L2488, L2500, L795 );
and3 U616 ( L67, L2488, L2500, L800 );
and3 U617 ( L14, L2488, L2500, L805 );
and3 U618 ( L120, L3803, L3815, L841 );
and3 U619 ( L11, L2488, L2500, L857 );
and3 U620 ( L118, L3745, L3757, L880 );
and3 U621 ( L176, L1621, L1633, L1660 );
and3 U622 ( L176, L2293, L2304, L2331 );
or2 U623 ( L2566, L2568, L2569 );
or2 U624 ( L2572, L2574, L2575 );
or2 U625 ( L2578, L2580, L2581 );
or2 U626 ( L2584, L2586, L2587 );
or3 U627 ( L2590, L2592, L457, L2593 );
or3 U628 ( L2595, L2597, L468, L2598 );
or3 U629 ( L2600, L2602, L422, L2603 );
or3 U630 ( L2605, L2607, L435, L2608 );
or2 U631 ( L2660, L2662, L2663 );
or2 U632 ( L2666, L2668, L2669 );
or2 U633 ( L2672, L2674, L2675 );
or2 U634 ( L2678, L2680, L2681 );
or3 U635 ( L2684, L2686, L389, L2687 );
or3 U636 ( L2689, L2691, L400, L2692 );
or3 U637 ( L2694, L2696, L411, L2697 );
or3 U638 ( L2699, L2701, L374, L2702 );
and2 U639 ( L289, L2728, L2747 );
and2 U640 ( L281, L2728, L2749 );
and2 U641 ( L273, L2728, L2751 );
and2 U642 ( L265, L2728, L2753 );
and2 U643 ( L257, L2728, L2755 );
and2 U644 ( L234, L2741, L2757 );
and2 U645 ( L226, L2741, L2759 );
and2 U646 ( L218, L2741, L2761 );
and2 U647 ( L210, L2741, L2763 );
and2 U648 ( L206, L2741, L2765 );
inv U649 ( L2847, L2857 );
or2 U650 ( L2906, L2907, L2908 );
or2 U651 ( L2909, L2910, L2911 );
or2 U652 ( L2913, L2914, L2915 );
or3 U653 ( L2922, L2924, L479, L2925 );
or3 U654 ( L2927, L2929, L490, L2930 );
or2 U655 ( L2918, L2920, L2933 );
or2 U656 ( L2973, L2975, L2976 );
or2 U657 ( L2982, L2984, L2985 );
or2 U658 ( L2988, L2990, L2991 );
or3 U659 ( L2994, L2996, L503, L2997 );
or3 U660 ( L3001, L3003, L523, L3004 );
or3 U661 ( L3006, L3008, L534, L3009 );
or2 U662 ( L3056, L3057, L3058 );
or2 U663 ( L3060, L3061, L3062 );
or2 U664 ( L3064, L3065, L3066 );
or2 U665 ( L3068, L3069, L3070 );
or3 U666 ( L3073, L3075, L389, L3076 );
or3 U667 ( L3078, L3080, L400, L3081 );
or3 U668 ( L3083, L3085, L411, L3086 );
or3 U669 ( L3088, L3090, L374, L3091 );
and2 U670 ( L369, L3099, L3118 );
and2 U671 ( L361, L3099, L3120 );
and2 U672 ( L351, L3099, L3122 );
and2 U673 ( L341, L3099, L3124 );
and2 U674 ( L324, L3112, L3127 );
and2 U675 ( L316, L3112, L3129 );
and2 U676 ( L308, L3112, L3131 );
and2 U677 ( L302, L3112, L3133 );
and2 U678 ( L293, L3112, L3135 );
or2 U679 ( L3099, L3126, L3147 );
and2 U680 ( L83, L3187, L3192 );
and2 U681 ( L87, L3187, L3195 );
and2 U682 ( L34, L3187, L3198 );
and2 U683 ( L34, L3187, L3201 );
or2 U684 ( L3228, L3229, L3230 );
or2 U685 ( L3234, L3235, L3236 );
or2 U686 ( L3238, L3239, L3240 );
or3 U687 ( L3243, L3244, L503, L3245 );
or3 U688 ( L3249, L3250, L523, L3251 );
or3 U689 ( L3253, L3254, L534, L3255 );
or2 U690 ( L3280, L3281, L3282 );
or2 U691 ( L3283, L3284, L3285 );
or2 U692 ( L3287, L3288, L3289 );
or3 U693 ( L3295, L3296, L479, L3297 );
or3 U694 ( L3299, L3300, L490, L3301 );
inv U695 ( L3306, L3309 );
inv U696 ( L3310, L3313 );
inv U697 ( L3318, L3321 );
inv U698 ( L3322, L3325 );
or2 U699 ( L3326, L3327, L3328 );
and3 U700 ( L2405, L446, L3310, L3329 );
or2 U701 ( L3333, L3334, L3335 );
and3 U702 ( L2405, L446, L3322, L3336 );
and2 U703 ( L3555, L3306, L3341 );
and2 U704 ( L3555, L3318, L3345 );
or2 U705 ( L3386, L3387, L3388 );
or2 U706 ( L3390, L3391, L3392 );
or2 U707 ( L3394, L3395, L3396 );
or2 U708 ( L3398, L3399, L3400 );
or3 U709 ( L3403, L3405, L457, L3406 );
or3 U710 ( L3408, L3410, L468, L3411 );
or3 U711 ( L3413, L3415, L422, L3416 );
or3 U712 ( L3418, L3420, L435, L3421 );
nand2 U713 ( L3422, L3423, L3424 );
nand2 U714 ( L3431, L3432, L3433 );
inv U715 ( L3489, L3492 );
inv U716 ( L3493, L3496 );
and3 U717 ( L117, L3745, L3757, L3780 );
and3 U718 ( L126, L3745, L3757, L3783 );
and3 U719 ( L127, L3745, L3757, L3786 );
and3 U720 ( L128, L3745, L3757, L3789 );
and3 U721 ( L131, L3803, L3815, L3838 );
and3 U722 ( L129, L3803, L3815, L3841 );
and3 U723 ( L119, L3803, L3815, L3844 );
and3 U724 ( L130, L3803, L3815, L3847 );
nand2 U725 ( L3895, L3896, L3897 );
nand2 U726 ( L3904, L3905, L3906 );
nand2 U727 ( L3913, L3914, L3915 );
and3 U728 ( L122, L3979, L3991, L4011 );
and3 U729 ( L113, L3979, L3991, L4014 );
and3 U730 ( L53, L3979, L3991, L4017 );
and3 U731 ( L114, L3979, L3991, L4020 );
and3 U732 ( L115, L3979, L3991, L4023 );
and3 U733 ( L52, L4037, L4049, L4069 );
and3 U734 ( L112, L4037, L4049, L4072 );
and3 U735 ( L116, L4037, L4049, L4075 );
and3 U736 ( L121, L4037, L4049, L4078 );
and3 U737 ( L123, L4037, L4049, L4081 );
nand2 U738 ( L5116, L5117, L5206 );
nand2 U739 ( L5106, L5107, L5209 );
and2 U740 ( L3233, L3247, L5307 );
or2 U741 ( L3292, L3293, L5322 );
inv U742 ( L5366, L5372 );
nand2 U743 ( L5366, L5373, L5375 );
nand2 U744 ( L5364, L5365, L5399 );
inv U745 ( L3015, L2813 );
or2 U746 ( L3195, L3196, L3197 );
or2 U747 ( L3198, L3199, L3200 );
or2 U748 ( L3201, L3202, L3203 );
or2 U749 ( L3192, L3193, L3194 );
inv U750 ( L2569, L2570 );
inv U751 ( L2575, L2576 );
inv U752 ( L2581, L2582 );
inv U753 ( L2587, L2588 );
inv U754 ( L2663, L2664 );
inv U755 ( L2669, L2670 );
inv U756 ( L2675, L2676 );
inv U757 ( L2681, L2682 );
or2 U758 ( L2749, L2750, L2767 );
or2 U759 ( L2751, L2752, L2772 );
or2 U760 ( L2753, L2754, L2776 );
or2 U761 ( L2755, L2756, L2780 );
or2 U762 ( L2757, L2758, L2784 );
or2 U763 ( L2759, L2760, L2788 );
or2 U764 ( L2761, L2762, L2794 );
or2 U765 ( L2763, L2764, L2798 );
or2 U766 ( L2765, L2766, L2802 );
inv U767 ( L2911, L2912 );
inv U768 ( L2915, L2916 );
inv U769 ( L2908, L2936 );
inv U770 ( L2976, L2977 );
inv U771 ( L2985, L2986 );
inv U772 ( L2991, L2992 );
inv U773 ( L3058, L3059 );
inv U774 ( L3062, L3063 );
inv U775 ( L3066, L3067 );
inv U776 ( L3070, L3071 );
or2 U777 ( L3120, L3121, L3137 );
or2 U778 ( L3122, L3123, L3139 );
or2 U779 ( L3124, L3125, L3143 );
or2 U780 ( L3127, L3128, L3151 );
or2 U781 ( L3129, L3130, L3155 );
or2 U782 ( L3131, L3132, L3161 );
or2 U783 ( L3133, L3134, L3165 );
or2 U784 ( L3135, L3136, L3167 );
inv U785 ( L3230, L3231 );
inv U786 ( L3236, L3237 );
inv U787 ( L3240, L3241 );
inv U788 ( L3285, L3286 );
inv U789 ( L3289, L3290 );
and3 U790 ( L446, L2382, L3313, L3330 );
and3 U791 ( L446, L2382, L3325, L3337 );
and2 U792 ( L2361, L3309, L3342 );
and2 U793 ( L2361, L3321, L3346 );
inv U794 ( L3328, L3348 );
inv U795 ( L3335, L3352 );
inv U796 ( L3388, L3389 );
inv U797 ( L3392, L3393 );
inv U798 ( L3396, L3397 );
inv U799 ( L3400, L3401 );
and3 U800 ( L3015, L3803, L3823, L3845 );
or2 U801 ( L3118, L3119, L5126 );
or2 U802 ( L2747, L2748, L5178 );
inv U803 ( L3282, L5325 );
nand2 U804 ( L5369, L5372, L5374 );
inv U805 ( L2933, L2810 );
and2 U806 ( L3197, L3176, L635 );
and3 U807 ( L24, L2838, L2857, L2878 );
and3 U808 ( L25, L2828, L2857, L2879 );
and3 U809 ( L26, L2838, L2857, L2874 );
and3 U810 ( L81, L2828, L2857, L2875 );
and2 U811 ( L3200, L3176, L703 );
and3 U812 ( L79, L2838, L2857, L2866 );
and3 U813 ( L23, L2828, L2857, L2867 );
and3 U814 ( L82, L2838, L2857, L2870 );
and3 U815 ( L80, L2828, L2857, L2871 );
and2 U816 ( L3203, L3176, L716 );
and2 U817 ( L3194, L3176, L819 );
and2 U818 ( L3147, L514, L1789 );
and2 U819 ( L514, L3147, L2036 );
and2 U820 ( L2570, L2593, L2611 );
and2 U821 ( L2576, L2598, L2615 );
and2 U822 ( L2582, L2603, L2619 );
and2 U823 ( L2588, L2608, L2623 );
and2 U824 ( L2664, L2687, L2705 );
and2 U825 ( L2670, L2692, L2709 );
and2 U826 ( L2676, L2697, L2713 );
and2 U827 ( L2682, L2702, L2717 );
and2 U828 ( L2912, L2925, L2939 );
and2 U829 ( L2916, L2930, L2942 );
buffer U830 ( L2933, L2945 );
and2 U831 ( L2977, L2997, L3012 );
and2 U832 ( L2986, L3004, L3018 );
and2 U833 ( L2992, L3009, L3021 );
or2 U834 ( L3329, L3330, L3331 );
or2 U835 ( L3336, L3337, L3338 );
or3 U836 ( L3341, L3342, L446, L3343 );
or3 U837 ( L3345, L3346, L446, L3347 );
inv U838 ( L3424, L3428 );
inv U839 ( L3433, L3437 );
and3 U840 ( L3433, L3424, L3489, L3514 );
and3 U841 ( L3352, L3803, L3823, L3836 );
and2 U842 ( L3071, L3091, L3852 );
inv U843 ( L5307, L5311 );
inv U844 ( L3897, L3901 );
inv U845 ( L3906, L3910 );
buffer U846 ( L3915, L3934 );
buffer U847 ( L3915, L3938 );
buffer U848 ( L3147, L4652 );
buffer U849 ( L3147, L4783 );
buffer U850 ( L3147, L5137 );
inv U851 ( L5206, L5212 );
inv U852 ( L5209, L5213 );
and2 U853 ( L3063, L3081, L5260 );
and2 U854 ( L3067, L3086, L5263 );
and2 U855 ( L3401, L3421, L5268 );
and2 U856 ( L3059, L3076, L5271 );
and2 U857 ( L3393, L3411, L5276 );
and2 U858 ( L3397, L3416, L5279 );
and2 U859 ( L3389, L3406, L5289 );
and2 U860 ( L3237, L3251, L5296 );
and2 U861 ( L3241, L3255, L5299 );
and2 U862 ( L3231, L3245, L5304 );
and2 U863 ( L3286, L3297, L5312 );
and2 U864 ( L3290, L3301, L5315 );
inv U865 ( L5322, L5328 );
nand2 U866 ( L5374, L5375, L5396 );
inv U867 ( L5399, L5403 );
and2 U868 ( L446, L2802, L1286 );
inv U869 ( L2936, L2809 );
inv U870 ( L3348, L597 );
and2 U871 ( L2802, L446, L1031 );
inv U872 ( L635, L636 );
or4 U873 ( L2878, L2879, L2880, L2881, L637 );
or4 U874 ( L2874, L2875, L2876, L2877, L671 );
inv U875 ( L703, L704 );
or4 U876 ( L2866, L2867, L2868, L2869, L705 );
or4 U877 ( L2870, L2871, L2872, L2873, L713 );
inv U878 ( L716, L717 );
inv U879 ( L819, L820 );
and2 U880 ( L2798, L457, L1046 );
and2 U881 ( L2794, L468, L1064 );
and2 U882 ( L422, L2788, L1071 );
and2 U883 ( L2784, L435, L1097 );
and2 U884 ( L2780, L389, L1111 );
and2 U885 ( L2776, L400, L1128 );
and2 U886 ( L2772, L411, L1145 );
and2 U887 ( L2767, L374, L1160 );
and2 U888 ( L457, L2798, L1301 );
and2 U889 ( L468, L2794, L1318 );
and2 U890 ( L422, L2788, L1324 );
and2 U891 ( L435, L2784, L1341 );
and2 U892 ( L389, L2780, L1359 );
and2 U893 ( L400, L2776, L1382 );
and2 U894 ( L411, L2772, L1404 );
and2 U895 ( L374, L2767, L1412 );
inv U896 ( L3167, L1704 );
inv U897 ( L3165, L1712 );
buffer U898 ( L3165, L1724 );
and2 U899 ( L3161, L479, L1742 );
and2 U900 ( L490, L3155, L1749 );
and2 U901 ( L3151, L503, L1775 );
and2 U902 ( L3143, L523, L1806 );
and2 U903 ( L3139, L534, L1823 );
inv U904 ( L3137, L1829 );
buffer U905 ( L3137, L1837 );
inv U906 ( L3167, L1958 );
inv U907 ( L3165, L1966 );
buffer U908 ( L3165, L1978 );
and2 U909 ( L479, L3161, L1995 );
and2 U910 ( L490, L3155, L2001 );
and2 U911 ( L503, L3151, L2018 );
and2 U912 ( L523, L3143, L2059 );
and2 U913 ( L534, L3139, L2081 );
buffer U914 ( L3137, L2089 );
inv U915 ( L3137, L2106 );
buffer U916 ( L3167, L3170 );
inv U917 ( L3331, L3332 );
inv U918 ( L3338, L3339 );
inv U919 ( L5126, L5132 );
inv U920 ( L5178, L5184 );
inv U921 ( L3852, L3853 );
inv U922 ( L3348, L3874 );
and3 U923 ( L2936, L4037, L4056, L4076 );
buffer U924 ( L2802, L4116 );
buffer U925 ( L2798, L4124 );
buffer U926 ( L2794, L4132 );
buffer U927 ( L2788, L4140 );
buffer U928 ( L2784, L4148 );
buffer U929 ( L2780, L4156 );
buffer U930 ( L2776, L4164 );
buffer U931 ( L2772, L4172 );
buffer U932 ( L2767, L4180 );
nor2 U933 ( L422, L2788, L4228 );
buffer U934 ( L2802, L4279 );
buffer U935 ( L2798, L4287 );
buffer U936 ( L2794, L4295 );
buffer U937 ( L2784, L4303 );
buffer U938 ( L2780, L4311 );
buffer U939 ( L2776, L4319 );
buffer U940 ( L2772, L4327 );
buffer U941 ( L2788, L4335 );
buffer U942 ( L2767, L4343 );
nor2 U943 ( L422, L2788, L4348 );
nor2 U944 ( L374, L2767, L4464 );
buffer U945 ( L3161, L4628 );
buffer U946 ( L3155, L4636 );
buffer U947 ( L3151, L4644 );
buffer U948 ( L3143, L4660 );
buffer U949 ( L3139, L4668 );
nor2 U950 ( L490, L3155, L4716 );
buffer U951 ( L3161, L4767 );
buffer U952 ( L3151, L4775 );
buffer U953 ( L3143, L4791 );
buffer U954 ( L3139, L4799 );
buffer U955 ( L3155, L4807 );
nor2 U956 ( L490, L3155, L4812 );
buffer U957 ( L3139, L5118 );
buffer U958 ( L3143, L5121 );
buffer U959 ( L3137, L5129 );
buffer U960 ( L3151, L5134 );
buffer U961 ( L3161, L5142 );
buffer U962 ( L3155, L5145 );
buffer U963 ( L3167, L5152 );
buffer U964 ( L3165, L5155 );
buffer U965 ( L2788, L5162 );
buffer U966 ( L2784, L5165 );
buffer U967 ( L2798, L5170 );
buffer U968 ( L2794, L5173 );
buffer U969 ( L2802, L5181 );
buffer U970 ( L2772, L5186 );
buffer U971 ( L2767, L5189 );
buffer U972 ( L2780, L5196 );
buffer U973 ( L2776, L5199 );
nand2 U974 ( L5209, L5212, L5214 );
nand2 U975 ( L5206, L5213, L5215 );
inv U976 ( L5325, L5329 );
nand2 U977 ( L5325, L5328, L5330 );
inv U978 ( L2942, L2807 );
inv U979 ( L2939, L2808 );
inv U980 ( L3021, L2811 );
inv U981 ( L3018, L2812 );
inv U982 ( L3012, L2814 );
inv U983 ( L2623, L2626 );
inv U984 ( L2619, L2622 );
inv U985 ( L2615, L2618 );
inv U986 ( L2611, L2614 );
inv U987 ( L2717, L2720 );
inv U988 ( L2713, L2716 );
inv U989 ( L2709, L2712 );
inv U990 ( L2705, L2708 );
and2 U991 ( L637, L2827, L639 );
and2 U992 ( L671, L2827, L673 );
and2 U993 ( L705, L2827, L707 );
and2 U994 ( L713, L2827, L715 );
and3 U995 ( L2945, L3728, L3721, L3731 );
inv U996 ( L4652, L4658 );
nand2 U997 ( L4652, L4659, L1777 );
nand2 U998 ( L4783, L4786, L2019 );
inv U999 ( L4783, L4787 );
and2 U1000 ( L3332, L3343, L3350 );
and2 U1001 ( L3339, L3347, L3353 );
inv U1002 ( L5137, L5141 );
and3 U1003 ( L3428, L3433, L3492, L3513 );
and3 U1004 ( L3424, L3437, L3496, L3516 );
and3 U1005 ( L3437, L3428, L3493, L3517 );
and3 U1006 ( L2717, L3745, L3765, L3778 );
and3 U1007 ( L2713, L3745, L3765, L3781 );
and3 U1008 ( L2709, L3745, L3765, L3784 );
and3 U1009 ( L2705, L3745, L3765, L3787 );
and3 U1010 ( L3021, L3803, L3823, L3839 );
and3 U1011 ( L3018, L3803, L3823, L3842 );
inv U1012 ( L5260, L5266 );
inv U1013 ( L5263, L5267 );
inv U1014 ( L5268, L5274 );
inv U1015 ( L5271, L5275 );
inv U1016 ( L5296, L5302 );
inv U1017 ( L5299, L5303 );
inv U1018 ( L5304, L5310 );
nand2 U1019 ( L5304, L5311, L3891 );
inv U1020 ( L3934, L3937 );
inv U1021 ( L3938, L3941 );
and3 U1022 ( L3906, L3897, L3934, L3955 );
and3 U1023 ( L3910, L3901, L3938, L3958 );
and3 U1024 ( L2623, L3979, L3998, L4009 );
and3 U1025 ( L2619, L3979, L3998, L4012 );
and3 U1026 ( L2615, L3979, L3998, L4015 );
and3 U1027 ( L2611, L3979, L3998, L4018 );
and3 U1028 ( L3012, L4037, L4056, L4067 );
and3 U1029 ( L2942, L4037, L4056, L4070 );
and3 U1030 ( L2939, L4037, L4056, L4073 );
and3 U1031 ( L2945, L4037, L4056, L4079 );
nand2 U1032 ( L5214, L5215, L5239 );
inv U1033 ( L5276, L5282 );
inv U1034 ( L5279, L5283 );
inv U1035 ( L5289, L5293 );
inv U1036 ( L5312, L5318 );
inv U1037 ( L5315, L5319 );
nand2 U1038 ( L5322, L5329, L5331 );
inv U1039 ( L5396, L5402 );
nand2 U1040 ( L5396, L5403, L5405 );
and4 U1041 ( L2807, L2808, L2809, L2810, L595 );
and4 U1042 ( L2811, L2812, L2813, L2814, L596 );
and4 U1043 ( L2626, L2622, L2618, L2614, L607 );
and4 U1044 ( L2720, L2716, L2712, L2708, L608 );
and2 U1045 ( L1704, L1724, L1845 );
and3 U1046 ( L1712, L1704, L1742, L1846 );
and2 U1047 ( L1958, L1978, L2115 );
and3 U1048 ( L1966, L1958, L1995, L2116 );
inv U1049 ( L4116, L4122 );
nand2 U1050 ( L4116, L4123, L1022 );
inv U1051 ( L4124, L4130 );
nand2 U1052 ( L4124, L4131, L1033 );
inv U1053 ( L4132, L4138 );
nand2 U1054 ( L4132, L4139, L1051 );
inv U1055 ( L4140, L4146 );
nand2 U1056 ( L4140, L4147, L1079 );
inv U1057 ( L4148, L4154 );
nand2 U1058 ( L4148, L4155, L1088 );
inv U1059 ( L4156, L4162 );
nand2 U1060 ( L4156, L4163, L1099 );
inv U1061 ( L4164, L4170 );
nand2 U1062 ( L4164, L4171, L1115 );
inv U1063 ( L4172, L4178 );
nand2 U1064 ( L4172, L4179, L1133 );
inv U1065 ( L4180, L4186 );
nand2 U1066 ( L4180, L4187, L1151 );
inv U1067 ( L4228, L4234 );
nand2 U1068 ( L4279, L4282, L1276 );
inv U1069 ( L4279, L4283 );
nand2 U1070 ( L4287, L4290, L1287 );
inv U1071 ( L4287, L4291 );
nand2 U1072 ( L4295, L4298, L1305 );
inv U1073 ( L4295, L4299 );
nand2 U1074 ( L4303, L4306, L1330 );
inv U1075 ( L4303, L4307 );
nand2 U1076 ( L4311, L4314, L1342 );
inv U1077 ( L4311, L4315 );
nand2 U1078 ( L4319, L4322, L1363 );
inv U1079 ( L4319, L4323 );
nand2 U1080 ( L4327, L4330, L1388 );
inv U1081 ( L4327, L4331 );
nand2 U1082 ( L4335, L4338, L1420 );
inv U1083 ( L4335, L4339 );
nand2 U1084 ( L4343, L4346, L1428 );
inv U1085 ( L4343, L4347 );
inv U1086 ( L4628, L4634 );
nand2 U1087 ( L4628, L4635, L1729 );
inv U1088 ( L4636, L4642 );
nand2 U1089 ( L4636, L4643, L1757 );
inv U1090 ( L4644, L4650 );
nand2 U1091 ( L4644, L4651, L1766 );
nand2 U1092 ( L4655, L4658, L1776 );
inv U1093 ( L4660, L4666 );
nand2 U1094 ( L4660, L4667, L1793 );
inv U1095 ( L4668, L4674 );
nand2 U1096 ( L4668, L4675, L1811 );
and2 U1097 ( L1712, L1742, L1849 );
and2 U1098 ( L1712, L1742, L1852 );
and2 U1099 ( L54, L1829, L1875 );
inv U1100 ( L4716, L4722 );
nand2 U1101 ( L4767, L4770, L1982 );
inv U1102 ( L4767, L4771 );
nand2 U1103 ( L4775, L4778, L2007 );
inv U1104 ( L4775, L4779 );
nand2 U1105 ( L4780, L4787, L2020 );
nand2 U1106 ( L4791, L4794, L2040 );
inv U1107 ( L4791, L4795 );
nand2 U1108 ( L4799, L4802, L2065 );
inv U1109 ( L4799, L4803 );
nand2 U1110 ( L4807, L4810, L2097 );
inv U1111 ( L4807, L4811 );
and2 U1112 ( L1966, L1995, L2119 );
and2 U1113 ( L1966, L1995, L2122 );
inv U1114 ( L5118, L5124 );
inv U1115 ( L5121, L5125 );
nand2 U1116 ( L5129, L5132, L3452 );
inv U1117 ( L5129, L5133 );
inv U1118 ( L5134, L5140 );
nand2 U1119 ( L5134, L5141, L3462 );
inv U1120 ( L5162, L5168 );
inv U1121 ( L5165, L5169 );
inv U1122 ( L5170, L5176 );
inv U1123 ( L5173, L5177 );
nand2 U1124 ( L5181, L5184, L3484 );
inv U1125 ( L5181, L5185 );
nor2 U1126 ( L3513, L3514, L3515 );
nor2 U1127 ( L3516, L3517, L3518 );
inv U1128 ( L3853, L3857 );
nand2 U1129 ( L5263, L5266, L3860 );
nand2 U1130 ( L5260, L5267, L3861 );
nand2 U1131 ( L5271, L5274, L3869 );
nand2 U1132 ( L5268, L5275, L3870 );
inv U1133 ( L3874, L3878 );
nand2 U1134 ( L5299, L5302, L3881 );
nand2 U1135 ( L5296, L5303, L3882 );
nand2 U1136 ( L5307, L5310, L3890 );
and3 U1137 ( L3901, L3906, L3937, L3954 );
and3 U1138 ( L3897, L3910, L3941, L3957 );
and3 U1139 ( L3353, L3979, L3998, L4021 );
inv U1140 ( L3170, L4099 );
buffer U1141 ( L1071, L4236 );
inv U1142 ( L4348, L4354 );
buffer U1143 ( L1324, L4406 );
inv U1144 ( L4464, L4470 );
buffer U1145 ( L1412, L4552 );
buffer U1146 ( L1829, L4679 );
buffer U1147 ( L1704, L4687 );
buffer U1148 ( L1704, L4695 );
buffer U1149 ( L1712, L4703 );
buffer U1150 ( L1712, L4711 );
buffer U1151 ( L1749, L4724 );
inv U1152 ( L4812, L4818 );
buffer U1153 ( L1958, L4855 );
buffer U1154 ( L1966, L4865 );
buffer U1155 ( L2001, L4870 );
buffer U1156 ( L1958, L4913 );
buffer U1157 ( L1966, L4923 );
buffer U1158 ( L2106, L4951 );
buffer U1159 ( L2089, L5006 );
buffer U1160 ( L2106, L5039 );
inv U1161 ( L5142, L5148 );
inv U1162 ( L5145, L5149 );
inv U1163 ( L5152, L5158 );
inv U1164 ( L5155, L5159 );
inv U1165 ( L5186, L5192 );
inv U1166 ( L5189, L5193 );
inv U1167 ( L5196, L5202 );
inv U1168 ( L5199, L5203 );
nand2 U1169 ( L5279, L5282, L5284 );
nand2 U1170 ( L5276, L5283, L5285 );
nand2 U1171 ( L5315, L5318, L5320 );
nand2 U1172 ( L5312, L5319, L5321 );
nand2 U1173 ( L5330, L5331, L5386 );
nand2 U1174 ( L5399, L5402, L5404 );
and3 U1175 ( L595, L596, L597, L598 );
inv U1176 ( L3350, L609 );
nand2 U1177 ( L4119, L4122, L1021 );
nand2 U1178 ( L4127, L4130, L1032 );
nand2 U1179 ( L4135, L4138, L1050 );
nand2 U1180 ( L4143, L4146, L1078 );
nand2 U1181 ( L4151, L4154, L1087 );
nand2 U1182 ( L4159, L4162, L1098 );
nand2 U1183 ( L4167, L4170, L1114 );
nand2 U1184 ( L4175, L4178, L1132 );
nand2 U1185 ( L4183, L4186, L1150 );
nand2 U1186 ( L4276, L4283, L1277 );
nand2 U1187 ( L4284, L4291, L1288 );
nand2 U1188 ( L4292, L4299, L1306 );
nand2 U1189 ( L4300, L4307, L1331 );
nand2 U1190 ( L4308, L4315, L1343 );
nand2 U1191 ( L4316, L4323, L1364 );
nand2 U1192 ( L4324, L4331, L1389 );
nand2 U1193 ( L4332, L4339, L1421 );
nand2 U1194 ( L4340, L4347, L1429 );
nand2 U1195 ( L4631, L4634, L1728 );
nand2 U1196 ( L4639, L4642, L1756 );
nand2 U1197 ( L4647, L4650, L1765 );
nand2 U1198 ( L1776, L1777, L1778 );
nand2 U1199 ( L4663, L4666, L1792 );
nand2 U1200 ( L4671, L4674, L1810 );
nand2 U1201 ( L4764, L4771, L1983 );
nand2 U1202 ( L4772, L4779, L2008 );
nand2 U1203 ( L2019, L2020, L2021 );
nand2 U1204 ( L4788, L4795, L2041 );
nand2 U1205 ( L4796, L4803, L2066 );
nand2 U1206 ( L4804, L4811, L2098 );
nand2 U1207 ( L5121, L5124, L3443 );
nand2 U1208 ( L5118, L5125, L3444 );
nand2 U1209 ( L5126, L5133, L3453 );
nand2 U1210 ( L5137, L5140, L3461 );
nand2 U1211 ( L5165, L5168, L3466 );
nand2 U1212 ( L5162, L5169, L3467 );
nand2 U1213 ( L5173, L5176, L3475 );
nand2 U1214 ( L5170, L5177, L3476 );
nand2 U1215 ( L5178, L5185, L3485 );
inv U1216 ( L5239, L5243 );
nand2 U1217 ( L3860, L3861, L3862 );
nand2 U1218 ( L3869, L3870, L3871 );
nand2 U1219 ( L3881, L3882, L3883 );
nand2 U1220 ( L3890, L3891, L3892 );
nor2 U1221 ( L3954, L3955, L3956 );
nor2 U1222 ( L3957, L3958, L3959 );
or2 U1223 ( L1837, L1875, L4756 );
nand2 U1224 ( L5145, L5148, L5150 );
nand2 U1225 ( L5142, L5149, L5151 );
nand2 U1226 ( L5155, L5158, L5160 );
nand2 U1227 ( L5152, L5159, L5161 );
nand2 U1228 ( L5189, L5192, L5194 );
nand2 U1229 ( L5186, L5193, L5195 );
nand2 U1230 ( L5199, L5202, L5204 );
nand2 U1231 ( L5196, L5203, L5205 );
nand2 U1232 ( L3518, L3515, L5236 );
buffer U1233 ( L3350, L5286 );
nand2 U1234 ( L5284, L5285, L5379 );
nand2 U1235 ( L5320, L5321, L5389 );
nand2 U1236 ( L5404, L5405, L5425 );
and3 U1237 ( L607, L608, L609, L610 );
nand2 U1238 ( L1021, L1022, L1023 );
nand2 U1239 ( L1032, L1033, L1034 );
nand2 U1240 ( L1050, L1051, L1052 );
nand2 U1241 ( L1078, L1079, L1080 );
nand2 U1242 ( L1087, L1088, L1089 );
nand2 U1243 ( L1098, L1099, L1100 );
nand2 U1244 ( L1114, L1115, L1116 );
nand2 U1245 ( L1132, L1133, L1134 );
nand2 U1246 ( L1150, L1151, L1152 );
inv U1247 ( L4236, L4242 );
nand2 U1248 ( L1276, L1277, L1278 );
nand2 U1249 ( L1287, L1288, L1289 );
nand2 U1250 ( L1305, L1306, L1307 );
nand2 U1251 ( L1330, L1331, L1332 );
nand2 U1252 ( L1342, L1343, L1344 );
nand2 U1253 ( L1363, L1364, L1365 );
nand2 U1254 ( L1388, L1389, L1390 );
nand2 U1255 ( L1420, L1421, L1422 );
nand2 U1256 ( L1428, L1429, L1430 );
nand2 U1257 ( L1728, L1729, L1730 );
nand2 U1258 ( L1756, L1757, L1758 );
nand2 U1259 ( L1765, L1766, L1767 );
nand2 U1260 ( L1792, L1793, L1794 );
nand2 U1261 ( L1810, L1811, L1812 );
nand2 U1262 ( L4679, L4682, L1876 );
inv U1263 ( L4679, L4683 );
inv U1264 ( L4687, L4691 );
inv U1265 ( L4695, L4699 );
inv U1266 ( L4703, L4707 );
inv U1267 ( L4711, L4715 );
inv U1268 ( L4724, L4730 );
nand2 U1269 ( L1982, L1983, L1984 );
nand2 U1270 ( L2007, L2008, L2009 );
nand2 U1271 ( L2040, L2041, L2042 );
nand2 U1272 ( L2065, L2066, L2067 );
nand2 U1273 ( L2097, L2098, L2099 );
inv U1274 ( L4865, L4869 );
inv U1275 ( L4923, L4927 );
nand2 U1276 ( L3443, L3444, L3445 );
nand2 U1277 ( L3452, L3453, L3454 );
nand2 U1278 ( L3461, L3462, L3463 );
nand2 U1279 ( L3466, L3467, L3468 );
nand2 U1280 ( L3475, L3476, L3477 );
nand2 U1281 ( L3484, L3485, L3486 );
and2 U1282 ( L4099, L3170, L4103 );
inv U1283 ( L4406, L4412 );
inv U1284 ( L4552, L4558 );
inv U1285 ( L4855, L4859 );
inv U1286 ( L4870, L4876 );
inv U1287 ( L4913, L4917 );
inv U1288 ( L4951, L4955 );
inv U1289 ( L5006, L5012 );
inv U1290 ( L5039, L5043 );
nand2 U1291 ( L5160, L5161, L5216 );
nand2 U1292 ( L5150, L5151, L5219 );
nand2 U1293 ( L5204, L5205, L5226 );
nand2 U1294 ( L5194, L5195, L5229 );
inv U1295 ( L5386, L5392 );
nand2 U1296 ( L3959, L3956, L5422 );
and2 U1297 ( L1778, L1806, L1866 );
nand2 U1298 ( L4676, L4683, L1877 );
inv U1299 ( L4756, L4762 );
and2 U1300 ( L2021, L2059, L2142 );
and2 U1301 ( L2021, L2059, L2146 );
inv U1302 ( L5236, L5242 );
nand2 U1303 ( L5236, L5243, L3532 );
inv U1304 ( L3862, L3866 );
inv U1305 ( L3883, L3887 );
buffer U1306 ( L3871, L3918 );
buffer U1307 ( L3871, L3922 );
buffer U1308 ( L3892, L3926 );
buffer U1309 ( L3892, L3930 );
inv U1310 ( L5425, L5429 );
or2 U1311 ( L4099, L4103, L4104 );
buffer U1312 ( L1778, L4743 );
buffer U1313 ( L2021, L4991 );
buffer U1314 ( L2021, L5001 );
inv U1315 ( L5286, L5292 );
nand2 U1316 ( L5286, L5293, L5295 );
inv U1317 ( L5379, L5383 );
inv U1318 ( L5389, L5393 );
nand2 U1319 ( L5389, L5392, L5394 );
and2 U1320 ( L1278, L1301, L1439 );
and3 U1321 ( L1289, L1278, L1318, L1440 );
and4 U1322 ( L1307, L1278, L1324, L1289, L1441 );
and4 U1323 ( L1730, L1704, L1749, L1712, L1847 );
and2 U1324 ( L1023, L1046, L1168 );
and3 U1325 ( L1034, L1023, L1064, L1169 );
and4 U1326 ( L1052, L1023, L1071, L1034, L1170 );
and4 U1327 ( L1984, L1958, L2001, L1966, L2117 );
inv U1328 ( L1080, L1086 );
and4 U1329 ( L1034, L1080, L1052, L1023, L1166 );
and2 U1330 ( L1034, L1064, L1171 );
and3 U1331 ( L1052, L1071, L1034, L1172 );
and3 U1332 ( L1080, L1052, L1034, L1173 );
and2 U1333 ( L1034, L1064, L1174 );
and3 U1334 ( L1071, L1052, L1034, L1175 );
and2 U1335 ( L1052, L1071, L1176 );
and2 U1336 ( L1080, L1052, L1177 );
and2 U1337 ( L1052, L1071, L1178 );
and5 U1338 ( L1100, L1152, L1116, L1089, L1134, L1179 );
and2 U1339 ( L1089, L1111, L1181 );
and3 U1340 ( L1100, L1089, L1128, L1182 );
and4 U1341 ( L1116, L1089, L1145, L1100, L1183 );
and5 U1342 ( L1134, L1116, L1089, L1160, L1100, L1184 );
and2 U1343 ( L1100, L1128, L1188 );
and3 U1344 ( L1116, L1145, L1100, L1189 );
and4 U1345 ( L1134, L1116, L1160, L1100, L1190 );
and5 U1346 ( L4, L1152, L1116, L1134, L1100, L1191 );
and2 U1347 ( L1145, L1116, L1192 );
and3 U1348 ( L1134, L1116, L1160, L1193 );
and4 U1349 ( L4, L1152, L1116, L1134, L1194 );
and2 U1350 ( L1134, L1160, L1195 );
and3 U1351 ( L4, L1152, L1134, L1196 );
and2 U1352 ( L4, L1152, L1197 );
and4 U1353 ( L1422, L1307, L1289, L1278, L1437 );
and2 U1354 ( L1289, L1318, L1442 );
and3 U1355 ( L1307, L1324, L1289, L1443 );
and3 U1356 ( L1422, L1307, L1289, L1444 );
and2 U1357 ( L1289, L1318, L1445 );
and3 U1358 ( L1307, L1324, L1289, L1446 );
and2 U1359 ( L1307, L1324, L1447 );
and5 U1360 ( L1430, L1390, L1365, L1344, L1332, L1451 );
and2 U1361 ( L1332, L1359, L1454 );
and3 U1362 ( L1344, L1332, L1382, L1455 );
and4 U1363 ( L1365, L1332, L1404, L1344, L1456 );
and5 U1364 ( L1390, L1365, L1332, L1412, L1344, L1457 );
and2 U1365 ( L1344, L1382, L1465 );
and3 U1366 ( L1365, L1404, L1344, L1466 );
and4 U1367 ( L1390, L1365, L1412, L1344, L1467 );
and4 U1368 ( L1430, L1365, L1344, L1390, L1468 );
and2 U1369 ( L1344, L1382, L1469 );
and3 U1370 ( L1365, L1404, L1344, L1470 );
and4 U1371 ( L1390, L1365, L1412, L1344, L1471 );
and2 U1372 ( L1365, L1404, L1472 );
and3 U1373 ( L1390, L1365, L1412, L1473 );
and3 U1374 ( L1430, L1365, L1390, L1474 );
and2 U1375 ( L1365, L1404, L1475 );
and3 U1376 ( L1390, L1365, L1412, L1476 );
and2 U1377 ( L1390, L1412, L1477 );
and2 U1378 ( L1422, L1307, L1481 );
and2 U1379 ( L1430, L1390, L1482 );
inv U1380 ( L1758, L1764 );
and4 U1381 ( L1712, L1758, L1730, L1704, L1843 );
and3 U1382 ( L1730, L1749, L1712, L1850 );
and3 U1383 ( L1758, L1730, L1712, L1851 );
and3 U1384 ( L1749, L1730, L1712, L1853 );
and2 U1385 ( L1730, L1749, L1854 );
and2 U1386 ( L1758, L1730, L1855 );
and2 U1387 ( L1730, L1749, L1856 );
and5 U1388 ( L1778, L1829, L1794, L1767, L1812, L1857 );
and2 U1389 ( L1767, L1789, L1859 );
and3 U1390 ( L1778, L1767, L1806, L1860 );
and4 U1391 ( L1794, L1767, L1823, L1778, L1861 );
and5 U1392 ( L1812, L1794, L1767, L1837, L1778, L1862 );
and3 U1393 ( L1794, L1823, L1778, L1867 );
and4 U1394 ( L1812, L1794, L1837, L1778, L1868 );
and5 U1395 ( L54, L1829, L1794, L1812, L1778, L1869 );
and2 U1396 ( L1823, L1794, L1870 );
and3 U1397 ( L1812, L1794, L1837, L1871 );
and4 U1398 ( L54, L1829, L1794, L1812, L1872 );
and2 U1399 ( L1812, L1837, L1873 );
and3 U1400 ( L54, L1829, L1812, L1874 );
nand2 U1401 ( L1876, L1877, L1878 );
and4 U1402 ( L2099, L1984, L1966, L1958, L2113 );
and3 U1403 ( L1984, L2001, L1966, L2120 );
and3 U1404 ( L2099, L1984, L1966, L2121 );
and3 U1405 ( L1984, L2001, L1966, L2123 );
and2 U1406 ( L1984, L2001, L2124 );
and5 U1407 ( L2106, L2067, L2042, L2021, L2009, L2128 );
and2 U1408 ( L2009, L2036, L2131 );
and3 U1409 ( L2021, L2009, L2059, L2132 );
and4 U1410 ( L2042, L2009, L2081, L2021, L2133 );
and5 U1411 ( L2067, L2042, L2009, L2089, L2021, L2134 );
and3 U1412 ( L2042, L2081, L2021, L2143 );
and4 U1413 ( L2067, L2042, L2089, L2021, L2144 );
and4 U1414 ( L2106, L2042, L2021, L2067, L2145 );
and3 U1415 ( L2042, L2081, L2021, L2147 );
and4 U1416 ( L2067, L2042, L2089, L2021, L2148 );
and2 U1417 ( L2042, L2081, L2149 );
and3 U1418 ( L2067, L2042, L2089, L2150 );
and3 U1419 ( L2106, L2042, L2067, L2151 );
and2 U1420 ( L2042, L2081, L2152 );
and3 U1421 ( L2067, L2042, L2089, L2153 );
and2 U1422 ( L2067, L2089, L2154 );
and2 U1423 ( L2099, L1984, L2158 );
and2 U1424 ( L2106, L2067, L2159 );
inv U1425 ( L3445, L3449 );
inv U1426 ( L3454, L3458 );
inv U1427 ( L3468, L3472 );
inv U1428 ( L3477, L3481 );
buffer U1429 ( L3463, L3497 );
buffer U1430 ( L3463, L3501 );
buffer U1431 ( L3486, L3505 );
buffer U1432 ( L3486, L3509 );
nand2 U1433 ( L5239, L5242, L3531 );
inv U1434 ( L5422, L5428 );
nand2 U1435 ( L5422, L5429, L3967 );
buffer U1436 ( L1152, L4191 );
buffer U1437 ( L1023, L4199 );
buffer U1438 ( L1023, L4207 );
buffer U1439 ( L1034, L4215 );
buffer U1440 ( L1034, L4223 );
buffer U1441 ( L1052, L4231 );
buffer U1442 ( L1052, L4239 );
buffer U1443 ( L1089, L4247 );
buffer U1444 ( L1100, L4255 );
buffer U1445 ( L1116, L4263 );
buffer U1446 ( L1134, L4271 );
buffer U1447 ( L1422, L4371 );
buffer U1448 ( L1307, L4381 );
buffer U1449 ( L1278, L4391 );
buffer U1450 ( L1289, L4401 );
buffer U1451 ( L1422, L4429 );
buffer U1452 ( L1307, L4439 );
buffer U1453 ( L1278, L4449 );
buffer U1454 ( L1289, L4459 );
buffer U1455 ( L1430, L4497 );
buffer U1456 ( L1390, L4507 );
buffer U1457 ( L1332, L4517 );
buffer U1458 ( L1365, L4527 );
buffer U1459 ( L1344, L4537 );
buffer U1460 ( L1344, L4547 );
buffer U1461 ( L1430, L4585 );
buffer U1462 ( L1390, L4595 );
buffer U1463 ( L1332, L4605 );
buffer U1464 ( L1365, L4615 );
buffer U1465 ( L1730, L4719 );
buffer U1466 ( L1730, L4727 );
buffer U1467 ( L1767, L4735 );
buffer U1468 ( L1794, L4751 );
buffer U1469 ( L1812, L4759 );
buffer U1470 ( L2099, L4835 );
buffer U1471 ( L1984, L4845 );
buffer U1472 ( L2099, L4893 );
buffer U1473 ( L1984, L4903 );
buffer U1474 ( L2067, L4961 );
buffer U1475 ( L2009, L4971 );
buffer U1476 ( L2042, L4981 );
buffer U1477 ( L2067, L5049 );
buffer U1478 ( L2009, L5059 );
buffer U1479 ( L2042, L5069 );
inv U1480 ( L5216, L5222 );
inv U1481 ( L5219, L5223 );
inv U1482 ( L5226, L5232 );
inv U1483 ( L5229, L5233 );
nand2 U1484 ( L5289, L5292, L5294 );
nand2 U1485 ( L5386, L5393, L5395 );
or4 U1486 ( L1286, L1439, L1440, L1441, L589 );
or4 U1487 ( L3167, L1845, L1846, L1847, L616 );
or4 U1488 ( L1031, L1168, L1169, L1170, L619 );
or4 U1489 ( L3167, L2115, L2116, L2117, L627 );
or5 U1490 ( L1097, L1181, L1182, L1183, L1184, L1185 );
or2 U1491 ( L1318, L1447, L1448 );
or5 U1492 ( L1341, L1454, L1455, L1456, L1457, L1458 );
or2 U1493 ( L1404, L1477, L1478 );
or5 U1494 ( L1775, L1859, L1860, L1861, L1862, L1863 );
inv U1495 ( L4743, L4747 );
or2 U1496 ( L1995, L2124, L2125 );
or5 U1497 ( L2018, L2131, L2132, L2133, L2134, L2135 );
or2 U1498 ( L2081, L2154, L2155 );
inv U1499 ( L4991, L4995 );
inv U1500 ( L5001, L5005 );
nand2 U1501 ( L3531, L3532, L3533 );
inv U1502 ( L3918, L3921 );
inv U1503 ( L3922, L3925 );
inv U1504 ( L3926, L3929 );
inv U1505 ( L3930, L3933 );
and3 U1506 ( L3862, L3853, L3918, L3943 );
and3 U1507 ( L3866, L3857, L3922, L3946 );
and3 U1508 ( L3883, L3874, L3926, L3949 );
and3 U1509 ( L3887, L3878, L3930, L3952 );
nand2 U1510 ( L5425, L5428, L3966 );
nand2 U1511 ( L4104, L132, L4107 );
or4 U1512 ( L1046, L1171, L1172, L1173, L4196 );
nor3 U1513 ( L1046, L1174, L1175, L4204 );
or3 U1514 ( L1064, L1176, L1177, L4212 );
nor2 U1515 ( L1064, L1178, L4220 );
or5 U1516 ( L1111, L1188, L1189, L1190, L1191, L4244 );
or4 U1517 ( L1128, L1192, L1193, L1194, L4252 );
or3 U1518 ( L1145, L1195, L1196, L4260 );
or2 U1519 ( L1160, L1197, L4268 );
or4 U1520 ( L1301, L1442, L1443, L1444, L4361 );
nor3 U1521 ( L1301, L1445, L1446, L4419 );
or4 U1522 ( L1382, L1472, L1473, L1474, L4467 );
or5 U1523 ( L1359, L1465, L1466, L1467, L1468, L4487 );
nor3 U1524 ( L1382, L1475, L1476, L4555 );
nor4 U1525 ( L1359, L1469, L1470, L1471, L4575 );
or4 U1526 ( L1724, L1849, L1850, L1851, L4684 );
nor3 U1527 ( L1724, L1852, L1853, L4692 );
or3 U1528 ( L1742, L1854, L1855, L4700 );
nor2 U1529 ( L1742, L1856, L4708 );
or5 U1530 ( L1789, L1866, L1867, L1868, L1869, L4732 );
or4 U1531 ( L1806, L1870, L1871, L1872, L4740 );
or3 U1532 ( L1823, L1873, L1874, L4748 );
or4 U1533 ( L1978, L2119, L2120, L2121, L4825 );
nor3 U1534 ( L1978, L2122, L2123, L4883 );
or4 U1535 ( L2059, L2149, L2150, L2151, L4928 );
or5 U1536 ( L2036, L2142, L2143, L2144, L2145, L4941 );
nor3 U1537 ( L2059, L2152, L2153, L5009 );
nor4 U1538 ( L2036, L2146, L2147, L2148, L5029 );
nand2 U1539 ( L5219, L5222, L5224 );
nand2 U1540 ( L5216, L5223, L5225 );
nand2 U1541 ( L5229, L5232, L5234 );
nand2 U1542 ( L5226, L5233, L5235 );
nand2 U1543 ( L5294, L5295, L5376 );
nand2 U1544 ( L5394, L5395, L5417 );
inv U1545 ( L1878, L576 );
and2 U1546 ( L1437, L1451, L588 );
and2 U1547 ( L1843, L1857, L615 );
and2 U1548 ( L2113, L2128, L626 );
and2 U1549 ( L1166, L1179, L632 );
nand2 U1550 ( L4191, L4194, L1198 );
inv U1551 ( L4191, L4195 );
inv U1552 ( L4199, L4203 );
inv U1553 ( L4207, L4211 );
inv U1554 ( L4215, L4219 );
inv U1555 ( L4223, L4227 );
nand2 U1556 ( L4231, L4234, L1217 );
inv U1557 ( L4231, L4235 );
nand2 U1558 ( L4239, L4242, L1221 );
inv U1559 ( L4239, L4243 );
and2 U1560 ( L1179, L4, L1224 );
inv U1561 ( L4247, L4251 );
inv U1562 ( L4255, L4259 );
inv U1563 ( L4263, L4267 );
inv U1564 ( L4271, L4275 );
inv U1565 ( L1451, L1453 );
inv U1566 ( L4401, L4405 );
inv U1567 ( L4459, L4463 );
inv U1568 ( L4537, L4541 );
inv U1569 ( L4547, L4551 );
nand2 U1570 ( L4719, L4722, L1895 );
inv U1571 ( L4719, L4723 );
nand2 U1572 ( L4727, L4730, L1899 );
inv U1573 ( L4727, L4731 );
and2 U1574 ( L1857, L54, L1902 );
inv U1575 ( L4735, L4739 );
inv U1576 ( L4751, L4755 );
nand2 U1577 ( L4759, L4762, L1929 );
inv U1578 ( L4759, L4763 );
inv U1579 ( L2128, L2130 );
inv U1580 ( L3497, L3500 );
inv U1581 ( L3501, L3504 );
inv U1582 ( L3505, L3508 );
inv U1583 ( L3509, L3512 );
and3 U1584 ( L3454, L3445, L3497, L3520 );
and3 U1585 ( L3458, L3449, L3501, L3523 );
and3 U1586 ( L3477, L3468, L3505, L3526 );
and3 U1587 ( L3481, L3472, L3509, L3529 );
buffer U1588 ( L3533, L1002 );
and3 U1589 ( L1878, L3795, L3823, L3837 );
and3 U1590 ( L3857, L3862, L3921, L3942 );
and3 U1591 ( L3853, L3866, L3925, L3945 );
and3 U1592 ( L3878, L3883, L3929, L3948 );
and3 U1593 ( L3874, L3887, L3933, L3951 );
nand2 U1594 ( L3966, L3967, L3968 );
inv U1595 ( L4371, L4375 );
inv U1596 ( L4381, L4385 );
inv U1597 ( L4391, L4395 );
inv U1598 ( L4429, L4433 );
inv U1599 ( L4439, L4443 );
inv U1600 ( L4449, L4453 );
inv U1601 ( L4497, L4501 );
inv U1602 ( L4507, L4511 );
inv U1603 ( L4517, L4521 );
inv U1604 ( L4527, L4531 );
inv U1605 ( L4615, L4619 );
inv U1606 ( L4585, L4589 );
inv U1607 ( L4595, L4599 );
inv U1608 ( L4605, L4609 );
inv U1609 ( L4835, L4839 );
inv U1610 ( L4845, L4849 );
inv U1611 ( L4893, L4897 );
inv U1612 ( L4903, L4907 );
inv U1613 ( L4961, L4965 );
inv U1614 ( L4971, L4975 );
inv U1615 ( L4981, L4985 );
inv U1616 ( L5069, L5073 );
inv U1617 ( L5049, L5053 );
inv U1618 ( L5059, L5063 );
nand2 U1619 ( L5224, L5225, L5247 );
nand2 U1620 ( L5234, L5235, L5255 );
and2 U1621 ( L1437, L1458, L590 );
and2 U1622 ( L1863, L1843, L617 );
and2 U1623 ( L1185, L1166, L620 );
and2 U1624 ( L2113, L2135, L628 );
inv U1625 ( L3533, L3535 );
nand2 U1626 ( L4188, L4195, L1199 );
inv U1627 ( L4196, L4202 );
nand2 U1628 ( L4196, L4203, L1204 );
inv U1629 ( L4204, L4210 );
nand2 U1630 ( L4204, L4211, L1207 );
inv U1631 ( L4212, L4218 );
nand2 U1632 ( L4212, L4219, L1211 );
inv U1633 ( L4220, L4226 );
nand2 U1634 ( L4220, L4227, L1214 );
nand2 U1635 ( L4228, L4235, L1218 );
nand2 U1636 ( L4236, L4243, L1222 );
or2 U1637 ( L1185, L1224, L1225 );
inv U1638 ( L4244, L4250 );
nand2 U1639 ( L4244, L4251, L1237 );
inv U1640 ( L4252, L4258 );
nand2 U1641 ( L4252, L4259, L1242 );
inv U1642 ( L4260, L4266 );
nand2 U1643 ( L4260, L4267, L1247 );
inv U1644 ( L4268, L4274 );
nand2 U1645 ( L4268, L4275, L1252 );
inv U1646 ( L1458, L1462 );
inv U1647 ( L4684, L4690 );
nand2 U1648 ( L4684, L4691, L1882 );
inv U1649 ( L4692, L4698 );
nand2 U1650 ( L4692, L4699, L1885 );
inv U1651 ( L4700, L4706 );
nand2 U1652 ( L4700, L4707, L1889 );
inv U1653 ( L4708, L4714 );
nand2 U1654 ( L4708, L4715, L1892 );
nand2 U1655 ( L4716, L4723, L1896 );
nand2 U1656 ( L4724, L4731, L1900 );
or2 U1657 ( L1863, L1902, L1903 );
inv U1658 ( L4732, L4738 );
nand2 U1659 ( L4732, L4739, L1915 );
inv U1660 ( L4740, L4746 );
nand2 U1661 ( L4740, L4747, L1920 );
inv U1662 ( L4748, L4754 );
nand2 U1663 ( L4748, L4755, L1925 );
nand2 U1664 ( L4756, L4763, L1930 );
inv U1665 ( L2135, L2139 );
and3 U1666 ( L3449, L3454, L3500, L3519 );
and3 U1667 ( L3445, L3458, L3504, L3522 );
and3 U1668 ( L3472, L3477, L3508, L3525 );
and3 U1669 ( L3468, L3481, L3512, L3528 );
or3 U1670 ( L3836, L3837, L3838, L3848 );
nor2 U1671 ( L3942, L3943, L3944 );
nor2 U1672 ( L3945, L3946, L3947 );
nor2 U1673 ( L3948, L3949, L3950 );
nor2 U1674 ( L3951, L3952, L3953 );
inv U1675 ( L5417, L5421 );
buffer U1676 ( L3968, L1004 );
and2 U1677 ( L4104, L4107, L4111 );
and2 U1678 ( L4107, L132, L4112 );
or2 U1679 ( L1448, L1481, L4351 );
inv U1680 ( L4361, L4365 );
inv U1681 ( L1448, L4409 );
inv U1682 ( L4419, L4423 );
inv U1683 ( L4467, L4471 );
nand2 U1684 ( L4467, L4470, L4472 );
or2 U1685 ( L1478, L1482, L4477 );
inv U1686 ( L4487, L4491 );
inv U1687 ( L4555, L4559 );
nand2 U1688 ( L4555, L4558, L4560 );
inv U1689 ( L1478, L4565 );
inv U1690 ( L4575, L4579 );
or2 U1691 ( L2125, L2158, L4815 );
inv U1692 ( L4825, L4829 );
inv U1693 ( L2125, L4873 );
inv U1694 ( L4883, L4887 );
or2 U1695 ( L2155, L2159, L4931 );
inv U1696 ( L4928, L4934 );
inv U1697 ( L4941, L4945 );
inv U1698 ( L5009, L5013 );
nand2 U1699 ( L5009, L5012, L5014 );
inv U1700 ( L2155, L5019 );
inv U1701 ( L5029, L5033 );
inv U1702 ( L5376, L5382 );
nand2 U1703 ( L5376, L5383, L5385 );
or2 U1704 ( L589, L590, L591 );
or2 U1705 ( L616, L617, L618 );
or2 U1706 ( L619, L620, L621 );
or2 U1707 ( L627, L628, L629 );
inv U1708 ( L3968, L3970 );
nand2 U1709 ( L1198, L1199, L1200 );
nand2 U1710 ( L4199, L4202, L1203 );
nand2 U1711 ( L4207, L4210, L1206 );
nand2 U1712 ( L4215, L4218, L1210 );
nand2 U1713 ( L4223, L4226, L1213 );
nand2 U1714 ( L1217, L1218, L1219 );
nand2 U1715 ( L1221, L1222, L1223 );
nand2 U1716 ( L4247, L4250, L1236 );
nand2 U1717 ( L4255, L4258, L1241 );
nand2 U1718 ( L4263, L4266, L1246 );
nand2 U1719 ( L4271, L4274, L1251 );
nand2 U1720 ( L4687, L4690, L1881 );
nand2 U1721 ( L4695, L4698, L1884 );
nand2 U1722 ( L4703, L4706, L1888 );
nand2 U1723 ( L4711, L4714, L1891 );
nand2 U1724 ( L1895, L1896, L1897 );
nand2 U1725 ( L1899, L1900, L1901 );
nand2 U1726 ( L4735, L4738, L1914 );
nand2 U1727 ( L4743, L4746, L1919 );
nand2 U1728 ( L4751, L4754, L1924 );
nand2 U1729 ( L1929, L1930, L1931 );
nor2 U1730 ( L3519, L3520, L3521 );
nor2 U1731 ( L3522, L3523, L3524 );
nor2 U1732 ( L3525, L3526, L3527 );
nor2 U1733 ( L3528, L3529, L3530 );
inv U1734 ( L5247, L5251 );
inv U1735 ( L5255, L5259 );
or2 U1736 ( L4111, L4112, L4113 );
nand2 U1737 ( L4464, L4471, L4473 );
nand2 U1738 ( L4552, L4559, L4561 );
nand2 U1739 ( L5006, L5013, L5015 );
nand2 U1740 ( L5379, L5382, L5384 );
nand2 U1741 ( L3947, L3944, L5406 );
nand2 U1742 ( L3953, L3950, L5414 );
and3 U1743 ( L3848, L1621, L1645, L1664 );
and3 U1744 ( L3848, L2293, L2316, L2335 );
and3 U1745 ( L3848, L2430, L2454, L718 );
inv U1746 ( L3848, L822 );
and3 U1747 ( L3848, L2488, L2512, L855 );
nand2 U1748 ( L1203, L1204, L1205 );
nand2 U1749 ( L1206, L1207, L1208 );
nand2 U1750 ( L1210, L1211, L1212 );
nand2 U1751 ( L1213, L1214, L1215 );
inv U1752 ( L1219, L1220 );
inv U1753 ( L1225, L1231 );
nand2 U1754 ( L1236, L1237, L1238 );
nand2 U1755 ( L1241, L1242, L1243 );
nand2 U1756 ( L1246, L1247, L1248 );
nand2 U1757 ( L1251, L1252, L1253 );
and2 U1758 ( L1225, L1086, L1272 );
and2 U1759 ( L1462, L1453, L1483 );
nand2 U1760 ( L1881, L1882, L1883 );
nand2 U1761 ( L1884, L1885, L1886 );
nand2 U1762 ( L1888, L1889, L1890 );
nand2 U1763 ( L1891, L1892, L1893 );
inv U1764 ( L1897, L1898 );
inv U1765 ( L1903, L1909 );
nand2 U1766 ( L1914, L1915, L1916 );
nand2 U1767 ( L1919, L1920, L1921 );
nand2 U1768 ( L1924, L1925, L1926 );
and2 U1769 ( L1903, L1764, L1953 );
and2 U1770 ( L2139, L2130, L2160 );
inv U1771 ( L4351, L4355 );
nand2 U1772 ( L4351, L4354, L4356 );
inv U1773 ( L4409, L4413 );
nand2 U1774 ( L4409, L4412, L4414 );
nand2 U1775 ( L4472, L4473, L4474 );
inv U1776 ( L4477, L4481 );
nand2 U1777 ( L4560, L4561, L4562 );
inv U1778 ( L4565, L4569 );
inv U1779 ( L4815, L4819 );
nand2 U1780 ( L4815, L4818, L4820 );
inv U1781 ( L4873, L4877 );
nand2 U1782 ( L4873, L4876, L4878 );
inv U1783 ( L4931, L4935 );
nand2 U1784 ( L4931, L4934, L4936 );
nand2 U1785 ( L5014, L5015, L5016 );
inv U1786 ( L5019, L5023 );
nand2 U1787 ( L3524, L3521, L5244 );
nand2 U1788 ( L3530, L3527, L5252 );
nand2 U1789 ( L5384, L5385, L5409 );
inv U1790 ( L1200, L566 );
inv U1791 ( L1931, L577 );
and3 U1792 ( L4113, L3724, L3721, L3733 );
inv U1793 ( L1208, L1209 );
inv U1794 ( L1215, L1216 );
and2 U1795 ( L1225, L1205, L1257 );
and2 U1796 ( L1225, L1212, L1262 );
and2 U1797 ( L1225, L1220, L1267 );
inv U1798 ( L1886, L1887 );
inv U1799 ( L1893, L1894 );
and2 U1800 ( L1903, L1883, L1935 );
and2 U1801 ( L1903, L1890, L1943 );
and2 U1802 ( L1903, L1898, L1948 );
and3 U1803 ( L1200, L3737, L3765, L3779 );
and3 U1804 ( L1931, L3795, L3823, L3840 );
inv U1805 ( L5406, L5412 );
inv U1806 ( L5414, L5420 );
nand2 U1807 ( L5414, L5421, L3964 );
nand2 U1808 ( L4348, L4355, L4357 );
nand2 U1809 ( L4406, L4413, L4415 );
nand2 U1810 ( L4812, L4819, L4821 );
nand2 U1811 ( L4870, L4877, L4879 );
nand2 U1812 ( L4928, L4935, L4937 );
inv U1813 ( L1253, L567 );
inv U1814 ( L1248, L568 );
inv U1815 ( L1243, L569 );
inv U1816 ( L1238, L570 );
inv U1817 ( L1926, L578 );
inv U1818 ( L1921, L579 );
inv U1819 ( L1916, L580 );
and2 U1820 ( L1209, L1231, L1256 );
and2 U1821 ( L1216, L1231, L1261 );
and2 U1822 ( L1223, L1231, L1266 );
and2 U1823 ( L1080, L1231, L1271 );
inv U1824 ( L1483, L1486 );
and2 U1825 ( L1887, L1909, L1934 );
and2 U1826 ( L1894, L1909, L1942 );
and2 U1827 ( L1901, L1909, L1947 );
and2 U1828 ( L1758, L1909, L1952 );
inv U1829 ( L2160, L2163 );
inv U1830 ( L5244, L5250 );
nand2 U1831 ( L5244, L5251, L3537 );
inv U1832 ( L5252, L5258 );
nand2 U1833 ( L5252, L5259, L3542 );
and3 U1834 ( L1253, L3737, L3765, L3782 );
and3 U1835 ( L1248, L3737, L3765, L3785 );
and3 U1836 ( L1243, L3737, L3765, L3788 );
or3 U1837 ( L3778, L3779, L3780, L3790 );
and3 U1838 ( L1926, L3795, L3823, L3843 );
and3 U1839 ( L1921, L3795, L3823, L3846 );
or3 U1840 ( L3839, L3840, L3841, L3849 );
nand2 U1841 ( L5409, L5412, L3960 );
inv U1842 ( L5409, L5413 );
nand2 U1843 ( L5417, L5420, L3963 );
and3 U1844 ( L1238, L3972, L3998, L4010 );
and3 U1845 ( L1916, L4030, L4056, L4068 );
nand2 U1846 ( L4356, L4357, L4358 );
nand2 U1847 ( L4414, L4415, L4416 );
inv U1848 ( L4474, L4480 );
nand2 U1849 ( L4474, L4481, L4483 );
inv U1850 ( L4562, L4568 );
nand2 U1851 ( L4562, L4569, L4571 );
nand2 U1852 ( L4820, L4821, L4822 );
nand2 U1853 ( L4878, L4879, L4880 );
nand2 U1854 ( L4936, L4937, L4938 );
inv U1855 ( L5016, L5022 );
nand2 U1856 ( L5016, L5023, L5025 );
or2 U1857 ( L1256, L1257, L1258 );
or2 U1858 ( L1261, L1262, L1263 );
or2 U1859 ( L1266, L1267, L1268 );
or2 U1860 ( L1271, L1272, L1273 );
or2 U1861 ( L1934, L1935, L1936 );
or2 U1862 ( L1942, L1943, L1944 );
or2 U1863 ( L1947, L1948, L1949 );
or2 U1864 ( L1952, L1953, L1954 );
nand2 U1865 ( L5247, L5250, L3536 );
nand2 U1866 ( L5255, L5258, L3541 );
or3 U1867 ( L3781, L3782, L3783, L3791 );
or3 U1868 ( L3784, L3785, L3786, L3792 );
or3 U1869 ( L3787, L3788, L3789, L3793 );
or3 U1870 ( L3842, L3843, L3844, L3850 );
or3 U1871 ( L3845, L3846, L3847, L3851 );
nand2 U1872 ( L5406, L5413, L3961 );
nand2 U1873 ( L3963, L3964, L3965 );
or3 U1874 ( L4009, L4010, L4011, L4024 );
or3 U1875 ( L4067, L4068, L4069, L4082 );
nand2 U1876 ( L4477, L4480, L4482 );
nand2 U1877 ( L4565, L4568, L4570 );
nand2 U1878 ( L5019, L5022, L5024 );
and3 U1879 ( L3790, L1609, L1645, L1666 );
and3 U1880 ( L3849, L1621, L1645, L1670 );
and3 U1881 ( L3790, L2281, L2316, L2337 );
and3 U1882 ( L3849, L2293, L2316, L2341 );
and3 U1883 ( L3790, L2418, L2454, L719 );
and3 U1884 ( L3849, L2430, L2454, L758 );
and3 U1885 ( L3849, L2488, L2512, L798 );
inv U1886 ( L3849, L838 );
and3 U1887 ( L3790, L2476, L2512, L856 );
inv U1888 ( L3790, L861 );
nand2 U1889 ( L3536, L3537, L3538 );
nand2 U1890 ( L3541, L3542, L3543 );
nand2 U1891 ( L3960, L3961, L3962 );
inv U1892 ( L4358, L4364 );
nand2 U1893 ( L4358, L4365, L4367 );
inv U1894 ( L4416, L4422 );
nand2 U1895 ( L4416, L4423, L4425 );
nand2 U1896 ( L4482, L4483, L4484 );
nand2 U1897 ( L4570, L4571, L4572 );
inv U1898 ( L4822, L4828 );
nand2 U1899 ( L4822, L4829, L4831 );
inv U1900 ( L4880, L4886 );
nand2 U1901 ( L4880, L4887, L4889 );
inv U1902 ( L4938, L4944 );
nand2 U1903 ( L4938, L4945, L4947 );
nand2 U1904 ( L5024, L5025, L5026 );
inv U1905 ( L1273, L571 );
inv U1906 ( L1268, L572 );
inv U1907 ( L1263, L573 );
inv U1908 ( L1258, L574 );
inv U1909 ( L1954, L581 );
inv U1910 ( L1949, L582 );
inv U1911 ( L1944, L583 );
inv U1912 ( L1936, L584 );
inv U1913 ( L1936, L623 );
and3 U1914 ( L4082, L1540, L1564, L1576 );
and3 U1915 ( L4024, L1528, L1564, L1578 );
or4 U1916 ( L1664, L1666, L1667, L1668, L659 );
and3 U1917 ( L3791, L1609, L1645, L1672 );
and3 U1918 ( L3850, L1621, L1645, L1676 );
and3 U1919 ( L3792, L1609, L1645, L1678 );
and3 U1920 ( L3851, L1621, L1645, L1682 );
and3 U1921 ( L3793, L1609, L1645, L1684 );
and3 U1922 ( L4082, L2215, L2238, L2250 );
and3 U1923 ( L4024, L2203, L2238, L2252 );
or4 U1924 ( L2335, L2337, L2338, L2339, L691 );
and3 U1925 ( L3791, L2281, L2316, L2343 );
and3 U1926 ( L3850, L2293, L2316, L2347 );
and3 U1927 ( L3792, L2281, L2316, L2349 );
and3 U1928 ( L3851, L2293, L2316, L2353 );
and3 U1929 ( L3793, L2281, L2316, L2355 );
or4 U1930 ( L718, L719, L720, L721, L722 );
and3 U1931 ( L4082, L3570, L3594, L743 );
and3 U1932 ( L4024, L3558, L3594, L744 );
and3 U1933 ( L3851, L2430, L2454, L748 );
and3 U1934 ( L3793, L2418, L2454, L749 );
and3 U1935 ( L3850, L2430, L2454, L753 );
and3 U1936 ( L3792, L2418, L2454, L754 );
and3 U1937 ( L3791, L2418, L2454, L759 );
and3 U1938 ( L4082, L3672, L3696, L783 );
and3 U1939 ( L4024, L3660, L3696, L784 );
and3 U1940 ( L3851, L2488, L2512, L788 );
and3 U1941 ( L3793, L2476, L2512, L789 );
and3 U1942 ( L3850, L2488, L2512, L793 );
and3 U1943 ( L3792, L2476, L2512, L794 );
and3 U1944 ( L3791, L2476, L2512, L799 );
and3 U1945 ( L1936, L3724, L3717, L3735 );
inv U1946 ( L4082, L832 );
inv U1947 ( L3851, L834 );
inv U1948 ( L3850, L836 );
inv U1949 ( L3965, L3835 );
or4 U1950 ( L855, L856, L857, L858, L859 );
inv U1951 ( L4024, L871 );
inv U1952 ( L3793, L873 );
inv U1953 ( L3792, L875 );
inv U1954 ( L3791, L877 );
buffer U1955 ( L3538, L998 );
buffer U1956 ( L3543, L1000 );
and2 U1957 ( L3965, L3632, L3651 );
and3 U1958 ( L1273, L3972, L3998, L4013 );
and3 U1959 ( L1268, L3972, L3998, L4016 );
and3 U1960 ( L1263, L3972, L3998, L4019 );
and3 U1961 ( L1258, L3972, L3998, L4022 );
and3 U1962 ( L1954, L4030, L4056, L4071 );
and3 U1963 ( L1949, L4030, L4056, L4074 );
and3 U1964 ( L1944, L4030, L4056, L4077 );
and3 U1965 ( L1936, L4030, L4056, L4080 );
nand2 U1966 ( L4113, L1936, L4096 );
nand2 U1967 ( L4361, L4364, L4366 );
nand2 U1968 ( L4419, L4422, L4424 );
nand2 U1969 ( L4825, L4828, L4830 );
nand2 U1970 ( L4883, L4886, L4888 );
nand2 U1971 ( L4941, L4944, L4946 );
and9 U1972 ( L566, L567, L568, L569, L570, L571, L572, L573, L574, L575 );
and9 U1973 ( L576, L577, L578, L579, L580, L581, L582, L583, L584, L585 );
or4 U1974 ( L1576, L1578, L1579, L1580, L640 );
and2 U1975 ( L659, L1606, L661 );
or4 U1976 ( L1670, L1672, L1673, L1674, L662 );
or4 U1977 ( L1676, L1678, L1679, L1680, L665 );
or4 U1978 ( L1682, L1684, L1685, L1686, L668 );
or4 U1979 ( L2250, L2252, L2253, L2254, L674 );
and2 U1980 ( L691, L2279, L693 );
or4 U1981 ( L2341, L2343, L2344, L2345, L694 );
or4 U1982 ( L2347, L2349, L2350, L2351, L697 );
or4 U1983 ( L2353, L2355, L2356, L2357, L700 );
or4 U1984 ( L743, L744, L745, L746, L747 );
or4 U1985 ( L748, L749, L750, L751, L752 );
or4 U1986 ( L753, L754, L755, L756, L757 );
or4 U1987 ( L758, L759, L760, L761, L762 );
or4 U1988 ( L783, L784, L785, L786, L787 );
or4 U1989 ( L788, L789, L790, L791, L792 );
or4 U1990 ( L793, L794, L795, L796, L797 );
or4 U1991 ( L798, L799, L800, L801, L802 );
or4 U1992 ( L3731, L3733, L3734, L3735, L817 );
and3 U1993 ( L3835, L3803, L3823, L839 );
inv U1994 ( L3538, L3540 );
inv U1995 ( L3543, L3545 );
inv U1996 ( L3962, L3777 );
and2 U1997 ( L3962, L3632, L3648 );
or3 U1998 ( L4012, L4013, L4014, L4025 );
or3 U1999 ( L4015, L4016, L4017, L4026 );
or3 U2000 ( L4018, L4019, L4020, L4027 );
or3 U2001 ( L4021, L4022, L4023, L4028 );
or3 U2002 ( L4070, L4071, L4072, L4083 );
or3 U2003 ( L4073, L4074, L4075, L4084 );
or3 U2004 ( L4076, L4077, L4078, L4085 );
or3 U2005 ( L4079, L4080, L4081, L4086 );
nand2 U2006 ( L4366, L4367, L4368 );
nand2 U2007 ( L4424, L4425, L4426 );
inv U2008 ( L4484, L4490 );
nand2 U2009 ( L4484, L4491, L4493 );
inv U2010 ( L4572, L4578 );
nand2 U2011 ( L4572, L4579, L4581 );
nand2 U2012 ( L4830, L4831, L4832 );
nand2 U2013 ( L4888, L4889, L4890 );
nand2 U2014 ( L4946, L4947, L4948 );
inv U2015 ( L5026, L5032 );
nand2 U2016 ( L5026, L5033, L5035 );
and2 U2017 ( L640, L1526, L642 );
and2 U2018 ( L662, L1606, L664 );
and2 U2019 ( L665, L1606, L667 );
and2 U2020 ( L668, L1606, L670 );
and2 U2021 ( L674, L2202, L676 );
and2 U2022 ( L694, L2279, L696 );
and2 U2023 ( L697, L2279, L699 );
and2 U2024 ( L700, L2279, L702 );
and2 U2025 ( L4113, L4096, L811 );
and2 U2026 ( L4096, L1936, L812 );
and2 U2027 ( L816, L817, L818 );
and5 U2028 ( L562, L3540, L3545, L3535, L3970, L853 );
and3 U2029 ( L3777, L3745, L3765, L878 );
nand2 U2030 ( L4487, L4490, L4492 );
nand2 U2031 ( L4575, L4578, L4580 );
nand2 U2032 ( L5029, L5032, L5034 );
and3 U2033 ( L4083, L1540, L1564, L1582 );
and3 U2034 ( L4025, L1528, L1564, L1584 );
and3 U2035 ( L4084, L1540, L1564, L1588 );
and3 U2036 ( L4026, L1528, L1564, L1590 );
and3 U2037 ( L4085, L1540, L1564, L1594 );
and3 U2038 ( L4027, L1528, L1564, L1596 );
and3 U2039 ( L4086, L1540, L1564, L1600 );
and3 U2040 ( L4028, L1528, L1564, L1602 );
and3 U2041 ( L4083, L2215, L2238, L2256 );
and3 U2042 ( L4025, L2203, L2238, L2258 );
and3 U2043 ( L4084, L2215, L2238, L2262 );
and3 U2044 ( L4026, L2203, L2238, L2264 );
and3 U2045 ( L4085, L2215, L2238, L2268 );
and3 U2046 ( L4027, L2203, L2238, L2270 );
and3 U2047 ( L4086, L2215, L2238, L2274 );
and3 U2048 ( L4028, L2203, L2238, L2276 );
and3 U2049 ( L4086, L3672, L3696, L708 );
and3 U2050 ( L4028, L3660, L3696, L709 );
and3 U2051 ( L4086, L3570, L3594, L723 );
and3 U2052 ( L4028, L3558, L3594, L724 );
and3 U2053 ( L4085, L3570, L3594, L728 );
and3 U2054 ( L4027, L3558, L3594, L729 );
and3 U2055 ( L4084, L3570, L3594, L733 );
and3 U2056 ( L4026, L3558, L3594, L734 );
and3 U2057 ( L4083, L3570, L3594, L738 );
and3 U2058 ( L4025, L3558, L3594, L739 );
and3 U2059 ( L4085, L3672, L3696, L768 );
and3 U2060 ( L4027, L3660, L3696, L769 );
and3 U2061 ( L4084, L3672, L3696, L773 );
and3 U2062 ( L4026, L3660, L3696, L774 );
and3 U2063 ( L4083, L3672, L3696, L778 );
and3 U2064 ( L4025, L3660, L3696, L779 );
or2 U2065 ( L811, L812, L813 );
inv U2066 ( L4086, L824 );
inv U2067 ( L4085, L826 );
inv U2068 ( L4084, L828 );
inv U2069 ( L4083, L830 );
and3 U2070 ( L852, L853, L245, L854 );
inv U2071 ( L4028, L863 );
inv U2072 ( L4027, L865 );
inv U2073 ( L4026, L867 );
inv U2074 ( L4025, L869 );
inv U2075 ( L4368, L4374 );
nand2 U2076 ( L4368, L4375, L4377 );
inv U2077 ( L4426, L4432 );
nand2 U2078 ( L4426, L4433, L4435 );
nand2 U2079 ( L4492, L4493, L4494 );
nand2 U2080 ( L4580, L4581, L4582 );
inv U2081 ( L4832, L4838 );
nand2 U2082 ( L4832, L4839, L4841 );
inv U2083 ( L4890, L4896 );
nand2 U2084 ( L4890, L4897, L4899 );
inv U2085 ( L4948, L4954 );
nand2 U2086 ( L4948, L4955, L4957 );
nand2 U2087 ( L5034, L5035, L5036 );
or4 U2088 ( L1582, L1584, L1585, L1586, L643 );
or4 U2089 ( L1588, L1590, L1591, L1592, L646 );
or4 U2090 ( L1594, L1596, L1597, L1598, L649 );
or4 U2091 ( L1600, L1602, L1603, L1604, L652 );
or4 U2092 ( L2256, L2258, L2259, L2260, L677 );
or4 U2093 ( L2262, L2264, L2265, L2266, L680 );
or4 U2094 ( L2268, L2270, L2271, L2272, L683 );
or4 U2095 ( L2274, L2276, L2277, L2278, L686 );
or4 U2096 ( L708, L709, L710, L711, L712 );
or4 U2097 ( L723, L724, L725, L726, L727 );
or4 U2098 ( L728, L729, L730, L731, L732 );
or4 U2099 ( L733, L734, L735, L736, L737 );
or4 U2100 ( L738, L739, L740, L741, L742 );
or4 U2101 ( L768, L769, L770, L771, L772 );
or4 U2102 ( L773, L774, L775, L776, L777 );
or4 U2103 ( L778, L779, L780, L781, L782 );
nand2 U2104 ( L4371, L4374, L4376 );
nand2 U2105 ( L4429, L4432, L4434 );
nand2 U2106 ( L4835, L4838, L4840 );
nand2 U2107 ( L4893, L4896, L4898 );
nand2 U2108 ( L4951, L4954, L4956 );
and2 U2109 ( L643, L1526, L645 );
and2 U2110 ( L646, L1526, L648 );
and2 U2111 ( L649, L1526, L651 );
and2 U2112 ( L652, L1526, L654 );
and2 U2113 ( L677, L2202, L679 );
and2 U2114 ( L680, L2202, L682 );
and2 U2115 ( L683, L2202, L685 );
and2 U2116 ( L686, L2202, L688 );
nand2 U2117 ( L4376, L4377, L4378 );
nand2 U2118 ( L4434, L4435, L4436 );
inv U2119 ( L4494, L4500 );
nand2 U2120 ( L4494, L4501, L4503 );
inv U2121 ( L4582, L4588 );
nand2 U2122 ( L4582, L4589, L4591 );
nand2 U2123 ( L4840, L4841, L4842 );
nand2 U2124 ( L4898, L4899, L4900 );
nand2 U2125 ( L4956, L4957, L4958 );
inv U2126 ( L5036, L5042 );
nand2 U2127 ( L5036, L5043, L5045 );
nand2 U2128 ( L4497, L4500, L4502 );
nand2 U2129 ( L4585, L4588, L4590 );
nand2 U2130 ( L5039, L5042, L5044 );
inv U2131 ( L4378, L4384 );
nand2 U2132 ( L4378, L4385, L4387 );
inv U2133 ( L4436, L4442 );
nand2 U2134 ( L4436, L4443, L4445 );
nand2 U2135 ( L4502, L4503, L4504 );
nand2 U2136 ( L4590, L4591, L4592 );
inv U2137 ( L4842, L4848 );
nand2 U2138 ( L4842, L4849, L4851 );
inv U2139 ( L4900, L4906 );
nand2 U2140 ( L4900, L4907, L4909 );
inv U2141 ( L4958, L4964 );
nand2 U2142 ( L4958, L4965, L4967 );
nand2 U2143 ( L5044, L5045, L5046 );
nand2 U2144 ( L4381, L4384, L4386 );
nand2 U2145 ( L4439, L4442, L4444 );
nand2 U2146 ( L4845, L4848, L4850 );
nand2 U2147 ( L4903, L4906, L4908 );
nand2 U2148 ( L4961, L4964, L4966 );
nand2 U2149 ( L4386, L4387, L4388 );
nand2 U2150 ( L4444, L4445, L4446 );
inv U2151 ( L4504, L4510 );
nand2 U2152 ( L4504, L4511, L4513 );
inv U2153 ( L4592, L4598 );
nand2 U2154 ( L4592, L4599, L4601 );
nand2 U2155 ( L4850, L4851, L4852 );
nand2 U2156 ( L4908, L4909, L4910 );
nand2 U2157 ( L4966, L4967, L4968 );
inv U2158 ( L5046, L5052 );
nand2 U2159 ( L5046, L5053, L5055 );
nand2 U2160 ( L4507, L4510, L4512 );
nand2 U2161 ( L4595, L4598, L4600 );
nand2 U2162 ( L5049, L5052, L5054 );
inv U2163 ( L4388, L4394 );
nand2 U2164 ( L4388, L4395, L4397 );
inv U2165 ( L4446, L4452 );
nand2 U2166 ( L4446, L4453, L4455 );
nand2 U2167 ( L4512, L4513, L4514 );
nand2 U2168 ( L4600, L4601, L4602 );
inv U2169 ( L4852, L4858 );
nand2 U2170 ( L4852, L4859, L4861 );
inv U2171 ( L4910, L4916 );
nand2 U2172 ( L4910, L4917, L4919 );
inv U2173 ( L4968, L4974 );
nand2 U2174 ( L4968, L4975, L4977 );
nand2 U2175 ( L5054, L5055, L5056 );
nand2 U2176 ( L4391, L4394, L4396 );
nand2 U2177 ( L4449, L4452, L4454 );
nand2 U2178 ( L4855, L4858, L4860 );
nand2 U2179 ( L4913, L4916, L4918 );
nand2 U2180 ( L4971, L4974, L4976 );
nand2 U2181 ( L4396, L4397, L4398 );
nand2 U2182 ( L4454, L4455, L4456 );
inv U2183 ( L4514, L4520 );
nand2 U2184 ( L4514, L4521, L4523 );
inv U2185 ( L4602, L4608 );
nand2 U2186 ( L4602, L4609, L4611 );
nand2 U2187 ( L4860, L4861, L4862 );
nand2 U2188 ( L4918, L4919, L4920 );
nand2 U2189 ( L4976, L4977, L4978 );
inv U2190 ( L5056, L5062 );
nand2 U2191 ( L5056, L5063, L5065 );
nand2 U2192 ( L4517, L4520, L4522 );
nand2 U2193 ( L4605, L4608, L4610 );
nand2 U2194 ( L5059, L5062, L5064 );
inv U2195 ( L4398, L4404 );
nand2 U2196 ( L4398, L4405, L1488 );
inv U2197 ( L4456, L4462 );
nand2 U2198 ( L4456, L4463, L1493 );
inv U2199 ( L4862, L4868 );
nand2 U2200 ( L4862, L4869, L2165 );
inv U2201 ( L4920, L4926 );
nand2 U2202 ( L4920, L4927, L2170 );
nand2 U2203 ( L4522, L4523, L4524 );
nand2 U2204 ( L4610, L4611, L4612 );
inv U2205 ( L4978, L4984 );
nand2 U2206 ( L4978, L4985, L4987 );
nand2 U2207 ( L5064, L5065, L5066 );
nand2 U2208 ( L4401, L4404, L1487 );
nand2 U2209 ( L4459, L4462, L1492 );
nand2 U2210 ( L4865, L4868, L2164 );
nand2 U2211 ( L4923, L4926, L2169 );
nand2 U2212 ( L4981, L4984, L4986 );
nand2 U2213 ( L1487, L1488, L1489 );
nand2 U2214 ( L1492, L1493, L1494 );
nand2 U2215 ( L2164, L2165, L2166 );
nand2 U2216 ( L2169, L2170, L2171 );
inv U2217 ( L4524, L4530 );
nand2 U2218 ( L4524, L4531, L4533 );
inv U2219 ( L4612, L4618 );
nand2 U2220 ( L4612, L4619, L4543 );
nand2 U2221 ( L4986, L4987, L4988 );
inv U2222 ( L5066, L5072 );
nand2 U2223 ( L5066, L5073, L4997 );
nand2 U2224 ( L4527, L4530, L4532 );
nand2 U2225 ( L4615, L4618, L4542 );
nand2 U2226 ( L5069, L5072, L4996 );
and3 U2227 ( L1494, L1462, L1502, L1513 );
and3 U2228 ( L1489, L1458, L1502, L1514 );
and3 U2229 ( L1494, L1483, L1497, L1515 );
and3 U2230 ( L1489, L1486, L1497, L1516 );
inv U2231 ( L4988, L4994 );
nand2 U2232 ( L4988, L4995, L2184 );
and3 U2233 ( L2171, L2139, L2179, L2190 );
and3 U2234 ( L2166, L2135, L2179, L2191 );
and3 U2235 ( L2171, L2160, L2174, L2192 );
and3 U2236 ( L2166, L2163, L2174, L2193 );
nand2 U2237 ( L4532, L4533, L4534 );
nand2 U2238 ( L4542, L4543, L4544 );
nand2 U2239 ( L4996, L4997, L4998 );
nand2 U2240 ( L4991, L4994, L2183 );
or4 U2241 ( L1513, L1514, L1515, L1516, L4620 );
or4 U2242 ( L2190, L2191, L2192, L2193, L5074 );
inv U2243 ( L4534, L4540 );
nand2 U2244 ( L4534, L4541, L1507 );
inv U2245 ( L4544, L4550 );
nand2 U2246 ( L4544, L4551, L1510 );
nand2 U2247 ( L2183, L2184, L2185 );
inv U2248 ( L4998, L5004 );
nand2 U2249 ( L4998, L5005, L2187 );
nand2 U2250 ( L4537, L4540, L1506 );
nand2 U2251 ( L4547, L4550, L1509 );
inv U2252 ( L4620, L4626 );
nand2 U2253 ( L5001, L5004, L2186 );
and2 U2254 ( L2174, L2185, L2195 );
inv U2255 ( L5074, L5080 );
nand2 U2256 ( L1506, L1507, L1508 );
nand2 U2257 ( L1509, L1510, L1511 );
nand2 U2258 ( L2186, L2187, L2188 );
inv U2259 ( L1511, L1512 );
and2 U2260 ( L1497, L1508, L1518 );
inv U2261 ( L2188, L2189 );
and2 U2262 ( L1512, L1502, L1517 );
and2 U2263 ( L2189, L2179, L2194 );
or2 U2264 ( L1517, L1518, L4623 );
or2 U2265 ( L2194, L2195, L5077 );
nand2 U2266 ( L4623, L4626, L1519 );
inv U2267 ( L4623, L4627 );
nand2 U2268 ( L5077, L5080, L2196 );
inv U2269 ( L5077, L5081 );
nand2 U2270 ( L4620, L4627, L1520 );
nand2 U2271 ( L5074, L5081, L2197 );
nand2 U2272 ( L1519, L1520, L1521 );
nand2 U2273 ( L2196, L2197, L2198 );
and3 U2274 ( L2198, L3795, L3823, L840 );
and3 U2275 ( L1521, L3737, L3765, L879 );
inv U2276 ( L1521, L1524 );
inv U2277 ( L2198, L2201 );
or4 U2278 ( L839, L840, L841, L842, L843 );
or4 U2279 ( L878, L879, L880, L881, L882 );
and2 U2280 ( L1524, L3628, L3649 );
and2 U2281 ( L2201, L3628, L3652 );
or2 U2282 ( L3648, L3649, L3657 );
or2 U2283 ( L3651, L3652, L3658 );
and2 U2284 ( L3657, L3622, L3636 );
and2 U2285 ( L3658, L3622, L3639 );
and2 U2286 ( L3657, L3622, L3642 );
and2 U2287 ( L3658, L3622, L3645 );
or2 U2288 ( L3636, L3637, L3653 );
or2 U2289 ( L3639, L3640, L3654 );
or2 U2290 ( L3642, L3643, L3655 );
or2 U2291 ( L3645, L3646, L3656 );
and3 U2292 ( L3656, L2430, L2454, L763 );
and3 U2293 ( L3655, L2418, L2454, L764 );
and3 U2294 ( L3656, L2488, L2512, L803 );
and3 U2295 ( L3655, L2476, L2512, L804 );
and3 U2296 ( L3654, L1621, L1645, L1657 );
and3 U2297 ( L3653, L1609, L1645, L1659 );
and3 U2298 ( L3654, L2293, L2316, L2328 );
and3 U2299 ( L3653, L2281, L2316, L2330 );
or4 U2300 ( L1657, L1659, L1660, L1661, L1662 );
or4 U2301 ( L2328, L2330, L2331, L2332, L2333 );
or4 U2302 ( L763, L764, L765, L766, L767 );
or4 U2303 ( L803, L804, L805, L806, L807 );
and2 U2304 ( L1662, L1606, L657 );
and2 U2305 ( L2333, L2279, L689 );
inv U2306 ( L657, L658 );
inv U2307 ( L689, L690 );
endmodule
|
Added c5315/c5315high.v.
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 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520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 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/****************************************************************************
* *
* VERILOG HIGH-LEVEL DESCRIPTION OF THE ISCAS-85 BENCHMARK CIRCUIT c5315 *
* *
* *
* Written by : Hakan Yalcin (hyalcin@cadence.com) *
* Verified by : Jonathan David Hauke (jhauke@eecs.umich.edu) *
* *
* First created: Jan 31, 1997 *
* Last modified: Oct 20, 1998 *
* *
****************************************************************************/
module Circuit5315(
in293, in302, in308, in316, in324, in341, in351,
in361, in299, in307, in315, in323, in331, in338, in348,
in358, in366, in206, in210, in218, in226, in234, in257,
in265, in273, in281, in209, in217, in225, in233, in241,
in264, in272, in280, in288, in54, in4, in2174, in1497,
in332, in335, in479, in490, in503, in514, in523, in534,
in446, in457, in468, in422, in435, in389, in400, in411,
in374, in191, in200, in194, in197, in203, in149, in155,
in188, in182, in161, in170, in164, in167, in173, in146,
in152, in158, in185, in109, in43, in46, in100, in91,
in76, in73, in67, in11, in106, in37, in49, in103,
in40, in20, in17, in70, in61, in123, in52, in121,
in116, in112, in130, in119, in129, in131, in115, in122,
in114, in53, in113, in128, in127, in126, in117, in176,
in179, in14, in64, in248, in251, in242, in254, in3552,
in3550, in3546, in3548, in120, in94, in118, in97, in4091,
in4092, in137, in4090, in4089, in4087, in4088, in1694, in1691,
in1690, in1689, in372, in369, in292, in289, in562, in245,
in552, in556, in559, in386, in132, in23, in80, in25,
in81, in79, in82, in24, in26, in86, in88, in87,
in83, in34, in4115, in135, in3717, in3724, in141, in2358,
in31, in27, in545, in549, in3173, in136, in1, in373,
in145, in2824, in140,
out658, out690, out767, out807, out654, out651, out648,
out645, out642, out670, out667, out664, out661, out688, out685,
out682, out679, out676, out702, out699, out696, out693, out727,
out732, out737, out742, out747, out752, out757, out762, out722,
out712, out772, out777, out782, out787, out792, out797, out802,
out859, out824, out826, out832, out828, out830, out834, out836,
out838, out822, out863, out871, out865, out867, out869, out873,
out875, out877, out861, out629, out591, out618, out615, out621,
out588, out626, out632, out843, out882, out585, out575, out598,
out610, out998, out1002, out1000, out1004, out854, out623, out813,
out818, out707, out715, out639, out673, out636, out820, out717,
out704, out593, out594, out602, out809, out611, out599, out612,
out600, out850, out848, out849, out851, out887, out298, out926,
out892, out973, out993, out144, out601, out847, out815, out634,
out810, out845, out656, out923, out939, out921, out978, out949,
out889, out603, out604, out606);
input
in293, in302, in308, in316, in324, in341, in351,
in361, in299, in307, in315, in323, in331, in338, in348,
in358, in366, in206, in210, in218, in226, in234, in257,
in265, in273, in281, in209, in217, in225, in233, in241,
in264, in272, in280, in288, in54, in4, in2174, in1497,
in332, in335, in479, in490, in503, in514, in523, in534,
in446, in457, in468, in422, in435, in389, in400, in411,
in374, in191, in200, in194, in197, in203, in149, in155,
in188, in182, in161, in170, in164, in167, in173, in146,
in152, in158, in185, in109, in43, in46, in100, in91,
in76, in73, in67, in11, in106, in37, in49, in103,
in40, in20, in17, in70, in61, in123, in52, in121,
in116, in112, in130, in119, in129, in131, in115, in122,
in114, in53, in113, in128, in127, in126, in117, in176,
in179, in14, in64, in248, in251, in242, in254, in3552,
in3550, in3546, in3548, in120, in94, in118, in97, in4091,
in4092, in137, in4090, in4089, in4087, in4088, in1694, in1691,
in1690, in1689, in372, in369, in292, in289, in562, in245,
in552, in556, in559, in386, in132, in23, in80, in25,
in81, in79, in82, in24, in26, in86, in88, in87,
in83, in34, in4115, in135, in3717, in3724, in141, in2358,
in31, in27, in545, in549, in3173, in136, in1, in373,
in145, in2824, in140;
output
out658, out690, out767, out807, out654, out651, out648,
out645, out642, out670, out667, out664, out661, out688, out685,
out682, out679, out676, out702, out699, out696, out693, out727,
out732, out737, out742, out747, out752, out757, out762, out722,
out712, out772, out777, out782, out787, out792, out797, out802,
out859, out824, out826, out832, out828, out830, out834, out836,
out838, out822, out863, out871, out865, out867, out869, out873,
out875, out877, out861, out629, out591, out618, out615, out621,
out588, out626, out632, out843, out882, out585, out575, out598,
out610, out998, out1002, out1000, out1004, out854, out623, out813,
out818, out707, out715, out639, out673, out636, out820, out717,
out704, out593, out594, out602, out809, out611, out599, out612,
out600, out850, out848, out849, out851, out887, out298, out926,
out892, out973, out993, out144, out601, out847, out815, out634,
out810, out845, out656, out923, out939, out921, out978, out949,
out889, out603, out604, out606;
/************************/
wire VDD;
assign VDD = 1'b1;
wire [8:0] X0bus, X1bus, Abus;
wire [8:0] Y0bus, Y1bus, Bbus;
wire CinFX, CinFY;
wire CinParX, CinParY;
wire MuxSelX, MuxSelY;
wire [10:0] MuxSelPF;
wire [8:0] QF1bus, QF2bus, QF3bus, QF4bus;
wire [8:0] WXbus, WYbus;
wire QP1, QP2, QP3, QP4;
wire [7:0] ContLogic;
wire [1:0] ParXin, ParYin;
wire [5:0] ContParChk;
wire [16:0] MiscMuxIn;
wire [7:0] MiscContIn;
wire [8:0] MiscInbus;
wire [1:0] WparX, WparY;
wire [8:0] OF1bus, OF2bus, OF3bus, OF4bus;
wire OP1, OP2, OP3, OP4;
wire SumLogicParXout, SumLogicParYout;
wire CoutFX_in0, CoutFY_in0;
wire PropThruX, PropThruY;
wire [8:0] NotXFbus, NotYFbus;
wire [3:0] ZeroFlagOut;
wire [4:0] ParChkOut;
wire [10:0] MiscMuxOut;
wire [25:0] MiscOutbus;
/************************/
// inputs
assign
X0bus[8:0] = { in293, in302, in308, in316, in324,
VDD, in341, in351, in361 },
X1bus[8:0] = { in299, in307, in315, in323, in331,
in338, in348, in358, in366 };
assign
Y0bus[8:0] = { in206, in210, in218, in226, in234,
in257, in265, in273, in281 },
Y1bus[8:0] = { in209, in217, in225, in233, in241,
in264, in272, in280, in288 };
assign
CinFX = in54, CinFY = in4,
CinParX = in2174, CinParY = in1497;
assign
MuxSelX = in332, MuxSelY = in335;
assign
Abus[8:0] = { VDD, VDD, in479, in490, in503,
in514, in523, in534, VDD };
assign
Bbus[8:0] = { in446, in457, in468, in422, in435,
in389, in400, in411, in374 };
assign
QF1bus[8:0] = { in191, in194, in197, in203, in200,
in149, in155, in188, in182 },
QF2bus[8:0] = { in161, in164, in167, in173, in170,
in146, in152, in158, in185 },
QF3bus[8:0] = { in109, in46, in100, in91, in43,
in76, in73, in67, in11 },
QF4bus[8:0] = { in106, in49, in103, in40, in37,
in20, in17, in70, in61 };
assign
WXbus[8:0] = { in123, in121, in116, in112, in52,
in130, in119, in129, in131 },
WYbus[8:0] = { in115, in114, in53, in113, in122,
in128, in127, in126, in117 };
assign
QP1 = in176, QP2 = in179, QP3 = in14, QP4 = in64;
assign
ContLogic[7:0] = { in248, in251, in242, in254,
in3552, in3550, in3546, in3548 };
assign
WparX[1:0] = { in120, in94 },
WparY[1:0] = { in118, in97 };
assign
MuxSelPF[10:0] = { in4091, in4092, in137, in4090, in4089, in4087,
in4088, in1694, in1691, in1690, in1689 };
assign
ParXin[1:0] = { in372, in369 },
ParYin[1:0] = { in292, in289 };
assign
ContParChk[5:0] = { in562, in245, in552, in556, in559, in386 };
assign
MiscMuxIn[16:0] = { in132, in23, in80, in25, in81,
in79, in82, in24, in26, in86, in83, in88, in88,
in87, in83, in34, in34 };
assign
MiscContIn[7:0] = { in4115, in135, in3717, in3724,
in141, in2358, in31, in27 };
assign
MiscInbus[8:0] = { in545, in549, in3173, in136, in1,
in373, in145, in2824, in140 };
// outputs
assign
out658 = OP1, out690 = OP2, out767 = OP3, out807 = OP4;
assign
{ out654, out651, out648, out645, out642,
out670, out667, out664, out661 } = OF1bus[8:0],
{ out688, out685, out682, out679, out676,
out702, out699, out696, out693 } = OF2bus[8:0],
{ out727, out732, out737, out742, out747,
out752, out757, out762, out722 } = OF3bus[8:0],
{ out712, out772, out777, out782, out787,
out792, out797, out802, out859 } = OF4bus[8:0];
assign
{ out824, out826, out828, out830, out832,
out834, out836, out838, out822 } = NotXFbus[8:0],
{ out863, out865, out867, out869, out871,
out873, out875, out877, out861 } = NotYFbus[8:0];
assign
out629 = CoutFX_in0, out591 = CoutFY_in0,
out618 = CoutFX_in0, out621 = CoutFY_in0;
assign
out615 = PropThruX, out588 = PropThruY,
out626 = PropThruX, out632 = PropThruY;
assign
out843 = SumLogicParXout, out882 = SumLogicParYout;
assign
{ out585, out575, out598, out610 } = ZeroFlagOut[3:0];
assign
{ out998, out1002, out1000, out1004, out854 } = ParChkOut[4:0];
assign
{ out623, out813, out818, out707, out715, out639,
out673, out636, out820, out717, out704 } = MiscMuxOut[10:0];
assign
{ out593, out594, out602, out809, out611, out599,
out612, out600, out850, out848, out849, out851,
out887, out298, out926, out892, out973, out993,
out144, out601, out847, out815, out634, out810,
out845, out656 } = MiscOutbus[25:0];
// identical misc. outputs
assign
out923 = out144, out939 = out993, out921 = out993,
out978 = out993, out949 = out993, out889 = out887,
out603 = out594, out604 = out594, out606 = out602;
/* instantiate top level circuit */
TopLevel5315 Ckt5315( X0bus, X1bus, Abus, Y0bus, Y1bus, Bbus, CinFX, CinFY,
CinParX, CinParY, MuxSelX, MuxSelY, MuxSelPF,
QF1bus, QF2bus, QF3bus, QF4bus, QP1, QP2, QP3, QP4,
WXbus, WYbus, ContLogic, ParXin, ParYin, ContParChk,
MiscMuxIn, MiscContIn, MiscInbus, WparX, WparY,
OF1bus, OF2bus, OF3bus, OF4bus, OP1, OP2, OP3, OP4,
SumLogicParXout, SumLogicParYout, CoutFX_in0, CoutFY_in0,
PropThruX, PropThruY, NotXFbus, NotYFbus, ZeroFlagOut,
ParChkOut, MiscMuxOut, MiscOutbus );
endmodule // Circuit5315
/***************************************************************************/
/***************************************************************************/
module TopLevel5315( X0bus, X1bus, Abus, Y0bus, Y1bus, Bbus, CinFX, CinFY,
CinParX, CinParY, MuxSelX, MuxSelY, MuxSelPF,
QF1bus, QF2bus, QF3bus, QF4bus, QP1, QP2, QP3, QP4,
WXbus, WYbus, ContLogic, ParXin, ParYin, ContParChk,
MiscMuxIn, MiscContIn, MiscInbus, WparX, WparY,
OF1bus, OF2bus, OF3bus, OF4bus, OP1, OP2, OP3, OP4,
SumLogicParXout, SumLogicParYout, CoutFX_in0, CoutFY_in0,
PropThruX, PropThruY, NotFXbus, NotFYbus, ZeroFlagOut,
ParChkOut, MiscMuxOut, MiscOutbus );
input [8:0] X0bus, X1bus, Abus;
input [8:0] Y0bus, Y1bus, Bbus;
input CinFX, CinFY;
input CinParX, CinParY;
input MuxSelX, MuxSelY;
input [10:0] MuxSelPF;
input [8:0] QF1bus, QF2bus, QF3bus, QF4bus;
input QP1, QP2, QP3, QP4;
input [8:0] WXbus, WYbus;
input [1:0] WparX, WparY;
input [7:0] ContLogic;
input [1:0] ParXin, ParYin;
input [5:0] ContParChk;
input [16:0] MiscMuxIn;
input [7:0] MiscContIn;
input [8:0] MiscInbus;
output [8:0] OF1bus, OF2bus, OF3bus, OF4bus;
output OP1, OP2, OP3, OP4;
output SumLogicParXout, SumLogicParYout;
output CoutFX_in0, CoutFY_in0;
output PropThruX, PropThruY;
output [8:0] NotFXbus, NotFYbus;
output [3:0] ZeroFlagOut;
output [4:0] ParChkOut;
output [10:0] MiscMuxOut;
output [25:0] MiscOutbus;
wire [8:0] Xbus, Ybus;
wire [8:0] FXbus, FYbus;
wire [8:0] SumXbus, LogicXbus, SumYbus, LogicYbus;
wire [3:0] ContLogicPar, NotContLogic3_0;
wire [35:0] ContLogicInX, ContLogicInY;
wire Not_SumLogicParX, Not_SumLogicParY;
wire GND;
assign GND = 1'b0;
Mux9bit_2_1 M1( X0bus, X1bus, MuxSelX, Xbus );
Mux9bit_2_1 M2( Y0bus, Y1bus, MuxSelY, Ybus );
assign ContLogicPar[3:0] = ContLogic[7:4];
// parity blocks
CalcParity M3( X0bus, { GND, Abus[7:0] }, Xbus, Abus, WparX,
MuxSelPF[10:9], ContLogicPar, CinParX,
Not_SumLogicParX, SumLogicParXout );
CalcParity M4( Y0bus, Bbus, Ybus, Bbus, WparY,
MuxSelPF[10:9], ContLogicPar, CinParY,
Not_SumLogicParY, SumLogicParYout );
MuxesPar_4 M5( Not_SumLogicParX, Not_SumLogicParY, QP1, QP2, QP3, QP4,
MuxSelPF[8:0], OP1, OP2, OP3, OP4 );
// sum-logic blocks
Invert4 M0( ContLogic[3:0], NotContLogic3_0 );
assign
ContLogicInX[35:0] = { ContLogicPar, ContLogicPar, ContLogicPar,
ContLogicPar, NotContLogic3_0, NotContLogic3_0,
NotContLogic3_0, NotContLogic3_0, ContLogicPar },
ContLogicInY[35:0] = { ContLogicPar, NotContLogic3_0, NotContLogic3_0,
NotContLogic3_0, NotContLogic3_0, NotContLogic3_0,
NotContLogic3_0, NotContLogic3_0, NotContLogic3_0 };
CalcSumLogic M6( X0bus, { GND, Abus[7:0] }, Xbus, Abus, CinFX, WXbus,
ContLogicInX, MuxSelPF[10:9],
LogicXbus, SumXbus, FXbus, CoutFX_in0, PropThruX );
CalcSumLogic M7( Y0bus, Bbus, Ybus, Bbus, CinFY, WYbus,
ContLogicInY, MuxSelPF[10:9],
LogicYbus, SumYbus, FYbus, CoutFY_in0, PropThruY );
MuxesF8bit_4 M8( FXbus, FYbus, QF1bus, QF2bus, QF3bus, QF4bus, MuxSelPF[8:0],
OF1bus, OF2bus, OF3bus, OF4bus );
// other logic
Invert9 M9( FXbus, NotFXbus ),
M10( FYbus, NotFYbus );
ZeroFlags M11( SumXbus, LogicXbus, SumYbus, LogicYbus, ZeroFlagOut );
BusParityChk M12( X0bus, Xbus, Y0bus, Ybus, ParXin, ParYin,
MuxSelX, MuxSelY, ContParChk, ParChkOut );
// miscellaneous logic
MiscLogic M13( MiscMuxIn, MiscContIn, MiscInbus, ContParChk,
Xbus[8], LogicXbus[8], SumXbus[8], WXbus[8],
X1bus[3:0], X1bus[8], X0bus[8], MuxSelPF[8],
MiscMuxOut, MiscOutbus );
endmodule // TopLevel5315
/***************************************************************************
* Module: Mux9bit_2_1
*
* Function: 9-bit 2:1 Muxes
***************************************************************************/
module Mux9bit_2_1( In0, In1, ContIn, Out );
input [8:0] In0, In1;
input ContIn;
output [8:0] Out;
Mux4bit_2_1 Mux9_0( In0[3:0], In1[3:0], ContIn, Out[3:0] ),
Mux9_1( In0[7:4], In1[7:4], ContIn, Out[7:4] );
Mux2_1 Mux9_2( In0[8], In1[8], ContIn, Out[8] );
endmodule // Mux9bit_2_1
/********************************************/
module Mux4bit_2_1( In0, In1, ContIn, Out );
input [3:0] In0, In1;
input ContIn;
output [3:0] Out;
Mux2_1 Mux4_0( In0[0], In1[0], ContIn, Out[0] ),
Mux4_1( In0[1], In1[1], ContIn, Out[1] ),
Mux4_2( In0[2], In1[2], ContIn, Out[2] ),
Mux4_3( In0[3], In1[3], ContIn, Out[3] );
endmodule // Mux4bit_2_1
/***************************************************************************
* Module: CalcParity
*
* Function: calculates the parity of the result (XYsumbus+ABsumbus+CinPar),
* and of (XYlogicbus OPR ABlogicbus), where OPR is a logical operator
* specified by ContLogicPar.
*
* - ContLogicPar is 4 bits wide, so the parity of 16 different logical
* functions can be calculated.
*
***************************************************************************/
module CalcParity( XYlogicbus, ABlogicbus, XYsumbus, ABsumbus, Wpar,
MuxSel, ContLogicPar, CinPar,
NotSumLogicPar, SumLogicParOut );
input [8:0] XYlogicbus, ABlogicbus;
input [8:0] XYsumbus, ABsumbus;
input [1:0] Wpar;
input [1:0] MuxSel;
input [3:0] ContLogicPar;
input CinPar;
output NotSumLogicPar, SumLogicParOut;
LogicParity CalP0( XYlogicbus, ABlogicbus, ContLogicPar, LogicPar );
SumParity CalP1( XYsumbus, ABsumbus, CinPar, SumPar );
Muxes2_Mux4 CalP2( LogicPar, SumPar, Wpar, MuxSel,
NotSumLogicPar, SumLogicParOut );
endmodule // CalcParity
/********************************************/
module LogicParity( XYlogicbus, ABlogicbus, ContLogicPar, LogicPar );
input [8:0] XYlogicbus, ABlogicbus;
input [3:0] ContLogicPar;
output LogicPar;
wire [35:0] ContLogicIn;
wire [8:0] LogicOut;
assign
ContLogicIn[35:0] = { ContLogicPar, ContLogicPar, ContLogicPar,
ContLogicPar, ContLogicPar, ContLogicPar,
ContLogicPar, ContLogicPar, ContLogicPar };
ComputeLogic LP0( XYlogicbus, ABlogicbus, ContLogicIn, LogicOut );
ParityTree9bit LP1( LogicOut, LogicPar );
endmodule // LogicParity
/********************************************/
module ComputeLogic( In1bus, In2bus, ContLogicIn, Outbus );
input [8:0] In1bus, In2bus;
input [35:0] ContLogicIn;
output [8:0] Outbus;
LogicBlock CL0( In1bus[0], In2bus[0], ContLogicIn[3:0], Outbus[0] ),
CL1( In1bus[1], In2bus[1], ContLogicIn[7:4], Outbus[1] ),
CL2( In1bus[2], In2bus[2], ContLogicIn[11:8], Outbus[2] ),
CL3( In1bus[3], In2bus[3], ContLogicIn[15:12], Outbus[3] ),
CL4( In1bus[4], In2bus[4], ContLogicIn[19:16], Outbus[4] ),
CL5( In1bus[5], In2bus[5], ContLogicIn[23:20], Outbus[5] ),
CL6( In1bus[6], In2bus[6], ContLogicIn[27:24], Outbus[6] ),
CL7( In1bus[7], In2bus[7], ContLogicIn[31:28], Outbus[7] ),
CL8( In1bus[8], In2bus[8], ContLogicIn[35:32], Outbus[8] );
endmodule // ComputeLogic
/********************************************
* LogicBlock: implements all 16 functions of
* In1 and In2 as selected by the 4-bit
* ContLogic input.
********************************************/
module LogicBlock( In1, In2, ContLogic, Out );
input In1, In2;
input [3:0] ContLogic;
output Out;
Mux2_1 LB0( ContLogic[0], ContLogic[1], In1, line0),
LB1( ContLogic[2], ContLogic[3], In1, line1);
or2 LB2( .A(In2), .B(line0), .Y(line2) );
nand2 LB3( .A(In2), .B(line1), .Y(line3) );
and2 LB4( .A(line2), .B(line3), .Y(Out) );
endmodule // LogicBlock
/***********************************************************************
* Submodule: SumParity
*
* Function: calculates the parity of the sum (In1bus + In2bus + Cin)
*
* The parity is calculated separately for the lower 5-bit block
* and the upper 4-bit block. In each case, two parities are calculated:
* one with an assumed carry of 0 to that block, and another with 1.
* For the 5-bit block, the correct parity is determined by Cin.
* For the 4-bit block, the carry input Cin as well as the carry from
* the (lower) 5-bit block to the (higher) 4-bit block determine
* the correct parity.
*
************************************************************************/
module SumParity( In1bus, In2bus, Cin, SumPar );
input [8:0] In1bus, In2bus;
input Cin;
output SumPar;
wire [8:0] Genbus, Propbus;
wire [8:0] LocalC0, LocalC1;
GenProp9 SP0( In1bus, In2bus, Genbus, Propbus );
// first caculate the local carries
// (local carries in 8th position are not needed)
GenLocalCarry5 SP1( Genbus[4:0], Propbus[4:0], LocalC0[4:0], LocalC1[4:0] );
GenLocalCarry3 SP2( Genbus[7:5], Propbus[7:5], LocalC0[7:5], LocalC1[7:5] );
SerialParity9nc SP3( { Propbus[4:0], LocalC0[3:0] }, ParLo0 );
SerialParity9c SP4( { Propbus[4:0], LocalC1[3:0] }, ParLo1 );
SerialParity7nc SP5( { Propbus[8:5], LocalC0[7:5] }, ParHi0 );
SerialParity7c SP6( { Propbus[8:5], LocalC1[7:5] }, ParHi1 );
Mux2_1 SP7( ParLo0, ParLo1, Cin, ParLo),
SP8( ParHi0, ParHi1, LocalC0[4], ParHiCin0),
SP9( ParHi0, ParHi1, LocalC1[4], ParHiCin1),
SP10( ParHiCin0, ParHiCin1, Cin, ParHi);
XOR2a SP11( .A(ParLo), .B(ParHi), .Y(SumPar) );
endmodule // SumParity
/********************************************/
module GenProp9( In1bus, In2bus, Gbus, Pbus);
input [8:0] In1bus, In2bus;
output [8:0] Gbus, Pbus;
and2 GP9_0( .A(In1bus[0]), .B(In2bus[0]), .Y(Gbus[0]) ),
GP9_1( .A(In1bus[1]), .B(In2bus[1]), .Y(Gbus[1]) ),
GP9_2( .A(In1bus[2]), .B(In2bus[2]), .Y(Gbus[2]) ),
GP9_3( .A(In1bus[3]), .B(In2bus[3]), .Y(Gbus[3]) ),
GP9_4( .A(In1bus[4]), .B(In2bus[4]), .Y(Gbus[4]) ),
GP9_5( .A(In1bus[5]), .B(In2bus[5]), .Y(Gbus[5]) ),
GP9_6( .A(In1bus[6]), .B(In2bus[6]), .Y(Gbus[6]) ),
GP9_7( .A(In1bus[7]), .B(In2bus[7]), .Y(Gbus[7]) ),
GP9_8( .A(In1bus[8]), .B(In2bus[8]), .Y(Gbus[8]) );
XOR2a GP9_9( .A(In1bus[0]), .B(In2bus[0]), .Y(Pbus[0]) ),
GP9_10( .A(In1bus[1]), .B(In2bus[1]), .Y(Pbus[1]) ),
GP9_11( .A(In1bus[2]), .B(In2bus[2]), .Y(Pbus[2]) ),
GP9_12( .A(In1bus[3]), .B(In2bus[3]), .Y(Pbus[3]) ),
GP9_13( .A(In1bus[4]), .B(In2bus[4]), .Y(Pbus[4]) ),
GP9_14( .A(In1bus[5]), .B(In2bus[5]), .Y(Pbus[5]) ),
GP9_15( .A(In1bus[6]), .B(In2bus[6]), .Y(Pbus[6]) ),
GP9_16( .A(In1bus[7]), .B(In2bus[7]), .Y(Pbus[7]) ),
GP9_17( .A(In1bus[8]), .B(In2bus[8]), .Y(Pbus[8]) );
endmodule // GenProp9
/********************************************/
module GenLocalCarry5( Gbus, Pbus, LocalC0, LocalC1 );
input [4:0] Gbus, Pbus;
output [4:0] LocalC0, LocalC1;
GenLocalCarry4 GLC5_0( Gbus[3:0], Pbus[3:0],
LocalC0[3:0], LocalC1[3:0] );
AND_OR5a GLC5_1( Gbus[4], Pbus[4], Gbus[3], Pbus[3], Gbus[2],
Pbus[2], Gbus[1], Pbus[1], Gbus[0],
LocalC0[4] );
AND_OR6b GLC5_2( Gbus[4], Pbus[4], Gbus[3], Pbus[3], Gbus[2],
Pbus[2], Gbus[1], Pbus[1], Gbus[0], Pbus[0],
LocalC1[4] );
endmodule // GenLocalCarry5
/******************************************************/
module GenLocalCarry4( Gbus, Pbus, LocalC0, LocalC1 );
input [3:0] Gbus, Pbus;
output [3:0] LocalC0, LocalC1;
GenLocalCarry3 GLC4_0( Gbus[2:0], Pbus[2:0],
LocalC0[2:0], LocalC1[2:0] );
AND_OR4a GLC4_1( Gbus[3], Pbus[3], Gbus[2], Pbus[2], Gbus[1],
Pbus[1], Gbus[0], LocalC0[3] );
AND_OR5b GLC4_2( Gbus[3], Pbus[3], Gbus[2], Pbus[2], Gbus[1],
Pbus[1], Gbus[0], Pbus[0], LocalC1[3] );
endmodule // GenLocalCarry4
/******************************************************/
module GenLocalCarry3( Gbus, Pbus, LocalC0, LocalC1 );
input [2:0] Gbus, Pbus;
output [2:0] LocalC0, LocalC1;
assign LocalC0[0] = Gbus[0];
or2 GLC4_0( .A(Gbus[0]), .B(Pbus[0]), .Y(LocalC1[0]) );
AND_OR2 GLC4_1( Gbus[1], Pbus[1], Gbus[0], LocalC0[1] );
AND_OR3b GLC4_2( Gbus[1], Pbus[1], Gbus[0], Pbus[0], LocalC1[1] );
AND_OR3a GLC4_3( Gbus[2], Pbus[2], Gbus[1], Pbus[1], Gbus[0],
LocalC0[2] );
AND_OR4b GLC4_4( Gbus[2], Pbus[2], Gbus[1], Pbus[1], Gbus[0],
Pbus[0], LocalC1[2] );
endmodule // GenLocalCarry3
/******************************************************/
module SerialParity9nc( Inbus, Out);
input [8:0] Inbus;
output Out;
SerialParity7nc SP9nc0( Inbus[6:0], line0 );
XOR2a SP9nc1( .A(Inbus[7]), .B(line0), .Y(line1) ),
SP9nc2( .A(Inbus[8]), .B(line1), .Y(Out) );
endmodule // SerialParity9nc
/******************************************************/
module SerialParity9c( Inbus, Out);
input [8:0] Inbus;
output Out;
// Inbus[6] is inverted in SerialParity7c
SerialParity7c SP9nc0( Inbus[6:0], line0 );
XOR2a SP9nc1( .A(Inbus[7]), .B(line0), .Y(line1) ),
SP9nc2( .A(Inbus[8]), .B(line1), .Y(Out) );
endmodule // SerialParity9c
/******************************************************/
module SerialParity7nc( Inbus, Out);
input [6:0] Inbus;
output Out;
XOR2a SP7nc0( .A(Inbus[0]), .B(Inbus[1]), .Y(line0) ),
SP7nc1( .A(Inbus[2]), .B(line0), .Y(line1) ),
SP7nc2( .A(Inbus[3]), .B(line1), .Y(line2) ),
SP7nc3( .A(Inbus[4]), .B(line2), .Y(line3) ),
SP7nc4( .A(Inbus[5]), .B(line3), .Y(line4) ),
SP7nc5( .A(Inbus[6]), .B(line4), .Y(Out) );
endmodule // SerialParity7nc
/******************************************************/
module SerialParity7c( Inbus, Out);
input [6:0] Inbus;
output Out;
wire [6:0] NewInbus;
// invert one bit to complement the output
// -- Inbus[6] is chosen so the inverter is not on the longest path
inv SP7c0( .A(Inbus[6]), .Y(NewInbus[6]) );
assign NewInbus[5:0] = Inbus[5:0];
SerialParity7nc SP7c2( NewInbus, Out );
endmodule // SerialParity7c
/******************************************************/
module Muxes2_Mux4( LogicPar, SumPar, Wpar, MuxSel,
NotSumLogicPar, SumLogicParOut );
input LogicPar, SumPar;
input [1:0] Wpar, MuxSel;
output NotSumLogicPar, SumLogicParOut;
inv M2M4_0( .A(LogicPar), .Y(NotLogicPar) ),
M2M4_1( .A(SumPar), .Y(NotSumPar) );
Mux2_1 M2M4_2( NotLogicPar, NotSumPar, MuxSel[1], line0 ),
M2M4_3( line0, Wpar[0], MuxSel[0], NotSumLogicPar );
Mux4_1 M2M4_4( LogicPar, Wpar[1], SumPar, 1'b1,
MuxSel[1], MuxSel[0], SumLogicParOut );
endmodule // Muxes2_Mux4
/***************************************************************************
* Module: MuxesPar_4
*
* Function: includes a set of 4 muxes.
* The outputs of two of the muxes can be masked with an AND gate.
*
***************************************************************************/
module MuxesPar_4( ParX, ParY, QP1, QP2, QP3, QP4, MuxSelbus,
OP1, OP2, OP3, OP4 );
input ParX, ParY, QP1, QP2, QP3, QP4;
input [8:0] MuxSelbus;
output OP1, OP2, OP3, OP4;
Muxes4 MP0( ParX, ParY, QP1, QP2, QP3, QP4, MuxSelbus,
NotOP1, NotOP2, OP3, OP4 );
inv MP1( .A(NotOP1), .Y(OP1) ),
MP2( .A(NotOP2), .Y(OP2) );
endmodule // MuxesPar_4
/********************************************/
module Muxes4( InM1, InM2, In1, In2, In3, In4, MuxSelbus,
Out1, Out2, Out3, Out4 );
input InM1, InM2, In1, In2, In3, In4;
input [8:0] MuxSelbus;
output Out1, Out2, Out3, Out4;
Mux4_1 MXS0( InM1, InM2, In1, In2, MuxSelbus[1], MuxSelbus[0], tempOut1 ),
MXS1( InM1, InM2, In1, In2, MuxSelbus[3], MuxSelbus[2], tempOut2 ),
MXS2( InM1, InM2, In3, In4, MuxSelbus[5], MuxSelbus[4], Out3 ),
MXS3( InM1, InM2, In3, In4, MuxSelbus[7], MuxSelbus[6], Out4 );
and2 MXS4( .A(tempOut1), .B(MuxSelbus[8]), .Y(Out1) ),
MXS5( .A(tempOut2), .B(MuxSelbus[8]), .Y(Out2) );
endmodule // Muxes4
/***************************************************************************
* Module: CalcSumLogic
*
* Function: calculates the sum (XYsumbus + ABsumbus + Cin), and
* the logical operation (XYlogicbus OPR ABlogicbus), both of which
* are 9 bits wide.
*
* -Note that the OPR is not uniform for all bit positions; that's why
* it's 36 bits wide, 4 bits for each bit.
*
* -Also computed by the Adder9 module are Cout_in0 and PropThru.
* Cout_in0: the carry-out bit assuming Cin=0
* PropThru: AND of all propagate bits, so it indicates whether
* Cin can propagate all the way through 9 bits.
* (The actual carry output can be calculated by Cout_in0+Cin.PropThru)
*
***************************************************************************/
module CalcSumLogic( XYlogicbus, ABlogicbus, XYsumbus, ABsumbus, Cin, WXYbus,
ContLogicIn, MuxSel,
Logicbus, Sumbus, FXYbus, Cout_in0, PropThru );
input [8:0] XYlogicbus, ABlogicbus;
input [8:0] XYsumbus, ABsumbus;
input Cin;
input [8:0] WXYbus;
input [35:0] ContLogicIn;
input [1:0] MuxSel;
output [8:0] Sumbus, Logicbus;
output [8:0] FXYbus;
output Cout_in0, PropThru;
ComputeLogic CSL0( XYlogicbus, ABlogicbus, ContLogicIn, Logicbus );
Adder9 CSL1( XYsumbus, ABsumbus, Cin, Sumbus, Cout_in0, PropThru );
Mux9bit_4_1 CSL2( Logicbus, WXYbus, Sumbus, { 9'b000000000 },
MuxSel[1], MuxSel[0], FXYbus );
endmodule // CalcSumLogic
/********************************************************************
* Submodule: Adder9
*
* Function: calculates the sum (In1bus + In2bus + Cin).
*
* The structure of this adder is slightly different from the
* one that computes the parity of the result.
* A CLA is used to compute the sum outputs for the lower
* 6 bits. Two sets of sum signals are computed for the upper
* 3 bits: one assuming carry[4]=0, and another assuming carry[4]=1
* The actual carry[4] signal selects the correct sum bits.
*
********************************************************************/
module Adder9 ( In1bus, In2bus, Cin, Sumbus, Cout_in0, PropThru );
input [8:0] In1bus, In2bus;
input Cin;
output [8:0] Sumbus;
output Cout_in0, PropThru;
wire [8:0] Genbus, Propbus;
wire [2:0] LocalHC0, LocalHC1; // for bits # 7-5
wire [4:0] Carry;
wire [5:0] SumH01bus;
GenProp9 Add0( In1bus, In2bus, Genbus, Propbus );
// generate actual carry lines #0-4
// Cout_in0 is the carry for the entire operation with Cin=0
CLAblock Add1( Genbus, Propbus, Cin, Carry, Cout_in0, PropThru );
// generate local carries for bits #7-5
GenLocalCarry3 Add2( Genbus[7:5], Propbus[7:5], LocalHC0, LocalHC1 );
// for bits # 0-5, generate sum directly : prop XOR carry
XOR2a6bit Add3( Propbus[5:0], { Carry[4:0], Cin }, Sumbus[5:0] );
// for bits #6-8, generate two sums, one assuming Carry[4]=0,
// the other assuming Carry[4]=1
XOR2a6bit Add4( { Propbus[8:6], Propbus[8:6] },
{ LocalHC1[2:0], LocalHC0[2:0] }, SumH01bus );
// now choose the correct sums #6-8
Mux2_1 Add5( SumH01bus[0], SumH01bus[3], Carry[4], Sumbus[6] ),
Add6( SumH01bus[1], SumH01bus[4], Carry[4], Sumbus[7] ),
Add7( SumH01bus[2], SumH01bus[5], Carry[4], Sumbus[8] );
endmodule // Adder9
/********************************************/
module CLAblock( Gbus, Pbus, Cin, Carry, Cout_in0, PropThru );
input [8:0] Gbus, Pbus;
input Cin;
output [4:0] Carry;
output Cout_in0, PropThru;
wire LocalC0_4;
// actual carry lines #0-3
AND_OR2 CB0( Gbus[0], Pbus[0], Cin, Carry[0] );
AND_OR3a CB1( Gbus[1], Pbus[1], Gbus[0], Pbus[0], Cin, Carry[1] );
AND_OR4a CB2( Gbus[2], Pbus[2], Gbus[1], Pbus[1], Gbus[0],
Pbus[0], Cin, Carry[2] );
AND_OR5a CB3( Gbus[3], Pbus[3], Gbus[2], Pbus[2], Gbus[1], Pbus[1],
Gbus[0], Pbus[0], Cin, Carry[3] );
// LocalC0_4 is the carry out of bit #4 with Cin=0
AND_OR5a CB4( Gbus[4], Pbus[4], Gbus[3], Pbus[3], Gbus[2], Pbus[2],
Gbus[1], Pbus[1], Gbus[0], LocalC0_4 );
and5 CB5( .A(Pbus[0]), .B(Pbus[1]), .C(Pbus[2]),
.D(Pbus[3]), .E(Pbus[4]), .Y(Prop4_0) );
and2 CB6( .A(Cin), .B(Prop4_0), .Y(PropCin) );
or2 CB7( .A(LocalC0_4), .B(PropCin), .Y(Carry[4]) );
// now Cout_in0 (the carryout line for the entire operation with Cin=0)
AND_OR5a CB8( Gbus[8], Pbus[8], Gbus[7], Pbus[7], Gbus[6], Pbus[6],
Gbus[5], Pbus[5], LocalC0_4, Cout_in0 );
// Propthr: and of all propagate lines
and4 CB9( .A(Pbus[5]), .B(Pbus[6]), .C(Pbus[7]), .D(Pbus[8]),
.Y(Prop8_5) );
and2 CB10( .A(Prop4_0), .B(Prop8_5), .Y(PropThru) );
endmodule // CLAblock
/***************************************************************************
* Module: MuxesF8bit_4
*
* Function: includes four sets of 9-bit Muxes whose inputs are
* FXbus and FYbus, the outputs of the CalcSumLogic modules, and
* input buses QF1, QF2, QF3, QF4.
*
***************************************************************************/
module MuxesF8bit_4( FXbus, FYbus, QF1bus, QF2bus, QF3bus, QF4bus, MuxSelbus,
OF1bus, OF2bus, OF3bus, OF4bus );
input [8:0] FXbus, FYbus, QF1bus, QF2bus, QF3bus, QF4bus;
input [8:0] MuxSelbus;
output [8:0] OF1bus, OF2bus, OF3bus, OF4bus;
MuxesF4bit_4 MF8_0( FXbus[3:0], FYbus[3:0], QF1bus[3:0], QF2bus[3:0],
QF3bus[3:0], QF4bus[3:0], MuxSelbus[8:0],
OF1bus[3:0], OF2bus[3:0], OF3bus[3:0], OF4bus[3:0] ),
MF8_1( FXbus[7:4], FYbus[7:4], QF1bus[7:4], QF2bus[7:4],
QF3bus[7:4], QF4bus[7:4], MuxSelbus[8:0],
OF1bus[7:4], OF2bus[7:4], OF3bus[7:4], OF4bus[7:4] );
Muxes4 MF8_2( FXbus[8], FYbus[8], QF1bus[8], QF2bus[8],
QF3bus[8], QF4bus[8], MuxSelbus[8:0],
OF1bus[8], OF2bus[8], OF3bus[8], OF4bus[8] );
endmodule // MuxesF8bit_4
/********************************************/
module MuxesF4bit_4( FXbus, FYbus, QF1bus, QF2bus, QF3bus, QF4bus, MuxSelbus,
OF1bus, OF2bus, OF3bus, OF4bus );
input [3:0] FXbus, FYbus, QF1bus, QF2bus, QF3bus, QF4bus;
input [8:0] MuxSelbus;
output [3:0] OF1bus, OF2bus, OF3bus, OF4bus;
Muxes4 MF4_0( FXbus[0], FYbus[0], QF1bus[0], QF2bus[0],
QF3bus[0], QF4bus[0], MuxSelbus[8:0],
OF1bus[0], OF2bus[0], OF3bus[0], OF4bus[0] ),
MF4_1( FXbus[1], FYbus[1], QF1bus[1], QF2bus[1],
QF3bus[1], QF4bus[1], MuxSelbus[8:0],
OF1bus[1], OF2bus[1], OF3bus[1], OF4bus[1] ),
MF4_2( FXbus[2], FYbus[2], QF1bus[2], QF2bus[2],
QF3bus[2], QF4bus[2], MuxSelbus[8:0],
OF1bus[2], OF2bus[2], OF3bus[2], OF4bus[2] ),
MF8_3( FXbus[3], FYbus[3], QF1bus[3], QF2bus[3],
QF3bus[3], QF4bus[3], MuxSelbus[8:0],
OF1bus[3], OF2bus[3], OF3bus[3], OF4bus[3] );
endmodule // MuxesF4bit_4
/***************************************************************************
* Module: ZeroFlags
*
* Function: generates the zero signal for four 9-bit buses:
* SumX, LogicX, SumY and LogicY.
* In each case, the zero signal is equal to the NOR of all the inputs.
*
***************************************************************************/
module ZeroFlags( SumX, LogicX, SumY, LogicY, ZeroFlagOut );
input [8:0] SumX, LogicX, SumY, LogicY;
output [3:0] ZeroFlagOut;
NOR9 ZF0( SumX, ZeroFlagOut[3] ),
ZF1( SumY, ZeroFlagOut[2] ),
ZF2( LogicX, ZeroFlagOut[1] ),
ZF3( LogicY, ZeroFlagOut[0] );
endmodule // ZeroFlags
/***************************************************************************
* Module: BusParityChk
*
* Function: computes the parity of four 10-bit buses:
* X0bus, Xbus, Y0bus and Ybus, each with an additional input.
* ParChkOut[0] is the AND of all the bus parities and can be masked
* by ContParChk inputs.
*
***************************************************************************/
module BusParityChk( X0bus, Xbus, Y0bus, Ybus, ParXin, ParYin,
MuxSelX, MuxSelY, ContParChk, ParChkOut );
input [8:0] X0bus, Xbus, Y0bus, Ybus;
input [1:0] ParXin, ParYin;
input MuxSelX, MuxSelY;
input [5:0] ContParChk;
output [4:0] ParChkOut;
wire ParX, ParY;
wire [3:0] NotParChk;
Mux2_1 BPC0( ParXin[0], ParXin[1], MuxSelX, ParX ),
BPC1( ParYin[0], ParYin[1], MuxSelY, ParY );
ParityTree10bit BPC2( { ParX, Xbus[8:0] }, ParChkOut[4] ),
BPC3( { ParXin[0], X0bus[8:0] }, ParChkOut[3] ),
BPC4( { ParY, Ybus[8:0] }, ParChkOut[2] ),
BPC5( { ParYin[0], Y0bus[8:0] }, ParChkOut[1] );
Invert4 BPC6( ParChkOut[4:1], NotParChk );
and5 BPC7( .A(NotParChk[3]), .B(NotParChk[2]), .C(NotParChk[1]),
.D(NotParChk[0]), .E(ContParChk[5]), .Y(line7) );
and4 BPC8( .A(ContParChk[0]), .B(ContParChk[1]), .C(ContParChk[2]),
.D(ContParChk[3]), .Y(line8) );
and3 BPC9( .A(line8), .B(line7), .C(ContParChk[4]),
.Y(ParChkOut[0]) );
endmodule // BusParityChk
/***************************************************************************
* Module: MiscLogic
*
* Function: contains muxes and gates that are mostly unstructured
* and unrelated to the rest of the circuit.
*
* - The MiscMuxLogic block includes four 2:1 and 4:1 muxes with
* independent inputs.
* - The MiscRandomLogic block contains mostly inverters and buffers.
*
***************************************************************************/
module MiscLogic( MiscMuxIn, MiscContIn, MiscInbus, ContParChk,
Xbus_8, LogicXbus_8, SumXbus_8, WXbus_8,
X1bus3_0, X1bus_8, X0bus_8, MuxSelPF_8,
MiscMuxOut, MiscOutbus );
input [16:0] MiscMuxIn;
input [7:0] MiscContIn;
input [8:0] MiscInbus;
input [5:0] ContParChk;
input Xbus_8, LogicXbus_8, SumXbus_8, WXbus_8;
input X1bus_8, X0bus_8, MuxSelPF_8;
input [3:0] X1bus3_0;
output [10:0] MiscMuxOut;
output [25:0] MiscOutbus;
wire ContBeta;
MiscMuxLogic UM13_0( { Xbus_8, LogicXbus_8, SumXbus_8, WXbus_8, MiscMuxIn },
MiscContIn, ContBeta, MiscMuxOut );
MiscRandomLogic UM13_1( { X1bus3_0, X1bus_8, X0bus_8, MuxSelPF_8, MiscInbus },
ContParChk, MiscContIn, ContBeta, MiscOutbus );
endmodule // MiscLogic
/********************************************/
module MiscMuxLogic( NewMuxIn, MiscContIn, ContBeta, MiscMuxOut );
input [20:0] NewMuxIn;
input [7:0] MiscContIn;
output ContBeta;
output [10:0] MiscMuxOut;
wire [3:0] tempOut1, tempOut2, tempOut3;
and2 MML0( .A(MiscContIn[0]), .B(MiscContIn[1]), .Y(ContBeta) );
inv MML1( .A(ContBeta), .Y(NotContBeta) ),
MML2( .A(MiscContIn[2]), .Y(NotContIn2) );
Mux4bit_2_1 MML3( NewMuxIn[3:0], NewMuxIn[7:4], NotContIn2,
tempOut1 );
Mux4bit_4_1 MML4( NewMuxIn[11:8], NewMuxIn[15:12], { 4'b1111 },
{ 4'b1111 }, NotContBeta, MiscContIn[2],
tempOut2 );
// MiscMuxOut[3:0] and MiscMuxOut[7:4]
Mask_And4bit MML5( tempOut1, ContBeta, tempOut3 );
Invert4 MML6( tempOut3, MiscMuxOut[3:0] );
Mask_And4bit MML7( tempOut2, MiscContIn[3], MiscMuxOut[7:4] );
// MiscMuxOut[8] -- out818
inv MML8( .A(NewMuxIn[20]), .Y(NotMuxIn20) );
XOR2b MML9( .A(NotMuxIn20), .B(NewMuxIn[16]), .Y(tempMuxin) );
Mux4_1 MML10( NewMuxIn[19], tempMuxin, NewMuxIn[17], NewMuxIn[18],
MiscContIn[5], MiscContIn[4], tempMuxout );
nand2 MML11( .A(MiscContIn[6]), .B(MiscContIn[7]), .Y(tempMuxcont) );
and2 MML12( .A(tempMuxcont), .B(tempMuxout), .Y(MiscMuxOut[8]) );
// MiscMuxOut[9] -- out813
XOR2b MML13( .A(tempMuxin), .B(NewMuxIn[18]), .Y(MiscMuxOut[9]) );
// MiscMuxOut[10]=not(SumXbus[8]) -- out623
inv MML14( .A(NewMuxIn[18]), .Y(MiscMuxOut[10]) );
endmodule // MiscMuxLogic
/********************************************/
module MiscRandomLogic( NewMiscbus, ContParChk, MiscContIn, ContBeta, MiscOutbus );
input [15:0] NewMiscbus;
input [5:0] ContParChk;
input [7:0] MiscContIn;
input ContBeta;
output [25:0] MiscOutbus;
// NewMiscbus: { X1bus3_0, X1bus_8, X0bus_8, MuxSelPF_8, MiscInbus }
// 15-12 11 10 9 8-0
nand2 MRL0( .A(ContBeta), .B(NewMiscbus[0]), .Y(MiscOutbus[0]) );
inv MRL1( .A(NewMiscbus[1]), .Y(NotMisc1) );
and2 MRL2( .A(NotMisc1), .B(MiscContIn[0]), .Y(line2) );
inv MRL3( .A(line2), .Y(MiscOutbus[1]) );
and2 MRL4( .A(MiscContIn[3]), .B(NewMiscbus[2]), .Y(MiscOutbus[2]) );
nand2 MRL5( .A(NewMiscbus[3]), .B(NewMiscbus[4]), .Y(line6) );
inv MRL6( .A(line6), .Y(MiscOutbus[3]) );
inv MRL7( .A(NewMiscbus[6]), .Y(NotMisc6) );
and2 MRL8( .A(NewMiscbus[5]), .B(NotMisc6), .Y(MiscOutbus[4]) );
and2 MRL9( .A(ContParChk[0]), .B(ContParChk[2]), .Y(line12) );
inv MRL10( .A(line12), .Y(MiscOutbus[5]) );
and2 MRL11( .A(ContParChk[3]), .B(ContParChk[5]), .Y(MiscOutbus[6]) );
Buffer7 MRL12( { NewMiscbus[11:9], NewMiscbus[7:6], NewMiscbus[4],
MiscContIn[3] }, MiscOutbus[13:7] );
Invert4 MRL13( { ContParChk[5:3], ContParChk[1] }, MiscOutbus[17:14] );
Invert4 MRL14( NewMiscbus[15:12], MiscOutbus[21:18] );
Invert4 MRL15( { NewMiscbus[11], NewMiscbus[8:7], ContBeta },
MiscOutbus[25:22] );
endmodule // MiscRandomLogic
/***************************************************************************
* Description of some basic gates/modules
***************************************************************************/
/********************************************/
module ParityTree10bit( Inbus, ParOut );
input [9:0] Inbus;
output ParOut;
XOR2a PT0( .A(Inbus[5]), .B(Inbus[6]), .Y(line0) ),
PT1( .A(Inbus[7]), .B(Inbus[8]), .Y(line1) ),
PT2( .A(Inbus[0]), .B(Inbus[9]), .Y(line2) ),
PT3( .A(Inbus[1]), .B(Inbus[2]), .Y(line3) ),
PT4( .A(Inbus[3]), .B(Inbus[4]), .Y(line4) );
XOR2a PT5( .A(line0), .B(line1), .Y(line5) );
XOR3a PT6( .A(line2), .B(line3), .C(line4), .Y(line6) );
XOR2a PT7( .A(line5), .B(line6), .Y(ParOut) );
endmodule // ParityTree10bit
/********************************************/
module ParityTree9bit( Inbus, ParOut );
input [8:0] Inbus;
output ParOut;
XOR2a PT1( .A(Inbus[5]), .B(Inbus[6]), .Y(line1) ),
PT2( .A(Inbus[7]), .B(Inbus[8]), .Y(line2) ),
PT3( .A(Inbus[1]), .B(Inbus[2]), .Y(line3) ),
PT4( .A(Inbus[3]), .B(Inbus[4]), .Y(line4) );
XOR2a PT5( .A(line1), .B(line2), .Y(line5) );
XOR3a PT6( .A(line3), .B(Inbus[0]), .C(line4), .Y(line6) );
XOR2a PT7( .A(line5), .B(line6), .Y(ParOut) );
endmodule // ParityTree9bit
/********************************************/
module Invert4( Inbus, Outbus );
input [3:0] Inbus;
output [3:0] Outbus;
inv Inv4_0( .A(Inbus[0]), .Y(Outbus[0]) ),
Inv4_1( .A(Inbus[1]), .Y(Outbus[1]) ),
Inv4_2( .A(Inbus[2]), .Y(Outbus[2]) ),
Inv4_3( .A(Inbus[3]), .Y(Outbus[3]) );
endmodule // Invert4
/********************************************/
module Invert9( Inbus, Outbus );
input [8:0] Inbus;
output [8:0] Outbus;
Invert4 Inv9_0( Inbus[3:0], Outbus[3:0] ),
Inv9_1( Inbus[7:4], Outbus[7:4] );
inv Inv9_2( .A(Inbus[8]), .Y(Outbus[8]) );
endmodule // Invert9
/********************************************/
module Buffer7( Inbus, Outbus );
input [6:0] Inbus;
output [6:0] Outbus;
buffer B7_0( .A(Inbus[0]), .Y(Outbus[0]) ),
B7_1( .A(Inbus[1]), .Y(Outbus[1]) ),
B7_2( .A(Inbus[2]), .Y(Outbus[2]) ),
B7_3( .A(Inbus[3]), .Y(Outbus[3]) ),
B7_4( .A(Inbus[4]), .Y(Outbus[4]) ),
B7_5( .A(Inbus[5]), .Y(Outbus[5]) ),
B7_6( .A(Inbus[6]), .Y(Outbus[6]) );
endmodule // Buffer7
/********************************************/
module XOR2a6bit( In1bus, In2bus, Outbus );
input [5:0] In1bus, In2bus;
output [5:0] Outbus;
XOR2a X2a6_0( .A(In1bus[0]), .B(In2bus[0]), .Y(Outbus[0]) ),
X2a6_1( .A(In1bus[1]), .B(In2bus[1]), .Y(Outbus[1]) ),
X2a6_2( .A(In1bus[2]), .B(In2bus[2]), .Y(Outbus[2]) ),
X2a6_3( .A(In1bus[3]), .B(In2bus[3]), .Y(Outbus[3]) ),
X2a6_4( .A(In1bus[4]), .B(In2bus[4]), .Y(Outbus[4]) ),
X2a6_5( .A(In1bus[5]), .B(In2bus[5]), .Y(Outbus[5]) );
endmodule // XOR2a6bit
/********************************************/
module Mux4_1( In0, In1, In2, In3, ContHi, ContLo, Out );
input In0, In1, In2, In3, ContHi, ContLo;
output Out;
inv Mux4_0( .A(ContLo), .Y(Not_ContLo) ),
Mux4_1( .A(ContHi), .Y(Not_ContHi) );
and3 Mux4_2( .A(In0), .B(Not_ContHi), .C(Not_ContLo), .Y(line2) ),
Mux4_3( .A(In1), .B(Not_ContHi), .C(ContLo), .Y(line3) ),
Mux4_4( .A(In2), .B(ContHi), .C(Not_ContLo), .Y(line4) ),
Mux4_5( .A(In3), .B(ContHi), .C(ContLo), .Y(line5) );
or4 Mux4_6( .A(line2), .B(line3), .C(line4), .D(line5), .Y(Out) );
endmodule // Mux4_1
/********************************************/
module Mux2_1( In0, In1, ContIn, Out );
input In0, In1, ContIn;
output Out;
inv Mux2_0( .A(ContIn), .Y(Not_ContIn) );
and2 Mux2_1( .A(In0), .B(Not_ContIn), .Y(line1) ),
Mux2_2( .A(In1), .B(ContIn), .Y(line2) );
or2 Mux2_3( .A(line1), .B(line2), .Y(Out) );
endmodule // Mux2_1
/********************************************/
module Mux9bit_4_1( In1bus, In2bus, In3bus, In4bus,
ContHi, ContLo, Outbus );
input [8:0] In1bus, In2bus, In3bus, In4bus;
input ContHi, ContLo;
output [8:0] Outbus;
Mux4bit_4_1 Mx9_0( In1bus[3:0], In2bus[3:0], In3bus[3:0], In4bus[3:0],
ContHi, ContLo, Outbus[3:0] ),
Mx9_1( In1bus[7:4], In2bus[7:4], In3bus[7:4], In4bus[7:4],
ContHi, ContLo, Outbus[7:4] );
Mux4_1 Mx9_2( In1bus[8], In2bus[8], In3bus[8], In4bus[8],
ContHi, ContLo, Outbus[8] );
endmodule // Mux9bit_4_1
/********************************************/
module Mux4bit_4_1( In1bus, In2bus, In3bus, In4bus,
ContHi, ContLo, Outbus );
input [3:0] In1bus, In2bus, In3bus, In4bus;
input ContHi, ContLo;
output [3:0] Outbus;
Mux4_1 Mx4_0( In1bus[0], In2bus[0], In3bus[0], In4bus[0],
ContHi, ContLo, Outbus[0] ),
Mx4_1( In1bus[1], In2bus[1], In3bus[1], In4bus[1],
ContHi, ContLo, Outbus[1] ),
Mx4_2( In1bus[2], In2bus[2], In3bus[2], In4bus[2],
ContHi, ContLo, Outbus[2] ),
Mx4_3( In1bus[3], In2bus[3], In3bus[3], In4bus[3],
ContHi, ContLo, Outbus[3] );
endmodule // Mux4bit_4_1
/******************************************************/
module Mask_And4bit( Inbus, Mask, Outbus );
input [3:0] Inbus;
input Mask;
output [3:0] Outbus;
and2 Ma0( .A(Inbus[0]), .B(Mask), .Y(Outbus[0]) ),
Ma1( .A(Inbus[1]), .B(Mask), .Y(Outbus[1]) ),
Ma2( .A(Inbus[2]), .B(Mask), .Y(Outbus[2]) ),
Ma3( .A(Inbus[3]), .B(Mask), .Y(Outbus[3]) );
endmodule // AND4bit
/******************************************************/
module AND_OR2( O, P, Q, YY);
input O, P, Q;
output YY;
and2 Ao2_0( .A(P), .B(Q), .Y(line0) );
or2 Ao2_1( .A(O), .B(line0), .Y(YY) );
endmodule // AND_OR2
/******************************************************/
module AND_OR3a( O, P, Q, R, S, YY);
input O, P, Q, R, S;
output YY;
and2 Ao3a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao3a_1( .A(P), .B(R), .C(S), .Y(line1) );
or3 Ao3a_2( .A(O), .B(line0), .C(line1), .Y(YY) );
endmodule // AND_OR3a
/******************************************************/
module AND_OR3b( O, P, Q, R, YY);
input O, P, Q, R;
output YY;
and2 Ao3a_0( .A(P), .B(Q), .Y(line0) );
and2 Ao3a_1( .A(P), .B(R), .Y(line1) );
or3 Ao3a_2( .A(O), .B(line0), .C(line1), .Y(YY) );
endmodule // AND_OR3b
/******************************************************/
module AND_OR4a( O, P, Q, R, S, T, U, YY);
input O, P, Q, R, S, T, U;
output YY;
and2 Ao4a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao4a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao4a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
or4 Ao4a_3( .A(O), .B(line0), .C(line1), .D(line2), .Y(YY) );
endmodule // AND_OR4a
/******************************************************/
module AND_OR4b( O, P, Q, R, S, T, YY);
input O, P, Q, R, S, T;
output YY;
and2 Ao4a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao4a_1( .A(P), .B(R), .C(S), .Y(line1) );
and3 Ao4a_2( .A(P), .B(R), .C(T), .Y(line2) );
or4 Ao4a_3( .A(O), .B(line0), .C(line1), .D(line2), .Y(YY) );
endmodule // AND_OR4a
/******************************************************/
module AND_OR5a( O, P, Q, R, S, T, U, V, W, YY);
input O, P, Q, R, S, T, U, V, W;
output YY;
and2 Ao5a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao5a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao5a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
and5 Ao5a_3( .A(P), .B(R), .C(T), .D(V), .E(W), .Y(line3) );
or5 Ao5a_4( .A(O), .B(line0), .C(line1), .D(line2), .E(line3), .Y(YY) );
endmodule // AND_OR5a
/******************************************************/
module AND_OR5b( O, P, Q, R, S, T, U, V, YY);
input O, P, Q, R, S, T, U, V;
output YY;
and2 Ao5a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao5a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao5a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
and4 Ao5a_3( .A(P), .B(R), .C(T), .D(V), .Y(line3) );
or5 Ao5a_4( .A(O), .B(line0), .C(line1), .D(line2), .E(line3), .Y(YY) );
endmodule // AND_OR5b
/******************************************************/
module AND_OR6a( O, P, Q, R, S, T, U, V, W, X, Y, YY);
input O, P, Q, R, S, T, U, V, W, X, Y;
output YY;
and2 Ao6a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao6a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao6a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
and5 Ao6a_3( .A(P), .B(R), .C(T), .D(V), .E(W), .Y(line3) );
and6 Ao6a_4( .A(P), .B(R), .C(T), .D(V), .E(X), .F(Y), .Y(line4) );
or6 Ao6a_5( .A(O), .B(line0), .C(line1), .D(line2), .E(line3),
.F(line4), .Y(YY) );
endmodule // AND_OR6a
/******************************************************/
module AND_OR6b( O, P, Q, R, S, T, U, V, W, X, YY);
input O, P, Q, R, S, T, U, V, W, X;
output YY;
and2 Ao6a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao6a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao6a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
and5 Ao6a_3( .A(P), .B(R), .C(T), .D(V), .E(W), .Y(line3) );
and5 Ao6a_4( .A(P), .B(R), .C(T), .D(V), .E(X), .Y(line4) );
or6 Ao6a_5( .A(O), .B(line0), .C(line1), .D(line2), .E(line3),
.F(line4), .Y(YY) );
endmodule // AND_OR6b
/******************************************************/
module XOR2a ( A, B, Y );
input A, B;
output Y;
inv Xo0( .A(A), .Y(NotA) ),
Xo1( .A(B), .Y(NotB) );
nand2 Xo2( .A(NotA), .B(B), .Y(line2) ),
Xo3( .A(NotB), .B(A), .Y(line3) ),
Xo4( .A(line2), .B(line3), .Y(Y) );
endmodule // XOR2a
/******************************************************/
module XOR2b ( A, B, Y );
input A, B;
output Y;
nand2 Xo0( .A(A), .B(B), .Y(NotAB) );
and2 Xo1( .A(A), .B(NotAB), .Y(line1) ),
Xo2( .A(NotAB), .B(B), .Y(line2) );
or2 Xo3( .A(line1), .B(line2), .Y(Y) );
endmodule // XOR2b
/********************************************/
module XOR3a( A, B, C, Y);
input A, B, C;
output Y;
inv Xo3_0( .A(A), .Y(NotA) ),
Xo3_1( .A(B), .Y(NotB) ),
Xo3_2( .A(C), .Y(NotC) );
and3 Xo3_3( .A(NotA), .B(NotB), .C(C), .Y(line3) ),
Xo3_4( .A(NotA), .B(B), .C(NotC), .Y(line4) ),
Xo3_5( .A(A), .B(NotB), .C(NotC), .Y(line5) ),
Xo3_6( .A(A), .B(B), .C(C), .Y(line6) );
nor2 Xo3_7( .A(line3), .B(line4), .Y(line7) ),
Xo3_8( .A(line5), .B(line6), .Y(line8) );
nand2 Xo3_9( .A(line7), .B(line8), .Y(Y) );
endmodule // XOR3a
/********************************************/
module NOR9(In, Out);
input [8:0] In;
output Out;
nor9 n9(.A(In[0]), .B(In[1]), .C(In[2]), .D(In[3]), .E(In[4]), .F(In[5]),
.G(In[6]), .H(In[7]), .I(In[8]), .Y(Out) );
endmodule // NOR9
|
Added c5315/flat5315.v.
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2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 | /**************************************************************************** * * * FLAT VERSION of HIGH-LEVEL MODEL for c5315 * * * * * * Generated by: Hakan Yalcin (hyalcin@cadence.com) * * Verified by: Jonathan David Hauke (jhauke@eecs.umich.edu) * * * * Oct 20, 1998 * * * ****************************************************************************/ // Flat Verilog File module c5315g ( in293, in302, in308, in316, in324, in341, in351, in361, in299, in307, in315, in323, in331, in338, in348, in358, in366, in206, in210, in218, in226, in234, in257, in265, in273, in281, in209, in217, in225, in233, in241, in264, in272, in280, in288, in54, in4, in2174, in1497, in332, in335, in479, in490, in503, in514, in523, in534, in446, in457, in468, in422, in435, in389, in400, in411, in374, in191, in200, in194, in197, in203, in149, in155, in188, in182, in161, in170, in164, in167, in173, in146, in152, in158, in185, in109, in43, in46, in100, in91, in76, in73, in67, in11, in106, in37, in49, in103, in40, in20, in17, in70, in61, in123, in52, in121, in116, in112, in130, in119, in129, in131, in115, in122, in114, in53, in113, in128, in127, in126, in117, in176, in179, in14, in64, in248, in251, in242, in254, in3552, in3550, in3546, in3548, in120, in94, in118, in97, in4091, in4092, in137, in4090, in4089, in4087, in4088, in1694, in1691, in1690, in1689, in372, in369, in292, in289, in562, in245, in552, in556, in559, in386, in132, in23, in80, in25, in81, in79, in82, in24, in26, in86, in88, in87, in83, in34, in4115, in135, in3717, in3724, in141, in2358, in31, in27, in545, in549, in3173, in136, in1, in373, in145, in2824, in140, out658, out690, out767, out807, out654, out651, out648, out645, out642, out670, out667, out664, out661, out688, out685, out682, out679, out676, out702, out699, out696, out693, out727, out732, out737, out742, out747, out752, out757, out762, out722, out712, out772, out777, out782, out787, out792, out797, out802, out859, out824, out826, out832, out828, out830, out834, out836, out838, out822, out863, out871, out865, out867, out869, out873, out875, out877, out861, out629, out591, out618, out615, out621, out588, out626, out632, out843, out882, out585, out575, out598, out610, out998, out1002, out1000, out1004, out854, out623, out813, out818, out707, out715, out639, out673, out636, out820, out717, out704, out593, out594, out602, out809, out611, out599, out612, out600, out850, out848, out849, out851, out887, out298, out926, out892, out973, out993, out144, out601, out847, out815, out634, out810, out845, out656, out923, out939, out921, out978, out949, out889, out603, out604, out606); input in293, in302, in308, in316, in324, in341, in351, in361, in299, in307, in315, in323, in331, in338, in348, in358, in366, in206, in210, in218, in226, in234, in257, in265, in273, in281, in209, in217, in225, in233, in241, in264, in272, in280, in288, in54, in4, in2174, in1497, in332, in335, in479, in490, in503, in514, in523, in534, in446, in457, in468, in422, in435, in389, in400, in411, in374, in191, in200, in194, in197, in203, in149, in155, in188, in182, in161, in170, in164, in167, in173, in146, in152, in158, in185, in109, in43, in46, in100, in91, in76, in73, in67, in11, in106, in37, in49, in103, in40, in20, in17, in70, in61, in123, in52, in121, in116, in112, in130, in119, in129, in131, in115, in122, in114, in53, in113, in128, in127, in126, in117, in176, in179, in14, in64, in248, in251, in242, in254, in3552, in3550, in3546, in3548, in120, in94, in118, in97, in4091, in4092, in137, in4090, in4089, in4087, in4088, in1694, in1691, in1690, in1689, in372, in369, in292, in289, in562, in245, in552, in556, in559, in386, in132, in23, in80, in25, in81, in79, in82, in24, in26, in86, in88, in87, in83, in34, in4115, in135, in3717, in3724, in141, in2358, in31, in27, in545, in549, in3173, in136, in1, in373, in145, in2824, in140; output out658, out690, out767, out807, out654, out651, out648, out645, out642, out670, out667, out664, out661, out688, out685, out682, out679, out676, out702, out699, out696, out693, out727, out732, out737, out742, out747, out752, out757, out762, out722, out712, out772, out777, out782, out787, out792, out797, out802, out859, out824, out826, out832, out828, out830, out834, out836, out838, out822, out863, out871, out865, out867, out869, out873, out875, out877, out861, out629, out591, out618, out615, out621, out588, out626, out632, out843, out882, out585, out575, out598, out610, out998, out1002, out1000, out1004, out854, out623, out813, out818, out707, out715, out639, out673, out636, out820, out717, out704, out593, out594, out602, out809, out611, out599, out612, out600, out850, out848, out849, out851, out887, out298, out926, out892, out973, out993, out144, out601, out847, out815, out634, out810, out845, out656, out923, out939, out921, out978, out949, out889, out603, out604, out606; inv M1_Mux9_0_Mux4_0_Mux2_0(in332, M1_Mux9_0_Mux4_0_Not_ContIn); and2 M1_Mux9_0_Mux4_0_Mux2_1(in361, M1_Mux9_0_Mux4_0_Not_ContIn, M1_Mux9_0_Mux4_0_line1); and2 M1_Mux9_0_Mux4_0_Mux2_2(in366, in332, M1_Mux9_0_Mux4_0_line2); or2 M1_Mux9_0_Mux4_0_Mux2_3(M1_Mux9_0_Mux4_0_line1, M1_Mux9_0_Mux4_0_line2, Xbus_0); inv M1_Mux9_0_Mux4_1_Mux2_0(in332, M1_Mux9_0_Mux4_1_Not_ContIn); and2 M1_Mux9_0_Mux4_1_Mux2_1(in351, M1_Mux9_0_Mux4_1_Not_ContIn, M1_Mux9_0_Mux4_1_line1); and2 M1_Mux9_0_Mux4_1_Mux2_2(in358, in332, M1_Mux9_0_Mux4_1_line2); or2 M1_Mux9_0_Mux4_1_Mux2_3(M1_Mux9_0_Mux4_1_line1, M1_Mux9_0_Mux4_1_line2, Xbus_1); inv M1_Mux9_0_Mux4_2_Mux2_0(in332, M1_Mux9_0_Mux4_2_Not_ContIn); and2 M1_Mux9_0_Mux4_2_Mux2_1(in341, M1_Mux9_0_Mux4_2_Not_ContIn, M1_Mux9_0_Mux4_2_line1); and2 M1_Mux9_0_Mux4_2_Mux2_2(in348, in332, M1_Mux9_0_Mux4_2_line2); or2 M1_Mux9_0_Mux4_2_Mux2_3(M1_Mux9_0_Mux4_2_line1, M1_Mux9_0_Mux4_2_line2, Xbus_2); inv M1_Mux9_0_Mux4_3_Mux2_0(in332, M1_Mux9_0_Mux4_3_Not_ContIn); and2 M1_Mux9_0_Mux4_3_Mux2_1(vdd, M1_Mux9_0_Mux4_3_Not_ContIn, M1_Mux9_0_Mux4_3_line1); and2 M1_Mux9_0_Mux4_3_Mux2_2(in338, in332, M1_Mux9_0_Mux4_3_line2); or2 M1_Mux9_0_Mux4_3_Mux2_3(M1_Mux9_0_Mux4_3_line1, M1_Mux9_0_Mux4_3_line2, Xbus_3); inv M1_Mux9_1_Mux4_0_Mux2_0(in332, M1_Mux9_1_Mux4_0_Not_ContIn); and2 M1_Mux9_1_Mux4_0_Mux2_1(in324, M1_Mux9_1_Mux4_0_Not_ContIn, M1_Mux9_1_Mux4_0_line1); and2 M1_Mux9_1_Mux4_0_Mux2_2(in331, in332, M1_Mux9_1_Mux4_0_line2); or2 M1_Mux9_1_Mux4_0_Mux2_3(M1_Mux9_1_Mux4_0_line1, M1_Mux9_1_Mux4_0_line2, Xbus_4); inv M1_Mux9_1_Mux4_1_Mux2_0(in332, M1_Mux9_1_Mux4_1_Not_ContIn); and2 M1_Mux9_1_Mux4_1_Mux2_1(in316, M1_Mux9_1_Mux4_1_Not_ContIn, M1_Mux9_1_Mux4_1_line1); and2 M1_Mux9_1_Mux4_1_Mux2_2(in323, in332, M1_Mux9_1_Mux4_1_line2); or2 M1_Mux9_1_Mux4_1_Mux2_3(M1_Mux9_1_Mux4_1_line1, M1_Mux9_1_Mux4_1_line2, Xbus_5); inv M1_Mux9_1_Mux4_2_Mux2_0(in332, M1_Mux9_1_Mux4_2_Not_ContIn); and2 M1_Mux9_1_Mux4_2_Mux2_1(in308, M1_Mux9_1_Mux4_2_Not_ContIn, M1_Mux9_1_Mux4_2_line1); and2 M1_Mux9_1_Mux4_2_Mux2_2(in315, in332, M1_Mux9_1_Mux4_2_line2); or2 M1_Mux9_1_Mux4_2_Mux2_3(M1_Mux9_1_Mux4_2_line1, M1_Mux9_1_Mux4_2_line2, Xbus_6); inv M1_Mux9_1_Mux4_3_Mux2_0(in332, M1_Mux9_1_Mux4_3_Not_ContIn); and2 M1_Mux9_1_Mux4_3_Mux2_1(in302, M1_Mux9_1_Mux4_3_Not_ContIn, M1_Mux9_1_Mux4_3_line1); and2 M1_Mux9_1_Mux4_3_Mux2_2(in307, in332, M1_Mux9_1_Mux4_3_line2); or2 M1_Mux9_1_Mux4_3_Mux2_3(M1_Mux9_1_Mux4_3_line1, M1_Mux9_1_Mux4_3_line2, Xbus_7); inv M1_Mux9_2_Mux2_0(in332, M1_Mux9_2_Not_ContIn); and2 M1_Mux9_2_Mux2_1(in293, M1_Mux9_2_Not_ContIn, M1_Mux9_2_line1); and2 M1_Mux9_2_Mux2_2(in299, in332, M1_Mux9_2_line2); or2 M1_Mux9_2_Mux2_3(M1_Mux9_2_line1, M1_Mux9_2_line2, Xbus_8); inv M2_Mux9_0_Mux4_0_Mux2_0(in335, M2_Mux9_0_Mux4_0_Not_ContIn); and2 M2_Mux9_0_Mux4_0_Mux2_1(in281, M2_Mux9_0_Mux4_0_Not_ContIn, M2_Mux9_0_Mux4_0_line1); and2 M2_Mux9_0_Mux4_0_Mux2_2(in288, in335, M2_Mux9_0_Mux4_0_line2); or2 M2_Mux9_0_Mux4_0_Mux2_3(M2_Mux9_0_Mux4_0_line1, M2_Mux9_0_Mux4_0_line2, Ybus_0); inv M2_Mux9_0_Mux4_1_Mux2_0(in335, M2_Mux9_0_Mux4_1_Not_ContIn); and2 M2_Mux9_0_Mux4_1_Mux2_1(in273, M2_Mux9_0_Mux4_1_Not_ContIn, M2_Mux9_0_Mux4_1_line1); and2 M2_Mux9_0_Mux4_1_Mux2_2(in280, in335, M2_Mux9_0_Mux4_1_line2); or2 M2_Mux9_0_Mux4_1_Mux2_3(M2_Mux9_0_Mux4_1_line1, M2_Mux9_0_Mux4_1_line2, Ybus_1); inv M2_Mux9_0_Mux4_2_Mux2_0(in335, M2_Mux9_0_Mux4_2_Not_ContIn); and2 M2_Mux9_0_Mux4_2_Mux2_1(in265, M2_Mux9_0_Mux4_2_Not_ContIn, M2_Mux9_0_Mux4_2_line1); and2 M2_Mux9_0_Mux4_2_Mux2_2(in272, in335, M2_Mux9_0_Mux4_2_line2); or2 M2_Mux9_0_Mux4_2_Mux2_3(M2_Mux9_0_Mux4_2_line1, M2_Mux9_0_Mux4_2_line2, Ybus_2); inv M2_Mux9_0_Mux4_3_Mux2_0(in335, M2_Mux9_0_Mux4_3_Not_ContIn); and2 M2_Mux9_0_Mux4_3_Mux2_1(in257, M2_Mux9_0_Mux4_3_Not_ContIn, M2_Mux9_0_Mux4_3_line1); and2 M2_Mux9_0_Mux4_3_Mux2_2(in264, in335, M2_Mux9_0_Mux4_3_line2); or2 M2_Mux9_0_Mux4_3_Mux2_3(M2_Mux9_0_Mux4_3_line1, M2_Mux9_0_Mux4_3_line2, Ybus_3); inv M2_Mux9_1_Mux4_0_Mux2_0(in335, M2_Mux9_1_Mux4_0_Not_ContIn); and2 M2_Mux9_1_Mux4_0_Mux2_1(in234, M2_Mux9_1_Mux4_0_Not_ContIn, M2_Mux9_1_Mux4_0_line1); and2 M2_Mux9_1_Mux4_0_Mux2_2(in241, in335, M2_Mux9_1_Mux4_0_line2); or2 M2_Mux9_1_Mux4_0_Mux2_3(M2_Mux9_1_Mux4_0_line1, M2_Mux9_1_Mux4_0_line2, Ybus_4); inv M2_Mux9_1_Mux4_1_Mux2_0(in335, M2_Mux9_1_Mux4_1_Not_ContIn); and2 M2_Mux9_1_Mux4_1_Mux2_1(in226, M2_Mux9_1_Mux4_1_Not_ContIn, M2_Mux9_1_Mux4_1_line1); and2 M2_Mux9_1_Mux4_1_Mux2_2(in233, in335, M2_Mux9_1_Mux4_1_line2); or2 M2_Mux9_1_Mux4_1_Mux2_3(M2_Mux9_1_Mux4_1_line1, M2_Mux9_1_Mux4_1_line2, Ybus_5); inv M2_Mux9_1_Mux4_2_Mux2_0(in335, M2_Mux9_1_Mux4_2_Not_ContIn); and2 M2_Mux9_1_Mux4_2_Mux2_1(in218, M2_Mux9_1_Mux4_2_Not_ContIn, M2_Mux9_1_Mux4_2_line1); and2 M2_Mux9_1_Mux4_2_Mux2_2(in225, in335, M2_Mux9_1_Mux4_2_line2); or2 M2_Mux9_1_Mux4_2_Mux2_3(M2_Mux9_1_Mux4_2_line1, M2_Mux9_1_Mux4_2_line2, Ybus_6); inv M2_Mux9_1_Mux4_3_Mux2_0(in335, M2_Mux9_1_Mux4_3_Not_ContIn); and2 M2_Mux9_1_Mux4_3_Mux2_1(in210, M2_Mux9_1_Mux4_3_Not_ContIn, M2_Mux9_1_Mux4_3_line1); and2 M2_Mux9_1_Mux4_3_Mux2_2(in217, in335, M2_Mux9_1_Mux4_3_line2); or2 M2_Mux9_1_Mux4_3_Mux2_3(M2_Mux9_1_Mux4_3_line1, M2_Mux9_1_Mux4_3_line2, Ybus_7); inv M2_Mux9_2_Mux2_0(in335, M2_Mux9_2_Not_ContIn); and2 M2_Mux9_2_Mux2_1(in206, M2_Mux9_2_Not_ContIn, M2_Mux9_2_line1); and2 M2_Mux9_2_Mux2_2(in209, in335, M2_Mux9_2_line2); or2 M2_Mux9_2_Mux2_3(M2_Mux9_2_line1, M2_Mux9_2_line2, Ybus_8); inv M3_CalP0_LP0_CL0_LB0_Mux2_0(in361, M3_CalP0_LP0_CL0_LB0_Not_ContIn); and2 M3_CalP0_LP0_CL0_LB0_Mux2_1(in254, M3_CalP0_LP0_CL0_LB0_Not_ContIn, M3_CalP0_LP0_CL0_LB0_line1); and2 M3_CalP0_LP0_CL0_LB0_Mux2_2(in242, in361, M3_CalP0_LP0_CL0_LB0_line2); or2 M3_CalP0_LP0_CL0_LB0_Mux2_3(M3_CalP0_LP0_CL0_LB0_line1, M3_CalP0_LP0_CL0_LB0_line2, M3_CalP0_LP0_CL0_line0); inv M3_CalP0_LP0_CL0_LB1_Mux2_0(in361, M3_CalP0_LP0_CL0_LB1_Not_ContIn); and2 M3_CalP0_LP0_CL0_LB1_Mux2_1(in251, M3_CalP0_LP0_CL0_LB1_Not_ContIn, M3_CalP0_LP0_CL0_LB1_line1); and2 M3_CalP0_LP0_CL0_LB1_Mux2_2(in248, in361, M3_CalP0_LP0_CL0_LB1_line2); or2 M3_CalP0_LP0_CL0_LB1_Mux2_3(M3_CalP0_LP0_CL0_LB1_line1, M3_CalP0_LP0_CL0_LB1_line2, M3_CalP0_LP0_CL0_line1); or2 M3_CalP0_LP0_CL0_LB2(vdd, M3_CalP0_LP0_CL0_line0, M3_CalP0_LP0_CL0_line2); nand2 M3_CalP0_LP0_CL0_LB3(vdd, M3_CalP0_LP0_CL0_line1, M3_CalP0_LP0_CL0_line3); and2 M3_CalP0_LP0_CL0_LB4(M3_CalP0_LP0_CL0_line2, M3_CalP0_LP0_CL0_line3, M3_CalP0_LogicOut_0); inv M3_CalP0_LP0_CL1_LB0_Mux2_0(in351, M3_CalP0_LP0_CL1_LB0_Not_ContIn); and2 M3_CalP0_LP0_CL1_LB0_Mux2_1(in254, M3_CalP0_LP0_CL1_LB0_Not_ContIn, M3_CalP0_LP0_CL1_LB0_line1); and2 M3_CalP0_LP0_CL1_LB0_Mux2_2(in242, in351, M3_CalP0_LP0_CL1_LB0_line2); or2 M3_CalP0_LP0_CL1_LB0_Mux2_3(M3_CalP0_LP0_CL1_LB0_line1, M3_CalP0_LP0_CL1_LB0_line2, M3_CalP0_LP0_CL1_line0); inv M3_CalP0_LP0_CL1_LB1_Mux2_0(in351, M3_CalP0_LP0_CL1_LB1_Not_ContIn); and2 M3_CalP0_LP0_CL1_LB1_Mux2_1(in251, M3_CalP0_LP0_CL1_LB1_Not_ContIn, M3_CalP0_LP0_CL1_LB1_line1); and2 M3_CalP0_LP0_CL1_LB1_Mux2_2(in248, in351, M3_CalP0_LP0_CL1_LB1_line2); or2 M3_CalP0_LP0_CL1_LB1_Mux2_3(M3_CalP0_LP0_CL1_LB1_line1, M3_CalP0_LP0_CL1_LB1_line2, M3_CalP0_LP0_CL1_line1); or2 M3_CalP0_LP0_CL1_LB2(in534, M3_CalP0_LP0_CL1_line0, M3_CalP0_LP0_CL1_line2); nand2 M3_CalP0_LP0_CL1_LB3(in534, M3_CalP0_LP0_CL1_line1, M3_CalP0_LP0_CL1_line3); and2 M3_CalP0_LP0_CL1_LB4(M3_CalP0_LP0_CL1_line2, M3_CalP0_LP0_CL1_line3, M3_CalP0_LogicOut_1); inv M3_CalP0_LP0_CL2_LB0_Mux2_0(in341, M3_CalP0_LP0_CL2_LB0_Not_ContIn); and2 M3_CalP0_LP0_CL2_LB0_Mux2_1(in254, M3_CalP0_LP0_CL2_LB0_Not_ContIn, M3_CalP0_LP0_CL2_LB0_line1); and2 M3_CalP0_LP0_CL2_LB0_Mux2_2(in242, in341, M3_CalP0_LP0_CL2_LB0_line2); or2 M3_CalP0_LP0_CL2_LB0_Mux2_3(M3_CalP0_LP0_CL2_LB0_line1, M3_CalP0_LP0_CL2_LB0_line2, M3_CalP0_LP0_CL2_line0); inv M3_CalP0_LP0_CL2_LB1_Mux2_0(in341, M3_CalP0_LP0_CL2_LB1_Not_ContIn); and2 M3_CalP0_LP0_CL2_LB1_Mux2_1(in251, M3_CalP0_LP0_CL2_LB1_Not_ContIn, M3_CalP0_LP0_CL2_LB1_line1); and2 M3_CalP0_LP0_CL2_LB1_Mux2_2(in248, in341, M3_CalP0_LP0_CL2_LB1_line2); or2 M3_CalP0_LP0_CL2_LB1_Mux2_3(M3_CalP0_LP0_CL2_LB1_line1, M3_CalP0_LP0_CL2_LB1_line2, M3_CalP0_LP0_CL2_line1); or2 M3_CalP0_LP0_CL2_LB2(in523, M3_CalP0_LP0_CL2_line0, M3_CalP0_LP0_CL2_line2); nand2 M3_CalP0_LP0_CL2_LB3(in523, M3_CalP0_LP0_CL2_line1, M3_CalP0_LP0_CL2_line3); and2 M3_CalP0_LP0_CL2_LB4(M3_CalP0_LP0_CL2_line2, M3_CalP0_LP0_CL2_line3, M3_CalP0_LogicOut_2); inv M3_CalP0_LP0_CL3_LB0_Mux2_0(vdd, M3_CalP0_LP0_CL3_LB0_Not_ContIn); and2 M3_CalP0_LP0_CL3_LB0_Mux2_1(in254, M3_CalP0_LP0_CL3_LB0_Not_ContIn, M3_CalP0_LP0_CL3_LB0_line1); and2 M3_CalP0_LP0_CL3_LB0_Mux2_2(in242, vdd, M3_CalP0_LP0_CL3_LB0_line2); or2 M3_CalP0_LP0_CL3_LB0_Mux2_3(M3_CalP0_LP0_CL3_LB0_line1, M3_CalP0_LP0_CL3_LB0_line2, M3_CalP0_LP0_CL3_line0); inv M3_CalP0_LP0_CL3_LB1_Mux2_0(vdd, M3_CalP0_LP0_CL3_LB1_Not_ContIn); and2 M3_CalP0_LP0_CL3_LB1_Mux2_1(in251, M3_CalP0_LP0_CL3_LB1_Not_ContIn, M3_CalP0_LP0_CL3_LB1_line1); and2 M3_CalP0_LP0_CL3_LB1_Mux2_2(in248, vdd, M3_CalP0_LP0_CL3_LB1_line2); or2 M3_CalP0_LP0_CL3_LB1_Mux2_3(M3_CalP0_LP0_CL3_LB1_line1, M3_CalP0_LP0_CL3_LB1_line2, M3_CalP0_LP0_CL3_line1); or2 M3_CalP0_LP0_CL3_LB2(in514, M3_CalP0_LP0_CL3_line0, M3_CalP0_LP0_CL3_line2); nand2 M3_CalP0_LP0_CL3_LB3(in514, M3_CalP0_LP0_CL3_line1, M3_CalP0_LP0_CL3_line3); and2 M3_CalP0_LP0_CL3_LB4(M3_CalP0_LP0_CL3_line2, M3_CalP0_LP0_CL3_line3, M3_CalP0_LogicOut_3); inv M3_CalP0_LP0_CL4_LB0_Mux2_0(in324, M3_CalP0_LP0_CL4_LB0_Not_ContIn); and2 M3_CalP0_LP0_CL4_LB0_Mux2_1(in254, M3_CalP0_LP0_CL4_LB0_Not_ContIn, M3_CalP0_LP0_CL4_LB0_line1); and2 M3_CalP0_LP0_CL4_LB0_Mux2_2(in242, in324, M3_CalP0_LP0_CL4_LB0_line2); or2 M3_CalP0_LP0_CL4_LB0_Mux2_3(M3_CalP0_LP0_CL4_LB0_line1, M3_CalP0_LP0_CL4_LB0_line2, M3_CalP0_LP0_CL4_line0); inv M3_CalP0_LP0_CL4_LB1_Mux2_0(in324, M3_CalP0_LP0_CL4_LB1_Not_ContIn); and2 M3_CalP0_LP0_CL4_LB1_Mux2_1(in251, M3_CalP0_LP0_CL4_LB1_Not_ContIn, M3_CalP0_LP0_CL4_LB1_line1); and2 M3_CalP0_LP0_CL4_LB1_Mux2_2(in248, in324, M3_CalP0_LP0_CL4_LB1_line2); or2 M3_CalP0_LP0_CL4_LB1_Mux2_3(M3_CalP0_LP0_CL4_LB1_line1, M3_CalP0_LP0_CL4_LB1_line2, M3_CalP0_LP0_CL4_line1); or2 M3_CalP0_LP0_CL4_LB2(in503, M3_CalP0_LP0_CL4_line0, M3_CalP0_LP0_CL4_line2); nand2 M3_CalP0_LP0_CL4_LB3(in503, M3_CalP0_LP0_CL4_line1, M3_CalP0_LP0_CL4_line3); and2 M3_CalP0_LP0_CL4_LB4(M3_CalP0_LP0_CL4_line2, M3_CalP0_LP0_CL4_line3, M3_CalP0_LogicOut_4); inv M3_CalP0_LP0_CL5_LB0_Mux2_0(in316, M3_CalP0_LP0_CL5_LB0_Not_ContIn); and2 M3_CalP0_LP0_CL5_LB0_Mux2_1(in254, M3_CalP0_LP0_CL5_LB0_Not_ContIn, M3_CalP0_LP0_CL5_LB0_line1); and2 M3_CalP0_LP0_CL5_LB0_Mux2_2(in242, in316, M3_CalP0_LP0_CL5_LB0_line2); or2 M3_CalP0_LP0_CL5_LB0_Mux2_3(M3_CalP0_LP0_CL5_LB0_line1, M3_CalP0_LP0_CL5_LB0_line2, M3_CalP0_LP0_CL5_line0); inv M3_CalP0_LP0_CL5_LB1_Mux2_0(in316, M3_CalP0_LP0_CL5_LB1_Not_ContIn); and2 M3_CalP0_LP0_CL5_LB1_Mux2_1(in251, M3_CalP0_LP0_CL5_LB1_Not_ContIn, M3_CalP0_LP0_CL5_LB1_line1); and2 M3_CalP0_LP0_CL5_LB1_Mux2_2(in248, in316, M3_CalP0_LP0_CL5_LB1_line2); or2 M3_CalP0_LP0_CL5_LB1_Mux2_3(M3_CalP0_LP0_CL5_LB1_line1, M3_CalP0_LP0_CL5_LB1_line2, M3_CalP0_LP0_CL5_line1); or2 M3_CalP0_LP0_CL5_LB2(in490, M3_CalP0_LP0_CL5_line0, M3_CalP0_LP0_CL5_line2); nand2 M3_CalP0_LP0_CL5_LB3(in490, M3_CalP0_LP0_CL5_line1, M3_CalP0_LP0_CL5_line3); and2 M3_CalP0_LP0_CL5_LB4(M3_CalP0_LP0_CL5_line2, M3_CalP0_LP0_CL5_line3, M3_CalP0_LogicOut_5); inv M3_CalP0_LP0_CL6_LB0_Mux2_0(in308, M3_CalP0_LP0_CL6_LB0_Not_ContIn); and2 M3_CalP0_LP0_CL6_LB0_Mux2_1(in254, M3_CalP0_LP0_CL6_LB0_Not_ContIn, M3_CalP0_LP0_CL6_LB0_line1); and2 M3_CalP0_LP0_CL6_LB0_Mux2_2(in242, in308, M3_CalP0_LP0_CL6_LB0_line2); or2 M3_CalP0_LP0_CL6_LB0_Mux2_3(M3_CalP0_LP0_CL6_LB0_line1, M3_CalP0_LP0_CL6_LB0_line2, M3_CalP0_LP0_CL6_line0); inv M3_CalP0_LP0_CL6_LB1_Mux2_0(in308, M3_CalP0_LP0_CL6_LB1_Not_ContIn); and2 M3_CalP0_LP0_CL6_LB1_Mux2_1(in251, M3_CalP0_LP0_CL6_LB1_Not_ContIn, M3_CalP0_LP0_CL6_LB1_line1); and2 M3_CalP0_LP0_CL6_LB1_Mux2_2(in248, in308, M3_CalP0_LP0_CL6_LB1_line2); or2 M3_CalP0_LP0_CL6_LB1_Mux2_3(M3_CalP0_LP0_CL6_LB1_line1, M3_CalP0_LP0_CL6_LB1_line2, M3_CalP0_LP0_CL6_line1); or2 M3_CalP0_LP0_CL6_LB2(in479, M3_CalP0_LP0_CL6_line0, M3_CalP0_LP0_CL6_line2); nand2 M3_CalP0_LP0_CL6_LB3(in479, M3_CalP0_LP0_CL6_line1, M3_CalP0_LP0_CL6_line3); and2 M3_CalP0_LP0_CL6_LB4(M3_CalP0_LP0_CL6_line2, M3_CalP0_LP0_CL6_line3, M3_CalP0_LogicOut_6); inv M3_CalP0_LP0_CL7_LB0_Mux2_0(in302, M3_CalP0_LP0_CL7_LB0_Not_ContIn); and2 M3_CalP0_LP0_CL7_LB0_Mux2_1(in254, M3_CalP0_LP0_CL7_LB0_Not_ContIn, M3_CalP0_LP0_CL7_LB0_line1); and2 M3_CalP0_LP0_CL7_LB0_Mux2_2(in242, in302, M3_CalP0_LP0_CL7_LB0_line2); or2 M3_CalP0_LP0_CL7_LB0_Mux2_3(M3_CalP0_LP0_CL7_LB0_line1, M3_CalP0_LP0_CL7_LB0_line2, M3_CalP0_LP0_CL7_line0); inv M3_CalP0_LP0_CL7_LB1_Mux2_0(in302, M3_CalP0_LP0_CL7_LB1_Not_ContIn); and2 M3_CalP0_LP0_CL7_LB1_Mux2_1(in251, M3_CalP0_LP0_CL7_LB1_Not_ContIn, M3_CalP0_LP0_CL7_LB1_line1); and2 M3_CalP0_LP0_CL7_LB1_Mux2_2(in248, in302, M3_CalP0_LP0_CL7_LB1_line2); or2 M3_CalP0_LP0_CL7_LB1_Mux2_3(M3_CalP0_LP0_CL7_LB1_line1, M3_CalP0_LP0_CL7_LB1_line2, M3_CalP0_LP0_CL7_line1); or2 M3_CalP0_LP0_CL7_LB2(vdd, M3_CalP0_LP0_CL7_line0, M3_CalP0_LP0_CL7_line2); nand2 M3_CalP0_LP0_CL7_LB3(vdd, M3_CalP0_LP0_CL7_line1, M3_CalP0_LP0_CL7_line3); and2 M3_CalP0_LP0_CL7_LB4(M3_CalP0_LP0_CL7_line2, M3_CalP0_LP0_CL7_line3, M3_CalP0_LogicOut_7); inv M3_CalP0_LP0_CL8_LB0_Mux2_0(in293, M3_CalP0_LP0_CL8_LB0_Not_ContIn); and2 M3_CalP0_LP0_CL8_LB0_Mux2_1(in254, M3_CalP0_LP0_CL8_LB0_Not_ContIn, M3_CalP0_LP0_CL8_LB0_line1); and2 M3_CalP0_LP0_CL8_LB0_Mux2_2(in242, in293, M3_CalP0_LP0_CL8_LB0_line2); or2 M3_CalP0_LP0_CL8_LB0_Mux2_3(M3_CalP0_LP0_CL8_LB0_line1, M3_CalP0_LP0_CL8_LB0_line2, M3_CalP0_LP0_CL8_line0); inv M3_CalP0_LP0_CL8_LB1_Mux2_0(in293, M3_CalP0_LP0_CL8_LB1_Not_ContIn); and2 M3_CalP0_LP0_CL8_LB1_Mux2_1(in251, M3_CalP0_LP0_CL8_LB1_Not_ContIn, M3_CalP0_LP0_CL8_LB1_line1); and2 M3_CalP0_LP0_CL8_LB1_Mux2_2(in248, in293, M3_CalP0_LP0_CL8_LB1_line2); or2 M3_CalP0_LP0_CL8_LB1_Mux2_3(M3_CalP0_LP0_CL8_LB1_line1, M3_CalP0_LP0_CL8_LB1_line2, M3_CalP0_LP0_CL8_line1); or2 M3_CalP0_LP0_CL8_LB2(gnd, M3_CalP0_LP0_CL8_line0, M3_CalP0_LP0_CL8_line2); nand2 M3_CalP0_LP0_CL8_LB3(gnd, M3_CalP0_LP0_CL8_line1, M3_CalP0_LP0_CL8_line3); and2 M3_CalP0_LP0_CL8_LB4(M3_CalP0_LP0_CL8_line2, M3_CalP0_LP0_CL8_line3, M3_CalP0_LogicOut_8); inv M3_CalP0_LP1_PT1_Xo0(M3_CalP0_LogicOut_5, M3_CalP0_LP1_PT1_NotA); inv M3_CalP0_LP1_PT1_Xo1(M3_CalP0_LogicOut_6, M3_CalP0_LP1_PT1_NotB); nand2 M3_CalP0_LP1_PT1_Xo2(M3_CalP0_LP1_PT1_NotA, M3_CalP0_LogicOut_6, M3_CalP0_LP1_PT1_line2); nand2 M3_CalP0_LP1_PT1_Xo3(M3_CalP0_LP1_PT1_NotB, M3_CalP0_LogicOut_5, M3_CalP0_LP1_PT1_line3); nand2 M3_CalP0_LP1_PT1_Xo4(M3_CalP0_LP1_PT1_line2, M3_CalP0_LP1_PT1_line3, M3_CalP0_LP1_line1); inv M3_CalP0_LP1_PT2_Xo0(M3_CalP0_LogicOut_7, M3_CalP0_LP1_PT2_NotA); inv M3_CalP0_LP1_PT2_Xo1(M3_CalP0_LogicOut_8, M3_CalP0_LP1_PT2_NotB); nand2 M3_CalP0_LP1_PT2_Xo2(M3_CalP0_LP1_PT2_NotA, M3_CalP0_LogicOut_8, M3_CalP0_LP1_PT2_line2); nand2 M3_CalP0_LP1_PT2_Xo3(M3_CalP0_LP1_PT2_NotB, M3_CalP0_LogicOut_7, M3_CalP0_LP1_PT2_line3); nand2 M3_CalP0_LP1_PT2_Xo4(M3_CalP0_LP1_PT2_line2, M3_CalP0_LP1_PT2_line3, M3_CalP0_LP1_line2); inv M3_CalP0_LP1_PT3_Xo0(M3_CalP0_LogicOut_1, M3_CalP0_LP1_PT3_NotA); inv M3_CalP0_LP1_PT3_Xo1(M3_CalP0_LogicOut_2, M3_CalP0_LP1_PT3_NotB); nand2 M3_CalP0_LP1_PT3_Xo2(M3_CalP0_LP1_PT3_NotA, M3_CalP0_LogicOut_2, M3_CalP0_LP1_PT3_line2); nand2 M3_CalP0_LP1_PT3_Xo3(M3_CalP0_LP1_PT3_NotB, M3_CalP0_LogicOut_1, M3_CalP0_LP1_PT3_line3); nand2 M3_CalP0_LP1_PT3_Xo4(M3_CalP0_LP1_PT3_line2, M3_CalP0_LP1_PT3_line3, M3_CalP0_LP1_line3); inv M3_CalP0_LP1_PT4_Xo0(M3_CalP0_LogicOut_3, M3_CalP0_LP1_PT4_NotA); inv M3_CalP0_LP1_PT4_Xo1(M3_CalP0_LogicOut_4, M3_CalP0_LP1_PT4_NotB); nand2 M3_CalP0_LP1_PT4_Xo2(M3_CalP0_LP1_PT4_NotA, M3_CalP0_LogicOut_4, M3_CalP0_LP1_PT4_line2); nand2 M3_CalP0_LP1_PT4_Xo3(M3_CalP0_LP1_PT4_NotB, M3_CalP0_LogicOut_3, M3_CalP0_LP1_PT4_line3); nand2 M3_CalP0_LP1_PT4_Xo4(M3_CalP0_LP1_PT4_line2, M3_CalP0_LP1_PT4_line3, M3_CalP0_LP1_line4); inv M3_CalP0_LP1_PT5_Xo0(M3_CalP0_LP1_line1, M3_CalP0_LP1_PT5_NotA); inv M3_CalP0_LP1_PT5_Xo1(M3_CalP0_LP1_line2, M3_CalP0_LP1_PT5_NotB); nand2 M3_CalP0_LP1_PT5_Xo2(M3_CalP0_LP1_PT5_NotA, M3_CalP0_LP1_line2, M3_CalP0_LP1_PT5_line2); nand2 M3_CalP0_LP1_PT5_Xo3(M3_CalP0_LP1_PT5_NotB, M3_CalP0_LP1_line1, M3_CalP0_LP1_PT5_line3); nand2 M3_CalP0_LP1_PT5_Xo4(M3_CalP0_LP1_PT5_line2, M3_CalP0_LP1_PT5_line3, M3_CalP0_LP1_line5); inv M3_CalP0_LP1_PT6_Xo3_0(M3_CalP0_LP1_line3, M3_CalP0_LP1_PT6_NotA); inv M3_CalP0_LP1_PT6_Xo3_1(M3_CalP0_LogicOut_0, M3_CalP0_LP1_PT6_NotB); inv M3_CalP0_LP1_PT6_Xo3_2(M3_CalP0_LP1_line4, M3_CalP0_LP1_PT6_NotC); and3 M3_CalP0_LP1_PT6_Xo3_3(M3_CalP0_LP1_PT6_NotA, M3_CalP0_LP1_PT6_NotB, M3_CalP0_LP1_line4, M3_CalP0_LP1_PT6_line3); and3 M3_CalP0_LP1_PT6_Xo3_4(M3_CalP0_LP1_PT6_NotA, M3_CalP0_LogicOut_0, M3_CalP0_LP1_PT6_NotC, M3_CalP0_LP1_PT6_line4); and3 M3_CalP0_LP1_PT6_Xo3_5(M3_CalP0_LP1_line3, M3_CalP0_LP1_PT6_NotB, M3_CalP0_LP1_PT6_NotC, M3_CalP0_LP1_PT6_line5); and3 M3_CalP0_LP1_PT6_Xo3_6(M3_CalP0_LP1_line3, M3_CalP0_LogicOut_0, M3_CalP0_LP1_line4, M3_CalP0_LP1_PT6_line6); nor2 M3_CalP0_LP1_PT6_Xo3_7(M3_CalP0_LP1_PT6_line3, M3_CalP0_LP1_PT6_line4, M3_CalP0_LP1_PT6_line7); nor2 M3_CalP0_LP1_PT6_Xo3_8(M3_CalP0_LP1_PT6_line5, M3_CalP0_LP1_PT6_line6, M3_CalP0_LP1_PT6_line8); nand2 M3_CalP0_LP1_PT6_Xo3_9(M3_CalP0_LP1_PT6_line7, M3_CalP0_LP1_PT6_line8, M3_CalP0_LP1_line6); inv M3_CalP0_LP1_PT7_Xo0(M3_CalP0_LP1_line5, M3_CalP0_LP1_PT7_NotA); inv M3_CalP0_LP1_PT7_Xo1(M3_CalP0_LP1_line6, M3_CalP0_LP1_PT7_NotB); nand2 M3_CalP0_LP1_PT7_Xo2(M3_CalP0_LP1_PT7_NotA, M3_CalP0_LP1_line6, M3_CalP0_LP1_PT7_line2); nand2 M3_CalP0_LP1_PT7_Xo3(M3_CalP0_LP1_PT7_NotB, M3_CalP0_LP1_line5, M3_CalP0_LP1_PT7_line3); nand2 M3_CalP0_LP1_PT7_Xo4(M3_CalP0_LP1_PT7_line2, M3_CalP0_LP1_PT7_line3, M3_LogicPar); and2 M3_CalP1_SP0_GP9_0(Xbus_0, vdd, M3_CalP1_Genbus_0); and2 M3_CalP1_SP0_GP9_1(Xbus_1, in534, M3_CalP1_Genbus_1); and2 M3_CalP1_SP0_GP9_2(Xbus_2, in523, M3_CalP1_Genbus_2); and2 M3_CalP1_SP0_GP9_3(Xbus_3, in514, M3_CalP1_Genbus_3); and2 M3_CalP1_SP0_GP9_4(Xbus_4, in503, M3_CalP1_Genbus_4); and2 M3_CalP1_SP0_GP9_5(Xbus_5, in490, M3_CalP1_Genbus_5); and2 M3_CalP1_SP0_GP9_6(Xbus_6, in479, M3_CalP1_Genbus_6); and2 M3_CalP1_SP0_GP9_7(Xbus_7, vdd, M3_CalP1_Genbus_7); and2 M3_CalP1_SP0_GP9_8(Xbus_8, vdd, M3_CalP1_Genbus_8); inv M3_CalP1_SP0_GP9_9_Xo0(Xbus_0, M3_CalP1_SP0_GP9_9_NotA); inv M3_CalP1_SP0_GP9_9_Xo1(vdd, M3_CalP1_SP0_GP9_9_NotB); nand2 M3_CalP1_SP0_GP9_9_Xo2(M3_CalP1_SP0_GP9_9_NotA, vdd, M3_CalP1_SP0_GP9_9_line2); nand2 M3_CalP1_SP0_GP9_9_Xo3(M3_CalP1_SP0_GP9_9_NotB, Xbus_0, M3_CalP1_SP0_GP9_9_line3); nand2 M3_CalP1_SP0_GP9_9_Xo4(M3_CalP1_SP0_GP9_9_line2, M3_CalP1_SP0_GP9_9_line3, M3_CalP1_Propbus_0); inv M3_CalP1_SP0_GP9_10_Xo0(Xbus_1, M3_CalP1_SP0_GP9_10_NotA); inv M3_CalP1_SP0_GP9_10_Xo1(in534, M3_CalP1_SP0_GP9_10_NotB); nand2 M3_CalP1_SP0_GP9_10_Xo2(M3_CalP1_SP0_GP9_10_NotA, in534, M3_CalP1_SP0_GP9_10_line2); nand2 M3_CalP1_SP0_GP9_10_Xo3(M3_CalP1_SP0_GP9_10_NotB, Xbus_1, M3_CalP1_SP0_GP9_10_line3); nand2 M3_CalP1_SP0_GP9_10_Xo4(M3_CalP1_SP0_GP9_10_line2, M3_CalP1_SP0_GP9_10_line3, M3_CalP1_Propbus_1); inv M3_CalP1_SP0_GP9_11_Xo0(Xbus_2, M3_CalP1_SP0_GP9_11_NotA); inv M3_CalP1_SP0_GP9_11_Xo1(in523, M3_CalP1_SP0_GP9_11_NotB); nand2 M3_CalP1_SP0_GP9_11_Xo2(M3_CalP1_SP0_GP9_11_NotA, in523, M3_CalP1_SP0_GP9_11_line2); nand2 M3_CalP1_SP0_GP9_11_Xo3(M3_CalP1_SP0_GP9_11_NotB, Xbus_2, M3_CalP1_SP0_GP9_11_line3); nand2 M3_CalP1_SP0_GP9_11_Xo4(M3_CalP1_SP0_GP9_11_line2, M3_CalP1_SP0_GP9_11_line3, M3_CalP1_Propbus_2); inv M3_CalP1_SP0_GP9_12_Xo0(Xbus_3, M3_CalP1_SP0_GP9_12_NotA); inv M3_CalP1_SP0_GP9_12_Xo1(in514, M3_CalP1_SP0_GP9_12_NotB); nand2 M3_CalP1_SP0_GP9_12_Xo2(M3_CalP1_SP0_GP9_12_NotA, in514, M3_CalP1_SP0_GP9_12_line2); nand2 M3_CalP1_SP0_GP9_12_Xo3(M3_CalP1_SP0_GP9_12_NotB, Xbus_3, M3_CalP1_SP0_GP9_12_line3); nand2 M3_CalP1_SP0_GP9_12_Xo4(M3_CalP1_SP0_GP9_12_line2, M3_CalP1_SP0_GP9_12_line3, M3_CalP1_Propbus_3); inv M3_CalP1_SP0_GP9_13_Xo0(Xbus_4, M3_CalP1_SP0_GP9_13_NotA); inv M3_CalP1_SP0_GP9_13_Xo1(in503, M3_CalP1_SP0_GP9_13_NotB); nand2 M3_CalP1_SP0_GP9_13_Xo2(M3_CalP1_SP0_GP9_13_NotA, in503, M3_CalP1_SP0_GP9_13_line2); nand2 M3_CalP1_SP0_GP9_13_Xo3(M3_CalP1_SP0_GP9_13_NotB, Xbus_4, M3_CalP1_SP0_GP9_13_line3); nand2 M3_CalP1_SP0_GP9_13_Xo4(M3_CalP1_SP0_GP9_13_line2, M3_CalP1_SP0_GP9_13_line3, M3_CalP1_Propbus_4); inv M3_CalP1_SP0_GP9_14_Xo0(Xbus_5, M3_CalP1_SP0_GP9_14_NotA); inv M3_CalP1_SP0_GP9_14_Xo1(in490, M3_CalP1_SP0_GP9_14_NotB); nand2 M3_CalP1_SP0_GP9_14_Xo2(M3_CalP1_SP0_GP9_14_NotA, in490, M3_CalP1_SP0_GP9_14_line2); nand2 M3_CalP1_SP0_GP9_14_Xo3(M3_CalP1_SP0_GP9_14_NotB, Xbus_5, M3_CalP1_SP0_GP9_14_line3); nand2 M3_CalP1_SP0_GP9_14_Xo4(M3_CalP1_SP0_GP9_14_line2, M3_CalP1_SP0_GP9_14_line3, M3_CalP1_Propbus_5); inv M3_CalP1_SP0_GP9_15_Xo0(Xbus_6, M3_CalP1_SP0_GP9_15_NotA); inv M3_CalP1_SP0_GP9_15_Xo1(in479, M3_CalP1_SP0_GP9_15_NotB); nand2 M3_CalP1_SP0_GP9_15_Xo2(M3_CalP1_SP0_GP9_15_NotA, in479, M3_CalP1_SP0_GP9_15_line2); nand2 M3_CalP1_SP0_GP9_15_Xo3(M3_CalP1_SP0_GP9_15_NotB, Xbus_6, M3_CalP1_SP0_GP9_15_line3); nand2 M3_CalP1_SP0_GP9_15_Xo4(M3_CalP1_SP0_GP9_15_line2, M3_CalP1_SP0_GP9_15_line3, M3_CalP1_Propbus_6); inv M3_CalP1_SP0_GP9_16_Xo0(Xbus_7, M3_CalP1_SP0_GP9_16_NotA); inv M3_CalP1_SP0_GP9_16_Xo1(vdd, M3_CalP1_SP0_GP9_16_NotB); nand2 M3_CalP1_SP0_GP9_16_Xo2(M3_CalP1_SP0_GP9_16_NotA, vdd, M3_CalP1_SP0_GP9_16_line2); nand2 M3_CalP1_SP0_GP9_16_Xo3(M3_CalP1_SP0_GP9_16_NotB, Xbus_7, M3_CalP1_SP0_GP9_16_line3); nand2 M3_CalP1_SP0_GP9_16_Xo4(M3_CalP1_SP0_GP9_16_line2, M3_CalP1_SP0_GP9_16_line3, M3_CalP1_Propbus_7); inv M3_CalP1_SP0_GP9_17_Xo0(Xbus_8, M3_CalP1_SP0_GP9_17_NotA); inv M3_CalP1_SP0_GP9_17_Xo1(vdd, M3_CalP1_SP0_GP9_17_NotB); nand2 M3_CalP1_SP0_GP9_17_Xo2(M3_CalP1_SP0_GP9_17_NotA, vdd, M3_CalP1_SP0_GP9_17_line2); nand2 M3_CalP1_SP0_GP9_17_Xo3(M3_CalP1_SP0_GP9_17_NotB, Xbus_8, M3_CalP1_SP0_GP9_17_line3); nand2 M3_CalP1_SP0_GP9_17_Xo4(M3_CalP1_SP0_GP9_17_line2, M3_CalP1_SP0_GP9_17_line3, M3_CalP1_Propbus_8); or2 M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_0(M3_CalP1_Genbus_0, M3_CalP1_Propbus_0, M3_CalP1_LocalC1_0); and2 M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_1_Ao2_0(M3_CalP1_Propbus_1, M3_CalP1_Genbus_0, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_1_line0); or2 M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_1_Ao2_1(M3_CalP1_Genbus_1, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_1_line0, M3_CalP1_LocalC0_1); and2 M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_Ao3a_0(M3_CalP1_Propbus_1, M3_CalP1_Genbus_0, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_line0); and2 M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_Ao3a_1(M3_CalP1_Propbus_1, M3_CalP1_Propbus_0, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_line1); or3 M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_Ao3a_2(M3_CalP1_Genbus_1, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_line0, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_line1, M3_CalP1_LocalC1_1); and2 M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_Ao3a_0(M3_CalP1_Propbus_2, M3_CalP1_Genbus_1, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_line0); and3 M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_Ao3a_1(M3_CalP1_Propbus_2, M3_CalP1_Propbus_1, M3_CalP1_Genbus_0, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_line1); or3 M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_Ao3a_2(M3_CalP1_Genbus_2, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_line0, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_line1, M3_CalP1_LocalC0_2); and2 M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_Ao4a_0(M3_CalP1_Propbus_2, M3_CalP1_Genbus_1, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_line0); and3 M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_Ao4a_1(M3_CalP1_Propbus_2, M3_CalP1_Propbus_1, M3_CalP1_Genbus_0, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_line1); and3 M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_Ao4a_2(M3_CalP1_Propbus_2, M3_CalP1_Propbus_1, M3_CalP1_Propbus_0, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_line2); or4 M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_Ao4a_3(M3_CalP1_Genbus_2, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_line0, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_line1, M3_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_line2, M3_CalP1_LocalC1_2); and2 M3_CalP1_SP1_GLC5_0_GLC4_1_Ao4a_0(M3_CalP1_Propbus_3, M3_CalP1_Genbus_2, M3_CalP1_SP1_GLC5_0_GLC4_1_line0); and3 M3_CalP1_SP1_GLC5_0_GLC4_1_Ao4a_1(M3_CalP1_Propbus_3, M3_CalP1_Propbus_2, M3_CalP1_Genbus_1, M3_CalP1_SP1_GLC5_0_GLC4_1_line1); and4 M3_CalP1_SP1_GLC5_0_GLC4_1_Ao4a_2(M3_CalP1_Propbus_3, M3_CalP1_Propbus_2, M3_CalP1_Propbus_1, M3_CalP1_Genbus_0, M3_CalP1_SP1_GLC5_0_GLC4_1_line2); or4 M3_CalP1_SP1_GLC5_0_GLC4_1_Ao4a_3(M3_CalP1_Genbus_3, M3_CalP1_SP1_GLC5_0_GLC4_1_line0, M3_CalP1_SP1_GLC5_0_GLC4_1_line1, M3_CalP1_SP1_GLC5_0_GLC4_1_line2, M3_CalP1_LocalC0_3); and2 M3_CalP1_SP1_GLC5_0_GLC4_2_Ao5a_0(M3_CalP1_Propbus_3, M3_CalP1_Genbus_2, M3_CalP1_SP1_GLC5_0_GLC4_2_line0); and3 M3_CalP1_SP1_GLC5_0_GLC4_2_Ao5a_1(M3_CalP1_Propbus_3, M3_CalP1_Propbus_2, M3_CalP1_Genbus_1, M3_CalP1_SP1_GLC5_0_GLC4_2_line1); and4 M3_CalP1_SP1_GLC5_0_GLC4_2_Ao5a_2(M3_CalP1_Propbus_3, M3_CalP1_Propbus_2, M3_CalP1_Propbus_1, M3_CalP1_Genbus_0, M3_CalP1_SP1_GLC5_0_GLC4_2_line2); and4 M3_CalP1_SP1_GLC5_0_GLC4_2_Ao5a_3(M3_CalP1_Propbus_3, M3_CalP1_Propbus_2, M3_CalP1_Propbus_1, M3_CalP1_Propbus_0, M3_CalP1_SP1_GLC5_0_GLC4_2_line3); or5 M3_CalP1_SP1_GLC5_0_GLC4_2_Ao5a_4(M3_CalP1_Genbus_3, M3_CalP1_SP1_GLC5_0_GLC4_2_line0, M3_CalP1_SP1_GLC5_0_GLC4_2_line1, M3_CalP1_SP1_GLC5_0_GLC4_2_line2, M3_CalP1_SP1_GLC5_0_GLC4_2_line3, M3_CalP1_LocalC1_3); and2 M3_CalP1_SP1_GLC5_1_Ao5a_0(M3_CalP1_Propbus_4, M3_CalP1_Genbus_3, M3_CalP1_SP1_GLC5_1_line0); and3 M3_CalP1_SP1_GLC5_1_Ao5a_1(M3_CalP1_Propbus_4, M3_CalP1_Propbus_3, M3_CalP1_Genbus_2, M3_CalP1_SP1_GLC5_1_line1); and4 M3_CalP1_SP1_GLC5_1_Ao5a_2(M3_CalP1_Propbus_4, M3_CalP1_Propbus_3, M3_CalP1_Propbus_2, M3_CalP1_Genbus_1, M3_CalP1_SP1_GLC5_1_line2); and5 M3_CalP1_SP1_GLC5_1_Ao5a_3(M3_CalP1_Propbus_4, M3_CalP1_Propbus_3, M3_CalP1_Propbus_2, M3_CalP1_Propbus_1, M3_CalP1_Genbus_0, M3_CalP1_SP1_GLC5_1_line3); or5 M3_CalP1_SP1_GLC5_1_Ao5a_4(M3_CalP1_Genbus_4, M3_CalP1_SP1_GLC5_1_line0, M3_CalP1_SP1_GLC5_1_line1, M3_CalP1_SP1_GLC5_1_line2, M3_CalP1_SP1_GLC5_1_line3, M3_CalP1_LocalC0_4); and2 M3_CalP1_SP1_GLC5_2_Ao6a_0(M3_CalP1_Propbus_4, M3_CalP1_Genbus_3, M3_CalP1_SP1_GLC5_2_line0); and3 M3_CalP1_SP1_GLC5_2_Ao6a_1(M3_CalP1_Propbus_4, M3_CalP1_Propbus_3, M3_CalP1_Genbus_2, M3_CalP1_SP1_GLC5_2_line1); and4 M3_CalP1_SP1_GLC5_2_Ao6a_2(M3_CalP1_Propbus_4, M3_CalP1_Propbus_3, M3_CalP1_Propbus_2, M3_CalP1_Genbus_1, M3_CalP1_SP1_GLC5_2_line2); and5 M3_CalP1_SP1_GLC5_2_Ao6a_3(M3_CalP1_Propbus_4, M3_CalP1_Propbus_3, M3_CalP1_Propbus_2, M3_CalP1_Propbus_1, M3_CalP1_Genbus_0, M3_CalP1_SP1_GLC5_2_line3); and5 M3_CalP1_SP1_GLC5_2_Ao6a_4(M3_CalP1_Propbus_4, M3_CalP1_Propbus_3, M3_CalP1_Propbus_2, M3_CalP1_Propbus_1, M3_CalP1_Propbus_0, M3_CalP1_SP1_GLC5_2_line4); or6 M3_CalP1_SP1_GLC5_2_Ao6a_5(M3_CalP1_Genbus_4, M3_CalP1_SP1_GLC5_2_line0, M3_CalP1_SP1_GLC5_2_line1, M3_CalP1_SP1_GLC5_2_line2, M3_CalP1_SP1_GLC5_2_line3, M3_CalP1_SP1_GLC5_2_line4, M3_CalP1_LocalC1_4); or2 M3_CalP1_SP2_GLC4_0(M3_CalP1_Genbus_5, M3_CalP1_Propbus_5, M3_CalP1_LocalC1_5); and2 M3_CalP1_SP2_GLC4_1_Ao2_0(M3_CalP1_Propbus_6, M3_CalP1_Genbus_5, M3_CalP1_SP2_GLC4_1_line0); or2 M3_CalP1_SP2_GLC4_1_Ao2_1(M3_CalP1_Genbus_6, M3_CalP1_SP2_GLC4_1_line0, M3_CalP1_LocalC0_6); and2 M3_CalP1_SP2_GLC4_2_Ao3a_0(M3_CalP1_Propbus_6, M3_CalP1_Genbus_5, M3_CalP1_SP2_GLC4_2_line0); and2 M3_CalP1_SP2_GLC4_2_Ao3a_1(M3_CalP1_Propbus_6, M3_CalP1_Propbus_5, M3_CalP1_SP2_GLC4_2_line1); or3 M3_CalP1_SP2_GLC4_2_Ao3a_2(M3_CalP1_Genbus_6, M3_CalP1_SP2_GLC4_2_line0, M3_CalP1_SP2_GLC4_2_line1, M3_CalP1_LocalC1_6); and2 M3_CalP1_SP2_GLC4_3_Ao3a_0(M3_CalP1_Propbus_7, M3_CalP1_Genbus_6, M3_CalP1_SP2_GLC4_3_line0); and3 M3_CalP1_SP2_GLC4_3_Ao3a_1(M3_CalP1_Propbus_7, M3_CalP1_Propbus_6, M3_CalP1_Genbus_5, M3_CalP1_SP2_GLC4_3_line1); or3 M3_CalP1_SP2_GLC4_3_Ao3a_2(M3_CalP1_Genbus_7, M3_CalP1_SP2_GLC4_3_line0, M3_CalP1_SP2_GLC4_3_line1, M3_CalP1_LocalC0_7); and2 M3_CalP1_SP2_GLC4_4_Ao4a_0(M3_CalP1_Propbus_7, M3_CalP1_Genbus_6, M3_CalP1_SP2_GLC4_4_line0); and3 M3_CalP1_SP2_GLC4_4_Ao4a_1(M3_CalP1_Propbus_7, M3_CalP1_Propbus_6, M3_CalP1_Genbus_5, M3_CalP1_SP2_GLC4_4_line1); and3 M3_CalP1_SP2_GLC4_4_Ao4a_2(M3_CalP1_Propbus_7, M3_CalP1_Propbus_6, M3_CalP1_Propbus_5, M3_CalP1_SP2_GLC4_4_line2); or4 M3_CalP1_SP2_GLC4_4_Ao4a_3(M3_CalP1_Genbus_7, M3_CalP1_SP2_GLC4_4_line0, M3_CalP1_SP2_GLC4_4_line1, M3_CalP1_SP2_GLC4_4_line2, M3_CalP1_LocalC1_7); inv M3_CalP1_SP3_SP9nc0_SP7nc0_Xo0(M3_CalP1_Genbus_0, M3_CalP1_SP3_SP9nc0_SP7nc0_NotA); inv M3_CalP1_SP3_SP9nc0_SP7nc0_Xo1(M3_CalP1_LocalC0_1, M3_CalP1_SP3_SP9nc0_SP7nc0_NotB); nand2 M3_CalP1_SP3_SP9nc0_SP7nc0_Xo2(M3_CalP1_SP3_SP9nc0_SP7nc0_NotA, M3_CalP1_LocalC0_1, M3_CalP1_SP3_SP9nc0_SP7nc0_line2); nand2 M3_CalP1_SP3_SP9nc0_SP7nc0_Xo3(M3_CalP1_SP3_SP9nc0_SP7nc0_NotB, M3_CalP1_Genbus_0, M3_CalP1_SP3_SP9nc0_SP7nc0_line3); nand2 M3_CalP1_SP3_SP9nc0_SP7nc0_Xo4(M3_CalP1_SP3_SP9nc0_SP7nc0_line2, M3_CalP1_SP3_SP9nc0_SP7nc0_line3, M3_CalP1_SP3_SP9nc0_line0); inv M3_CalP1_SP3_SP9nc0_SP7nc1_Xo0(M3_CalP1_LocalC0_2, M3_CalP1_SP3_SP9nc0_SP7nc1_NotA); inv M3_CalP1_SP3_SP9nc0_SP7nc1_Xo1(M3_CalP1_SP3_SP9nc0_line0, M3_CalP1_SP3_SP9nc0_SP7nc1_NotB); nand2 M3_CalP1_SP3_SP9nc0_SP7nc1_Xo2(M3_CalP1_SP3_SP9nc0_SP7nc1_NotA, M3_CalP1_SP3_SP9nc0_line0, M3_CalP1_SP3_SP9nc0_SP7nc1_line2); nand2 M3_CalP1_SP3_SP9nc0_SP7nc1_Xo3(M3_CalP1_SP3_SP9nc0_SP7nc1_NotB, M3_CalP1_LocalC0_2, M3_CalP1_SP3_SP9nc0_SP7nc1_line3); nand2 M3_CalP1_SP3_SP9nc0_SP7nc1_Xo4(M3_CalP1_SP3_SP9nc0_SP7nc1_line2, M3_CalP1_SP3_SP9nc0_SP7nc1_line3, M3_CalP1_SP3_SP9nc0_line1); inv M3_CalP1_SP3_SP9nc0_SP7nc2_Xo0(M3_CalP1_LocalC0_3, M3_CalP1_SP3_SP9nc0_SP7nc2_NotA); inv M3_CalP1_SP3_SP9nc0_SP7nc2_Xo1(M3_CalP1_SP3_SP9nc0_line1, M3_CalP1_SP3_SP9nc0_SP7nc2_NotB); nand2 M3_CalP1_SP3_SP9nc0_SP7nc2_Xo2(M3_CalP1_SP3_SP9nc0_SP7nc2_NotA, M3_CalP1_SP3_SP9nc0_line1, M3_CalP1_SP3_SP9nc0_SP7nc2_line2); nand2 M3_CalP1_SP3_SP9nc0_SP7nc2_Xo3(M3_CalP1_SP3_SP9nc0_SP7nc2_NotB, M3_CalP1_LocalC0_3, M3_CalP1_SP3_SP9nc0_SP7nc2_line3); nand2 M3_CalP1_SP3_SP9nc0_SP7nc2_Xo4(M3_CalP1_SP3_SP9nc0_SP7nc2_line2, M3_CalP1_SP3_SP9nc0_SP7nc2_line3, M3_CalP1_SP3_SP9nc0_line2); inv M3_CalP1_SP3_SP9nc0_SP7nc3_Xo0(M3_CalP1_Propbus_0, M3_CalP1_SP3_SP9nc0_SP7nc3_NotA); inv M3_CalP1_SP3_SP9nc0_SP7nc3_Xo1(M3_CalP1_SP3_SP9nc0_line2, M3_CalP1_SP3_SP9nc0_SP7nc3_NotB); nand2 M3_CalP1_SP3_SP9nc0_SP7nc3_Xo2(M3_CalP1_SP3_SP9nc0_SP7nc3_NotA, M3_CalP1_SP3_SP9nc0_line2, M3_CalP1_SP3_SP9nc0_SP7nc3_line2); nand2 M3_CalP1_SP3_SP9nc0_SP7nc3_Xo3(M3_CalP1_SP3_SP9nc0_SP7nc3_NotB, M3_CalP1_Propbus_0, M3_CalP1_SP3_SP9nc0_SP7nc3_line3); nand2 M3_CalP1_SP3_SP9nc0_SP7nc3_Xo4(M3_CalP1_SP3_SP9nc0_SP7nc3_line2, M3_CalP1_SP3_SP9nc0_SP7nc3_line3, M3_CalP1_SP3_SP9nc0_line3); inv M3_CalP1_SP3_SP9nc0_SP7nc4_Xo0(M3_CalP1_Propbus_1, M3_CalP1_SP3_SP9nc0_SP7nc4_NotA); inv M3_CalP1_SP3_SP9nc0_SP7nc4_Xo1(M3_CalP1_SP3_SP9nc0_line3, M3_CalP1_SP3_SP9nc0_SP7nc4_NotB); nand2 M3_CalP1_SP3_SP9nc0_SP7nc4_Xo2(M3_CalP1_SP3_SP9nc0_SP7nc4_NotA, M3_CalP1_SP3_SP9nc0_line3, M3_CalP1_SP3_SP9nc0_SP7nc4_line2); nand2 M3_CalP1_SP3_SP9nc0_SP7nc4_Xo3(M3_CalP1_SP3_SP9nc0_SP7nc4_NotB, M3_CalP1_Propbus_1, M3_CalP1_SP3_SP9nc0_SP7nc4_line3); nand2 M3_CalP1_SP3_SP9nc0_SP7nc4_Xo4(M3_CalP1_SP3_SP9nc0_SP7nc4_line2, M3_CalP1_SP3_SP9nc0_SP7nc4_line3, M3_CalP1_SP3_SP9nc0_line4); inv M3_CalP1_SP3_SP9nc0_SP7nc5_Xo0(M3_CalP1_Propbus_2, M3_CalP1_SP3_SP9nc0_SP7nc5_NotA); inv M3_CalP1_SP3_SP9nc0_SP7nc5_Xo1(M3_CalP1_SP3_SP9nc0_line4, M3_CalP1_SP3_SP9nc0_SP7nc5_NotB); nand2 M3_CalP1_SP3_SP9nc0_SP7nc5_Xo2(M3_CalP1_SP3_SP9nc0_SP7nc5_NotA, M3_CalP1_SP3_SP9nc0_line4, M3_CalP1_SP3_SP9nc0_SP7nc5_line2); nand2 M3_CalP1_SP3_SP9nc0_SP7nc5_Xo3(M3_CalP1_SP3_SP9nc0_SP7nc5_NotB, M3_CalP1_Propbus_2, M3_CalP1_SP3_SP9nc0_SP7nc5_line3); nand2 M3_CalP1_SP3_SP9nc0_SP7nc5_Xo4(M3_CalP1_SP3_SP9nc0_SP7nc5_line2, M3_CalP1_SP3_SP9nc0_SP7nc5_line3, M3_CalP1_SP3_line0); inv M3_CalP1_SP3_SP9nc1_Xo0(M3_CalP1_Propbus_3, M3_CalP1_SP3_SP9nc1_NotA); inv M3_CalP1_SP3_SP9nc1_Xo1(M3_CalP1_SP3_line0, M3_CalP1_SP3_SP9nc1_NotB); nand2 M3_CalP1_SP3_SP9nc1_Xo2(M3_CalP1_SP3_SP9nc1_NotA, M3_CalP1_SP3_line0, M3_CalP1_SP3_SP9nc1_line2); nand2 M3_CalP1_SP3_SP9nc1_Xo3(M3_CalP1_SP3_SP9nc1_NotB, M3_CalP1_Propbus_3, M3_CalP1_SP3_SP9nc1_line3); nand2 M3_CalP1_SP3_SP9nc1_Xo4(M3_CalP1_SP3_SP9nc1_line2, M3_CalP1_SP3_SP9nc1_line3, M3_CalP1_SP3_line1); inv M3_CalP1_SP3_SP9nc2_Xo0(M3_CalP1_Propbus_4, M3_CalP1_SP3_SP9nc2_NotA); inv M3_CalP1_SP3_SP9nc2_Xo1(M3_CalP1_SP3_line1, M3_CalP1_SP3_SP9nc2_NotB); nand2 M3_CalP1_SP3_SP9nc2_Xo2(M3_CalP1_SP3_SP9nc2_NotA, M3_CalP1_SP3_line1, M3_CalP1_SP3_SP9nc2_line2); nand2 M3_CalP1_SP3_SP9nc2_Xo3(M3_CalP1_SP3_SP9nc2_NotB, M3_CalP1_Propbus_4, M3_CalP1_SP3_SP9nc2_line3); nand2 M3_CalP1_SP3_SP9nc2_Xo4(M3_CalP1_SP3_SP9nc2_line2, M3_CalP1_SP3_SP9nc2_line3, M3_CalP1_ParLo0); inv M3_CalP1_SP4_SP9nc0_SP7c0(M3_CalP1_Propbus_2, M3_CalP1_SP4_SP9nc0_NewInbus_6); inv M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_Xo0(M3_CalP1_LocalC1_0, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_NotA); inv M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_Xo1(M3_CalP1_LocalC1_1, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_NotB); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_Xo2(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_NotA, M3_CalP1_LocalC1_1, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_line2); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_Xo3(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_NotB, M3_CalP1_LocalC1_0, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_line3); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_Xo4(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_line2, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_line3, M3_CalP1_SP4_SP9nc0_SP7c2_line0); inv M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_Xo0(M3_CalP1_LocalC1_2, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_NotA); inv M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_Xo1(M3_CalP1_SP4_SP9nc0_SP7c2_line0, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_NotB); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_Xo2(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_NotA, M3_CalP1_SP4_SP9nc0_SP7c2_line0, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_line2); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_Xo3(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_NotB, M3_CalP1_LocalC1_2, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_line3); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_Xo4(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_line2, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_line3, M3_CalP1_SP4_SP9nc0_SP7c2_line1); inv M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_Xo0(M3_CalP1_LocalC1_3, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_NotA); inv M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_Xo1(M3_CalP1_SP4_SP9nc0_SP7c2_line1, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_NotB); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_Xo2(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_NotA, M3_CalP1_SP4_SP9nc0_SP7c2_line1, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_line2); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_Xo3(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_NotB, M3_CalP1_LocalC1_3, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_line3); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_Xo4(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_line2, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_line3, M3_CalP1_SP4_SP9nc0_SP7c2_line2); inv M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_Xo0(M3_CalP1_Propbus_0, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_NotA); inv M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_Xo1(M3_CalP1_SP4_SP9nc0_SP7c2_line2, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_NotB); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_Xo2(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_NotA, M3_CalP1_SP4_SP9nc0_SP7c2_line2, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_line2); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_Xo3(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_NotB, M3_CalP1_Propbus_0, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_line3); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_Xo4(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_line2, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_line3, M3_CalP1_SP4_SP9nc0_SP7c2_line3); inv M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_Xo0(M3_CalP1_Propbus_1, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_NotA); inv M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_Xo1(M3_CalP1_SP4_SP9nc0_SP7c2_line3, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_NotB); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_Xo2(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_NotA, M3_CalP1_SP4_SP9nc0_SP7c2_line3, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_line2); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_Xo3(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_NotB, M3_CalP1_Propbus_1, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_line3); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_Xo4(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_line2, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_line3, M3_CalP1_SP4_SP9nc0_SP7c2_line4); inv M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_Xo0(M3_CalP1_SP4_SP9nc0_NewInbus_6, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_NotA); inv M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_Xo1(M3_CalP1_SP4_SP9nc0_SP7c2_line4, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_NotB); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_Xo2(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_NotA, M3_CalP1_SP4_SP9nc0_SP7c2_line4, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_line2); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_Xo3(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_NotB, M3_CalP1_SP4_SP9nc0_NewInbus_6, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_line3); nand2 M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_Xo4(M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_line2, M3_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_line3, M3_CalP1_SP4_line0); inv M3_CalP1_SP4_SP9nc1_Xo0(M3_CalP1_Propbus_3, M3_CalP1_SP4_SP9nc1_NotA); inv M3_CalP1_SP4_SP9nc1_Xo1(M3_CalP1_SP4_line0, M3_CalP1_SP4_SP9nc1_NotB); nand2 M3_CalP1_SP4_SP9nc1_Xo2(M3_CalP1_SP4_SP9nc1_NotA, M3_CalP1_SP4_line0, M3_CalP1_SP4_SP9nc1_line2); nand2 M3_CalP1_SP4_SP9nc1_Xo3(M3_CalP1_SP4_SP9nc1_NotB, M3_CalP1_Propbus_3, M3_CalP1_SP4_SP9nc1_line3); nand2 M3_CalP1_SP4_SP9nc1_Xo4(M3_CalP1_SP4_SP9nc1_line2, M3_CalP1_SP4_SP9nc1_line3, M3_CalP1_SP4_line1); inv M3_CalP1_SP4_SP9nc2_Xo0(M3_CalP1_Propbus_4, M3_CalP1_SP4_SP9nc2_NotA); inv M3_CalP1_SP4_SP9nc2_Xo1(M3_CalP1_SP4_line1, M3_CalP1_SP4_SP9nc2_NotB); nand2 M3_CalP1_SP4_SP9nc2_Xo2(M3_CalP1_SP4_SP9nc2_NotA, M3_CalP1_SP4_line1, M3_CalP1_SP4_SP9nc2_line2); nand2 M3_CalP1_SP4_SP9nc2_Xo3(M3_CalP1_SP4_SP9nc2_NotB, M3_CalP1_Propbus_4, M3_CalP1_SP4_SP9nc2_line3); nand2 M3_CalP1_SP4_SP9nc2_Xo4(M3_CalP1_SP4_SP9nc2_line2, M3_CalP1_SP4_SP9nc2_line3, M3_CalP1_ParLo1); inv M3_CalP1_SP5_SP7nc0_Xo0(M3_CalP1_Genbus_5, M3_CalP1_SP5_SP7nc0_NotA); inv M3_CalP1_SP5_SP7nc0_Xo1(M3_CalP1_LocalC0_6, M3_CalP1_SP5_SP7nc0_NotB); nand2 M3_CalP1_SP5_SP7nc0_Xo2(M3_CalP1_SP5_SP7nc0_NotA, M3_CalP1_LocalC0_6, M3_CalP1_SP5_SP7nc0_line2); nand2 M3_CalP1_SP5_SP7nc0_Xo3(M3_CalP1_SP5_SP7nc0_NotB, M3_CalP1_Genbus_5, M3_CalP1_SP5_SP7nc0_line3); nand2 M3_CalP1_SP5_SP7nc0_Xo4(M3_CalP1_SP5_SP7nc0_line2, M3_CalP1_SP5_SP7nc0_line3, M3_CalP1_SP5_line0); inv M3_CalP1_SP5_SP7nc1_Xo0(M3_CalP1_LocalC0_7, M3_CalP1_SP5_SP7nc1_NotA); inv M3_CalP1_SP5_SP7nc1_Xo1(M3_CalP1_SP5_line0, M3_CalP1_SP5_SP7nc1_NotB); nand2 M3_CalP1_SP5_SP7nc1_Xo2(M3_CalP1_SP5_SP7nc1_NotA, M3_CalP1_SP5_line0, M3_CalP1_SP5_SP7nc1_line2); nand2 M3_CalP1_SP5_SP7nc1_Xo3(M3_CalP1_SP5_SP7nc1_NotB, M3_CalP1_LocalC0_7, M3_CalP1_SP5_SP7nc1_line3); nand2 M3_CalP1_SP5_SP7nc1_Xo4(M3_CalP1_SP5_SP7nc1_line2, M3_CalP1_SP5_SP7nc1_line3, M3_CalP1_SP5_line1); inv M3_CalP1_SP5_SP7nc2_Xo0(M3_CalP1_Propbus_5, M3_CalP1_SP5_SP7nc2_NotA); inv M3_CalP1_SP5_SP7nc2_Xo1(M3_CalP1_SP5_line1, M3_CalP1_SP5_SP7nc2_NotB); nand2 M3_CalP1_SP5_SP7nc2_Xo2(M3_CalP1_SP5_SP7nc2_NotA, M3_CalP1_SP5_line1, M3_CalP1_SP5_SP7nc2_line2); nand2 M3_CalP1_SP5_SP7nc2_Xo3(M3_CalP1_SP5_SP7nc2_NotB, M3_CalP1_Propbus_5, M3_CalP1_SP5_SP7nc2_line3); nand2 M3_CalP1_SP5_SP7nc2_Xo4(M3_CalP1_SP5_SP7nc2_line2, M3_CalP1_SP5_SP7nc2_line3, M3_CalP1_SP5_line2); inv M3_CalP1_SP5_SP7nc3_Xo0(M3_CalP1_Propbus_6, M3_CalP1_SP5_SP7nc3_NotA); inv M3_CalP1_SP5_SP7nc3_Xo1(M3_CalP1_SP5_line2, M3_CalP1_SP5_SP7nc3_NotB); nand2 M3_CalP1_SP5_SP7nc3_Xo2(M3_CalP1_SP5_SP7nc3_NotA, M3_CalP1_SP5_line2, M3_CalP1_SP5_SP7nc3_line2); nand2 M3_CalP1_SP5_SP7nc3_Xo3(M3_CalP1_SP5_SP7nc3_NotB, M3_CalP1_Propbus_6, M3_CalP1_SP5_SP7nc3_line3); nand2 M3_CalP1_SP5_SP7nc3_Xo4(M3_CalP1_SP5_SP7nc3_line2, M3_CalP1_SP5_SP7nc3_line3, M3_CalP1_SP5_line3); inv M3_CalP1_SP5_SP7nc4_Xo0(M3_CalP1_Propbus_7, M3_CalP1_SP5_SP7nc4_NotA); inv M3_CalP1_SP5_SP7nc4_Xo1(M3_CalP1_SP5_line3, M3_CalP1_SP5_SP7nc4_NotB); nand2 M3_CalP1_SP5_SP7nc4_Xo2(M3_CalP1_SP5_SP7nc4_NotA, M3_CalP1_SP5_line3, M3_CalP1_SP5_SP7nc4_line2); nand2 M3_CalP1_SP5_SP7nc4_Xo3(M3_CalP1_SP5_SP7nc4_NotB, M3_CalP1_Propbus_7, M3_CalP1_SP5_SP7nc4_line3); nand2 M3_CalP1_SP5_SP7nc4_Xo4(M3_CalP1_SP5_SP7nc4_line2, M3_CalP1_SP5_SP7nc4_line3, M3_CalP1_SP5_line4); inv M3_CalP1_SP5_SP7nc5_Xo0(M3_CalP1_Propbus_8, M3_CalP1_SP5_SP7nc5_NotA); inv M3_CalP1_SP5_SP7nc5_Xo1(M3_CalP1_SP5_line4, M3_CalP1_SP5_SP7nc5_NotB); nand2 M3_CalP1_SP5_SP7nc5_Xo2(M3_CalP1_SP5_SP7nc5_NotA, M3_CalP1_SP5_line4, M3_CalP1_SP5_SP7nc5_line2); nand2 M3_CalP1_SP5_SP7nc5_Xo3(M3_CalP1_SP5_SP7nc5_NotB, M3_CalP1_Propbus_8, M3_CalP1_SP5_SP7nc5_line3); nand2 M3_CalP1_SP5_SP7nc5_Xo4(M3_CalP1_SP5_SP7nc5_line2, M3_CalP1_SP5_SP7nc5_line3, M3_CalP1_ParHi0); inv M3_CalP1_SP6_SP7c0(M3_CalP1_Propbus_8, M3_CalP1_SP6_NewInbus_6); inv M3_CalP1_SP6_SP7c2_SP7nc0_Xo0(M3_CalP1_LocalC1_5, M3_CalP1_SP6_SP7c2_SP7nc0_NotA); inv M3_CalP1_SP6_SP7c2_SP7nc0_Xo1(M3_CalP1_LocalC1_6, M3_CalP1_SP6_SP7c2_SP7nc0_NotB); nand2 M3_CalP1_SP6_SP7c2_SP7nc0_Xo2(M3_CalP1_SP6_SP7c2_SP7nc0_NotA, M3_CalP1_LocalC1_6, M3_CalP1_SP6_SP7c2_SP7nc0_line2); nand2 M3_CalP1_SP6_SP7c2_SP7nc0_Xo3(M3_CalP1_SP6_SP7c2_SP7nc0_NotB, M3_CalP1_LocalC1_5, M3_CalP1_SP6_SP7c2_SP7nc0_line3); nand2 M3_CalP1_SP6_SP7c2_SP7nc0_Xo4(M3_CalP1_SP6_SP7c2_SP7nc0_line2, M3_CalP1_SP6_SP7c2_SP7nc0_line3, M3_CalP1_SP6_SP7c2_line0); inv M3_CalP1_SP6_SP7c2_SP7nc1_Xo0(M3_CalP1_LocalC1_7, M3_CalP1_SP6_SP7c2_SP7nc1_NotA); inv M3_CalP1_SP6_SP7c2_SP7nc1_Xo1(M3_CalP1_SP6_SP7c2_line0, M3_CalP1_SP6_SP7c2_SP7nc1_NotB); nand2 M3_CalP1_SP6_SP7c2_SP7nc1_Xo2(M3_CalP1_SP6_SP7c2_SP7nc1_NotA, M3_CalP1_SP6_SP7c2_line0, M3_CalP1_SP6_SP7c2_SP7nc1_line2); nand2 M3_CalP1_SP6_SP7c2_SP7nc1_Xo3(M3_CalP1_SP6_SP7c2_SP7nc1_NotB, M3_CalP1_LocalC1_7, M3_CalP1_SP6_SP7c2_SP7nc1_line3); nand2 M3_CalP1_SP6_SP7c2_SP7nc1_Xo4(M3_CalP1_SP6_SP7c2_SP7nc1_line2, M3_CalP1_SP6_SP7c2_SP7nc1_line3, M3_CalP1_SP6_SP7c2_line1); inv M3_CalP1_SP6_SP7c2_SP7nc2_Xo0(M3_CalP1_Propbus_5, M3_CalP1_SP6_SP7c2_SP7nc2_NotA); inv M3_CalP1_SP6_SP7c2_SP7nc2_Xo1(M3_CalP1_SP6_SP7c2_line1, M3_CalP1_SP6_SP7c2_SP7nc2_NotB); nand2 M3_CalP1_SP6_SP7c2_SP7nc2_Xo2(M3_CalP1_SP6_SP7c2_SP7nc2_NotA, M3_CalP1_SP6_SP7c2_line1, M3_CalP1_SP6_SP7c2_SP7nc2_line2); nand2 M3_CalP1_SP6_SP7c2_SP7nc2_Xo3(M3_CalP1_SP6_SP7c2_SP7nc2_NotB, M3_CalP1_Propbus_5, M3_CalP1_SP6_SP7c2_SP7nc2_line3); nand2 M3_CalP1_SP6_SP7c2_SP7nc2_Xo4(M3_CalP1_SP6_SP7c2_SP7nc2_line2, M3_CalP1_SP6_SP7c2_SP7nc2_line3, M3_CalP1_SP6_SP7c2_line2); inv M3_CalP1_SP6_SP7c2_SP7nc3_Xo0(M3_CalP1_Propbus_6, M3_CalP1_SP6_SP7c2_SP7nc3_NotA); inv M3_CalP1_SP6_SP7c2_SP7nc3_Xo1(M3_CalP1_SP6_SP7c2_line2, M3_CalP1_SP6_SP7c2_SP7nc3_NotB); nand2 M3_CalP1_SP6_SP7c2_SP7nc3_Xo2(M3_CalP1_SP6_SP7c2_SP7nc3_NotA, M3_CalP1_SP6_SP7c2_line2, M3_CalP1_SP6_SP7c2_SP7nc3_line2); nand2 M3_CalP1_SP6_SP7c2_SP7nc3_Xo3(M3_CalP1_SP6_SP7c2_SP7nc3_NotB, M3_CalP1_Propbus_6, M3_CalP1_SP6_SP7c2_SP7nc3_line3); nand2 M3_CalP1_SP6_SP7c2_SP7nc3_Xo4(M3_CalP1_SP6_SP7c2_SP7nc3_line2, M3_CalP1_SP6_SP7c2_SP7nc3_line3, M3_CalP1_SP6_SP7c2_line3); inv M3_CalP1_SP6_SP7c2_SP7nc4_Xo0(M3_CalP1_Propbus_7, M3_CalP1_SP6_SP7c2_SP7nc4_NotA); inv M3_CalP1_SP6_SP7c2_SP7nc4_Xo1(M3_CalP1_SP6_SP7c2_line3, M3_CalP1_SP6_SP7c2_SP7nc4_NotB); nand2 M3_CalP1_SP6_SP7c2_SP7nc4_Xo2(M3_CalP1_SP6_SP7c2_SP7nc4_NotA, M3_CalP1_SP6_SP7c2_line3, M3_CalP1_SP6_SP7c2_SP7nc4_line2); nand2 M3_CalP1_SP6_SP7c2_SP7nc4_Xo3(M3_CalP1_SP6_SP7c2_SP7nc4_NotB, M3_CalP1_Propbus_7, M3_CalP1_SP6_SP7c2_SP7nc4_line3); nand2 M3_CalP1_SP6_SP7c2_SP7nc4_Xo4(M3_CalP1_SP6_SP7c2_SP7nc4_line2, M3_CalP1_SP6_SP7c2_SP7nc4_line3, M3_CalP1_SP6_SP7c2_line4); inv M3_CalP1_SP6_SP7c2_SP7nc5_Xo0(M3_CalP1_SP6_NewInbus_6, M3_CalP1_SP6_SP7c2_SP7nc5_NotA); inv M3_CalP1_SP6_SP7c2_SP7nc5_Xo1(M3_CalP1_SP6_SP7c2_line4, M3_CalP1_SP6_SP7c2_SP7nc5_NotB); nand2 M3_CalP1_SP6_SP7c2_SP7nc5_Xo2(M3_CalP1_SP6_SP7c2_SP7nc5_NotA, M3_CalP1_SP6_SP7c2_line4, M3_CalP1_SP6_SP7c2_SP7nc5_line2); nand2 M3_CalP1_SP6_SP7c2_SP7nc5_Xo3(M3_CalP1_SP6_SP7c2_SP7nc5_NotB, M3_CalP1_SP6_NewInbus_6, M3_CalP1_SP6_SP7c2_SP7nc5_line3); nand2 M3_CalP1_SP6_SP7c2_SP7nc5_Xo4(M3_CalP1_SP6_SP7c2_SP7nc5_line2, M3_CalP1_SP6_SP7c2_SP7nc5_line3, M3_CalP1_ParHi1); inv M3_CalP1_SP7_Mux2_0(in2174, M3_CalP1_SP7_Not_ContIn); and2 M3_CalP1_SP7_Mux2_1(M3_CalP1_ParLo0, M3_CalP1_SP7_Not_ContIn, M3_CalP1_SP7_line1); and2 M3_CalP1_SP7_Mux2_2(M3_CalP1_ParLo1, in2174, M3_CalP1_SP7_line2); or2 M3_CalP1_SP7_Mux2_3(M3_CalP1_SP7_line1, M3_CalP1_SP7_line2, M3_CalP1_ParLo); inv M3_CalP1_SP8_Mux2_0(M3_CalP1_LocalC0_4, M3_CalP1_SP8_Not_ContIn); and2 M3_CalP1_SP8_Mux2_1(M3_CalP1_ParHi0, M3_CalP1_SP8_Not_ContIn, M3_CalP1_SP8_line1); and2 M3_CalP1_SP8_Mux2_2(M3_CalP1_ParHi1, M3_CalP1_LocalC0_4, M3_CalP1_SP8_line2); or2 M3_CalP1_SP8_Mux2_3(M3_CalP1_SP8_line1, M3_CalP1_SP8_line2, M3_CalP1_ParHiCin0); inv M3_CalP1_SP9_Mux2_0(M3_CalP1_LocalC1_4, M3_CalP1_SP9_Not_ContIn); and2 M3_CalP1_SP9_Mux2_1(M3_CalP1_ParHi0, M3_CalP1_SP9_Not_ContIn, M3_CalP1_SP9_line1); and2 M3_CalP1_SP9_Mux2_2(M3_CalP1_ParHi1, M3_CalP1_LocalC1_4, M3_CalP1_SP9_line2); or2 M3_CalP1_SP9_Mux2_3(M3_CalP1_SP9_line1, M3_CalP1_SP9_line2, M3_CalP1_ParHiCin1); inv M3_CalP1_SP10_Mux2_0(in2174, M3_CalP1_SP10_Not_ContIn); and2 M3_CalP1_SP10_Mux2_1(M3_CalP1_ParHiCin0, M3_CalP1_SP10_Not_ContIn, M3_CalP1_SP10_line1); and2 M3_CalP1_SP10_Mux2_2(M3_CalP1_ParHiCin1, in2174, M3_CalP1_SP10_line2); or2 M3_CalP1_SP10_Mux2_3(M3_CalP1_SP10_line1, M3_CalP1_SP10_line2, M3_CalP1_ParHi); inv M3_CalP1_SP11_Xo0(M3_CalP1_ParLo, M3_CalP1_SP11_NotA); inv M3_CalP1_SP11_Xo1(M3_CalP1_ParHi, M3_CalP1_SP11_NotB); nand2 M3_CalP1_SP11_Xo2(M3_CalP1_SP11_NotA, M3_CalP1_ParHi, M3_CalP1_SP11_line2); nand2 M3_CalP1_SP11_Xo3(M3_CalP1_SP11_NotB, M3_CalP1_ParLo, M3_CalP1_SP11_line3); nand2 M3_CalP1_SP11_Xo4(M3_CalP1_SP11_line2, M3_CalP1_SP11_line3, M3_SumPar); inv M3_CalP2_M2M4_0(M3_LogicPar, M3_CalP2_NotLogicPar); inv M3_CalP2_M2M4_1(M3_SumPar, M3_CalP2_NotSumPar); inv M3_CalP2_M2M4_2_Mux2_0(in4091, M3_CalP2_M2M4_2_Not_ContIn); and2 M3_CalP2_M2M4_2_Mux2_1(M3_CalP2_NotLogicPar, M3_CalP2_M2M4_2_Not_ContIn, M3_CalP2_M2M4_2_line1); and2 M3_CalP2_M2M4_2_Mux2_2(M3_CalP2_NotSumPar, in4091, M3_CalP2_M2M4_2_line2); or2 M3_CalP2_M2M4_2_Mux2_3(M3_CalP2_M2M4_2_line1, M3_CalP2_M2M4_2_line2, M3_CalP2_line0); inv M3_CalP2_M2M4_3_Mux2_0(in4092, M3_CalP2_M2M4_3_Not_ContIn); and2 M3_CalP2_M2M4_3_Mux2_1(M3_CalP2_line0, M3_CalP2_M2M4_3_Not_ContIn, M3_CalP2_M2M4_3_line1); and2 M3_CalP2_M2M4_3_Mux2_2(in94, in4092, M3_CalP2_M2M4_3_line2); or2 M3_CalP2_M2M4_3_Mux2_3(M3_CalP2_M2M4_3_line1, M3_CalP2_M2M4_3_line2, Not_SumLogicParX); inv M3_CalP2_M2M4_4_Mux4_0(in4092, M3_CalP2_M2M4_4_Not_ContLo); inv M3_CalP2_M2M4_4_Mux4_1(in4091, M3_CalP2_M2M4_4_Not_ContHi); and3 M3_CalP2_M2M4_4_Mux4_2(M3_LogicPar, M3_CalP2_M2M4_4_Not_ContHi, M3_CalP2_M2M4_4_Not_ContLo, M3_CalP2_M2M4_4_line2); and3 M3_CalP2_M2M4_4_Mux4_3(in120, M3_CalP2_M2M4_4_Not_ContHi, in4092, M3_CalP2_M2M4_4_line3); and3 M3_CalP2_M2M4_4_Mux4_4(M3_SumPar, in4091, M3_CalP2_M2M4_4_Not_ContLo, M3_CalP2_M2M4_4_line4); and3 M3_CalP2_M2M4_4_Mux4_5(vdd, in4091, in4092, M3_CalP2_M2M4_4_line5); or4 M3_CalP2_M2M4_4_Mux4_6(M3_CalP2_M2M4_4_line2, M3_CalP2_M2M4_4_line3, M3_CalP2_M2M4_4_line4, M3_CalP2_M2M4_4_line5, out843); inv M4_CalP0_LP0_CL0_LB0_Mux2_0(in281, M4_CalP0_LP0_CL0_LB0_Not_ContIn); and2 M4_CalP0_LP0_CL0_LB0_Mux2_1(in254, M4_CalP0_LP0_CL0_LB0_Not_ContIn, M4_CalP0_LP0_CL0_LB0_line1); and2 M4_CalP0_LP0_CL0_LB0_Mux2_2(in242, in281, M4_CalP0_LP0_CL0_LB0_line2); or2 M4_CalP0_LP0_CL0_LB0_Mux2_3(M4_CalP0_LP0_CL0_LB0_line1, M4_CalP0_LP0_CL0_LB0_line2, M4_CalP0_LP0_CL0_line0); inv M4_CalP0_LP0_CL0_LB1_Mux2_0(in281, M4_CalP0_LP0_CL0_LB1_Not_ContIn); and2 M4_CalP0_LP0_CL0_LB1_Mux2_1(in251, M4_CalP0_LP0_CL0_LB1_Not_ContIn, M4_CalP0_LP0_CL0_LB1_line1); and2 M4_CalP0_LP0_CL0_LB1_Mux2_2(in248, in281, M4_CalP0_LP0_CL0_LB1_line2); or2 M4_CalP0_LP0_CL0_LB1_Mux2_3(M4_CalP0_LP0_CL0_LB1_line1, M4_CalP0_LP0_CL0_LB1_line2, M4_CalP0_LP0_CL0_line1); or2 M4_CalP0_LP0_CL0_LB2(in374, M4_CalP0_LP0_CL0_line0, M4_CalP0_LP0_CL0_line2); nand2 M4_CalP0_LP0_CL0_LB3(in374, M4_CalP0_LP0_CL0_line1, M4_CalP0_LP0_CL0_line3); and2 M4_CalP0_LP0_CL0_LB4(M4_CalP0_LP0_CL0_line2, M4_CalP0_LP0_CL0_line3, M4_CalP0_LogicOut_0); inv M4_CalP0_LP0_CL1_LB0_Mux2_0(in273, M4_CalP0_LP0_CL1_LB0_Not_ContIn); and2 M4_CalP0_LP0_CL1_LB0_Mux2_1(in254, M4_CalP0_LP0_CL1_LB0_Not_ContIn, M4_CalP0_LP0_CL1_LB0_line1); and2 M4_CalP0_LP0_CL1_LB0_Mux2_2(in242, in273, M4_CalP0_LP0_CL1_LB0_line2); or2 M4_CalP0_LP0_CL1_LB0_Mux2_3(M4_CalP0_LP0_CL1_LB0_line1, M4_CalP0_LP0_CL1_LB0_line2, M4_CalP0_LP0_CL1_line0); inv M4_CalP0_LP0_CL1_LB1_Mux2_0(in273, M4_CalP0_LP0_CL1_LB1_Not_ContIn); and2 M4_CalP0_LP0_CL1_LB1_Mux2_1(in251, M4_CalP0_LP0_CL1_LB1_Not_ContIn, M4_CalP0_LP0_CL1_LB1_line1); and2 M4_CalP0_LP0_CL1_LB1_Mux2_2(in248, in273, M4_CalP0_LP0_CL1_LB1_line2); or2 M4_CalP0_LP0_CL1_LB1_Mux2_3(M4_CalP0_LP0_CL1_LB1_line1, M4_CalP0_LP0_CL1_LB1_line2, M4_CalP0_LP0_CL1_line1); or2 M4_CalP0_LP0_CL1_LB2(in411, M4_CalP0_LP0_CL1_line0, M4_CalP0_LP0_CL1_line2); nand2 M4_CalP0_LP0_CL1_LB3(in411, M4_CalP0_LP0_CL1_line1, M4_CalP0_LP0_CL1_line3); and2 M4_CalP0_LP0_CL1_LB4(M4_CalP0_LP0_CL1_line2, M4_CalP0_LP0_CL1_line3, M4_CalP0_LogicOut_1); inv M4_CalP0_LP0_CL2_LB0_Mux2_0(in265, M4_CalP0_LP0_CL2_LB0_Not_ContIn); and2 M4_CalP0_LP0_CL2_LB0_Mux2_1(in254, M4_CalP0_LP0_CL2_LB0_Not_ContIn, M4_CalP0_LP0_CL2_LB0_line1); and2 M4_CalP0_LP0_CL2_LB0_Mux2_2(in242, in265, M4_CalP0_LP0_CL2_LB0_line2); or2 M4_CalP0_LP0_CL2_LB0_Mux2_3(M4_CalP0_LP0_CL2_LB0_line1, M4_CalP0_LP0_CL2_LB0_line2, M4_CalP0_LP0_CL2_line0); inv M4_CalP0_LP0_CL2_LB1_Mux2_0(in265, M4_CalP0_LP0_CL2_LB1_Not_ContIn); and2 M4_CalP0_LP0_CL2_LB1_Mux2_1(in251, M4_CalP0_LP0_CL2_LB1_Not_ContIn, M4_CalP0_LP0_CL2_LB1_line1); and2 M4_CalP0_LP0_CL2_LB1_Mux2_2(in248, in265, M4_CalP0_LP0_CL2_LB1_line2); or2 M4_CalP0_LP0_CL2_LB1_Mux2_3(M4_CalP0_LP0_CL2_LB1_line1, M4_CalP0_LP0_CL2_LB1_line2, M4_CalP0_LP0_CL2_line1); or2 M4_CalP0_LP0_CL2_LB2(in400, M4_CalP0_LP0_CL2_line0, M4_CalP0_LP0_CL2_line2); nand2 M4_CalP0_LP0_CL2_LB3(in400, M4_CalP0_LP0_CL2_line1, M4_CalP0_LP0_CL2_line3); and2 M4_CalP0_LP0_CL2_LB4(M4_CalP0_LP0_CL2_line2, M4_CalP0_LP0_CL2_line3, M4_CalP0_LogicOut_2); inv M4_CalP0_LP0_CL3_LB0_Mux2_0(in257, M4_CalP0_LP0_CL3_LB0_Not_ContIn); and2 M4_CalP0_LP0_CL3_LB0_Mux2_1(in254, M4_CalP0_LP0_CL3_LB0_Not_ContIn, M4_CalP0_LP0_CL3_LB0_line1); and2 M4_CalP0_LP0_CL3_LB0_Mux2_2(in242, in257, M4_CalP0_LP0_CL3_LB0_line2); or2 M4_CalP0_LP0_CL3_LB0_Mux2_3(M4_CalP0_LP0_CL3_LB0_line1, M4_CalP0_LP0_CL3_LB0_line2, M4_CalP0_LP0_CL3_line0); inv M4_CalP0_LP0_CL3_LB1_Mux2_0(in257, M4_CalP0_LP0_CL3_LB1_Not_ContIn); and2 M4_CalP0_LP0_CL3_LB1_Mux2_1(in251, M4_CalP0_LP0_CL3_LB1_Not_ContIn, M4_CalP0_LP0_CL3_LB1_line1); and2 M4_CalP0_LP0_CL3_LB1_Mux2_2(in248, in257, M4_CalP0_LP0_CL3_LB1_line2); or2 M4_CalP0_LP0_CL3_LB1_Mux2_3(M4_CalP0_LP0_CL3_LB1_line1, M4_CalP0_LP0_CL3_LB1_line2, M4_CalP0_LP0_CL3_line1); or2 M4_CalP0_LP0_CL3_LB2(in389, M4_CalP0_LP0_CL3_line0, M4_CalP0_LP0_CL3_line2); nand2 M4_CalP0_LP0_CL3_LB3(in389, M4_CalP0_LP0_CL3_line1, M4_CalP0_LP0_CL3_line3); and2 M4_CalP0_LP0_CL3_LB4(M4_CalP0_LP0_CL3_line2, M4_CalP0_LP0_CL3_line3, M4_CalP0_LogicOut_3); inv M4_CalP0_LP0_CL4_LB0_Mux2_0(in234, M4_CalP0_LP0_CL4_LB0_Not_ContIn); and2 M4_CalP0_LP0_CL4_LB0_Mux2_1(in254, M4_CalP0_LP0_CL4_LB0_Not_ContIn, M4_CalP0_LP0_CL4_LB0_line1); and2 M4_CalP0_LP0_CL4_LB0_Mux2_2(in242, in234, M4_CalP0_LP0_CL4_LB0_line2); or2 M4_CalP0_LP0_CL4_LB0_Mux2_3(M4_CalP0_LP0_CL4_LB0_line1, M4_CalP0_LP0_CL4_LB0_line2, M4_CalP0_LP0_CL4_line0); inv M4_CalP0_LP0_CL4_LB1_Mux2_0(in234, M4_CalP0_LP0_CL4_LB1_Not_ContIn); and2 M4_CalP0_LP0_CL4_LB1_Mux2_1(in251, M4_CalP0_LP0_CL4_LB1_Not_ContIn, M4_CalP0_LP0_CL4_LB1_line1); and2 M4_CalP0_LP0_CL4_LB1_Mux2_2(in248, in234, M4_CalP0_LP0_CL4_LB1_line2); or2 M4_CalP0_LP0_CL4_LB1_Mux2_3(M4_CalP0_LP0_CL4_LB1_line1, M4_CalP0_LP0_CL4_LB1_line2, M4_CalP0_LP0_CL4_line1); or2 M4_CalP0_LP0_CL4_LB2(in435, M4_CalP0_LP0_CL4_line0, M4_CalP0_LP0_CL4_line2); nand2 M4_CalP0_LP0_CL4_LB3(in435, M4_CalP0_LP0_CL4_line1, M4_CalP0_LP0_CL4_line3); and2 M4_CalP0_LP0_CL4_LB4(M4_CalP0_LP0_CL4_line2, M4_CalP0_LP0_CL4_line3, M4_CalP0_LogicOut_4); inv M4_CalP0_LP0_CL5_LB0_Mux2_0(in226, M4_CalP0_LP0_CL5_LB0_Not_ContIn); and2 M4_CalP0_LP0_CL5_LB0_Mux2_1(in254, M4_CalP0_LP0_CL5_LB0_Not_ContIn, M4_CalP0_LP0_CL5_LB0_line1); and2 M4_CalP0_LP0_CL5_LB0_Mux2_2(in242, in226, M4_CalP0_LP0_CL5_LB0_line2); or2 M4_CalP0_LP0_CL5_LB0_Mux2_3(M4_CalP0_LP0_CL5_LB0_line1, M4_CalP0_LP0_CL5_LB0_line2, M4_CalP0_LP0_CL5_line0); inv M4_CalP0_LP0_CL5_LB1_Mux2_0(in226, M4_CalP0_LP0_CL5_LB1_Not_ContIn); and2 M4_CalP0_LP0_CL5_LB1_Mux2_1(in251, M4_CalP0_LP0_CL5_LB1_Not_ContIn, M4_CalP0_LP0_CL5_LB1_line1); and2 M4_CalP0_LP0_CL5_LB1_Mux2_2(in248, in226, M4_CalP0_LP0_CL5_LB1_line2); or2 M4_CalP0_LP0_CL5_LB1_Mux2_3(M4_CalP0_LP0_CL5_LB1_line1, M4_CalP0_LP0_CL5_LB1_line2, M4_CalP0_LP0_CL5_line1); or2 M4_CalP0_LP0_CL5_LB2(in422, M4_CalP0_LP0_CL5_line0, M4_CalP0_LP0_CL5_line2); nand2 M4_CalP0_LP0_CL5_LB3(in422, M4_CalP0_LP0_CL5_line1, M4_CalP0_LP0_CL5_line3); and2 M4_CalP0_LP0_CL5_LB4(M4_CalP0_LP0_CL5_line2, M4_CalP0_LP0_CL5_line3, M4_CalP0_LogicOut_5); inv M4_CalP0_LP0_CL6_LB0_Mux2_0(in218, M4_CalP0_LP0_CL6_LB0_Not_ContIn); and2 M4_CalP0_LP0_CL6_LB0_Mux2_1(in254, M4_CalP0_LP0_CL6_LB0_Not_ContIn, M4_CalP0_LP0_CL6_LB0_line1); and2 M4_CalP0_LP0_CL6_LB0_Mux2_2(in242, in218, M4_CalP0_LP0_CL6_LB0_line2); or2 M4_CalP0_LP0_CL6_LB0_Mux2_3(M4_CalP0_LP0_CL6_LB0_line1, M4_CalP0_LP0_CL6_LB0_line2, M4_CalP0_LP0_CL6_line0); inv M4_CalP0_LP0_CL6_LB1_Mux2_0(in218, M4_CalP0_LP0_CL6_LB1_Not_ContIn); and2 M4_CalP0_LP0_CL6_LB1_Mux2_1(in251, M4_CalP0_LP0_CL6_LB1_Not_ContIn, M4_CalP0_LP0_CL6_LB1_line1); and2 M4_CalP0_LP0_CL6_LB1_Mux2_2(in248, in218, M4_CalP0_LP0_CL6_LB1_line2); or2 M4_CalP0_LP0_CL6_LB1_Mux2_3(M4_CalP0_LP0_CL6_LB1_line1, M4_CalP0_LP0_CL6_LB1_line2, M4_CalP0_LP0_CL6_line1); or2 M4_CalP0_LP0_CL6_LB2(in468, M4_CalP0_LP0_CL6_line0, M4_CalP0_LP0_CL6_line2); nand2 M4_CalP0_LP0_CL6_LB3(in468, M4_CalP0_LP0_CL6_line1, M4_CalP0_LP0_CL6_line3); and2 M4_CalP0_LP0_CL6_LB4(M4_CalP0_LP0_CL6_line2, M4_CalP0_LP0_CL6_line3, M4_CalP0_LogicOut_6); inv M4_CalP0_LP0_CL7_LB0_Mux2_0(in210, M4_CalP0_LP0_CL7_LB0_Not_ContIn); and2 M4_CalP0_LP0_CL7_LB0_Mux2_1(in254, M4_CalP0_LP0_CL7_LB0_Not_ContIn, M4_CalP0_LP0_CL7_LB0_line1); and2 M4_CalP0_LP0_CL7_LB0_Mux2_2(in242, in210, M4_CalP0_LP0_CL7_LB0_line2); or2 M4_CalP0_LP0_CL7_LB0_Mux2_3(M4_CalP0_LP0_CL7_LB0_line1, M4_CalP0_LP0_CL7_LB0_line2, M4_CalP0_LP0_CL7_line0); inv M4_CalP0_LP0_CL7_LB1_Mux2_0(in210, M4_CalP0_LP0_CL7_LB1_Not_ContIn); and2 M4_CalP0_LP0_CL7_LB1_Mux2_1(in251, M4_CalP0_LP0_CL7_LB1_Not_ContIn, M4_CalP0_LP0_CL7_LB1_line1); and2 M4_CalP0_LP0_CL7_LB1_Mux2_2(in248, in210, M4_CalP0_LP0_CL7_LB1_line2); or2 M4_CalP0_LP0_CL7_LB1_Mux2_3(M4_CalP0_LP0_CL7_LB1_line1, M4_CalP0_LP0_CL7_LB1_line2, M4_CalP0_LP0_CL7_line1); or2 M4_CalP0_LP0_CL7_LB2(in457, M4_CalP0_LP0_CL7_line0, M4_CalP0_LP0_CL7_line2); nand2 M4_CalP0_LP0_CL7_LB3(in457, M4_CalP0_LP0_CL7_line1, M4_CalP0_LP0_CL7_line3); and2 M4_CalP0_LP0_CL7_LB4(M4_CalP0_LP0_CL7_line2, M4_CalP0_LP0_CL7_line3, M4_CalP0_LogicOut_7); inv M4_CalP0_LP0_CL8_LB0_Mux2_0(in206, M4_CalP0_LP0_CL8_LB0_Not_ContIn); and2 M4_CalP0_LP0_CL8_LB0_Mux2_1(in254, M4_CalP0_LP0_CL8_LB0_Not_ContIn, M4_CalP0_LP0_CL8_LB0_line1); and2 M4_CalP0_LP0_CL8_LB0_Mux2_2(in242, in206, M4_CalP0_LP0_CL8_LB0_line2); or2 M4_CalP0_LP0_CL8_LB0_Mux2_3(M4_CalP0_LP0_CL8_LB0_line1, M4_CalP0_LP0_CL8_LB0_line2, M4_CalP0_LP0_CL8_line0); inv M4_CalP0_LP0_CL8_LB1_Mux2_0(in206, M4_CalP0_LP0_CL8_LB1_Not_ContIn); and2 M4_CalP0_LP0_CL8_LB1_Mux2_1(in251, M4_CalP0_LP0_CL8_LB1_Not_ContIn, M4_CalP0_LP0_CL8_LB1_line1); and2 M4_CalP0_LP0_CL8_LB1_Mux2_2(in248, in206, M4_CalP0_LP0_CL8_LB1_line2); or2 M4_CalP0_LP0_CL8_LB1_Mux2_3(M4_CalP0_LP0_CL8_LB1_line1, M4_CalP0_LP0_CL8_LB1_line2, M4_CalP0_LP0_CL8_line1); or2 M4_CalP0_LP0_CL8_LB2(in446, M4_CalP0_LP0_CL8_line0, M4_CalP0_LP0_CL8_line2); nand2 M4_CalP0_LP0_CL8_LB3(in446, M4_CalP0_LP0_CL8_line1, M4_CalP0_LP0_CL8_line3); and2 M4_CalP0_LP0_CL8_LB4(M4_CalP0_LP0_CL8_line2, M4_CalP0_LP0_CL8_line3, M4_CalP0_LogicOut_8); inv M4_CalP0_LP1_PT1_Xo0(M4_CalP0_LogicOut_5, M4_CalP0_LP1_PT1_NotA); inv M4_CalP0_LP1_PT1_Xo1(M4_CalP0_LogicOut_6, M4_CalP0_LP1_PT1_NotB); nand2 M4_CalP0_LP1_PT1_Xo2(M4_CalP0_LP1_PT1_NotA, M4_CalP0_LogicOut_6, M4_CalP0_LP1_PT1_line2); nand2 M4_CalP0_LP1_PT1_Xo3(M4_CalP0_LP1_PT1_NotB, M4_CalP0_LogicOut_5, M4_CalP0_LP1_PT1_line3); nand2 M4_CalP0_LP1_PT1_Xo4(M4_CalP0_LP1_PT1_line2, M4_CalP0_LP1_PT1_line3, M4_CalP0_LP1_line1); inv M4_CalP0_LP1_PT2_Xo0(M4_CalP0_LogicOut_7, M4_CalP0_LP1_PT2_NotA); inv M4_CalP0_LP1_PT2_Xo1(M4_CalP0_LogicOut_8, M4_CalP0_LP1_PT2_NotB); nand2 M4_CalP0_LP1_PT2_Xo2(M4_CalP0_LP1_PT2_NotA, M4_CalP0_LogicOut_8, M4_CalP0_LP1_PT2_line2); nand2 M4_CalP0_LP1_PT2_Xo3(M4_CalP0_LP1_PT2_NotB, M4_CalP0_LogicOut_7, M4_CalP0_LP1_PT2_line3); nand2 M4_CalP0_LP1_PT2_Xo4(M4_CalP0_LP1_PT2_line2, M4_CalP0_LP1_PT2_line3, M4_CalP0_LP1_line2); inv M4_CalP0_LP1_PT3_Xo0(M4_CalP0_LogicOut_1, M4_CalP0_LP1_PT3_NotA); inv M4_CalP0_LP1_PT3_Xo1(M4_CalP0_LogicOut_2, M4_CalP0_LP1_PT3_NotB); nand2 M4_CalP0_LP1_PT3_Xo2(M4_CalP0_LP1_PT3_NotA, M4_CalP0_LogicOut_2, M4_CalP0_LP1_PT3_line2); nand2 M4_CalP0_LP1_PT3_Xo3(M4_CalP0_LP1_PT3_NotB, M4_CalP0_LogicOut_1, M4_CalP0_LP1_PT3_line3); nand2 M4_CalP0_LP1_PT3_Xo4(M4_CalP0_LP1_PT3_line2, M4_CalP0_LP1_PT3_line3, M4_CalP0_LP1_line3); inv M4_CalP0_LP1_PT4_Xo0(M4_CalP0_LogicOut_3, M4_CalP0_LP1_PT4_NotA); inv M4_CalP0_LP1_PT4_Xo1(M4_CalP0_LogicOut_4, M4_CalP0_LP1_PT4_NotB); nand2 M4_CalP0_LP1_PT4_Xo2(M4_CalP0_LP1_PT4_NotA, M4_CalP0_LogicOut_4, M4_CalP0_LP1_PT4_line2); nand2 M4_CalP0_LP1_PT4_Xo3(M4_CalP0_LP1_PT4_NotB, M4_CalP0_LogicOut_3, M4_CalP0_LP1_PT4_line3); nand2 M4_CalP0_LP1_PT4_Xo4(M4_CalP0_LP1_PT4_line2, M4_CalP0_LP1_PT4_line3, M4_CalP0_LP1_line4); inv M4_CalP0_LP1_PT5_Xo0(M4_CalP0_LP1_line1, M4_CalP0_LP1_PT5_NotA); inv M4_CalP0_LP1_PT5_Xo1(M4_CalP0_LP1_line2, M4_CalP0_LP1_PT5_NotB); nand2 M4_CalP0_LP1_PT5_Xo2(M4_CalP0_LP1_PT5_NotA, M4_CalP0_LP1_line2, M4_CalP0_LP1_PT5_line2); nand2 M4_CalP0_LP1_PT5_Xo3(M4_CalP0_LP1_PT5_NotB, M4_CalP0_LP1_line1, M4_CalP0_LP1_PT5_line3); nand2 M4_CalP0_LP1_PT5_Xo4(M4_CalP0_LP1_PT5_line2, M4_CalP0_LP1_PT5_line3, M4_CalP0_LP1_line5); inv M4_CalP0_LP1_PT6_Xo3_0(M4_CalP0_LP1_line3, M4_CalP0_LP1_PT6_NotA); inv M4_CalP0_LP1_PT6_Xo3_1(M4_CalP0_LogicOut_0, M4_CalP0_LP1_PT6_NotB); inv M4_CalP0_LP1_PT6_Xo3_2(M4_CalP0_LP1_line4, M4_CalP0_LP1_PT6_NotC); and3 M4_CalP0_LP1_PT6_Xo3_3(M4_CalP0_LP1_PT6_NotA, M4_CalP0_LP1_PT6_NotB, M4_CalP0_LP1_line4, M4_CalP0_LP1_PT6_line3); and3 M4_CalP0_LP1_PT6_Xo3_4(M4_CalP0_LP1_PT6_NotA, M4_CalP0_LogicOut_0, M4_CalP0_LP1_PT6_NotC, M4_CalP0_LP1_PT6_line4); and3 M4_CalP0_LP1_PT6_Xo3_5(M4_CalP0_LP1_line3, M4_CalP0_LP1_PT6_NotB, M4_CalP0_LP1_PT6_NotC, M4_CalP0_LP1_PT6_line5); and3 M4_CalP0_LP1_PT6_Xo3_6(M4_CalP0_LP1_line3, M4_CalP0_LogicOut_0, M4_CalP0_LP1_line4, M4_CalP0_LP1_PT6_line6); nor2 M4_CalP0_LP1_PT6_Xo3_7(M4_CalP0_LP1_PT6_line3, M4_CalP0_LP1_PT6_line4, M4_CalP0_LP1_PT6_line7); nor2 M4_CalP0_LP1_PT6_Xo3_8(M4_CalP0_LP1_PT6_line5, M4_CalP0_LP1_PT6_line6, M4_CalP0_LP1_PT6_line8); nand2 M4_CalP0_LP1_PT6_Xo3_9(M4_CalP0_LP1_PT6_line7, M4_CalP0_LP1_PT6_line8, M4_CalP0_LP1_line6); inv M4_CalP0_LP1_PT7_Xo0(M4_CalP0_LP1_line5, M4_CalP0_LP1_PT7_NotA); inv M4_CalP0_LP1_PT7_Xo1(M4_CalP0_LP1_line6, M4_CalP0_LP1_PT7_NotB); nand2 M4_CalP0_LP1_PT7_Xo2(M4_CalP0_LP1_PT7_NotA, M4_CalP0_LP1_line6, M4_CalP0_LP1_PT7_line2); nand2 M4_CalP0_LP1_PT7_Xo3(M4_CalP0_LP1_PT7_NotB, M4_CalP0_LP1_line5, M4_CalP0_LP1_PT7_line3); nand2 M4_CalP0_LP1_PT7_Xo4(M4_CalP0_LP1_PT7_line2, M4_CalP0_LP1_PT7_line3, M4_LogicPar); and2 M4_CalP1_SP0_GP9_0(Ybus_0, in374, M4_CalP1_Genbus_0); and2 M4_CalP1_SP0_GP9_1(Ybus_1, in411, M4_CalP1_Genbus_1); and2 M4_CalP1_SP0_GP9_2(Ybus_2, in400, M4_CalP1_Genbus_2); and2 M4_CalP1_SP0_GP9_3(Ybus_3, in389, M4_CalP1_Genbus_3); and2 M4_CalP1_SP0_GP9_4(Ybus_4, in435, M4_CalP1_Genbus_4); and2 M4_CalP1_SP0_GP9_5(Ybus_5, in422, M4_CalP1_Genbus_5); and2 M4_CalP1_SP0_GP9_6(Ybus_6, in468, M4_CalP1_Genbus_6); and2 M4_CalP1_SP0_GP9_7(Ybus_7, in457, M4_CalP1_Genbus_7); and2 M4_CalP1_SP0_GP9_8(Ybus_8, in446, M4_CalP1_Genbus_8); inv M4_CalP1_SP0_GP9_9_Xo0(Ybus_0, M4_CalP1_SP0_GP9_9_NotA); inv M4_CalP1_SP0_GP9_9_Xo1(in374, M4_CalP1_SP0_GP9_9_NotB); nand2 M4_CalP1_SP0_GP9_9_Xo2(M4_CalP1_SP0_GP9_9_NotA, in374, M4_CalP1_SP0_GP9_9_line2); nand2 M4_CalP1_SP0_GP9_9_Xo3(M4_CalP1_SP0_GP9_9_NotB, Ybus_0, M4_CalP1_SP0_GP9_9_line3); nand2 M4_CalP1_SP0_GP9_9_Xo4(M4_CalP1_SP0_GP9_9_line2, M4_CalP1_SP0_GP9_9_line3, M4_CalP1_Propbus_0); inv M4_CalP1_SP0_GP9_10_Xo0(Ybus_1, M4_CalP1_SP0_GP9_10_NotA); inv M4_CalP1_SP0_GP9_10_Xo1(in411, M4_CalP1_SP0_GP9_10_NotB); nand2 M4_CalP1_SP0_GP9_10_Xo2(M4_CalP1_SP0_GP9_10_NotA, in411, M4_CalP1_SP0_GP9_10_line2); nand2 M4_CalP1_SP0_GP9_10_Xo3(M4_CalP1_SP0_GP9_10_NotB, Ybus_1, M4_CalP1_SP0_GP9_10_line3); nand2 M4_CalP1_SP0_GP9_10_Xo4(M4_CalP1_SP0_GP9_10_line2, M4_CalP1_SP0_GP9_10_line3, M4_CalP1_Propbus_1); inv M4_CalP1_SP0_GP9_11_Xo0(Ybus_2, M4_CalP1_SP0_GP9_11_NotA); inv M4_CalP1_SP0_GP9_11_Xo1(in400, M4_CalP1_SP0_GP9_11_NotB); nand2 M4_CalP1_SP0_GP9_11_Xo2(M4_CalP1_SP0_GP9_11_NotA, in400, M4_CalP1_SP0_GP9_11_line2); nand2 M4_CalP1_SP0_GP9_11_Xo3(M4_CalP1_SP0_GP9_11_NotB, Ybus_2, M4_CalP1_SP0_GP9_11_line3); nand2 M4_CalP1_SP0_GP9_11_Xo4(M4_CalP1_SP0_GP9_11_line2, M4_CalP1_SP0_GP9_11_line3, M4_CalP1_Propbus_2); inv M4_CalP1_SP0_GP9_12_Xo0(Ybus_3, M4_CalP1_SP0_GP9_12_NotA); inv M4_CalP1_SP0_GP9_12_Xo1(in389, M4_CalP1_SP0_GP9_12_NotB); nand2 M4_CalP1_SP0_GP9_12_Xo2(M4_CalP1_SP0_GP9_12_NotA, in389, M4_CalP1_SP0_GP9_12_line2); nand2 M4_CalP1_SP0_GP9_12_Xo3(M4_CalP1_SP0_GP9_12_NotB, Ybus_3, M4_CalP1_SP0_GP9_12_line3); nand2 M4_CalP1_SP0_GP9_12_Xo4(M4_CalP1_SP0_GP9_12_line2, M4_CalP1_SP0_GP9_12_line3, M4_CalP1_Propbus_3); inv M4_CalP1_SP0_GP9_13_Xo0(Ybus_4, M4_CalP1_SP0_GP9_13_NotA); inv M4_CalP1_SP0_GP9_13_Xo1(in435, M4_CalP1_SP0_GP9_13_NotB); nand2 M4_CalP1_SP0_GP9_13_Xo2(M4_CalP1_SP0_GP9_13_NotA, in435, M4_CalP1_SP0_GP9_13_line2); nand2 M4_CalP1_SP0_GP9_13_Xo3(M4_CalP1_SP0_GP9_13_NotB, Ybus_4, M4_CalP1_SP0_GP9_13_line3); nand2 M4_CalP1_SP0_GP9_13_Xo4(M4_CalP1_SP0_GP9_13_line2, M4_CalP1_SP0_GP9_13_line3, M4_CalP1_Propbus_4); inv M4_CalP1_SP0_GP9_14_Xo0(Ybus_5, M4_CalP1_SP0_GP9_14_NotA); inv M4_CalP1_SP0_GP9_14_Xo1(in422, M4_CalP1_SP0_GP9_14_NotB); nand2 M4_CalP1_SP0_GP9_14_Xo2(M4_CalP1_SP0_GP9_14_NotA, in422, M4_CalP1_SP0_GP9_14_line2); nand2 M4_CalP1_SP0_GP9_14_Xo3(M4_CalP1_SP0_GP9_14_NotB, Ybus_5, M4_CalP1_SP0_GP9_14_line3); nand2 M4_CalP1_SP0_GP9_14_Xo4(M4_CalP1_SP0_GP9_14_line2, M4_CalP1_SP0_GP9_14_line3, M4_CalP1_Propbus_5); inv M4_CalP1_SP0_GP9_15_Xo0(Ybus_6, M4_CalP1_SP0_GP9_15_NotA); inv M4_CalP1_SP0_GP9_15_Xo1(in468, M4_CalP1_SP0_GP9_15_NotB); nand2 M4_CalP1_SP0_GP9_15_Xo2(M4_CalP1_SP0_GP9_15_NotA, in468, M4_CalP1_SP0_GP9_15_line2); nand2 M4_CalP1_SP0_GP9_15_Xo3(M4_CalP1_SP0_GP9_15_NotB, Ybus_6, M4_CalP1_SP0_GP9_15_line3); nand2 M4_CalP1_SP0_GP9_15_Xo4(M4_CalP1_SP0_GP9_15_line2, M4_CalP1_SP0_GP9_15_line3, M4_CalP1_Propbus_6); inv M4_CalP1_SP0_GP9_16_Xo0(Ybus_7, M4_CalP1_SP0_GP9_16_NotA); inv M4_CalP1_SP0_GP9_16_Xo1(in457, M4_CalP1_SP0_GP9_16_NotB); nand2 M4_CalP1_SP0_GP9_16_Xo2(M4_CalP1_SP0_GP9_16_NotA, in457, M4_CalP1_SP0_GP9_16_line2); nand2 M4_CalP1_SP0_GP9_16_Xo3(M4_CalP1_SP0_GP9_16_NotB, Ybus_7, M4_CalP1_SP0_GP9_16_line3); nand2 M4_CalP1_SP0_GP9_16_Xo4(M4_CalP1_SP0_GP9_16_line2, M4_CalP1_SP0_GP9_16_line3, M4_CalP1_Propbus_7); inv M4_CalP1_SP0_GP9_17_Xo0(Ybus_8, M4_CalP1_SP0_GP9_17_NotA); inv M4_CalP1_SP0_GP9_17_Xo1(in446, M4_CalP1_SP0_GP9_17_NotB); nand2 M4_CalP1_SP0_GP9_17_Xo2(M4_CalP1_SP0_GP9_17_NotA, in446, M4_CalP1_SP0_GP9_17_line2); nand2 M4_CalP1_SP0_GP9_17_Xo3(M4_CalP1_SP0_GP9_17_NotB, Ybus_8, M4_CalP1_SP0_GP9_17_line3); nand2 M4_CalP1_SP0_GP9_17_Xo4(M4_CalP1_SP0_GP9_17_line2, M4_CalP1_SP0_GP9_17_line3, M4_CalP1_Propbus_8); or2 M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_0(M4_CalP1_Genbus_0, M4_CalP1_Propbus_0, M4_CalP1_LocalC1_0); and2 M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_1_Ao2_0(M4_CalP1_Propbus_1, M4_CalP1_Genbus_0, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_1_line0); or2 M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_1_Ao2_1(M4_CalP1_Genbus_1, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_1_line0, M4_CalP1_LocalC0_1); and2 M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_Ao3a_0(M4_CalP1_Propbus_1, M4_CalP1_Genbus_0, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_line0); and2 M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_Ao3a_1(M4_CalP1_Propbus_1, M4_CalP1_Propbus_0, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_line1); or3 M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_Ao3a_2(M4_CalP1_Genbus_1, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_line0, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_2_line1, M4_CalP1_LocalC1_1); and2 M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_Ao3a_0(M4_CalP1_Propbus_2, M4_CalP1_Genbus_1, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_line0); and3 M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_Ao3a_1(M4_CalP1_Propbus_2, M4_CalP1_Propbus_1, M4_CalP1_Genbus_0, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_line1); or3 M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_Ao3a_2(M4_CalP1_Genbus_2, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_line0, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_3_line1, M4_CalP1_LocalC0_2); and2 M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_Ao4a_0(M4_CalP1_Propbus_2, M4_CalP1_Genbus_1, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_line0); and3 M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_Ao4a_1(M4_CalP1_Propbus_2, M4_CalP1_Propbus_1, M4_CalP1_Genbus_0, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_line1); and3 M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_Ao4a_2(M4_CalP1_Propbus_2, M4_CalP1_Propbus_1, M4_CalP1_Propbus_0, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_line2); or4 M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_Ao4a_3(M4_CalP1_Genbus_2, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_line0, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_line1, M4_CalP1_SP1_GLC5_0_GLC4_0_GLC4_4_line2, M4_CalP1_LocalC1_2); and2 M4_CalP1_SP1_GLC5_0_GLC4_1_Ao4a_0(M4_CalP1_Propbus_3, M4_CalP1_Genbus_2, M4_CalP1_SP1_GLC5_0_GLC4_1_line0); and3 M4_CalP1_SP1_GLC5_0_GLC4_1_Ao4a_1(M4_CalP1_Propbus_3, M4_CalP1_Propbus_2, M4_CalP1_Genbus_1, M4_CalP1_SP1_GLC5_0_GLC4_1_line1); and4 M4_CalP1_SP1_GLC5_0_GLC4_1_Ao4a_2(M4_CalP1_Propbus_3, M4_CalP1_Propbus_2, M4_CalP1_Propbus_1, M4_CalP1_Genbus_0, M4_CalP1_SP1_GLC5_0_GLC4_1_line2); or4 M4_CalP1_SP1_GLC5_0_GLC4_1_Ao4a_3(M4_CalP1_Genbus_3, M4_CalP1_SP1_GLC5_0_GLC4_1_line0, M4_CalP1_SP1_GLC5_0_GLC4_1_line1, M4_CalP1_SP1_GLC5_0_GLC4_1_line2, M4_CalP1_LocalC0_3); and2 M4_CalP1_SP1_GLC5_0_GLC4_2_Ao5a_0(M4_CalP1_Propbus_3, M4_CalP1_Genbus_2, M4_CalP1_SP1_GLC5_0_GLC4_2_line0); and3 M4_CalP1_SP1_GLC5_0_GLC4_2_Ao5a_1(M4_CalP1_Propbus_3, M4_CalP1_Propbus_2, M4_CalP1_Genbus_1, M4_CalP1_SP1_GLC5_0_GLC4_2_line1); and4 M4_CalP1_SP1_GLC5_0_GLC4_2_Ao5a_2(M4_CalP1_Propbus_3, M4_CalP1_Propbus_2, M4_CalP1_Propbus_1, M4_CalP1_Genbus_0, M4_CalP1_SP1_GLC5_0_GLC4_2_line2); and4 M4_CalP1_SP1_GLC5_0_GLC4_2_Ao5a_3(M4_CalP1_Propbus_3, M4_CalP1_Propbus_2, M4_CalP1_Propbus_1, M4_CalP1_Propbus_0, M4_CalP1_SP1_GLC5_0_GLC4_2_line3); or5 M4_CalP1_SP1_GLC5_0_GLC4_2_Ao5a_4(M4_CalP1_Genbus_3, M4_CalP1_SP1_GLC5_0_GLC4_2_line0, M4_CalP1_SP1_GLC5_0_GLC4_2_line1, M4_CalP1_SP1_GLC5_0_GLC4_2_line2, M4_CalP1_SP1_GLC5_0_GLC4_2_line3, M4_CalP1_LocalC1_3); and2 M4_CalP1_SP1_GLC5_1_Ao5a_0(M4_CalP1_Propbus_4, M4_CalP1_Genbus_3, M4_CalP1_SP1_GLC5_1_line0); and3 M4_CalP1_SP1_GLC5_1_Ao5a_1(M4_CalP1_Propbus_4, M4_CalP1_Propbus_3, M4_CalP1_Genbus_2, M4_CalP1_SP1_GLC5_1_line1); and4 M4_CalP1_SP1_GLC5_1_Ao5a_2(M4_CalP1_Propbus_4, M4_CalP1_Propbus_3, M4_CalP1_Propbus_2, M4_CalP1_Genbus_1, M4_CalP1_SP1_GLC5_1_line2); and5 M4_CalP1_SP1_GLC5_1_Ao5a_3(M4_CalP1_Propbus_4, M4_CalP1_Propbus_3, M4_CalP1_Propbus_2, M4_CalP1_Propbus_1, M4_CalP1_Genbus_0, M4_CalP1_SP1_GLC5_1_line3); or5 M4_CalP1_SP1_GLC5_1_Ao5a_4(M4_CalP1_Genbus_4, M4_CalP1_SP1_GLC5_1_line0, M4_CalP1_SP1_GLC5_1_line1, M4_CalP1_SP1_GLC5_1_line2, M4_CalP1_SP1_GLC5_1_line3, M4_CalP1_LocalC0_4); and2 M4_CalP1_SP1_GLC5_2_Ao6a_0(M4_CalP1_Propbus_4, M4_CalP1_Genbus_3, M4_CalP1_SP1_GLC5_2_line0); and3 M4_CalP1_SP1_GLC5_2_Ao6a_1(M4_CalP1_Propbus_4, M4_CalP1_Propbus_3, M4_CalP1_Genbus_2, M4_CalP1_SP1_GLC5_2_line1); and4 M4_CalP1_SP1_GLC5_2_Ao6a_2(M4_CalP1_Propbus_4, M4_CalP1_Propbus_3, M4_CalP1_Propbus_2, M4_CalP1_Genbus_1, M4_CalP1_SP1_GLC5_2_line2); and5 M4_CalP1_SP1_GLC5_2_Ao6a_3(M4_CalP1_Propbus_4, M4_CalP1_Propbus_3, M4_CalP1_Propbus_2, M4_CalP1_Propbus_1, M4_CalP1_Genbus_0, M4_CalP1_SP1_GLC5_2_line3); and5 M4_CalP1_SP1_GLC5_2_Ao6a_4(M4_CalP1_Propbus_4, M4_CalP1_Propbus_3, M4_CalP1_Propbus_2, M4_CalP1_Propbus_1, M4_CalP1_Propbus_0, M4_CalP1_SP1_GLC5_2_line4); or6 M4_CalP1_SP1_GLC5_2_Ao6a_5(M4_CalP1_Genbus_4, M4_CalP1_SP1_GLC5_2_line0, M4_CalP1_SP1_GLC5_2_line1, M4_CalP1_SP1_GLC5_2_line2, M4_CalP1_SP1_GLC5_2_line3, M4_CalP1_SP1_GLC5_2_line4, M4_CalP1_LocalC1_4); or2 M4_CalP1_SP2_GLC4_0(M4_CalP1_Genbus_5, M4_CalP1_Propbus_5, M4_CalP1_LocalC1_5); and2 M4_CalP1_SP2_GLC4_1_Ao2_0(M4_CalP1_Propbus_6, M4_CalP1_Genbus_5, M4_CalP1_SP2_GLC4_1_line0); or2 M4_CalP1_SP2_GLC4_1_Ao2_1(M4_CalP1_Genbus_6, M4_CalP1_SP2_GLC4_1_line0, M4_CalP1_LocalC0_6); and2 M4_CalP1_SP2_GLC4_2_Ao3a_0(M4_CalP1_Propbus_6, M4_CalP1_Genbus_5, M4_CalP1_SP2_GLC4_2_line0); and2 M4_CalP1_SP2_GLC4_2_Ao3a_1(M4_CalP1_Propbus_6, M4_CalP1_Propbus_5, M4_CalP1_SP2_GLC4_2_line1); or3 M4_CalP1_SP2_GLC4_2_Ao3a_2(M4_CalP1_Genbus_6, M4_CalP1_SP2_GLC4_2_line0, M4_CalP1_SP2_GLC4_2_line1, M4_CalP1_LocalC1_6); and2 M4_CalP1_SP2_GLC4_3_Ao3a_0(M4_CalP1_Propbus_7, M4_CalP1_Genbus_6, M4_CalP1_SP2_GLC4_3_line0); and3 M4_CalP1_SP2_GLC4_3_Ao3a_1(M4_CalP1_Propbus_7, M4_CalP1_Propbus_6, M4_CalP1_Genbus_5, M4_CalP1_SP2_GLC4_3_line1); or3 M4_CalP1_SP2_GLC4_3_Ao3a_2(M4_CalP1_Genbus_7, M4_CalP1_SP2_GLC4_3_line0, M4_CalP1_SP2_GLC4_3_line1, M4_CalP1_LocalC0_7); and2 M4_CalP1_SP2_GLC4_4_Ao4a_0(M4_CalP1_Propbus_7, M4_CalP1_Genbus_6, M4_CalP1_SP2_GLC4_4_line0); and3 M4_CalP1_SP2_GLC4_4_Ao4a_1(M4_CalP1_Propbus_7, M4_CalP1_Propbus_6, M4_CalP1_Genbus_5, M4_CalP1_SP2_GLC4_4_line1); and3 M4_CalP1_SP2_GLC4_4_Ao4a_2(M4_CalP1_Propbus_7, M4_CalP1_Propbus_6, M4_CalP1_Propbus_5, M4_CalP1_SP2_GLC4_4_line2); or4 M4_CalP1_SP2_GLC4_4_Ao4a_3(M4_CalP1_Genbus_7, M4_CalP1_SP2_GLC4_4_line0, M4_CalP1_SP2_GLC4_4_line1, M4_CalP1_SP2_GLC4_4_line2, M4_CalP1_LocalC1_7); inv M4_CalP1_SP3_SP9nc0_SP7nc0_Xo0(M4_CalP1_Genbus_0, M4_CalP1_SP3_SP9nc0_SP7nc0_NotA); inv M4_CalP1_SP3_SP9nc0_SP7nc0_Xo1(M4_CalP1_LocalC0_1, M4_CalP1_SP3_SP9nc0_SP7nc0_NotB); nand2 M4_CalP1_SP3_SP9nc0_SP7nc0_Xo2(M4_CalP1_SP3_SP9nc0_SP7nc0_NotA, M4_CalP1_LocalC0_1, M4_CalP1_SP3_SP9nc0_SP7nc0_line2); nand2 M4_CalP1_SP3_SP9nc0_SP7nc0_Xo3(M4_CalP1_SP3_SP9nc0_SP7nc0_NotB, M4_CalP1_Genbus_0, M4_CalP1_SP3_SP9nc0_SP7nc0_line3); nand2 M4_CalP1_SP3_SP9nc0_SP7nc0_Xo4(M4_CalP1_SP3_SP9nc0_SP7nc0_line2, M4_CalP1_SP3_SP9nc0_SP7nc0_line3, M4_CalP1_SP3_SP9nc0_line0); inv M4_CalP1_SP3_SP9nc0_SP7nc1_Xo0(M4_CalP1_LocalC0_2, M4_CalP1_SP3_SP9nc0_SP7nc1_NotA); inv M4_CalP1_SP3_SP9nc0_SP7nc1_Xo1(M4_CalP1_SP3_SP9nc0_line0, M4_CalP1_SP3_SP9nc0_SP7nc1_NotB); nand2 M4_CalP1_SP3_SP9nc0_SP7nc1_Xo2(M4_CalP1_SP3_SP9nc0_SP7nc1_NotA, M4_CalP1_SP3_SP9nc0_line0, M4_CalP1_SP3_SP9nc0_SP7nc1_line2); nand2 M4_CalP1_SP3_SP9nc0_SP7nc1_Xo3(M4_CalP1_SP3_SP9nc0_SP7nc1_NotB, M4_CalP1_LocalC0_2, M4_CalP1_SP3_SP9nc0_SP7nc1_line3); nand2 M4_CalP1_SP3_SP9nc0_SP7nc1_Xo4(M4_CalP1_SP3_SP9nc0_SP7nc1_line2, M4_CalP1_SP3_SP9nc0_SP7nc1_line3, M4_CalP1_SP3_SP9nc0_line1); inv M4_CalP1_SP3_SP9nc0_SP7nc2_Xo0(M4_CalP1_LocalC0_3, M4_CalP1_SP3_SP9nc0_SP7nc2_NotA); inv M4_CalP1_SP3_SP9nc0_SP7nc2_Xo1(M4_CalP1_SP3_SP9nc0_line1, M4_CalP1_SP3_SP9nc0_SP7nc2_NotB); nand2 M4_CalP1_SP3_SP9nc0_SP7nc2_Xo2(M4_CalP1_SP3_SP9nc0_SP7nc2_NotA, M4_CalP1_SP3_SP9nc0_line1, M4_CalP1_SP3_SP9nc0_SP7nc2_line2); nand2 M4_CalP1_SP3_SP9nc0_SP7nc2_Xo3(M4_CalP1_SP3_SP9nc0_SP7nc2_NotB, M4_CalP1_LocalC0_3, M4_CalP1_SP3_SP9nc0_SP7nc2_line3); nand2 M4_CalP1_SP3_SP9nc0_SP7nc2_Xo4(M4_CalP1_SP3_SP9nc0_SP7nc2_line2, M4_CalP1_SP3_SP9nc0_SP7nc2_line3, M4_CalP1_SP3_SP9nc0_line2); inv M4_CalP1_SP3_SP9nc0_SP7nc3_Xo0(M4_CalP1_Propbus_0, M4_CalP1_SP3_SP9nc0_SP7nc3_NotA); inv M4_CalP1_SP3_SP9nc0_SP7nc3_Xo1(M4_CalP1_SP3_SP9nc0_line2, M4_CalP1_SP3_SP9nc0_SP7nc3_NotB); nand2 M4_CalP1_SP3_SP9nc0_SP7nc3_Xo2(M4_CalP1_SP3_SP9nc0_SP7nc3_NotA, M4_CalP1_SP3_SP9nc0_line2, M4_CalP1_SP3_SP9nc0_SP7nc3_line2); nand2 M4_CalP1_SP3_SP9nc0_SP7nc3_Xo3(M4_CalP1_SP3_SP9nc0_SP7nc3_NotB, M4_CalP1_Propbus_0, M4_CalP1_SP3_SP9nc0_SP7nc3_line3); nand2 M4_CalP1_SP3_SP9nc0_SP7nc3_Xo4(M4_CalP1_SP3_SP9nc0_SP7nc3_line2, M4_CalP1_SP3_SP9nc0_SP7nc3_line3, M4_CalP1_SP3_SP9nc0_line3); inv M4_CalP1_SP3_SP9nc0_SP7nc4_Xo0(M4_CalP1_Propbus_1, M4_CalP1_SP3_SP9nc0_SP7nc4_NotA); inv M4_CalP1_SP3_SP9nc0_SP7nc4_Xo1(M4_CalP1_SP3_SP9nc0_line3, M4_CalP1_SP3_SP9nc0_SP7nc4_NotB); nand2 M4_CalP1_SP3_SP9nc0_SP7nc4_Xo2(M4_CalP1_SP3_SP9nc0_SP7nc4_NotA, M4_CalP1_SP3_SP9nc0_line3, M4_CalP1_SP3_SP9nc0_SP7nc4_line2); nand2 M4_CalP1_SP3_SP9nc0_SP7nc4_Xo3(M4_CalP1_SP3_SP9nc0_SP7nc4_NotB, M4_CalP1_Propbus_1, M4_CalP1_SP3_SP9nc0_SP7nc4_line3); nand2 M4_CalP1_SP3_SP9nc0_SP7nc4_Xo4(M4_CalP1_SP3_SP9nc0_SP7nc4_line2, M4_CalP1_SP3_SP9nc0_SP7nc4_line3, M4_CalP1_SP3_SP9nc0_line4); inv M4_CalP1_SP3_SP9nc0_SP7nc5_Xo0(M4_CalP1_Propbus_2, M4_CalP1_SP3_SP9nc0_SP7nc5_NotA); inv M4_CalP1_SP3_SP9nc0_SP7nc5_Xo1(M4_CalP1_SP3_SP9nc0_line4, M4_CalP1_SP3_SP9nc0_SP7nc5_NotB); nand2 M4_CalP1_SP3_SP9nc0_SP7nc5_Xo2(M4_CalP1_SP3_SP9nc0_SP7nc5_NotA, M4_CalP1_SP3_SP9nc0_line4, M4_CalP1_SP3_SP9nc0_SP7nc5_line2); nand2 M4_CalP1_SP3_SP9nc0_SP7nc5_Xo3(M4_CalP1_SP3_SP9nc0_SP7nc5_NotB, M4_CalP1_Propbus_2, M4_CalP1_SP3_SP9nc0_SP7nc5_line3); nand2 M4_CalP1_SP3_SP9nc0_SP7nc5_Xo4(M4_CalP1_SP3_SP9nc0_SP7nc5_line2, M4_CalP1_SP3_SP9nc0_SP7nc5_line3, M4_CalP1_SP3_line0); inv M4_CalP1_SP3_SP9nc1_Xo0(M4_CalP1_Propbus_3, M4_CalP1_SP3_SP9nc1_NotA); inv M4_CalP1_SP3_SP9nc1_Xo1(M4_CalP1_SP3_line0, M4_CalP1_SP3_SP9nc1_NotB); nand2 M4_CalP1_SP3_SP9nc1_Xo2(M4_CalP1_SP3_SP9nc1_NotA, M4_CalP1_SP3_line0, M4_CalP1_SP3_SP9nc1_line2); nand2 M4_CalP1_SP3_SP9nc1_Xo3(M4_CalP1_SP3_SP9nc1_NotB, M4_CalP1_Propbus_3, M4_CalP1_SP3_SP9nc1_line3); nand2 M4_CalP1_SP3_SP9nc1_Xo4(M4_CalP1_SP3_SP9nc1_line2, M4_CalP1_SP3_SP9nc1_line3, M4_CalP1_SP3_line1); inv M4_CalP1_SP3_SP9nc2_Xo0(M4_CalP1_Propbus_4, M4_CalP1_SP3_SP9nc2_NotA); inv M4_CalP1_SP3_SP9nc2_Xo1(M4_CalP1_SP3_line1, M4_CalP1_SP3_SP9nc2_NotB); nand2 M4_CalP1_SP3_SP9nc2_Xo2(M4_CalP1_SP3_SP9nc2_NotA, M4_CalP1_SP3_line1, M4_CalP1_SP3_SP9nc2_line2); nand2 M4_CalP1_SP3_SP9nc2_Xo3(M4_CalP1_SP3_SP9nc2_NotB, M4_CalP1_Propbus_4, M4_CalP1_SP3_SP9nc2_line3); nand2 M4_CalP1_SP3_SP9nc2_Xo4(M4_CalP1_SP3_SP9nc2_line2, M4_CalP1_SP3_SP9nc2_line3, M4_CalP1_ParLo0); inv M4_CalP1_SP4_SP9nc0_SP7c0(M4_CalP1_Propbus_2, M4_CalP1_SP4_SP9nc0_NewInbus_6); inv M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_Xo0(M4_CalP1_LocalC1_0, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_NotA); inv M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_Xo1(M4_CalP1_LocalC1_1, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_NotB); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_Xo2(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_NotA, M4_CalP1_LocalC1_1, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_line2); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_Xo3(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_NotB, M4_CalP1_LocalC1_0, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_line3); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_Xo4(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_line2, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc0_line3, M4_CalP1_SP4_SP9nc0_SP7c2_line0); inv M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_Xo0(M4_CalP1_LocalC1_2, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_NotA); inv M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_Xo1(M4_CalP1_SP4_SP9nc0_SP7c2_line0, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_NotB); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_Xo2(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_NotA, M4_CalP1_SP4_SP9nc0_SP7c2_line0, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_line2); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_Xo3(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_NotB, M4_CalP1_LocalC1_2, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_line3); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_Xo4(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_line2, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc1_line3, M4_CalP1_SP4_SP9nc0_SP7c2_line1); inv M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_Xo0(M4_CalP1_LocalC1_3, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_NotA); inv M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_Xo1(M4_CalP1_SP4_SP9nc0_SP7c2_line1, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_NotB); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_Xo2(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_NotA, M4_CalP1_SP4_SP9nc0_SP7c2_line1, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_line2); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_Xo3(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_NotB, M4_CalP1_LocalC1_3, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_line3); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_Xo4(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_line2, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc2_line3, M4_CalP1_SP4_SP9nc0_SP7c2_line2); inv M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_Xo0(M4_CalP1_Propbus_0, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_NotA); inv M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_Xo1(M4_CalP1_SP4_SP9nc0_SP7c2_line2, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_NotB); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_Xo2(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_NotA, M4_CalP1_SP4_SP9nc0_SP7c2_line2, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_line2); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_Xo3(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_NotB, M4_CalP1_Propbus_0, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_line3); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_Xo4(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_line2, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc3_line3, M4_CalP1_SP4_SP9nc0_SP7c2_line3); inv M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_Xo0(M4_CalP1_Propbus_1, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_NotA); inv M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_Xo1(M4_CalP1_SP4_SP9nc0_SP7c2_line3, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_NotB); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_Xo2(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_NotA, M4_CalP1_SP4_SP9nc0_SP7c2_line3, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_line2); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_Xo3(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_NotB, M4_CalP1_Propbus_1, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_line3); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_Xo4(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_line2, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc4_line3, M4_CalP1_SP4_SP9nc0_SP7c2_line4); inv M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_Xo0(M4_CalP1_SP4_SP9nc0_NewInbus_6, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_NotA); inv M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_Xo1(M4_CalP1_SP4_SP9nc0_SP7c2_line4, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_NotB); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_Xo2(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_NotA, M4_CalP1_SP4_SP9nc0_SP7c2_line4, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_line2); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_Xo3(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_NotB, M4_CalP1_SP4_SP9nc0_NewInbus_6, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_line3); nand2 M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_Xo4(M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_line2, M4_CalP1_SP4_SP9nc0_SP7c2_SP7nc5_line3, M4_CalP1_SP4_line0); inv M4_CalP1_SP4_SP9nc1_Xo0(M4_CalP1_Propbus_3, M4_CalP1_SP4_SP9nc1_NotA); inv M4_CalP1_SP4_SP9nc1_Xo1(M4_CalP1_SP4_line0, M4_CalP1_SP4_SP9nc1_NotB); nand2 M4_CalP1_SP4_SP9nc1_Xo2(M4_CalP1_SP4_SP9nc1_NotA, M4_CalP1_SP4_line0, M4_CalP1_SP4_SP9nc1_line2); nand2 M4_CalP1_SP4_SP9nc1_Xo3(M4_CalP1_SP4_SP9nc1_NotB, M4_CalP1_Propbus_3, M4_CalP1_SP4_SP9nc1_line3); nand2 M4_CalP1_SP4_SP9nc1_Xo4(M4_CalP1_SP4_SP9nc1_line2, M4_CalP1_SP4_SP9nc1_line3, M4_CalP1_SP4_line1); inv M4_CalP1_SP4_SP9nc2_Xo0(M4_CalP1_Propbus_4, M4_CalP1_SP4_SP9nc2_NotA); inv M4_CalP1_SP4_SP9nc2_Xo1(M4_CalP1_SP4_line1, M4_CalP1_SP4_SP9nc2_NotB); nand2 M4_CalP1_SP4_SP9nc2_Xo2(M4_CalP1_SP4_SP9nc2_NotA, M4_CalP1_SP4_line1, M4_CalP1_SP4_SP9nc2_line2); nand2 M4_CalP1_SP4_SP9nc2_Xo3(M4_CalP1_SP4_SP9nc2_NotB, M4_CalP1_Propbus_4, M4_CalP1_SP4_SP9nc2_line3); nand2 M4_CalP1_SP4_SP9nc2_Xo4(M4_CalP1_SP4_SP9nc2_line2, M4_CalP1_SP4_SP9nc2_line3, M4_CalP1_ParLo1); inv M4_CalP1_SP5_SP7nc0_Xo0(M4_CalP1_Genbus_5, M4_CalP1_SP5_SP7nc0_NotA); inv M4_CalP1_SP5_SP7nc0_Xo1(M4_CalP1_LocalC0_6, M4_CalP1_SP5_SP7nc0_NotB); nand2 M4_CalP1_SP5_SP7nc0_Xo2(M4_CalP1_SP5_SP7nc0_NotA, M4_CalP1_LocalC0_6, M4_CalP1_SP5_SP7nc0_line2); nand2 M4_CalP1_SP5_SP7nc0_Xo3(M4_CalP1_SP5_SP7nc0_NotB, M4_CalP1_Genbus_5, M4_CalP1_SP5_SP7nc0_line3); nand2 M4_CalP1_SP5_SP7nc0_Xo4(M4_CalP1_SP5_SP7nc0_line2, M4_CalP1_SP5_SP7nc0_line3, M4_CalP1_SP5_line0); inv M4_CalP1_SP5_SP7nc1_Xo0(M4_CalP1_LocalC0_7, M4_CalP1_SP5_SP7nc1_NotA); inv M4_CalP1_SP5_SP7nc1_Xo1(M4_CalP1_SP5_line0, M4_CalP1_SP5_SP7nc1_NotB); nand2 M4_CalP1_SP5_SP7nc1_Xo2(M4_CalP1_SP5_SP7nc1_NotA, M4_CalP1_SP5_line0, M4_CalP1_SP5_SP7nc1_line2); nand2 M4_CalP1_SP5_SP7nc1_Xo3(M4_CalP1_SP5_SP7nc1_NotB, M4_CalP1_LocalC0_7, M4_CalP1_SP5_SP7nc1_line3); nand2 M4_CalP1_SP5_SP7nc1_Xo4(M4_CalP1_SP5_SP7nc1_line2, M4_CalP1_SP5_SP7nc1_line3, M4_CalP1_SP5_line1); inv M4_CalP1_SP5_SP7nc2_Xo0(M4_CalP1_Propbus_5, M4_CalP1_SP5_SP7nc2_NotA); inv M4_CalP1_SP5_SP7nc2_Xo1(M4_CalP1_SP5_line1, M4_CalP1_SP5_SP7nc2_NotB); nand2 M4_CalP1_SP5_SP7nc2_Xo2(M4_CalP1_SP5_SP7nc2_NotA, M4_CalP1_SP5_line1, M4_CalP1_SP5_SP7nc2_line2); nand2 M4_CalP1_SP5_SP7nc2_Xo3(M4_CalP1_SP5_SP7nc2_NotB, M4_CalP1_Propbus_5, M4_CalP1_SP5_SP7nc2_line3); nand2 M4_CalP1_SP5_SP7nc2_Xo4(M4_CalP1_SP5_SP7nc2_line2, M4_CalP1_SP5_SP7nc2_line3, M4_CalP1_SP5_line2); inv M4_CalP1_SP5_SP7nc3_Xo0(M4_CalP1_Propbus_6, M4_CalP1_SP5_SP7nc3_NotA); inv M4_CalP1_SP5_SP7nc3_Xo1(M4_CalP1_SP5_line2, M4_CalP1_SP5_SP7nc3_NotB); nand2 M4_CalP1_SP5_SP7nc3_Xo2(M4_CalP1_SP5_SP7nc3_NotA, M4_CalP1_SP5_line2, M4_CalP1_SP5_SP7nc3_line2); nand2 M4_CalP1_SP5_SP7nc3_Xo3(M4_CalP1_SP5_SP7nc3_NotB, M4_CalP1_Propbus_6, M4_CalP1_SP5_SP7nc3_line3); nand2 M4_CalP1_SP5_SP7nc3_Xo4(M4_CalP1_SP5_SP7nc3_line2, M4_CalP1_SP5_SP7nc3_line3, M4_CalP1_SP5_line3); inv M4_CalP1_SP5_SP7nc4_Xo0(M4_CalP1_Propbus_7, M4_CalP1_SP5_SP7nc4_NotA); inv M4_CalP1_SP5_SP7nc4_Xo1(M4_CalP1_SP5_line3, M4_CalP1_SP5_SP7nc4_NotB); nand2 M4_CalP1_SP5_SP7nc4_Xo2(M4_CalP1_SP5_SP7nc4_NotA, M4_CalP1_SP5_line3, M4_CalP1_SP5_SP7nc4_line2); nand2 M4_CalP1_SP5_SP7nc4_Xo3(M4_CalP1_SP5_SP7nc4_NotB, M4_CalP1_Propbus_7, M4_CalP1_SP5_SP7nc4_line3); nand2 M4_CalP1_SP5_SP7nc4_Xo4(M4_CalP1_SP5_SP7nc4_line2, M4_CalP1_SP5_SP7nc4_line3, M4_CalP1_SP5_line4); inv M4_CalP1_SP5_SP7nc5_Xo0(M4_CalP1_Propbus_8, M4_CalP1_SP5_SP7nc5_NotA); inv M4_CalP1_SP5_SP7nc5_Xo1(M4_CalP1_SP5_line4, M4_CalP1_SP5_SP7nc5_NotB); nand2 M4_CalP1_SP5_SP7nc5_Xo2(M4_CalP1_SP5_SP7nc5_NotA, M4_CalP1_SP5_line4, M4_CalP1_SP5_SP7nc5_line2); nand2 M4_CalP1_SP5_SP7nc5_Xo3(M4_CalP1_SP5_SP7nc5_NotB, M4_CalP1_Propbus_8, M4_CalP1_SP5_SP7nc5_line3); nand2 M4_CalP1_SP5_SP7nc5_Xo4(M4_CalP1_SP5_SP7nc5_line2, M4_CalP1_SP5_SP7nc5_line3, M4_CalP1_ParHi0); inv M4_CalP1_SP6_SP7c0(M4_CalP1_Propbus_8, M4_CalP1_SP6_NewInbus_6); inv M4_CalP1_SP6_SP7c2_SP7nc0_Xo0(M4_CalP1_LocalC1_5, M4_CalP1_SP6_SP7c2_SP7nc0_NotA); inv M4_CalP1_SP6_SP7c2_SP7nc0_Xo1(M4_CalP1_LocalC1_6, M4_CalP1_SP6_SP7c2_SP7nc0_NotB); nand2 M4_CalP1_SP6_SP7c2_SP7nc0_Xo2(M4_CalP1_SP6_SP7c2_SP7nc0_NotA, M4_CalP1_LocalC1_6, M4_CalP1_SP6_SP7c2_SP7nc0_line2); nand2 M4_CalP1_SP6_SP7c2_SP7nc0_Xo3(M4_CalP1_SP6_SP7c2_SP7nc0_NotB, M4_CalP1_LocalC1_5, M4_CalP1_SP6_SP7c2_SP7nc0_line3); nand2 M4_CalP1_SP6_SP7c2_SP7nc0_Xo4(M4_CalP1_SP6_SP7c2_SP7nc0_line2, M4_CalP1_SP6_SP7c2_SP7nc0_line3, M4_CalP1_SP6_SP7c2_line0); inv M4_CalP1_SP6_SP7c2_SP7nc1_Xo0(M4_CalP1_LocalC1_7, M4_CalP1_SP6_SP7c2_SP7nc1_NotA); inv M4_CalP1_SP6_SP7c2_SP7nc1_Xo1(M4_CalP1_SP6_SP7c2_line0, M4_CalP1_SP6_SP7c2_SP7nc1_NotB); nand2 M4_CalP1_SP6_SP7c2_SP7nc1_Xo2(M4_CalP1_SP6_SP7c2_SP7nc1_NotA, M4_CalP1_SP6_SP7c2_line0, M4_CalP1_SP6_SP7c2_SP7nc1_line2); nand2 M4_CalP1_SP6_SP7c2_SP7nc1_Xo3(M4_CalP1_SP6_SP7c2_SP7nc1_NotB, M4_CalP1_LocalC1_7, M4_CalP1_SP6_SP7c2_SP7nc1_line3); nand2 M4_CalP1_SP6_SP7c2_SP7nc1_Xo4(M4_CalP1_SP6_SP7c2_SP7nc1_line2, M4_CalP1_SP6_SP7c2_SP7nc1_line3, M4_CalP1_SP6_SP7c2_line1); inv M4_CalP1_SP6_SP7c2_SP7nc2_Xo0(M4_CalP1_Propbus_5, M4_CalP1_SP6_SP7c2_SP7nc2_NotA); inv M4_CalP1_SP6_SP7c2_SP7nc2_Xo1(M4_CalP1_SP6_SP7c2_line1, M4_CalP1_SP6_SP7c2_SP7nc2_NotB); nand2 M4_CalP1_SP6_SP7c2_SP7nc2_Xo2(M4_CalP1_SP6_SP7c2_SP7nc2_NotA, M4_CalP1_SP6_SP7c2_line1, M4_CalP1_SP6_SP7c2_SP7nc2_line2); nand2 M4_CalP1_SP6_SP7c2_SP7nc2_Xo3(M4_CalP1_SP6_SP7c2_SP7nc2_NotB, M4_CalP1_Propbus_5, M4_CalP1_SP6_SP7c2_SP7nc2_line3); nand2 M4_CalP1_SP6_SP7c2_SP7nc2_Xo4(M4_CalP1_SP6_SP7c2_SP7nc2_line2, M4_CalP1_SP6_SP7c2_SP7nc2_line3, M4_CalP1_SP6_SP7c2_line2); inv M4_CalP1_SP6_SP7c2_SP7nc3_Xo0(M4_CalP1_Propbus_6, M4_CalP1_SP6_SP7c2_SP7nc3_NotA); inv M4_CalP1_SP6_SP7c2_SP7nc3_Xo1(M4_CalP1_SP6_SP7c2_line2, M4_CalP1_SP6_SP7c2_SP7nc3_NotB); nand2 M4_CalP1_SP6_SP7c2_SP7nc3_Xo2(M4_CalP1_SP6_SP7c2_SP7nc3_NotA, M4_CalP1_SP6_SP7c2_line2, M4_CalP1_SP6_SP7c2_SP7nc3_line2); nand2 M4_CalP1_SP6_SP7c2_SP7nc3_Xo3(M4_CalP1_SP6_SP7c2_SP7nc3_NotB, M4_CalP1_Propbus_6, M4_CalP1_SP6_SP7c2_SP7nc3_line3); nand2 M4_CalP1_SP6_SP7c2_SP7nc3_Xo4(M4_CalP1_SP6_SP7c2_SP7nc3_line2, M4_CalP1_SP6_SP7c2_SP7nc3_line3, M4_CalP1_SP6_SP7c2_line3); inv M4_CalP1_SP6_SP7c2_SP7nc4_Xo0(M4_CalP1_Propbus_7, M4_CalP1_SP6_SP7c2_SP7nc4_NotA); inv M4_CalP1_SP6_SP7c2_SP7nc4_Xo1(M4_CalP1_SP6_SP7c2_line3, M4_CalP1_SP6_SP7c2_SP7nc4_NotB); nand2 M4_CalP1_SP6_SP7c2_SP7nc4_Xo2(M4_CalP1_SP6_SP7c2_SP7nc4_NotA, M4_CalP1_SP6_SP7c2_line3, M4_CalP1_SP6_SP7c2_SP7nc4_line2); nand2 M4_CalP1_SP6_SP7c2_SP7nc4_Xo3(M4_CalP1_SP6_SP7c2_SP7nc4_NotB, M4_CalP1_Propbus_7, M4_CalP1_SP6_SP7c2_SP7nc4_line3); nand2 M4_CalP1_SP6_SP7c2_SP7nc4_Xo4(M4_CalP1_SP6_SP7c2_SP7nc4_line2, M4_CalP1_SP6_SP7c2_SP7nc4_line3, M4_CalP1_SP6_SP7c2_line4); inv M4_CalP1_SP6_SP7c2_SP7nc5_Xo0(M4_CalP1_SP6_NewInbus_6, M4_CalP1_SP6_SP7c2_SP7nc5_NotA); inv M4_CalP1_SP6_SP7c2_SP7nc5_Xo1(M4_CalP1_SP6_SP7c2_line4, M4_CalP1_SP6_SP7c2_SP7nc5_NotB); nand2 M4_CalP1_SP6_SP7c2_SP7nc5_Xo2(M4_CalP1_SP6_SP7c2_SP7nc5_NotA, M4_CalP1_SP6_SP7c2_line4, M4_CalP1_SP6_SP7c2_SP7nc5_line2); nand2 M4_CalP1_SP6_SP7c2_SP7nc5_Xo3(M4_CalP1_SP6_SP7c2_SP7nc5_NotB, M4_CalP1_SP6_NewInbus_6, M4_CalP1_SP6_SP7c2_SP7nc5_line3); nand2 M4_CalP1_SP6_SP7c2_SP7nc5_Xo4(M4_CalP1_SP6_SP7c2_SP7nc5_line2, M4_CalP1_SP6_SP7c2_SP7nc5_line3, M4_CalP1_ParHi1); inv M4_CalP1_SP7_Mux2_0(in1497, M4_CalP1_SP7_Not_ContIn); and2 M4_CalP1_SP7_Mux2_1(M4_CalP1_ParLo0, M4_CalP1_SP7_Not_ContIn, M4_CalP1_SP7_line1); and2 M4_CalP1_SP7_Mux2_2(M4_CalP1_ParLo1, in1497, M4_CalP1_SP7_line2); or2 M4_CalP1_SP7_Mux2_3(M4_CalP1_SP7_line1, M4_CalP1_SP7_line2, M4_CalP1_ParLo); inv M4_CalP1_SP8_Mux2_0(M4_CalP1_LocalC0_4, M4_CalP1_SP8_Not_ContIn); and2 M4_CalP1_SP8_Mux2_1(M4_CalP1_ParHi0, M4_CalP1_SP8_Not_ContIn, M4_CalP1_SP8_line1); and2 M4_CalP1_SP8_Mux2_2(M4_CalP1_ParHi1, M4_CalP1_LocalC0_4, M4_CalP1_SP8_line2); or2 M4_CalP1_SP8_Mux2_3(M4_CalP1_SP8_line1, M4_CalP1_SP8_line2, M4_CalP1_ParHiCin0); inv M4_CalP1_SP9_Mux2_0(M4_CalP1_LocalC1_4, M4_CalP1_SP9_Not_ContIn); and2 M4_CalP1_SP9_Mux2_1(M4_CalP1_ParHi0, M4_CalP1_SP9_Not_ContIn, M4_CalP1_SP9_line1); and2 M4_CalP1_SP9_Mux2_2(M4_CalP1_ParHi1, M4_CalP1_LocalC1_4, M4_CalP1_SP9_line2); or2 M4_CalP1_SP9_Mux2_3(M4_CalP1_SP9_line1, M4_CalP1_SP9_line2, M4_CalP1_ParHiCin1); inv M4_CalP1_SP10_Mux2_0(in1497, M4_CalP1_SP10_Not_ContIn); and2 M4_CalP1_SP10_Mux2_1(M4_CalP1_ParHiCin0, M4_CalP1_SP10_Not_ContIn, M4_CalP1_SP10_line1); and2 M4_CalP1_SP10_Mux2_2(M4_CalP1_ParHiCin1, in1497, M4_CalP1_SP10_line2); or2 M4_CalP1_SP10_Mux2_3(M4_CalP1_SP10_line1, M4_CalP1_SP10_line2, M4_CalP1_ParHi); inv M4_CalP1_SP11_Xo0(M4_CalP1_ParLo, M4_CalP1_SP11_NotA); inv M4_CalP1_SP11_Xo1(M4_CalP1_ParHi, M4_CalP1_SP11_NotB); nand2 M4_CalP1_SP11_Xo2(M4_CalP1_SP11_NotA, M4_CalP1_ParHi, M4_CalP1_SP11_line2); nand2 M4_CalP1_SP11_Xo3(M4_CalP1_SP11_NotB, M4_CalP1_ParLo, M4_CalP1_SP11_line3); nand2 M4_CalP1_SP11_Xo4(M4_CalP1_SP11_line2, M4_CalP1_SP11_line3, M4_SumPar); inv M4_CalP2_M2M4_0(M4_LogicPar, M4_CalP2_NotLogicPar); inv M4_CalP2_M2M4_1(M4_SumPar, M4_CalP2_NotSumPar); inv M4_CalP2_M2M4_2_Mux2_0(in4091, M4_CalP2_M2M4_2_Not_ContIn); and2 M4_CalP2_M2M4_2_Mux2_1(M4_CalP2_NotLogicPar, M4_CalP2_M2M4_2_Not_ContIn, M4_CalP2_M2M4_2_line1); and2 M4_CalP2_M2M4_2_Mux2_2(M4_CalP2_NotSumPar, in4091, M4_CalP2_M2M4_2_line2); or2 M4_CalP2_M2M4_2_Mux2_3(M4_CalP2_M2M4_2_line1, M4_CalP2_M2M4_2_line2, M4_CalP2_line0); inv M4_CalP2_M2M4_3_Mux2_0(in4092, M4_CalP2_M2M4_3_Not_ContIn); and2 M4_CalP2_M2M4_3_Mux2_1(M4_CalP2_line0, M4_CalP2_M2M4_3_Not_ContIn, M4_CalP2_M2M4_3_line1); and2 M4_CalP2_M2M4_3_Mux2_2(in97, in4092, M4_CalP2_M2M4_3_line2); or2 M4_CalP2_M2M4_3_Mux2_3(M4_CalP2_M2M4_3_line1, M4_CalP2_M2M4_3_line2, Not_SumLogicParY); inv M4_CalP2_M2M4_4_Mux4_0(in4092, M4_CalP2_M2M4_4_Not_ContLo); inv M4_CalP2_M2M4_4_Mux4_1(in4091, M4_CalP2_M2M4_4_Not_ContHi); and3 M4_CalP2_M2M4_4_Mux4_2(M4_LogicPar, M4_CalP2_M2M4_4_Not_ContHi, M4_CalP2_M2M4_4_Not_ContLo, M4_CalP2_M2M4_4_line2); and3 M4_CalP2_M2M4_4_Mux4_3(in118, M4_CalP2_M2M4_4_Not_ContHi, in4092, M4_CalP2_M2M4_4_line3); and3 M4_CalP2_M2M4_4_Mux4_4(M4_SumPar, in4091, M4_CalP2_M2M4_4_Not_ContLo, M4_CalP2_M2M4_4_line4); and3 M4_CalP2_M2M4_4_Mux4_5(vdd, in4091, in4092, M4_CalP2_M2M4_4_line5); or4 M4_CalP2_M2M4_4_Mux4_6(M4_CalP2_M2M4_4_line2, M4_CalP2_M2M4_4_line3, M4_CalP2_M2M4_4_line4, M4_CalP2_M2M4_4_line5, out882); inv M5_MP0_MXS0_Mux4_0(in1689, M5_MP0_MXS0_Not_ContLo); inv M5_MP0_MXS0_Mux4_1(in1690, M5_MP0_MXS0_Not_ContHi); and3 M5_MP0_MXS0_Mux4_2(Not_SumLogicParX, M5_MP0_MXS0_Not_ContHi, M5_MP0_MXS0_Not_ContLo, M5_MP0_MXS0_line2); and3 M5_MP0_MXS0_Mux4_3(Not_SumLogicParY, M5_MP0_MXS0_Not_ContHi, in1689, M5_MP0_MXS0_line3); and3 M5_MP0_MXS0_Mux4_4(in176, in1690, M5_MP0_MXS0_Not_ContLo, M5_MP0_MXS0_line4); and3 M5_MP0_MXS0_Mux4_5(in179, in1690, in1689, M5_MP0_MXS0_line5); or4 M5_MP0_MXS0_Mux4_6(M5_MP0_MXS0_line2, M5_MP0_MXS0_line3, M5_MP0_MXS0_line4, M5_MP0_MXS0_line5, M5_MP0_tempOut1); inv M5_MP0_MXS1_Mux4_0(in1691, M5_MP0_MXS1_Not_ContLo); inv M5_MP0_MXS1_Mux4_1(in1694, M5_MP0_MXS1_Not_ContHi); and3 M5_MP0_MXS1_Mux4_2(Not_SumLogicParX, M5_MP0_MXS1_Not_ContHi, M5_MP0_MXS1_Not_ContLo, M5_MP0_MXS1_line2); and3 M5_MP0_MXS1_Mux4_3(Not_SumLogicParY, M5_MP0_MXS1_Not_ContHi, in1691, M5_MP0_MXS1_line3); and3 M5_MP0_MXS1_Mux4_4(in176, in1694, M5_MP0_MXS1_Not_ContLo, M5_MP0_MXS1_line4); and3 M5_MP0_MXS1_Mux4_5(in179, in1694, in1691, M5_MP0_MXS1_line5); or4 M5_MP0_MXS1_Mux4_6(M5_MP0_MXS1_line2, M5_MP0_MXS1_line3, M5_MP0_MXS1_line4, M5_MP0_MXS1_line5, M5_MP0_tempOut2); inv M5_MP0_MXS2_Mux4_0(in4088, M5_MP0_MXS2_Not_ContLo); inv M5_MP0_MXS2_Mux4_1(in4087, M5_MP0_MXS2_Not_ContHi); and3 M5_MP0_MXS2_Mux4_2(Not_SumLogicParX, M5_MP0_MXS2_Not_ContHi, M5_MP0_MXS2_Not_ContLo, M5_MP0_MXS2_line2); and3 M5_MP0_MXS2_Mux4_3(Not_SumLogicParY, M5_MP0_MXS2_Not_ContHi, in4088, M5_MP0_MXS2_line3); and3 M5_MP0_MXS2_Mux4_4(in14, in4087, M5_MP0_MXS2_Not_ContLo, M5_MP0_MXS2_line4); and3 M5_MP0_MXS2_Mux4_5(in64, in4087, in4088, M5_MP0_MXS2_line5); or4 M5_MP0_MXS2_Mux4_6(M5_MP0_MXS2_line2, M5_MP0_MXS2_line3, M5_MP0_MXS2_line4, M5_MP0_MXS2_line5, out767); inv M5_MP0_MXS3_Mux4_0(in4089, M5_MP0_MXS3_Not_ContLo); inv M5_MP0_MXS3_Mux4_1(in4090, M5_MP0_MXS3_Not_ContHi); and3 M5_MP0_MXS3_Mux4_2(Not_SumLogicParX, M5_MP0_MXS3_Not_ContHi, M5_MP0_MXS3_Not_ContLo, M5_MP0_MXS3_line2); and3 M5_MP0_MXS3_Mux4_3(Not_SumLogicParY, M5_MP0_MXS3_Not_ContHi, in4089, M5_MP0_MXS3_line3); and3 M5_MP0_MXS3_Mux4_4(in14, in4090, M5_MP0_MXS3_Not_ContLo, M5_MP0_MXS3_line4); and3 M5_MP0_MXS3_Mux4_5(in64, in4090, in4089, M5_MP0_MXS3_line5); or4 M5_MP0_MXS3_Mux4_6(M5_MP0_MXS3_line2, M5_MP0_MXS3_line3, M5_MP0_MXS3_line4, M5_MP0_MXS3_line5, out807); and2 M5_MP0_MXS4(M5_MP0_tempOut1, in137, M5_NotOP1); and2 M5_MP0_MXS5(M5_MP0_tempOut2, in137, M5_NotOP2); inv M5_MP1(M5_NotOP1, out658); inv M5_MP2(M5_NotOP2, out690); inv M0_Inv4_0(in3548, NotContLogic3_0_0); inv M0_Inv4_1(in3546, NotContLogic3_0_1); inv M0_Inv4_2(in3550, NotContLogic3_0_2); inv M0_Inv4_3(in3552, NotContLogic3_0_3); inv M6_CSL0_CL0_LB0_Mux2_0(in361, M6_CSL0_CL0_LB0_Not_ContIn); and2 M6_CSL0_CL0_LB0_Mux2_1(in254, M6_CSL0_CL0_LB0_Not_ContIn, M6_CSL0_CL0_LB0_line1); and2 M6_CSL0_CL0_LB0_Mux2_2(in242, in361, M6_CSL0_CL0_LB0_line2); or2 M6_CSL0_CL0_LB0_Mux2_3(M6_CSL0_CL0_LB0_line1, M6_CSL0_CL0_LB0_line2, M6_CSL0_CL0_line0); inv M6_CSL0_CL0_LB1_Mux2_0(in361, M6_CSL0_CL0_LB1_Not_ContIn); and2 M6_CSL0_CL0_LB1_Mux2_1(in251, M6_CSL0_CL0_LB1_Not_ContIn, M6_CSL0_CL0_LB1_line1); and2 M6_CSL0_CL0_LB1_Mux2_2(in248, in361, M6_CSL0_CL0_LB1_line2); or2 M6_CSL0_CL0_LB1_Mux2_3(M6_CSL0_CL0_LB1_line1, M6_CSL0_CL0_LB1_line2, M6_CSL0_CL0_line1); or2 M6_CSL0_CL0_LB2(vdd, M6_CSL0_CL0_line0, M6_CSL0_CL0_line2); nand2 M6_CSL0_CL0_LB3(vdd, M6_CSL0_CL0_line1, M6_CSL0_CL0_line3); and2 M6_CSL0_CL0_LB4(M6_CSL0_CL0_line2, M6_CSL0_CL0_line3, LogicXbus_0); inv M6_CSL0_CL1_LB0_Mux2_0(in351, M6_CSL0_CL1_LB0_Not_ContIn); and2 M6_CSL0_CL1_LB0_Mux2_1(NotContLogic3_0_0, M6_CSL0_CL1_LB0_Not_ContIn, M6_CSL0_CL1_LB0_line1); and2 M6_CSL0_CL1_LB0_Mux2_2(NotContLogic3_0_1, in351, M6_CSL0_CL1_LB0_line2); or2 M6_CSL0_CL1_LB0_Mux2_3(M6_CSL0_CL1_LB0_line1, M6_CSL0_CL1_LB0_line2, M6_CSL0_CL1_line0); inv M6_CSL0_CL1_LB1_Mux2_0(in351, M6_CSL0_CL1_LB1_Not_ContIn); and2 M6_CSL0_CL1_LB1_Mux2_1(NotContLogic3_0_2, M6_CSL0_CL1_LB1_Not_ContIn, M6_CSL0_CL1_LB1_line1); and2 M6_CSL0_CL1_LB1_Mux2_2(NotContLogic3_0_3, in351, M6_CSL0_CL1_LB1_line2); or2 M6_CSL0_CL1_LB1_Mux2_3(M6_CSL0_CL1_LB1_line1, M6_CSL0_CL1_LB1_line2, M6_CSL0_CL1_line1); or2 M6_CSL0_CL1_LB2(in534, M6_CSL0_CL1_line0, M6_CSL0_CL1_line2); nand2 M6_CSL0_CL1_LB3(in534, M6_CSL0_CL1_line1, M6_CSL0_CL1_line3); and2 M6_CSL0_CL1_LB4(M6_CSL0_CL1_line2, M6_CSL0_CL1_line3, LogicXbus_1); inv M6_CSL0_CL2_LB0_Mux2_0(in341, M6_CSL0_CL2_LB0_Not_ContIn); and2 M6_CSL0_CL2_LB0_Mux2_1(NotContLogic3_0_0, M6_CSL0_CL2_LB0_Not_ContIn, M6_CSL0_CL2_LB0_line1); and2 M6_CSL0_CL2_LB0_Mux2_2(NotContLogic3_0_1, in341, M6_CSL0_CL2_LB0_line2); or2 M6_CSL0_CL2_LB0_Mux2_3(M6_CSL0_CL2_LB0_line1, M6_CSL0_CL2_LB0_line2, M6_CSL0_CL2_line0); inv M6_CSL0_CL2_LB1_Mux2_0(in341, M6_CSL0_CL2_LB1_Not_ContIn); and2 M6_CSL0_CL2_LB1_Mux2_1(NotContLogic3_0_2, M6_CSL0_CL2_LB1_Not_ContIn, M6_CSL0_CL2_LB1_line1); and2 M6_CSL0_CL2_LB1_Mux2_2(NotContLogic3_0_3, in341, M6_CSL0_CL2_LB1_line2); or2 M6_CSL0_CL2_LB1_Mux2_3(M6_CSL0_CL2_LB1_line1, M6_CSL0_CL2_LB1_line2, M6_CSL0_CL2_line1); or2 M6_CSL0_CL2_LB2(in523, M6_CSL0_CL2_line0, M6_CSL0_CL2_line2); nand2 M6_CSL0_CL2_LB3(in523, M6_CSL0_CL2_line1, M6_CSL0_CL2_line3); and2 M6_CSL0_CL2_LB4(M6_CSL0_CL2_line2, M6_CSL0_CL2_line3, LogicXbus_2); inv M6_CSL0_CL3_LB0_Mux2_0(vdd, M6_CSL0_CL3_LB0_Not_ContIn); and2 M6_CSL0_CL3_LB0_Mux2_1(NotContLogic3_0_0, M6_CSL0_CL3_LB0_Not_ContIn, M6_CSL0_CL3_LB0_line1); and2 M6_CSL0_CL3_LB0_Mux2_2(NotContLogic3_0_1, vdd, M6_CSL0_CL3_LB0_line2); or2 M6_CSL0_CL3_LB0_Mux2_3(M6_CSL0_CL3_LB0_line1, M6_CSL0_CL3_LB0_line2, M6_CSL0_CL3_line0); inv M6_CSL0_CL3_LB1_Mux2_0(vdd, M6_CSL0_CL3_LB1_Not_ContIn); and2 M6_CSL0_CL3_LB1_Mux2_1(NotContLogic3_0_2, M6_CSL0_CL3_LB1_Not_ContIn, M6_CSL0_CL3_LB1_line1); and2 M6_CSL0_CL3_LB1_Mux2_2(NotContLogic3_0_3, vdd, M6_CSL0_CL3_LB1_line2); or2 M6_CSL0_CL3_LB1_Mux2_3(M6_CSL0_CL3_LB1_line1, M6_CSL0_CL3_LB1_line2, M6_CSL0_CL3_line1); or2 M6_CSL0_CL3_LB2(in514, M6_CSL0_CL3_line0, M6_CSL0_CL3_line2); nand2 M6_CSL0_CL3_LB3(in514, M6_CSL0_CL3_line1, M6_CSL0_CL3_line3); and2 M6_CSL0_CL3_LB4(M6_CSL0_CL3_line2, M6_CSL0_CL3_line3, LogicXbus_3); inv M6_CSL0_CL4_LB0_Mux2_0(in324, M6_CSL0_CL4_LB0_Not_ContIn); and2 M6_CSL0_CL4_LB0_Mux2_1(NotContLogic3_0_0, M6_CSL0_CL4_LB0_Not_ContIn, M6_CSL0_CL4_LB0_line1); and2 M6_CSL0_CL4_LB0_Mux2_2(NotContLogic3_0_1, in324, M6_CSL0_CL4_LB0_line2); or2 M6_CSL0_CL4_LB0_Mux2_3(M6_CSL0_CL4_LB0_line1, M6_CSL0_CL4_LB0_line2, M6_CSL0_CL4_line0); inv M6_CSL0_CL4_LB1_Mux2_0(in324, M6_CSL0_CL4_LB1_Not_ContIn); and2 M6_CSL0_CL4_LB1_Mux2_1(NotContLogic3_0_2, M6_CSL0_CL4_LB1_Not_ContIn, M6_CSL0_CL4_LB1_line1); and2 M6_CSL0_CL4_LB1_Mux2_2(NotContLogic3_0_3, in324, M6_CSL0_CL4_LB1_line2); or2 M6_CSL0_CL4_LB1_Mux2_3(M6_CSL0_CL4_LB1_line1, M6_CSL0_CL4_LB1_line2, M6_CSL0_CL4_line1); or2 M6_CSL0_CL4_LB2(in503, M6_CSL0_CL4_line0, M6_CSL0_CL4_line2); nand2 M6_CSL0_CL4_LB3(in503, M6_CSL0_CL4_line1, M6_CSL0_CL4_line3); and2 M6_CSL0_CL4_LB4(M6_CSL0_CL4_line2, M6_CSL0_CL4_line3, LogicXbus_4); inv M6_CSL0_CL5_LB0_Mux2_0(in316, M6_CSL0_CL5_LB0_Not_ContIn); and2 M6_CSL0_CL5_LB0_Mux2_1(in254, M6_CSL0_CL5_LB0_Not_ContIn, M6_CSL0_CL5_LB0_line1); and2 M6_CSL0_CL5_LB0_Mux2_2(in242, in316, M6_CSL0_CL5_LB0_line2); or2 M6_CSL0_CL5_LB0_Mux2_3(M6_CSL0_CL5_LB0_line1, M6_CSL0_CL5_LB0_line2, M6_CSL0_CL5_line0); inv M6_CSL0_CL5_LB1_Mux2_0(in316, M6_CSL0_CL5_LB1_Not_ContIn); and2 M6_CSL0_CL5_LB1_Mux2_1(in251, M6_CSL0_CL5_LB1_Not_ContIn, M6_CSL0_CL5_LB1_line1); and2 M6_CSL0_CL5_LB1_Mux2_2(in248, in316, M6_CSL0_CL5_LB1_line2); or2 M6_CSL0_CL5_LB1_Mux2_3(M6_CSL0_CL5_LB1_line1, M6_CSL0_CL5_LB1_line2, M6_CSL0_CL5_line1); or2 M6_CSL0_CL5_LB2(in490, M6_CSL0_CL5_line0, M6_CSL0_CL5_line2); nand2 M6_CSL0_CL5_LB3(in490, M6_CSL0_CL5_line1, M6_CSL0_CL5_line3); and2 M6_CSL0_CL5_LB4(M6_CSL0_CL5_line2, M6_CSL0_CL5_line3, LogicXbus_5); inv M6_CSL0_CL6_LB0_Mux2_0(in308, M6_CSL0_CL6_LB0_Not_ContIn); and2 M6_CSL0_CL6_LB0_Mux2_1(in254, M6_CSL0_CL6_LB0_Not_ContIn, M6_CSL0_CL6_LB0_line1); and2 M6_CSL0_CL6_LB0_Mux2_2(in242, in308, M6_CSL0_CL6_LB0_line2); or2 M6_CSL0_CL6_LB0_Mux2_3(M6_CSL0_CL6_LB0_line1, M6_CSL0_CL6_LB0_line2, M6_CSL0_CL6_line0); inv M6_CSL0_CL6_LB1_Mux2_0(in308, M6_CSL0_CL6_LB1_Not_ContIn); and2 M6_CSL0_CL6_LB1_Mux2_1(in251, M6_CSL0_CL6_LB1_Not_ContIn, M6_CSL0_CL6_LB1_line1); and2 M6_CSL0_CL6_LB1_Mux2_2(in248, in308, M6_CSL0_CL6_LB1_line2); or2 M6_CSL0_CL6_LB1_Mux2_3(M6_CSL0_CL6_LB1_line1, M6_CSL0_CL6_LB1_line2, M6_CSL0_CL6_line1); or2 M6_CSL0_CL6_LB2(in479, M6_CSL0_CL6_line0, M6_CSL0_CL6_line2); nand2 M6_CSL0_CL6_LB3(in479, M6_CSL0_CL6_line1, M6_CSL0_CL6_line3); and2 M6_CSL0_CL6_LB4(M6_CSL0_CL6_line2, M6_CSL0_CL6_line3, LogicXbus_6); inv M6_CSL0_CL7_LB0_Mux2_0(in302, M6_CSL0_CL7_LB0_Not_ContIn); and2 M6_CSL0_CL7_LB0_Mux2_1(in254, M6_CSL0_CL7_LB0_Not_ContIn, M6_CSL0_CL7_LB0_line1); and2 M6_CSL0_CL7_LB0_Mux2_2(in242, in302, M6_CSL0_CL7_LB0_line2); or2 M6_CSL0_CL7_LB0_Mux2_3(M6_CSL0_CL7_LB0_line1, M6_CSL0_CL7_LB0_line2, M6_CSL0_CL7_line0); inv M6_CSL0_CL7_LB1_Mux2_0(in302, M6_CSL0_CL7_LB1_Not_ContIn); and2 M6_CSL0_CL7_LB1_Mux2_1(in251, M6_CSL0_CL7_LB1_Not_ContIn, M6_CSL0_CL7_LB1_line1); and2 M6_CSL0_CL7_LB1_Mux2_2(in248, in302, M6_CSL0_CL7_LB1_line2); or2 M6_CSL0_CL7_LB1_Mux2_3(M6_CSL0_CL7_LB1_line1, M6_CSL0_CL7_LB1_line2, M6_CSL0_CL7_line1); or2 M6_CSL0_CL7_LB2(vdd, M6_CSL0_CL7_line0, M6_CSL0_CL7_line2); nand2 M6_CSL0_CL7_LB3(vdd, M6_CSL0_CL7_line1, M6_CSL0_CL7_line3); and2 M6_CSL0_CL7_LB4(M6_CSL0_CL7_line2, M6_CSL0_CL7_line3, LogicXbus_7); inv M6_CSL0_CL8_LB0_Mux2_0(in293, M6_CSL0_CL8_LB0_Not_ContIn); and2 M6_CSL0_CL8_LB0_Mux2_1(in254, M6_CSL0_CL8_LB0_Not_ContIn, M6_CSL0_CL8_LB0_line1); and2 M6_CSL0_CL8_LB0_Mux2_2(in242, in293, M6_CSL0_CL8_LB0_line2); or2 M6_CSL0_CL8_LB0_Mux2_3(M6_CSL0_CL8_LB0_line1, M6_CSL0_CL8_LB0_line2, M6_CSL0_CL8_line0); inv M6_CSL0_CL8_LB1_Mux2_0(in293, M6_CSL0_CL8_LB1_Not_ContIn); and2 M6_CSL0_CL8_LB1_Mux2_1(in251, M6_CSL0_CL8_LB1_Not_ContIn, M6_CSL0_CL8_LB1_line1); and2 M6_CSL0_CL8_LB1_Mux2_2(in248, in293, M6_CSL0_CL8_LB1_line2); or2 M6_CSL0_CL8_LB1_Mux2_3(M6_CSL0_CL8_LB1_line1, M6_CSL0_CL8_LB1_line2, M6_CSL0_CL8_line1); or2 M6_CSL0_CL8_LB2(gnd, M6_CSL0_CL8_line0, M6_CSL0_CL8_line2); nand2 M6_CSL0_CL8_LB3(gnd, M6_CSL0_CL8_line1, M6_CSL0_CL8_line3); and2 M6_CSL0_CL8_LB4(M6_CSL0_CL8_line2, M6_CSL0_CL8_line3, LogicXbus_8); and2 M6_CSL1_Add0_GP9_0(Xbus_0, vdd, M6_CSL1_Genbus_0); and2 M6_CSL1_Add0_GP9_1(Xbus_1, in534, M6_CSL1_Genbus_1); and2 M6_CSL1_Add0_GP9_2(Xbus_2, in523, M6_CSL1_Genbus_2); and2 M6_CSL1_Add0_GP9_3(Xbus_3, in514, M6_CSL1_Genbus_3); and2 M6_CSL1_Add0_GP9_4(Xbus_4, in503, M6_CSL1_Genbus_4); and2 M6_CSL1_Add0_GP9_5(Xbus_5, in490, M6_CSL1_Genbus_5); and2 M6_CSL1_Add0_GP9_6(Xbus_6, in479, M6_CSL1_Genbus_6); and2 M6_CSL1_Add0_GP9_7(Xbus_7, vdd, M6_CSL1_Genbus_7); and2 M6_CSL1_Add0_GP9_8(Xbus_8, vdd, M6_CSL1_Genbus_8); inv M6_CSL1_Add0_GP9_9_Xo0(Xbus_0, M6_CSL1_Add0_GP9_9_NotA); inv M6_CSL1_Add0_GP9_9_Xo1(vdd, M6_CSL1_Add0_GP9_9_NotB); nand2 M6_CSL1_Add0_GP9_9_Xo2(M6_CSL1_Add0_GP9_9_NotA, vdd, M6_CSL1_Add0_GP9_9_line2); nand2 M6_CSL1_Add0_GP9_9_Xo3(M6_CSL1_Add0_GP9_9_NotB, Xbus_0, M6_CSL1_Add0_GP9_9_line3); nand2 M6_CSL1_Add0_GP9_9_Xo4(M6_CSL1_Add0_GP9_9_line2, M6_CSL1_Add0_GP9_9_line3, M6_CSL1_Propbus_0); inv M6_CSL1_Add0_GP9_10_Xo0(Xbus_1, M6_CSL1_Add0_GP9_10_NotA); inv M6_CSL1_Add0_GP9_10_Xo1(in534, M6_CSL1_Add0_GP9_10_NotB); nand2 M6_CSL1_Add0_GP9_10_Xo2(M6_CSL1_Add0_GP9_10_NotA, in534, M6_CSL1_Add0_GP9_10_line2); nand2 M6_CSL1_Add0_GP9_10_Xo3(M6_CSL1_Add0_GP9_10_NotB, Xbus_1, M6_CSL1_Add0_GP9_10_line3); nand2 M6_CSL1_Add0_GP9_10_Xo4(M6_CSL1_Add0_GP9_10_line2, M6_CSL1_Add0_GP9_10_line3, M6_CSL1_Propbus_1); inv M6_CSL1_Add0_GP9_11_Xo0(Xbus_2, M6_CSL1_Add0_GP9_11_NotA); inv M6_CSL1_Add0_GP9_11_Xo1(in523, M6_CSL1_Add0_GP9_11_NotB); nand2 M6_CSL1_Add0_GP9_11_Xo2(M6_CSL1_Add0_GP9_11_NotA, in523, M6_CSL1_Add0_GP9_11_line2); nand2 M6_CSL1_Add0_GP9_11_Xo3(M6_CSL1_Add0_GP9_11_NotB, Xbus_2, M6_CSL1_Add0_GP9_11_line3); nand2 M6_CSL1_Add0_GP9_11_Xo4(M6_CSL1_Add0_GP9_11_line2, M6_CSL1_Add0_GP9_11_line3, M6_CSL1_Propbus_2); inv M6_CSL1_Add0_GP9_12_Xo0(Xbus_3, M6_CSL1_Add0_GP9_12_NotA); inv M6_CSL1_Add0_GP9_12_Xo1(in514, M6_CSL1_Add0_GP9_12_NotB); nand2 M6_CSL1_Add0_GP9_12_Xo2(M6_CSL1_Add0_GP9_12_NotA, in514, M6_CSL1_Add0_GP9_12_line2); nand2 M6_CSL1_Add0_GP9_12_Xo3(M6_CSL1_Add0_GP9_12_NotB, Xbus_3, M6_CSL1_Add0_GP9_12_line3); nand2 M6_CSL1_Add0_GP9_12_Xo4(M6_CSL1_Add0_GP9_12_line2, M6_CSL1_Add0_GP9_12_line3, M6_CSL1_Propbus_3); inv M6_CSL1_Add0_GP9_13_Xo0(Xbus_4, M6_CSL1_Add0_GP9_13_NotA); inv M6_CSL1_Add0_GP9_13_Xo1(in503, M6_CSL1_Add0_GP9_13_NotB); nand2 M6_CSL1_Add0_GP9_13_Xo2(M6_CSL1_Add0_GP9_13_NotA, in503, M6_CSL1_Add0_GP9_13_line2); nand2 M6_CSL1_Add0_GP9_13_Xo3(M6_CSL1_Add0_GP9_13_NotB, Xbus_4, M6_CSL1_Add0_GP9_13_line3); nand2 M6_CSL1_Add0_GP9_13_Xo4(M6_CSL1_Add0_GP9_13_line2, M6_CSL1_Add0_GP9_13_line3, M6_CSL1_Propbus_4); inv M6_CSL1_Add0_GP9_14_Xo0(Xbus_5, M6_CSL1_Add0_GP9_14_NotA); inv M6_CSL1_Add0_GP9_14_Xo1(in490, M6_CSL1_Add0_GP9_14_NotB); nand2 M6_CSL1_Add0_GP9_14_Xo2(M6_CSL1_Add0_GP9_14_NotA, in490, M6_CSL1_Add0_GP9_14_line2); nand2 M6_CSL1_Add0_GP9_14_Xo3(M6_CSL1_Add0_GP9_14_NotB, Xbus_5, M6_CSL1_Add0_GP9_14_line3); nand2 M6_CSL1_Add0_GP9_14_Xo4(M6_CSL1_Add0_GP9_14_line2, M6_CSL1_Add0_GP9_14_line3, M6_CSL1_Propbus_5); inv M6_CSL1_Add0_GP9_15_Xo0(Xbus_6, M6_CSL1_Add0_GP9_15_NotA); inv M6_CSL1_Add0_GP9_15_Xo1(in479, M6_CSL1_Add0_GP9_15_NotB); nand2 M6_CSL1_Add0_GP9_15_Xo2(M6_CSL1_Add0_GP9_15_NotA, in479, M6_CSL1_Add0_GP9_15_line2); nand2 M6_CSL1_Add0_GP9_15_Xo3(M6_CSL1_Add0_GP9_15_NotB, Xbus_6, M6_CSL1_Add0_GP9_15_line3); nand2 M6_CSL1_Add0_GP9_15_Xo4(M6_CSL1_Add0_GP9_15_line2, M6_CSL1_Add0_GP9_15_line3, M6_CSL1_Propbus_6); inv M6_CSL1_Add0_GP9_16_Xo0(Xbus_7, M6_CSL1_Add0_GP9_16_NotA); inv M6_CSL1_Add0_GP9_16_Xo1(vdd, M6_CSL1_Add0_GP9_16_NotB); nand2 M6_CSL1_Add0_GP9_16_Xo2(M6_CSL1_Add0_GP9_16_NotA, vdd, M6_CSL1_Add0_GP9_16_line2); nand2 M6_CSL1_Add0_GP9_16_Xo3(M6_CSL1_Add0_GP9_16_NotB, Xbus_7, M6_CSL1_Add0_GP9_16_line3); nand2 M6_CSL1_Add0_GP9_16_Xo4(M6_CSL1_Add0_GP9_16_line2, M6_CSL1_Add0_GP9_16_line3, M6_CSL1_Propbus_7); inv M6_CSL1_Add0_GP9_17_Xo0(Xbus_8, M6_CSL1_Add0_GP9_17_NotA); inv M6_CSL1_Add0_GP9_17_Xo1(vdd, M6_CSL1_Add0_GP9_17_NotB); nand2 M6_CSL1_Add0_GP9_17_Xo2(M6_CSL1_Add0_GP9_17_NotA, vdd, M6_CSL1_Add0_GP9_17_line2); nand2 M6_CSL1_Add0_GP9_17_Xo3(M6_CSL1_Add0_GP9_17_NotB, Xbus_8, M6_CSL1_Add0_GP9_17_line3); nand2 M6_CSL1_Add0_GP9_17_Xo4(M6_CSL1_Add0_GP9_17_line2, M6_CSL1_Add0_GP9_17_line3, M6_CSL1_Propbus_8); and2 M6_CSL1_Add1_CB0_Ao2_0(M6_CSL1_Propbus_0, in54, M6_CSL1_Add1_CB0_line0); or2 M6_CSL1_Add1_CB0_Ao2_1(M6_CSL1_Genbus_0, M6_CSL1_Add1_CB0_line0, M6_CSL1_Carry_0); and2 M6_CSL1_Add1_CB1_Ao3a_0(M6_CSL1_Propbus_1, M6_CSL1_Genbus_0, M6_CSL1_Add1_CB1_line0); and3 M6_CSL1_Add1_CB1_Ao3a_1(M6_CSL1_Propbus_1, M6_CSL1_Propbus_0, in54, M6_CSL1_Add1_CB1_line1); or3 M6_CSL1_Add1_CB1_Ao3a_2(M6_CSL1_Genbus_1, M6_CSL1_Add1_CB1_line0, M6_CSL1_Add1_CB1_line1, M6_CSL1_Carry_1); and2 M6_CSL1_Add1_CB2_Ao4a_0(M6_CSL1_Propbus_2, M6_CSL1_Genbus_1, M6_CSL1_Add1_CB2_line0); and3 M6_CSL1_Add1_CB2_Ao4a_1(M6_CSL1_Propbus_2, M6_CSL1_Propbus_1, M6_CSL1_Genbus_0, M6_CSL1_Add1_CB2_line1); and4 M6_CSL1_Add1_CB2_Ao4a_2(M6_CSL1_Propbus_2, M6_CSL1_Propbus_1, M6_CSL1_Propbus_0, in54, M6_CSL1_Add1_CB2_line2); or4 M6_CSL1_Add1_CB2_Ao4a_3(M6_CSL1_Genbus_2, M6_CSL1_Add1_CB2_line0, M6_CSL1_Add1_CB2_line1, M6_CSL1_Add1_CB2_line2, M6_CSL1_Carry_2); and2 M6_CSL1_Add1_CB3_Ao5a_0(M6_CSL1_Propbus_3, M6_CSL1_Genbus_2, M6_CSL1_Add1_CB3_line0); and3 M6_CSL1_Add1_CB3_Ao5a_1(M6_CSL1_Propbus_3, M6_CSL1_Propbus_2, M6_CSL1_Genbus_1, M6_CSL1_Add1_CB3_line1); and4 M6_CSL1_Add1_CB3_Ao5a_2(M6_CSL1_Propbus_3, M6_CSL1_Propbus_2, M6_CSL1_Propbus_1, M6_CSL1_Genbus_0, M6_CSL1_Add1_CB3_line2); and5 M6_CSL1_Add1_CB3_Ao5a_3(M6_CSL1_Propbus_3, M6_CSL1_Propbus_2, M6_CSL1_Propbus_1, M6_CSL1_Propbus_0, in54, M6_CSL1_Add1_CB3_line3); or5 M6_CSL1_Add1_CB3_Ao5a_4(M6_CSL1_Genbus_3, M6_CSL1_Add1_CB3_line0, M6_CSL1_Add1_CB3_line1, M6_CSL1_Add1_CB3_line2, M6_CSL1_Add1_CB3_line3, M6_CSL1_Carry_3); and2 M6_CSL1_Add1_CB4_Ao5a_0(M6_CSL1_Propbus_4, M6_CSL1_Genbus_3, M6_CSL1_Add1_CB4_line0); and3 M6_CSL1_Add1_CB4_Ao5a_1(M6_CSL1_Propbus_4, M6_CSL1_Propbus_3, M6_CSL1_Genbus_2, M6_CSL1_Add1_CB4_line1); and4 M6_CSL1_Add1_CB4_Ao5a_2(M6_CSL1_Propbus_4, M6_CSL1_Propbus_3, M6_CSL1_Propbus_2, M6_CSL1_Genbus_1, M6_CSL1_Add1_CB4_line2); and5 M6_CSL1_Add1_CB4_Ao5a_3(M6_CSL1_Propbus_4, M6_CSL1_Propbus_3, M6_CSL1_Propbus_2, M6_CSL1_Propbus_1, M6_CSL1_Genbus_0, M6_CSL1_Add1_CB4_line3); or5 M6_CSL1_Add1_CB4_Ao5a_4(M6_CSL1_Genbus_4, M6_CSL1_Add1_CB4_line0, M6_CSL1_Add1_CB4_line1, M6_CSL1_Add1_CB4_line2, M6_CSL1_Add1_CB4_line3, M6_CSL1_Add1_LocalC0_4); and5 M6_CSL1_Add1_CB5(M6_CSL1_Propbus_0, M6_CSL1_Propbus_1, M6_CSL1_Propbus_2, M6_CSL1_Propbus_3, M6_CSL1_Propbus_4, M6_CSL1_Add1_Prop4_0); and2 M6_CSL1_Add1_CB6(in54, M6_CSL1_Add1_Prop4_0, M6_CSL1_Add1_PropCin); or2 M6_CSL1_Add1_CB7(M6_CSL1_Add1_LocalC0_4, M6_CSL1_Add1_PropCin, M6_CSL1_Carry_4); and2 M6_CSL1_Add1_CB8_Ao5a_0(M6_CSL1_Propbus_8, M6_CSL1_Genbus_7, M6_CSL1_Add1_CB8_line0); and3 M6_CSL1_Add1_CB8_Ao5a_1(M6_CSL1_Propbus_8, M6_CSL1_Propbus_7, M6_CSL1_Genbus_6, M6_CSL1_Add1_CB8_line1); and4 M6_CSL1_Add1_CB8_Ao5a_2(M6_CSL1_Propbus_8, M6_CSL1_Propbus_7, M6_CSL1_Propbus_6, M6_CSL1_Genbus_5, M6_CSL1_Add1_CB8_line2); and5 M6_CSL1_Add1_CB8_Ao5a_3(M6_CSL1_Propbus_8, M6_CSL1_Propbus_7, M6_CSL1_Propbus_6, M6_CSL1_Propbus_5, M6_CSL1_Add1_LocalC0_4, M6_CSL1_Add1_CB8_line3); or5 M6_CSL1_Add1_CB8_Ao5a_4(M6_CSL1_Genbus_8, M6_CSL1_Add1_CB8_line0, M6_CSL1_Add1_CB8_line1, M6_CSL1_Add1_CB8_line2, M6_CSL1_Add1_CB8_line3, out629); and4 M6_CSL1_Add1_CB9(M6_CSL1_Propbus_5, M6_CSL1_Propbus_6, M6_CSL1_Propbus_7, M6_CSL1_Propbus_8, M6_CSL1_Add1_Prop8_5); and2 M6_CSL1_Add1_CB10(M6_CSL1_Add1_Prop4_0, M6_CSL1_Add1_Prop8_5, out615); or2 M6_CSL1_Add2_GLC4_0(M6_CSL1_Genbus_5, M6_CSL1_Propbus_5, M6_CSL1_LocalHC1_0); and2 M6_CSL1_Add2_GLC4_1_Ao2_0(M6_CSL1_Propbus_6, M6_CSL1_Genbus_5, M6_CSL1_Add2_GLC4_1_line0); or2 M6_CSL1_Add2_GLC4_1_Ao2_1(M6_CSL1_Genbus_6, M6_CSL1_Add2_GLC4_1_line0, M6_CSL1_LocalHC0_1); and2 M6_CSL1_Add2_GLC4_2_Ao3a_0(M6_CSL1_Propbus_6, M6_CSL1_Genbus_5, M6_CSL1_Add2_GLC4_2_line0); and2 M6_CSL1_Add2_GLC4_2_Ao3a_1(M6_CSL1_Propbus_6, M6_CSL1_Propbus_5, M6_CSL1_Add2_GLC4_2_line1); or3 M6_CSL1_Add2_GLC4_2_Ao3a_2(M6_CSL1_Genbus_6, M6_CSL1_Add2_GLC4_2_line0, M6_CSL1_Add2_GLC4_2_line1, M6_CSL1_LocalHC1_1); and2 M6_CSL1_Add2_GLC4_3_Ao3a_0(M6_CSL1_Propbus_7, M6_CSL1_Genbus_6, M6_CSL1_Add2_GLC4_3_line0); and3 M6_CSL1_Add2_GLC4_3_Ao3a_1(M6_CSL1_Propbus_7, M6_CSL1_Propbus_6, M6_CSL1_Genbus_5, M6_CSL1_Add2_GLC4_3_line1); or3 M6_CSL1_Add2_GLC4_3_Ao3a_2(M6_CSL1_Genbus_7, M6_CSL1_Add2_GLC4_3_line0, M6_CSL1_Add2_GLC4_3_line1, M6_CSL1_LocalHC0_2); and2 M6_CSL1_Add2_GLC4_4_Ao4a_0(M6_CSL1_Propbus_7, M6_CSL1_Genbus_6, M6_CSL1_Add2_GLC4_4_line0); and3 M6_CSL1_Add2_GLC4_4_Ao4a_1(M6_CSL1_Propbus_7, M6_CSL1_Propbus_6, M6_CSL1_Genbus_5, M6_CSL1_Add2_GLC4_4_line1); and3 M6_CSL1_Add2_GLC4_4_Ao4a_2(M6_CSL1_Propbus_7, M6_CSL1_Propbus_6, M6_CSL1_Propbus_5, M6_CSL1_Add2_GLC4_4_line2); or4 M6_CSL1_Add2_GLC4_4_Ao4a_3(M6_CSL1_Genbus_7, M6_CSL1_Add2_GLC4_4_line0, M6_CSL1_Add2_GLC4_4_line1, M6_CSL1_Add2_GLC4_4_line2, M6_CSL1_LocalHC1_2); inv M6_CSL1_Add3_X2a6_0_Xo0(M6_CSL1_Propbus_0, M6_CSL1_Add3_X2a6_0_NotA); inv M6_CSL1_Add3_X2a6_0_Xo1(in54, M6_CSL1_Add3_X2a6_0_NotB); nand2 M6_CSL1_Add3_X2a6_0_Xo2(M6_CSL1_Add3_X2a6_0_NotA, in54, M6_CSL1_Add3_X2a6_0_line2); nand2 M6_CSL1_Add3_X2a6_0_Xo3(M6_CSL1_Add3_X2a6_0_NotB, M6_CSL1_Propbus_0, M6_CSL1_Add3_X2a6_0_line3); nand2 M6_CSL1_Add3_X2a6_0_Xo4(M6_CSL1_Add3_X2a6_0_line2, M6_CSL1_Add3_X2a6_0_line3, SumXbus_0); inv M6_CSL1_Add3_X2a6_1_Xo0(M6_CSL1_Propbus_1, M6_CSL1_Add3_X2a6_1_NotA); inv M6_CSL1_Add3_X2a6_1_Xo1(M6_CSL1_Carry_0, M6_CSL1_Add3_X2a6_1_NotB); nand2 M6_CSL1_Add3_X2a6_1_Xo2(M6_CSL1_Add3_X2a6_1_NotA, M6_CSL1_Carry_0, M6_CSL1_Add3_X2a6_1_line2); nand2 M6_CSL1_Add3_X2a6_1_Xo3(M6_CSL1_Add3_X2a6_1_NotB, M6_CSL1_Propbus_1, M6_CSL1_Add3_X2a6_1_line3); nand2 M6_CSL1_Add3_X2a6_1_Xo4(M6_CSL1_Add3_X2a6_1_line2, M6_CSL1_Add3_X2a6_1_line3, SumXbus_1); inv M6_CSL1_Add3_X2a6_2_Xo0(M6_CSL1_Propbus_2, M6_CSL1_Add3_X2a6_2_NotA); inv M6_CSL1_Add3_X2a6_2_Xo1(M6_CSL1_Carry_1, M6_CSL1_Add3_X2a6_2_NotB); nand2 M6_CSL1_Add3_X2a6_2_Xo2(M6_CSL1_Add3_X2a6_2_NotA, M6_CSL1_Carry_1, M6_CSL1_Add3_X2a6_2_line2); nand2 M6_CSL1_Add3_X2a6_2_Xo3(M6_CSL1_Add3_X2a6_2_NotB, M6_CSL1_Propbus_2, M6_CSL1_Add3_X2a6_2_line3); nand2 M6_CSL1_Add3_X2a6_2_Xo4(M6_CSL1_Add3_X2a6_2_line2, M6_CSL1_Add3_X2a6_2_line3, SumXbus_2); inv M6_CSL1_Add3_X2a6_3_Xo0(M6_CSL1_Propbus_3, M6_CSL1_Add3_X2a6_3_NotA); inv M6_CSL1_Add3_X2a6_3_Xo1(M6_CSL1_Carry_2, M6_CSL1_Add3_X2a6_3_NotB); nand2 M6_CSL1_Add3_X2a6_3_Xo2(M6_CSL1_Add3_X2a6_3_NotA, M6_CSL1_Carry_2, M6_CSL1_Add3_X2a6_3_line2); nand2 M6_CSL1_Add3_X2a6_3_Xo3(M6_CSL1_Add3_X2a6_3_NotB, M6_CSL1_Propbus_3, M6_CSL1_Add3_X2a6_3_line3); nand2 M6_CSL1_Add3_X2a6_3_Xo4(M6_CSL1_Add3_X2a6_3_line2, M6_CSL1_Add3_X2a6_3_line3, SumXbus_3); inv M6_CSL1_Add3_X2a6_4_Xo0(M6_CSL1_Propbus_4, M6_CSL1_Add3_X2a6_4_NotA); inv M6_CSL1_Add3_X2a6_4_Xo1(M6_CSL1_Carry_3, M6_CSL1_Add3_X2a6_4_NotB); nand2 M6_CSL1_Add3_X2a6_4_Xo2(M6_CSL1_Add3_X2a6_4_NotA, M6_CSL1_Carry_3, M6_CSL1_Add3_X2a6_4_line2); nand2 M6_CSL1_Add3_X2a6_4_Xo3(M6_CSL1_Add3_X2a6_4_NotB, M6_CSL1_Propbus_4, M6_CSL1_Add3_X2a6_4_line3); nand2 M6_CSL1_Add3_X2a6_4_Xo4(M6_CSL1_Add3_X2a6_4_line2, M6_CSL1_Add3_X2a6_4_line3, SumXbus_4); inv M6_CSL1_Add3_X2a6_5_Xo0(M6_CSL1_Propbus_5, M6_CSL1_Add3_X2a6_5_NotA); inv M6_CSL1_Add3_X2a6_5_Xo1(M6_CSL1_Carry_4, M6_CSL1_Add3_X2a6_5_NotB); nand2 M6_CSL1_Add3_X2a6_5_Xo2(M6_CSL1_Add3_X2a6_5_NotA, M6_CSL1_Carry_4, M6_CSL1_Add3_X2a6_5_line2); nand2 M6_CSL1_Add3_X2a6_5_Xo3(M6_CSL1_Add3_X2a6_5_NotB, M6_CSL1_Propbus_5, M6_CSL1_Add3_X2a6_5_line3); nand2 M6_CSL1_Add3_X2a6_5_Xo4(M6_CSL1_Add3_X2a6_5_line2, M6_CSL1_Add3_X2a6_5_line3, SumXbus_5); inv M6_CSL1_Add4_X2a6_0_Xo0(M6_CSL1_Propbus_6, M6_CSL1_Add4_X2a6_0_NotA); inv M6_CSL1_Add4_X2a6_0_Xo1(M6_CSL1_Genbus_5, M6_CSL1_Add4_X2a6_0_NotB); nand2 M6_CSL1_Add4_X2a6_0_Xo2(M6_CSL1_Add4_X2a6_0_NotA, M6_CSL1_Genbus_5, M6_CSL1_Add4_X2a6_0_line2); nand2 M6_CSL1_Add4_X2a6_0_Xo3(M6_CSL1_Add4_X2a6_0_NotB, M6_CSL1_Propbus_6, M6_CSL1_Add4_X2a6_0_line3); nand2 M6_CSL1_Add4_X2a6_0_Xo4(M6_CSL1_Add4_X2a6_0_line2, M6_CSL1_Add4_X2a6_0_line3, M6_CSL1_SumH01bus_0); inv M6_CSL1_Add4_X2a6_1_Xo0(M6_CSL1_Propbus_7, M6_CSL1_Add4_X2a6_1_NotA); inv M6_CSL1_Add4_X2a6_1_Xo1(M6_CSL1_LocalHC0_1, M6_CSL1_Add4_X2a6_1_NotB); nand2 M6_CSL1_Add4_X2a6_1_Xo2(M6_CSL1_Add4_X2a6_1_NotA, M6_CSL1_LocalHC0_1, M6_CSL1_Add4_X2a6_1_line2); nand2 M6_CSL1_Add4_X2a6_1_Xo3(M6_CSL1_Add4_X2a6_1_NotB, M6_CSL1_Propbus_7, M6_CSL1_Add4_X2a6_1_line3); nand2 M6_CSL1_Add4_X2a6_1_Xo4(M6_CSL1_Add4_X2a6_1_line2, M6_CSL1_Add4_X2a6_1_line3, M6_CSL1_SumH01bus_1); inv M6_CSL1_Add4_X2a6_2_Xo0(M6_CSL1_Propbus_8, M6_CSL1_Add4_X2a6_2_NotA); inv M6_CSL1_Add4_X2a6_2_Xo1(M6_CSL1_LocalHC0_2, M6_CSL1_Add4_X2a6_2_NotB); nand2 M6_CSL1_Add4_X2a6_2_Xo2(M6_CSL1_Add4_X2a6_2_NotA, M6_CSL1_LocalHC0_2, M6_CSL1_Add4_X2a6_2_line2); nand2 M6_CSL1_Add4_X2a6_2_Xo3(M6_CSL1_Add4_X2a6_2_NotB, M6_CSL1_Propbus_8, M6_CSL1_Add4_X2a6_2_line3); nand2 M6_CSL1_Add4_X2a6_2_Xo4(M6_CSL1_Add4_X2a6_2_line2, M6_CSL1_Add4_X2a6_2_line3, M6_CSL1_SumH01bus_2); inv M6_CSL1_Add4_X2a6_3_Xo0(M6_CSL1_Propbus_6, M6_CSL1_Add4_X2a6_3_NotA); inv M6_CSL1_Add4_X2a6_3_Xo1(M6_CSL1_LocalHC1_0, M6_CSL1_Add4_X2a6_3_NotB); nand2 M6_CSL1_Add4_X2a6_3_Xo2(M6_CSL1_Add4_X2a6_3_NotA, M6_CSL1_LocalHC1_0, M6_CSL1_Add4_X2a6_3_line2); nand2 M6_CSL1_Add4_X2a6_3_Xo3(M6_CSL1_Add4_X2a6_3_NotB, M6_CSL1_Propbus_6, M6_CSL1_Add4_X2a6_3_line3); nand2 M6_CSL1_Add4_X2a6_3_Xo4(M6_CSL1_Add4_X2a6_3_line2, M6_CSL1_Add4_X2a6_3_line3, M6_CSL1_SumH01bus_3); inv M6_CSL1_Add4_X2a6_4_Xo0(M6_CSL1_Propbus_7, M6_CSL1_Add4_X2a6_4_NotA); inv M6_CSL1_Add4_X2a6_4_Xo1(M6_CSL1_LocalHC1_1, M6_CSL1_Add4_X2a6_4_NotB); nand2 M6_CSL1_Add4_X2a6_4_Xo2(M6_CSL1_Add4_X2a6_4_NotA, M6_CSL1_LocalHC1_1, M6_CSL1_Add4_X2a6_4_line2); nand2 M6_CSL1_Add4_X2a6_4_Xo3(M6_CSL1_Add4_X2a6_4_NotB, M6_CSL1_Propbus_7, M6_CSL1_Add4_X2a6_4_line3); nand2 M6_CSL1_Add4_X2a6_4_Xo4(M6_CSL1_Add4_X2a6_4_line2, M6_CSL1_Add4_X2a6_4_line3, M6_CSL1_SumH01bus_4); inv M6_CSL1_Add4_X2a6_5_Xo0(M6_CSL1_Propbus_8, M6_CSL1_Add4_X2a6_5_NotA); inv M6_CSL1_Add4_X2a6_5_Xo1(M6_CSL1_LocalHC1_2, M6_CSL1_Add4_X2a6_5_NotB); nand2 M6_CSL1_Add4_X2a6_5_Xo2(M6_CSL1_Add4_X2a6_5_NotA, M6_CSL1_LocalHC1_2, M6_CSL1_Add4_X2a6_5_line2); nand2 M6_CSL1_Add4_X2a6_5_Xo3(M6_CSL1_Add4_X2a6_5_NotB, M6_CSL1_Propbus_8, M6_CSL1_Add4_X2a6_5_line3); nand2 M6_CSL1_Add4_X2a6_5_Xo4(M6_CSL1_Add4_X2a6_5_line2, M6_CSL1_Add4_X2a6_5_line3, M6_CSL1_SumH01bus_5); inv M6_CSL1_Add5_Mux2_0(M6_CSL1_Carry_4, M6_CSL1_Add5_Not_ContIn); and2 M6_CSL1_Add5_Mux2_1(M6_CSL1_SumH01bus_0, M6_CSL1_Add5_Not_ContIn, M6_CSL1_Add5_line1); and2 M6_CSL1_Add5_Mux2_2(M6_CSL1_SumH01bus_3, M6_CSL1_Carry_4, M6_CSL1_Add5_line2); or2 M6_CSL1_Add5_Mux2_3(M6_CSL1_Add5_line1, M6_CSL1_Add5_line2, SumXbus_6); inv M6_CSL1_Add6_Mux2_0(M6_CSL1_Carry_4, M6_CSL1_Add6_Not_ContIn); and2 M6_CSL1_Add6_Mux2_1(M6_CSL1_SumH01bus_1, M6_CSL1_Add6_Not_ContIn, M6_CSL1_Add6_line1); and2 M6_CSL1_Add6_Mux2_2(M6_CSL1_SumH01bus_4, M6_CSL1_Carry_4, M6_CSL1_Add6_line2); or2 M6_CSL1_Add6_Mux2_3(M6_CSL1_Add6_line1, M6_CSL1_Add6_line2, SumXbus_7); inv M6_CSL1_Add7_Mux2_0(M6_CSL1_Carry_4, M6_CSL1_Add7_Not_ContIn); and2 M6_CSL1_Add7_Mux2_1(M6_CSL1_SumH01bus_2, M6_CSL1_Add7_Not_ContIn, M6_CSL1_Add7_line1); and2 M6_CSL1_Add7_Mux2_2(M6_CSL1_SumH01bus_5, M6_CSL1_Carry_4, M6_CSL1_Add7_line2); or2 M6_CSL1_Add7_Mux2_3(M6_CSL1_Add7_line1, M6_CSL1_Add7_line2, SumXbus_8); inv M6_CSL2_Mx9_0_Mx4_0_Mux4_0(in4092, M6_CSL2_Mx9_0_Mx4_0_Not_ContLo); inv M6_CSL2_Mx9_0_Mx4_0_Mux4_1(in4091, M6_CSL2_Mx9_0_Mx4_0_Not_ContHi); and3 M6_CSL2_Mx9_0_Mx4_0_Mux4_2(LogicXbus_0, M6_CSL2_Mx9_0_Mx4_0_Not_ContHi, M6_CSL2_Mx9_0_Mx4_0_Not_ContLo, M6_CSL2_Mx9_0_Mx4_0_line2); and3 M6_CSL2_Mx9_0_Mx4_0_Mux4_3(in131, M6_CSL2_Mx9_0_Mx4_0_Not_ContHi, in4092, M6_CSL2_Mx9_0_Mx4_0_line3); and3 M6_CSL2_Mx9_0_Mx4_0_Mux4_4(SumXbus_0, in4091, M6_CSL2_Mx9_0_Mx4_0_Not_ContLo, M6_CSL2_Mx9_0_Mx4_0_line4); and3 M6_CSL2_Mx9_0_Mx4_0_Mux4_5(gnd, in4091, in4092, M6_CSL2_Mx9_0_Mx4_0_line5); or4 M6_CSL2_Mx9_0_Mx4_0_Mux4_6(M6_CSL2_Mx9_0_Mx4_0_line2, M6_CSL2_Mx9_0_Mx4_0_line3, M6_CSL2_Mx9_0_Mx4_0_line4, M6_CSL2_Mx9_0_Mx4_0_line5, FXbus_0); inv M6_CSL2_Mx9_0_Mx4_1_Mux4_0(in4092, M6_CSL2_Mx9_0_Mx4_1_Not_ContLo); inv M6_CSL2_Mx9_0_Mx4_1_Mux4_1(in4091, M6_CSL2_Mx9_0_Mx4_1_Not_ContHi); and3 M6_CSL2_Mx9_0_Mx4_1_Mux4_2(LogicXbus_1, M6_CSL2_Mx9_0_Mx4_1_Not_ContHi, M6_CSL2_Mx9_0_Mx4_1_Not_ContLo, M6_CSL2_Mx9_0_Mx4_1_line2); and3 M6_CSL2_Mx9_0_Mx4_1_Mux4_3(in129, M6_CSL2_Mx9_0_Mx4_1_Not_ContHi, in4092, M6_CSL2_Mx9_0_Mx4_1_line3); and3 M6_CSL2_Mx9_0_Mx4_1_Mux4_4(SumXbus_1, in4091, M6_CSL2_Mx9_0_Mx4_1_Not_ContLo, M6_CSL2_Mx9_0_Mx4_1_line4); and3 M6_CSL2_Mx9_0_Mx4_1_Mux4_5(gnd, in4091, in4092, M6_CSL2_Mx9_0_Mx4_1_line5); or4 M6_CSL2_Mx9_0_Mx4_1_Mux4_6(M6_CSL2_Mx9_0_Mx4_1_line2, M6_CSL2_Mx9_0_Mx4_1_line3, M6_CSL2_Mx9_0_Mx4_1_line4, M6_CSL2_Mx9_0_Mx4_1_line5, FXbus_1); inv M6_CSL2_Mx9_0_Mx4_2_Mux4_0(in4092, M6_CSL2_Mx9_0_Mx4_2_Not_ContLo); inv M6_CSL2_Mx9_0_Mx4_2_Mux4_1(in4091, M6_CSL2_Mx9_0_Mx4_2_Not_ContHi); and3 M6_CSL2_Mx9_0_Mx4_2_Mux4_2(LogicXbus_2, M6_CSL2_Mx9_0_Mx4_2_Not_ContHi, M6_CSL2_Mx9_0_Mx4_2_Not_ContLo, M6_CSL2_Mx9_0_Mx4_2_line2); and3 M6_CSL2_Mx9_0_Mx4_2_Mux4_3(in119, M6_CSL2_Mx9_0_Mx4_2_Not_ContHi, in4092, M6_CSL2_Mx9_0_Mx4_2_line3); and3 M6_CSL2_Mx9_0_Mx4_2_Mux4_4(SumXbus_2, in4091, M6_CSL2_Mx9_0_Mx4_2_Not_ContLo, M6_CSL2_Mx9_0_Mx4_2_line4); and3 M6_CSL2_Mx9_0_Mx4_2_Mux4_5(gnd, in4091, in4092, M6_CSL2_Mx9_0_Mx4_2_line5); or4 M6_CSL2_Mx9_0_Mx4_2_Mux4_6(M6_CSL2_Mx9_0_Mx4_2_line2, M6_CSL2_Mx9_0_Mx4_2_line3, M6_CSL2_Mx9_0_Mx4_2_line4, M6_CSL2_Mx9_0_Mx4_2_line5, FXbus_2); inv M6_CSL2_Mx9_0_Mx4_3_Mux4_0(in4092, M6_CSL2_Mx9_0_Mx4_3_Not_ContLo); inv M6_CSL2_Mx9_0_Mx4_3_Mux4_1(in4091, M6_CSL2_Mx9_0_Mx4_3_Not_ContHi); and3 M6_CSL2_Mx9_0_Mx4_3_Mux4_2(LogicXbus_3, M6_CSL2_Mx9_0_Mx4_3_Not_ContHi, M6_CSL2_Mx9_0_Mx4_3_Not_ContLo, M6_CSL2_Mx9_0_Mx4_3_line2); and3 M6_CSL2_Mx9_0_Mx4_3_Mux4_3(in130, M6_CSL2_Mx9_0_Mx4_3_Not_ContHi, in4092, M6_CSL2_Mx9_0_Mx4_3_line3); and3 M6_CSL2_Mx9_0_Mx4_3_Mux4_4(SumXbus_3, in4091, M6_CSL2_Mx9_0_Mx4_3_Not_ContLo, M6_CSL2_Mx9_0_Mx4_3_line4); and3 M6_CSL2_Mx9_0_Mx4_3_Mux4_5(gnd, in4091, in4092, M6_CSL2_Mx9_0_Mx4_3_line5); or4 M6_CSL2_Mx9_0_Mx4_3_Mux4_6(M6_CSL2_Mx9_0_Mx4_3_line2, M6_CSL2_Mx9_0_Mx4_3_line3, M6_CSL2_Mx9_0_Mx4_3_line4, M6_CSL2_Mx9_0_Mx4_3_line5, FXbus_3); inv M6_CSL2_Mx9_1_Mx4_0_Mux4_0(in4092, M6_CSL2_Mx9_1_Mx4_0_Not_ContLo); inv M6_CSL2_Mx9_1_Mx4_0_Mux4_1(in4091, M6_CSL2_Mx9_1_Mx4_0_Not_ContHi); and3 M6_CSL2_Mx9_1_Mx4_0_Mux4_2(LogicXbus_4, M6_CSL2_Mx9_1_Mx4_0_Not_ContHi, M6_CSL2_Mx9_1_Mx4_0_Not_ContLo, M6_CSL2_Mx9_1_Mx4_0_line2); and3 M6_CSL2_Mx9_1_Mx4_0_Mux4_3(in52, M6_CSL2_Mx9_1_Mx4_0_Not_ContHi, in4092, M6_CSL2_Mx9_1_Mx4_0_line3); and3 M6_CSL2_Mx9_1_Mx4_0_Mux4_4(SumXbus_4, in4091, M6_CSL2_Mx9_1_Mx4_0_Not_ContLo, M6_CSL2_Mx9_1_Mx4_0_line4); and3 M6_CSL2_Mx9_1_Mx4_0_Mux4_5(gnd, in4091, in4092, M6_CSL2_Mx9_1_Mx4_0_line5); or4 M6_CSL2_Mx9_1_Mx4_0_Mux4_6(M6_CSL2_Mx9_1_Mx4_0_line2, M6_CSL2_Mx9_1_Mx4_0_line3, M6_CSL2_Mx9_1_Mx4_0_line4, M6_CSL2_Mx9_1_Mx4_0_line5, FXbus_4); inv M6_CSL2_Mx9_1_Mx4_1_Mux4_0(in4092, M6_CSL2_Mx9_1_Mx4_1_Not_ContLo); inv M6_CSL2_Mx9_1_Mx4_1_Mux4_1(in4091, M6_CSL2_Mx9_1_Mx4_1_Not_ContHi); and3 M6_CSL2_Mx9_1_Mx4_1_Mux4_2(LogicXbus_5, M6_CSL2_Mx9_1_Mx4_1_Not_ContHi, M6_CSL2_Mx9_1_Mx4_1_Not_ContLo, M6_CSL2_Mx9_1_Mx4_1_line2); and3 M6_CSL2_Mx9_1_Mx4_1_Mux4_3(in112, M6_CSL2_Mx9_1_Mx4_1_Not_ContHi, in4092, M6_CSL2_Mx9_1_Mx4_1_line3); and3 M6_CSL2_Mx9_1_Mx4_1_Mux4_4(SumXbus_5, in4091, M6_CSL2_Mx9_1_Mx4_1_Not_ContLo, M6_CSL2_Mx9_1_Mx4_1_line4); and3 M6_CSL2_Mx9_1_Mx4_1_Mux4_5(gnd, in4091, in4092, M6_CSL2_Mx9_1_Mx4_1_line5); or4 M6_CSL2_Mx9_1_Mx4_1_Mux4_6(M6_CSL2_Mx9_1_Mx4_1_line2, M6_CSL2_Mx9_1_Mx4_1_line3, M6_CSL2_Mx9_1_Mx4_1_line4, M6_CSL2_Mx9_1_Mx4_1_line5, FXbus_5); inv M6_CSL2_Mx9_1_Mx4_2_Mux4_0(in4092, M6_CSL2_Mx9_1_Mx4_2_Not_ContLo); inv M6_CSL2_Mx9_1_Mx4_2_Mux4_1(in4091, M6_CSL2_Mx9_1_Mx4_2_Not_ContHi); and3 M6_CSL2_Mx9_1_Mx4_2_Mux4_2(LogicXbus_6, M6_CSL2_Mx9_1_Mx4_2_Not_ContHi, M6_CSL2_Mx9_1_Mx4_2_Not_ContLo, M6_CSL2_Mx9_1_Mx4_2_line2); and3 M6_CSL2_Mx9_1_Mx4_2_Mux4_3(in116, M6_CSL2_Mx9_1_Mx4_2_Not_ContHi, in4092, M6_CSL2_Mx9_1_Mx4_2_line3); and3 M6_CSL2_Mx9_1_Mx4_2_Mux4_4(SumXbus_6, in4091, M6_CSL2_Mx9_1_Mx4_2_Not_ContLo, M6_CSL2_Mx9_1_Mx4_2_line4); and3 M6_CSL2_Mx9_1_Mx4_2_Mux4_5(gnd, in4091, in4092, M6_CSL2_Mx9_1_Mx4_2_line5); or4 M6_CSL2_Mx9_1_Mx4_2_Mux4_6(M6_CSL2_Mx9_1_Mx4_2_line2, M6_CSL2_Mx9_1_Mx4_2_line3, M6_CSL2_Mx9_1_Mx4_2_line4, M6_CSL2_Mx9_1_Mx4_2_line5, FXbus_6); inv M6_CSL2_Mx9_1_Mx4_3_Mux4_0(in4092, M6_CSL2_Mx9_1_Mx4_3_Not_ContLo); inv M6_CSL2_Mx9_1_Mx4_3_Mux4_1(in4091, M6_CSL2_Mx9_1_Mx4_3_Not_ContHi); and3 M6_CSL2_Mx9_1_Mx4_3_Mux4_2(LogicXbus_7, M6_CSL2_Mx9_1_Mx4_3_Not_ContHi, M6_CSL2_Mx9_1_Mx4_3_Not_ContLo, M6_CSL2_Mx9_1_Mx4_3_line2); and3 M6_CSL2_Mx9_1_Mx4_3_Mux4_3(in121, M6_CSL2_Mx9_1_Mx4_3_Not_ContHi, in4092, M6_CSL2_Mx9_1_Mx4_3_line3); and3 M6_CSL2_Mx9_1_Mx4_3_Mux4_4(SumXbus_7, in4091, M6_CSL2_Mx9_1_Mx4_3_Not_ContLo, M6_CSL2_Mx9_1_Mx4_3_line4); and3 M6_CSL2_Mx9_1_Mx4_3_Mux4_5(gnd, in4091, in4092, M6_CSL2_Mx9_1_Mx4_3_line5); or4 M6_CSL2_Mx9_1_Mx4_3_Mux4_6(M6_CSL2_Mx9_1_Mx4_3_line2, M6_CSL2_Mx9_1_Mx4_3_line3, M6_CSL2_Mx9_1_Mx4_3_line4, M6_CSL2_Mx9_1_Mx4_3_line5, FXbus_7); inv M6_CSL2_Mx9_2_Mux4_0(in4092, M6_CSL2_Mx9_2_Not_ContLo); inv M6_CSL2_Mx9_2_Mux4_1(in4091, M6_CSL2_Mx9_2_Not_ContHi); and3 M6_CSL2_Mx9_2_Mux4_2(LogicXbus_8, M6_CSL2_Mx9_2_Not_ContHi, M6_CSL2_Mx9_2_Not_ContLo, M6_CSL2_Mx9_2_line2); and3 M6_CSL2_Mx9_2_Mux4_3(in123, M6_CSL2_Mx9_2_Not_ContHi, in4092, M6_CSL2_Mx9_2_line3); and3 M6_CSL2_Mx9_2_Mux4_4(SumXbus_8, in4091, M6_CSL2_Mx9_2_Not_ContLo, M6_CSL2_Mx9_2_line4); and3 M6_CSL2_Mx9_2_Mux4_5(gnd, in4091, in4092, M6_CSL2_Mx9_2_line5); or4 M6_CSL2_Mx9_2_Mux4_6(M6_CSL2_Mx9_2_line2, M6_CSL2_Mx9_2_line3, M6_CSL2_Mx9_2_line4, M6_CSL2_Mx9_2_line5, FXbus_8); inv M7_CSL0_CL0_LB0_Mux2_0(in281, M7_CSL0_CL0_LB0_Not_ContIn); and2 M7_CSL0_CL0_LB0_Mux2_1(NotContLogic3_0_0, M7_CSL0_CL0_LB0_Not_ContIn, M7_CSL0_CL0_LB0_line1); and2 M7_CSL0_CL0_LB0_Mux2_2(NotContLogic3_0_1, in281, M7_CSL0_CL0_LB0_line2); or2 M7_CSL0_CL0_LB0_Mux2_3(M7_CSL0_CL0_LB0_line1, M7_CSL0_CL0_LB0_line2, M7_CSL0_CL0_line0); inv M7_CSL0_CL0_LB1_Mux2_0(in281, M7_CSL0_CL0_LB1_Not_ContIn); and2 M7_CSL0_CL0_LB1_Mux2_1(NotContLogic3_0_2, M7_CSL0_CL0_LB1_Not_ContIn, M7_CSL0_CL0_LB1_line1); and2 M7_CSL0_CL0_LB1_Mux2_2(NotContLogic3_0_3, in281, M7_CSL0_CL0_LB1_line2); or2 M7_CSL0_CL0_LB1_Mux2_3(M7_CSL0_CL0_LB1_line1, M7_CSL0_CL0_LB1_line2, M7_CSL0_CL0_line1); or2 M7_CSL0_CL0_LB2(in374, M7_CSL0_CL0_line0, M7_CSL0_CL0_line2); nand2 M7_CSL0_CL0_LB3(in374, M7_CSL0_CL0_line1, M7_CSL0_CL0_line3); and2 M7_CSL0_CL0_LB4(M7_CSL0_CL0_line2, M7_CSL0_CL0_line3, LogicYbus_0); inv M7_CSL0_CL1_LB0_Mux2_0(in273, M7_CSL0_CL1_LB0_Not_ContIn); and2 M7_CSL0_CL1_LB0_Mux2_1(NotContLogic3_0_0, M7_CSL0_CL1_LB0_Not_ContIn, M7_CSL0_CL1_LB0_line1); and2 M7_CSL0_CL1_LB0_Mux2_2(NotContLogic3_0_1, in273, M7_CSL0_CL1_LB0_line2); or2 M7_CSL0_CL1_LB0_Mux2_3(M7_CSL0_CL1_LB0_line1, M7_CSL0_CL1_LB0_line2, M7_CSL0_CL1_line0); inv M7_CSL0_CL1_LB1_Mux2_0(in273, M7_CSL0_CL1_LB1_Not_ContIn); and2 M7_CSL0_CL1_LB1_Mux2_1(NotContLogic3_0_2, M7_CSL0_CL1_LB1_Not_ContIn, M7_CSL0_CL1_LB1_line1); and2 M7_CSL0_CL1_LB1_Mux2_2(NotContLogic3_0_3, in273, M7_CSL0_CL1_LB1_line2); or2 M7_CSL0_CL1_LB1_Mux2_3(M7_CSL0_CL1_LB1_line1, M7_CSL0_CL1_LB1_line2, M7_CSL0_CL1_line1); or2 M7_CSL0_CL1_LB2(in411, M7_CSL0_CL1_line0, M7_CSL0_CL1_line2); nand2 M7_CSL0_CL1_LB3(in411, M7_CSL0_CL1_line1, M7_CSL0_CL1_line3); and2 M7_CSL0_CL1_LB4(M7_CSL0_CL1_line2, M7_CSL0_CL1_line3, LogicYbus_1); inv M7_CSL0_CL2_LB0_Mux2_0(in265, M7_CSL0_CL2_LB0_Not_ContIn); and2 M7_CSL0_CL2_LB0_Mux2_1(NotContLogic3_0_0, M7_CSL0_CL2_LB0_Not_ContIn, M7_CSL0_CL2_LB0_line1); and2 M7_CSL0_CL2_LB0_Mux2_2(NotContLogic3_0_1, in265, M7_CSL0_CL2_LB0_line2); or2 M7_CSL0_CL2_LB0_Mux2_3(M7_CSL0_CL2_LB0_line1, M7_CSL0_CL2_LB0_line2, M7_CSL0_CL2_line0); inv M7_CSL0_CL2_LB1_Mux2_0(in265, M7_CSL0_CL2_LB1_Not_ContIn); and2 M7_CSL0_CL2_LB1_Mux2_1(NotContLogic3_0_2, M7_CSL0_CL2_LB1_Not_ContIn, M7_CSL0_CL2_LB1_line1); and2 M7_CSL0_CL2_LB1_Mux2_2(NotContLogic3_0_3, in265, M7_CSL0_CL2_LB1_line2); or2 M7_CSL0_CL2_LB1_Mux2_3(M7_CSL0_CL2_LB1_line1, M7_CSL0_CL2_LB1_line2, M7_CSL0_CL2_line1); or2 M7_CSL0_CL2_LB2(in400, M7_CSL0_CL2_line0, M7_CSL0_CL2_line2); nand2 M7_CSL0_CL2_LB3(in400, M7_CSL0_CL2_line1, M7_CSL0_CL2_line3); and2 M7_CSL0_CL2_LB4(M7_CSL0_CL2_line2, M7_CSL0_CL2_line3, LogicYbus_2); inv M7_CSL0_CL3_LB0_Mux2_0(in257, M7_CSL0_CL3_LB0_Not_ContIn); and2 M7_CSL0_CL3_LB0_Mux2_1(NotContLogic3_0_0, M7_CSL0_CL3_LB0_Not_ContIn, M7_CSL0_CL3_LB0_line1); and2 M7_CSL0_CL3_LB0_Mux2_2(NotContLogic3_0_1, in257, M7_CSL0_CL3_LB0_line2); or2 M7_CSL0_CL3_LB0_Mux2_3(M7_CSL0_CL3_LB0_line1, M7_CSL0_CL3_LB0_line2, M7_CSL0_CL3_line0); inv M7_CSL0_CL3_LB1_Mux2_0(in257, M7_CSL0_CL3_LB1_Not_ContIn); and2 M7_CSL0_CL3_LB1_Mux2_1(NotContLogic3_0_2, M7_CSL0_CL3_LB1_Not_ContIn, M7_CSL0_CL3_LB1_line1); and2 M7_CSL0_CL3_LB1_Mux2_2(NotContLogic3_0_3, in257, M7_CSL0_CL3_LB1_line2); or2 M7_CSL0_CL3_LB1_Mux2_3(M7_CSL0_CL3_LB1_line1, M7_CSL0_CL3_LB1_line2, M7_CSL0_CL3_line1); or2 M7_CSL0_CL3_LB2(in389, M7_CSL0_CL3_line0, M7_CSL0_CL3_line2); nand2 M7_CSL0_CL3_LB3(in389, M7_CSL0_CL3_line1, M7_CSL0_CL3_line3); and2 M7_CSL0_CL3_LB4(M7_CSL0_CL3_line2, M7_CSL0_CL3_line3, LogicYbus_3); inv M7_CSL0_CL4_LB0_Mux2_0(in234, M7_CSL0_CL4_LB0_Not_ContIn); and2 M7_CSL0_CL4_LB0_Mux2_1(NotContLogic3_0_0, M7_CSL0_CL4_LB0_Not_ContIn, M7_CSL0_CL4_LB0_line1); and2 M7_CSL0_CL4_LB0_Mux2_2(NotContLogic3_0_1, in234, M7_CSL0_CL4_LB0_line2); or2 M7_CSL0_CL4_LB0_Mux2_3(M7_CSL0_CL4_LB0_line1, M7_CSL0_CL4_LB0_line2, M7_CSL0_CL4_line0); inv M7_CSL0_CL4_LB1_Mux2_0(in234, M7_CSL0_CL4_LB1_Not_ContIn); and2 M7_CSL0_CL4_LB1_Mux2_1(NotContLogic3_0_2, M7_CSL0_CL4_LB1_Not_ContIn, M7_CSL0_CL4_LB1_line1); and2 M7_CSL0_CL4_LB1_Mux2_2(NotContLogic3_0_3, in234, M7_CSL0_CL4_LB1_line2); or2 M7_CSL0_CL4_LB1_Mux2_3(M7_CSL0_CL4_LB1_line1, M7_CSL0_CL4_LB1_line2, M7_CSL0_CL4_line1); or2 M7_CSL0_CL4_LB2(in435, M7_CSL0_CL4_line0, M7_CSL0_CL4_line2); nand2 M7_CSL0_CL4_LB3(in435, M7_CSL0_CL4_line1, M7_CSL0_CL4_line3); and2 M7_CSL0_CL4_LB4(M7_CSL0_CL4_line2, M7_CSL0_CL4_line3, LogicYbus_4); inv M7_CSL0_CL5_LB0_Mux2_0(in226, M7_CSL0_CL5_LB0_Not_ContIn); and2 M7_CSL0_CL5_LB0_Mux2_1(NotContLogic3_0_0, M7_CSL0_CL5_LB0_Not_ContIn, M7_CSL0_CL5_LB0_line1); and2 M7_CSL0_CL5_LB0_Mux2_2(NotContLogic3_0_1, in226, M7_CSL0_CL5_LB0_line2); or2 M7_CSL0_CL5_LB0_Mux2_3(M7_CSL0_CL5_LB0_line1, M7_CSL0_CL5_LB0_line2, M7_CSL0_CL5_line0); inv M7_CSL0_CL5_LB1_Mux2_0(in226, M7_CSL0_CL5_LB1_Not_ContIn); and2 M7_CSL0_CL5_LB1_Mux2_1(NotContLogic3_0_2, M7_CSL0_CL5_LB1_Not_ContIn, M7_CSL0_CL5_LB1_line1); and2 M7_CSL0_CL5_LB1_Mux2_2(NotContLogic3_0_3, in226, M7_CSL0_CL5_LB1_line2); or2 M7_CSL0_CL5_LB1_Mux2_3(M7_CSL0_CL5_LB1_line1, M7_CSL0_CL5_LB1_line2, M7_CSL0_CL5_line1); or2 M7_CSL0_CL5_LB2(in422, M7_CSL0_CL5_line0, M7_CSL0_CL5_line2); nand2 M7_CSL0_CL5_LB3(in422, M7_CSL0_CL5_line1, M7_CSL0_CL5_line3); and2 M7_CSL0_CL5_LB4(M7_CSL0_CL5_line2, M7_CSL0_CL5_line3, LogicYbus_5); inv M7_CSL0_CL6_LB0_Mux2_0(in218, M7_CSL0_CL6_LB0_Not_ContIn); and2 M7_CSL0_CL6_LB0_Mux2_1(NotContLogic3_0_0, M7_CSL0_CL6_LB0_Not_ContIn, M7_CSL0_CL6_LB0_line1); and2 M7_CSL0_CL6_LB0_Mux2_2(NotContLogic3_0_1, in218, M7_CSL0_CL6_LB0_line2); or2 M7_CSL0_CL6_LB0_Mux2_3(M7_CSL0_CL6_LB0_line1, M7_CSL0_CL6_LB0_line2, M7_CSL0_CL6_line0); inv M7_CSL0_CL6_LB1_Mux2_0(in218, M7_CSL0_CL6_LB1_Not_ContIn); and2 M7_CSL0_CL6_LB1_Mux2_1(NotContLogic3_0_2, M7_CSL0_CL6_LB1_Not_ContIn, M7_CSL0_CL6_LB1_line1); and2 M7_CSL0_CL6_LB1_Mux2_2(NotContLogic3_0_3, in218, M7_CSL0_CL6_LB1_line2); or2 M7_CSL0_CL6_LB1_Mux2_3(M7_CSL0_CL6_LB1_line1, M7_CSL0_CL6_LB1_line2, M7_CSL0_CL6_line1); or2 M7_CSL0_CL6_LB2(in468, M7_CSL0_CL6_line0, M7_CSL0_CL6_line2); nand2 M7_CSL0_CL6_LB3(in468, M7_CSL0_CL6_line1, M7_CSL0_CL6_line3); and2 M7_CSL0_CL6_LB4(M7_CSL0_CL6_line2, M7_CSL0_CL6_line3, LogicYbus_6); inv M7_CSL0_CL7_LB0_Mux2_0(in210, M7_CSL0_CL7_LB0_Not_ContIn); and2 M7_CSL0_CL7_LB0_Mux2_1(NotContLogic3_0_0, M7_CSL0_CL7_LB0_Not_ContIn, M7_CSL0_CL7_LB0_line1); and2 M7_CSL0_CL7_LB0_Mux2_2(NotContLogic3_0_1, in210, M7_CSL0_CL7_LB0_line2); or2 M7_CSL0_CL7_LB0_Mux2_3(M7_CSL0_CL7_LB0_line1, M7_CSL0_CL7_LB0_line2, M7_CSL0_CL7_line0); inv M7_CSL0_CL7_LB1_Mux2_0(in210, M7_CSL0_CL7_LB1_Not_ContIn); and2 M7_CSL0_CL7_LB1_Mux2_1(NotContLogic3_0_2, M7_CSL0_CL7_LB1_Not_ContIn, M7_CSL0_CL7_LB1_line1); and2 M7_CSL0_CL7_LB1_Mux2_2(NotContLogic3_0_3, in210, M7_CSL0_CL7_LB1_line2); or2 M7_CSL0_CL7_LB1_Mux2_3(M7_CSL0_CL7_LB1_line1, M7_CSL0_CL7_LB1_line2, M7_CSL0_CL7_line1); or2 M7_CSL0_CL7_LB2(in457, M7_CSL0_CL7_line0, M7_CSL0_CL7_line2); nand2 M7_CSL0_CL7_LB3(in457, M7_CSL0_CL7_line1, M7_CSL0_CL7_line3); and2 M7_CSL0_CL7_LB4(M7_CSL0_CL7_line2, M7_CSL0_CL7_line3, LogicYbus_7); inv M7_CSL0_CL8_LB0_Mux2_0(in206, M7_CSL0_CL8_LB0_Not_ContIn); and2 M7_CSL0_CL8_LB0_Mux2_1(in254, M7_CSL0_CL8_LB0_Not_ContIn, M7_CSL0_CL8_LB0_line1); and2 M7_CSL0_CL8_LB0_Mux2_2(in242, in206, M7_CSL0_CL8_LB0_line2); or2 M7_CSL0_CL8_LB0_Mux2_3(M7_CSL0_CL8_LB0_line1, M7_CSL0_CL8_LB0_line2, M7_CSL0_CL8_line0); inv M7_CSL0_CL8_LB1_Mux2_0(in206, M7_CSL0_CL8_LB1_Not_ContIn); and2 M7_CSL0_CL8_LB1_Mux2_1(in251, M7_CSL0_CL8_LB1_Not_ContIn, M7_CSL0_CL8_LB1_line1); and2 M7_CSL0_CL8_LB1_Mux2_2(in248, in206, M7_CSL0_CL8_LB1_line2); or2 M7_CSL0_CL8_LB1_Mux2_3(M7_CSL0_CL8_LB1_line1, M7_CSL0_CL8_LB1_line2, M7_CSL0_CL8_line1); or2 M7_CSL0_CL8_LB2(in446, M7_CSL0_CL8_line0, M7_CSL0_CL8_line2); nand2 M7_CSL0_CL8_LB3(in446, M7_CSL0_CL8_line1, M7_CSL0_CL8_line3); and2 M7_CSL0_CL8_LB4(M7_CSL0_CL8_line2, M7_CSL0_CL8_line3, LogicYbus_8); and2 M7_CSL1_Add0_GP9_0(Ybus_0, in374, M7_CSL1_Genbus_0); and2 M7_CSL1_Add0_GP9_1(Ybus_1, in411, M7_CSL1_Genbus_1); and2 M7_CSL1_Add0_GP9_2(Ybus_2, in400, M7_CSL1_Genbus_2); and2 M7_CSL1_Add0_GP9_3(Ybus_3, in389, M7_CSL1_Genbus_3); and2 M7_CSL1_Add0_GP9_4(Ybus_4, in435, M7_CSL1_Genbus_4); and2 M7_CSL1_Add0_GP9_5(Ybus_5, in422, M7_CSL1_Genbus_5); and2 M7_CSL1_Add0_GP9_6(Ybus_6, in468, M7_CSL1_Genbus_6); and2 M7_CSL1_Add0_GP9_7(Ybus_7, in457, M7_CSL1_Genbus_7); and2 M7_CSL1_Add0_GP9_8(Ybus_8, in446, M7_CSL1_Genbus_8); inv M7_CSL1_Add0_GP9_9_Xo0(Ybus_0, M7_CSL1_Add0_GP9_9_NotA); inv M7_CSL1_Add0_GP9_9_Xo1(in374, M7_CSL1_Add0_GP9_9_NotB); nand2 M7_CSL1_Add0_GP9_9_Xo2(M7_CSL1_Add0_GP9_9_NotA, in374, M7_CSL1_Add0_GP9_9_line2); nand2 M7_CSL1_Add0_GP9_9_Xo3(M7_CSL1_Add0_GP9_9_NotB, Ybus_0, M7_CSL1_Add0_GP9_9_line3); nand2 M7_CSL1_Add0_GP9_9_Xo4(M7_CSL1_Add0_GP9_9_line2, M7_CSL1_Add0_GP9_9_line3, M7_CSL1_Propbus_0); inv M7_CSL1_Add0_GP9_10_Xo0(Ybus_1, M7_CSL1_Add0_GP9_10_NotA); inv M7_CSL1_Add0_GP9_10_Xo1(in411, M7_CSL1_Add0_GP9_10_NotB); nand2 M7_CSL1_Add0_GP9_10_Xo2(M7_CSL1_Add0_GP9_10_NotA, in411, M7_CSL1_Add0_GP9_10_line2); nand2 M7_CSL1_Add0_GP9_10_Xo3(M7_CSL1_Add0_GP9_10_NotB, Ybus_1, M7_CSL1_Add0_GP9_10_line3); nand2 M7_CSL1_Add0_GP9_10_Xo4(M7_CSL1_Add0_GP9_10_line2, M7_CSL1_Add0_GP9_10_line3, M7_CSL1_Propbus_1); inv M7_CSL1_Add0_GP9_11_Xo0(Ybus_2, M7_CSL1_Add0_GP9_11_NotA); inv M7_CSL1_Add0_GP9_11_Xo1(in400, M7_CSL1_Add0_GP9_11_NotB); nand2 M7_CSL1_Add0_GP9_11_Xo2(M7_CSL1_Add0_GP9_11_NotA, in400, M7_CSL1_Add0_GP9_11_line2); nand2 M7_CSL1_Add0_GP9_11_Xo3(M7_CSL1_Add0_GP9_11_NotB, Ybus_2, M7_CSL1_Add0_GP9_11_line3); nand2 M7_CSL1_Add0_GP9_11_Xo4(M7_CSL1_Add0_GP9_11_line2, M7_CSL1_Add0_GP9_11_line3, M7_CSL1_Propbus_2); inv M7_CSL1_Add0_GP9_12_Xo0(Ybus_3, M7_CSL1_Add0_GP9_12_NotA); inv M7_CSL1_Add0_GP9_12_Xo1(in389, M7_CSL1_Add0_GP9_12_NotB); nand2 M7_CSL1_Add0_GP9_12_Xo2(M7_CSL1_Add0_GP9_12_NotA, in389, M7_CSL1_Add0_GP9_12_line2); nand2 M7_CSL1_Add0_GP9_12_Xo3(M7_CSL1_Add0_GP9_12_NotB, Ybus_3, M7_CSL1_Add0_GP9_12_line3); nand2 M7_CSL1_Add0_GP9_12_Xo4(M7_CSL1_Add0_GP9_12_line2, M7_CSL1_Add0_GP9_12_line3, M7_CSL1_Propbus_3); inv M7_CSL1_Add0_GP9_13_Xo0(Ybus_4, M7_CSL1_Add0_GP9_13_NotA); inv M7_CSL1_Add0_GP9_13_Xo1(in435, M7_CSL1_Add0_GP9_13_NotB); nand2 M7_CSL1_Add0_GP9_13_Xo2(M7_CSL1_Add0_GP9_13_NotA, in435, M7_CSL1_Add0_GP9_13_line2); nand2 M7_CSL1_Add0_GP9_13_Xo3(M7_CSL1_Add0_GP9_13_NotB, Ybus_4, M7_CSL1_Add0_GP9_13_line3); nand2 M7_CSL1_Add0_GP9_13_Xo4(M7_CSL1_Add0_GP9_13_line2, M7_CSL1_Add0_GP9_13_line3, M7_CSL1_Propbus_4); inv M7_CSL1_Add0_GP9_14_Xo0(Ybus_5, M7_CSL1_Add0_GP9_14_NotA); inv M7_CSL1_Add0_GP9_14_Xo1(in422, M7_CSL1_Add0_GP9_14_NotB); nand2 M7_CSL1_Add0_GP9_14_Xo2(M7_CSL1_Add0_GP9_14_NotA, in422, M7_CSL1_Add0_GP9_14_line2); nand2 M7_CSL1_Add0_GP9_14_Xo3(M7_CSL1_Add0_GP9_14_NotB, Ybus_5, M7_CSL1_Add0_GP9_14_line3); nand2 M7_CSL1_Add0_GP9_14_Xo4(M7_CSL1_Add0_GP9_14_line2, M7_CSL1_Add0_GP9_14_line3, M7_CSL1_Propbus_5); inv M7_CSL1_Add0_GP9_15_Xo0(Ybus_6, M7_CSL1_Add0_GP9_15_NotA); inv M7_CSL1_Add0_GP9_15_Xo1(in468, M7_CSL1_Add0_GP9_15_NotB); nand2 M7_CSL1_Add0_GP9_15_Xo2(M7_CSL1_Add0_GP9_15_NotA, in468, M7_CSL1_Add0_GP9_15_line2); nand2 M7_CSL1_Add0_GP9_15_Xo3(M7_CSL1_Add0_GP9_15_NotB, Ybus_6, M7_CSL1_Add0_GP9_15_line3); nand2 M7_CSL1_Add0_GP9_15_Xo4(M7_CSL1_Add0_GP9_15_line2, M7_CSL1_Add0_GP9_15_line3, M7_CSL1_Propbus_6); inv M7_CSL1_Add0_GP9_16_Xo0(Ybus_7, M7_CSL1_Add0_GP9_16_NotA); inv M7_CSL1_Add0_GP9_16_Xo1(in457, M7_CSL1_Add0_GP9_16_NotB); nand2 M7_CSL1_Add0_GP9_16_Xo2(M7_CSL1_Add0_GP9_16_NotA, in457, M7_CSL1_Add0_GP9_16_line2); nand2 M7_CSL1_Add0_GP9_16_Xo3(M7_CSL1_Add0_GP9_16_NotB, Ybus_7, M7_CSL1_Add0_GP9_16_line3); nand2 M7_CSL1_Add0_GP9_16_Xo4(M7_CSL1_Add0_GP9_16_line2, M7_CSL1_Add0_GP9_16_line3, M7_CSL1_Propbus_7); inv M7_CSL1_Add0_GP9_17_Xo0(Ybus_8, M7_CSL1_Add0_GP9_17_NotA); inv M7_CSL1_Add0_GP9_17_Xo1(in446, M7_CSL1_Add0_GP9_17_NotB); nand2 M7_CSL1_Add0_GP9_17_Xo2(M7_CSL1_Add0_GP9_17_NotA, in446, M7_CSL1_Add0_GP9_17_line2); nand2 M7_CSL1_Add0_GP9_17_Xo3(M7_CSL1_Add0_GP9_17_NotB, Ybus_8, M7_CSL1_Add0_GP9_17_line3); nand2 M7_CSL1_Add0_GP9_17_Xo4(M7_CSL1_Add0_GP9_17_line2, M7_CSL1_Add0_GP9_17_line3, M7_CSL1_Propbus_8); and2 M7_CSL1_Add1_CB0_Ao2_0(M7_CSL1_Propbus_0, in4, M7_CSL1_Add1_CB0_line0); or2 M7_CSL1_Add1_CB0_Ao2_1(M7_CSL1_Genbus_0, M7_CSL1_Add1_CB0_line0, M7_CSL1_Carry_0); and2 M7_CSL1_Add1_CB1_Ao3a_0(M7_CSL1_Propbus_1, M7_CSL1_Genbus_0, M7_CSL1_Add1_CB1_line0); and3 M7_CSL1_Add1_CB1_Ao3a_1(M7_CSL1_Propbus_1, M7_CSL1_Propbus_0, in4, M7_CSL1_Add1_CB1_line1); or3 M7_CSL1_Add1_CB1_Ao3a_2(M7_CSL1_Genbus_1, M7_CSL1_Add1_CB1_line0, M7_CSL1_Add1_CB1_line1, M7_CSL1_Carry_1); and2 M7_CSL1_Add1_CB2_Ao4a_0(M7_CSL1_Propbus_2, M7_CSL1_Genbus_1, M7_CSL1_Add1_CB2_line0); and3 M7_CSL1_Add1_CB2_Ao4a_1(M7_CSL1_Propbus_2, M7_CSL1_Propbus_1, M7_CSL1_Genbus_0, M7_CSL1_Add1_CB2_line1); and4 M7_CSL1_Add1_CB2_Ao4a_2(M7_CSL1_Propbus_2, M7_CSL1_Propbus_1, M7_CSL1_Propbus_0, in4, M7_CSL1_Add1_CB2_line2); or4 M7_CSL1_Add1_CB2_Ao4a_3(M7_CSL1_Genbus_2, M7_CSL1_Add1_CB2_line0, M7_CSL1_Add1_CB2_line1, M7_CSL1_Add1_CB2_line2, M7_CSL1_Carry_2); and2 M7_CSL1_Add1_CB3_Ao5a_0(M7_CSL1_Propbus_3, M7_CSL1_Genbus_2, M7_CSL1_Add1_CB3_line0); and3 M7_CSL1_Add1_CB3_Ao5a_1(M7_CSL1_Propbus_3, M7_CSL1_Propbus_2, M7_CSL1_Genbus_1, M7_CSL1_Add1_CB3_line1); and4 M7_CSL1_Add1_CB3_Ao5a_2(M7_CSL1_Propbus_3, M7_CSL1_Propbus_2, M7_CSL1_Propbus_1, M7_CSL1_Genbus_0, M7_CSL1_Add1_CB3_line2); and5 M7_CSL1_Add1_CB3_Ao5a_3(M7_CSL1_Propbus_3, M7_CSL1_Propbus_2, M7_CSL1_Propbus_1, M7_CSL1_Propbus_0, in4, M7_CSL1_Add1_CB3_line3); or5 M7_CSL1_Add1_CB3_Ao5a_4(M7_CSL1_Genbus_3, M7_CSL1_Add1_CB3_line0, M7_CSL1_Add1_CB3_line1, M7_CSL1_Add1_CB3_line2, M7_CSL1_Add1_CB3_line3, M7_CSL1_Carry_3); and2 M7_CSL1_Add1_CB4_Ao5a_0(M7_CSL1_Propbus_4, M7_CSL1_Genbus_3, M7_CSL1_Add1_CB4_line0); and3 M7_CSL1_Add1_CB4_Ao5a_1(M7_CSL1_Propbus_4, M7_CSL1_Propbus_3, M7_CSL1_Genbus_2, M7_CSL1_Add1_CB4_line1); and4 M7_CSL1_Add1_CB4_Ao5a_2(M7_CSL1_Propbus_4, M7_CSL1_Propbus_3, M7_CSL1_Propbus_2, M7_CSL1_Genbus_1, M7_CSL1_Add1_CB4_line2); and5 M7_CSL1_Add1_CB4_Ao5a_3(M7_CSL1_Propbus_4, M7_CSL1_Propbus_3, M7_CSL1_Propbus_2, M7_CSL1_Propbus_1, M7_CSL1_Genbus_0, M7_CSL1_Add1_CB4_line3); or5 M7_CSL1_Add1_CB4_Ao5a_4(M7_CSL1_Genbus_4, M7_CSL1_Add1_CB4_line0, M7_CSL1_Add1_CB4_line1, M7_CSL1_Add1_CB4_line2, M7_CSL1_Add1_CB4_line3, M7_CSL1_Add1_LocalC0_4); and5 M7_CSL1_Add1_CB5(M7_CSL1_Propbus_0, M7_CSL1_Propbus_1, M7_CSL1_Propbus_2, M7_CSL1_Propbus_3, M7_CSL1_Propbus_4, M7_CSL1_Add1_Prop4_0); and2 M7_CSL1_Add1_CB6(in4, M7_CSL1_Add1_Prop4_0, M7_CSL1_Add1_PropCin); or2 M7_CSL1_Add1_CB7(M7_CSL1_Add1_LocalC0_4, M7_CSL1_Add1_PropCin, M7_CSL1_Carry_4); and2 M7_CSL1_Add1_CB8_Ao5a_0(M7_CSL1_Propbus_8, M7_CSL1_Genbus_7, M7_CSL1_Add1_CB8_line0); and3 M7_CSL1_Add1_CB8_Ao5a_1(M7_CSL1_Propbus_8, M7_CSL1_Propbus_7, M7_CSL1_Genbus_6, M7_CSL1_Add1_CB8_line1); and4 M7_CSL1_Add1_CB8_Ao5a_2(M7_CSL1_Propbus_8, M7_CSL1_Propbus_7, M7_CSL1_Propbus_6, M7_CSL1_Genbus_5, M7_CSL1_Add1_CB8_line2); and5 M7_CSL1_Add1_CB8_Ao5a_3(M7_CSL1_Propbus_8, M7_CSL1_Propbus_7, M7_CSL1_Propbus_6, M7_CSL1_Propbus_5, M7_CSL1_Add1_LocalC0_4, M7_CSL1_Add1_CB8_line3); or5 M7_CSL1_Add1_CB8_Ao5a_4(M7_CSL1_Genbus_8, M7_CSL1_Add1_CB8_line0, M7_CSL1_Add1_CB8_line1, M7_CSL1_Add1_CB8_line2, M7_CSL1_Add1_CB8_line3, out591); and4 M7_CSL1_Add1_CB9(M7_CSL1_Propbus_5, M7_CSL1_Propbus_6, M7_CSL1_Propbus_7, M7_CSL1_Propbus_8, M7_CSL1_Add1_Prop8_5); and2 M7_CSL1_Add1_CB10(M7_CSL1_Add1_Prop4_0, M7_CSL1_Add1_Prop8_5, out588); or2 M7_CSL1_Add2_GLC4_0(M7_CSL1_Genbus_5, M7_CSL1_Propbus_5, M7_CSL1_LocalHC1_0); and2 M7_CSL1_Add2_GLC4_1_Ao2_0(M7_CSL1_Propbus_6, M7_CSL1_Genbus_5, M7_CSL1_Add2_GLC4_1_line0); or2 M7_CSL1_Add2_GLC4_1_Ao2_1(M7_CSL1_Genbus_6, M7_CSL1_Add2_GLC4_1_line0, M7_CSL1_LocalHC0_1); and2 M7_CSL1_Add2_GLC4_2_Ao3a_0(M7_CSL1_Propbus_6, M7_CSL1_Genbus_5, M7_CSL1_Add2_GLC4_2_line0); and2 M7_CSL1_Add2_GLC4_2_Ao3a_1(M7_CSL1_Propbus_6, M7_CSL1_Propbus_5, M7_CSL1_Add2_GLC4_2_line1); or3 M7_CSL1_Add2_GLC4_2_Ao3a_2(M7_CSL1_Genbus_6, M7_CSL1_Add2_GLC4_2_line0, M7_CSL1_Add2_GLC4_2_line1, M7_CSL1_LocalHC1_1); and2 M7_CSL1_Add2_GLC4_3_Ao3a_0(M7_CSL1_Propbus_7, M7_CSL1_Genbus_6, M7_CSL1_Add2_GLC4_3_line0); and3 M7_CSL1_Add2_GLC4_3_Ao3a_1(M7_CSL1_Propbus_7, M7_CSL1_Propbus_6, M7_CSL1_Genbus_5, M7_CSL1_Add2_GLC4_3_line1); or3 M7_CSL1_Add2_GLC4_3_Ao3a_2(M7_CSL1_Genbus_7, M7_CSL1_Add2_GLC4_3_line0, M7_CSL1_Add2_GLC4_3_line1, M7_CSL1_LocalHC0_2); and2 M7_CSL1_Add2_GLC4_4_Ao4a_0(M7_CSL1_Propbus_7, M7_CSL1_Genbus_6, M7_CSL1_Add2_GLC4_4_line0); and3 M7_CSL1_Add2_GLC4_4_Ao4a_1(M7_CSL1_Propbus_7, M7_CSL1_Propbus_6, M7_CSL1_Genbus_5, M7_CSL1_Add2_GLC4_4_line1); and3 M7_CSL1_Add2_GLC4_4_Ao4a_2(M7_CSL1_Propbus_7, M7_CSL1_Propbus_6, M7_CSL1_Propbus_5, M7_CSL1_Add2_GLC4_4_line2); or4 M7_CSL1_Add2_GLC4_4_Ao4a_3(M7_CSL1_Genbus_7, M7_CSL1_Add2_GLC4_4_line0, M7_CSL1_Add2_GLC4_4_line1, M7_CSL1_Add2_GLC4_4_line2, M7_CSL1_LocalHC1_2); inv M7_CSL1_Add3_X2a6_0_Xo0(M7_CSL1_Propbus_0, M7_CSL1_Add3_X2a6_0_NotA); inv M7_CSL1_Add3_X2a6_0_Xo1(in4, M7_CSL1_Add3_X2a6_0_NotB); nand2 M7_CSL1_Add3_X2a6_0_Xo2(M7_CSL1_Add3_X2a6_0_NotA, in4, M7_CSL1_Add3_X2a6_0_line2); nand2 M7_CSL1_Add3_X2a6_0_Xo3(M7_CSL1_Add3_X2a6_0_NotB, M7_CSL1_Propbus_0, M7_CSL1_Add3_X2a6_0_line3); nand2 M7_CSL1_Add3_X2a6_0_Xo4(M7_CSL1_Add3_X2a6_0_line2, M7_CSL1_Add3_X2a6_0_line3, SumYbus_0); inv M7_CSL1_Add3_X2a6_1_Xo0(M7_CSL1_Propbus_1, M7_CSL1_Add3_X2a6_1_NotA); inv M7_CSL1_Add3_X2a6_1_Xo1(M7_CSL1_Carry_0, M7_CSL1_Add3_X2a6_1_NotB); nand2 M7_CSL1_Add3_X2a6_1_Xo2(M7_CSL1_Add3_X2a6_1_NotA, M7_CSL1_Carry_0, M7_CSL1_Add3_X2a6_1_line2); nand2 M7_CSL1_Add3_X2a6_1_Xo3(M7_CSL1_Add3_X2a6_1_NotB, M7_CSL1_Propbus_1, M7_CSL1_Add3_X2a6_1_line3); nand2 M7_CSL1_Add3_X2a6_1_Xo4(M7_CSL1_Add3_X2a6_1_line2, M7_CSL1_Add3_X2a6_1_line3, SumYbus_1); inv M7_CSL1_Add3_X2a6_2_Xo0(M7_CSL1_Propbus_2, M7_CSL1_Add3_X2a6_2_NotA); inv M7_CSL1_Add3_X2a6_2_Xo1(M7_CSL1_Carry_1, M7_CSL1_Add3_X2a6_2_NotB); nand2 M7_CSL1_Add3_X2a6_2_Xo2(M7_CSL1_Add3_X2a6_2_NotA, M7_CSL1_Carry_1, M7_CSL1_Add3_X2a6_2_line2); nand2 M7_CSL1_Add3_X2a6_2_Xo3(M7_CSL1_Add3_X2a6_2_NotB, M7_CSL1_Propbus_2, M7_CSL1_Add3_X2a6_2_line3); nand2 M7_CSL1_Add3_X2a6_2_Xo4(M7_CSL1_Add3_X2a6_2_line2, M7_CSL1_Add3_X2a6_2_line3, SumYbus_2); inv M7_CSL1_Add3_X2a6_3_Xo0(M7_CSL1_Propbus_3, M7_CSL1_Add3_X2a6_3_NotA); inv M7_CSL1_Add3_X2a6_3_Xo1(M7_CSL1_Carry_2, M7_CSL1_Add3_X2a6_3_NotB); nand2 M7_CSL1_Add3_X2a6_3_Xo2(M7_CSL1_Add3_X2a6_3_NotA, M7_CSL1_Carry_2, M7_CSL1_Add3_X2a6_3_line2); nand2 M7_CSL1_Add3_X2a6_3_Xo3(M7_CSL1_Add3_X2a6_3_NotB, M7_CSL1_Propbus_3, M7_CSL1_Add3_X2a6_3_line3); nand2 M7_CSL1_Add3_X2a6_3_Xo4(M7_CSL1_Add3_X2a6_3_line2, M7_CSL1_Add3_X2a6_3_line3, SumYbus_3); inv M7_CSL1_Add3_X2a6_4_Xo0(M7_CSL1_Propbus_4, M7_CSL1_Add3_X2a6_4_NotA); inv M7_CSL1_Add3_X2a6_4_Xo1(M7_CSL1_Carry_3, M7_CSL1_Add3_X2a6_4_NotB); nand2 M7_CSL1_Add3_X2a6_4_Xo2(M7_CSL1_Add3_X2a6_4_NotA, M7_CSL1_Carry_3, M7_CSL1_Add3_X2a6_4_line2); nand2 M7_CSL1_Add3_X2a6_4_Xo3(M7_CSL1_Add3_X2a6_4_NotB, M7_CSL1_Propbus_4, M7_CSL1_Add3_X2a6_4_line3); nand2 M7_CSL1_Add3_X2a6_4_Xo4(M7_CSL1_Add3_X2a6_4_line2, M7_CSL1_Add3_X2a6_4_line3, SumYbus_4); inv M7_CSL1_Add3_X2a6_5_Xo0(M7_CSL1_Propbus_5, M7_CSL1_Add3_X2a6_5_NotA); inv M7_CSL1_Add3_X2a6_5_Xo1(M7_CSL1_Carry_4, M7_CSL1_Add3_X2a6_5_NotB); nand2 M7_CSL1_Add3_X2a6_5_Xo2(M7_CSL1_Add3_X2a6_5_NotA, M7_CSL1_Carry_4, M7_CSL1_Add3_X2a6_5_line2); nand2 M7_CSL1_Add3_X2a6_5_Xo3(M7_CSL1_Add3_X2a6_5_NotB, M7_CSL1_Propbus_5, M7_CSL1_Add3_X2a6_5_line3); nand2 M7_CSL1_Add3_X2a6_5_Xo4(M7_CSL1_Add3_X2a6_5_line2, M7_CSL1_Add3_X2a6_5_line3, SumYbus_5); inv M7_CSL1_Add4_X2a6_0_Xo0(M7_CSL1_Propbus_6, M7_CSL1_Add4_X2a6_0_NotA); inv M7_CSL1_Add4_X2a6_0_Xo1(M7_CSL1_Genbus_5, M7_CSL1_Add4_X2a6_0_NotB); nand2 M7_CSL1_Add4_X2a6_0_Xo2(M7_CSL1_Add4_X2a6_0_NotA, M7_CSL1_Genbus_5, M7_CSL1_Add4_X2a6_0_line2); nand2 M7_CSL1_Add4_X2a6_0_Xo3(M7_CSL1_Add4_X2a6_0_NotB, M7_CSL1_Propbus_6, M7_CSL1_Add4_X2a6_0_line3); nand2 M7_CSL1_Add4_X2a6_0_Xo4(M7_CSL1_Add4_X2a6_0_line2, M7_CSL1_Add4_X2a6_0_line3, M7_CSL1_SumH01bus_0); inv M7_CSL1_Add4_X2a6_1_Xo0(M7_CSL1_Propbus_7, M7_CSL1_Add4_X2a6_1_NotA); inv M7_CSL1_Add4_X2a6_1_Xo1(M7_CSL1_LocalHC0_1, M7_CSL1_Add4_X2a6_1_NotB); nand2 M7_CSL1_Add4_X2a6_1_Xo2(M7_CSL1_Add4_X2a6_1_NotA, M7_CSL1_LocalHC0_1, M7_CSL1_Add4_X2a6_1_line2); nand2 M7_CSL1_Add4_X2a6_1_Xo3(M7_CSL1_Add4_X2a6_1_NotB, M7_CSL1_Propbus_7, M7_CSL1_Add4_X2a6_1_line3); nand2 M7_CSL1_Add4_X2a6_1_Xo4(M7_CSL1_Add4_X2a6_1_line2, M7_CSL1_Add4_X2a6_1_line3, M7_CSL1_SumH01bus_1); inv M7_CSL1_Add4_X2a6_2_Xo0(M7_CSL1_Propbus_8, M7_CSL1_Add4_X2a6_2_NotA); inv M7_CSL1_Add4_X2a6_2_Xo1(M7_CSL1_LocalHC0_2, M7_CSL1_Add4_X2a6_2_NotB); nand2 M7_CSL1_Add4_X2a6_2_Xo2(M7_CSL1_Add4_X2a6_2_NotA, M7_CSL1_LocalHC0_2, M7_CSL1_Add4_X2a6_2_line2); nand2 M7_CSL1_Add4_X2a6_2_Xo3(M7_CSL1_Add4_X2a6_2_NotB, M7_CSL1_Propbus_8, M7_CSL1_Add4_X2a6_2_line3); nand2 M7_CSL1_Add4_X2a6_2_Xo4(M7_CSL1_Add4_X2a6_2_line2, M7_CSL1_Add4_X2a6_2_line3, M7_CSL1_SumH01bus_2); inv M7_CSL1_Add4_X2a6_3_Xo0(M7_CSL1_Propbus_6, M7_CSL1_Add4_X2a6_3_NotA); inv M7_CSL1_Add4_X2a6_3_Xo1(M7_CSL1_LocalHC1_0, M7_CSL1_Add4_X2a6_3_NotB); nand2 M7_CSL1_Add4_X2a6_3_Xo2(M7_CSL1_Add4_X2a6_3_NotA, M7_CSL1_LocalHC1_0, M7_CSL1_Add4_X2a6_3_line2); nand2 M7_CSL1_Add4_X2a6_3_Xo3(M7_CSL1_Add4_X2a6_3_NotB, M7_CSL1_Propbus_6, M7_CSL1_Add4_X2a6_3_line3); nand2 M7_CSL1_Add4_X2a6_3_Xo4(M7_CSL1_Add4_X2a6_3_line2, M7_CSL1_Add4_X2a6_3_line3, M7_CSL1_SumH01bus_3); inv M7_CSL1_Add4_X2a6_4_Xo0(M7_CSL1_Propbus_7, M7_CSL1_Add4_X2a6_4_NotA); inv M7_CSL1_Add4_X2a6_4_Xo1(M7_CSL1_LocalHC1_1, M7_CSL1_Add4_X2a6_4_NotB); nand2 M7_CSL1_Add4_X2a6_4_Xo2(M7_CSL1_Add4_X2a6_4_NotA, M7_CSL1_LocalHC1_1, M7_CSL1_Add4_X2a6_4_line2); nand2 M7_CSL1_Add4_X2a6_4_Xo3(M7_CSL1_Add4_X2a6_4_NotB, M7_CSL1_Propbus_7, M7_CSL1_Add4_X2a6_4_line3); nand2 M7_CSL1_Add4_X2a6_4_Xo4(M7_CSL1_Add4_X2a6_4_line2, M7_CSL1_Add4_X2a6_4_line3, M7_CSL1_SumH01bus_4); inv M7_CSL1_Add4_X2a6_5_Xo0(M7_CSL1_Propbus_8, M7_CSL1_Add4_X2a6_5_NotA); inv M7_CSL1_Add4_X2a6_5_Xo1(M7_CSL1_LocalHC1_2, M7_CSL1_Add4_X2a6_5_NotB); nand2 M7_CSL1_Add4_X2a6_5_Xo2(M7_CSL1_Add4_X2a6_5_NotA, M7_CSL1_LocalHC1_2, M7_CSL1_Add4_X2a6_5_line2); nand2 M7_CSL1_Add4_X2a6_5_Xo3(M7_CSL1_Add4_X2a6_5_NotB, M7_CSL1_Propbus_8, M7_CSL1_Add4_X2a6_5_line3); nand2 M7_CSL1_Add4_X2a6_5_Xo4(M7_CSL1_Add4_X2a6_5_line2, M7_CSL1_Add4_X2a6_5_line3, M7_CSL1_SumH01bus_5); inv M7_CSL1_Add5_Mux2_0(M7_CSL1_Carry_4, M7_CSL1_Add5_Not_ContIn); and2 M7_CSL1_Add5_Mux2_1(M7_CSL1_SumH01bus_0, M7_CSL1_Add5_Not_ContIn, M7_CSL1_Add5_line1); and2 M7_CSL1_Add5_Mux2_2(M7_CSL1_SumH01bus_3, M7_CSL1_Carry_4, M7_CSL1_Add5_line2); or2 M7_CSL1_Add5_Mux2_3(M7_CSL1_Add5_line1, M7_CSL1_Add5_line2, SumYbus_6); inv M7_CSL1_Add6_Mux2_0(M7_CSL1_Carry_4, M7_CSL1_Add6_Not_ContIn); and2 M7_CSL1_Add6_Mux2_1(M7_CSL1_SumH01bus_1, M7_CSL1_Add6_Not_ContIn, M7_CSL1_Add6_line1); and2 M7_CSL1_Add6_Mux2_2(M7_CSL1_SumH01bus_4, M7_CSL1_Carry_4, M7_CSL1_Add6_line2); or2 M7_CSL1_Add6_Mux2_3(M7_CSL1_Add6_line1, M7_CSL1_Add6_line2, SumYbus_7); inv M7_CSL1_Add7_Mux2_0(M7_CSL1_Carry_4, M7_CSL1_Add7_Not_ContIn); and2 M7_CSL1_Add7_Mux2_1(M7_CSL1_SumH01bus_2, M7_CSL1_Add7_Not_ContIn, M7_CSL1_Add7_line1); and2 M7_CSL1_Add7_Mux2_2(M7_CSL1_SumH01bus_5, M7_CSL1_Carry_4, M7_CSL1_Add7_line2); or2 M7_CSL1_Add7_Mux2_3(M7_CSL1_Add7_line1, M7_CSL1_Add7_line2, SumYbus_8); inv M7_CSL2_Mx9_0_Mx4_0_Mux4_0(in4092, M7_CSL2_Mx9_0_Mx4_0_Not_ContLo); inv M7_CSL2_Mx9_0_Mx4_0_Mux4_1(in4091, M7_CSL2_Mx9_0_Mx4_0_Not_ContHi); and3 M7_CSL2_Mx9_0_Mx4_0_Mux4_2(LogicYbus_0, M7_CSL2_Mx9_0_Mx4_0_Not_ContHi, M7_CSL2_Mx9_0_Mx4_0_Not_ContLo, M7_CSL2_Mx9_0_Mx4_0_line2); and3 M7_CSL2_Mx9_0_Mx4_0_Mux4_3(in117, M7_CSL2_Mx9_0_Mx4_0_Not_ContHi, in4092, M7_CSL2_Mx9_0_Mx4_0_line3); and3 M7_CSL2_Mx9_0_Mx4_0_Mux4_4(SumYbus_0, in4091, M7_CSL2_Mx9_0_Mx4_0_Not_ContLo, M7_CSL2_Mx9_0_Mx4_0_line4); and3 M7_CSL2_Mx9_0_Mx4_0_Mux4_5(gnd, in4091, in4092, M7_CSL2_Mx9_0_Mx4_0_line5); or4 M7_CSL2_Mx9_0_Mx4_0_Mux4_6(M7_CSL2_Mx9_0_Mx4_0_line2, M7_CSL2_Mx9_0_Mx4_0_line3, M7_CSL2_Mx9_0_Mx4_0_line4, M7_CSL2_Mx9_0_Mx4_0_line5, FYbus_0); inv M7_CSL2_Mx9_0_Mx4_1_Mux4_0(in4092, M7_CSL2_Mx9_0_Mx4_1_Not_ContLo); inv M7_CSL2_Mx9_0_Mx4_1_Mux4_1(in4091, M7_CSL2_Mx9_0_Mx4_1_Not_ContHi); and3 M7_CSL2_Mx9_0_Mx4_1_Mux4_2(LogicYbus_1, M7_CSL2_Mx9_0_Mx4_1_Not_ContHi, M7_CSL2_Mx9_0_Mx4_1_Not_ContLo, M7_CSL2_Mx9_0_Mx4_1_line2); and3 M7_CSL2_Mx9_0_Mx4_1_Mux4_3(in126, M7_CSL2_Mx9_0_Mx4_1_Not_ContHi, in4092, M7_CSL2_Mx9_0_Mx4_1_line3); and3 M7_CSL2_Mx9_0_Mx4_1_Mux4_4(SumYbus_1, in4091, M7_CSL2_Mx9_0_Mx4_1_Not_ContLo, M7_CSL2_Mx9_0_Mx4_1_line4); and3 M7_CSL2_Mx9_0_Mx4_1_Mux4_5(gnd, in4091, in4092, M7_CSL2_Mx9_0_Mx4_1_line5); or4 M7_CSL2_Mx9_0_Mx4_1_Mux4_6(M7_CSL2_Mx9_0_Mx4_1_line2, M7_CSL2_Mx9_0_Mx4_1_line3, M7_CSL2_Mx9_0_Mx4_1_line4, M7_CSL2_Mx9_0_Mx4_1_line5, FYbus_1); inv M7_CSL2_Mx9_0_Mx4_2_Mux4_0(in4092, M7_CSL2_Mx9_0_Mx4_2_Not_ContLo); inv M7_CSL2_Mx9_0_Mx4_2_Mux4_1(in4091, M7_CSL2_Mx9_0_Mx4_2_Not_ContHi); and3 M7_CSL2_Mx9_0_Mx4_2_Mux4_2(LogicYbus_2, M7_CSL2_Mx9_0_Mx4_2_Not_ContHi, M7_CSL2_Mx9_0_Mx4_2_Not_ContLo, M7_CSL2_Mx9_0_Mx4_2_line2); and3 M7_CSL2_Mx9_0_Mx4_2_Mux4_3(in127, M7_CSL2_Mx9_0_Mx4_2_Not_ContHi, in4092, M7_CSL2_Mx9_0_Mx4_2_line3); and3 M7_CSL2_Mx9_0_Mx4_2_Mux4_4(SumYbus_2, in4091, M7_CSL2_Mx9_0_Mx4_2_Not_ContLo, M7_CSL2_Mx9_0_Mx4_2_line4); and3 M7_CSL2_Mx9_0_Mx4_2_Mux4_5(gnd, in4091, in4092, M7_CSL2_Mx9_0_Mx4_2_line5); or4 M7_CSL2_Mx9_0_Mx4_2_Mux4_6(M7_CSL2_Mx9_0_Mx4_2_line2, M7_CSL2_Mx9_0_Mx4_2_line3, M7_CSL2_Mx9_0_Mx4_2_line4, M7_CSL2_Mx9_0_Mx4_2_line5, FYbus_2); inv M7_CSL2_Mx9_0_Mx4_3_Mux4_0(in4092, M7_CSL2_Mx9_0_Mx4_3_Not_ContLo); inv M7_CSL2_Mx9_0_Mx4_3_Mux4_1(in4091, M7_CSL2_Mx9_0_Mx4_3_Not_ContHi); and3 M7_CSL2_Mx9_0_Mx4_3_Mux4_2(LogicYbus_3, M7_CSL2_Mx9_0_Mx4_3_Not_ContHi, M7_CSL2_Mx9_0_Mx4_3_Not_ContLo, M7_CSL2_Mx9_0_Mx4_3_line2); and3 M7_CSL2_Mx9_0_Mx4_3_Mux4_3(in128, M7_CSL2_Mx9_0_Mx4_3_Not_ContHi, in4092, M7_CSL2_Mx9_0_Mx4_3_line3); and3 M7_CSL2_Mx9_0_Mx4_3_Mux4_4(SumYbus_3, in4091, M7_CSL2_Mx9_0_Mx4_3_Not_ContLo, M7_CSL2_Mx9_0_Mx4_3_line4); and3 M7_CSL2_Mx9_0_Mx4_3_Mux4_5(gnd, in4091, in4092, M7_CSL2_Mx9_0_Mx4_3_line5); or4 M7_CSL2_Mx9_0_Mx4_3_Mux4_6(M7_CSL2_Mx9_0_Mx4_3_line2, M7_CSL2_Mx9_0_Mx4_3_line3, M7_CSL2_Mx9_0_Mx4_3_line4, M7_CSL2_Mx9_0_Mx4_3_line5, FYbus_3); inv M7_CSL2_Mx9_1_Mx4_0_Mux4_0(in4092, M7_CSL2_Mx9_1_Mx4_0_Not_ContLo); inv M7_CSL2_Mx9_1_Mx4_0_Mux4_1(in4091, M7_CSL2_Mx9_1_Mx4_0_Not_ContHi); and3 M7_CSL2_Mx9_1_Mx4_0_Mux4_2(LogicYbus_4, M7_CSL2_Mx9_1_Mx4_0_Not_ContHi, M7_CSL2_Mx9_1_Mx4_0_Not_ContLo, M7_CSL2_Mx9_1_Mx4_0_line2); and3 M7_CSL2_Mx9_1_Mx4_0_Mux4_3(in122, M7_CSL2_Mx9_1_Mx4_0_Not_ContHi, in4092, M7_CSL2_Mx9_1_Mx4_0_line3); and3 M7_CSL2_Mx9_1_Mx4_0_Mux4_4(SumYbus_4, in4091, M7_CSL2_Mx9_1_Mx4_0_Not_ContLo, M7_CSL2_Mx9_1_Mx4_0_line4); and3 M7_CSL2_Mx9_1_Mx4_0_Mux4_5(gnd, in4091, in4092, M7_CSL2_Mx9_1_Mx4_0_line5); or4 M7_CSL2_Mx9_1_Mx4_0_Mux4_6(M7_CSL2_Mx9_1_Mx4_0_line2, M7_CSL2_Mx9_1_Mx4_0_line3, M7_CSL2_Mx9_1_Mx4_0_line4, M7_CSL2_Mx9_1_Mx4_0_line5, FYbus_4); inv M7_CSL2_Mx9_1_Mx4_1_Mux4_0(in4092, M7_CSL2_Mx9_1_Mx4_1_Not_ContLo); inv M7_CSL2_Mx9_1_Mx4_1_Mux4_1(in4091, M7_CSL2_Mx9_1_Mx4_1_Not_ContHi); and3 M7_CSL2_Mx9_1_Mx4_1_Mux4_2(LogicYbus_5, M7_CSL2_Mx9_1_Mx4_1_Not_ContHi, M7_CSL2_Mx9_1_Mx4_1_Not_ContLo, M7_CSL2_Mx9_1_Mx4_1_line2); and3 M7_CSL2_Mx9_1_Mx4_1_Mux4_3(in113, M7_CSL2_Mx9_1_Mx4_1_Not_ContHi, in4092, M7_CSL2_Mx9_1_Mx4_1_line3); and3 M7_CSL2_Mx9_1_Mx4_1_Mux4_4(SumYbus_5, in4091, M7_CSL2_Mx9_1_Mx4_1_Not_ContLo, M7_CSL2_Mx9_1_Mx4_1_line4); and3 M7_CSL2_Mx9_1_Mx4_1_Mux4_5(gnd, in4091, in4092, M7_CSL2_Mx9_1_Mx4_1_line5); or4 M7_CSL2_Mx9_1_Mx4_1_Mux4_6(M7_CSL2_Mx9_1_Mx4_1_line2, M7_CSL2_Mx9_1_Mx4_1_line3, M7_CSL2_Mx9_1_Mx4_1_line4, M7_CSL2_Mx9_1_Mx4_1_line5, FYbus_5); inv M7_CSL2_Mx9_1_Mx4_2_Mux4_0(in4092, M7_CSL2_Mx9_1_Mx4_2_Not_ContLo); inv M7_CSL2_Mx9_1_Mx4_2_Mux4_1(in4091, M7_CSL2_Mx9_1_Mx4_2_Not_ContHi); and3 M7_CSL2_Mx9_1_Mx4_2_Mux4_2(LogicYbus_6, M7_CSL2_Mx9_1_Mx4_2_Not_ContHi, M7_CSL2_Mx9_1_Mx4_2_Not_ContLo, M7_CSL2_Mx9_1_Mx4_2_line2); and3 M7_CSL2_Mx9_1_Mx4_2_Mux4_3(in53, M7_CSL2_Mx9_1_Mx4_2_Not_ContHi, in4092, M7_CSL2_Mx9_1_Mx4_2_line3); and3 M7_CSL2_Mx9_1_Mx4_2_Mux4_4(SumYbus_6, in4091, M7_CSL2_Mx9_1_Mx4_2_Not_ContLo, M7_CSL2_Mx9_1_Mx4_2_line4); and3 M7_CSL2_Mx9_1_Mx4_2_Mux4_5(gnd, in4091, in4092, M7_CSL2_Mx9_1_Mx4_2_line5); or4 M7_CSL2_Mx9_1_Mx4_2_Mux4_6(M7_CSL2_Mx9_1_Mx4_2_line2, M7_CSL2_Mx9_1_Mx4_2_line3, M7_CSL2_Mx9_1_Mx4_2_line4, M7_CSL2_Mx9_1_Mx4_2_line5, FYbus_6); inv M7_CSL2_Mx9_1_Mx4_3_Mux4_0(in4092, M7_CSL2_Mx9_1_Mx4_3_Not_ContLo); inv M7_CSL2_Mx9_1_Mx4_3_Mux4_1(in4091, M7_CSL2_Mx9_1_Mx4_3_Not_ContHi); and3 M7_CSL2_Mx9_1_Mx4_3_Mux4_2(LogicYbus_7, M7_CSL2_Mx9_1_Mx4_3_Not_ContHi, M7_CSL2_Mx9_1_Mx4_3_Not_ContLo, M7_CSL2_Mx9_1_Mx4_3_line2); and3 M7_CSL2_Mx9_1_Mx4_3_Mux4_3(in114, M7_CSL2_Mx9_1_Mx4_3_Not_ContHi, in4092, M7_CSL2_Mx9_1_Mx4_3_line3); and3 M7_CSL2_Mx9_1_Mx4_3_Mux4_4(SumYbus_7, in4091, M7_CSL2_Mx9_1_Mx4_3_Not_ContLo, M7_CSL2_Mx9_1_Mx4_3_line4); and3 M7_CSL2_Mx9_1_Mx4_3_Mux4_5(gnd, in4091, in4092, M7_CSL2_Mx9_1_Mx4_3_line5); or4 M7_CSL2_Mx9_1_Mx4_3_Mux4_6(M7_CSL2_Mx9_1_Mx4_3_line2, M7_CSL2_Mx9_1_Mx4_3_line3, M7_CSL2_Mx9_1_Mx4_3_line4, M7_CSL2_Mx9_1_Mx4_3_line5, FYbus_7); inv M7_CSL2_Mx9_2_Mux4_0(in4092, M7_CSL2_Mx9_2_Not_ContLo); inv M7_CSL2_Mx9_2_Mux4_1(in4091, M7_CSL2_Mx9_2_Not_ContHi); and3 M7_CSL2_Mx9_2_Mux4_2(LogicYbus_8, M7_CSL2_Mx9_2_Not_ContHi, M7_CSL2_Mx9_2_Not_ContLo, M7_CSL2_Mx9_2_line2); and3 M7_CSL2_Mx9_2_Mux4_3(in115, M7_CSL2_Mx9_2_Not_ContHi, in4092, M7_CSL2_Mx9_2_line3); and3 M7_CSL2_Mx9_2_Mux4_4(SumYbus_8, in4091, M7_CSL2_Mx9_2_Not_ContLo, M7_CSL2_Mx9_2_line4); and3 M7_CSL2_Mx9_2_Mux4_5(gnd, in4091, in4092, M7_CSL2_Mx9_2_line5); or4 M7_CSL2_Mx9_2_Mux4_6(M7_CSL2_Mx9_2_line2, M7_CSL2_Mx9_2_line3, M7_CSL2_Mx9_2_line4, M7_CSL2_Mx9_2_line5, FYbus_8); inv M8_MF8_0_MF4_0_MXS0_Mux4_0(in1689, M8_MF8_0_MF4_0_MXS0_Not_ContLo); inv M8_MF8_0_MF4_0_MXS0_Mux4_1(in1690, M8_MF8_0_MF4_0_MXS0_Not_ContHi); and3 M8_MF8_0_MF4_0_MXS0_Mux4_2(FXbus_0, M8_MF8_0_MF4_0_MXS0_Not_ContHi, M8_MF8_0_MF4_0_MXS0_Not_ContLo, M8_MF8_0_MF4_0_MXS0_line2); and3 M8_MF8_0_MF4_0_MXS0_Mux4_3(FYbus_0, M8_MF8_0_MF4_0_MXS0_Not_ContHi, in1689, M8_MF8_0_MF4_0_MXS0_line3); and3 M8_MF8_0_MF4_0_MXS0_Mux4_4(in182, in1690, M8_MF8_0_MF4_0_MXS0_Not_ContLo, M8_MF8_0_MF4_0_MXS0_line4); and3 M8_MF8_0_MF4_0_MXS0_Mux4_5(in185, in1690, in1689, M8_MF8_0_MF4_0_MXS0_line5); or4 M8_MF8_0_MF4_0_MXS0_Mux4_6(M8_MF8_0_MF4_0_MXS0_line2, M8_MF8_0_MF4_0_MXS0_line3, M8_MF8_0_MF4_0_MXS0_line4, M8_MF8_0_MF4_0_MXS0_line5, M8_MF8_0_MF4_0_tempOut1); inv M8_MF8_0_MF4_0_MXS1_Mux4_0(in1691, M8_MF8_0_MF4_0_MXS1_Not_ContLo); inv M8_MF8_0_MF4_0_MXS1_Mux4_1(in1694, M8_MF8_0_MF4_0_MXS1_Not_ContHi); and3 M8_MF8_0_MF4_0_MXS1_Mux4_2(FXbus_0, M8_MF8_0_MF4_0_MXS1_Not_ContHi, M8_MF8_0_MF4_0_MXS1_Not_ContLo, M8_MF8_0_MF4_0_MXS1_line2); and3 M8_MF8_0_MF4_0_MXS1_Mux4_3(FYbus_0, M8_MF8_0_MF4_0_MXS1_Not_ContHi, in1691, M8_MF8_0_MF4_0_MXS1_line3); and3 M8_MF8_0_MF4_0_MXS1_Mux4_4(in182, in1694, M8_MF8_0_MF4_0_MXS1_Not_ContLo, M8_MF8_0_MF4_0_MXS1_line4); and3 M8_MF8_0_MF4_0_MXS1_Mux4_5(in185, in1694, in1691, M8_MF8_0_MF4_0_MXS1_line5); or4 M8_MF8_0_MF4_0_MXS1_Mux4_6(M8_MF8_0_MF4_0_MXS1_line2, M8_MF8_0_MF4_0_MXS1_line3, M8_MF8_0_MF4_0_MXS1_line4, M8_MF8_0_MF4_0_MXS1_line5, M8_MF8_0_MF4_0_tempOut2); inv M8_MF8_0_MF4_0_MXS2_Mux4_0(in4088, M8_MF8_0_MF4_0_MXS2_Not_ContLo); inv M8_MF8_0_MF4_0_MXS2_Mux4_1(in4087, M8_MF8_0_MF4_0_MXS2_Not_ContHi); and3 M8_MF8_0_MF4_0_MXS2_Mux4_2(FXbus_0, M8_MF8_0_MF4_0_MXS2_Not_ContHi, M8_MF8_0_MF4_0_MXS2_Not_ContLo, M8_MF8_0_MF4_0_MXS2_line2); and3 M8_MF8_0_MF4_0_MXS2_Mux4_3(FYbus_0, M8_MF8_0_MF4_0_MXS2_Not_ContHi, in4088, M8_MF8_0_MF4_0_MXS2_line3); and3 M8_MF8_0_MF4_0_MXS2_Mux4_4(in11, in4087, M8_MF8_0_MF4_0_MXS2_Not_ContLo, M8_MF8_0_MF4_0_MXS2_line4); and3 M8_MF8_0_MF4_0_MXS2_Mux4_5(in61, in4087, in4088, M8_MF8_0_MF4_0_MXS2_line5); or4 M8_MF8_0_MF4_0_MXS2_Mux4_6(M8_MF8_0_MF4_0_MXS2_line2, M8_MF8_0_MF4_0_MXS2_line3, M8_MF8_0_MF4_0_MXS2_line4, M8_MF8_0_MF4_0_MXS2_line5, out722); inv M8_MF8_0_MF4_0_MXS3_Mux4_0(in4089, M8_MF8_0_MF4_0_MXS3_Not_ContLo); inv M8_MF8_0_MF4_0_MXS3_Mux4_1(in4090, M8_MF8_0_MF4_0_MXS3_Not_ContHi); and3 M8_MF8_0_MF4_0_MXS3_Mux4_2(FXbus_0, M8_MF8_0_MF4_0_MXS3_Not_ContHi, M8_MF8_0_MF4_0_MXS3_Not_ContLo, M8_MF8_0_MF4_0_MXS3_line2); and3 M8_MF8_0_MF4_0_MXS3_Mux4_3(FYbus_0, M8_MF8_0_MF4_0_MXS3_Not_ContHi, in4089, M8_MF8_0_MF4_0_MXS3_line3); and3 M8_MF8_0_MF4_0_MXS3_Mux4_4(in11, in4090, M8_MF8_0_MF4_0_MXS3_Not_ContLo, M8_MF8_0_MF4_0_MXS3_line4); and3 M8_MF8_0_MF4_0_MXS3_Mux4_5(in61, in4090, in4089, M8_MF8_0_MF4_0_MXS3_line5); or4 M8_MF8_0_MF4_0_MXS3_Mux4_6(M8_MF8_0_MF4_0_MXS3_line2, M8_MF8_0_MF4_0_MXS3_line3, M8_MF8_0_MF4_0_MXS3_line4, M8_MF8_0_MF4_0_MXS3_line5, out859); and2 M8_MF8_0_MF4_0_MXS4(M8_MF8_0_MF4_0_tempOut1, in137, out661); and2 M8_MF8_0_MF4_0_MXS5(M8_MF8_0_MF4_0_tempOut2, in137, out693); inv M8_MF8_0_MF4_1_MXS0_Mux4_0(in1689, M8_MF8_0_MF4_1_MXS0_Not_ContLo); inv M8_MF8_0_MF4_1_MXS0_Mux4_1(in1690, M8_MF8_0_MF4_1_MXS0_Not_ContHi); and3 M8_MF8_0_MF4_1_MXS0_Mux4_2(FXbus_1, M8_MF8_0_MF4_1_MXS0_Not_ContHi, M8_MF8_0_MF4_1_MXS0_Not_ContLo, M8_MF8_0_MF4_1_MXS0_line2); and3 M8_MF8_0_MF4_1_MXS0_Mux4_3(FYbus_1, M8_MF8_0_MF4_1_MXS0_Not_ContHi, in1689, M8_MF8_0_MF4_1_MXS0_line3); and3 M8_MF8_0_MF4_1_MXS0_Mux4_4(in188, in1690, M8_MF8_0_MF4_1_MXS0_Not_ContLo, M8_MF8_0_MF4_1_MXS0_line4); and3 M8_MF8_0_MF4_1_MXS0_Mux4_5(in158, in1690, in1689, M8_MF8_0_MF4_1_MXS0_line5); or4 M8_MF8_0_MF4_1_MXS0_Mux4_6(M8_MF8_0_MF4_1_MXS0_line2, M8_MF8_0_MF4_1_MXS0_line3, M8_MF8_0_MF4_1_MXS0_line4, M8_MF8_0_MF4_1_MXS0_line5, M8_MF8_0_MF4_1_tempOut1); inv M8_MF8_0_MF4_1_MXS1_Mux4_0(in1691, M8_MF8_0_MF4_1_MXS1_Not_ContLo); inv M8_MF8_0_MF4_1_MXS1_Mux4_1(in1694, M8_MF8_0_MF4_1_MXS1_Not_ContHi); and3 M8_MF8_0_MF4_1_MXS1_Mux4_2(FXbus_1, M8_MF8_0_MF4_1_MXS1_Not_ContHi, M8_MF8_0_MF4_1_MXS1_Not_ContLo, M8_MF8_0_MF4_1_MXS1_line2); and3 M8_MF8_0_MF4_1_MXS1_Mux4_3(FYbus_1, M8_MF8_0_MF4_1_MXS1_Not_ContHi, in1691, M8_MF8_0_MF4_1_MXS1_line3); and3 M8_MF8_0_MF4_1_MXS1_Mux4_4(in188, in1694, M8_MF8_0_MF4_1_MXS1_Not_ContLo, M8_MF8_0_MF4_1_MXS1_line4); and3 M8_MF8_0_MF4_1_MXS1_Mux4_5(in158, in1694, in1691, M8_MF8_0_MF4_1_MXS1_line5); or4 M8_MF8_0_MF4_1_MXS1_Mux4_6(M8_MF8_0_MF4_1_MXS1_line2, M8_MF8_0_MF4_1_MXS1_line3, M8_MF8_0_MF4_1_MXS1_line4, M8_MF8_0_MF4_1_MXS1_line5, M8_MF8_0_MF4_1_tempOut2); inv M8_MF8_0_MF4_1_MXS2_Mux4_0(in4088, M8_MF8_0_MF4_1_MXS2_Not_ContLo); inv M8_MF8_0_MF4_1_MXS2_Mux4_1(in4087, M8_MF8_0_MF4_1_MXS2_Not_ContHi); and3 M8_MF8_0_MF4_1_MXS2_Mux4_2(FXbus_1, M8_MF8_0_MF4_1_MXS2_Not_ContHi, M8_MF8_0_MF4_1_MXS2_Not_ContLo, M8_MF8_0_MF4_1_MXS2_line2); and3 M8_MF8_0_MF4_1_MXS2_Mux4_3(FYbus_1, M8_MF8_0_MF4_1_MXS2_Not_ContHi, in4088, M8_MF8_0_MF4_1_MXS2_line3); and3 M8_MF8_0_MF4_1_MXS2_Mux4_4(in67, in4087, M8_MF8_0_MF4_1_MXS2_Not_ContLo, M8_MF8_0_MF4_1_MXS2_line4); and3 M8_MF8_0_MF4_1_MXS2_Mux4_5(in70, in4087, in4088, M8_MF8_0_MF4_1_MXS2_line5); or4 M8_MF8_0_MF4_1_MXS2_Mux4_6(M8_MF8_0_MF4_1_MXS2_line2, M8_MF8_0_MF4_1_MXS2_line3, M8_MF8_0_MF4_1_MXS2_line4, M8_MF8_0_MF4_1_MXS2_line5, out762); inv M8_MF8_0_MF4_1_MXS3_Mux4_0(in4089, M8_MF8_0_MF4_1_MXS3_Not_ContLo); inv M8_MF8_0_MF4_1_MXS3_Mux4_1(in4090, M8_MF8_0_MF4_1_MXS3_Not_ContHi); and3 M8_MF8_0_MF4_1_MXS3_Mux4_2(FXbus_1, M8_MF8_0_MF4_1_MXS3_Not_ContHi, M8_MF8_0_MF4_1_MXS3_Not_ContLo, M8_MF8_0_MF4_1_MXS3_line2); and3 M8_MF8_0_MF4_1_MXS3_Mux4_3(FYbus_1, M8_MF8_0_MF4_1_MXS3_Not_ContHi, in4089, M8_MF8_0_MF4_1_MXS3_line3); and3 M8_MF8_0_MF4_1_MXS3_Mux4_4(in67, in4090, M8_MF8_0_MF4_1_MXS3_Not_ContLo, M8_MF8_0_MF4_1_MXS3_line4); and3 M8_MF8_0_MF4_1_MXS3_Mux4_5(in70, in4090, in4089, M8_MF8_0_MF4_1_MXS3_line5); or4 M8_MF8_0_MF4_1_MXS3_Mux4_6(M8_MF8_0_MF4_1_MXS3_line2, M8_MF8_0_MF4_1_MXS3_line3, M8_MF8_0_MF4_1_MXS3_line4, M8_MF8_0_MF4_1_MXS3_line5, out802); and2 M8_MF8_0_MF4_1_MXS4(M8_MF8_0_MF4_1_tempOut1, in137, out664); and2 M8_MF8_0_MF4_1_MXS5(M8_MF8_0_MF4_1_tempOut2, in137, out696); inv M8_MF8_0_MF4_2_MXS0_Mux4_0(in1689, M8_MF8_0_MF4_2_MXS0_Not_ContLo); inv M8_MF8_0_MF4_2_MXS0_Mux4_1(in1690, M8_MF8_0_MF4_2_MXS0_Not_ContHi); and3 M8_MF8_0_MF4_2_MXS0_Mux4_2(FXbus_2, M8_MF8_0_MF4_2_MXS0_Not_ContHi, M8_MF8_0_MF4_2_MXS0_Not_ContLo, M8_MF8_0_MF4_2_MXS0_line2); and3 M8_MF8_0_MF4_2_MXS0_Mux4_3(FYbus_2, M8_MF8_0_MF4_2_MXS0_Not_ContHi, in1689, M8_MF8_0_MF4_2_MXS0_line3); and3 M8_MF8_0_MF4_2_MXS0_Mux4_4(in155, in1690, M8_MF8_0_MF4_2_MXS0_Not_ContLo, M8_MF8_0_MF4_2_MXS0_line4); and3 M8_MF8_0_MF4_2_MXS0_Mux4_5(in152, in1690, in1689, M8_MF8_0_MF4_2_MXS0_line5); or4 M8_MF8_0_MF4_2_MXS0_Mux4_6(M8_MF8_0_MF4_2_MXS0_line2, M8_MF8_0_MF4_2_MXS0_line3, M8_MF8_0_MF4_2_MXS0_line4, M8_MF8_0_MF4_2_MXS0_line5, M8_MF8_0_MF4_2_tempOut1); inv M8_MF8_0_MF4_2_MXS1_Mux4_0(in1691, M8_MF8_0_MF4_2_MXS1_Not_ContLo); inv M8_MF8_0_MF4_2_MXS1_Mux4_1(in1694, M8_MF8_0_MF4_2_MXS1_Not_ContHi); and3 M8_MF8_0_MF4_2_MXS1_Mux4_2(FXbus_2, M8_MF8_0_MF4_2_MXS1_Not_ContHi, M8_MF8_0_MF4_2_MXS1_Not_ContLo, M8_MF8_0_MF4_2_MXS1_line2); and3 M8_MF8_0_MF4_2_MXS1_Mux4_3(FYbus_2, M8_MF8_0_MF4_2_MXS1_Not_ContHi, in1691, M8_MF8_0_MF4_2_MXS1_line3); and3 M8_MF8_0_MF4_2_MXS1_Mux4_4(in155, in1694, M8_MF8_0_MF4_2_MXS1_Not_ContLo, M8_MF8_0_MF4_2_MXS1_line4); and3 M8_MF8_0_MF4_2_MXS1_Mux4_5(in152, in1694, in1691, M8_MF8_0_MF4_2_MXS1_line5); or4 M8_MF8_0_MF4_2_MXS1_Mux4_6(M8_MF8_0_MF4_2_MXS1_line2, M8_MF8_0_MF4_2_MXS1_line3, M8_MF8_0_MF4_2_MXS1_line4, M8_MF8_0_MF4_2_MXS1_line5, M8_MF8_0_MF4_2_tempOut2); inv M8_MF8_0_MF4_2_MXS2_Mux4_0(in4088, M8_MF8_0_MF4_2_MXS2_Not_ContLo); inv M8_MF8_0_MF4_2_MXS2_Mux4_1(in4087, M8_MF8_0_MF4_2_MXS2_Not_ContHi); and3 M8_MF8_0_MF4_2_MXS2_Mux4_2(FXbus_2, M8_MF8_0_MF4_2_MXS2_Not_ContHi, M8_MF8_0_MF4_2_MXS2_Not_ContLo, M8_MF8_0_MF4_2_MXS2_line2); and3 M8_MF8_0_MF4_2_MXS2_Mux4_3(FYbus_2, M8_MF8_0_MF4_2_MXS2_Not_ContHi, in4088, M8_MF8_0_MF4_2_MXS2_line3); and3 M8_MF8_0_MF4_2_MXS2_Mux4_4(in73, in4087, M8_MF8_0_MF4_2_MXS2_Not_ContLo, M8_MF8_0_MF4_2_MXS2_line4); and3 M8_MF8_0_MF4_2_MXS2_Mux4_5(in17, in4087, in4088, M8_MF8_0_MF4_2_MXS2_line5); or4 M8_MF8_0_MF4_2_MXS2_Mux4_6(M8_MF8_0_MF4_2_MXS2_line2, M8_MF8_0_MF4_2_MXS2_line3, M8_MF8_0_MF4_2_MXS2_line4, M8_MF8_0_MF4_2_MXS2_line5, out757); inv M8_MF8_0_MF4_2_MXS3_Mux4_0(in4089, M8_MF8_0_MF4_2_MXS3_Not_ContLo); inv M8_MF8_0_MF4_2_MXS3_Mux4_1(in4090, M8_MF8_0_MF4_2_MXS3_Not_ContHi); and3 M8_MF8_0_MF4_2_MXS3_Mux4_2(FXbus_2, M8_MF8_0_MF4_2_MXS3_Not_ContHi, M8_MF8_0_MF4_2_MXS3_Not_ContLo, M8_MF8_0_MF4_2_MXS3_line2); and3 M8_MF8_0_MF4_2_MXS3_Mux4_3(FYbus_2, M8_MF8_0_MF4_2_MXS3_Not_ContHi, in4089, M8_MF8_0_MF4_2_MXS3_line3); and3 M8_MF8_0_MF4_2_MXS3_Mux4_4(in73, in4090, M8_MF8_0_MF4_2_MXS3_Not_ContLo, M8_MF8_0_MF4_2_MXS3_line4); and3 M8_MF8_0_MF4_2_MXS3_Mux4_5(in17, in4090, in4089, M8_MF8_0_MF4_2_MXS3_line5); or4 M8_MF8_0_MF4_2_MXS3_Mux4_6(M8_MF8_0_MF4_2_MXS3_line2, M8_MF8_0_MF4_2_MXS3_line3, M8_MF8_0_MF4_2_MXS3_line4, M8_MF8_0_MF4_2_MXS3_line5, out797); and2 M8_MF8_0_MF4_2_MXS4(M8_MF8_0_MF4_2_tempOut1, in137, out667); and2 M8_MF8_0_MF4_2_MXS5(M8_MF8_0_MF4_2_tempOut2, in137, out699); inv M8_MF8_0_MF8_3_MXS0_Mux4_0(in1689, M8_MF8_0_MF8_3_MXS0_Not_ContLo); inv M8_MF8_0_MF8_3_MXS0_Mux4_1(in1690, M8_MF8_0_MF8_3_MXS0_Not_ContHi); and3 M8_MF8_0_MF8_3_MXS0_Mux4_2(FXbus_3, M8_MF8_0_MF8_3_MXS0_Not_ContHi, M8_MF8_0_MF8_3_MXS0_Not_ContLo, M8_MF8_0_MF8_3_MXS0_line2); and3 M8_MF8_0_MF8_3_MXS0_Mux4_3(FYbus_3, M8_MF8_0_MF8_3_MXS0_Not_ContHi, in1689, M8_MF8_0_MF8_3_MXS0_line3); and3 M8_MF8_0_MF8_3_MXS0_Mux4_4(in149, in1690, M8_MF8_0_MF8_3_MXS0_Not_ContLo, M8_MF8_0_MF8_3_MXS0_line4); and3 M8_MF8_0_MF8_3_MXS0_Mux4_5(in146, in1690, in1689, M8_MF8_0_MF8_3_MXS0_line5); or4 M8_MF8_0_MF8_3_MXS0_Mux4_6(M8_MF8_0_MF8_3_MXS0_line2, M8_MF8_0_MF8_3_MXS0_line3, M8_MF8_0_MF8_3_MXS0_line4, M8_MF8_0_MF8_3_MXS0_line5, M8_MF8_0_MF8_3_tempOut1); inv M8_MF8_0_MF8_3_MXS1_Mux4_0(in1691, M8_MF8_0_MF8_3_MXS1_Not_ContLo); inv M8_MF8_0_MF8_3_MXS1_Mux4_1(in1694, M8_MF8_0_MF8_3_MXS1_Not_ContHi); and3 M8_MF8_0_MF8_3_MXS1_Mux4_2(FXbus_3, M8_MF8_0_MF8_3_MXS1_Not_ContHi, M8_MF8_0_MF8_3_MXS1_Not_ContLo, M8_MF8_0_MF8_3_MXS1_line2); and3 M8_MF8_0_MF8_3_MXS1_Mux4_3(FYbus_3, M8_MF8_0_MF8_3_MXS1_Not_ContHi, in1691, M8_MF8_0_MF8_3_MXS1_line3); and3 M8_MF8_0_MF8_3_MXS1_Mux4_4(in149, in1694, M8_MF8_0_MF8_3_MXS1_Not_ContLo, M8_MF8_0_MF8_3_MXS1_line4); and3 M8_MF8_0_MF8_3_MXS1_Mux4_5(in146, in1694, in1691, M8_MF8_0_MF8_3_MXS1_line5); or4 M8_MF8_0_MF8_3_MXS1_Mux4_6(M8_MF8_0_MF8_3_MXS1_line2, M8_MF8_0_MF8_3_MXS1_line3, M8_MF8_0_MF8_3_MXS1_line4, M8_MF8_0_MF8_3_MXS1_line5, M8_MF8_0_MF8_3_tempOut2); inv M8_MF8_0_MF8_3_MXS2_Mux4_0(in4088, M8_MF8_0_MF8_3_MXS2_Not_ContLo); inv M8_MF8_0_MF8_3_MXS2_Mux4_1(in4087, M8_MF8_0_MF8_3_MXS2_Not_ContHi); and3 M8_MF8_0_MF8_3_MXS2_Mux4_2(FXbus_3, M8_MF8_0_MF8_3_MXS2_Not_ContHi, M8_MF8_0_MF8_3_MXS2_Not_ContLo, M8_MF8_0_MF8_3_MXS2_line2); and3 M8_MF8_0_MF8_3_MXS2_Mux4_3(FYbus_3, M8_MF8_0_MF8_3_MXS2_Not_ContHi, in4088, M8_MF8_0_MF8_3_MXS2_line3); and3 M8_MF8_0_MF8_3_MXS2_Mux4_4(in76, in4087, M8_MF8_0_MF8_3_MXS2_Not_ContLo, M8_MF8_0_MF8_3_MXS2_line4); and3 M8_MF8_0_MF8_3_MXS2_Mux4_5(in20, in4087, in4088, M8_MF8_0_MF8_3_MXS2_line5); or4 M8_MF8_0_MF8_3_MXS2_Mux4_6(M8_MF8_0_MF8_3_MXS2_line2, M8_MF8_0_MF8_3_MXS2_line3, M8_MF8_0_MF8_3_MXS2_line4, M8_MF8_0_MF8_3_MXS2_line5, out752); inv M8_MF8_0_MF8_3_MXS3_Mux4_0(in4089, M8_MF8_0_MF8_3_MXS3_Not_ContLo); inv M8_MF8_0_MF8_3_MXS3_Mux4_1(in4090, M8_MF8_0_MF8_3_MXS3_Not_ContHi); and3 M8_MF8_0_MF8_3_MXS3_Mux4_2(FXbus_3, M8_MF8_0_MF8_3_MXS3_Not_ContHi, M8_MF8_0_MF8_3_MXS3_Not_ContLo, M8_MF8_0_MF8_3_MXS3_line2); and3 M8_MF8_0_MF8_3_MXS3_Mux4_3(FYbus_3, M8_MF8_0_MF8_3_MXS3_Not_ContHi, in4089, M8_MF8_0_MF8_3_MXS3_line3); and3 M8_MF8_0_MF8_3_MXS3_Mux4_4(in76, in4090, M8_MF8_0_MF8_3_MXS3_Not_ContLo, M8_MF8_0_MF8_3_MXS3_line4); and3 M8_MF8_0_MF8_3_MXS3_Mux4_5(in20, in4090, in4089, M8_MF8_0_MF8_3_MXS3_line5); or4 M8_MF8_0_MF8_3_MXS3_Mux4_6(M8_MF8_0_MF8_3_MXS3_line2, M8_MF8_0_MF8_3_MXS3_line3, M8_MF8_0_MF8_3_MXS3_line4, M8_MF8_0_MF8_3_MXS3_line5, out792); and2 M8_MF8_0_MF8_3_MXS4(M8_MF8_0_MF8_3_tempOut1, in137, out670); and2 M8_MF8_0_MF8_3_MXS5(M8_MF8_0_MF8_3_tempOut2, in137, out702); inv M8_MF8_1_MF4_0_MXS0_Mux4_0(in1689, M8_MF8_1_MF4_0_MXS0_Not_ContLo); inv M8_MF8_1_MF4_0_MXS0_Mux4_1(in1690, M8_MF8_1_MF4_0_MXS0_Not_ContHi); and3 M8_MF8_1_MF4_0_MXS0_Mux4_2(FXbus_4, M8_MF8_1_MF4_0_MXS0_Not_ContHi, M8_MF8_1_MF4_0_MXS0_Not_ContLo, M8_MF8_1_MF4_0_MXS0_line2); and3 M8_MF8_1_MF4_0_MXS0_Mux4_3(FYbus_4, M8_MF8_1_MF4_0_MXS0_Not_ContHi, in1689, M8_MF8_1_MF4_0_MXS0_line3); and3 M8_MF8_1_MF4_0_MXS0_Mux4_4(in200, in1690, M8_MF8_1_MF4_0_MXS0_Not_ContLo, M8_MF8_1_MF4_0_MXS0_line4); and3 M8_MF8_1_MF4_0_MXS0_Mux4_5(in170, in1690, in1689, M8_MF8_1_MF4_0_MXS0_line5); or4 M8_MF8_1_MF4_0_MXS0_Mux4_6(M8_MF8_1_MF4_0_MXS0_line2, M8_MF8_1_MF4_0_MXS0_line3, M8_MF8_1_MF4_0_MXS0_line4, M8_MF8_1_MF4_0_MXS0_line5, M8_MF8_1_MF4_0_tempOut1); inv M8_MF8_1_MF4_0_MXS1_Mux4_0(in1691, M8_MF8_1_MF4_0_MXS1_Not_ContLo); inv M8_MF8_1_MF4_0_MXS1_Mux4_1(in1694, M8_MF8_1_MF4_0_MXS1_Not_ContHi); and3 M8_MF8_1_MF4_0_MXS1_Mux4_2(FXbus_4, M8_MF8_1_MF4_0_MXS1_Not_ContHi, M8_MF8_1_MF4_0_MXS1_Not_ContLo, M8_MF8_1_MF4_0_MXS1_line2); and3 M8_MF8_1_MF4_0_MXS1_Mux4_3(FYbus_4, M8_MF8_1_MF4_0_MXS1_Not_ContHi, in1691, M8_MF8_1_MF4_0_MXS1_line3); and3 M8_MF8_1_MF4_0_MXS1_Mux4_4(in200, in1694, M8_MF8_1_MF4_0_MXS1_Not_ContLo, M8_MF8_1_MF4_0_MXS1_line4); and3 M8_MF8_1_MF4_0_MXS1_Mux4_5(in170, in1694, in1691, M8_MF8_1_MF4_0_MXS1_line5); or4 M8_MF8_1_MF4_0_MXS1_Mux4_6(M8_MF8_1_MF4_0_MXS1_line2, M8_MF8_1_MF4_0_MXS1_line3, M8_MF8_1_MF4_0_MXS1_line4, M8_MF8_1_MF4_0_MXS1_line5, M8_MF8_1_MF4_0_tempOut2); inv M8_MF8_1_MF4_0_MXS2_Mux4_0(in4088, M8_MF8_1_MF4_0_MXS2_Not_ContLo); inv M8_MF8_1_MF4_0_MXS2_Mux4_1(in4087, M8_MF8_1_MF4_0_MXS2_Not_ContHi); and3 M8_MF8_1_MF4_0_MXS2_Mux4_2(FXbus_4, M8_MF8_1_MF4_0_MXS2_Not_ContHi, M8_MF8_1_MF4_0_MXS2_Not_ContLo, M8_MF8_1_MF4_0_MXS2_line2); and3 M8_MF8_1_MF4_0_MXS2_Mux4_3(FYbus_4, M8_MF8_1_MF4_0_MXS2_Not_ContHi, in4088, M8_MF8_1_MF4_0_MXS2_line3); and3 M8_MF8_1_MF4_0_MXS2_Mux4_4(in43, in4087, M8_MF8_1_MF4_0_MXS2_Not_ContLo, M8_MF8_1_MF4_0_MXS2_line4); and3 M8_MF8_1_MF4_0_MXS2_Mux4_5(in37, in4087, in4088, M8_MF8_1_MF4_0_MXS2_line5); or4 M8_MF8_1_MF4_0_MXS2_Mux4_6(M8_MF8_1_MF4_0_MXS2_line2, M8_MF8_1_MF4_0_MXS2_line3, M8_MF8_1_MF4_0_MXS2_line4, M8_MF8_1_MF4_0_MXS2_line5, out747); inv M8_MF8_1_MF4_0_MXS3_Mux4_0(in4089, M8_MF8_1_MF4_0_MXS3_Not_ContLo); inv M8_MF8_1_MF4_0_MXS3_Mux4_1(in4090, M8_MF8_1_MF4_0_MXS3_Not_ContHi); and3 M8_MF8_1_MF4_0_MXS3_Mux4_2(FXbus_4, M8_MF8_1_MF4_0_MXS3_Not_ContHi, M8_MF8_1_MF4_0_MXS3_Not_ContLo, M8_MF8_1_MF4_0_MXS3_line2); and3 M8_MF8_1_MF4_0_MXS3_Mux4_3(FYbus_4, M8_MF8_1_MF4_0_MXS3_Not_ContHi, in4089, M8_MF8_1_MF4_0_MXS3_line3); and3 M8_MF8_1_MF4_0_MXS3_Mux4_4(in43, in4090, M8_MF8_1_MF4_0_MXS3_Not_ContLo, M8_MF8_1_MF4_0_MXS3_line4); and3 M8_MF8_1_MF4_0_MXS3_Mux4_5(in37, in4090, in4089, M8_MF8_1_MF4_0_MXS3_line5); or4 M8_MF8_1_MF4_0_MXS3_Mux4_6(M8_MF8_1_MF4_0_MXS3_line2, M8_MF8_1_MF4_0_MXS3_line3, M8_MF8_1_MF4_0_MXS3_line4, M8_MF8_1_MF4_0_MXS3_line5, out787); and2 M8_MF8_1_MF4_0_MXS4(M8_MF8_1_MF4_0_tempOut1, in137, out642); and2 M8_MF8_1_MF4_0_MXS5(M8_MF8_1_MF4_0_tempOut2, in137, out676); inv M8_MF8_1_MF4_1_MXS0_Mux4_0(in1689, M8_MF8_1_MF4_1_MXS0_Not_ContLo); inv M8_MF8_1_MF4_1_MXS0_Mux4_1(in1690, M8_MF8_1_MF4_1_MXS0_Not_ContHi); and3 M8_MF8_1_MF4_1_MXS0_Mux4_2(FXbus_5, M8_MF8_1_MF4_1_MXS0_Not_ContHi, M8_MF8_1_MF4_1_MXS0_Not_ContLo, M8_MF8_1_MF4_1_MXS0_line2); and3 M8_MF8_1_MF4_1_MXS0_Mux4_3(FYbus_5, M8_MF8_1_MF4_1_MXS0_Not_ContHi, in1689, M8_MF8_1_MF4_1_MXS0_line3); and3 M8_MF8_1_MF4_1_MXS0_Mux4_4(in203, in1690, M8_MF8_1_MF4_1_MXS0_Not_ContLo, M8_MF8_1_MF4_1_MXS0_line4); and3 M8_MF8_1_MF4_1_MXS0_Mux4_5(in173, in1690, in1689, M8_MF8_1_MF4_1_MXS0_line5); or4 M8_MF8_1_MF4_1_MXS0_Mux4_6(M8_MF8_1_MF4_1_MXS0_line2, M8_MF8_1_MF4_1_MXS0_line3, M8_MF8_1_MF4_1_MXS0_line4, M8_MF8_1_MF4_1_MXS0_line5, M8_MF8_1_MF4_1_tempOut1); inv M8_MF8_1_MF4_1_MXS1_Mux4_0(in1691, M8_MF8_1_MF4_1_MXS1_Not_ContLo); inv M8_MF8_1_MF4_1_MXS1_Mux4_1(in1694, M8_MF8_1_MF4_1_MXS1_Not_ContHi); and3 M8_MF8_1_MF4_1_MXS1_Mux4_2(FXbus_5, M8_MF8_1_MF4_1_MXS1_Not_ContHi, M8_MF8_1_MF4_1_MXS1_Not_ContLo, M8_MF8_1_MF4_1_MXS1_line2); and3 M8_MF8_1_MF4_1_MXS1_Mux4_3(FYbus_5, M8_MF8_1_MF4_1_MXS1_Not_ContHi, in1691, M8_MF8_1_MF4_1_MXS1_line3); and3 M8_MF8_1_MF4_1_MXS1_Mux4_4(in203, in1694, M8_MF8_1_MF4_1_MXS1_Not_ContLo, M8_MF8_1_MF4_1_MXS1_line4); and3 M8_MF8_1_MF4_1_MXS1_Mux4_5(in173, in1694, in1691, M8_MF8_1_MF4_1_MXS1_line5); or4 M8_MF8_1_MF4_1_MXS1_Mux4_6(M8_MF8_1_MF4_1_MXS1_line2, M8_MF8_1_MF4_1_MXS1_line3, M8_MF8_1_MF4_1_MXS1_line4, M8_MF8_1_MF4_1_MXS1_line5, M8_MF8_1_MF4_1_tempOut2); inv M8_MF8_1_MF4_1_MXS2_Mux4_0(in4088, M8_MF8_1_MF4_1_MXS2_Not_ContLo); inv M8_MF8_1_MF4_1_MXS2_Mux4_1(in4087, M8_MF8_1_MF4_1_MXS2_Not_ContHi); and3 M8_MF8_1_MF4_1_MXS2_Mux4_2(FXbus_5, M8_MF8_1_MF4_1_MXS2_Not_ContHi, M8_MF8_1_MF4_1_MXS2_Not_ContLo, M8_MF8_1_MF4_1_MXS2_line2); and3 M8_MF8_1_MF4_1_MXS2_Mux4_3(FYbus_5, M8_MF8_1_MF4_1_MXS2_Not_ContHi, in4088, M8_MF8_1_MF4_1_MXS2_line3); and3 M8_MF8_1_MF4_1_MXS2_Mux4_4(in91, in4087, M8_MF8_1_MF4_1_MXS2_Not_ContLo, M8_MF8_1_MF4_1_MXS2_line4); and3 M8_MF8_1_MF4_1_MXS2_Mux4_5(in40, in4087, in4088, M8_MF8_1_MF4_1_MXS2_line5); or4 M8_MF8_1_MF4_1_MXS2_Mux4_6(M8_MF8_1_MF4_1_MXS2_line2, M8_MF8_1_MF4_1_MXS2_line3, M8_MF8_1_MF4_1_MXS2_line4, M8_MF8_1_MF4_1_MXS2_line5, out742); inv M8_MF8_1_MF4_1_MXS3_Mux4_0(in4089, M8_MF8_1_MF4_1_MXS3_Not_ContLo); inv M8_MF8_1_MF4_1_MXS3_Mux4_1(in4090, M8_MF8_1_MF4_1_MXS3_Not_ContHi); and3 M8_MF8_1_MF4_1_MXS3_Mux4_2(FXbus_5, M8_MF8_1_MF4_1_MXS3_Not_ContHi, M8_MF8_1_MF4_1_MXS3_Not_ContLo, M8_MF8_1_MF4_1_MXS3_line2); and3 M8_MF8_1_MF4_1_MXS3_Mux4_3(FYbus_5, M8_MF8_1_MF4_1_MXS3_Not_ContHi, in4089, M8_MF8_1_MF4_1_MXS3_line3); and3 M8_MF8_1_MF4_1_MXS3_Mux4_4(in91, in4090, M8_MF8_1_MF4_1_MXS3_Not_ContLo, M8_MF8_1_MF4_1_MXS3_line4); and3 M8_MF8_1_MF4_1_MXS3_Mux4_5(in40, in4090, in4089, M8_MF8_1_MF4_1_MXS3_line5); or4 M8_MF8_1_MF4_1_MXS3_Mux4_6(M8_MF8_1_MF4_1_MXS3_line2, M8_MF8_1_MF4_1_MXS3_line3, M8_MF8_1_MF4_1_MXS3_line4, M8_MF8_1_MF4_1_MXS3_line5, out782); and2 M8_MF8_1_MF4_1_MXS4(M8_MF8_1_MF4_1_tempOut1, in137, out645); and2 M8_MF8_1_MF4_1_MXS5(M8_MF8_1_MF4_1_tempOut2, in137, out679); inv M8_MF8_1_MF4_2_MXS0_Mux4_0(in1689, M8_MF8_1_MF4_2_MXS0_Not_ContLo); inv M8_MF8_1_MF4_2_MXS0_Mux4_1(in1690, M8_MF8_1_MF4_2_MXS0_Not_ContHi); and3 M8_MF8_1_MF4_2_MXS0_Mux4_2(FXbus_6, M8_MF8_1_MF4_2_MXS0_Not_ContHi, M8_MF8_1_MF4_2_MXS0_Not_ContLo, M8_MF8_1_MF4_2_MXS0_line2); and3 M8_MF8_1_MF4_2_MXS0_Mux4_3(FYbus_6, M8_MF8_1_MF4_2_MXS0_Not_ContHi, in1689, M8_MF8_1_MF4_2_MXS0_line3); and3 M8_MF8_1_MF4_2_MXS0_Mux4_4(in197, in1690, M8_MF8_1_MF4_2_MXS0_Not_ContLo, M8_MF8_1_MF4_2_MXS0_line4); and3 M8_MF8_1_MF4_2_MXS0_Mux4_5(in167, in1690, in1689, M8_MF8_1_MF4_2_MXS0_line5); or4 M8_MF8_1_MF4_2_MXS0_Mux4_6(M8_MF8_1_MF4_2_MXS0_line2, M8_MF8_1_MF4_2_MXS0_line3, M8_MF8_1_MF4_2_MXS0_line4, M8_MF8_1_MF4_2_MXS0_line5, M8_MF8_1_MF4_2_tempOut1); inv M8_MF8_1_MF4_2_MXS1_Mux4_0(in1691, M8_MF8_1_MF4_2_MXS1_Not_ContLo); inv M8_MF8_1_MF4_2_MXS1_Mux4_1(in1694, M8_MF8_1_MF4_2_MXS1_Not_ContHi); and3 M8_MF8_1_MF4_2_MXS1_Mux4_2(FXbus_6, M8_MF8_1_MF4_2_MXS1_Not_ContHi, M8_MF8_1_MF4_2_MXS1_Not_ContLo, M8_MF8_1_MF4_2_MXS1_line2); and3 M8_MF8_1_MF4_2_MXS1_Mux4_3(FYbus_6, M8_MF8_1_MF4_2_MXS1_Not_ContHi, in1691, M8_MF8_1_MF4_2_MXS1_line3); and3 M8_MF8_1_MF4_2_MXS1_Mux4_4(in197, in1694, M8_MF8_1_MF4_2_MXS1_Not_ContLo, M8_MF8_1_MF4_2_MXS1_line4); and3 M8_MF8_1_MF4_2_MXS1_Mux4_5(in167, in1694, in1691, M8_MF8_1_MF4_2_MXS1_line5); or4 M8_MF8_1_MF4_2_MXS1_Mux4_6(M8_MF8_1_MF4_2_MXS1_line2, M8_MF8_1_MF4_2_MXS1_line3, M8_MF8_1_MF4_2_MXS1_line4, M8_MF8_1_MF4_2_MXS1_line5, M8_MF8_1_MF4_2_tempOut2); inv M8_MF8_1_MF4_2_MXS2_Mux4_0(in4088, M8_MF8_1_MF4_2_MXS2_Not_ContLo); inv M8_MF8_1_MF4_2_MXS2_Mux4_1(in4087, M8_MF8_1_MF4_2_MXS2_Not_ContHi); and3 M8_MF8_1_MF4_2_MXS2_Mux4_2(FXbus_6, M8_MF8_1_MF4_2_MXS2_Not_ContHi, M8_MF8_1_MF4_2_MXS2_Not_ContLo, M8_MF8_1_MF4_2_MXS2_line2); and3 M8_MF8_1_MF4_2_MXS2_Mux4_3(FYbus_6, M8_MF8_1_MF4_2_MXS2_Not_ContHi, in4088, M8_MF8_1_MF4_2_MXS2_line3); and3 M8_MF8_1_MF4_2_MXS2_Mux4_4(in100, in4087, M8_MF8_1_MF4_2_MXS2_Not_ContLo, M8_MF8_1_MF4_2_MXS2_line4); and3 M8_MF8_1_MF4_2_MXS2_Mux4_5(in103, in4087, in4088, M8_MF8_1_MF4_2_MXS2_line5); or4 M8_MF8_1_MF4_2_MXS2_Mux4_6(M8_MF8_1_MF4_2_MXS2_line2, M8_MF8_1_MF4_2_MXS2_line3, M8_MF8_1_MF4_2_MXS2_line4, M8_MF8_1_MF4_2_MXS2_line5, out737); inv M8_MF8_1_MF4_2_MXS3_Mux4_0(in4089, M8_MF8_1_MF4_2_MXS3_Not_ContLo); inv M8_MF8_1_MF4_2_MXS3_Mux4_1(in4090, M8_MF8_1_MF4_2_MXS3_Not_ContHi); and3 M8_MF8_1_MF4_2_MXS3_Mux4_2(FXbus_6, M8_MF8_1_MF4_2_MXS3_Not_ContHi, M8_MF8_1_MF4_2_MXS3_Not_ContLo, M8_MF8_1_MF4_2_MXS3_line2); and3 M8_MF8_1_MF4_2_MXS3_Mux4_3(FYbus_6, M8_MF8_1_MF4_2_MXS3_Not_ContHi, in4089, M8_MF8_1_MF4_2_MXS3_line3); and3 M8_MF8_1_MF4_2_MXS3_Mux4_4(in100, in4090, M8_MF8_1_MF4_2_MXS3_Not_ContLo, M8_MF8_1_MF4_2_MXS3_line4); and3 M8_MF8_1_MF4_2_MXS3_Mux4_5(in103, in4090, in4089, M8_MF8_1_MF4_2_MXS3_line5); or4 M8_MF8_1_MF4_2_MXS3_Mux4_6(M8_MF8_1_MF4_2_MXS3_line2, M8_MF8_1_MF4_2_MXS3_line3, M8_MF8_1_MF4_2_MXS3_line4, M8_MF8_1_MF4_2_MXS3_line5, out777); and2 M8_MF8_1_MF4_2_MXS4(M8_MF8_1_MF4_2_tempOut1, in137, out648); and2 M8_MF8_1_MF4_2_MXS5(M8_MF8_1_MF4_2_tempOut2, in137, out682); inv M8_MF8_1_MF8_3_MXS0_Mux4_0(in1689, M8_MF8_1_MF8_3_MXS0_Not_ContLo); inv M8_MF8_1_MF8_3_MXS0_Mux4_1(in1690, M8_MF8_1_MF8_3_MXS0_Not_ContHi); and3 M8_MF8_1_MF8_3_MXS0_Mux4_2(FXbus_7, M8_MF8_1_MF8_3_MXS0_Not_ContHi, M8_MF8_1_MF8_3_MXS0_Not_ContLo, M8_MF8_1_MF8_3_MXS0_line2); and3 M8_MF8_1_MF8_3_MXS0_Mux4_3(FYbus_7, M8_MF8_1_MF8_3_MXS0_Not_ContHi, in1689, M8_MF8_1_MF8_3_MXS0_line3); and3 M8_MF8_1_MF8_3_MXS0_Mux4_4(in194, in1690, M8_MF8_1_MF8_3_MXS0_Not_ContLo, M8_MF8_1_MF8_3_MXS0_line4); and3 M8_MF8_1_MF8_3_MXS0_Mux4_5(in164, in1690, in1689, M8_MF8_1_MF8_3_MXS0_line5); or4 M8_MF8_1_MF8_3_MXS0_Mux4_6(M8_MF8_1_MF8_3_MXS0_line2, M8_MF8_1_MF8_3_MXS0_line3, M8_MF8_1_MF8_3_MXS0_line4, M8_MF8_1_MF8_3_MXS0_line5, M8_MF8_1_MF8_3_tempOut1); inv M8_MF8_1_MF8_3_MXS1_Mux4_0(in1691, M8_MF8_1_MF8_3_MXS1_Not_ContLo); inv M8_MF8_1_MF8_3_MXS1_Mux4_1(in1694, M8_MF8_1_MF8_3_MXS1_Not_ContHi); and3 M8_MF8_1_MF8_3_MXS1_Mux4_2(FXbus_7, M8_MF8_1_MF8_3_MXS1_Not_ContHi, M8_MF8_1_MF8_3_MXS1_Not_ContLo, M8_MF8_1_MF8_3_MXS1_line2); and3 M8_MF8_1_MF8_3_MXS1_Mux4_3(FYbus_7, M8_MF8_1_MF8_3_MXS1_Not_ContHi, in1691, M8_MF8_1_MF8_3_MXS1_line3); and3 M8_MF8_1_MF8_3_MXS1_Mux4_4(in194, in1694, M8_MF8_1_MF8_3_MXS1_Not_ContLo, M8_MF8_1_MF8_3_MXS1_line4); and3 M8_MF8_1_MF8_3_MXS1_Mux4_5(in164, in1694, in1691, M8_MF8_1_MF8_3_MXS1_line5); or4 M8_MF8_1_MF8_3_MXS1_Mux4_6(M8_MF8_1_MF8_3_MXS1_line2, M8_MF8_1_MF8_3_MXS1_line3, M8_MF8_1_MF8_3_MXS1_line4, M8_MF8_1_MF8_3_MXS1_line5, M8_MF8_1_MF8_3_tempOut2); inv M8_MF8_1_MF8_3_MXS2_Mux4_0(in4088, M8_MF8_1_MF8_3_MXS2_Not_ContLo); inv M8_MF8_1_MF8_3_MXS2_Mux4_1(in4087, M8_MF8_1_MF8_3_MXS2_Not_ContHi); and3 M8_MF8_1_MF8_3_MXS2_Mux4_2(FXbus_7, M8_MF8_1_MF8_3_MXS2_Not_ContHi, M8_MF8_1_MF8_3_MXS2_Not_ContLo, M8_MF8_1_MF8_3_MXS2_line2); and3 M8_MF8_1_MF8_3_MXS2_Mux4_3(FYbus_7, M8_MF8_1_MF8_3_MXS2_Not_ContHi, in4088, M8_MF8_1_MF8_3_MXS2_line3); and3 M8_MF8_1_MF8_3_MXS2_Mux4_4(in46, in4087, M8_MF8_1_MF8_3_MXS2_Not_ContLo, M8_MF8_1_MF8_3_MXS2_line4); and3 M8_MF8_1_MF8_3_MXS2_Mux4_5(in49, in4087, in4088, M8_MF8_1_MF8_3_MXS2_line5); or4 M8_MF8_1_MF8_3_MXS2_Mux4_6(M8_MF8_1_MF8_3_MXS2_line2, M8_MF8_1_MF8_3_MXS2_line3, M8_MF8_1_MF8_3_MXS2_line4, M8_MF8_1_MF8_3_MXS2_line5, out732); inv M8_MF8_1_MF8_3_MXS3_Mux4_0(in4089, M8_MF8_1_MF8_3_MXS3_Not_ContLo); inv M8_MF8_1_MF8_3_MXS3_Mux4_1(in4090, M8_MF8_1_MF8_3_MXS3_Not_ContHi); and3 M8_MF8_1_MF8_3_MXS3_Mux4_2(FXbus_7, M8_MF8_1_MF8_3_MXS3_Not_ContHi, M8_MF8_1_MF8_3_MXS3_Not_ContLo, M8_MF8_1_MF8_3_MXS3_line2); and3 M8_MF8_1_MF8_3_MXS3_Mux4_3(FYbus_7, M8_MF8_1_MF8_3_MXS3_Not_ContHi, in4089, M8_MF8_1_MF8_3_MXS3_line3); and3 M8_MF8_1_MF8_3_MXS3_Mux4_4(in46, in4090, M8_MF8_1_MF8_3_MXS3_Not_ContLo, M8_MF8_1_MF8_3_MXS3_line4); and3 M8_MF8_1_MF8_3_MXS3_Mux4_5(in49, in4090, in4089, M8_MF8_1_MF8_3_MXS3_line5); or4 M8_MF8_1_MF8_3_MXS3_Mux4_6(M8_MF8_1_MF8_3_MXS3_line2, M8_MF8_1_MF8_3_MXS3_line3, M8_MF8_1_MF8_3_MXS3_line4, M8_MF8_1_MF8_3_MXS3_line5, out772); and2 M8_MF8_1_MF8_3_MXS4(M8_MF8_1_MF8_3_tempOut1, in137, out651); and2 M8_MF8_1_MF8_3_MXS5(M8_MF8_1_MF8_3_tempOut2, in137, out685); inv M8_MF8_2_MXS0_Mux4_0(in1689, M8_MF8_2_MXS0_Not_ContLo); inv M8_MF8_2_MXS0_Mux4_1(in1690, M8_MF8_2_MXS0_Not_ContHi); and3 M8_MF8_2_MXS0_Mux4_2(FXbus_8, M8_MF8_2_MXS0_Not_ContHi, M8_MF8_2_MXS0_Not_ContLo, M8_MF8_2_MXS0_line2); and3 M8_MF8_2_MXS0_Mux4_3(FYbus_8, M8_MF8_2_MXS0_Not_ContHi, in1689, M8_MF8_2_MXS0_line3); and3 M8_MF8_2_MXS0_Mux4_4(in191, in1690, M8_MF8_2_MXS0_Not_ContLo, M8_MF8_2_MXS0_line4); and3 M8_MF8_2_MXS0_Mux4_5(in161, in1690, in1689, M8_MF8_2_MXS0_line5); or4 M8_MF8_2_MXS0_Mux4_6(M8_MF8_2_MXS0_line2, M8_MF8_2_MXS0_line3, M8_MF8_2_MXS0_line4, M8_MF8_2_MXS0_line5, M8_MF8_2_tempOut1); inv M8_MF8_2_MXS1_Mux4_0(in1691, M8_MF8_2_MXS1_Not_ContLo); inv M8_MF8_2_MXS1_Mux4_1(in1694, M8_MF8_2_MXS1_Not_ContHi); and3 M8_MF8_2_MXS1_Mux4_2(FXbus_8, M8_MF8_2_MXS1_Not_ContHi, M8_MF8_2_MXS1_Not_ContLo, M8_MF8_2_MXS1_line2); and3 M8_MF8_2_MXS1_Mux4_3(FYbus_8, M8_MF8_2_MXS1_Not_ContHi, in1691, M8_MF8_2_MXS1_line3); and3 M8_MF8_2_MXS1_Mux4_4(in191, in1694, M8_MF8_2_MXS1_Not_ContLo, M8_MF8_2_MXS1_line4); and3 M8_MF8_2_MXS1_Mux4_5(in161, in1694, in1691, M8_MF8_2_MXS1_line5); or4 M8_MF8_2_MXS1_Mux4_6(M8_MF8_2_MXS1_line2, M8_MF8_2_MXS1_line3, M8_MF8_2_MXS1_line4, M8_MF8_2_MXS1_line5, M8_MF8_2_tempOut2); inv M8_MF8_2_MXS2_Mux4_0(in4088, M8_MF8_2_MXS2_Not_ContLo); inv M8_MF8_2_MXS2_Mux4_1(in4087, M8_MF8_2_MXS2_Not_ContHi); and3 M8_MF8_2_MXS2_Mux4_2(FXbus_8, M8_MF8_2_MXS2_Not_ContHi, M8_MF8_2_MXS2_Not_ContLo, M8_MF8_2_MXS2_line2); and3 M8_MF8_2_MXS2_Mux4_3(FYbus_8, M8_MF8_2_MXS2_Not_ContHi, in4088, M8_MF8_2_MXS2_line3); and3 M8_MF8_2_MXS2_Mux4_4(in109, in4087, M8_MF8_2_MXS2_Not_ContLo, M8_MF8_2_MXS2_line4); and3 M8_MF8_2_MXS2_Mux4_5(in106, in4087, in4088, M8_MF8_2_MXS2_line5); or4 M8_MF8_2_MXS2_Mux4_6(M8_MF8_2_MXS2_line2, M8_MF8_2_MXS2_line3, M8_MF8_2_MXS2_line4, M8_MF8_2_MXS2_line5, out727); inv M8_MF8_2_MXS3_Mux4_0(in4089, M8_MF8_2_MXS3_Not_ContLo); inv M8_MF8_2_MXS3_Mux4_1(in4090, M8_MF8_2_MXS3_Not_ContHi); and3 M8_MF8_2_MXS3_Mux4_2(FXbus_8, M8_MF8_2_MXS3_Not_ContHi, M8_MF8_2_MXS3_Not_ContLo, M8_MF8_2_MXS3_line2); and3 M8_MF8_2_MXS3_Mux4_3(FYbus_8, M8_MF8_2_MXS3_Not_ContHi, in4089, M8_MF8_2_MXS3_line3); and3 M8_MF8_2_MXS3_Mux4_4(in109, in4090, M8_MF8_2_MXS3_Not_ContLo, M8_MF8_2_MXS3_line4); and3 M8_MF8_2_MXS3_Mux4_5(in106, in4090, in4089, M8_MF8_2_MXS3_line5); or4 M8_MF8_2_MXS3_Mux4_6(M8_MF8_2_MXS3_line2, M8_MF8_2_MXS3_line3, M8_MF8_2_MXS3_line4, M8_MF8_2_MXS3_line5, out712); and2 M8_MF8_2_MXS4(M8_MF8_2_tempOut1, in137, out654); and2 M8_MF8_2_MXS5(M8_MF8_2_tempOut2, in137, out688); inv M9_Inv9_0_Inv4_0(FXbus_0, out822); inv M9_Inv9_0_Inv4_1(FXbus_1, out838); inv M9_Inv9_0_Inv4_2(FXbus_2, out836); inv M9_Inv9_0_Inv4_3(FXbus_3, out834); inv M9_Inv9_1_Inv4_0(FXbus_4, out832); inv M9_Inv9_1_Inv4_1(FXbus_5, out830); inv M9_Inv9_1_Inv4_2(FXbus_6, out828); inv M9_Inv9_1_Inv4_3(FXbus_7, out826); inv M9_Inv9_2(FXbus_8, out824); inv M10_Inv9_0_Inv4_0(FYbus_0, out861); inv M10_Inv9_0_Inv4_1(FYbus_1, out877); inv M10_Inv9_0_Inv4_2(FYbus_2, out875); inv M10_Inv9_0_Inv4_3(FYbus_3, out873); inv M10_Inv9_1_Inv4_0(FYbus_4, out871); inv M10_Inv9_1_Inv4_1(FYbus_5, out869); inv M10_Inv9_1_Inv4_2(FYbus_6, out867); inv M10_Inv9_1_Inv4_3(FYbus_7, out865); inv M10_Inv9_2(FYbus_8, out863); nor9 M11_ZF0_n9(SumXbus_0, SumXbus_1, SumXbus_2, SumXbus_3, SumXbus_4, SumXbus_5, SumXbus_6, SumXbus_7, SumXbus_8, out585); nor9 M11_ZF1_n9(SumYbus_0, SumYbus_1, SumYbus_2, SumYbus_3, SumYbus_4, SumYbus_5, SumYbus_6, SumYbus_7, SumYbus_8, out575); nor9 M11_ZF2_n9(LogicXbus_0, LogicXbus_1, LogicXbus_2, LogicXbus_3, LogicXbus_4, LogicXbus_5, LogicXbus_6, LogicXbus_7, LogicXbus_8, out598); nor9 M11_ZF3_n9(LogicYbus_0, LogicYbus_1, LogicYbus_2, LogicYbus_3, LogicYbus_4, LogicYbus_5, LogicYbus_6, LogicYbus_7, LogicYbus_8, out610); inv M12_BPC0_Mux2_0(in332, M12_BPC0_Not_ContIn); and2 M12_BPC0_Mux2_1(in369, M12_BPC0_Not_ContIn, M12_BPC0_line1); and2 M12_BPC0_Mux2_2(in372, in332, M12_BPC0_line2); or2 M12_BPC0_Mux2_3(M12_BPC0_line1, M12_BPC0_line2, M12_ParX); inv M12_BPC1_Mux2_0(in335, M12_BPC1_Not_ContIn); and2 M12_BPC1_Mux2_1(in289, M12_BPC1_Not_ContIn, M12_BPC1_line1); and2 M12_BPC1_Mux2_2(in292, in335, M12_BPC1_line2); or2 M12_BPC1_Mux2_3(M12_BPC1_line1, M12_BPC1_line2, M12_ParY); inv M12_BPC2_PT0_Xo0(Xbus_5, M12_BPC2_PT0_NotA); inv M12_BPC2_PT0_Xo1(Xbus_6, M12_BPC2_PT0_NotB); nand2 M12_BPC2_PT0_Xo2(M12_BPC2_PT0_NotA, Xbus_6, M12_BPC2_PT0_line2); nand2 M12_BPC2_PT0_Xo3(M12_BPC2_PT0_NotB, Xbus_5, M12_BPC2_PT0_line3); nand2 M12_BPC2_PT0_Xo4(M12_BPC2_PT0_line2, M12_BPC2_PT0_line3, M12_BPC2_line0); inv M12_BPC2_PT1_Xo0(Xbus_7, M12_BPC2_PT1_NotA); inv M12_BPC2_PT1_Xo1(Xbus_8, M12_BPC2_PT1_NotB); nand2 M12_BPC2_PT1_Xo2(M12_BPC2_PT1_NotA, Xbus_8, M12_BPC2_PT1_line2); nand2 M12_BPC2_PT1_Xo3(M12_BPC2_PT1_NotB, Xbus_7, M12_BPC2_PT1_line3); nand2 M12_BPC2_PT1_Xo4(M12_BPC2_PT1_line2, M12_BPC2_PT1_line3, M12_BPC2_line1); inv M12_BPC2_PT2_Xo0(Xbus_0, M12_BPC2_PT2_NotA); inv M12_BPC2_PT2_Xo1(M12_ParX, M12_BPC2_PT2_NotB); nand2 M12_BPC2_PT2_Xo2(M12_BPC2_PT2_NotA, M12_ParX, M12_BPC2_PT2_line2); nand2 M12_BPC2_PT2_Xo3(M12_BPC2_PT2_NotB, Xbus_0, M12_BPC2_PT2_line3); nand2 M12_BPC2_PT2_Xo4(M12_BPC2_PT2_line2, M12_BPC2_PT2_line3, M12_BPC2_line2); inv M12_BPC2_PT3_Xo0(Xbus_1, M12_BPC2_PT3_NotA); inv M12_BPC2_PT3_Xo1(Xbus_2, M12_BPC2_PT3_NotB); nand2 M12_BPC2_PT3_Xo2(M12_BPC2_PT3_NotA, Xbus_2, M12_BPC2_PT3_line2); nand2 M12_BPC2_PT3_Xo3(M12_BPC2_PT3_NotB, Xbus_1, M12_BPC2_PT3_line3); nand2 M12_BPC2_PT3_Xo4(M12_BPC2_PT3_line2, M12_BPC2_PT3_line3, M12_BPC2_line3); inv M12_BPC2_PT4_Xo0(Xbus_3, M12_BPC2_PT4_NotA); inv M12_BPC2_PT4_Xo1(Xbus_4, M12_BPC2_PT4_NotB); nand2 M12_BPC2_PT4_Xo2(M12_BPC2_PT4_NotA, Xbus_4, M12_BPC2_PT4_line2); nand2 M12_BPC2_PT4_Xo3(M12_BPC2_PT4_NotB, Xbus_3, M12_BPC2_PT4_line3); nand2 M12_BPC2_PT4_Xo4(M12_BPC2_PT4_line2, M12_BPC2_PT4_line3, M12_BPC2_line4); inv M12_BPC2_PT5_Xo0(M12_BPC2_line0, M12_BPC2_PT5_NotA); inv M12_BPC2_PT5_Xo1(M12_BPC2_line1, M12_BPC2_PT5_NotB); nand2 M12_BPC2_PT5_Xo2(M12_BPC2_PT5_NotA, M12_BPC2_line1, M12_BPC2_PT5_line2); nand2 M12_BPC2_PT5_Xo3(M12_BPC2_PT5_NotB, M12_BPC2_line0, M12_BPC2_PT5_line3); nand2 M12_BPC2_PT5_Xo4(M12_BPC2_PT5_line2, M12_BPC2_PT5_line3, M12_BPC2_line5); inv M12_BPC2_PT6_Xo3_0(M12_BPC2_line2, M12_BPC2_PT6_NotA); inv M12_BPC2_PT6_Xo3_1(M12_BPC2_line3, M12_BPC2_PT6_NotB); inv M12_BPC2_PT6_Xo3_2(M12_BPC2_line4, M12_BPC2_PT6_NotC); and3 M12_BPC2_PT6_Xo3_3(M12_BPC2_PT6_NotA, M12_BPC2_PT6_NotB, M12_BPC2_line4, M12_BPC2_PT6_line3); and3 M12_BPC2_PT6_Xo3_4(M12_BPC2_PT6_NotA, M12_BPC2_line3, M12_BPC2_PT6_NotC, M12_BPC2_PT6_line4); and3 M12_BPC2_PT6_Xo3_5(M12_BPC2_line2, M12_BPC2_PT6_NotB, M12_BPC2_PT6_NotC, M12_BPC2_PT6_line5); and3 M12_BPC2_PT6_Xo3_6(M12_BPC2_line2, M12_BPC2_line3, M12_BPC2_line4, M12_BPC2_PT6_line6); nor2 M12_BPC2_PT6_Xo3_7(M12_BPC2_PT6_line3, M12_BPC2_PT6_line4, M12_BPC2_PT6_line7); nor2 M12_BPC2_PT6_Xo3_8(M12_BPC2_PT6_line5, M12_BPC2_PT6_line6, M12_BPC2_PT6_line8); nand2 M12_BPC2_PT6_Xo3_9(M12_BPC2_PT6_line7, M12_BPC2_PT6_line8, M12_BPC2_line6); inv M12_BPC2_PT7_Xo0(M12_BPC2_line5, M12_BPC2_PT7_NotA); inv M12_BPC2_PT7_Xo1(M12_BPC2_line6, M12_BPC2_PT7_NotB); nand2 M12_BPC2_PT7_Xo2(M12_BPC2_PT7_NotA, M12_BPC2_line6, M12_BPC2_PT7_line2); nand2 M12_BPC2_PT7_Xo3(M12_BPC2_PT7_NotB, M12_BPC2_line5, M12_BPC2_PT7_line3); nand2 M12_BPC2_PT7_Xo4(M12_BPC2_PT7_line2, M12_BPC2_PT7_line3, out998); inv M12_BPC3_PT0_Xo0(in316, M12_BPC3_PT0_NotA); inv M12_BPC3_PT0_Xo1(in308, M12_BPC3_PT0_NotB); nand2 M12_BPC3_PT0_Xo2(M12_BPC3_PT0_NotA, in308, M12_BPC3_PT0_line2); nand2 M12_BPC3_PT0_Xo3(M12_BPC3_PT0_NotB, in316, M12_BPC3_PT0_line3); nand2 M12_BPC3_PT0_Xo4(M12_BPC3_PT0_line2, M12_BPC3_PT0_line3, M12_BPC3_line0); inv M12_BPC3_PT1_Xo0(in302, M12_BPC3_PT1_NotA); inv M12_BPC3_PT1_Xo1(in293, M12_BPC3_PT1_NotB); nand2 M12_BPC3_PT1_Xo2(M12_BPC3_PT1_NotA, in293, M12_BPC3_PT1_line2); nand2 M12_BPC3_PT1_Xo3(M12_BPC3_PT1_NotB, in302, M12_BPC3_PT1_line3); nand2 M12_BPC3_PT1_Xo4(M12_BPC3_PT1_line2, M12_BPC3_PT1_line3, M12_BPC3_line1); inv M12_BPC3_PT2_Xo0(in361, M12_BPC3_PT2_NotA); inv M12_BPC3_PT2_Xo1(in369, M12_BPC3_PT2_NotB); nand2 M12_BPC3_PT2_Xo2(M12_BPC3_PT2_NotA, in369, M12_BPC3_PT2_line2); nand2 M12_BPC3_PT2_Xo3(M12_BPC3_PT2_NotB, in361, M12_BPC3_PT2_line3); nand2 M12_BPC3_PT2_Xo4(M12_BPC3_PT2_line2, M12_BPC3_PT2_line3, M12_BPC3_line2); inv M12_BPC3_PT3_Xo0(in351, M12_BPC3_PT3_NotA); inv M12_BPC3_PT3_Xo1(in341, M12_BPC3_PT3_NotB); nand2 M12_BPC3_PT3_Xo2(M12_BPC3_PT3_NotA, in341, M12_BPC3_PT3_line2); nand2 M12_BPC3_PT3_Xo3(M12_BPC3_PT3_NotB, in351, M12_BPC3_PT3_line3); nand2 M12_BPC3_PT3_Xo4(M12_BPC3_PT3_line2, M12_BPC3_PT3_line3, M12_BPC3_line3); inv M12_BPC3_PT4_Xo0(vdd, M12_BPC3_PT4_NotA); inv M12_BPC3_PT4_Xo1(in324, M12_BPC3_PT4_NotB); nand2 M12_BPC3_PT4_Xo2(M12_BPC3_PT4_NotA, in324, M12_BPC3_PT4_line2); nand2 M12_BPC3_PT4_Xo3(M12_BPC3_PT4_NotB, vdd, M12_BPC3_PT4_line3); nand2 M12_BPC3_PT4_Xo4(M12_BPC3_PT4_line2, M12_BPC3_PT4_line3, M12_BPC3_line4); inv M12_BPC3_PT5_Xo0(M12_BPC3_line0, M12_BPC3_PT5_NotA); inv M12_BPC3_PT5_Xo1(M12_BPC3_line1, M12_BPC3_PT5_NotB); nand2 M12_BPC3_PT5_Xo2(M12_BPC3_PT5_NotA, M12_BPC3_line1, M12_BPC3_PT5_line2); nand2 M12_BPC3_PT5_Xo3(M12_BPC3_PT5_NotB, M12_BPC3_line0, M12_BPC3_PT5_line3); nand2 M12_BPC3_PT5_Xo4(M12_BPC3_PT5_line2, M12_BPC3_PT5_line3, M12_BPC3_line5); inv M12_BPC3_PT6_Xo3_0(M12_BPC3_line2, M12_BPC3_PT6_NotA); inv M12_BPC3_PT6_Xo3_1(M12_BPC3_line3, M12_BPC3_PT6_NotB); inv M12_BPC3_PT6_Xo3_2(M12_BPC3_line4, M12_BPC3_PT6_NotC); and3 M12_BPC3_PT6_Xo3_3(M12_BPC3_PT6_NotA, M12_BPC3_PT6_NotB, M12_BPC3_line4, M12_BPC3_PT6_line3); and3 M12_BPC3_PT6_Xo3_4(M12_BPC3_PT6_NotA, M12_BPC3_line3, M12_BPC3_PT6_NotC, M12_BPC3_PT6_line4); and3 M12_BPC3_PT6_Xo3_5(M12_BPC3_line2, M12_BPC3_PT6_NotB, M12_BPC3_PT6_NotC, M12_BPC3_PT6_line5); and3 M12_BPC3_PT6_Xo3_6(M12_BPC3_line2, M12_BPC3_line3, M12_BPC3_line4, M12_BPC3_PT6_line6); nor2 M12_BPC3_PT6_Xo3_7(M12_BPC3_PT6_line3, M12_BPC3_PT6_line4, M12_BPC3_PT6_line7); nor2 M12_BPC3_PT6_Xo3_8(M12_BPC3_PT6_line5, M12_BPC3_PT6_line6, M12_BPC3_PT6_line8); nand2 M12_BPC3_PT6_Xo3_9(M12_BPC3_PT6_line7, M12_BPC3_PT6_line8, M12_BPC3_line6); inv M12_BPC3_PT7_Xo0(M12_BPC3_line5, M12_BPC3_PT7_NotA); inv M12_BPC3_PT7_Xo1(M12_BPC3_line6, M12_BPC3_PT7_NotB); nand2 M12_BPC3_PT7_Xo2(M12_BPC3_PT7_NotA, M12_BPC3_line6, M12_BPC3_PT7_line2); nand2 M12_BPC3_PT7_Xo3(M12_BPC3_PT7_NotB, M12_BPC3_line5, M12_BPC3_PT7_line3); nand2 M12_BPC3_PT7_Xo4(M12_BPC3_PT7_line2, M12_BPC3_PT7_line3, out1002); inv M12_BPC4_PT0_Xo0(Ybus_5, M12_BPC4_PT0_NotA); inv M12_BPC4_PT0_Xo1(Ybus_6, M12_BPC4_PT0_NotB); nand2 M12_BPC4_PT0_Xo2(M12_BPC4_PT0_NotA, Ybus_6, M12_BPC4_PT0_line2); nand2 M12_BPC4_PT0_Xo3(M12_BPC4_PT0_NotB, Ybus_5, M12_BPC4_PT0_line3); nand2 M12_BPC4_PT0_Xo4(M12_BPC4_PT0_line2, M12_BPC4_PT0_line3, M12_BPC4_line0); inv M12_BPC4_PT1_Xo0(Ybus_7, M12_BPC4_PT1_NotA); inv M12_BPC4_PT1_Xo1(Ybus_8, M12_BPC4_PT1_NotB); nand2 M12_BPC4_PT1_Xo2(M12_BPC4_PT1_NotA, Ybus_8, M12_BPC4_PT1_line2); nand2 M12_BPC4_PT1_Xo3(M12_BPC4_PT1_NotB, Ybus_7, M12_BPC4_PT1_line3); nand2 M12_BPC4_PT1_Xo4(M12_BPC4_PT1_line2, M12_BPC4_PT1_line3, M12_BPC4_line1); inv M12_BPC4_PT2_Xo0(Ybus_0, M12_BPC4_PT2_NotA); inv M12_BPC4_PT2_Xo1(M12_ParY, M12_BPC4_PT2_NotB); nand2 M12_BPC4_PT2_Xo2(M12_BPC4_PT2_NotA, M12_ParY, M12_BPC4_PT2_line2); nand2 M12_BPC4_PT2_Xo3(M12_BPC4_PT2_NotB, Ybus_0, M12_BPC4_PT2_line3); nand2 M12_BPC4_PT2_Xo4(M12_BPC4_PT2_line2, M12_BPC4_PT2_line3, M12_BPC4_line2); inv M12_BPC4_PT3_Xo0(Ybus_1, M12_BPC4_PT3_NotA); inv M12_BPC4_PT3_Xo1(Ybus_2, M12_BPC4_PT3_NotB); nand2 M12_BPC4_PT3_Xo2(M12_BPC4_PT3_NotA, Ybus_2, M12_BPC4_PT3_line2); nand2 M12_BPC4_PT3_Xo3(M12_BPC4_PT3_NotB, Ybus_1, M12_BPC4_PT3_line3); nand2 M12_BPC4_PT3_Xo4(M12_BPC4_PT3_line2, M12_BPC4_PT3_line3, M12_BPC4_line3); inv M12_BPC4_PT4_Xo0(Ybus_3, M12_BPC4_PT4_NotA); inv M12_BPC4_PT4_Xo1(Ybus_4, M12_BPC4_PT4_NotB); nand2 M12_BPC4_PT4_Xo2(M12_BPC4_PT4_NotA, Ybus_4, M12_BPC4_PT4_line2); nand2 M12_BPC4_PT4_Xo3(M12_BPC4_PT4_NotB, Ybus_3, M12_BPC4_PT4_line3); nand2 M12_BPC4_PT4_Xo4(M12_BPC4_PT4_line2, M12_BPC4_PT4_line3, M12_BPC4_line4); inv M12_BPC4_PT5_Xo0(M12_BPC4_line0, M12_BPC4_PT5_NotA); inv M12_BPC4_PT5_Xo1(M12_BPC4_line1, M12_BPC4_PT5_NotB); nand2 M12_BPC4_PT5_Xo2(M12_BPC4_PT5_NotA, M12_BPC4_line1, M12_BPC4_PT5_line2); nand2 M12_BPC4_PT5_Xo3(M12_BPC4_PT5_NotB, M12_BPC4_line0, M12_BPC4_PT5_line3); nand2 M12_BPC4_PT5_Xo4(M12_BPC4_PT5_line2, M12_BPC4_PT5_line3, M12_BPC4_line5); inv M12_BPC4_PT6_Xo3_0(M12_BPC4_line2, M12_BPC4_PT6_NotA); inv M12_BPC4_PT6_Xo3_1(M12_BPC4_line3, M12_BPC4_PT6_NotB); inv M12_BPC4_PT6_Xo3_2(M12_BPC4_line4, M12_BPC4_PT6_NotC); and3 M12_BPC4_PT6_Xo3_3(M12_BPC4_PT6_NotA, M12_BPC4_PT6_NotB, M12_BPC4_line4, M12_BPC4_PT6_line3); and3 M12_BPC4_PT6_Xo3_4(M12_BPC4_PT6_NotA, M12_BPC4_line3, M12_BPC4_PT6_NotC, M12_BPC4_PT6_line4); and3 M12_BPC4_PT6_Xo3_5(M12_BPC4_line2, M12_BPC4_PT6_NotB, M12_BPC4_PT6_NotC, M12_BPC4_PT6_line5); and3 M12_BPC4_PT6_Xo3_6(M12_BPC4_line2, M12_BPC4_line3, M12_BPC4_line4, M12_BPC4_PT6_line6); nor2 M12_BPC4_PT6_Xo3_7(M12_BPC4_PT6_line3, M12_BPC4_PT6_line4, M12_BPC4_PT6_line7); nor2 M12_BPC4_PT6_Xo3_8(M12_BPC4_PT6_line5, M12_BPC4_PT6_line6, M12_BPC4_PT6_line8); nand2 M12_BPC4_PT6_Xo3_9(M12_BPC4_PT6_line7, M12_BPC4_PT6_line8, M12_BPC4_line6); inv M12_BPC4_PT7_Xo0(M12_BPC4_line5, M12_BPC4_PT7_NotA); inv M12_BPC4_PT7_Xo1(M12_BPC4_line6, M12_BPC4_PT7_NotB); nand2 M12_BPC4_PT7_Xo2(M12_BPC4_PT7_NotA, M12_BPC4_line6, M12_BPC4_PT7_line2); nand2 M12_BPC4_PT7_Xo3(M12_BPC4_PT7_NotB, M12_BPC4_line5, M12_BPC4_PT7_line3); nand2 M12_BPC4_PT7_Xo4(M12_BPC4_PT7_line2, M12_BPC4_PT7_line3, out1000); inv M12_BPC5_PT0_Xo0(in226, M12_BPC5_PT0_NotA); inv M12_BPC5_PT0_Xo1(in218, M12_BPC5_PT0_NotB); nand2 M12_BPC5_PT0_Xo2(M12_BPC5_PT0_NotA, in218, M12_BPC5_PT0_line2); nand2 M12_BPC5_PT0_Xo3(M12_BPC5_PT0_NotB, in226, M12_BPC5_PT0_line3); nand2 M12_BPC5_PT0_Xo4(M12_BPC5_PT0_line2, M12_BPC5_PT0_line3, M12_BPC5_line0); inv M12_BPC5_PT1_Xo0(in210, M12_BPC5_PT1_NotA); inv M12_BPC5_PT1_Xo1(in206, M12_BPC5_PT1_NotB); nand2 M12_BPC5_PT1_Xo2(M12_BPC5_PT1_NotA, in206, M12_BPC5_PT1_line2); nand2 M12_BPC5_PT1_Xo3(M12_BPC5_PT1_NotB, in210, M12_BPC5_PT1_line3); nand2 M12_BPC5_PT1_Xo4(M12_BPC5_PT1_line2, M12_BPC5_PT1_line3, M12_BPC5_line1); inv M12_BPC5_PT2_Xo0(in281, M12_BPC5_PT2_NotA); inv M12_BPC5_PT2_Xo1(in289, M12_BPC5_PT2_NotB); nand2 M12_BPC5_PT2_Xo2(M12_BPC5_PT2_NotA, in289, M12_BPC5_PT2_line2); nand2 M12_BPC5_PT2_Xo3(M12_BPC5_PT2_NotB, in281, M12_BPC5_PT2_line3); nand2 M12_BPC5_PT2_Xo4(M12_BPC5_PT2_line2, M12_BPC5_PT2_line3, M12_BPC5_line2); inv M12_BPC5_PT3_Xo0(in273, M12_BPC5_PT3_NotA); inv M12_BPC5_PT3_Xo1(in265, M12_BPC5_PT3_NotB); nand2 M12_BPC5_PT3_Xo2(M12_BPC5_PT3_NotA, in265, M12_BPC5_PT3_line2); nand2 M12_BPC5_PT3_Xo3(M12_BPC5_PT3_NotB, in273, M12_BPC5_PT3_line3); nand2 M12_BPC5_PT3_Xo4(M12_BPC5_PT3_line2, M12_BPC5_PT3_line3, M12_BPC5_line3); inv M12_BPC5_PT4_Xo0(in257, M12_BPC5_PT4_NotA); inv M12_BPC5_PT4_Xo1(in234, M12_BPC5_PT4_NotB); nand2 M12_BPC5_PT4_Xo2(M12_BPC5_PT4_NotA, in234, M12_BPC5_PT4_line2); nand2 M12_BPC5_PT4_Xo3(M12_BPC5_PT4_NotB, in257, M12_BPC5_PT4_line3); nand2 M12_BPC5_PT4_Xo4(M12_BPC5_PT4_line2, M12_BPC5_PT4_line3, M12_BPC5_line4); inv M12_BPC5_PT5_Xo0(M12_BPC5_line0, M12_BPC5_PT5_NotA); inv M12_BPC5_PT5_Xo1(M12_BPC5_line1, M12_BPC5_PT5_NotB); nand2 M12_BPC5_PT5_Xo2(M12_BPC5_PT5_NotA, M12_BPC5_line1, M12_BPC5_PT5_line2); nand2 M12_BPC5_PT5_Xo3(M12_BPC5_PT5_NotB, M12_BPC5_line0, M12_BPC5_PT5_line3); nand2 M12_BPC5_PT5_Xo4(M12_BPC5_PT5_line2, M12_BPC5_PT5_line3, M12_BPC5_line5); inv M12_BPC5_PT6_Xo3_0(M12_BPC5_line2, M12_BPC5_PT6_NotA); inv M12_BPC5_PT6_Xo3_1(M12_BPC5_line3, M12_BPC5_PT6_NotB); inv M12_BPC5_PT6_Xo3_2(M12_BPC5_line4, M12_BPC5_PT6_NotC); and3 M12_BPC5_PT6_Xo3_3(M12_BPC5_PT6_NotA, M12_BPC5_PT6_NotB, M12_BPC5_line4, M12_BPC5_PT6_line3); and3 M12_BPC5_PT6_Xo3_4(M12_BPC5_PT6_NotA, M12_BPC5_line3, M12_BPC5_PT6_NotC, M12_BPC5_PT6_line4); and3 M12_BPC5_PT6_Xo3_5(M12_BPC5_line2, M12_BPC5_PT6_NotB, M12_BPC5_PT6_NotC, M12_BPC5_PT6_line5); and3 M12_BPC5_PT6_Xo3_6(M12_BPC5_line2, M12_BPC5_line3, M12_BPC5_line4, M12_BPC5_PT6_line6); nor2 M12_BPC5_PT6_Xo3_7(M12_BPC5_PT6_line3, M12_BPC5_PT6_line4, M12_BPC5_PT6_line7); nor2 M12_BPC5_PT6_Xo3_8(M12_BPC5_PT6_line5, M12_BPC5_PT6_line6, M12_BPC5_PT6_line8); nand2 M12_BPC5_PT6_Xo3_9(M12_BPC5_PT6_line7, M12_BPC5_PT6_line8, M12_BPC5_line6); inv M12_BPC5_PT7_Xo0(M12_BPC5_line5, M12_BPC5_PT7_NotA); inv M12_BPC5_PT7_Xo1(M12_BPC5_line6, M12_BPC5_PT7_NotB); nand2 M12_BPC5_PT7_Xo2(M12_BPC5_PT7_NotA, M12_BPC5_line6, M12_BPC5_PT7_line2); nand2 M12_BPC5_PT7_Xo3(M12_BPC5_PT7_NotB, M12_BPC5_line5, M12_BPC5_PT7_line3); nand2 M12_BPC5_PT7_Xo4(M12_BPC5_PT7_line2, M12_BPC5_PT7_line3, out1004); inv M12_BPC6_Inv4_0(out1004, M12_NotParChk_0); inv M12_BPC6_Inv4_1(out1000, M12_NotParChk_1); inv M12_BPC6_Inv4_2(out1002, M12_NotParChk_2); inv M12_BPC6_Inv4_3(out998, M12_NotParChk_3); and5 M12_BPC7(M12_NotParChk_3, M12_NotParChk_2, M12_NotParChk_1, M12_NotParChk_0, in562, M12_line7); and4 M12_BPC8(in386, in559, in556, in552, M12_line8); and3 M12_BPC9(M12_line8, M12_line7, in245, out854); and2 M13_UM13_0_MML0(in27, in31, M13_ContBeta); inv M13_UM13_0_MML1(M13_ContBeta, M13_UM13_0_NotContBeta); inv M13_UM13_0_MML2(in2358, M13_UM13_0_NotContIn2); inv M13_UM13_0_MML3_Mux4_0_Mux2_0(M13_UM13_0_NotContIn2, M13_UM13_0_MML3_Mux4_0_Not_ContIn); and2 M13_UM13_0_MML3_Mux4_0_Mux2_1(in34, M13_UM13_0_MML3_Mux4_0_Not_ContIn, M13_UM13_0_MML3_Mux4_0_line1); and2 M13_UM13_0_MML3_Mux4_0_Mux2_2(in88, M13_UM13_0_NotContIn2, M13_UM13_0_MML3_Mux4_0_line2); or2 M13_UM13_0_MML3_Mux4_0_Mux2_3(M13_UM13_0_MML3_Mux4_0_line1, M13_UM13_0_MML3_Mux4_0_line2, M13_UM13_0_tempOut1_0); inv M13_UM13_0_MML3_Mux4_1_Mux2_0(M13_UM13_0_NotContIn2, M13_UM13_0_MML3_Mux4_1_Not_ContIn); and2 M13_UM13_0_MML3_Mux4_1_Mux2_1(in34, M13_UM13_0_MML3_Mux4_1_Not_ContIn, M13_UM13_0_MML3_Mux4_1_line1); and2 M13_UM13_0_MML3_Mux4_1_Mux2_2(in88, M13_UM13_0_NotContIn2, M13_UM13_0_MML3_Mux4_1_line2); or2 M13_UM13_0_MML3_Mux4_1_Mux2_3(M13_UM13_0_MML3_Mux4_1_line1, M13_UM13_0_MML3_Mux4_1_line2, M13_UM13_0_tempOut1_1); inv M13_UM13_0_MML3_Mux4_2_Mux2_0(M13_UM13_0_NotContIn2, M13_UM13_0_MML3_Mux4_2_Not_ContIn); and2 M13_UM13_0_MML3_Mux4_2_Mux2_1(in83, M13_UM13_0_MML3_Mux4_2_Not_ContIn, M13_UM13_0_MML3_Mux4_2_line1); and2 M13_UM13_0_MML3_Mux4_2_Mux2_2(in83, M13_UM13_0_NotContIn2, M13_UM13_0_MML3_Mux4_2_line2); or2 M13_UM13_0_MML3_Mux4_2_Mux2_3(M13_UM13_0_MML3_Mux4_2_line1, M13_UM13_0_MML3_Mux4_2_line2, M13_UM13_0_tempOut1_2); inv M13_UM13_0_MML3_Mux4_3_Mux2_0(M13_UM13_0_NotContIn2, M13_UM13_0_MML3_Mux4_3_Not_ContIn); and2 M13_UM13_0_MML3_Mux4_3_Mux2_1(in87, M13_UM13_0_MML3_Mux4_3_Not_ContIn, M13_UM13_0_MML3_Mux4_3_line1); and2 M13_UM13_0_MML3_Mux4_3_Mux2_2(in86, M13_UM13_0_NotContIn2, M13_UM13_0_MML3_Mux4_3_line2); or2 M13_UM13_0_MML3_Mux4_3_Mux2_3(M13_UM13_0_MML3_Mux4_3_line1, M13_UM13_0_MML3_Mux4_3_line2, M13_UM13_0_tempOut1_3); inv M13_UM13_0_MML4_Mx4_0_Mux4_0(in2358, M13_UM13_0_MML4_Mx4_0_Not_ContLo); inv M13_UM13_0_MML4_Mx4_0_Mux4_1(M13_UM13_0_NotContBeta, M13_UM13_0_MML4_Mx4_0_Not_ContHi); and3 M13_UM13_0_MML4_Mx4_0_Mux4_2(in26, M13_UM13_0_MML4_Mx4_0_Not_ContHi, M13_UM13_0_MML4_Mx4_0_Not_ContLo, M13_UM13_0_MML4_Mx4_0_line2); and3 M13_UM13_0_MML4_Mx4_0_Mux4_3(in81, M13_UM13_0_MML4_Mx4_0_Not_ContHi, in2358, M13_UM13_0_MML4_Mx4_0_line3); and3 M13_UM13_0_MML4_Mx4_0_Mux4_4(vdd, M13_UM13_0_NotContBeta, M13_UM13_0_MML4_Mx4_0_Not_ContLo, M13_UM13_0_MML4_Mx4_0_line4); and3 M13_UM13_0_MML4_Mx4_0_Mux4_5(vdd, M13_UM13_0_NotContBeta, in2358, M13_UM13_0_MML4_Mx4_0_line5); or4 M13_UM13_0_MML4_Mx4_0_Mux4_6(M13_UM13_0_MML4_Mx4_0_line2, M13_UM13_0_MML4_Mx4_0_line3, M13_UM13_0_MML4_Mx4_0_line4, M13_UM13_0_MML4_Mx4_0_line5, M13_UM13_0_tempOut2_0); inv M13_UM13_0_MML4_Mx4_1_Mux4_0(in2358, M13_UM13_0_MML4_Mx4_1_Not_ContLo); inv M13_UM13_0_MML4_Mx4_1_Mux4_1(M13_UM13_0_NotContBeta, M13_UM13_0_MML4_Mx4_1_Not_ContHi); and3 M13_UM13_0_MML4_Mx4_1_Mux4_2(in24, M13_UM13_0_MML4_Mx4_1_Not_ContHi, M13_UM13_0_MML4_Mx4_1_Not_ContLo, M13_UM13_0_MML4_Mx4_1_line2); and3 M13_UM13_0_MML4_Mx4_1_Mux4_3(in25, M13_UM13_0_MML4_Mx4_1_Not_ContHi, in2358, M13_UM13_0_MML4_Mx4_1_line3); and3 M13_UM13_0_MML4_Mx4_1_Mux4_4(vdd, M13_UM13_0_NotContBeta, M13_UM13_0_MML4_Mx4_1_Not_ContLo, M13_UM13_0_MML4_Mx4_1_line4); and3 M13_UM13_0_MML4_Mx4_1_Mux4_5(vdd, M13_UM13_0_NotContBeta, in2358, M13_UM13_0_MML4_Mx4_1_line5); or4 M13_UM13_0_MML4_Mx4_1_Mux4_6(M13_UM13_0_MML4_Mx4_1_line2, M13_UM13_0_MML4_Mx4_1_line3, M13_UM13_0_MML4_Mx4_1_line4, M13_UM13_0_MML4_Mx4_1_line5, M13_UM13_0_tempOut2_1); inv M13_UM13_0_MML4_Mx4_2_Mux4_0(in2358, M13_UM13_0_MML4_Mx4_2_Not_ContLo); inv M13_UM13_0_MML4_Mx4_2_Mux4_1(M13_UM13_0_NotContBeta, M13_UM13_0_MML4_Mx4_2_Not_ContHi); and3 M13_UM13_0_MML4_Mx4_2_Mux4_2(in82, M13_UM13_0_MML4_Mx4_2_Not_ContHi, M13_UM13_0_MML4_Mx4_2_Not_ContLo, M13_UM13_0_MML4_Mx4_2_line2); and3 M13_UM13_0_MML4_Mx4_2_Mux4_3(in80, M13_UM13_0_MML4_Mx4_2_Not_ContHi, in2358, M13_UM13_0_MML4_Mx4_2_line3); and3 M13_UM13_0_MML4_Mx4_2_Mux4_4(vdd, M13_UM13_0_NotContBeta, M13_UM13_0_MML4_Mx4_2_Not_ContLo, M13_UM13_0_MML4_Mx4_2_line4); and3 M13_UM13_0_MML4_Mx4_2_Mux4_5(vdd, M13_UM13_0_NotContBeta, in2358, M13_UM13_0_MML4_Mx4_2_line5); or4 M13_UM13_0_MML4_Mx4_2_Mux4_6(M13_UM13_0_MML4_Mx4_2_line2, M13_UM13_0_MML4_Mx4_2_line3, M13_UM13_0_MML4_Mx4_2_line4, M13_UM13_0_MML4_Mx4_2_line5, M13_UM13_0_tempOut2_2); inv M13_UM13_0_MML4_Mx4_3_Mux4_0(in2358, M13_UM13_0_MML4_Mx4_3_Not_ContLo); inv M13_UM13_0_MML4_Mx4_3_Mux4_1(M13_UM13_0_NotContBeta, M13_UM13_0_MML4_Mx4_3_Not_ContHi); and3 M13_UM13_0_MML4_Mx4_3_Mux4_2(in79, M13_UM13_0_MML4_Mx4_3_Not_ContHi, M13_UM13_0_MML4_Mx4_3_Not_ContLo, M13_UM13_0_MML4_Mx4_3_line2); and3 M13_UM13_0_MML4_Mx4_3_Mux4_3(in23, M13_UM13_0_MML4_Mx4_3_Not_ContHi, in2358, M13_UM13_0_MML4_Mx4_3_line3); and3 M13_UM13_0_MML4_Mx4_3_Mux4_4(vdd, M13_UM13_0_NotContBeta, M13_UM13_0_MML4_Mx4_3_Not_ContLo, M13_UM13_0_MML4_Mx4_3_line4); and3 M13_UM13_0_MML4_Mx4_3_Mux4_5(vdd, M13_UM13_0_NotContBeta, in2358, M13_UM13_0_MML4_Mx4_3_line5); or4 M13_UM13_0_MML4_Mx4_3_Mux4_6(M13_UM13_0_MML4_Mx4_3_line2, M13_UM13_0_MML4_Mx4_3_line3, M13_UM13_0_MML4_Mx4_3_line4, M13_UM13_0_MML4_Mx4_3_line5, M13_UM13_0_tempOut2_3); and2 M13_UM13_0_MML5_Ma0(M13_UM13_0_tempOut1_0, M13_ContBeta, M13_UM13_0_tempOut3_0); and2 M13_UM13_0_MML5_Ma1(M13_UM13_0_tempOut1_1, M13_ContBeta, M13_UM13_0_tempOut3_1); and2 M13_UM13_0_MML5_Ma2(M13_UM13_0_tempOut1_2, M13_ContBeta, M13_UM13_0_tempOut3_2); and2 M13_UM13_0_MML5_Ma3(M13_UM13_0_tempOut1_3, M13_ContBeta, M13_UM13_0_tempOut3_3); inv M13_UM13_0_MML6_Inv4_0(M13_UM13_0_tempOut3_0, out704); inv M13_UM13_0_MML6_Inv4_1(M13_UM13_0_tempOut3_1, out717); inv M13_UM13_0_MML6_Inv4_2(M13_UM13_0_tempOut3_2, out820); inv M13_UM13_0_MML6_Inv4_3(M13_UM13_0_tempOut3_3, out636); and2 M13_UM13_0_MML7_Ma0(M13_UM13_0_tempOut2_0, in141, out673); and2 M13_UM13_0_MML7_Ma1(M13_UM13_0_tempOut2_1, in141, out639); and2 M13_UM13_0_MML7_Ma2(M13_UM13_0_tempOut2_2, in141, out715); and2 M13_UM13_0_MML7_Ma3(M13_UM13_0_tempOut2_3, in141, out707); inv M13_UM13_0_MML8(Xbus_8, M13_UM13_0_NotMuxIn20); nand2 M13_UM13_0_MML9_Xo0(M13_UM13_0_NotMuxIn20, in132, M13_UM13_0_MML9_NotAB); and2 M13_UM13_0_MML9_Xo1(M13_UM13_0_NotMuxIn20, M13_UM13_0_MML9_NotAB, M13_UM13_0_MML9_line1); and2 M13_UM13_0_MML9_Xo2(M13_UM13_0_MML9_NotAB, in132, M13_UM13_0_MML9_line2); or2 M13_UM13_0_MML9_Xo3(M13_UM13_0_MML9_line1, M13_UM13_0_MML9_line2, M13_UM13_0_tempMuxin); inv M13_UM13_0_MML10_Mux4_0(in3724, M13_UM13_0_MML10_Not_ContLo); inv M13_UM13_0_MML10_Mux4_1(in3717, M13_UM13_0_MML10_Not_ContHi); and3 M13_UM13_0_MML10_Mux4_2(LogicXbus_8, M13_UM13_0_MML10_Not_ContHi, M13_UM13_0_MML10_Not_ContLo, M13_UM13_0_MML10_line2); and3 M13_UM13_0_MML10_Mux4_3(M13_UM13_0_tempMuxin, M13_UM13_0_MML10_Not_ContHi, in3724, M13_UM13_0_MML10_line3); and3 M13_UM13_0_MML10_Mux4_4(in123, in3717, M13_UM13_0_MML10_Not_ContLo, M13_UM13_0_MML10_line4); and3 M13_UM13_0_MML10_Mux4_5(SumXbus_8, in3717, in3724, M13_UM13_0_MML10_line5); or4 M13_UM13_0_MML10_Mux4_6(M13_UM13_0_MML10_line2, M13_UM13_0_MML10_line3, M13_UM13_0_MML10_line4, M13_UM13_0_MML10_line5, M13_UM13_0_tempMuxout); nand2 M13_UM13_0_MML11(in135, in4115, M13_UM13_0_tempMuxcont); and2 M13_UM13_0_MML12(M13_UM13_0_tempMuxcont, M13_UM13_0_tempMuxout, out818); nand2 M13_UM13_0_MML13_Xo0(M13_UM13_0_tempMuxin, SumXbus_8, M13_UM13_0_MML13_NotAB); and2 M13_UM13_0_MML13_Xo1(M13_UM13_0_tempMuxin, M13_UM13_0_MML13_NotAB, M13_UM13_0_MML13_line1); and2 M13_UM13_0_MML13_Xo2(M13_UM13_0_MML13_NotAB, SumXbus_8, M13_UM13_0_MML13_line2); or2 M13_UM13_0_MML13_Xo3(M13_UM13_0_MML13_line1, M13_UM13_0_MML13_line2, out813); inv M13_UM13_0_MML14(SumXbus_8, out623); nand2 M13_UM13_1_MRL0(M13_ContBeta, in140, out656); inv M13_UM13_1_MRL1(in2824, M13_UM13_1_NotMisc1); and2 M13_UM13_1_MRL2(M13_UM13_1_NotMisc1, in27, M13_UM13_1_line2); inv M13_UM13_1_MRL3(M13_UM13_1_line2, out845); and2 M13_UM13_1_MRL4(in141, in145, out810); nand2 M13_UM13_1_MRL5(in373, in1, M13_UM13_1_line6); inv M13_UM13_1_MRL6(M13_UM13_1_line6, out634); inv M13_UM13_1_MRL7(in3173, M13_UM13_1_NotMisc6); and2 M13_UM13_1_MRL8(in136, M13_UM13_1_NotMisc6, out815); and2 M13_UM13_1_MRL9(in386, in556, M13_UM13_1_line12); inv M13_UM13_1_MRL10(M13_UM13_1_line12, out847); and2 M13_UM13_1_MRL11(in552, in562, out601); buffer M13_UM13_1_MRL12_B7_0(in141, out144); buffer M13_UM13_1_MRL12_B7_1(in1, out993); buffer M13_UM13_1_MRL12_B7_2(in3173, out973); buffer M13_UM13_1_MRL12_B7_3(in549, out892); buffer M13_UM13_1_MRL12_B7_4(in137, out926); buffer M13_UM13_1_MRL12_B7_5(in293, out298); buffer M13_UM13_1_MRL12_B7_6(in299, out887); inv M13_UM13_1_MRL13_Inv4_0(in559, out851); inv M13_UM13_1_MRL13_Inv4_1(in552, out849); inv M13_UM13_1_MRL13_Inv4_2(in245, out848); inv M13_UM13_1_MRL13_Inv4_3(in562, out850); inv M13_UM13_1_MRL14_Inv4_0(in366, out600); inv M13_UM13_1_MRL14_Inv4_1(in358, out612); inv M13_UM13_1_MRL14_Inv4_2(in348, out599); inv M13_UM13_1_MRL14_Inv4_3(in338, out611); inv M13_UM13_1_MRL15_Inv4_0(M13_ContBeta, out809); inv M13_UM13_1_MRL15_Inv4_1(in549, out602); inv M13_UM13_1_MRL15_Inv4_2(in545, out594); inv M13_UM13_1_MRL15_Inv4_3(in299, out593); assign out618 = out629; assign out621 = out591; assign out626 = out615; assign out632 = out588; assign out923 = out144; assign out939 = out993; assign out921 = out993; assign out978 = out993; assign out949 = out993; assign out889 = out887; assign out603 = out594; assign out604 = out594; assign out606 = out602; assign vdd = 1'b1; assign gnd = 1'b0; endmodule |
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> > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c6288</TITLE> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C6288 16x16 Multiplier</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="c6288.gif" WIDTH=756 HEIGHT=415></P> <B><P>Statistics: </B>32 inputs; 32 outputs; 2406 gates; <A HREF="c6288bus.html">bus translations</A></P> <B><P>Function: </B>The c6288 benchmark, whose multiplication function was previously known, represents a much larger gate-level circuit that also has a concise functional description. The figure above shows how the 2406 gates form 240 full and half adder cells arranged in a 15x16 matrix. An alternate representation is shown <A HREF="c6288alt.html">here</A>, and the adder cells are detailed <A HREF="c6288fa.html">here</A>. </P> <B><P>Models:</P> <UL> </B><LI><A HREF="c6288.isc">c6288 ISCAS-85 netlist</A><B> </LI> </B><LI><A HREF="c6288.v">c6288 Verilog hierarchical structural model</A><B> </LI> </B><LI><A HREF="c6288b.v">c6288 Verilog hierarchical behavioral model</A> </LI> <LI><A HREF="c6288.tests">c6288 complete gate-level tests</A></LI></UL> </BODY> </HTML> |
Added c6288.isc.
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 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8133 8134 8135 8136 8137 8138 8139 8140 8141 8142 8143 8144 8145 8146 8147 8148 8149 8150 8151 8152 8153 8154 8155 8156 8157 8158 8159 8160 8161 8162 8163 8164 8165 8166 8167 8168 8169 8170 8171 8172 8173 8174 8175 8176 8177 8178 8179 8180 8181 8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 8200 8201 8202 8203 8204 8205 8206 8207 8208 8209 8210 8211 8212 8213 8214 8215 8216 8217 8218 8219 8220 8221 8222 8223 8224 8225 8226 8227 8228 8229 8230 8231 8232 8233 8234 8235 8236 8237 8238 8239 8240 8241 8242 8243 8244 8245 8246 8247 8248 8249 8250 8251 8252 8253 8254 8255 8256 8257 8258 8259 8260 8261 8262 8263 8264 8265 8266 8267 8268 8269 8270 8271 8272 8273 8274 8275 8276 8277 8278 8279 8280 8281 8282 8283 8284 8285 8286 8287 8288 8289 8290 8291 8292 8293 8294 8295 8296 8297 8298 8299 8300 8301 8302 8303 8304 8305 8306 8307 8308 8309 8310 8311 8312 8313 8314 8315 8316 8317 8318 8319 8320 8321 8322 8323 8324 8325 8326 8327 8328 8329 8330 8331 8332 8333 8334 8335 8336 8337 8338 8339 8340 8341 8342 8343 8344 8345 8346 8347 8348 8349 8350 8351 8352 8353 8354 8355 8356 8357 8358 8359 8360 8361 8362 8363 8364 8365 8366 8367 8368 8369 8370 8371 8372 8373 8374 8375 8376 8377 8378 8379 8380 8381 8382 8383 8384 8385 8386 8387 8388 8389 8390 8391 8392 8393 8394 8395 8396 8397 8398 8399 8400 8401 8402 8403 8404 8405 8406 8407 8408 8409 8410 8411 8412 8413 8414 8415 8416 8417 8418 8419 8420 8421 8422 8423 8424 8425 8426 8427 8428 8429 8430 8431 8432 8433 8434 8435 8436 8437 8438 8439 8440 8441 8442 8443 8444 8445 8446 8447 8448 8449 8450 8451 8452 8453 8454 8455 8456 8457 8458 8459 8460 8461 8462 8463 8464 8465 8466 8467 8468 8469 8470 8471 8472 8473 8474 8475 8476 8477 8478 8479 8480 8481 8482 8483 8484 8485 8486 8487 8488 8489 8490 8491 8492 8493 8494 8495 8496 8497 8498 8499 8500 8501 8502 8503 8504 8505 8506 8507 8508 8509 8510 8511 8512 8513 8514 8515 8516 8517 8518 8519 8520 8521 8522 8523 8524 8525 8526 8527 8528 8529 8530 8531 8532 8533 8534 8535 8536 8537 8538 8539 8540 8541 8542 8543 8544 8545 8546 8547 8548 8549 8550 8551 8552 8553 8554 8555 8556 8557 8558 8559 8560 8561 8562 8563 8564 8565 8566 8567 8568 8569 8570 8571 8572 8573 8574 8575 8576 8577 8578 8579 8580 8581 8582 8583 8584 8585 8586 8587 8588 8589 8590 8591 8592 8593 8594 8595 8596 8597 8598 8599 8600 8601 8602 8603 8604 8605 8606 8607 8608 8609 8610 8611 8612 8613 8614 8615 8616 8617 8618 8619 8620 8621 8622 8623 8624 8625 8626 8627 8628 8629 8630 8631 8632 8633 8634 8635 8636 8637 8638 8639 8640 8641 8642 8643 8644 8645 8646 8647 8648 8649 8650 8651 8652 8653 8654 8655 8656 8657 8658 8659 8660 8661 8662 8663 8664 8665 8666 8667 8668 8669 8670 8671 8672 8673 8674 8675 8676 8677 8678 8679 8680 8681 8682 8683 8684 8685 8686 8687 8688 8689 8690 8691 8692 8693 8694 8695 8696 8697 8698 8699 8700 8701 8702 8703 8704 8705 8706 8707 8708 8709 8710 8711 8712 8713 8714 8715 8716 8717 8718 8719 8720 8721 8722 |
* combinational logic example "c6288"
*-------------------------------------------------------------
*
*
* total number of lines in the netlist .............. 6288
* simplistically reduced equivalent fault set size = 7744
* lines from primary input gates ....... 32
* lines from primary output gates ....... 32
* lines from interior gate outputs ...... 2384
* lines from ** 1456 ** fanout stems ... 3840
*
* avg_fanin = 1.99, max_fanin = 2
* avg_fanout = 2.64, max_fanout = 16
*
*
*
*
*
1 1gat inpt 16 0 >sa0 >sa1
2 1f01 from 1gat >sa1
3 1f02 from 1gat >sa1
4 1f03 from 1gat >sa1
5 1f04 from 1gat >sa1
6 1f05 from 1gat >sa1
7 1f06 from 1gat >sa1
8 1f07 from 1gat >sa1
9 1f08 from 1gat >sa1
10 1f09 from 1gat >sa1
11 1f10 from 1gat >sa1
12 1f11 from 1gat >sa1
13 1f12 from 1gat >sa1
14 1f13 from 1gat >sa1
15 1f14 from 1gat >sa1
16 1f15 from 1gat >sa1
17 1f16 from 1gat >sa1
18 18gat inpt 16 0 >sa0 >sa1
19 18f01 from 18gat >sa1
20 18f02 from 18gat >sa1
21 18f03 from 18gat >sa1
22 18f04 from 18gat >sa1
23 18f05 from 18gat >sa1
24 18f06 from 18gat >sa1
25 18f07 from 18gat >sa1
26 18f08 from 18gat >sa1
27 18f09 from 18gat >sa1
28 18f10 from 18gat >sa1
29 18f11 from 18gat >sa1
30 18f12 from 18gat >sa1
31 18f13 from 18gat >sa1
32 18f14 from 18gat >sa1
33 18f15 from 18gat >sa1
34 18f16 from 18gat >sa1
35 35gat inpt 16 0 >sa0 >sa1
36 35f01 from 35gat >sa1
37 35f02 from 35gat >sa1
38 35f03 from 35gat >sa1
39 35f04 from 35gat >sa1
40 35f05 from 35gat >sa1
41 35f06 from 35gat >sa1
42 35f07 from 35gat >sa1
43 35f08 from 35gat >sa1
44 35f09 from 35gat >sa1
45 35f10 from 35gat >sa1
46 35f11 from 35gat >sa1
47 35f12 from 35gat >sa1
48 35f13 from 35gat >sa1
49 35f14 from 35gat >sa1
50 35f15 from 35gat >sa1
51 35f16 from 35gat >sa1
52 52gat inpt 16 0 >sa0 >sa1
53 52f01 from 52gat >sa1
54 52f02 from 52gat >sa1
55 52f03 from 52gat >sa1
56 52f04 from 52gat >sa1
57 52f05 from 52gat >sa1
58 52f06 from 52gat >sa1
59 52f07 from 52gat >sa1
60 52f08 from 52gat >sa1
61 52f09 from 52gat >sa1
62 52f10 from 52gat >sa1
63 52f11 from 52gat >sa1
64 52f12 from 52gat >sa1
65 52f13 from 52gat >sa1
66 52f14 from 52gat >sa1
67 52f15 from 52gat >sa1
68 52f16 from 52gat >sa1
69 69gat inpt 16 0 >sa0 >sa1
70 69f01 from 69gat >sa1
71 69f02 from 69gat >sa1
72 69f03 from 69gat >sa1
73 69f04 from 69gat >sa1
74 69f05 from 69gat >sa1
75 69f06 from 69gat >sa1
76 69f07 from 69gat >sa1
77 69f08 from 69gat >sa1
78 69f09 from 69gat >sa1
79 69f10 from 69gat >sa1
80 69f11 from 69gat >sa1
81 69f12 from 69gat >sa1
82 69f13 from 69gat >sa1
83 69f14 from 69gat >sa1
84 69f15 from 69gat >sa1
85 69f16 from 69gat >sa1
86 86gat inpt 16 0 >sa0 >sa1
87 86f01 from 86gat >sa1
88 86f02 from 86gat >sa1
89 86f03 from 86gat >sa1
90 86f04 from 86gat >sa1
91 86f05 from 86gat >sa1
92 86f06 from 86gat >sa1
93 86f07 from 86gat >sa1
94 86f08 from 86gat >sa1
95 86f09 from 86gat >sa1
96 86f10 from 86gat >sa1
97 86f11 from 86gat >sa1
98 86f12 from 86gat >sa1
99 86f13 from 86gat >sa1
100 86f14 from 86gat >sa1
101 86f15 from 86gat >sa1
102 86f16 from 86gat >sa1
103 103gat inpt 16 0 >sa0 >sa1
104 103f01 from 103gat >sa1
105 103f02 from 103gat >sa1
106 103f03 from 103gat >sa1
107 103f04 from 103gat >sa1
108 103f05 from 103gat >sa1
109 103f06 from 103gat >sa1
110 103f07 from 103gat >sa1
111 103f08 from 103gat >sa1
112 103f09 from 103gat >sa1
113 103f10 from 103gat >sa1
114 103f11 from 103gat >sa1
115 103f12 from 103gat >sa1
116 103f13 from 103gat >sa1
117 103f14 from 103gat >sa1
118 103f15 from 103gat >sa1
119 103f16 from 103gat >sa1
120 120gat inpt 16 0 >sa0 >sa1
121 120f01 from 120gat >sa1
122 120f02 from 120gat >sa1
123 120f03 from 120gat >sa1
124 120f04 from 120gat >sa1
125 120f05 from 120gat >sa1
126 120f06 from 120gat >sa1
127 120f07 from 120gat >sa1
128 120f08 from 120gat >sa1
129 120f09 from 120gat >sa1
130 120f10 from 120gat >sa1
131 120f11 from 120gat >sa1
132 120f12 from 120gat >sa1
133 120f13 from 120gat >sa1
134 120f14 from 120gat >sa1
135 120f15 from 120gat >sa1
136 120f16 from 120gat >sa1
137 137gat inpt 16 0 >sa0 >sa1
138 137f01 from 137gat >sa1
139 137f02 from 137gat >sa1
140 137f03 from 137gat >sa1
141 137f04 from 137gat >sa1
142 137f05 from 137gat >sa1
143 137f06 from 137gat >sa1
144 137f07 from 137gat >sa1
145 137f08 from 137gat >sa1
146 137f09 from 137gat >sa1
147 137f10 from 137gat >sa1
148 137f11 from 137gat >sa1
149 137f12 from 137gat >sa1
150 137f13 from 137gat >sa1
151 137f14 from 137gat >sa1
152 137f15 from 137gat >sa1
153 137f16 from 137gat >sa1
154 154gat inpt 16 0 >sa0 >sa1
155 154f01 from 154gat >sa1
156 154f02 from 154gat >sa1
157 154f03 from 154gat >sa1
158 154f04 from 154gat >sa1
159 154f05 from 154gat >sa1
160 154f06 from 154gat >sa1
161 154f07 from 154gat >sa1
162 154f08 from 154gat >sa1
163 154f09 from 154gat >sa1
164 154f10 from 154gat >sa1
165 154f11 from 154gat >sa1
166 154f12 from 154gat >sa1
167 154f13 from 154gat >sa1
168 154f14 from 154gat >sa1
169 154f15 from 154gat >sa1
170 154f16 from 154gat >sa1
171 171gat inpt 16 0 >sa0 >sa1
172 171f01 from 171gat >sa1
173 171f02 from 171gat >sa1
174 171f03 from 171gat >sa1
175 171f04 from 171gat >sa1
176 171f05 from 171gat >sa1
177 171f06 from 171gat >sa1
178 171f07 from 171gat >sa1
179 171f08 from 171gat >sa1
180 171f09 from 171gat >sa1
181 171f10 from 171gat >sa1
182 171f11 from 171gat >sa1
183 171f12 from 171gat >sa1
184 171f13 from 171gat >sa1
185 171f14 from 171gat >sa1
186 171f15 from 171gat >sa1
187 171f16 from 171gat >sa1
188 188gat inpt 16 0 >sa0 >sa1
189 188f01 from 188gat >sa1
190 188f02 from 188gat >sa1
191 188f03 from 188gat >sa1
192 188f04 from 188gat >sa1
193 188f05 from 188gat >sa1
194 188f06 from 188gat >sa1
195 188f07 from 188gat >sa1
196 188f08 from 188gat >sa1
197 188f09 from 188gat >sa1
198 188f10 from 188gat >sa1
199 188f11 from 188gat >sa1
200 188f12 from 188gat >sa1
201 188f13 from 188gat >sa1
202 188f14 from 188gat >sa1
203 188f15 from 188gat >sa1
204 188f16 from 188gat >sa1
205 205gat inpt 16 0 >sa0 >sa1
206 205f01 from 205gat >sa1
207 205f02 from 205gat >sa1
208 205f03 from 205gat >sa1
209 205f04 from 205gat >sa1
210 205f05 from 205gat >sa1
211 205f06 from 205gat >sa1
212 205f07 from 205gat >sa1
213 205f08 from 205gat >sa1
214 205f09 from 205gat >sa1
215 205f10 from 205gat >sa1
216 205f11 from 205gat >sa1
217 205f12 from 205gat >sa1
218 205f13 from 205gat >sa1
219 205f14 from 205gat >sa1
220 205f15 from 205gat >sa1
221 205f16 from 205gat >sa1
222 222gat inpt 16 0 >sa0 >sa1
223 222f01 from 222gat >sa1
224 222f02 from 222gat >sa1
225 222f03 from 222gat >sa1
226 222f04 from 222gat >sa1
227 222f05 from 222gat >sa1
228 222f06 from 222gat >sa1
229 222f07 from 222gat >sa1
230 222f08 from 222gat >sa1
231 222f09 from 222gat >sa1
232 222f10 from 222gat >sa1
233 222f11 from 222gat >sa1
234 222f12 from 222gat >sa1
235 222f13 from 222gat >sa1
236 222f14 from 222gat >sa1
237 222f15 from 222gat >sa1
238 222f16 from 222gat >sa1
239 239gat inpt 16 0 >sa0 >sa1
240 239f01 from 239gat >sa1
241 239f02 from 239gat >sa1
242 239f03 from 239gat >sa1
243 239f04 from 239gat >sa1
244 239f05 from 239gat >sa1
245 239f06 from 239gat >sa1
246 239f07 from 239gat >sa1
247 239f08 from 239gat >sa1
248 239f09 from 239gat >sa1
249 239f10 from 239gat >sa1
250 239f11 from 239gat >sa1
251 239f12 from 239gat >sa1
252 239f13 from 239gat >sa1
253 239f14 from 239gat >sa1
254 239f15 from 239gat >sa1
255 239f16 from 239gat >sa1
256 256gat inpt 16 0 >sa0 >sa1
257 256f01 from 256gat >sa1
258 256f02 from 256gat >sa1
259 256f03 from 256gat >sa1
260 256f04 from 256gat >sa1
261 256f05 from 256gat >sa1
262 256f06 from 256gat >sa1
263 256f07 from 256gat >sa1
264 256f08 from 256gat >sa1
265 256f09 from 256gat >sa1
266 256f10 from 256gat >sa1
267 256f11 from 256gat >sa1
268 256f12 from 256gat >sa1
269 256f13 from 256gat >sa1
270 256f14 from 256gat >sa1
271 256f15 from 256gat >sa1
272 256f16 from 256gat >sa1
273 273gat inpt 16 0 >sa0 >sa1
274 273f01 from 273gat >sa1
275 273f02 from 273gat >sa1
276 273f03 from 273gat >sa1
277 273f04 from 273gat >sa1
278 273f05 from 273gat >sa1
279 273f06 from 273gat >sa1
280 273f07 from 273gat >sa1
281 273f08 from 273gat >sa1
282 273f09 from 273gat >sa1
283 273f10 from 273gat >sa1
284 273f11 from 273gat >sa1
285 273f12 from 273gat >sa1
286 273f13 from 273gat >sa1
287 273f14 from 273gat >sa1
288 273f15 from 273gat >sa1
289 273f16 from 273gat >sa1
290 290gat inpt 16 0 >sa0 >sa1
291 290f01 from 290gat >sa1
292 290f02 from 290gat >sa1
293 290f03 from 290gat >sa1
294 290f04 from 290gat >sa1
295 290f05 from 290gat >sa1
296 290f06 from 290gat >sa1
297 290f07 from 290gat >sa1
298 290f08 from 290gat >sa1
299 290f09 from 290gat >sa1
300 290f10 from 290gat >sa1
301 290f11 from 290gat >sa1
302 290f12 from 290gat >sa1
303 290f13 from 290gat >sa1
304 290f14 from 290gat >sa1
305 290f15 from 290gat >sa1
306 290f16 from 290gat >sa1
307 307gat inpt 16 0 >sa0 >sa1
308 307f01 from 307gat >sa1
309 307f02 from 307gat >sa1
310 307f03 from 307gat >sa1
311 307f04 from 307gat >sa1
312 307f05 from 307gat >sa1
313 307f06 from 307gat >sa1
314 307f07 from 307gat >sa1
315 307f08 from 307gat >sa1
316 307f09 from 307gat >sa1
317 307f10 from 307gat >sa1
318 307f11 from 307gat >sa1
319 307f12 from 307gat >sa1
320 307f13 from 307gat >sa1
321 307f14 from 307gat >sa1
322 307f15 from 307gat >sa1
323 307f16 from 307gat >sa1
324 324gat inpt 16 0 >sa0 >sa1
325 324f01 from 324gat >sa1
326 324f02 from 324gat >sa1
327 324f03 from 324gat >sa1
328 324f04 from 324gat >sa1
329 324f05 from 324gat >sa1
330 324f06 from 324gat >sa1
331 324f07 from 324gat >sa1
332 324f08 from 324gat >sa1
333 324f09 from 324gat >sa1
334 324f10 from 324gat >sa1
335 324f11 from 324gat >sa1
336 324f12 from 324gat >sa1
337 324f13 from 324gat >sa1
338 324f14 from 324gat >sa1
339 324f15 from 324gat >sa1
340 324f16 from 324gat >sa1
341 341gat inpt 16 0 >sa0 >sa1
342 341f01 from 341gat >sa1
343 341f02 from 341gat >sa1
344 341f03 from 341gat >sa1
345 341f04 from 341gat >sa1
346 341f05 from 341gat >sa1
347 341f06 from 341gat >sa1
348 341f07 from 341gat >sa1
349 341f08 from 341gat >sa1
350 341f09 from 341gat >sa1
351 341f10 from 341gat >sa1
352 341f11 from 341gat >sa1
353 341f12 from 341gat >sa1
354 341f13 from 341gat >sa1
355 341f14 from 341gat >sa1
356 341f15 from 341gat >sa1
357 341f16 from 341gat >sa1
358 358gat inpt 16 0 >sa0 >sa1
359 358f01 from 358gat >sa1
360 358f02 from 358gat >sa1
361 358f03 from 358gat >sa1
362 358f04 from 358gat >sa1
363 358f05 from 358gat >sa1
364 358f06 from 358gat >sa1
365 358f07 from 358gat >sa1
366 358f08 from 358gat >sa1
367 358f09 from 358gat >sa1
368 358f10 from 358gat >sa1
369 358f11 from 358gat >sa1
370 358f12 from 358gat >sa1
371 358f13 from 358gat >sa1
372 358f14 from 358gat >sa1
373 358f15 from 358gat >sa1
374 358f16 from 358gat >sa1
375 375gat inpt 16 0 >sa0 >sa1
376 375f01 from 375gat >sa1
377 375f02 from 375gat >sa1
378 375f03 from 375gat >sa1
379 375f04 from 375gat >sa1
380 375f05 from 375gat >sa1
381 375f06 from 375gat >sa1
382 375f07 from 375gat >sa1
383 375f08 from 375gat >sa1
384 375f09 from 375gat >sa1
385 375f10 from 375gat >sa1
386 375f11 from 375gat >sa1
387 375f12 from 375gat >sa1
388 375f13 from 375gat >sa1
389 375f14 from 375gat >sa1
390 375f15 from 375gat >sa1
391 375f16 from 375gat >sa1
392 392gat inpt 16 0 >sa0 >sa1
393 392f01 from 392gat >sa1
394 392f02 from 392gat >sa1
395 392f03 from 392gat >sa1
396 392f04 from 392gat >sa1
397 392f05 from 392gat >sa1
398 392f06 from 392gat >sa1
399 392f07 from 392gat >sa1
400 392f08 from 392gat >sa1
401 392f09 from 392gat >sa1
402 392f10 from 392gat >sa1
403 392f11 from 392gat >sa1
404 392f12 from 392gat >sa1
405 392f13 from 392gat >sa1
406 392f14 from 392gat >sa1
407 392f15 from 392gat >sa1
408 392f16 from 392gat >sa1
409 409gat inpt 16 0 >sa0 >sa1
410 409f01 from 409gat >sa1
411 409f02 from 409gat >sa1
412 409f03 from 409gat >sa1
413 409f04 from 409gat >sa1
414 409f05 from 409gat >sa1
415 409f06 from 409gat >sa1
416 409f07 from 409gat >sa1
417 409f08 from 409gat >sa1
418 409f09 from 409gat >sa1
419 409f10 from 409gat >sa1
420 409f11 from 409gat >sa1
421 409f12 from 409gat >sa1
422 409f13 from 409gat >sa1
423 409f14 from 409gat >sa1
424 409f15 from 409gat >sa1
425 409f16 from 409gat >sa1
426 426gat inpt 16 0 >sa0 >sa1
427 426f01 from 426gat >sa1
428 426f02 from 426gat >sa1
429 426f03 from 426gat >sa1
430 426f04 from 426gat >sa1
431 426f05 from 426gat >sa1
432 426f06 from 426gat >sa1
433 426f07 from 426gat >sa1
434 426f08 from 426gat >sa1
435 426f09 from 426gat >sa1
436 426f10 from 426gat >sa1
437 426f11 from 426gat >sa1
438 426f12 from 426gat >sa1
439 426f13 from 426gat >sa1
440 426f14 from 426gat >sa1
441 426f15 from 426gat >sa1
442 426f16 from 426gat >sa1
443 443gat inpt 16 0 >sa0 >sa1
444 443f01 from 443gat >sa1
445 443f02 from 443gat >sa1
446 443f03 from 443gat >sa1
447 443f04 from 443gat >sa1
448 443f05 from 443gat >sa1
449 443f06 from 443gat >sa1
450 443f07 from 443gat >sa1
451 443f08 from 443gat >sa1
452 443f09 from 443gat >sa1
453 443f10 from 443gat >sa1
454 443f11 from 443gat >sa1
455 443f12 from 443gat >sa1
456 443f13 from 443gat >sa1
457 443f14 from 443gat >sa1
458 443f15 from 443gat >sa1
459 443f16 from 443gat >sa1
460 460gat inpt 16 0 >sa0 >sa1
461 460f01 from 460gat >sa1
462 460f02 from 460gat >sa1
463 460f03 from 460gat >sa1
464 460f04 from 460gat >sa1
465 460f05 from 460gat >sa1
466 460f06 from 460gat >sa1
467 460f07 from 460gat >sa1
468 460f08 from 460gat >sa1
469 460f09 from 460gat >sa1
470 460f10 from 460gat >sa1
471 460f11 from 460gat >sa1
472 460f12 from 460gat >sa1
473 460f13 from 460gat >sa1
474 460f14 from 460gat >sa1
475 460f15 from 460gat >sa1
476 460f16 from 460gat >sa1
477 477gat inpt 16 0 >sa0 >sa1
478 477f01 from 477gat >sa1
479 477f02 from 477gat >sa1
480 477f03 from 477gat >sa1
481 477f04 from 477gat >sa1
482 477f05 from 477gat >sa1
483 477f06 from 477gat >sa1
484 477f07 from 477gat >sa1
485 477f08 from 477gat >sa1
486 477f09 from 477gat >sa1
487 477f10 from 477gat >sa1
488 477f11 from 477gat >sa1
489 477f12 from 477gat >sa1
490 477f13 from 477gat >sa1
491 477f14 from 477gat >sa1
492 477f15 from 477gat >sa1
493 477f16 from 477gat >sa1
494 494gat inpt 16 0 >sa0 >sa1
495 494f01 from 494gat >sa1
496 494f02 from 494gat >sa1
497 494f03 from 494gat >sa1
498 494f04 from 494gat >sa1
499 494f05 from 494gat >sa1
500 494f06 from 494gat >sa1
501 494f07 from 494gat >sa1
502 494f08 from 494gat >sa1
503 494f09 from 494gat >sa1
504 494f10 from 494gat >sa1
505 494f11 from 494gat >sa1
506 494f12 from 494gat >sa1
507 494f13 from 494gat >sa1
508 494f14 from 494gat >sa1
509 494f15 from 494gat >sa1
510 494f16 from 494gat >sa1
511 511gat inpt 16 0 >sa0 >sa1
512 511f01 from 511gat >sa1
513 511f02 from 511gat >sa1
514 511f03 from 511gat >sa1
515 511f04 from 511gat >sa1
516 511f05 from 511gat >sa1
517 511f06 from 511gat >sa1
518 511f07 from 511gat >sa1
519 511f08 from 511gat >sa1
520 511f09 from 511gat >sa1
521 511f10 from 511gat >sa1
522 511f11 from 511gat >sa1
523 511f12 from 511gat >sa1
524 511f13 from 511gat >sa1
525 511f14 from 511gat >sa1
526 511f15 from 511gat >sa1
527 511f16 from 511gat >sa1
528 528gat inpt 16 0 >sa0 >sa1
529 528f01 from 528gat >sa1
530 528f02 from 528gat >sa1
531 528f03 from 528gat >sa1
532 528f04 from 528gat >sa1
533 528f05 from 528gat >sa1
534 528f06 from 528gat >sa1
535 528f07 from 528gat >sa1
536 528f08 from 528gat >sa1
537 528f09 from 528gat >sa1
538 528f10 from 528gat >sa1
539 528f11 from 528gat >sa1
540 528f12 from 528gat >sa1
541 528f13 from 528gat >sa1
542 528f14 from 528gat >sa1
543 528f15 from 528gat >sa1
544 528f16 from 528gat >sa1
545 545gat and 0 2 >sa0 >sa1
2 274
546 546gat and 2 2 >sa0 >sa1
3 291
547 546f01 from 546gat >sa0
548 546f02 from 546gat >sa0
549 549gat and 2 2 >sa0 >sa1
4 308
550 549f01 from 549gat >sa0
551 549f02 from 549gat >sa0
552 552gat and 2 2 >sa0 >sa1
5 325
553 552f01 from 552gat >sa0
554 552f02 from 552gat >sa0
555 555gat and 2 2 >sa0 >sa1
6 342
556 555f01 from 555gat >sa0
557 555f02 from 555gat >sa0
558 558gat and 2 2 >sa0 >sa1
7 359
559 558f01 from 558gat >sa0
560 558f02 from 558gat >sa0
561 561gat and 2 2 >sa0 >sa1
8 376
562 561f01 from 561gat >sa0
563 561f02 from 561gat >sa0
564 564gat and 2 2 >sa0 >sa1
9 393
565 564f01 from 564gat >sa0
566 564f02 from 564gat >sa0
567 567gat and 2 2 >sa0 >sa1
10 410
568 567f01 from 567gat >sa0
569 567f02 from 567gat >sa0
570 570gat and 2 2 >sa0 >sa1
11 427
571 570f01 from 570gat >sa0
572 570f02 from 570gat >sa0
573 573gat and 2 2 >sa0 >sa1
12 444
574 573f01 from 573gat >sa0
575 573f02 from 573gat >sa0
576 576gat and 2 2 >sa0 >sa1
13 461
577 576f01 from 576gat >sa0
578 576f02 from 576gat >sa0
579 579gat and 2 2 >sa0 >sa1
14 478
580 579f01 from 579gat >sa0
581 579f02 from 579gat >sa0
582 582gat and 2 2 >sa0 >sa1
15 495
583 582f01 from 582gat >sa0
584 582f02 from 582gat >sa0
585 585gat and 2 2 >sa0 >sa1
16 512
586 585f01 from 585gat >sa0
587 585f02 from 585gat >sa0
588 588gat and 2 2 >sa0 >sa1
17 529
589 588f01 from 588gat >sa0
590 588f02 from 588gat >sa0
591 591gat and 2 2 >sa0 >sa1
19 275
592 591f01 from 591gat
593 591f02 from 591gat >sa0
594 594gat and 2 2 >sa0 >sa1
20 292
595 594f01 from 594gat >sa0
596 594f02 from 594gat >sa0
597 597gat and 2 2 >sa0 >sa1
21 309
598 597f01 from 597gat >sa0
599 597f02 from 597gat >sa0
600 600gat and 2 2 >sa0 >sa1
22 326
601 600f01 from 600gat >sa0
602 600f02 from 600gat >sa0
603 603gat and 2 2 >sa0 >sa1
23 343
604 603f01 from 603gat >sa0
605 603f02 from 603gat >sa0
606 606gat and 2 2 >sa0 >sa1
24 360
607 606f01 from 606gat >sa0
608 606f02 from 606gat >sa0
609 609gat and 2 2 >sa0 >sa1
25 377
610 609f01 from 609gat >sa0
611 609f02 from 609gat >sa0
612 612gat and 2 2 >sa0 >sa1
26 394
613 612f01 from 612gat >sa0
614 612f02 from 612gat >sa0
615 615gat and 2 2 >sa0 >sa1
27 411
616 615f01 from 615gat >sa0
617 615f02 from 615gat >sa0
618 618gat and 2 2 >sa0 >sa1
28 428
619 618f01 from 618gat >sa0
620 618f02 from 618gat >sa0
621 621gat and 2 2 >sa0 >sa1
29 445
622 621f01 from 621gat >sa0
623 621f02 from 621gat >sa0
624 624gat and 2 2 >sa0 >sa1
30 462
625 624f01 from 624gat >sa0
626 624f02 from 624gat >sa0
627 627gat and 2 2 >sa0 >sa1
31 479
628 627f01 from 627gat >sa0
629 627f02 from 627gat >sa0
630 630gat and 2 2 >sa0 >sa1
32 496
631 630f01 from 630gat >sa0
632 630f02 from 630gat >sa0
633 633gat and 2 2 >sa0 >sa1
33 513
634 633f01 from 633gat >sa0
635 633f02 from 633gat >sa0
636 636gat and 2 2 >sa0 >sa1
34 530
637 636f01 from 636gat >sa0
638 636f02 from 636gat >sa0
639 639gat and 2 2 >sa0 >sa1
36 276
640 639f01 from 639gat
641 639f02 from 639gat >sa0
642 642gat and 2 2 >sa0 >sa1
37 293
643 642f01 from 642gat >sa0
644 642f02 from 642gat >sa0
645 645gat and 2 2 >sa0 >sa1
38 310
646 645f01 from 645gat >sa0
647 645f02 from 645gat >sa0
648 648gat and 2 2 >sa0 >sa1
39 327
649 648f01 from 648gat >sa0
650 648f02 from 648gat >sa0
651 651gat and 2 2 >sa0 >sa1
40 344
652 651f01 from 651gat >sa0
653 651f02 from 651gat >sa0
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41 361
655 654f01 from 654gat >sa0
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42 378
658 657f01 from 657gat >sa0
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43 395
661 660f01 from 660gat >sa0
662 660f02 from 660gat >sa0
663 663gat and 2 2 >sa0 >sa1
44 412
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665 663f02 from 663gat >sa0
666 666gat and 2 2 >sa0 >sa1
45 429
667 666f01 from 666gat >sa0
668 666f02 from 666gat >sa0
669 669gat and 2 2 >sa0 >sa1
46 446
670 669f01 from 669gat >sa0
671 669f02 from 669gat >sa0
672 672gat and 2 2 >sa0 >sa1
47 463
673 672f01 from 672gat >sa0
674 672f02 from 672gat >sa0
675 675gat and 2 2 >sa0 >sa1
48 480
676 675f01 from 675gat >sa0
677 675f02 from 675gat >sa0
678 678gat and 2 2 >sa0 >sa1
49 497
679 678f01 from 678gat >sa0
680 678f02 from 678gat >sa0
681 681gat and 2 2 >sa0 >sa1
50 514
682 681f01 from 681gat >sa0
683 681f02 from 681gat >sa0
684 684gat and 2 2 >sa0 >sa1
51 531
685 684f01 from 684gat >sa0
686 684f02 from 684gat >sa0
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53 277
688 687f01 from 687gat
689 687f02 from 687gat >sa0
690 690gat and 2 2 >sa0 >sa1
54 294
691 690f01 from 690gat >sa0
692 690f02 from 690gat >sa0
693 693gat and 2 2 >sa0 >sa1
55 311
694 693f01 from 693gat >sa0
695 693f02 from 693gat >sa0
696 696gat and 2 2 >sa0 >sa1
56 328
697 696f01 from 696gat >sa0
698 696f02 from 696gat >sa0
699 699gat and 2 2 >sa0 >sa1
57 345
700 699f01 from 699gat >sa0
701 699f02 from 699gat >sa0
702 702gat and 2 2 >sa0 >sa1
58 362
703 702f01 from 702gat >sa0
704 702f02 from 702gat >sa0
705 705gat and 2 2 >sa0 >sa1
59 379
706 705f01 from 705gat >sa0
707 705f02 from 705gat >sa0
708 708gat and 2 2 >sa0 >sa1
60 396
709 708f01 from 708gat >sa0
710 708f02 from 708gat >sa0
711 711gat and 2 2 >sa0 >sa1
61 413
712 711f01 from 711gat >sa0
713 711f02 from 711gat >sa0
714 714gat and 2 2 >sa0 >sa1
62 430
715 714f01 from 714gat >sa0
716 714f02 from 714gat >sa0
717 717gat and 2 2 >sa0 >sa1
63 447
718 717f01 from 717gat >sa0
719 717f02 from 717gat >sa0
720 720gat and 2 2 >sa0 >sa1
64 464
721 720f01 from 720gat >sa0
722 720f02 from 720gat >sa0
723 723gat and 2 2 >sa0 >sa1
65 481
724 723f01 from 723gat >sa0
725 723f02 from 723gat >sa0
726 726gat and 2 2 >sa0 >sa1
66 498
727 726f01 from 726gat >sa0
728 726f02 from 726gat >sa0
729 729gat and 2 2 >sa0 >sa1
67 515
730 729f01 from 729gat >sa0
731 729f02 from 729gat >sa0
732 732gat and 2 2 >sa0 >sa1
68 532
733 732f01 from 732gat >sa0
734 732f02 from 732gat >sa0
735 735gat and 2 2 >sa0 >sa1
70 278
736 735f01 from 735gat
737 735f02 from 735gat >sa0
738 738gat and 2 2 >sa0 >sa1
71 295
739 738f01 from 738gat >sa0
740 738f02 from 738gat >sa0
741 741gat and 2 2 >sa0 >sa1
72 312
742 741f01 from 741gat >sa0
743 741f02 from 741gat >sa0
744 744gat and 2 2 >sa0 >sa1
73 329
745 744f01 from 744gat >sa0
746 744f02 from 744gat >sa0
747 747gat and 2 2 >sa0 >sa1
74 346
748 747f01 from 747gat >sa0
749 747f02 from 747gat >sa0
750 750gat and 2 2 >sa0 >sa1
75 363
751 750f01 from 750gat >sa0
752 750f02 from 750gat >sa0
753 753gat and 2 2 >sa0 >sa1
76 380
754 753f01 from 753gat >sa0
755 753f02 from 753gat >sa0
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77 397
757 756f01 from 756gat >sa0
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78 414
760 759f01 from 759gat >sa0
761 759f02 from 759gat >sa0
762 762gat and 2 2 >sa0 >sa1
79 431
763 762f01 from 762gat >sa0
764 762f02 from 762gat >sa0
765 765gat and 2 2 >sa0 >sa1
80 448
766 765f01 from 765gat >sa0
767 765f02 from 765gat >sa0
768 768gat and 2 2 >sa0 >sa1
81 465
769 768f01 from 768gat >sa0
770 768f02 from 768gat >sa0
771 771gat and 2 2 >sa0 >sa1
82 482
772 771f01 from 771gat >sa0
773 771f02 from 771gat >sa0
774 774gat and 2 2 >sa0 >sa1
83 499
775 774f01 from 774gat >sa0
776 774f02 from 774gat >sa0
777 777gat and 2 2 >sa0 >sa1
84 516
778 777f01 from 777gat >sa0
779 777f02 from 777gat >sa0
780 780gat and 2 2 >sa0 >sa1
85 533
781 780f01 from 780gat >sa0
782 780f02 from 780gat >sa0
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87 279
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785 783f02 from 783gat >sa0
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88 296
787 786f01 from 786gat >sa0
788 786f02 from 786gat >sa0
789 789gat and 2 2 >sa0 >sa1
89 313
790 789f01 from 789gat >sa0
791 789f02 from 789gat >sa0
792 792gat and 2 2 >sa0 >sa1
90 330
793 792f01 from 792gat >sa0
794 792f02 from 792gat >sa0
795 795gat and 2 2 >sa0 >sa1
91 347
796 795f01 from 795gat >sa0
797 795f02 from 795gat >sa0
798 798gat and 2 2 >sa0 >sa1
92 364
799 798f01 from 798gat >sa0
800 798f02 from 798gat >sa0
801 801gat and 2 2 >sa0 >sa1
93 381
802 801f01 from 801gat >sa0
803 801f02 from 801gat >sa0
804 804gat and 2 2 >sa0 >sa1
94 398
805 804f01 from 804gat >sa0
806 804f02 from 804gat >sa0
807 807gat and 2 2 >sa0 >sa1
95 415
808 807f01 from 807gat >sa0
809 807f02 from 807gat >sa0
810 810gat and 2 2 >sa0 >sa1
96 432
811 810f01 from 810gat >sa0
812 810f02 from 810gat >sa0
813 813gat and 2 2 >sa0 >sa1
97 449
814 813f01 from 813gat >sa0
815 813f02 from 813gat >sa0
816 816gat and 2 2 >sa0 >sa1
98 466
817 816f01 from 816gat >sa0
818 816f02 from 816gat >sa0
819 819gat and 2 2 >sa0 >sa1
99 483
820 819f01 from 819gat >sa0
821 819f02 from 819gat >sa0
822 822gat and 2 2 >sa0 >sa1
100 500
823 822f01 from 822gat >sa0
824 822f02 from 822gat >sa0
825 825gat and 2 2 >sa0 >sa1
101 517
826 825f01 from 825gat >sa0
827 825f02 from 825gat >sa0
828 828gat and 2 2 >sa0 >sa1
102 534
829 828f01 from 828gat >sa0
830 828f02 from 828gat >sa0
831 831gat and 2 2 >sa0 >sa1
104 280
832 831f01 from 831gat
833 831f02 from 831gat >sa0
834 834gat and 2 2 >sa0 >sa1
105 297
835 834f01 from 834gat >sa0
836 834f02 from 834gat >sa0
837 837gat and 2 2 >sa0 >sa1
106 314
838 837f01 from 837gat >sa0
839 837f02 from 837gat >sa0
840 840gat and 2 2 >sa0 >sa1
107 331
841 840f01 from 840gat >sa0
842 840f02 from 840gat >sa0
843 843gat and 2 2 >sa0 >sa1
108 348
844 843f01 from 843gat >sa0
845 843f02 from 843gat >sa0
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109 365
847 846f01 from 846gat >sa0
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110 382
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851 849f02 from 849gat >sa0
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111 399
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112 416
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113 433
859 858f01 from 858gat >sa0
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114 450
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864 864gat and 2 2 >sa0 >sa1
115 467
865 864f01 from 864gat >sa0
866 864f02 from 864gat >sa0
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116 484
868 867f01 from 867gat >sa0
869 867f02 from 867gat >sa0
870 870gat and 2 2 >sa0 >sa1
117 501
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873 873gat and 2 2 >sa0 >sa1
118 518
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119 535
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121 281
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881 879f02 from 879gat >sa0
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122 298
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123 315
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124 332
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890 888f02 from 888gat >sa0
891 891gat and 2 2 >sa0 >sa1
125 349
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893 891f02 from 891gat >sa0
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126 366
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896 894f02 from 894gat >sa0
897 897gat and 2 2 >sa0 >sa1
127 383
898 897f01 from 897gat >sa0
899 897f02 from 897gat >sa0
900 900gat and 2 2 >sa0 >sa1
128 400
901 900f01 from 900gat >sa0
902 900f02 from 900gat >sa0
903 903gat and 2 2 >sa0 >sa1
129 417
904 903f01 from 903gat >sa0
905 903f02 from 903gat >sa0
906 906gat and 2 2 >sa0 >sa1
130 434
907 906f01 from 906gat >sa0
908 906f02 from 906gat >sa0
909 909gat and 2 2 >sa0 >sa1
131 451
910 909f01 from 909gat >sa0
911 909f02 from 909gat >sa0
912 912gat and 2 2 >sa0 >sa1
132 468
913 912f01 from 912gat >sa0
914 912f02 from 912gat >sa0
915 915gat and 2 2 >sa0 >sa1
133 485
916 915f01 from 915gat >sa0
917 915f02 from 915gat >sa0
918 918gat and 2 2 >sa0 >sa1
134 502
919 918f01 from 918gat >sa0
920 918f02 from 918gat >sa0
921 921gat and 2 2 >sa0 >sa1
135 519
922 921f01 from 921gat >sa0
923 921f02 from 921gat >sa0
924 924gat and 2 2 >sa0 >sa1
136 536
925 924f01 from 924gat >sa0
926 924f02 from 924gat >sa0
927 927gat and 2 2 >sa0 >sa1
138 282
928 927f01 from 927gat
929 927f02 from 927gat >sa0
930 930gat and 2 2 >sa0 >sa1
139 299
931 930f01 from 930gat >sa0
932 930f02 from 930gat >sa0
933 933gat and 2 2 >sa0 >sa1
140 316
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935 933f02 from 933gat >sa0
936 936gat and 2 2 >sa0 >sa1
141 333
937 936f01 from 936gat >sa0
938 936f02 from 936gat >sa0
939 939gat and 2 2 >sa0 >sa1
142 350
940 939f01 from 939gat >sa0
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143 367
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144 384
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145 401
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951 951gat and 2 2 >sa0 >sa1
146 418
952 951f01 from 951gat >sa0
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147 435
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148 452
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149 469
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150 486
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151 503
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152 520
970 969f01 from 969gat >sa0
971 969f02 from 969gat >sa0
972 972gat and 2 2 >sa0 >sa1
153 537
973 972f01 from 972gat >sa0
974 972f02 from 972gat >sa0
975 975gat and 2 2 >sa0 >sa1
155 283
976 975f01 from 975gat
977 975f02 from 975gat >sa0
978 978gat and 2 2 >sa0 >sa1
156 300
979 978f01 from 978gat >sa0
980 978f02 from 978gat >sa0
981 981gat and 2 2 >sa0 >sa1
157 317
982 981f01 from 981gat >sa0
983 981f02 from 981gat >sa0
984 984gat and 2 2 >sa0 >sa1
158 334
985 984f01 from 984gat >sa0
986 984f02 from 984gat >sa0
987 987gat and 2 2 >sa0 >sa1
159 351
988 987f01 from 987gat >sa0
989 987f02 from 987gat >sa0
990 990gat and 2 2 >sa0 >sa1
160 368
991 990f01 from 990gat >sa0
992 990f02 from 990gat >sa0
993 993gat and 2 2 >sa0 >sa1
161 385
994 993f01 from 993gat >sa0
995 993f02 from 993gat >sa0
996 996gat and 2 2 >sa0 >sa1
162 402
997 996f01 from 996gat >sa0
998 996f02 from 996gat >sa0
999 999gat and 2 2 >sa0 >sa1
163 419
1000 999f01 from 999gat >sa0
1001 999f02 from 999gat >sa0
1002 1002gat and 2 2 >sa0 >sa1
164 436
1003 1002f01 from 1002gat >sa0
1004 1002f02 from 1002gat >sa0
1005 1005gat and 2 2 >sa0 >sa1
165 453
1006 1005f01 from 1005gat >sa0
1007 1005f02 from 1005gat >sa0
1008 1008gat and 2 2 >sa0 >sa1
166 470
1009 1008f01 from 1008gat >sa0
1010 1008f02 from 1008gat >sa0
1011 1011gat and 2 2 >sa0 >sa1
167 487
1012 1011f01 from 1011gat >sa0
1013 1011f02 from 1011gat >sa0
1014 1014gat and 2 2 >sa0 >sa1
168 504
1015 1014f01 from 1014gat >sa0
1016 1014f02 from 1014gat >sa0
1017 1017gat and 2 2 >sa0 >sa1
169 521
1018 1017f01 from 1017gat >sa0
1019 1017f02 from 1017gat >sa0
1020 1020gat and 2 2 >sa0 >sa1
170 538
1021 1020f01 from 1020gat >sa0
1022 1020f02 from 1020gat >sa0
1023 1023gat and 2 2 >sa0 >sa1
172 284
1024 1023f01 from 1023gat
1025 1023f02 from 1023gat >sa0
1026 1026gat and 2 2 >sa0 >sa1
173 301
1027 1026f01 from 1026gat >sa0
1028 1026f02 from 1026gat >sa0
1029 1029gat and 2 2 >sa0 >sa1
174 318
1030 1029f01 from 1029gat >sa0
1031 1029f02 from 1029gat >sa0
1032 1032gat and 2 2 >sa0 >sa1
175 335
1033 1032f01 from 1032gat >sa0
1034 1032f02 from 1032gat >sa0
1035 1035gat and 2 2 >sa0 >sa1
176 352
1036 1035f01 from 1035gat >sa0
1037 1035f02 from 1035gat >sa0
1038 1038gat and 2 2 >sa0 >sa1
177 369
1039 1038f01 from 1038gat >sa0
1040 1038f02 from 1038gat >sa0
1041 1041gat and 2 2 >sa0 >sa1
178 386
1042 1041f01 from 1041gat >sa0
1043 1041f02 from 1041gat >sa0
1044 1044gat and 2 2 >sa0 >sa1
179 403
1045 1044f01 from 1044gat >sa0
1046 1044f02 from 1044gat >sa0
1047 1047gat and 2 2 >sa0 >sa1
180 420
1048 1047f01 from 1047gat >sa0
1049 1047f02 from 1047gat >sa0
1050 1050gat and 2 2 >sa0 >sa1
181 437
1051 1050f01 from 1050gat >sa0
1052 1050f02 from 1050gat >sa0
1053 1053gat and 2 2 >sa0 >sa1
182 454
1054 1053f01 from 1053gat >sa0
1055 1053f02 from 1053gat >sa0
1056 1056gat and 2 2 >sa0 >sa1
183 471
1057 1056f01 from 1056gat >sa0
1058 1056f02 from 1056gat >sa0
1059 1059gat and 2 2 >sa0 >sa1
184 488
1060 1059f01 from 1059gat >sa0
1061 1059f02 from 1059gat >sa0
1062 1062gat and 2 2 >sa0 >sa1
185 505
1063 1062f01 from 1062gat >sa0
1064 1062f02 from 1062gat >sa0
1065 1065gat and 2 2 >sa0 >sa1
186 522
1066 1065f01 from 1065gat >sa0
1067 1065f02 from 1065gat >sa0
1068 1068gat and 2 2 >sa0 >sa1
187 539
1069 1068f01 from 1068gat >sa0
1070 1068f02 from 1068gat >sa0
1071 1071gat and 2 2 >sa0 >sa1
189 285
1072 1071f01 from 1071gat
1073 1071f02 from 1071gat >sa0
1074 1074gat and 2 2 >sa0 >sa1
190 302
1075 1074f01 from 1074gat >sa0
1076 1074f02 from 1074gat >sa0
1077 1077gat and 2 2 >sa0 >sa1
191 319
1078 1077f01 from 1077gat >sa0
1079 1077f02 from 1077gat >sa0
1080 1080gat and 2 2 >sa0 >sa1
192 336
1081 1080f01 from 1080gat >sa0
1082 1080f02 from 1080gat >sa0
1083 1083gat and 2 2 >sa0 >sa1
193 353
1084 1083f01 from 1083gat >sa0
1085 1083f02 from 1083gat >sa0
1086 1086gat and 2 2 >sa0 >sa1
194 370
1087 1086f01 from 1086gat >sa0
1088 1086f02 from 1086gat >sa0
1089 1089gat and 2 2 >sa0 >sa1
195 387
1090 1089f01 from 1089gat >sa0
1091 1089f02 from 1089gat >sa0
1092 1092gat and 2 2 >sa0 >sa1
196 404
1093 1092f01 from 1092gat >sa0
1094 1092f02 from 1092gat >sa0
1095 1095gat and 2 2 >sa0 >sa1
197 421
1096 1095f01 from 1095gat >sa0
1097 1095f02 from 1095gat >sa0
1098 1098gat and 2 2 >sa0 >sa1
198 438
1099 1098f01 from 1098gat >sa0
1100 1098f02 from 1098gat >sa0
1101 1101gat and 2 2 >sa0 >sa1
199 455
1102 1101f01 from 1101gat >sa0
1103 1101f02 from 1101gat >sa0
1104 1104gat and 2 2 >sa0 >sa1
200 472
1105 1104f01 from 1104gat >sa0
1106 1104f02 from 1104gat >sa0
1107 1107gat and 2 2 >sa0 >sa1
201 489
1108 1107f01 from 1107gat >sa0
1109 1107f02 from 1107gat >sa0
1110 1110gat and 2 2 >sa0 >sa1
202 506
1111 1110f01 from 1110gat >sa0
1112 1110f02 from 1110gat >sa0
1113 1113gat and 2 2 >sa0 >sa1
203 523
1114 1113f01 from 1113gat >sa0
1115 1113f02 from 1113gat >sa0
1116 1116gat and 2 2 >sa0 >sa1
204 540
1117 1116f01 from 1116gat >sa0
1118 1116f02 from 1116gat >sa0
1119 1119gat and 2 2 >sa0 >sa1
206 286
1120 1119f01 from 1119gat
1121 1119f02 from 1119gat >sa0
1122 1122gat and 2 2 >sa0 >sa1
207 303
1123 1122f01 from 1122gat >sa0
1124 1122f02 from 1122gat >sa0
1125 1125gat and 2 2 >sa0 >sa1
208 320
1126 1125f01 from 1125gat >sa0
1127 1125f02 from 1125gat >sa0
1128 1128gat and 2 2 >sa0 >sa1
209 337
1129 1128f01 from 1128gat >sa0
1130 1128f02 from 1128gat >sa0
1131 1131gat and 2 2 >sa0 >sa1
210 354
1132 1131f01 from 1131gat >sa0
1133 1131f02 from 1131gat >sa0
1134 1134gat and 2 2 >sa0 >sa1
211 371
1135 1134f01 from 1134gat >sa0
1136 1134f02 from 1134gat >sa0
1137 1137gat and 2 2 >sa0 >sa1
212 388
1138 1137f01 from 1137gat >sa0
1139 1137f02 from 1137gat >sa0
1140 1140gat and 2 2 >sa0 >sa1
213 405
1141 1140f01 from 1140gat >sa0
1142 1140f02 from 1140gat >sa0
1143 1143gat and 2 2 >sa0 >sa1
214 422
1144 1143f01 from 1143gat >sa0
1145 1143f02 from 1143gat >sa0
1146 1146gat and 2 2 >sa0 >sa1
215 439
1147 1146f01 from 1146gat >sa0
1148 1146f02 from 1146gat >sa0
1149 1149gat and 2 2 >sa0 >sa1
216 456
1150 1149f01 from 1149gat >sa0
1151 1149f02 from 1149gat >sa0
1152 1152gat and 2 2 >sa0 >sa1
217 473
1153 1152f01 from 1152gat >sa0
1154 1152f02 from 1152gat >sa0
1155 1155gat and 2 2 >sa0 >sa1
218 490
1156 1155f01 from 1155gat >sa0
1157 1155f02 from 1155gat >sa0
1158 1158gat and 2 2 >sa0 >sa1
219 507
1159 1158f01 from 1158gat >sa0
1160 1158f02 from 1158gat >sa0
1161 1161gat and 2 2 >sa0 >sa1
220 524
1162 1161f01 from 1161gat >sa0
1163 1161f02 from 1161gat >sa0
1164 1164gat and 2 2 >sa0 >sa1
221 541
1165 1164f01 from 1164gat >sa0
1166 1164f02 from 1164gat >sa0
1167 1167gat and 2 2 >sa0 >sa1
223 287
1168 1167f01 from 1167gat
1169 1167f02 from 1167gat >sa0
1170 1170gat and 2 2 >sa0 >sa1
224 304
1171 1170f01 from 1170gat >sa0
1172 1170f02 from 1170gat >sa0
1173 1173gat and 2 2 >sa0 >sa1
225 321
1174 1173f01 from 1173gat >sa0
1175 1173f02 from 1173gat >sa0
1176 1176gat and 2 2 >sa0 >sa1
226 338
1177 1176f01 from 1176gat >sa0
1178 1176f02 from 1176gat >sa0
1179 1179gat and 2 2 >sa0 >sa1
227 355
1180 1179f01 from 1179gat >sa0
1181 1179f02 from 1179gat >sa0
1182 1182gat and 2 2 >sa0 >sa1
228 372
1183 1182f01 from 1182gat >sa0
1184 1182f02 from 1182gat >sa0
1185 1185gat and 2 2 >sa0 >sa1
229 389
1186 1185f01 from 1185gat >sa0
1187 1185f02 from 1185gat >sa0
1188 1188gat and 2 2 >sa0 >sa1
230 406
1189 1188f01 from 1188gat >sa0
1190 1188f02 from 1188gat >sa0
1191 1191gat and 2 2 >sa0 >sa1
231 423
1192 1191f01 from 1191gat >sa0
1193 1191f02 from 1191gat >sa0
1194 1194gat and 2 2 >sa0 >sa1
232 440
1195 1194f01 from 1194gat >sa0
1196 1194f02 from 1194gat >sa0
1197 1197gat and 2 2 >sa0 >sa1
233 457
1198 1197f01 from 1197gat >sa0
1199 1197f02 from 1197gat >sa0
1200 1200gat and 2 2 >sa0 >sa1
234 474
1201 1200f01 from 1200gat >sa0
1202 1200f02 from 1200gat >sa0
1203 1203gat and 2 2 >sa0 >sa1
235 491
1204 1203f01 from 1203gat >sa0
1205 1203f02 from 1203gat >sa0
1206 1206gat and 2 2 >sa0 >sa1
236 508
1207 1206f01 from 1206gat >sa0
1208 1206f02 from 1206gat >sa0
1209 1209gat and 2 2 >sa0 >sa1
237 525
1210 1209f01 from 1209gat >sa0
1211 1209f02 from 1209gat >sa0
1212 1212gat and 2 2 >sa0 >sa1
238 542
1213 1212f01 from 1212gat >sa0
1214 1212f02 from 1212gat >sa0
1215 1215gat and 2 2 >sa0 >sa1
240 288
1216 1215f01 from 1215gat
1217 1215f02 from 1215gat >sa0
1218 1218gat and 2 2 >sa0 >sa1
241 305
1219 1218f01 from 1218gat >sa0
1220 1218f02 from 1218gat >sa0
1221 1221gat and 2 2 >sa0 >sa1
242 322
1222 1221f01 from 1221gat >sa0
1223 1221f02 from 1221gat >sa0
1224 1224gat and 2 2 >sa0 >sa1
243 339
1225 1224f01 from 1224gat >sa0
1226 1224f02 from 1224gat >sa0
1227 1227gat and 2 2 >sa0 >sa1
244 356
1228 1227f01 from 1227gat >sa0
1229 1227f02 from 1227gat >sa0
1230 1230gat and 2 2 >sa0 >sa1
245 373
1231 1230f01 from 1230gat >sa0
1232 1230f02 from 1230gat >sa0
1233 1233gat and 2 2 >sa0 >sa1
246 390
1234 1233f01 from 1233gat >sa0
1235 1233f02 from 1233gat >sa0
1236 1236gat and 2 2 >sa0 >sa1
247 407
1237 1236f01 from 1236gat >sa0
1238 1236f02 from 1236gat >sa0
1239 1239gat and 2 2 >sa0 >sa1
248 424
1240 1239f01 from 1239gat >sa0
1241 1239f02 from 1239gat >sa0
1242 1242gat and 2 2 >sa0 >sa1
249 441
1243 1242f01 from 1242gat >sa0
1244 1242f02 from 1242gat >sa0
1245 1245gat and 2 2 >sa0 >sa1
250 458
1246 1245f01 from 1245gat >sa0
1247 1245f02 from 1245gat >sa0
1248 1248gat and 2 2 >sa0 >sa1
251 475
1249 1248f01 from 1248gat >sa0
1250 1248f02 from 1248gat >sa0
1251 1251gat and 2 2 >sa0 >sa1
252 492
1252 1251f01 from 1251gat >sa0
1253 1251f02 from 1251gat >sa0
1254 1254gat and 2 2 >sa0 >sa1
253 509
1255 1254f01 from 1254gat >sa0
1256 1254f02 from 1254gat >sa0
1257 1257gat and 2 2 >sa0 >sa1
254 526
1258 1257f01 from 1257gat >sa0
1259 1257f02 from 1257gat >sa0
1260 1260gat and 2 2 >sa0 >sa1
255 543
1261 1260f01 from 1260gat >sa0
1262 1260f02 from 1260gat >sa0
1263 1263gat and 2 2 >sa0 >sa1
257 289
1264 1263f01 from 1263gat
1265 1263f02 from 1263gat >sa0
1266 1266gat and 2 2 >sa0 >sa1
258 306
1267 1266f01 from 1266gat >sa0
1268 1266f02 from 1266gat >sa0
1269 1269gat and 2 2 >sa0 >sa1
259 323
1270 1269f01 from 1269gat >sa0
1271 1269f02 from 1269gat >sa0
1272 1272gat and 2 2 >sa0 >sa1
260 340
1273 1272f01 from 1272gat >sa0
1274 1272f02 from 1272gat >sa0
1275 1275gat and 2 2 >sa0 >sa1
261 357
1276 1275f01 from 1275gat >sa0
1277 1275f02 from 1275gat >sa0
1278 1278gat and 2 2 >sa0 >sa1
262 374
1279 1278f01 from 1278gat >sa0
1280 1278f02 from 1278gat >sa0
1281 1281gat and 2 2 >sa0 >sa1
263 391
1282 1281f01 from 1281gat >sa0
1283 1281f02 from 1281gat >sa0
1284 1284gat and 2 2 >sa0 >sa1
264 408
1285 1284f01 from 1284gat >sa0
1286 1284f02 from 1284gat >sa0
1287 1287gat and 2 2 >sa0 >sa1
265 425
1288 1287f01 from 1287gat >sa0
1289 1287f02 from 1287gat >sa0
1290 1290gat and 2 2 >sa0 >sa1
266 442
1291 1290f01 from 1290gat >sa0
1292 1290f02 from 1290gat >sa0
1293 1293gat and 2 2 >sa0 >sa1
267 459
1294 1293f01 from 1293gat >sa0
1295 1293f02 from 1293gat >sa0
1296 1296gat and 2 2 >sa0 >sa1
268 476
1297 1296f01 from 1296gat >sa0
1298 1296f02 from 1296gat >sa0
1299 1299gat and 2 2 >sa0 >sa1
269 493
1300 1299f01 from 1299gat >sa0
1301 1299f02 from 1299gat >sa0
1302 1302gat and 2 2 >sa0 >sa1
270 510
1303 1302f01 from 1302gat >sa0
1304 1302f02 from 1302gat >sa0
1305 1305gat and 2 2 >sa0 >sa1
271 527
1306 1305f01 from 1305gat >sa0
1307 1305f02 from 1305gat >sa0
1308 1308gat and 2 2 >sa0 >sa1
272 544
1309 1308f01 from 1308gat >sa0
1310 1308f02 from 1308gat >sa0
1311 1311gat not 3 1 >sa0 >sa1
592
1312 1311f01 from 1311gat >sa0
1313 1311f02 from 1311gat >sa0
1314 1311f03 from 1311gat
1315 1315gat not 3 1 >sa0 >sa1
640
1316 1315f01 from 1315gat >sa0
1317 1315f02 from 1315gat >sa0
1318 1315f03 from 1315gat
1319 1319gat not 3 1 >sa0 >sa1
688
1320 1319f01 from 1319gat >sa0
1321 1319f02 from 1319gat >sa0
1322 1319f03 from 1319gat
1323 1323gat not 3 1 >sa0 >sa1
736
1324 1323f01 from 1323gat >sa0
1325 1323f02 from 1323gat >sa0
1326 1323f03 from 1323gat
1327 1327gat not 3 1 >sa0 >sa1
784
1328 1327f01 from 1327gat >sa0
1329 1327f02 from 1327gat >sa0
1330 1327f03 from 1327gat
1331 1331gat not 3 1 >sa0 >sa1
832
1332 1331f01 from 1331gat >sa0
1333 1331f02 from 1331gat >sa0
1334 1331f03 from 1331gat
1335 1335gat not 3 1 >sa0 >sa1
880
1336 1335f01 from 1335gat >sa0
1337 1335f02 from 1335gat >sa0
1338 1335f03 from 1335gat
1339 1339gat not 3 1 >sa0 >sa1
928
1340 1339f01 from 1339gat >sa0
1341 1339f02 from 1339gat >sa0
1342 1339f03 from 1339gat
1343 1343gat not 3 1 >sa0 >sa1
976
1344 1343f01 from 1343gat >sa0
1345 1343f02 from 1343gat >sa0
1346 1343f03 from 1343gat
1347 1347gat not 3 1 >sa0 >sa1
1024
1348 1347f01 from 1347gat >sa0
1349 1347f02 from 1347gat >sa0
1350 1347f03 from 1347gat
1351 1351gat not 3 1 >sa0 >sa1
1072
1352 1351f01 from 1351gat >sa0
1353 1351f02 from 1351gat >sa0
1354 1351f03 from 1351gat
1355 1355gat not 3 1 >sa0 >sa1
1120
1356 1355f01 from 1355gat >sa0
1357 1355f02 from 1355gat >sa0
1358 1355f03 from 1355gat
1359 1359gat not 3 1 >sa0 >sa1
1168
1360 1359f01 from 1359gat >sa0
1361 1359f02 from 1359gat >sa0
1362 1359f03 from 1359gat
1363 1363gat not 3 1 >sa0 >sa1
1216
1364 1363f01 from 1363gat >sa0
1365 1363f02 from 1363gat >sa0
1366 1363f03 from 1363gat
1367 1367gat not 3 1 >sa0 >sa1
1264
1368 1367f01 from 1367gat >sa0
1369 1367f02 from 1367gat >sa0
1370 1367f03 from 1367gat
1371 1371gat nor 1 2 >sa0
593 1313
1372 1372gat not 1 1 >sa0
1314
1373 1373gat nor 1 2 >sa0
641 1317
1374 1374gat not 1 1 >sa0
1318
1375 1375gat nor 1 2 >sa0
689 1321
1376 1376gat not 1 1 >sa0
1322
1377 1377gat nor 1 2 >sa0
737 1325
1378 1378gat not 1 1 >sa0
1326
1379 1379gat nor 1 2 >sa0
785 1329
1380 1380gat not 1 1 >sa0
1330
1381 1381gat nor 1 2 >sa0
833 1333
1382 1382gat not 1 1 >sa0
1334
1383 1383gat nor 1 2 >sa0
881 1337
1384 1384gat not 1 1 >sa0
1338
1385 1385gat nor 1 2 >sa0
929 1341
1386 1386gat not 1 1 >sa0
1342
1387 1387gat nor 1 2 >sa0
977 1345
1388 1388gat not 1 1 >sa0
1346
1389 1389gat nor 1 2 >sa0
1025 1349
1390 1390gat not 1 1 >sa0
1350
1391 1391gat nor 1 2 >sa0
1073 1353
1392 1392gat not 1 1 >sa0
1354
1393 1393gat nor 1 2 >sa0
1121 1357
1394 1394gat not 1 1 >sa0
1358
1395 1395gat nor 1 2 >sa0
1169 1361
1396 1396gat not 1 1 >sa0
1362
1397 1397gat nor 1 2 >sa0
1217 1365
1398 1398gat not 1 1 >sa0
1366
1399 1399gat nor 1 2 >sa0
1265 1369
1400 1400gat not 1 1 >sa0
1370
1401 1401gat nor 2 2 >sa0 >sa1
1371 1372
1402 1401f01 from 1401gat >sa0
1403 1401f02 from 1401gat >sa0
1404 1404gat nor 2 2 >sa0 >sa1
1373 1374
1405 1404f01 from 1404gat >sa0
1406 1404f02 from 1404gat >sa0
1407 1407gat nor 2 2 >sa0 >sa1
1375 1376
1408 1407f01 from 1407gat >sa0
1409 1407f02 from 1407gat >sa0
1410 1410gat nor 2 2 >sa0 >sa1
1377 1378
1411 1410f01 from 1410gat >sa0
1412 1410f02 from 1410gat >sa0
1413 1413gat nor 2 2 >sa0 >sa1
1379 1380
1414 1413f01 from 1413gat >sa0
1415 1413f02 from 1413gat >sa0
1416 1416gat nor 2 2 >sa0 >sa1
1381 1382
1417 1416f01 from 1416gat >sa0
1418 1416f02 from 1416gat >sa0
1419 1419gat nor 2 2 >sa0 >sa1
1383 1384
1420 1419f01 from 1419gat >sa0
1421 1419f02 from 1419gat >sa0
1422 1422gat nor 2 2 >sa0 >sa1
1385 1386
1423 1422f01 from 1422gat >sa0
1424 1422f02 from 1422gat >sa0
1425 1425gat nor 2 2 >sa0 >sa1
1387 1388
1426 1425f01 from 1425gat >sa0
1427 1425f02 from 1425gat >sa0
1428 1428gat nor 2 2 >sa0 >sa1
1389 1390
1429 1428f01 from 1428gat >sa0
1430 1428f02 from 1428gat >sa0
1431 1431gat nor 2 2 >sa0 >sa1
1391 1392
1432 1431f01 from 1431gat >sa0
1433 1431f02 from 1431gat >sa0
1434 1434gat nor 2 2 >sa0 >sa1
1393 1394
1435 1434f01 from 1434gat >sa0
1436 1434f02 from 1434gat >sa0
1437 1437gat nor 2 2 >sa0 >sa1
1395 1396
1438 1437f01 from 1437gat >sa0
1439 1437f02 from 1437gat >sa0
1440 1440gat nor 2 2 >sa0 >sa1
1397 1398
1441 1440f01 from 1440gat >sa0
1442 1440f02 from 1440gat >sa0
1443 1443gat nor 2 2 >sa0 >sa1
1399 1400
1444 1443f01 from 1443gat >sa0
1445 1443f02 from 1443gat >sa0
1446 1446gat nor 3 2 >sa0 >sa1
1403 548
1447 1446f01 from 1446gat >sa0
1448 1446f02 from 1446gat >sa0
1449 1446f03 from 1446gat >sa0
1450 1450gat nor 3 2 >sa0 >sa1
1406 596
1451 1450f01 from 1450gat >sa0
1452 1450f02 from 1450gat >sa0
1453 1450f03 from 1450gat >sa0
1454 1454gat nor 3 2 >sa0 >sa1
1409 644
1455 1454f01 from 1454gat >sa0
1456 1454f02 from 1454gat >sa0
1457 1454f03 from 1454gat >sa0
1458 1458gat nor 3 2 >sa0 >sa1
1412 692
1459 1458f01 from 1458gat >sa0
1460 1458f02 from 1458gat >sa0
1461 1458f03 from 1458gat >sa0
1462 1462gat nor 3 2 >sa0 >sa1
1415 740
1463 1462f01 from 1462gat >sa0
1464 1462f02 from 1462gat >sa0
1465 1462f03 from 1462gat >sa0
1466 1466gat nor 3 2 >sa0 >sa1
1418 788
1467 1466f01 from 1466gat >sa0
1468 1466f02 from 1466gat >sa0
1469 1466f03 from 1466gat >sa0
1470 1470gat nor 3 2 >sa0 >sa1
1421 836
1471 1470f01 from 1470gat >sa0
1472 1470f02 from 1470gat >sa0
1473 1470f03 from 1470gat >sa0
1474 1474gat nor 3 2 >sa0 >sa1
1424 884
1475 1474f01 from 1474gat >sa0
1476 1474f02 from 1474gat >sa0
1477 1474f03 from 1474gat >sa0
1478 1478gat nor 3 2 >sa0 >sa1
1427 932
1479 1478f01 from 1478gat >sa0
1480 1478f02 from 1478gat >sa0
1481 1478f03 from 1478gat >sa0
1482 1482gat nor 3 2 >sa0 >sa1
1430 980
1483 1482f01 from 1482gat >sa0
1484 1482f02 from 1482gat >sa0
1485 1482f03 from 1482gat >sa0
1486 1486gat nor 3 2 >sa0 >sa1
1433 1028
1487 1486f01 from 1486gat >sa0
1488 1486f02 from 1486gat >sa0
1489 1486f03 from 1486gat >sa0
1490 1490gat nor 3 2 >sa0 >sa1
1436 1076
1491 1490f01 from 1490gat >sa0
1492 1490f02 from 1490gat >sa0
1493 1490f03 from 1490gat >sa0
1494 1494gat nor 3 2 >sa0 >sa1
1439 1124
1495 1494f01 from 1494gat >sa0
1496 1494f02 from 1494gat >sa0
1497 1494f03 from 1494gat >sa0
1498 1498gat nor 3 2 >sa0 >sa1
1442 1172
1499 1498f01 from 1498gat >sa0
1500 1498f02 from 1498gat >sa0
1501 1498f03 from 1498gat >sa0
1502 1502gat nor 3 2 >sa0 >sa1
1445 1220
1503 1502f01 from 1502gat >sa0
1504 1502f02 from 1502gat >sa0
1505 1502f03 from 1502gat >sa0
1506 1506gat nor 1 2 >sa0
1402 1447
1507 1507gat nor 1 2 >sa0
1448 547
1508 1508gat nor 2 2 >sa0 >sa1
1312 1449
1509 1508f01 from 1508gat >sa0
1510 1508f02 from 1508gat >sa0
1511 1511gat nor 1 2 >sa0
1405 1451
1512 1512gat nor 1 2 >sa0
1452 595
1513 1513gat nor 2 2 >sa0 >sa1
1316 1453
1514 1513f01 from 1513gat >sa0
1515 1513f02 from 1513gat >sa0
1516 1516gat nor 1 2 >sa0
1408 1455
1517 1517gat nor 1 2 >sa0
1456 643
1518 1518gat nor 2 2 >sa0 >sa1
1320 1457
1519 1518f01 from 1518gat >sa0
1520 1518f02 from 1518gat >sa0
1521 1521gat nor 1 2 >sa0
1411 1459
1522 1522gat nor 1 2 >sa0
1460 691
1523 1523gat nor 2 2 >sa0 >sa1
1324 1461
1524 1523f01 from 1523gat >sa0
1525 1523f02 from 1523gat >sa0
1526 1526gat nor 1 2 >sa0
1414 1463
1527 1527gat nor 1 2 >sa0
1464 739
1528 1528gat nor 2 2 >sa0 >sa1
1328 1465
1529 1528f01 from 1528gat >sa0
1530 1528f02 from 1528gat >sa0
1531 1531gat nor 1 2 >sa0
1417 1467
1532 1532gat nor 1 2 >sa0
1468 787
1533 1533gat nor 2 2 >sa0 >sa1
1332 1469
1534 1533f01 from 1533gat >sa0
1535 1533f02 from 1533gat >sa0
1536 1536gat nor 1 2 >sa0
1420 1471
1537 1537gat nor 1 2 >sa0
1472 835
1538 1538gat nor 2 2 >sa0 >sa1
1336 1473
1539 1538f01 from 1538gat >sa0
1540 1538f02 from 1538gat >sa0
1541 1541gat nor 1 2 >sa0
1423 1475
1542 1542gat nor 1 2 >sa0
1476 883
1543 1543gat nor 2 2 >sa0 >sa1
1340 1477
1544 1543f01 from 1543gat >sa0
1545 1543f02 from 1543gat >sa0
1546 1546gat nor 1 2 >sa0
1426 1479
1547 1547gat nor 1 2 >sa0
1480 931
1548 1548gat nor 2 2 >sa0 >sa1
1344 1481
1549 1548f01 from 1548gat >sa0
1550 1548f02 from 1548gat >sa0
1551 1551gat nor 1 2 >sa0
1429 1483
1552 1552gat nor 1 2 >sa0
1484 979
1553 1553gat nor 2 2 >sa0 >sa1
1348 1485
1554 1553f01 from 1553gat >sa0
1555 1553f02 from 1553gat >sa0
1556 1556gat nor 1 2 >sa0
1432 1487
1557 1557gat nor 1 2 >sa0
1488 1027
1558 1558gat nor 2 2 >sa0 >sa1
1352 1489
1559 1558f01 from 1558gat >sa0
1560 1558f02 from 1558gat >sa0
1561 1561gat nor 1 2 >sa0
1435 1491
1562 1562gat nor 1 2 >sa0
1492 1075
1563 1563gat nor 2 2 >sa0 >sa1
1356 1493
1564 1563f01 from 1563gat >sa0
1565 1563f02 from 1563gat >sa0
1566 1566gat nor 1 2 >sa0
1438 1495
1567 1567gat nor 1 2 >sa0
1496 1123
1568 1568gat nor 2 2 >sa0 >sa1
1360 1497
1569 1568f01 from 1568gat >sa0
1570 1568f02 from 1568gat >sa0
1571 1571gat nor 1 2 >sa0
1441 1499
1572 1572gat nor 1 2 >sa0
1500 1171
1573 1573gat nor 2 2 >sa0 >sa1
1364 1501
1574 1573f01 from 1573gat >sa0
1575 1573f02 from 1573gat >sa0
1576 1576gat nor 1 2 >sa0
1444 1503
1577 1577gat nor 1 2 >sa0
1504 1219
1578 1578gat nor 2 2 >sa0 >sa1
1368 1505
1579 1578f01 from 1578gat >sa0
1580 1578f02 from 1578gat >sa0
1581 1581gat nor 0 2 >sa0 >sa1
1506 1507
1582 1582gat nor 2 2 >sa0 >sa1
1511 1512
1583 1582f01 from 1582gat >sa0
1584 1582f02 from 1582gat >sa0
1585 1585gat nor 2 2 >sa0 >sa1
1516 1517
1586 1585f01 from 1585gat >sa0
1587 1585f02 from 1585gat >sa0
1588 1588gat nor 2 2 >sa0 >sa1
1521 1522
1589 1588f01 from 1588gat >sa0
1590 1588f02 from 1588gat >sa0
1591 1591gat nor 2 2 >sa0 >sa1
1526 1527
1592 1591f01 from 1591gat >sa0
1593 1591f02 from 1591gat >sa0
1594 1594gat nor 2 2 >sa0 >sa1
1531 1532
1595 1594f01 from 1594gat >sa0
1596 1594f02 from 1594gat >sa0
1597 1597gat nor 2 2 >sa0 >sa1
1536 1537
1598 1597f01 from 1597gat >sa0
1599 1597f02 from 1597gat >sa0
1600 1600gat nor 2 2 >sa0 >sa1
1541 1542
1601 1600f01 from 1600gat >sa0
1602 1600f02 from 1600gat >sa0
1603 1603gat nor 2 2 >sa0 >sa1
1546 1547
1604 1603f01 from 1603gat >sa0
1605 1603f02 from 1603gat >sa0
1606 1606gat nor 2 2 >sa0 >sa1
1551 1552
1607 1606f01 from 1606gat >sa0
1608 1606f02 from 1606gat >sa0
1609 1609gat nor 2 2 >sa0 >sa1
1556 1557
1610 1609f01 from 1609gat >sa0
1611 1609f02 from 1609gat >sa0
1612 1612gat nor 2 2 >sa0 >sa1
1561 1562
1613 1612f01 from 1612gat >sa0
1614 1612f02 from 1612gat >sa0
1615 1615gat nor 2 2 >sa0 >sa1
1566 1567
1616 1615f01 from 1615gat >sa0
1617 1615f02 from 1615gat >sa0
1618 1618gat nor 2 2 >sa0 >sa1
1571 1572
1619 1618f01 from 1618gat >sa0
1620 1618f02 from 1618gat >sa0
1621 1621gat nor 2 2 >sa0 >sa1
1576 1577
1622 1621f01 from 1621gat >sa0
1623 1621f02 from 1621gat >sa0
1624 1624gat nor 3 2 >sa0 >sa1
1267 1579
1625 1624f01 from 1624gat >sa0
1626 1624f02 from 1624gat >sa0
1627 1624f03 from 1624gat >sa0
1628 1628gat nor 3 2 >sa0 >sa1
1583 1509
1629 1628f01 from 1628gat >sa0
1630 1628f02 from 1628gat >sa0
1631 1628f03 from 1628gat >sa0
1632 1632gat nor 3 2 >sa0 >sa1
1586 1514
1633 1632f01 from 1632gat >sa0
1634 1632f02 from 1632gat >sa0
1635 1632f03 from 1632gat >sa0
1636 1636gat nor 3 2 >sa0 >sa1
1589 1519
1637 1636f01 from 1636gat >sa0
1638 1636f02 from 1636gat >sa0
1639 1636f03 from 1636gat >sa0
1640 1640gat nor 3 2 >sa0 >sa1
1592 1524
1641 1640f01 from 1640gat >sa0
1642 1640f02 from 1640gat >sa0
1643 1640f03 from 1640gat >sa0
1644 1644gat nor 3 2 >sa0 >sa1
1595 1529
1645 1644f01 from 1644gat >sa0
1646 1644f02 from 1644gat >sa0
1647 1644f03 from 1644gat >sa0
1648 1648gat nor 3 2 >sa0 >sa1
1598 1534
1649 1648f01 from 1648gat >sa0
1650 1648f02 from 1648gat >sa0
1651 1648f03 from 1648gat >sa0
1652 1652gat nor 3 2 >sa0 >sa1
1601 1539
1653 1652f01 from 1652gat >sa0
1654 1652f02 from 1652gat >sa0
1655 1652f03 from 1652gat >sa0
1656 1656gat nor 3 2 >sa0 >sa1
1604 1544
1657 1656f01 from 1656gat >sa0
1658 1656f02 from 1656gat >sa0
1659 1656f03 from 1656gat >sa0
1660 1660gat nor 3 2 >sa0 >sa1
1607 1549
1661 1660f01 from 1660gat >sa0
1662 1660f02 from 1660gat >sa0
1663 1660f03 from 1660gat >sa0
1664 1664gat nor 3 2 >sa0 >sa1
1610 1554
1665 1664f01 from 1664gat >sa0
1666 1664f02 from 1664gat >sa0
1667 1664f03 from 1664gat >sa0
1668 1668gat nor 3 2 >sa0 >sa1
1613 1559
1669 1668f01 from 1668gat >sa0
1670 1668f02 from 1668gat >sa0
1671 1668f03 from 1668gat >sa0
1672 1672gat nor 3 2 >sa0 >sa1
1616 1564
1673 1672f01 from 1672gat >sa0
1674 1672f02 from 1672gat >sa0
1675 1672f03 from 1672gat >sa0
1676 1676gat nor 3 2 >sa0 >sa1
1619 1569
1677 1676f01 from 1676gat >sa0
1678 1676f02 from 1676gat >sa0
1679 1676f03 from 1676gat >sa0
1680 1680gat nor 3 2 >sa0 >sa1
1622 1574
1681 1680f01 from 1680gat >sa0
1682 1680f02 from 1680gat >sa0
1683 1680f03 from 1680gat >sa0
1684 1684gat nor 1 2 >sa0
1268 1626
1685 1685gat nor 1 2 >sa0
1627 1580
1686 1686gat nor 1 2 >sa0
1584 1630
1687 1687gat nor 1 2 >sa0
1631 1510
1688 1688gat nor 1 2 >sa0
1587 1634
1689 1689gat nor 1 2 >sa0
1635 1515
1690 1690gat nor 1 2 >sa0
1590 1638
1691 1691gat nor 1 2 >sa0
1639 1520
1692 1692gat nor 1 2 >sa0
1593 1642
1693 1693gat nor 1 2 >sa0
1643 1525
1694 1694gat nor 1 2 >sa0
1596 1646
1695 1695gat nor 1 2 >sa0
1647 1530
1696 1696gat nor 1 2 >sa0
1599 1650
1697 1697gat nor 1 2 >sa0
1651 1535
1698 1698gat nor 1 2 >sa0
1602 1654
1699 1699gat nor 1 2 >sa0
1655 1540
1700 1700gat nor 1 2 >sa0
1605 1658
1701 1701gat nor 1 2 >sa0
1659 1545
1702 1702gat nor 1 2 >sa0
1608 1662
1703 1703gat nor 1 2 >sa0
1663 1550
1704 1704gat nor 1 2 >sa0
1611 1666
1705 1705gat nor 1 2 >sa0
1667 1555
1706 1706gat nor 1 2 >sa0
1614 1670
1707 1707gat nor 1 2 >sa0
1671 1560
1708 1708gat nor 1 2 >sa0
1617 1674
1709 1709gat nor 1 2 >sa0
1675 1565
1710 1710gat nor 1 2 >sa0
1620 1678
1711 1711gat nor 1 2 >sa0
1679 1570
1712 1712gat nor 1 2 >sa0
1623 1682
1713 1713gat nor 1 2 >sa0
1683 1575
1714 1714gat nor 2 2 >sa0 >sa1
1684 1685
1715 1714f01 from 1714gat >sa0
1716 1714f02 from 1714gat >sa0
1717 1717gat nor 2 2 >sa0 >sa1
1686 1687
1718 1717f01 from 1717gat >sa0
1719 1717f02 from 1717gat >sa0
1720 1720gat nor 2 2 >sa0 >sa1
1688 1689
1721 1720f01 from 1720gat >sa0
1722 1720f02 from 1720gat >sa0
1723 1723gat nor 2 2 >sa0 >sa1
1690 1691
1724 1723f01 from 1723gat >sa0
1725 1723f02 from 1723gat >sa0
1726 1726gat nor 2 2 >sa0 >sa1
1692 1693
1727 1726f01 from 1726gat >sa0
1728 1726f02 from 1726gat >sa0
1729 1729gat nor 2 2 >sa0 >sa1
1694 1695
1730 1729f01 from 1729gat >sa0
1731 1729f02 from 1729gat >sa0
1732 1732gat nor 2 2 >sa0 >sa1
1696 1697
1733 1732f01 from 1732gat >sa0
1734 1732f02 from 1732gat >sa0
1735 1735gat nor 2 2 >sa0 >sa1
1698 1699
1736 1735f01 from 1735gat >sa0
1737 1735f02 from 1735gat >sa0
1738 1738gat nor 2 2 >sa0 >sa1
1700 1701
1739 1738f01 from 1738gat >sa0
1740 1738f02 from 1738gat >sa0
1741 1741gat nor 2 2 >sa0 >sa1
1702 1703
1742 1741f01 from 1741gat >sa0
1743 1741f02 from 1741gat >sa0
1744 1744gat nor 2 2 >sa0 >sa1
1704 1705
1745 1744f01 from 1744gat >sa0
1746 1744f02 from 1744gat >sa0
1747 1747gat nor 2 2 >sa0 >sa1
1706 1707
1748 1747f01 from 1747gat >sa0
1749 1747f02 from 1747gat >sa0
1750 1750gat nor 2 2 >sa0 >sa1
1708 1709
1751 1750f01 from 1750gat >sa0
1752 1750f02 from 1750gat >sa0
1753 1753gat nor 2 2 >sa0 >sa1
1710 1711
1754 1753f01 from 1753gat >sa0
1755 1753f02 from 1753gat >sa0
1756 1756gat nor 2 2 >sa0 >sa1
1712 1713
1757 1756f01 from 1756gat >sa0
1758 1756f02 from 1756gat >sa0
1759 1759gat nor 3 2 >sa0 >sa1
1716 1223
1760 1759f01 from 1759gat >sa0
1761 1759f02 from 1759gat >sa0
1762 1759f03 from 1759gat >sa0
1763 1763gat nor 3 2 >sa0 >sa1
1719 551
1764 1763f01 from 1763gat >sa0
1765 1763f02 from 1763gat >sa0
1766 1763f03 from 1763gat >sa0
1767 1767gat nor 3 2 >sa0 >sa1
1722 599
1768 1767f01 from 1767gat >sa0
1769 1767f02 from 1767gat >sa0
1770 1767f03 from 1767gat >sa0
1771 1771gat nor 3 2 >sa0 >sa1
1725 647
1772 1771f01 from 1771gat >sa0
1773 1771f02 from 1771gat >sa0
1774 1771f03 from 1771gat >sa0
1775 1775gat nor 3 2 >sa0 >sa1
1728 695
1776 1775f01 from 1775gat >sa0
1777 1775f02 from 1775gat >sa0
1778 1775f03 from 1775gat >sa0
1779 1779gat nor 3 2 >sa0 >sa1
1731 743
1780 1779f01 from 1779gat >sa0
1781 1779f02 from 1779gat >sa0
1782 1779f03 from 1779gat >sa0
1783 1783gat nor 3 2 >sa0 >sa1
1734 791
1784 1783f01 from 1783gat >sa0
1785 1783f02 from 1783gat >sa0
1786 1783f03 from 1783gat >sa0
1787 1787gat nor 3 2 >sa0 >sa1
1737 839
1788 1787f01 from 1787gat >sa0
1789 1787f02 from 1787gat >sa0
1790 1787f03 from 1787gat >sa0
1791 1791gat nor 3 2 >sa0 >sa1
1740 887
1792 1791f01 from 1791gat >sa0
1793 1791f02 from 1791gat >sa0
1794 1791f03 from 1791gat >sa0
1795 1795gat nor 3 2 >sa0 >sa1
1743 935
1796 1795f01 from 1795gat >sa0
1797 1795f02 from 1795gat >sa0
1798 1795f03 from 1795gat >sa0
1799 1799gat nor 3 2 >sa0 >sa1
1746 983
1800 1799f01 from 1799gat >sa0
1801 1799f02 from 1799gat >sa0
1802 1799f03 from 1799gat >sa0
1803 1803gat nor 3 2 >sa0 >sa1
1749 1031
1804 1803f01 from 1803gat >sa0
1805 1803f02 from 1803gat >sa0
1806 1803f03 from 1803gat >sa0
1807 1807gat nor 3 2 >sa0 >sa1
1752 1079
1808 1807f01 from 1807gat >sa0
1809 1807f02 from 1807gat >sa0
1810 1807f03 from 1807gat >sa0
1811 1811gat nor 3 2 >sa0 >sa1
1755 1127
1812 1811f01 from 1811gat >sa0
1813 1811f02 from 1811gat >sa0
1814 1811f03 from 1811gat >sa0
1815 1815gat nor 3 2 >sa0 >sa1
1758 1175
1816 1815f01 from 1815gat >sa0
1817 1815f02 from 1815gat >sa0
1818 1815f03 from 1815gat >sa0
1819 1819gat nor 1 2 >sa0
1715 1760
1820 1820gat nor 1 2 >sa0
1761 1222
1821 1821gat nor 2 2 >sa0 >sa1
1625 1762
1822 1821f01 from 1821gat >sa0
1823 1821f02 from 1821gat >sa0
1824 1824gat nor 1 2 >sa0
1718 1764
1825 1825gat nor 1 2 >sa0
1765 550
1826 1826gat nor 2 2 >sa0 >sa1
1629 1766
1827 1826f01 from 1826gat >sa0
1828 1826f02 from 1826gat >sa0
1829 1829gat nor 1 2 >sa0
1721 1768
1830 1830gat nor 1 2 >sa0
1769 598
1831 1831gat nor 2 2 >sa0 >sa1
1633 1770
1832 1831f01 from 1831gat >sa0
1833 1831f02 from 1831gat >sa0
1834 1834gat nor 1 2 >sa0
1724 1772
1835 1835gat nor 1 2 >sa0
1773 646
1836 1836gat nor 2 2 >sa0 >sa1
1637 1774
1837 1836f01 from 1836gat >sa0
1838 1836f02 from 1836gat >sa0
1839 1839gat nor 1 2 >sa0
1727 1776
1840 1840gat nor 1 2 >sa0
1777 694
1841 1841gat nor 2 2 >sa0 >sa1
1641 1778
1842 1841f01 from 1841gat >sa0
1843 1841f02 from 1841gat >sa0
1844 1844gat nor 1 2 >sa0
1730 1780
1845 1845gat nor 1 2 >sa0
1781 742
1846 1846gat nor 2 2 >sa0 >sa1
1645 1782
1847 1846f01 from 1846gat >sa0
1848 1846f02 from 1846gat >sa0
1849 1849gat nor 1 2 >sa0
1733 1784
1850 1850gat nor 1 2 >sa0
1785 790
1851 1851gat nor 2 2 >sa0 >sa1
1649 1786
1852 1851f01 from 1851gat >sa0
1853 1851f02 from 1851gat >sa0
1854 1854gat nor 1 2 >sa0
1736 1788
1855 1855gat nor 1 2 >sa0
1789 838
1856 1856gat nor 2 2 >sa0 >sa1
1653 1790
1857 1856f01 from 1856gat >sa0
1858 1856f02 from 1856gat >sa0
1859 1859gat nor 1 2 >sa0
1739 1792
1860 1860gat nor 1 2 >sa0
1793 886
1861 1861gat nor 2 2 >sa0 >sa1
1657 1794
1862 1861f01 from 1861gat >sa0
1863 1861f02 from 1861gat >sa0
1864 1864gat nor 1 2 >sa0
1742 1796
1865 1865gat nor 1 2 >sa0
1797 934
1866 1866gat nor 2 2 >sa0 >sa1
1661 1798
1867 1866f01 from 1866gat >sa0
1868 1866f02 from 1866gat >sa0
1869 1869gat nor 1 2 >sa0
1745 1800
1870 1870gat nor 1 2 >sa0
1801 982
1871 1871gat nor 2 2 >sa0 >sa1
1665 1802
1872 1871f01 from 1871gat >sa0
1873 1871f02 from 1871gat >sa0
1874 1874gat nor 1 2 >sa0
1748 1804
1875 1875gat nor 1 2 >sa0
1805 1030
1876 1876gat nor 2 2 >sa0 >sa1
1669 1806
1877 1876f01 from 1876gat >sa0
1878 1876f02 from 1876gat >sa0
1879 1879gat nor 1 2 >sa0
1751 1808
1880 1880gat nor 1 2 >sa0
1809 1078
1881 1881gat nor 2 2 >sa0 >sa1
1673 1810
1882 1881f01 from 1881gat >sa0
1883 1881f02 from 1881gat >sa0
1884 1884gat nor 1 2 >sa0
1754 1812
1885 1885gat nor 1 2 >sa0
1813 1126
1886 1886gat nor 2 2 >sa0 >sa1
1677 1814
1887 1886f01 from 1886gat >sa0
1888 1886f02 from 1886gat >sa0
1889 1889gat nor 1 2 >sa0
1757 1816
1890 1890gat nor 1 2 >sa0
1817 1174
1891 1891gat nor 2 2 >sa0 >sa1
1681 1818
1892 1891f01 from 1891gat >sa0
1893 1891f02 from 1891gat >sa0
1894 1894gat nor 2 2 >sa0 >sa1
1819 1820
1895 1894f01 from 1894gat >sa0
1896 1894f02 from 1894gat >sa0
1897 1897gat nor 3 2 >sa0 >sa1
1270 1822
1898 1897f01 from 1897gat >sa0
1899 1897f02 from 1897gat >sa0
1900 1897f03 from 1897gat >sa0
1901 1901gat nor 0 2 >sa0 >sa1
1824 1825
1902 1902gat nor 2 2 >sa0 >sa1
1829 1830
1903 1902f01 from 1902gat >sa0
1904 1902f02 from 1902gat >sa0
1905 1905gat nor 2 2 >sa0 >sa1
1834 1835
1906 1905f01 from 1905gat >sa0
1907 1905f02 from 1905gat >sa0
1908 1908gat nor 2 2 >sa0 >sa1
1839 1840
1909 1908f01 from 1908gat >sa0
1910 1908f02 from 1908gat >sa0
1911 1911gat nor 2 2 >sa0 >sa1
1844 1845
1912 1911f01 from 1911gat >sa0
1913 1911f02 from 1911gat >sa0
1914 1914gat nor 2 2 >sa0 >sa1
1849 1850
1915 1914f01 from 1914gat >sa0
1916 1914f02 from 1914gat >sa0
1917 1917gat nor 2 2 >sa0 >sa1
1854 1855
1918 1917f01 from 1917gat >sa0
1919 1917f02 from 1917gat >sa0
1920 1920gat nor 2 2 >sa0 >sa1
1859 1860
1921 1920f01 from 1920gat >sa0
1922 1920f02 from 1920gat >sa0
1923 1923gat nor 2 2 >sa0 >sa1
1864 1865
1924 1923f01 from 1923gat >sa0
1925 1923f02 from 1923gat >sa0
1926 1926gat nor 2 2 >sa0 >sa1
1869 1870
1927 1926f01 from 1926gat >sa0
1928 1926f02 from 1926gat >sa0
1929 1929gat nor 2 2 >sa0 >sa1
1874 1875
1930 1929f01 from 1929gat >sa0
1931 1929f02 from 1929gat >sa0
1932 1932gat nor 2 2 >sa0 >sa1
1879 1880
1933 1932f01 from 1932gat >sa0
1934 1932f02 from 1932gat >sa0
1935 1935gat nor 2 2 >sa0 >sa1
1884 1885
1936 1935f01 from 1935gat >sa0
1937 1935f02 from 1935gat >sa0
1938 1938gat nor 2 2 >sa0 >sa1
1889 1890
1939 1938f01 from 1938gat >sa0
1940 1938f02 from 1938gat >sa0
1941 1941gat nor 3 2 >sa0 >sa1
1895 1892
1942 1941f01 from 1941gat >sa0
1943 1941f02 from 1941gat >sa0
1944 1941f03 from 1941gat >sa0
1945 1945gat nor 1 2 >sa0
1271 1899
1946 1946gat nor 1 2 >sa0
1900 1823
1947 1947gat nor 3 2 >sa0 >sa1
1903 1827
1948 1947f01 from 1947gat >sa0
1949 1947f02 from 1947gat >sa0
1950 1947f03 from 1947gat >sa0
1951 1951gat nor 3 2 >sa0 >sa1
1906 1832
1952 1951f01 from 1951gat >sa0
1953 1951f02 from 1951gat >sa0
1954 1951f03 from 1951gat >sa0
1955 1955gat nor 3 2 >sa0 >sa1
1909 1837
1956 1955f01 from 1955gat >sa0
1957 1955f02 from 1955gat >sa0
1958 1955f03 from 1955gat >sa0
1959 1959gat nor 3 2 >sa0 >sa1
1912 1842
1960 1959f01 from 1959gat >sa0
1961 1959f02 from 1959gat >sa0
1962 1959f03 from 1959gat >sa0
1963 1963gat nor 3 2 >sa0 >sa1
1915 1847
1964 1963f01 from 1963gat >sa0
1965 1963f02 from 1963gat >sa0
1966 1963f03 from 1963gat >sa0
1967 1967gat nor 3 2 >sa0 >sa1
1918 1852
1968 1967f01 from 1967gat >sa0
1969 1967f02 from 1967gat >sa0
1970 1967f03 from 1967gat >sa0
1971 1971gat nor 3 2 >sa0 >sa1
1921 1857
1972 1971f01 from 1971gat >sa0
1973 1971f02 from 1971gat >sa0
1974 1971f03 from 1971gat >sa0
1975 1975gat nor 3 2 >sa0 >sa1
1924 1862
1976 1975f01 from 1975gat >sa0
1977 1975f02 from 1975gat >sa0
1978 1975f03 from 1975gat >sa0
1979 1979gat nor 3 2 >sa0 >sa1
1927 1867
1980 1979f01 from 1979gat >sa0
1981 1979f02 from 1979gat >sa0
1982 1979f03 from 1979gat >sa0
1983 1983gat nor 3 2 >sa0 >sa1
1930 1872
1984 1983f01 from 1983gat >sa0
1985 1983f02 from 1983gat >sa0
1986 1983f03 from 1983gat >sa0
1987 1987gat nor 3 2 >sa0 >sa1
1933 1877
1988 1987f01 from 1987gat >sa0
1989 1987f02 from 1987gat >sa0
1990 1987f03 from 1987gat >sa0
1991 1991gat nor 3 2 >sa0 >sa1
1936 1882
1992 1991f01 from 1991gat >sa0
1993 1991f02 from 1991gat >sa0
1994 1991f03 from 1991gat >sa0
1995 1995gat nor 3 2 >sa0 >sa1
1939 1887
1996 1995f01 from 1995gat >sa0
1997 1995f02 from 1995gat >sa0
1998 1995f03 from 1995gat >sa0
1999 1999gat nor 1 2 >sa0
1896 1943
2000 2000gat nor 1 2 >sa0
1944 1893
2001 2001gat nor 2 2 >sa0 >sa1
1945 1946
2002 2001f01 from 2001gat >sa0
2003 2001f02 from 2001gat >sa0
2004 2004gat nor 1 2 >sa0
1904 1949
2005 2005gat nor 1 2 >sa0
1950 1828
2006 2006gat nor 1 2 >sa0
1907 1953
2007 2007gat nor 1 2 >sa0
1954 1833
2008 2008gat nor 1 2 >sa0
1910 1957
2009 2009gat nor 1 2 >sa0
1958 1838
2010 2010gat nor 1 2 >sa0
1913 1961
2011 2011gat nor 1 2 >sa0
1962 1843
2012 2012gat nor 1 2 >sa0
1916 1965
2013 2013gat nor 1 2 >sa0
1966 1848
2014 2014gat nor 1 2 >sa0
1919 1969
2015 2015gat nor 1 2 >sa0
1970 1853
2016 2016gat nor 1 2 >sa0
1922 1973
2017 2017gat nor 1 2 >sa0
1974 1858
2018 2018gat nor 1 2 >sa0
1925 1977
2019 2019gat nor 1 2 >sa0
1978 1863
2020 2020gat nor 1 2 >sa0
1928 1981
2021 2021gat nor 1 2 >sa0
1982 1868
2022 2022gat nor 1 2 >sa0
1931 1985
2023 2023gat nor 1 2 >sa0
1986 1873
2024 2024gat nor 1 2 >sa0
1934 1989
2025 2025gat nor 1 2 >sa0
1990 1878
2026 2026gat nor 1 2 >sa0
1937 1993
2027 2027gat nor 1 2 >sa0
1994 1883
2028 2028gat nor 1 2 >sa0
1940 1997
2029 2029gat nor 1 2 >sa0
1998 1888
2030 2030gat nor 2 2 >sa0 >sa1
1999 2000
2031 2030f01 from 2030gat >sa0
2032 2030f02 from 2030gat >sa0
2033 2033gat nor 3 2 >sa0 >sa1
2003 1226
2034 2033f01 from 2033gat >sa0
2035 2033f02 from 2033gat >sa0
2036 2033f03 from 2033gat >sa0
2037 2037gat nor 2 2 >sa0 >sa1
2004 2005
2038 2037f01 from 2037gat >sa0
2039 2037f02 from 2037gat >sa0
2040 2040gat nor 2 2 >sa0 >sa1
2006 2007
2041 2040f01 from 2040gat >sa0
2042 2040f02 from 2040gat >sa0
2043 2043gat nor 2 2 >sa0 >sa1
2008 2009
2044 2043f01 from 2043gat >sa0
2045 2043f02 from 2043gat >sa0
2046 2046gat nor 2 2 >sa0 >sa1
2010 2011
2047 2046f01 from 2046gat >sa0
2048 2046f02 from 2046gat >sa0
2049 2049gat nor 2 2 >sa0 >sa1
2012 2013
2050 2049f01 from 2049gat >sa0
2051 2049f02 from 2049gat >sa0
2052 2052gat nor 2 2 >sa0 >sa1
2014 2015
2053 2052f01 from 2052gat >sa0
2054 2052f02 from 2052gat >sa0
2055 2055gat nor 2 2 >sa0 >sa1
2016 2017
2056 2055f01 from 2055gat >sa0
2057 2055f02 from 2055gat >sa0
2058 2058gat nor 2 2 >sa0 >sa1
2018 2019
2059 2058f01 from 2058gat >sa0
2060 2058f02 from 2058gat >sa0
2061 2061gat nor 2 2 >sa0 >sa1
2020 2021
2062 2061f01 from 2061gat >sa0
2063 2061f02 from 2061gat >sa0
2064 2064gat nor 2 2 >sa0 >sa1
2022 2023
2065 2064f01 from 2064gat >sa0
2066 2064f02 from 2064gat >sa0
2067 2067gat nor 2 2 >sa0 >sa1
2024 2025
2068 2067f01 from 2067gat >sa0
2069 2067f02 from 2067gat >sa0
2070 2070gat nor 2 2 >sa0 >sa1
2026 2027
2071 2070f01 from 2070gat >sa0
2072 2070f02 from 2070gat >sa0
2073 2073gat nor 2 2 >sa0 >sa1
2028 2029
2074 2073f01 from 2073gat >sa0
2075 2073f02 from 2073gat >sa0
2076 2076gat nor 3 2 >sa0 >sa1
2032 1178
2077 2076f01 from 2076gat >sa0
2078 2076f02 from 2076gat >sa0
2079 2076f03 from 2076gat >sa0
2080 2080gat nor 1 2 >sa0
2002 2034
2081 2081gat nor 1 2 >sa0
2035 1225
2082 2082gat nor 2 2 >sa0 >sa1
1898 2036
2083 2082f01 from 2082gat >sa0
2084 2082f02 from 2082gat >sa0
2085 2085gat nor 3 2 >sa0 >sa1
2039 554
2086 2085f01 from 2085gat >sa0
2087 2085f02 from 2085gat >sa0
2088 2085f03 from 2085gat >sa0
2089 2089gat nor 3 2 >sa0 >sa1
2042 602
2090 2089f01 from 2089gat >sa0
2091 2089f02 from 2089gat >sa0
2092 2089f03 from 2089gat >sa0
2093 2093gat nor 3 2 >sa0 >sa1
2045 650
2094 2093f01 from 2093gat >sa0
2095 2093f02 from 2093gat >sa0
2096 2093f03 from 2093gat >sa0
2097 2097gat nor 3 2 >sa0 >sa1
2048 698
2098 2097f01 from 2097gat >sa0
2099 2097f02 from 2097gat >sa0
2100 2097f03 from 2097gat >sa0
2101 2101gat nor 3 2 >sa0 >sa1
2051 746
2102 2101f01 from 2101gat >sa0
2103 2101f02 from 2101gat >sa0
2104 2101f03 from 2101gat >sa0
2105 2105gat nor 3 2 >sa0 >sa1
2054 794
2106 2105f01 from 2105gat >sa0
2107 2105f02 from 2105gat >sa0
2108 2105f03 from 2105gat >sa0
2109 2109gat nor 3 2 >sa0 >sa1
2057 842
2110 2109f01 from 2109gat >sa0
2111 2109f02 from 2109gat >sa0
2112 2109f03 from 2109gat >sa0
2113 2113gat nor 3 2 >sa0 >sa1
2060 890
2114 2113f01 from 2113gat >sa0
2115 2113f02 from 2113gat >sa0
2116 2113f03 from 2113gat >sa0
2117 2117gat nor 3 2 >sa0 >sa1
2063 938
2118 2117f01 from 2117gat >sa0
2119 2117f02 from 2117gat >sa0
2120 2117f03 from 2117gat >sa0
2121 2121gat nor 3 2 >sa0 >sa1
2066 986
2122 2121f01 from 2121gat >sa0
2123 2121f02 from 2121gat >sa0
2124 2121f03 from 2121gat >sa0
2125 2125gat nor 3 2 >sa0 >sa1
2069 1034
2126 2125f01 from 2125gat >sa0
2127 2125f02 from 2125gat >sa0
2128 2125f03 from 2125gat >sa0
2129 2129gat nor 3 2 >sa0 >sa1
2072 1082
2130 2129f01 from 2129gat >sa0
2131 2129f02 from 2129gat >sa0
2132 2129f03 from 2129gat >sa0
2133 2133gat nor 3 2 >sa0 >sa1
2075 1130
2134 2133f01 from 2133gat >sa0
2135 2133f02 from 2133gat >sa0
2136 2133f03 from 2133gat >sa0
2137 2137gat nor 1 2 >sa0
2031 2077
2138 2138gat nor 1 2 >sa0
2078 1177
2139 2139gat nor 2 2 >sa0 >sa1
1942 2079
2140 2139f01 from 2139gat >sa0
2141 2139f02 from 2139gat >sa0
2142 2142gat nor 2 2 >sa0 >sa1
2080 2081
2143 2142f01 from 2142gat >sa0
2144 2142f02 from 2142gat >sa0
2145 2145gat nor 3 2 >sa0 >sa1
1273 2083
2146 2145f01 from 2145gat >sa0
2147 2145f02 from 2145gat >sa0
2148 2145f03 from 2145gat >sa0
2149 2149gat nor 1 2 >sa0
2038 2086
2150 2150gat nor 1 2 >sa0
2087 553
2151 2151gat nor 2 2 >sa0 >sa1
1948 2088
2152 2151f01 from 2151gat >sa0
2153 2151f02 from 2151gat >sa0
2154 2154gat nor 1 2 >sa0
2041 2090
2155 2155gat nor 1 2 >sa0
2091 601
2156 2156gat nor 2 2 >sa0 >sa1
1952 2092
2157 2156f01 from 2156gat >sa0
2158 2156f02 from 2156gat >sa0
2159 2159gat nor 1 2 >sa0
2044 2094
2160 2160gat nor 1 2 >sa0
2095 649
2161 2161gat nor 2 2 >sa0 >sa1
1956 2096
2162 2161f01 from 2161gat >sa0
2163 2161f02 from 2161gat >sa0
2164 2164gat nor 1 2 >sa0
2047 2098
2165 2165gat nor 1 2 >sa0
2099 697
2166 2166gat nor 2 2 >sa0 >sa1
1960 2100
2167 2166f01 from 2166gat >sa0
2168 2166f02 from 2166gat >sa0
2169 2169gat nor 1 2 >sa0
2050 2102
2170 2170gat nor 1 2 >sa0
2103 745
2171 2171gat nor 2 2 >sa0 >sa1
1964 2104
2172 2171f01 from 2171gat >sa0
2173 2171f02 from 2171gat >sa0
2174 2174gat nor 1 2 >sa0
2053 2106
2175 2175gat nor 1 2 >sa0
2107 793
2176 2176gat nor 2 2 >sa0 >sa1
1968 2108
2177 2176f01 from 2176gat >sa0
2178 2176f02 from 2176gat >sa0
2179 2179gat nor 1 2 >sa0
2056 2110
2180 2180gat nor 1 2 >sa0
2111 841
2181 2181gat nor 2 2 >sa0 >sa1
1972 2112
2182 2181f01 from 2181gat >sa0
2183 2181f02 from 2181gat >sa0
2184 2184gat nor 1 2 >sa0
2059 2114
2185 2185gat nor 1 2 >sa0
2115 889
2186 2186gat nor 2 2 >sa0 >sa1
1976 2116
2187 2186f01 from 2186gat >sa0
2188 2186f02 from 2186gat >sa0
2189 2189gat nor 1 2 >sa0
2062 2118
2190 2190gat nor 1 2 >sa0
2119 937
2191 2191gat nor 2 2 >sa0 >sa1
1980 2120
2192 2191f01 from 2191gat >sa0
2193 2191f02 from 2191gat >sa0
2194 2194gat nor 1 2 >sa0
2065 2122
2195 2195gat nor 1 2 >sa0
2123 985
2196 2196gat nor 2 2 >sa0 >sa1
1984 2124
2197 2196f01 from 2196gat >sa0
2198 2196f02 from 2196gat >sa0
2199 2199gat nor 1 2 >sa0
2068 2126
2200 2200gat nor 1 2 >sa0
2127 1033
2201 2201gat nor 2 2 >sa0 >sa1
1988 2128
2202 2201f01 from 2201gat >sa0
2203 2201f02 from 2201gat >sa0
2204 2204gat nor 1 2 >sa0
2071 2130
2205 2205gat nor 1 2 >sa0
2131 1081
2206 2206gat nor 2 2 >sa0 >sa1
1992 2132
2207 2206f01 from 2206gat >sa0
2208 2206f02 from 2206gat >sa0
2209 2209gat nor 1 2 >sa0
2074 2134
2210 2210gat nor 1 2 >sa0
2135 1129
2211 2211gat nor 2 2 >sa0 >sa1
1996 2136
2212 2211f01 from 2211gat >sa0
2213 2211f02 from 2211gat >sa0
2214 2214gat nor 2 2 >sa0 >sa1
2137 2138
2215 2214f01 from 2214gat >sa0
2216 2214f02 from 2214gat >sa0
2217 2217gat nor 3 2 >sa0 >sa1
2143 2140
2218 2217f01 from 2217gat >sa0
2219 2217f02 from 2217gat >sa0
2220 2217f03 from 2217gat >sa0
2221 2221gat nor 1 2 >sa0
1274 2147
2222 2222gat nor 1 2 >sa0
2148 2084
2223 2223gat nor 0 2 >sa0 >sa1
2149 2150
2224 2224gat nor 2 2 >sa0 >sa1
2154 2155
2225 2224f01 from 2224gat >sa0
2226 2224f02 from 2224gat >sa0
2227 2227gat nor 2 2 >sa0 >sa1
2159 2160
2228 2227f01 from 2227gat >sa0
2229 2227f02 from 2227gat >sa0
2230 2230gat nor 2 2 >sa0 >sa1
2164 2165
2231 2230f01 from 2230gat >sa0
2232 2230f02 from 2230gat >sa0
2233 2233gat nor 2 2 >sa0 >sa1
2169 2170
2234 2233f01 from 2233gat >sa0
2235 2233f02 from 2233gat >sa0
2236 2236gat nor 2 2 >sa0 >sa1
2174 2175
2237 2236f01 from 2236gat >sa0
2238 2236f02 from 2236gat >sa0
2239 2239gat nor 2 2 >sa0 >sa1
2179 2180
2240 2239f01 from 2239gat >sa0
2241 2239f02 from 2239gat >sa0
2242 2242gat nor 2 2 >sa0 >sa1
2184 2185
2243 2242f01 from 2242gat >sa0
2244 2242f02 from 2242gat >sa0
2245 2245gat nor 2 2 >sa0 >sa1
2189 2190
2246 2245f01 from 2245gat >sa0
2247 2245f02 from 2245gat >sa0
2248 2248gat nor 2 2 >sa0 >sa1
2194 2195
2249 2248f01 from 2248gat >sa0
2250 2248f02 from 2248gat >sa0
2251 2251gat nor 2 2 >sa0 >sa1
2199 2200
2252 2251f01 from 2251gat >sa0
2253 2251f02 from 2251gat >sa0
2254 2254gat nor 2 2 >sa0 >sa1
2204 2205
2255 2254f01 from 2254gat >sa0
2256 2254f02 from 2254gat >sa0
2257 2257gat nor 2 2 >sa0 >sa1
2209 2210
2258 2257f01 from 2257gat >sa0
2259 2257f02 from 2257gat >sa0
2260 2260gat nor 3 2 >sa0 >sa1
2215 2212
2261 2260f01 from 2260gat >sa0
2262 2260f02 from 2260gat >sa0
2263 2260f03 from 2260gat >sa0
2264 2264gat nor 1 2 >sa0
2144 2219
2265 2265gat nor 1 2 >sa0
2220 2141
2266 2266gat nor 2 2 >sa0 >sa1
2221 2222
2267 2266f01 from 2266gat >sa0
2268 2266f02 from 2266gat >sa0
2269 2269gat nor 3 2 >sa0 >sa1
2225 2152
2270 2269f01 from 2269gat >sa0
2271 2269f02 from 2269gat >sa0
2272 2269f03 from 2269gat >sa0
2273 2273gat nor 3 2 >sa0 >sa1
2228 2157
2274 2273f01 from 2273gat >sa0
2275 2273f02 from 2273gat >sa0
2276 2273f03 from 2273gat >sa0
2277 2277gat nor 3 2 >sa0 >sa1
2231 2162
2278 2277f01 from 2277gat >sa0
2279 2277f02 from 2277gat >sa0
2280 2277f03 from 2277gat >sa0
2281 2281gat nor 3 2 >sa0 >sa1
2234 2167
2282 2281f01 from 2281gat >sa0
2283 2281f02 from 2281gat >sa0
2284 2281f03 from 2281gat >sa0
2285 2285gat nor 3 2 >sa0 >sa1
2237 2172
2286 2285f01 from 2285gat >sa0
2287 2285f02 from 2285gat >sa0
2288 2285f03 from 2285gat >sa0
2289 2289gat nor 3 2 >sa0 >sa1
2240 2177
2290 2289f01 from 2289gat >sa0
2291 2289f02 from 2289gat >sa0
2292 2289f03 from 2289gat >sa0
2293 2293gat nor 3 2 >sa0 >sa1
2243 2182
2294 2293f01 from 2293gat >sa0
2295 2293f02 from 2293gat >sa0
2296 2293f03 from 2293gat >sa0
2297 2297gat nor 3 2 >sa0 >sa1
2246 2187
2298 2297f01 from 2297gat >sa0
2299 2297f02 from 2297gat >sa0
2300 2297f03 from 2297gat >sa0
2301 2301gat nor 3 2 >sa0 >sa1
2249 2192
2302 2301f01 from 2301gat >sa0
2303 2301f02 from 2301gat >sa0
2304 2301f03 from 2301gat >sa0
2305 2305gat nor 3 2 >sa0 >sa1
2252 2197
2306 2305f01 from 2305gat >sa0
2307 2305f02 from 2305gat >sa0
2308 2305f03 from 2305gat >sa0
2309 2309gat nor 3 2 >sa0 >sa1
2255 2202
2310 2309f01 from 2309gat >sa0
2311 2309f02 from 2309gat >sa0
2312 2309f03 from 2309gat >sa0
2313 2313gat nor 3 2 >sa0 >sa1
2258 2207
2314 2313f01 from 2313gat >sa0
2315 2313f02 from 2313gat >sa0
2316 2313f03 from 2313gat >sa0
2317 2317gat nor 1 2 >sa0
2216 2262
2318 2318gat nor 1 2 >sa0
2263 2213
2319 2319gat nor 2 2 >sa0 >sa1
2264 2265
2320 2319f01 from 2319gat >sa0
2321 2319f02 from 2319gat >sa0
2322 2322gat nor 3 2 >sa0 >sa1
2268 1229
2323 2322f01 from 2322gat >sa0
2324 2322f02 from 2322gat >sa0
2325 2322f03 from 2322gat >sa0
2326 2326gat nor 1 2 >sa0
2226 2271
2327 2327gat nor 1 2 >sa0
2272 2153
2328 2328gat nor 1 2 >sa0
2229 2275
2329 2329gat nor 1 2 >sa0
2276 2158
2330 2330gat nor 1 2 >sa0
2232 2279
2331 2331gat nor 1 2 >sa0
2280 2163
2332 2332gat nor 1 2 >sa0
2235 2283
2333 2333gat nor 1 2 >sa0
2284 2168
2334 2334gat nor 1 2 >sa0
2238 2287
2335 2335gat nor 1 2 >sa0
2288 2173
2336 2336gat nor 1 2 >sa0
2241 2291
2337 2337gat nor 1 2 >sa0
2292 2178
2338 2338gat nor 1 2 >sa0
2244 2295
2339 2339gat nor 1 2 >sa0
2296 2183
2340 2340gat nor 1 2 >sa0
2247 2299
2341 2341gat nor 1 2 >sa0
2300 2188
2342 2342gat nor 1 2 >sa0
2250 2303
2343 2343gat nor 1 2 >sa0
2304 2193
2344 2344gat nor 1 2 >sa0
2253 2307
2345 2345gat nor 1 2 >sa0
2308 2198
2346 2346gat nor 1 2 >sa0
2256 2311
2347 2347gat nor 1 2 >sa0
2312 2203
2348 2348gat nor 1 2 >sa0
2259 2315
2349 2349gat nor 1 2 >sa0
2316 2208
2350 2350gat nor 2 2 >sa0 >sa1
2317 2318
2351 2350f01 from 2350gat >sa0
2352 2350f02 from 2350gat >sa0
2353 2353gat nor 3 2 >sa0 >sa1
2321 1181
2354 2353f01 from 2353gat >sa0
2355 2353f02 from 2353gat >sa0
2356 2353f03 from 2353gat >sa0
2357 2357gat nor 1 2 >sa0
2267 2323
2358 2358gat nor 1 2 >sa0
2324 1228
2359 2359gat nor 2 2 >sa0 >sa1
2146 2325
2360 2359f01 from 2359gat >sa0
2361 2359f02 from 2359gat >sa0
2362 2362gat nor 2 2 >sa0 >sa1
2326 2327
2363 2362f01 from 2362gat >sa0
2364 2362f02 from 2362gat >sa0
2365 2365gat nor 2 2 >sa0 >sa1
2328 2329
2366 2365f01 from 2365gat >sa0
2367 2365f02 from 2365gat >sa0
2368 2368gat nor 2 2 >sa0 >sa1
2330 2331
2369 2368f01 from 2368gat >sa0
2370 2368f02 from 2368gat >sa0
2371 2371gat nor 2 2 >sa0 >sa1
2332 2333
2372 2371f01 from 2371gat >sa0
2373 2371f02 from 2371gat >sa0
2374 2374gat nor 2 2 >sa0 >sa1
2334 2335
2375 2374f01 from 2374gat >sa0
2376 2374f02 from 2374gat >sa0
2377 2377gat nor 2 2 >sa0 >sa1
2336 2337
2378 2377f01 from 2377gat >sa0
2379 2377f02 from 2377gat >sa0
2380 2380gat nor 2 2 >sa0 >sa1
2338 2339
2381 2380f01 from 2380gat >sa0
2382 2380f02 from 2380gat >sa0
2383 2383gat nor 2 2 >sa0 >sa1
2340 2341
2384 2383f01 from 2383gat >sa0
2385 2383f02 from 2383gat >sa0
2386 2386gat nor 2 2 >sa0 >sa1
2342 2343
2387 2386f01 from 2386gat >sa0
2388 2386f02 from 2386gat >sa0
2389 2389gat nor 2 2 >sa0 >sa1
2344 2345
2390 2389f01 from 2389gat >sa0
2391 2389f02 from 2389gat >sa0
2392 2392gat nor 2 2 >sa0 >sa1
2346 2347
2393 2392f01 from 2392gat >sa0
2394 2392f02 from 2392gat >sa0
2395 2395gat nor 2 2 >sa0 >sa1
2348 2349
2396 2395f01 from 2395gat >sa0
2397 2395f02 from 2395gat >sa0
2398 2398gat nor 3 2 >sa0 >sa1
2352 1133
2399 2398f01 from 2398gat >sa0
2400 2398f02 from 2398gat >sa0
2401 2398f03 from 2398gat >sa0
2402 2402gat nor 1 2 >sa0
2320 2354
2403 2403gat nor 1 2 >sa0
2355 1180
2404 2404gat nor 2 2 >sa0 >sa1
2218 2356
2405 2404f01 from 2404gat >sa0
2406 2404f02 from 2404gat >sa0
2407 2407gat nor 2 2 >sa0 >sa1
2357 2358
2408 2407f01 from 2407gat >sa0
2409 2407f02 from 2407gat >sa0
2410 2410gat nor 3 2 >sa0 >sa1
1276 2360
2411 2410f01 from 2410gat >sa0
2412 2410f02 from 2410gat >sa0
2413 2410f03 from 2410gat >sa0
2414 2414gat nor 3 2 >sa0 >sa1
2364 557
2415 2414f01 from 2414gat >sa0
2416 2414f02 from 2414gat >sa0
2417 2414f03 from 2414gat >sa0
2418 2418gat nor 3 2 >sa0 >sa1
2367 605
2419 2418f01 from 2418gat >sa0
2420 2418f02 from 2418gat >sa0
2421 2418f03 from 2418gat >sa0
2422 2422gat nor 3 2 >sa0 >sa1
2370 653
2423 2422f01 from 2422gat >sa0
2424 2422f02 from 2422gat >sa0
2425 2422f03 from 2422gat >sa0
2426 2426gat nor 3 2 >sa0 >sa1
2373 701
2427 2426f01 from 2426gat >sa0
2428 2426f02 from 2426gat >sa0
2429 2426f03 from 2426gat >sa0
2430 2430gat nor 3 2 >sa0 >sa1
2376 749
2431 2430f01 from 2430gat >sa0
2432 2430f02 from 2430gat >sa0
2433 2430f03 from 2430gat >sa0
2434 2434gat nor 3 2 >sa0 >sa1
2379 797
2435 2434f01 from 2434gat >sa0
2436 2434f02 from 2434gat >sa0
2437 2434f03 from 2434gat >sa0
2438 2438gat nor 3 2 >sa0 >sa1
2382 845
2439 2438f01 from 2438gat >sa0
2440 2438f02 from 2438gat >sa0
2441 2438f03 from 2438gat >sa0
2442 2442gat nor 3 2 >sa0 >sa1
2385 893
2443 2442f01 from 2442gat >sa0
2444 2442f02 from 2442gat >sa0
2445 2442f03 from 2442gat >sa0
2446 2446gat nor 3 2 >sa0 >sa1
2388 941
2447 2446f01 from 2446gat >sa0
2448 2446f02 from 2446gat >sa0
2449 2446f03 from 2446gat >sa0
2450 2450gat nor 3 2 >sa0 >sa1
2391 989
2451 2450f01 from 2450gat >sa0
2452 2450f02 from 2450gat >sa0
2453 2450f03 from 2450gat >sa0
2454 2454gat nor 3 2 >sa0 >sa1
2394 1037
2455 2454f01 from 2454gat >sa0
2456 2454f02 from 2454gat >sa0
2457 2454f03 from 2454gat >sa0
2458 2458gat nor 3 2 >sa0 >sa1
2397 1085
2459 2458f01 from 2458gat >sa0
2460 2458f02 from 2458gat >sa0
2461 2458f03 from 2458gat >sa0
2462 2462gat nor 1 2 >sa0
2351 2399
2463 2463gat nor 1 2 >sa0
2400 1132
2464 2464gat nor 2 2 >sa0 >sa1
2261 2401
2465 2464f01 from 2464gat >sa0
2466 2464f02 from 2464gat >sa0
2467 2467gat nor 2 2 >sa0 >sa1
2402 2403
2468 2467f01 from 2467gat >sa0
2469 2467f02 from 2467gat >sa0
2470 2470gat nor 3 2 >sa0 >sa1
2408 2405
2471 2470f01 from 2470gat >sa0
2472 2470f02 from 2470gat >sa0
2473 2470f03 from 2470gat >sa0
2474 2474gat nor 1 2 >sa0
1277 2412
2475 2475gat nor 1 2 >sa0
2413 2361
2476 2476gat nor 1 2 >sa0
2363 2415
2477 2477gat nor 1 2 >sa0
2416 556
2478 2478gat nor 2 2 >sa0 >sa1
2270 2417
2479 2478f01 from 2478gat >sa0
2480 2478f02 from 2478gat >sa0
2481 2481gat nor 1 2 >sa0
2366 2419
2482 2482gat nor 1 2 >sa0
2420 604
2483 2483gat nor 2 2 >sa0 >sa1
2274 2421
2484 2483f01 from 2483gat >sa0
2485 2483f02 from 2483gat >sa0
2486 2486gat nor 1 2 >sa0
2369 2423
2487 2487gat nor 1 2 >sa0
2424 652
2488 2488gat nor 2 2 >sa0 >sa1
2278 2425
2489 2488f01 from 2488gat >sa0
2490 2488f02 from 2488gat >sa0
2491 2491gat nor 1 2 >sa0
2372 2427
2492 2492gat nor 1 2 >sa0
2428 700
2493 2493gat nor 2 2 >sa0 >sa1
2282 2429
2494 2493f01 from 2493gat >sa0
2495 2493f02 from 2493gat >sa0
2496 2496gat nor 1 2 >sa0
2375 2431
2497 2497gat nor 1 2 >sa0
2432 748
2498 2498gat nor 2 2 >sa0 >sa1
2286 2433
2499 2498f01 from 2498gat >sa0
2500 2498f02 from 2498gat >sa0
2501 2501gat nor 1 2 >sa0
2378 2435
2502 2502gat nor 1 2 >sa0
2436 796
2503 2503gat nor 2 2 >sa0 >sa1
2290 2437
2504 2503f01 from 2503gat >sa0
2505 2503f02 from 2503gat >sa0
2506 2506gat nor 1 2 >sa0
2381 2439
2507 2507gat nor 1 2 >sa0
2440 844
2508 2508gat nor 2 2 >sa0 >sa1
2294 2441
2509 2508f01 from 2508gat >sa0
2510 2508f02 from 2508gat >sa0
2511 2511gat nor 1 2 >sa0
2384 2443
2512 2512gat nor 1 2 >sa0
2444 892
2513 2513gat nor 2 2 >sa0 >sa1
2298 2445
2514 2513f01 from 2513gat >sa0
2515 2513f02 from 2513gat >sa0
2516 2516gat nor 1 2 >sa0
2387 2447
2517 2517gat nor 1 2 >sa0
2448 940
2518 2518gat nor 2 2 >sa0 >sa1
2302 2449
2519 2518f01 from 2518gat >sa0
2520 2518f02 from 2518gat >sa0
2521 2521gat nor 1 2 >sa0
2390 2451
2522 2522gat nor 1 2 >sa0
2452 988
2523 2523gat nor 2 2 >sa0 >sa1
2306 2453
2524 2523f01 from 2523gat >sa0
2525 2523f02 from 2523gat >sa0
2526 2526gat nor 1 2 >sa0
2393 2455
2527 2527gat nor 1 2 >sa0
2456 1036
2528 2528gat nor 2 2 >sa0 >sa1
2310 2457
2529 2528f01 from 2528gat >sa0
2530 2528f02 from 2528gat >sa0
2531 2531gat nor 1 2 >sa0
2396 2459
2532 2532gat nor 1 2 >sa0
2460 1084
2533 2533gat nor 2 2 >sa0 >sa1
2314 2461
2534 2533f01 from 2533gat >sa0
2535 2533f02 from 2533gat >sa0
2536 2536gat nor 2 2 >sa0 >sa1
2462 2463
2537 2536f01 from 2536gat >sa0
2538 2536f02 from 2536gat >sa0
2539 2539gat nor 3 2 >sa0 >sa1
2468 2465
2540 2539f01 from 2539gat >sa0
2541 2539f02 from 2539gat >sa0
2542 2539f03 from 2539gat >sa0
2543 2543gat nor 1 2 >sa0
2409 2472
2544 2544gat nor 1 2 >sa0
2473 2406
2545 2545gat nor 2 2 >sa0 >sa1
2474 2475
2546 2545f01 from 2545gat >sa0
2547 2545f02 from 2545gat >sa0
2548 2548gat nor 0 2 >sa0 >sa1
2476 2477
2549 2549gat nor 2 2 >sa0 >sa1
2481 2482
2550 2549f01 from 2549gat >sa0
2551 2549f02 from 2549gat >sa0
2552 2552gat nor 2 2 >sa0 >sa1
2486 2487
2553 2552f01 from 2552gat >sa0
2554 2552f02 from 2552gat >sa0
2555 2555gat nor 2 2 >sa0 >sa1
2491 2492
2556 2555f01 from 2555gat >sa0
2557 2555f02 from 2555gat >sa0
2558 2558gat nor 2 2 >sa0 >sa1
2496 2497
2559 2558f01 from 2558gat >sa0
2560 2558f02 from 2558gat >sa0
2561 2561gat nor 2 2 >sa0 >sa1
2501 2502
2562 2561f01 from 2561gat >sa0
2563 2561f02 from 2561gat >sa0
2564 2564gat nor 2 2 >sa0 >sa1
2506 2507
2565 2564f01 from 2564gat >sa0
2566 2564f02 from 2564gat >sa0
2567 2567gat nor 2 2 >sa0 >sa1
2511 2512
2568 2567f01 from 2567gat >sa0
2569 2567f02 from 2567gat >sa0
2570 2570gat nor 2 2 >sa0 >sa1
2516 2517
2571 2570f01 from 2570gat >sa0
2572 2570f02 from 2570gat >sa0
2573 2573gat nor 2 2 >sa0 >sa1
2521 2522
2574 2573f01 from 2573gat >sa0
2575 2573f02 from 2573gat >sa0
2576 2576gat nor 2 2 >sa0 >sa1
2526 2527
2577 2576f01 from 2576gat >sa0
2578 2576f02 from 2576gat >sa0
2579 2579gat nor 2 2 >sa0 >sa1
2531 2532
2580 2579f01 from 2579gat >sa0
2581 2579f02 from 2579gat >sa0
2582 2582gat nor 3 2 >sa0 >sa1
2537 2534
2583 2582f01 from 2582gat >sa0
2584 2582f02 from 2582gat >sa0
2585 2582f03 from 2582gat >sa0
2586 2586gat nor 1 2 >sa0
2469 2541
2587 2587gat nor 1 2 >sa0
2542 2466
2588 2588gat nor 2 2 >sa0 >sa1
2543 2544
2589 2588f01 from 2588gat >sa0
2590 2588f02 from 2588gat >sa0
2591 2591gat nor 3 2 >sa0 >sa1
2547 1232
2592 2591f01 from 2591gat >sa0
2593 2591f02 from 2591gat >sa0
2594 2591f03 from 2591gat >sa0
2595 2595gat nor 3 2 >sa0 >sa1
2550 2479
2596 2595f01 from 2595gat >sa0
2597 2595f02 from 2595gat >sa0
2598 2595f03 from 2595gat >sa0
2599 2599gat nor 3 2 >sa0 >sa1
2553 2484
2600 2599f01 from 2599gat >sa0
2601 2599f02 from 2599gat >sa0
2602 2599f03 from 2599gat >sa0
2603 2603gat nor 3 2 >sa0 >sa1
2556 2489
2604 2603f01 from 2603gat >sa0
2605 2603f02 from 2603gat >sa0
2606 2603f03 from 2603gat >sa0
2607 2607gat nor 3 2 >sa0 >sa1
2559 2494
2608 2607f01 from 2607gat >sa0
2609 2607f02 from 2607gat >sa0
2610 2607f03 from 2607gat >sa0
2611 2611gat nor 3 2 >sa0 >sa1
2562 2499
2612 2611f01 from 2611gat >sa0
2613 2611f02 from 2611gat >sa0
2614 2611f03 from 2611gat >sa0
2615 2615gat nor 3 2 >sa0 >sa1
2565 2504
2616 2615f01 from 2615gat >sa0
2617 2615f02 from 2615gat >sa0
2618 2615f03 from 2615gat >sa0
2619 2619gat nor 3 2 >sa0 >sa1
2568 2509
2620 2619f01 from 2619gat >sa0
2621 2619f02 from 2619gat >sa0
2622 2619f03 from 2619gat >sa0
2623 2623gat nor 3 2 >sa0 >sa1
2571 2514
2624 2623f01 from 2623gat >sa0
2625 2623f02 from 2623gat >sa0
2626 2623f03 from 2623gat >sa0
2627 2627gat nor 3 2 >sa0 >sa1
2574 2519
2628 2627f01 from 2627gat >sa0
2629 2627f02 from 2627gat >sa0
2630 2627f03 from 2627gat >sa0
2631 2631gat nor 3 2 >sa0 >sa1
2577 2524
2632 2631f01 from 2631gat >sa0
2633 2631f02 from 2631gat >sa0
2634 2631f03 from 2631gat >sa0
2635 2635gat nor 3 2 >sa0 >sa1
2580 2529
2636 2635f01 from 2635gat >sa0
2637 2635f02 from 2635gat >sa0
2638 2635f03 from 2635gat >sa0
2639 2639gat nor 1 2 >sa0
2538 2584
2640 2640gat nor 1 2 >sa0
2585 2535
2641 2641gat nor 2 2 >sa0 >sa1
2586 2587
2642 2641f01 from 2641gat >sa0
2643 2641f02 from 2641gat >sa0
2644 2644gat nor 3 2 >sa0 >sa1
2590 1184
2645 2644f01 from 2644gat >sa0
2646 2644f02 from 2644gat >sa0
2647 2644f03 from 2644gat >sa0
2648 2648gat nor 1 2 >sa0
2546 2592
2649 2649gat nor 1 2 >sa0
2593 1231
2650 2650gat nor 2 2 >sa0 >sa1
2411 2594
2651 2650f01 from 2650gat >sa0
2652 2650f02 from 2650gat >sa0
2653 2653gat nor 1 2 >sa0
2551 2597
2654 2654gat nor 1 2 >sa0
2598 2480
2655 2655gat nor 1 2 >sa0
2554 2601
2656 2656gat nor 1 2 >sa0
2602 2485
2657 2657gat nor 1 2 >sa0
2557 2605
2658 2658gat nor 1 2 >sa0
2606 2490
2659 2659gat nor 1 2 >sa0
2560 2609
2660 2660gat nor 1 2 >sa0
2610 2495
2661 2661gat nor 1 2 >sa0
2563 2613
2662 2662gat nor 1 2 >sa0
2614 2500
2663 2663gat nor 1 2 >sa0
2566 2617
2664 2664gat nor 1 2 >sa0
2618 2505
2665 2665gat nor 1 2 >sa0
2569 2621
2666 2666gat nor 1 2 >sa0
2622 2510
2667 2667gat nor 1 2 >sa0
2572 2625
2668 2668gat nor 1 2 >sa0
2626 2515
2669 2669gat nor 1 2 >sa0
2575 2629
2670 2670gat nor 1 2 >sa0
2630 2520
2671 2671gat nor 1 2 >sa0
2578 2633
2672 2672gat nor 1 2 >sa0
2634 2525
2673 2673gat nor 1 2 >sa0
2581 2637
2674 2674gat nor 1 2 >sa0
2638 2530
2675 2675gat nor 2 2 >sa0 >sa1
2639 2640
2676 2675f01 from 2675gat >sa0
2677 2675f02 from 2675gat >sa0
2678 2678gat nor 3 2 >sa0 >sa1
2643 1136
2679 2678f01 from 2678gat >sa0
2680 2678f02 from 2678gat >sa0
2681 2678f03 from 2678gat >sa0
2682 2682gat nor 1 2 >sa0
2589 2645
2683 2683gat nor 1 2 >sa0
2646 1183
2684 2684gat nor 2 2 >sa0 >sa1
2471 2647
2685 2684f01 from 2684gat >sa0
2686 2684f02 from 2684gat >sa0
2687 2687gat nor 2 2 >sa0 >sa1
2648 2649
2688 2687f01 from 2687gat >sa0
2689 2687f02 from 2687gat >sa0
2690 2690gat nor 3 2 >sa0 >sa1
1279 2651
2691 2690f01 from 2690gat >sa0
2692 2690f02 from 2690gat >sa0
2693 2690f03 from 2690gat >sa0
2694 2694gat nor 2 2 >sa0 >sa1
2653 2654
2695 2694f01 from 2694gat >sa0
2696 2694f02 from 2694gat >sa0
2697 2697gat nor 2 2 >sa0 >sa1
2655 2656
2698 2697f01 from 2697gat >sa0
2699 2697f02 from 2697gat >sa0
2700 2700gat nor 2 2 >sa0 >sa1
2657 2658
2701 2700f01 from 2700gat >sa0
2702 2700f02 from 2700gat >sa0
2703 2703gat nor 2 2 >sa0 >sa1
2659 2660
2704 2703f01 from 2703gat >sa0
2705 2703f02 from 2703gat >sa0
2706 2706gat nor 2 2 >sa0 >sa1
2661 2662
2707 2706f01 from 2706gat >sa0
2708 2706f02 from 2706gat >sa0
2709 2709gat nor 2 2 >sa0 >sa1
2663 2664
2710 2709f01 from 2709gat >sa0
2711 2709f02 from 2709gat >sa0
2712 2712gat nor 2 2 >sa0 >sa1
2665 2666
2713 2712f01 from 2712gat >sa0
2714 2712f02 from 2712gat >sa0
2715 2715gat nor 2 2 >sa0 >sa1
2667 2668
2716 2715f01 from 2715gat >sa0
2717 2715f02 from 2715gat >sa0
2718 2718gat nor 2 2 >sa0 >sa1
2669 2670
2719 2718f01 from 2718gat >sa0
2720 2718f02 from 2718gat >sa0
2721 2721gat nor 2 2 >sa0 >sa1
2671 2672
2722 2721f01 from 2721gat >sa0
2723 2721f02 from 2721gat >sa0
2724 2724gat nor 2 2 >sa0 >sa1
2673 2674
2725 2724f01 from 2724gat >sa0
2726 2724f02 from 2724gat >sa0
2727 2727gat nor 3 2 >sa0 >sa1
2677 1088
2728 2727f01 from 2727gat >sa0
2729 2727f02 from 2727gat >sa0
2730 2727f03 from 2727gat >sa0
2731 2731gat nor 1 2 >sa0
2642 2679
2732 2732gat nor 1 2 >sa0
2680 1135
2733 2733gat nor 2 2 >sa0 >sa1
2540 2681
2734 2733f01 from 2733gat >sa0
2735 2733f02 from 2733gat >sa0
2736 2736gat nor 2 2 >sa0 >sa1
2682 2683
2737 2736f01 from 2736gat >sa0
2738 2736f02 from 2736gat >sa0
2739 2739gat nor 3 2 >sa0 >sa1
2688 2685
2740 2739f01 from 2739gat >sa0
2741 2739f02 from 2739gat >sa0
2742 2739f03 from 2739gat >sa0
2743 2743gat nor 1 2 >sa0
1280 2692
2744 2744gat nor 1 2 >sa0
2693 2652
2745 2745gat nor 3 2 >sa0 >sa1
2696 560
2746 2745f01 from 2745gat >sa0
2747 2745f02 from 2745gat >sa0
2748 2745f03 from 2745gat >sa0
2749 2749gat nor 3 2 >sa0 >sa1
2699 608
2750 2749f01 from 2749gat >sa0
2751 2749f02 from 2749gat >sa0
2752 2749f03 from 2749gat >sa0
2753 2753gat nor 3 2 >sa0 >sa1
2702 656
2754 2753f01 from 2753gat >sa0
2755 2753f02 from 2753gat >sa0
2756 2753f03 from 2753gat >sa0
2757 2757gat nor 3 2 >sa0 >sa1
2705 704
2758 2757f01 from 2757gat >sa0
2759 2757f02 from 2757gat >sa0
2760 2757f03 from 2757gat >sa0
2761 2761gat nor 3 2 >sa0 >sa1
2708 752
2762 2761f01 from 2761gat >sa0
2763 2761f02 from 2761gat >sa0
2764 2761f03 from 2761gat >sa0
2765 2765gat nor 3 2 >sa0 >sa1
2711 800
2766 2765f01 from 2765gat >sa0
2767 2765f02 from 2765gat >sa0
2768 2765f03 from 2765gat >sa0
2769 2769gat nor 3 2 >sa0 >sa1
2714 848
2770 2769f01 from 2769gat >sa0
2771 2769f02 from 2769gat >sa0
2772 2769f03 from 2769gat >sa0
2773 2773gat nor 3 2 >sa0 >sa1
2717 896
2774 2773f01 from 2773gat >sa0
2775 2773f02 from 2773gat >sa0
2776 2773f03 from 2773gat >sa0
2777 2777gat nor 3 2 >sa0 >sa1
2720 944
2778 2777f01 from 2777gat >sa0
2779 2777f02 from 2777gat >sa0
2780 2777f03 from 2777gat >sa0
2781 2781gat nor 3 2 >sa0 >sa1
2723 992
2782 2781f01 from 2781gat >sa0
2783 2781f02 from 2781gat >sa0
2784 2781f03 from 2781gat >sa0
2785 2785gat nor 3 2 >sa0 >sa1
2726 1040
2786 2785f01 from 2785gat >sa0
2787 2785f02 from 2785gat >sa0
2788 2785f03 from 2785gat >sa0
2789 2789gat nor 1 2 >sa0
2676 2728
2790 2790gat nor 1 2 >sa0
2729 1087
2791 2791gat nor 2 2 >sa0 >sa1
2583 2730
2792 2791f01 from 2791gat >sa0
2793 2791f02 from 2791gat >sa0
2794 2794gat nor 2 2 >sa0 >sa1
2731 2732
2795 2794f01 from 2794gat >sa0
2796 2794f02 from 2794gat >sa0
2797 2797gat nor 3 2 >sa0 >sa1
2737 2734
2798 2797f01 from 2797gat >sa0
2799 2797f02 from 2797gat >sa0
2800 2797f03 from 2797gat >sa0
2801 2801gat nor 1 2 >sa0
2689 2741
2802 2802gat nor 1 2 >sa0
2742 2686
2803 2803gat nor 2 2 >sa0 >sa1
2743 2744
2804 2803f01 from 2803gat >sa0
2805 2803f02 from 2803gat >sa0
2806 2806gat nor 1 2 >sa0
2695 2746
2807 2807gat nor 1 2 >sa0
2747 559
2808 2808gat nor 2 2 >sa0 >sa1
2596 2748
2809 2808f01 from 2808gat >sa0
2810 2808f02 from 2808gat >sa0
2811 2811gat nor 1 2 >sa0
2698 2750
2812 2812gat nor 1 2 >sa0
2751 607
2813 2813gat nor 2 2 >sa0 >sa1
2600 2752
2814 2813f01 from 2813gat >sa0
2815 2813f02 from 2813gat >sa0
2816 2816gat nor 1 2 >sa0
2701 2754
2817 2817gat nor 1 2 >sa0
2755 655
2818 2818gat nor 2 2 >sa0 >sa1
2604 2756
2819 2818f01 from 2818gat >sa0
2820 2818f02 from 2818gat >sa0
2821 2821gat nor 1 2 >sa0
2704 2758
2822 2822gat nor 1 2 >sa0
2759 703
2823 2823gat nor 2 2 >sa0 >sa1
2608 2760
2824 2823f01 from 2823gat >sa0
2825 2823f02 from 2823gat >sa0
2826 2826gat nor 1 2 >sa0
2707 2762
2827 2827gat nor 1 2 >sa0
2763 751
2828 2828gat nor 2 2 >sa0 >sa1
2612 2764
2829 2828f01 from 2828gat >sa0
2830 2828f02 from 2828gat >sa0
2831 2831gat nor 1 2 >sa0
2710 2766
2832 2832gat nor 1 2 >sa0
2767 799
2833 2833gat nor 2 2 >sa0 >sa1
2616 2768
2834 2833f01 from 2833gat >sa0
2835 2833f02 from 2833gat >sa0
2836 2836gat nor 1 2 >sa0
2713 2770
2837 2837gat nor 1 2 >sa0
2771 847
2838 2838gat nor 2 2 >sa0 >sa1
2620 2772
2839 2838f01 from 2838gat >sa0
2840 2838f02 from 2838gat >sa0
2841 2841gat nor 1 2 >sa0
2716 2774
2842 2842gat nor 1 2 >sa0
2775 895
2843 2843gat nor 2 2 >sa0 >sa1
2624 2776
2844 2843f01 from 2843gat >sa0
2845 2843f02 from 2843gat >sa0
2846 2846gat nor 1 2 >sa0
2719 2778
2847 2847gat nor 1 2 >sa0
2779 943
2848 2848gat nor 2 2 >sa0 >sa1
2628 2780
2849 2848f01 from 2848gat >sa0
2850 2848f02 from 2848gat >sa0
2851 2851gat nor 1 2 >sa0
2722 2782
2852 2852gat nor 1 2 >sa0
2783 991
2853 2853gat nor 2 2 >sa0 >sa1
2632 2784
2854 2853f01 from 2853gat >sa0
2855 2853f02 from 2853gat >sa0
2856 2856gat nor 1 2 >sa0
2725 2786
2857 2857gat nor 1 2 >sa0
2787 1039
2858 2858gat nor 2 2 >sa0 >sa1
2636 2788
2859 2858f01 from 2858gat >sa0
2860 2858f02 from 2858gat >sa0
2861 2861gat nor 2 2 >sa0 >sa1
2789 2790
2862 2861f01 from 2861gat >sa0
2863 2861f02 from 2861gat >sa0
2864 2864gat nor 3 2 >sa0 >sa1
2795 2792
2865 2864f01 from 2864gat >sa0
2866 2864f02 from 2864gat >sa0
2867 2864f03 from 2864gat >sa0
2868 2868gat nor 1 2 >sa0
2738 2799
2869 2869gat nor 1 2 >sa0
2800 2735
2870 2870gat nor 2 2 >sa0 >sa1
2801 2802
2871 2870f01 from 2870gat >sa0
2872 2870f02 from 2870gat >sa0
2873 2873gat nor 3 2 >sa0 >sa1
2805 1235
2874 2873f01 from 2873gat >sa0
2875 2873f02 from 2873gat >sa0
2876 2873f03 from 2873gat >sa0
2877 2877gat nor 0 2 >sa0 >sa1
2806 2807
2878 2878gat nor 2 2 >sa0 >sa1
2811 2812
2879 2878f01 from 2878gat >sa0
2880 2878f02 from 2878gat >sa0
2881 2881gat nor 2 2 >sa0 >sa1
2816 2817
2882 2881f01 from 2881gat >sa0
2883 2881f02 from 2881gat >sa0
2884 2884gat nor 2 2 >sa0 >sa1
2821 2822
2885 2884f01 from 2884gat >sa0
2886 2884f02 from 2884gat >sa0
2887 2887gat nor 2 2 >sa0 >sa1
2826 2827
2888 2887f01 from 2887gat >sa0
2889 2887f02 from 2887gat >sa0
2890 2890gat nor 2 2 >sa0 >sa1
2831 2832
2891 2890f01 from 2890gat >sa0
2892 2890f02 from 2890gat >sa0
2893 2893gat nor 2 2 >sa0 >sa1
2836 2837
2894 2893f01 from 2893gat >sa0
2895 2893f02 from 2893gat >sa0
2896 2896gat nor 2 2 >sa0 >sa1
2841 2842
2897 2896f01 from 2896gat >sa0
2898 2896f02 from 2896gat >sa0
2899 2899gat nor 2 2 >sa0 >sa1
2846 2847
2900 2899f01 from 2899gat >sa0
2901 2899f02 from 2899gat >sa0
2902 2902gat nor 2 2 >sa0 >sa1
2851 2852
2903 2902f01 from 2902gat >sa0
2904 2902f02 from 2902gat >sa0
2905 2905gat nor 2 2 >sa0 >sa1
2856 2857
2906 2905f01 from 2905gat >sa0
2907 2905f02 from 2905gat >sa0
2908 2908gat nor 3 2 >sa0 >sa1
2862 2859
2909 2908f01 from 2908gat >sa0
2910 2908f02 from 2908gat >sa0
2911 2908f03 from 2908gat >sa0
2912 2912gat nor 1 2 >sa0
2796 2866
2913 2913gat nor 1 2 >sa0
2867 2793
2914 2914gat nor 2 2 >sa0 >sa1
2868 2869
2915 2914f01 from 2914gat >sa0
2916 2914f02 from 2914gat >sa0
2917 2917gat nor 3 2 >sa0 >sa1
2872 1187
2918 2917f01 from 2917gat >sa0
2919 2917f02 from 2917gat >sa0
2920 2917f03 from 2917gat >sa0
2921 2921gat nor 1 2 >sa0
2804 2874
2922 2922gat nor 1 2 >sa0
2875 1234
2923 2923gat nor 2 2 >sa0 >sa1
2691 2876
2924 2923f01 from 2923gat >sa0
2925 2923f02 from 2923gat >sa0
2926 2926gat nor 3 2 >sa0 >sa1
2879 2809
2927 2926f01 from 2926gat >sa0
2928 2926f02 from 2926gat >sa0
2929 2926f03 from 2926gat >sa0
2930 2930gat nor 3 2 >sa0 >sa1
2882 2814
2931 2930f01 from 2930gat >sa0
2932 2930f02 from 2930gat >sa0
2933 2930f03 from 2930gat >sa0
2934 2934gat nor 3 2 >sa0 >sa1
2885 2819
2935 2934f01 from 2934gat >sa0
2936 2934f02 from 2934gat >sa0
2937 2934f03 from 2934gat >sa0
2938 2938gat nor 3 2 >sa0 >sa1
2888 2824
2939 2938f01 from 2938gat >sa0
2940 2938f02 from 2938gat >sa0
2941 2938f03 from 2938gat >sa0
2942 2942gat nor 3 2 >sa0 >sa1
2891 2829
2943 2942f01 from 2942gat >sa0
2944 2942f02 from 2942gat >sa0
2945 2942f03 from 2942gat >sa0
2946 2946gat nor 3 2 >sa0 >sa1
2894 2834
2947 2946f01 from 2946gat >sa0
2948 2946f02 from 2946gat >sa0
2949 2946f03 from 2946gat >sa0
2950 2950gat nor 3 2 >sa0 >sa1
2897 2839
2951 2950f01 from 2950gat >sa0
2952 2950f02 from 2950gat >sa0
2953 2950f03 from 2950gat >sa0
2954 2954gat nor 3 2 >sa0 >sa1
2900 2844
2955 2954f01 from 2954gat >sa0
2956 2954f02 from 2954gat >sa0
2957 2954f03 from 2954gat >sa0
2958 2958gat nor 3 2 >sa0 >sa1
2903 2849
2959 2958f01 from 2958gat >sa0
2960 2958f02 from 2958gat >sa0
2961 2958f03 from 2958gat >sa0
2962 2962gat nor 3 2 >sa0 >sa1
2906 2854
2963 2962f01 from 2962gat >sa0
2964 2962f02 from 2962gat >sa0
2965 2962f03 from 2962gat >sa0
2966 2966gat nor 1 2 >sa0
2863 2910
2967 2967gat nor 1 2 >sa0
2911 2860
2968 2968gat nor 2 2 >sa0 >sa1
2912 2913
2969 2968f01 from 2968gat >sa0
2970 2968f02 from 2968gat >sa0
2971 2971gat nor 3 2 >sa0 >sa1
2916 1139
2972 2971f01 from 2971gat >sa0
2973 2971f02 from 2971gat >sa0
2974 2971f03 from 2971gat >sa0
2975 2975gat nor 1 2 >sa0
2871 2918
2976 2976gat nor 1 2 >sa0
2919 1186
2977 2977gat nor 2 2 >sa0 >sa1
2740 2920
2978 2977f01 from 2977gat >sa0
2979 2977f02 from 2977gat >sa0
2980 2980gat nor 2 2 >sa0 >sa1
2921 2922
2981 2980f01 from 2980gat >sa0
2982 2980f02 from 2980gat >sa0
2983 2983gat nor 3 2 >sa0 >sa1
1282 2924
2984 2983f01 from 2983gat >sa0
2985 2983f02 from 2983gat >sa0
2986 2983f03 from 2983gat >sa0
2987 2987gat nor 1 2 >sa0
2880 2928
2988 2988gat nor 1 2 >sa0
2929 2810
2989 2989gat nor 1 2 >sa0
2883 2932
2990 2990gat nor 1 2 >sa0
2933 2815
2991 2991gat nor 1 2 >sa0
2886 2936
2992 2992gat nor 1 2 >sa0
2937 2820
2993 2993gat nor 1 2 >sa0
2889 2940
2994 2994gat nor 1 2 >sa0
2941 2825
2995 2995gat nor 1 2 >sa0
2892 2944
2996 2996gat nor 1 2 >sa0
2945 2830
2997 2997gat nor 1 2 >sa0
2895 2948
2998 2998gat nor 1 2 >sa0
2949 2835
2999 2999gat nor 1 2 >sa0
2898 2952
3000 3000gat nor 1 2 >sa0
2953 2840
3001 3001gat nor 1 2 >sa0
2901 2956
3002 3002gat nor 1 2 >sa0
2957 2845
3003 3003gat nor 1 2 >sa0
2904 2960
3004 3004gat nor 1 2 >sa0
2961 2850
3005 3005gat nor 1 2 >sa0
2907 2964
3006 3006gat nor 1 2 >sa0
2965 2855
3007 3007gat nor 2 2 >sa0 >sa1
2966 2967
3008 3007f01 from 3007gat >sa0
3009 3007f02 from 3007gat >sa0
3010 3010gat nor 3 2 >sa0 >sa1
2970 1091
3011 3010f01 from 3010gat >sa0
3012 3010f02 from 3010gat >sa0
3013 3010f03 from 3010gat >sa0
3014 3014gat nor 1 2 >sa0
2915 2972
3015 3015gat nor 1 2 >sa0
2973 1138
3016 3016gat nor 2 2 >sa0 >sa1
2798 2974
3017 3016f01 from 3016gat >sa0
3018 3016f02 from 3016gat >sa0
3019 3019gat nor 2 2 >sa0 >sa1
2975 2976
3020 3019f01 from 3019gat >sa0
3021 3019f02 from 3019gat >sa0
3022 3022gat nor 3 2 >sa0 >sa1
2981 2978
3023 3022f01 from 3022gat >sa0
3024 3022f02 from 3022gat >sa0
3025 3022f03 from 3022gat >sa0
3026 3026gat nor 1 2 >sa0
1283 2985
3027 3027gat nor 1 2 >sa0
2986 2925
3028 3028gat nor 2 2 >sa0 >sa1
2987 2988
3029 3028f01 from 3028gat >sa0
3030 3028f02 from 3028gat >sa0
3031 3031gat nor 2 2 >sa0 >sa1
2989 2990
3032 3031f01 from 3031gat >sa0
3033 3031f02 from 3031gat >sa0
3034 3034gat nor 2 2 >sa0 >sa1
2991 2992
3035 3034f01 from 3034gat >sa0
3036 3034f02 from 3034gat >sa0
3037 3037gat nor 2 2 >sa0 >sa1
2993 2994
3038 3037f01 from 3037gat >sa0
3039 3037f02 from 3037gat >sa0
3040 3040gat nor 2 2 >sa0 >sa1
2995 2996
3041 3040f01 from 3040gat >sa0
3042 3040f02 from 3040gat >sa0
3043 3043gat nor 2 2 >sa0 >sa1
2997 2998
3044 3043f01 from 3043gat >sa0
3045 3043f02 from 3043gat >sa0
3046 3046gat nor 2 2 >sa0 >sa1
2999 3000
3047 3046f01 from 3046gat >sa0
3048 3046f02 from 3046gat >sa0
3049 3049gat nor 2 2 >sa0 >sa1
3001 3002
3050 3049f01 from 3049gat >sa0
3051 3049f02 from 3049gat >sa0
3052 3052gat nor 2 2 >sa0 >sa1
3003 3004
3053 3052f01 from 3052gat >sa0
3054 3052f02 from 3052gat >sa0
3055 3055gat nor 2 2 >sa0 >sa1
3005 3006
3056 3055f01 from 3055gat >sa0
3057 3055f02 from 3055gat >sa0
3058 3058gat nor 3 2 >sa0 >sa1
3009 1043
3059 3058f01 from 3058gat >sa0
3060 3058f02 from 3058gat >sa0
3061 3058f03 from 3058gat >sa0
3062 3062gat nor 1 2 >sa0
2969 3011
3063 3063gat nor 1 2 >sa0
3012 1090
3064 3064gat nor 2 2 >sa0 >sa1
2865 3013
3065 3064f01 from 3064gat >sa0
3066 3064f02 from 3064gat >sa0
3067 3067gat nor 2 2 >sa0 >sa1
3014 3015
3068 3067f01 from 3067gat >sa0
3069 3067f02 from 3067gat >sa0
3070 3070gat nor 3 2 >sa0 >sa1
3020 3017
3071 3070f01 from 3070gat >sa0
3072 3070f02 from 3070gat >sa0
3073 3070f03 from 3070gat >sa0
3074 3074gat nor 1 2 >sa0
2982 3024
3075 3075gat nor 1 2 >sa0
3025 2979
3076 3076gat nor 2 2 >sa0 >sa1
3026 3027
3077 3076f01 from 3076gat >sa0
3078 3076f02 from 3076gat >sa0
3079 3079gat nor 3 2 >sa0 >sa1
3030 563
3080 3079f01 from 3079gat >sa0
3081 3079f02 from 3079gat >sa0
3082 3079f03 from 3079gat >sa0
3083 3083gat nor 3 2 >sa0 >sa1
3033 611
3084 3083f01 from 3083gat >sa0
3085 3083f02 from 3083gat >sa0
3086 3083f03 from 3083gat >sa0
3087 3087gat nor 3 2 >sa0 >sa1
3036 659
3088 3087f01 from 3087gat >sa0
3089 3087f02 from 3087gat >sa0
3090 3087f03 from 3087gat >sa0
3091 3091gat nor 3 2 >sa0 >sa1
3039 707
3092 3091f01 from 3091gat >sa0
3093 3091f02 from 3091gat >sa0
3094 3091f03 from 3091gat >sa0
3095 3095gat nor 3 2 >sa0 >sa1
3042 755
3096 3095f01 from 3095gat >sa0
3097 3095f02 from 3095gat >sa0
3098 3095f03 from 3095gat >sa0
3099 3099gat nor 3 2 >sa0 >sa1
3045 803
3100 3099f01 from 3099gat >sa0
3101 3099f02 from 3099gat >sa0
3102 3099f03 from 3099gat >sa0
3103 3103gat nor 3 2 >sa0 >sa1
3048 851
3104 3103f01 from 3103gat >sa0
3105 3103f02 from 3103gat >sa0
3106 3103f03 from 3103gat >sa0
3107 3107gat nor 3 2 >sa0 >sa1
3051 899
3108 3107f01 from 3107gat >sa0
3109 3107f02 from 3107gat >sa0
3110 3107f03 from 3107gat >sa0
3111 3111gat nor 3 2 >sa0 >sa1
3054 947
3112 3111f01 from 3111gat >sa0
3113 3111f02 from 3111gat >sa0
3114 3111f03 from 3111gat >sa0
3115 3115gat nor 3 2 >sa0 >sa1
3057 995
3116 3115f01 from 3115gat >sa0
3117 3115f02 from 3115gat >sa0
3118 3115f03 from 3115gat >sa0
3119 3119gat nor 1 2 >sa0
3008 3059
3120 3120gat nor 1 2 >sa0
3060 1042
3121 3121gat nor 2 2 >sa0 >sa1
2909 3061
3122 3121f01 from 3121gat >sa0
3123 3121f02 from 3121gat >sa0
3124 3124gat nor 2 2 >sa0 >sa1
3062 3063
3125 3124f01 from 3124gat >sa0
3126 3124f02 from 3124gat >sa0
3127 3127gat nor 3 2 >sa0 >sa1
3068 3065
3128 3127f01 from 3127gat >sa0
3129 3127f02 from 3127gat >sa0
3130 3127f03 from 3127gat >sa0
3131 3131gat nor 1 2 >sa0
3021 3072
3132 3132gat nor 1 2 >sa0
3073 3018
3133 3133gat nor 2 2 >sa0 >sa1
3074 3075
3134 3133f01 from 3133gat >sa0
3135 3133f02 from 3133gat >sa0
3136 3136gat nor 3 2 >sa0 >sa1
3078 1238
3137 3136f01 from 3136gat >sa0
3138 3136f02 from 3136gat >sa0
3139 3136f03 from 3136gat >sa0
3140 3140gat nor 1 2 >sa0
3029 3080
3141 3141gat nor 1 2 >sa0
3081 562
3142 3142gat nor 2 2 >sa0 >sa1
2927 3082
3143 3142f01 from 3142gat >sa0
3144 3142f02 from 3142gat >sa0
3145 3145gat nor 1 2 >sa0
3032 3084
3146 3146gat nor 1 2 >sa0
3085 610
3147 3147gat nor 2 2 >sa0 >sa1
2931 3086
3148 3147f01 from 3147gat >sa0
3149 3147f02 from 3147gat >sa0
3150 3150gat nor 1 2 >sa0
3035 3088
3151 3151gat nor 1 2 >sa0
3089 658
3152 3152gat nor 2 2 >sa0 >sa1
2935 3090
3153 3152f01 from 3152gat >sa0
3154 3152f02 from 3152gat >sa0
3155 3155gat nor 1 2 >sa0
3038 3092
3156 3156gat nor 1 2 >sa0
3093 706
3157 3157gat nor 2 2 >sa0 >sa1
2939 3094
3158 3157f01 from 3157gat >sa0
3159 3157f02 from 3157gat >sa0
3160 3160gat nor 1 2 >sa0
3041 3096
3161 3161gat nor 1 2 >sa0
3097 754
3162 3162gat nor 2 2 >sa0 >sa1
2943 3098
3163 3162f01 from 3162gat >sa0
3164 3162f02 from 3162gat >sa0
3165 3165gat nor 1 2 >sa0
3044 3100
3166 3166gat nor 1 2 >sa0
3101 802
3167 3167gat nor 2 2 >sa0 >sa1
2947 3102
3168 3167f01 from 3167gat >sa0
3169 3167f02 from 3167gat >sa0
3170 3170gat nor 1 2 >sa0
3047 3104
3171 3171gat nor 1 2 >sa0
3105 850
3172 3172gat nor 2 2 >sa0 >sa1
2951 3106
3173 3172f01 from 3172gat >sa0
3174 3172f02 from 3172gat >sa0
3175 3175gat nor 1 2 >sa0
3050 3108
3176 3176gat nor 1 2 >sa0
3109 898
3177 3177gat nor 2 2 >sa0 >sa1
2955 3110
3178 3177f01 from 3177gat >sa0
3179 3177f02 from 3177gat >sa0
3180 3180gat nor 1 2 >sa0
3053 3112
3181 3181gat nor 1 2 >sa0
3113 946
3182 3182gat nor 2 2 >sa0 >sa1
2959 3114
3183 3182f01 from 3182gat >sa0
3184 3182f02 from 3182gat >sa0
3185 3185gat nor 1 2 >sa0
3056 3116
3186 3186gat nor 1 2 >sa0
3117 994
3187 3187gat nor 2 2 >sa0 >sa1
2963 3118
3188 3187f01 from 3187gat >sa0
3189 3187f02 from 3187gat >sa0
3190 3190gat nor 2 2 >sa0 >sa1
3119 3120
3191 3190f01 from 3190gat >sa0
3192 3190f02 from 3190gat >sa0
3193 3193gat nor 3 2 >sa0 >sa1
3125 3122
3194 3193f01 from 3193gat >sa0
3195 3193f02 from 3193gat >sa0
3196 3193f03 from 3193gat >sa0
3197 3197gat nor 1 2 >sa0
3069 3129
3198 3198gat nor 1 2 >sa0
3130 3066
3199 3199gat nor 2 2 >sa0 >sa1
3131 3132
3200 3199f01 from 3199gat >sa0
3201 3199f02 from 3199gat >sa0
3202 3202gat nor 3 2 >sa0 >sa1
3135 1190
3203 3202f01 from 3202gat >sa0
3204 3202f02 from 3202gat >sa0
3205 3202f03 from 3202gat >sa0
3206 3206gat nor 1 2 >sa0
3077 3137
3207 3207gat nor 1 2 >sa0
3138 1237
3208 3208gat nor 2 2 >sa0 >sa1
2984 3139
3209 3208f01 from 3208gat >sa0
3210 3208f02 from 3208gat >sa0
3211 3211gat nor 0 2 >sa0 >sa1
3140 3141
3212 3212gat nor 2 2 >sa0 >sa1
3145 3146
3213 3212f01 from 3212gat >sa0
3214 3212f02 from 3212gat >sa0
3215 3215gat nor 2 2 >sa0 >sa1
3150 3151
3216 3215f01 from 3215gat >sa0
3217 3215f02 from 3215gat >sa0
3218 3218gat nor 2 2 >sa0 >sa1
3155 3156
3219 3218f01 from 3218gat >sa0
3220 3218f02 from 3218gat >sa0
3221 3221gat nor 2 2 >sa0 >sa1
3160 3161
3222 3221f01 from 3221gat >sa0
3223 3221f02 from 3221gat >sa0
3224 3224gat nor 2 2 >sa0 >sa1
3165 3166
3225 3224f01 from 3224gat >sa0
3226 3224f02 from 3224gat >sa0
3227 3227gat nor 2 2 >sa0 >sa1
3170 3171
3228 3227f01 from 3227gat >sa0
3229 3227f02 from 3227gat >sa0
3230 3230gat nor 2 2 >sa0 >sa1
3175 3176
3231 3230f01 from 3230gat >sa0
3232 3230f02 from 3230gat >sa0
3233 3233gat nor 2 2 >sa0 >sa1
3180 3181
3234 3233f01 from 3233gat >sa0
3235 3233f02 from 3233gat >sa0
3236 3236gat nor 2 2 >sa0 >sa1
3185 3186
3237 3236f01 from 3236gat >sa0
3238 3236f02 from 3236gat >sa0
3239 3239gat nor 3 2 >sa0 >sa1
3191 3188
3240 3239f01 from 3239gat >sa0
3241 3239f02 from 3239gat >sa0
3242 3239f03 from 3239gat >sa0
3243 3243gat nor 1 2 >sa0
3126 3195
3244 3244gat nor 1 2 >sa0
3196 3123
3245 3245gat nor 2 2 >sa0 >sa1
3197 3198
3246 3245f01 from 3245gat >sa0
3247 3245f02 from 3245gat >sa0
3248 3248gat nor 3 2 >sa0 >sa1
3201 1142
3249 3248f01 from 3248gat >sa0
3250 3248f02 from 3248gat >sa0
3251 3248f03 from 3248gat >sa0
3252 3252gat nor 1 2 >sa0
3134 3203
3253 3253gat nor 1 2 >sa0
3204 1189
3254 3254gat nor 2 2 >sa0 >sa1
3023 3205
3255 3254f01 from 3254gat >sa0
3256 3254f02 from 3254gat >sa0
3257 3257gat nor 2 2 >sa0 >sa1
3206 3207
3258 3257f01 from 3257gat >sa0
3259 3257f02 from 3257gat >sa0
3260 3260gat nor 3 2 >sa0 >sa1
1285 3209
3261 3260f01 from 3260gat >sa0
3262 3260f02 from 3260gat >sa0
3263 3260f03 from 3260gat >sa0
3264 3264gat nor 3 2 >sa0 >sa1
3213 3143
3265 3264f01 from 3264gat >sa0
3266 3264f02 from 3264gat >sa0
3267 3264f03 from 3264gat >sa0
3268 3268gat nor 3 2 >sa0 >sa1
3216 3148
3269 3268f01 from 3268gat >sa0
3270 3268f02 from 3268gat >sa0
3271 3268f03 from 3268gat >sa0
3272 3272gat nor 3 2 >sa0 >sa1
3219 3153
3273 3272f01 from 3272gat >sa0
3274 3272f02 from 3272gat >sa0
3275 3272f03 from 3272gat >sa0
3276 3276gat nor 3 2 >sa0 >sa1
3222 3158
3277 3276f01 from 3276gat >sa0
3278 3276f02 from 3276gat >sa0
3279 3276f03 from 3276gat >sa0
3280 3280gat nor 3 2 >sa0 >sa1
3225 3163
3281 3280f01 from 3280gat >sa0
3282 3280f02 from 3280gat >sa0
3283 3280f03 from 3280gat >sa0
3284 3284gat nor 3 2 >sa0 >sa1
3228 3168
3285 3284f01 from 3284gat >sa0
3286 3284f02 from 3284gat >sa0
3287 3284f03 from 3284gat >sa0
3288 3288gat nor 3 2 >sa0 >sa1
3231 3173
3289 3288f01 from 3288gat >sa0
3290 3288f02 from 3288gat >sa0
3291 3288f03 from 3288gat >sa0
3292 3292gat nor 3 2 >sa0 >sa1
3234 3178
3293 3292f01 from 3292gat >sa0
3294 3292f02 from 3292gat >sa0
3295 3292f03 from 3292gat >sa0
3296 3296gat nor 3 2 >sa0 >sa1
3237 3183
3297 3296f01 from 3296gat >sa0
3298 3296f02 from 3296gat >sa0
3299 3296f03 from 3296gat >sa0
3300 3300gat nor 1 2 >sa0
3192 3241
3301 3301gat nor 1 2 >sa0
3242 3189
3302 3302gat nor 2 2 >sa0 >sa1
3243 3244
3303 3302f01 from 3302gat >sa0
3304 3302f02 from 3302gat >sa0
3305 3305gat nor 3 2 >sa0 >sa1
3247 1094
3306 3305f01 from 3305gat >sa0
3307 3305f02 from 3305gat >sa0
3308 3305f03 from 3305gat >sa0
3309 3309gat nor 1 2 >sa0
3200 3249
3310 3310gat nor 1 2 >sa0
3250 1141
3311 3311gat nor 2 2 >sa0 >sa1
3071 3251
3312 3311f01 from 3311gat >sa0
3313 3311f02 from 3311gat >sa0
3314 3314gat nor 2 2 >sa0 >sa1
3252 3253
3315 3314f01 from 3314gat >sa0
3316 3314f02 from 3314gat >sa0
3317 3317gat nor 3 2 >sa0 >sa1
3258 3255
3318 3317f01 from 3317gat >sa0
3319 3317f02 from 3317gat >sa0
3320 3317f03 from 3317gat >sa0
3321 3321gat nor 1 2 >sa0
1286 3262
3322 3322gat nor 1 2 >sa0
3263 3210
3323 3323gat nor 1 2 >sa0
3214 3266
3324 3324gat nor 1 2 >sa0
3267 3144
3325 3325gat nor 1 2 >sa0
3217 3270
3326 3326gat nor 1 2 >sa0
3271 3149
3327 3327gat nor 1 2 >sa0
3220 3274
3328 3328gat nor 1 2 >sa0
3275 3154
3329 3329gat nor 1 2 >sa0
3223 3278
3330 3330gat nor 1 2 >sa0
3279 3159
3331 3331gat nor 1 2 >sa0
3226 3282
3332 3332gat nor 1 2 >sa0
3283 3164
3333 3333gat nor 1 2 >sa0
3229 3286
3334 3334gat nor 1 2 >sa0
3287 3169
3335 3335gat nor 1 2 >sa0
3232 3290
3336 3336gat nor 1 2 >sa0
3291 3174
3337 3337gat nor 1 2 >sa0
3235 3294
3338 3338gat nor 1 2 >sa0
3295 3179
3339 3339gat nor 1 2 >sa0
3238 3298
3340 3340gat nor 1 2 >sa0
3299 3184
3341 3341gat nor 2 2 >sa0 >sa1
3300 3301
3342 3341f01 from 3341gat >sa0
3343 3341f02 from 3341gat >sa0
3344 3344gat nor 3 2 >sa0 >sa1
3304 1046
3345 3344f01 from 3344gat >sa0
3346 3344f02 from 3344gat >sa0
3347 3344f03 from 3344gat >sa0
3348 3348gat nor 1 2 >sa0
3246 3306
3349 3349gat nor 1 2 >sa0
3307 1093
3350 3350gat nor 2 2 >sa0 >sa1
3128 3308
3351 3350f01 from 3350gat >sa0
3352 3350f02 from 3350gat >sa0
3353 3353gat nor 2 2 >sa0 >sa1
3309 3310
3354 3353f01 from 3353gat >sa0
3355 3353f02 from 3353gat >sa0
3356 3356gat nor 3 2 >sa0 >sa1
3315 3312
3357 3356f01 from 3356gat >sa0
3358 3356f02 from 3356gat >sa0
3359 3356f03 from 3356gat >sa0
3360 3360gat nor 1 2 >sa0
3259 3319
3361 3361gat nor 1 2 >sa0
3320 3256
3362 3362gat nor 2 2 >sa0 >sa1
3321 3322
3363 3362f01 from 3362gat >sa0
3364 3362f02 from 3362gat >sa0
3365 3365gat nor 2 2 >sa0 >sa1
3323 3324
3366 3365f01 from 3365gat >sa0
3367 3365f02 from 3365gat >sa0
3368 3368gat nor 2 2 >sa0 >sa1
3325 3326
3369 3368f01 from 3368gat >sa0
3370 3368f02 from 3368gat >sa0
3371 3371gat nor 2 2 >sa0 >sa1
3327 3328
3372 3371f01 from 3371gat >sa0
3373 3371f02 from 3371gat >sa0
3374 3374gat nor 2 2 >sa0 >sa1
3329 3330
3375 3374f01 from 3374gat >sa0
3376 3374f02 from 3374gat >sa0
3377 3377gat nor 2 2 >sa0 >sa1
3331 3332
3378 3377f01 from 3377gat >sa0
3379 3377f02 from 3377gat >sa0
3380 3380gat nor 2 2 >sa0 >sa1
3333 3334
3381 3380f01 from 3380gat >sa0
3382 3380f02 from 3380gat >sa0
3383 3383gat nor 2 2 >sa0 >sa1
3335 3336
3384 3383f01 from 3383gat >sa0
3385 3383f02 from 3383gat >sa0
3386 3386gat nor 2 2 >sa0 >sa1
3337 3338
3387 3386f01 from 3386gat >sa0
3388 3386f02 from 3386gat >sa0
3389 3389gat nor 2 2 >sa0 >sa1
3339 3340
3390 3389f01 from 3389gat >sa0
3391 3389f02 from 3389gat >sa0
3392 3392gat nor 3 2 >sa0 >sa1
3343 998
3393 3392f01 from 3392gat >sa0
3394 3392f02 from 3392gat >sa0
3395 3392f03 from 3392gat >sa0
3396 3396gat nor 1 2 >sa0
3303 3345
3397 3397gat nor 1 2 >sa0
3346 1045
3398 3398gat nor 2 2 >sa0 >sa1
3194 3347
3399 3398f01 from 3398gat >sa0
3400 3398f02 from 3398gat >sa0
3401 3401gat nor 2 2 >sa0 >sa1
3348 3349
3402 3401f01 from 3401gat >sa0
3403 3401f02 from 3401gat >sa0
3404 3404gat nor 3 2 >sa0 >sa1
3354 3351
3405 3404f01 from 3404gat >sa0
3406 3404f02 from 3404gat >sa0
3407 3404f03 from 3404gat >sa0
3408 3408gat nor 1 2 >sa0
3316 3358
3409 3409gat nor 1 2 >sa0
3359 3313
3410 3410gat nor 2 2 >sa0 >sa1
3360 3361
3411 3410f01 from 3410gat >sa0
3412 3410f02 from 3410gat >sa0
3413 3413gat nor 3 2 >sa0 >sa1
3364 1241
3414 3413f01 from 3413gat >sa0
3415 3413f02 from 3413gat >sa0
3416 3413f03 from 3413gat >sa0
3417 3417gat nor 3 2 >sa0 >sa1
3367 566
3418 3417f01 from 3417gat >sa0
3419 3417f02 from 3417gat >sa0
3420 3417f03 from 3417gat >sa0
3421 3421gat nor 3 2 >sa0 >sa1
3370 614
3422 3421f01 from 3421gat >sa0
3423 3421f02 from 3421gat >sa0
3424 3421f03 from 3421gat >sa0
3425 3425gat nor 3 2 >sa0 >sa1
3373 662
3426 3425f01 from 3425gat >sa0
3427 3425f02 from 3425gat >sa0
3428 3425f03 from 3425gat >sa0
3429 3429gat nor 3 2 >sa0 >sa1
3376 710
3430 3429f01 from 3429gat >sa0
3431 3429f02 from 3429gat >sa0
3432 3429f03 from 3429gat >sa0
3433 3433gat nor 3 2 >sa0 >sa1
3379 758
3434 3433f01 from 3433gat >sa0
3435 3433f02 from 3433gat >sa0
3436 3433f03 from 3433gat >sa0
3437 3437gat nor 3 2 >sa0 >sa1
3382 806
3438 3437f01 from 3437gat >sa0
3439 3437f02 from 3437gat >sa0
3440 3437f03 from 3437gat >sa0
3441 3441gat nor 3 2 >sa0 >sa1
3385 854
3442 3441f01 from 3441gat >sa0
3443 3441f02 from 3441gat >sa0
3444 3441f03 from 3441gat >sa0
3445 3445gat nor 3 2 >sa0 >sa1
3388 902
3446 3445f01 from 3445gat >sa0
3447 3445f02 from 3445gat >sa0
3448 3445f03 from 3445gat >sa0
3449 3449gat nor 3 2 >sa0 >sa1
3391 950
3450 3449f01 from 3449gat >sa0
3451 3449f02 from 3449gat >sa0
3452 3449f03 from 3449gat >sa0
3453 3453gat nor 1 2 >sa0
3342 3393
3454 3454gat nor 1 2 >sa0
3394 997
3455 3455gat nor 2 2 >sa0 >sa1
3240 3395
3456 3455f01 from 3455gat >sa0
3457 3455f02 from 3455gat >sa0
3458 3458gat nor 2 2 >sa0 >sa1
3396 3397
3459 3458f01 from 3458gat >sa0
3460 3458f02 from 3458gat >sa0
3461 3461gat nor 3 2 >sa0 >sa1
3402 3399
3462 3461f01 from 3461gat >sa0
3463 3461f02 from 3461gat >sa0
3464 3461f03 from 3461gat >sa0
3465 3465gat nor 1 2 >sa0
3355 3406
3466 3466gat nor 1 2 >sa0
3407 3352
3467 3467gat nor 2 2 >sa0 >sa1
3408 3409
3468 3467f01 from 3467gat >sa0
3469 3467f02 from 3467gat >sa0
3470 3470gat nor 3 2 >sa0 >sa1
3412 1193
3471 3470f01 from 3470gat >sa0
3472 3470f02 from 3470gat >sa0
3473 3470f03 from 3470gat >sa0
3474 3474gat nor 1 2 >sa0
3363 3414
3475 3475gat nor 1 2 >sa0
3415 1240
3476 3476gat nor 2 2 >sa0 >sa1
3261 3416
3477 3476f01 from 3476gat >sa0
3478 3476f02 from 3476gat >sa0
3479 3479gat nor 1 2 >sa0
3366 3418
3480 3480gat nor 1 2 >sa0
3419 565
3481 3481gat nor 2 2 >sa0 >sa1
3265 3420
3482 3481f01 from 3481gat >sa0
3483 3481f02 from 3481gat >sa0
3484 3484gat nor 1 2 >sa0
3369 3422
3485 3485gat nor 1 2 >sa0
3423 613
3486 3486gat nor 2 2 >sa0 >sa1
3269 3424
3487 3486f01 from 3486gat >sa0
3488 3486f02 from 3486gat >sa0
3489 3489gat nor 1 2 >sa0
3372 3426
3490 3490gat nor 1 2 >sa0
3427 661
3491 3491gat nor 2 2 >sa0 >sa1
3273 3428
3492 3491f01 from 3491gat >sa0
3493 3491f02 from 3491gat >sa0
3494 3494gat nor 1 2 >sa0
3375 3430
3495 3495gat nor 1 2 >sa0
3431 709
3496 3496gat nor 2 2 >sa0 >sa1
3277 3432
3497 3496f01 from 3496gat >sa0
3498 3496f02 from 3496gat >sa0
3499 3499gat nor 1 2 >sa0
3378 3434
3500 3500gat nor 1 2 >sa0
3435 757
3501 3501gat nor 2 2 >sa0 >sa1
3281 3436
3502 3501f01 from 3501gat >sa0
3503 3501f02 from 3501gat >sa0
3504 3504gat nor 1 2 >sa0
3381 3438
3505 3505gat nor 1 2 >sa0
3439 805
3506 3506gat nor 2 2 >sa0 >sa1
3285 3440
3507 3506f01 from 3506gat >sa0
3508 3506f02 from 3506gat >sa0
3509 3509gat nor 1 2 >sa0
3384 3442
3510 3510gat nor 1 2 >sa0
3443 853
3511 3511gat nor 2 2 >sa0 >sa1
3289 3444
3512 3511f01 from 3511gat >sa0
3513 3511f02 from 3511gat >sa0
3514 3514gat nor 1 2 >sa0
3387 3446
3515 3515gat nor 1 2 >sa0
3447 901
3516 3516gat nor 2 2 >sa0 >sa1
3293 3448
3517 3516f01 from 3516gat >sa0
3518 3516f02 from 3516gat >sa0
3519 3519gat nor 1 2 >sa0
3390 3450
3520 3520gat nor 1 2 >sa0
3451 949
3521 3521gat nor 2 2 >sa0 >sa1
3297 3452
3522 3521f01 from 3521gat >sa0
3523 3521f02 from 3521gat >sa0
3524 3524gat nor 2 2 >sa0 >sa1
3453 3454
3525 3524f01 from 3524gat >sa0
3526 3524f02 from 3524gat >sa0
3527 3527gat nor 3 2 >sa0 >sa1
3459 3456
3528 3527f01 from 3527gat >sa0
3529 3527f02 from 3527gat >sa0
3530 3527f03 from 3527gat >sa0
3531 3531gat nor 1 2 >sa0
3403 3463
3532 3532gat nor 1 2 >sa0
3464 3400
3533 3533gat nor 2 2 >sa0 >sa1
3465 3466
3534 3533f01 from 3533gat >sa0
3535 3533f02 from 3533gat >sa0
3536 3536gat nor 3 2 >sa0 >sa1
3469 1145
3537 3536f01 from 3536gat >sa0
3538 3536f02 from 3536gat >sa0
3539 3536f03 from 3536gat >sa0
3540 3540gat nor 1 2 >sa0
3411 3471
3541 3541gat nor 1 2 >sa0
3472 1192
3542 3542gat nor 2 2 >sa0 >sa1
3318 3473
3543 3542f01 from 3542gat >sa0
3544 3542f02 from 3542gat >sa0
3545 3545gat nor 2 2 >sa0 >sa1
3474 3475
3546 3545f01 from 3545gat >sa0
3547 3545f02 from 3545gat >sa0
3548 3548gat nor 3 2 >sa0 >sa1
1288 3477
3549 3548f01 from 3548gat >sa0
3550 3548f02 from 3548gat >sa0
3551 3548f03 from 3548gat >sa0
3552 3552gat nor 0 2 >sa0 >sa1
3479 3480
3553 3553gat nor 2 2 >sa0 >sa1
3484 3485
3554 3553f01 from 3553gat >sa0
3555 3553f02 from 3553gat >sa0
3556 3556gat nor 2 2 >sa0 >sa1
3489 3490
3557 3556f01 from 3556gat >sa0
3558 3556f02 from 3556gat >sa0
3559 3559gat nor 2 2 >sa0 >sa1
3494 3495
3560 3559f01 from 3559gat >sa0
3561 3559f02 from 3559gat >sa0
3562 3562gat nor 2 2 >sa0 >sa1
3499 3500
3563 3562f01 from 3562gat >sa0
3564 3562f02 from 3562gat >sa0
3565 3565gat nor 2 2 >sa0 >sa1
3504 3505
3566 3565f01 from 3565gat >sa0
3567 3565f02 from 3565gat >sa0
3568 3568gat nor 2 2 >sa0 >sa1
3509 3510
3569 3568f01 from 3568gat >sa0
3570 3568f02 from 3568gat >sa0
3571 3571gat nor 2 2 >sa0 >sa1
3514 3515
3572 3571f01 from 3571gat >sa0
3573 3571f02 from 3571gat >sa0
3574 3574gat nor 2 2 >sa0 >sa1
3519 3520
3575 3574f01 from 3574gat >sa0
3576 3574f02 from 3574gat >sa0
3577 3577gat nor 3 2 >sa0 >sa1
3525 3522
3578 3577f01 from 3577gat >sa0
3579 3577f02 from 3577gat >sa0
3580 3577f03 from 3577gat >sa0
3581 3581gat nor 1 2 >sa0
3460 3529
3582 3582gat nor 1 2 >sa0
3530 3457
3583 3583gat nor 2 2 >sa0 >sa1
3531 3532
3584 3583f01 from 3583gat >sa0
3585 3583f02 from 3583gat >sa0
3586 3586gat nor 3 2 >sa0 >sa1
3535 1097
3587 3586f01 from 3586gat >sa0
3588 3586f02 from 3586gat >sa0
3589 3586f03 from 3586gat >sa0
3590 3590gat nor 1 2 >sa0
3468 3537
3591 3591gat nor 1 2 >sa0
3538 1144
3592 3592gat nor 2 2 >sa0 >sa1
3357 3539
3593 3592f01 from 3592gat >sa0
3594 3592f02 from 3592gat >sa0
3595 3595gat nor 2 2 >sa0 >sa1
3540 3541
3596 3595f01 from 3595gat >sa0
3597 3595f02 from 3595gat >sa0
3598 3598gat nor 3 2 >sa0 >sa1
3546 3543
3599 3598f01 from 3598gat >sa0
3600 3598f02 from 3598gat >sa0
3601 3598f03 from 3598gat >sa0
3602 3602gat nor 1 2 >sa0
1289 3550
3603 3603gat nor 1 2 >sa0
3551 3478
3604 3604gat nor 3 2 >sa0 >sa1
3554 3482
3605 3604f01 from 3604gat >sa0
3606 3604f02 from 3604gat >sa0
3607 3604f03 from 3604gat >sa0
3608 3608gat nor 3 2 >sa0 >sa1
3557 3487
3609 3608f01 from 3608gat >sa0
3610 3608f02 from 3608gat >sa0
3611 3608f03 from 3608gat >sa0
3612 3612gat nor 3 2 >sa0 >sa1
3560 3492
3613 3612f01 from 3612gat >sa0
3614 3612f02 from 3612gat >sa0
3615 3612f03 from 3612gat >sa0
3616 3616gat nor 3 2 >sa0 >sa1
3563 3497
3617 3616f01 from 3616gat >sa0
3618 3616f02 from 3616gat >sa0
3619 3616f03 from 3616gat >sa0
3620 3620gat nor 3 2 >sa0 >sa1
3566 3502
3621 3620f01 from 3620gat >sa0
3622 3620f02 from 3620gat >sa0
3623 3620f03 from 3620gat >sa0
3624 3624gat nor 3 2 >sa0 >sa1
3569 3507
3625 3624f01 from 3624gat >sa0
3626 3624f02 from 3624gat >sa0
3627 3624f03 from 3624gat >sa0
3628 3628gat nor 3 2 >sa0 >sa1
3572 3512
3629 3628f01 from 3628gat >sa0
3630 3628f02 from 3628gat >sa0
3631 3628f03 from 3628gat >sa0
3632 3632gat nor 3 2 >sa0 >sa1
3575 3517
3633 3632f01 from 3632gat >sa0
3634 3632f02 from 3632gat >sa0
3635 3632f03 from 3632gat >sa0
3636 3636gat nor 1 2 >sa0
3526 3579
3637 3637gat nor 1 2 >sa0
3580 3523
3638 3638gat nor 2 2 >sa0 >sa1
3581 3582
3639 3638f01 from 3638gat >sa0
3640 3638f02 from 3638gat >sa0
3641 3641gat nor 3 2 >sa0 >sa1
3585 1049
3642 3641f01 from 3641gat >sa0
3643 3641f02 from 3641gat >sa0
3644 3641f03 from 3641gat >sa0
3645 3645gat nor 1 2 >sa0
3534 3587
3646 3646gat nor 1 2 >sa0
3588 1096
3647 3647gat nor 2 2 >sa0 >sa1
3405 3589
3648 3647f01 from 3647gat >sa0
3649 3647f02 from 3647gat >sa0
3650 3650gat nor 2 2 >sa0 >sa1
3590 3591
3651 3650f01 from 3650gat >sa0
3652 3650f02 from 3650gat >sa0
3653 3653gat nor 3 2 >sa0 >sa1
3596 3593
3654 3653f01 from 3653gat >sa0
3655 3653f02 from 3653gat >sa0
3656 3653f03 from 3653gat >sa0
3657 3657gat nor 1 2 >sa0
3547 3600
3658 3658gat nor 1 2 >sa0
3601 3544
3659 3659gat nor 2 2 >sa0 >sa1
3602 3603
3660 3659f01 from 3659gat >sa0
3661 3659f02 from 3659gat >sa0
3662 3662gat nor 1 2 >sa0
3555 3606
3663 3663gat nor 1 2 >sa0
3607 3483
3664 3664gat nor 1 2 >sa0
3558 3610
3665 3665gat nor 1 2 >sa0
3611 3488
3666 3666gat nor 1 2 >sa0
3561 3614
3667 3667gat nor 1 2 >sa0
3615 3493
3668 3668gat nor 1 2 >sa0
3564 3618
3669 3669gat nor 1 2 >sa0
3619 3498
3670 3670gat nor 1 2 >sa0
3567 3622
3671 3671gat nor 1 2 >sa0
3623 3503
3672 3672gat nor 1 2 >sa0
3570 3626
3673 3673gat nor 1 2 >sa0
3627 3508
3674 3674gat nor 1 2 >sa0
3573 3630
3675 3675gat nor 1 2 >sa0
3631 3513
3676 3676gat nor 1 2 >sa0
3576 3634
3677 3677gat nor 1 2 >sa0
3635 3518
3678 3678gat nor 2 2 >sa0 >sa1
3636 3637
3679 3678f01 from 3678gat >sa0
3680 3678f02 from 3678gat >sa0
3681 3681gat nor 3 2 >sa0 >sa1
3640 1001
3682 3681f01 from 3681gat >sa0
3683 3681f02 from 3681gat >sa0
3684 3681f03 from 3681gat >sa0
3685 3685gat nor 1 2 >sa0
3584 3642
3686 3686gat nor 1 2 >sa0
3643 1048
3687 3687gat nor 2 2 >sa0 >sa1
3462 3644
3688 3687f01 from 3687gat >sa0
3689 3687f02 from 3687gat >sa0
3690 3690gat nor 2 2 >sa0 >sa1
3645 3646
3691 3690f01 from 3690gat >sa0
3692 3690f02 from 3690gat >sa0
3693 3693gat nor 3 2 >sa0 >sa1
3651 3648
3694 3693f01 from 3693gat >sa0
3695 3693f02 from 3693gat >sa0
3696 3693f03 from 3693gat >sa0
3697 3697gat nor 1 2 >sa0
3597 3655
3698 3698gat nor 1 2 >sa0
3656 3594
3699 3699gat nor 2 2 >sa0 >sa1
3657 3658
3700 3699f01 from 3699gat >sa0
3701 3699f02 from 3699gat >sa0
3702 3702gat nor 3 2 >sa0 >sa1
3661 1244
3703 3702f01 from 3702gat >sa0
3704 3702f02 from 3702gat >sa0
3705 3702f03 from 3702gat >sa0
3706 3706gat nor 2 2 >sa0 >sa1
3662 3663
3707 3706f01 from 3706gat >sa0
3708 3706f02 from 3706gat >sa0
3709 3709gat nor 2 2 >sa0 >sa1
3664 3665
3710 3709f01 from 3709gat >sa0
3711 3709f02 from 3709gat >sa0
3712 3712gat nor 2 2 >sa0 >sa1
3666 3667
3713 3712f01 from 3712gat >sa0
3714 3712f02 from 3712gat >sa0
3715 3715gat nor 2 2 >sa0 >sa1
3668 3669
3716 3715f01 from 3715gat >sa0
3717 3715f02 from 3715gat >sa0
3718 3718gat nor 2 2 >sa0 >sa1
3670 3671
3719 3718f01 from 3718gat >sa0
3720 3718f02 from 3718gat >sa0
3721 3721gat nor 2 2 >sa0 >sa1
3672 3673
3722 3721f01 from 3721gat >sa0
3723 3721f02 from 3721gat >sa0
3724 3724gat nor 2 2 >sa0 >sa1
3674 3675
3725 3724f01 from 3724gat >sa0
3726 3724f02 from 3724gat >sa0
3727 3727gat nor 2 2 >sa0 >sa1
3676 3677
3728 3727f01 from 3727gat >sa0
3729 3727f02 from 3727gat >sa0
3730 3730gat nor 3 2 >sa0 >sa1
3680 953
3731 3730f01 from 3730gat >sa0
3732 3730f02 from 3730gat >sa0
3733 3730f03 from 3730gat >sa0
3734 3734gat nor 1 2 >sa0
3639 3682
3735 3735gat nor 1 2 >sa0
3683 1000
3736 3736gat nor 2 2 >sa0 >sa1
3528 3684
3737 3736f01 from 3736gat >sa0
3738 3736f02 from 3736gat >sa0
3739 3739gat nor 2 2 >sa0 >sa1
3685 3686
3740 3739f01 from 3739gat >sa0
3741 3739f02 from 3739gat >sa0
3742 3742gat nor 3 2 >sa0 >sa1
3691 3688
3743 3742f01 from 3742gat >sa0
3744 3742f02 from 3742gat >sa0
3745 3742f03 from 3742gat >sa0
3746 3746gat nor 1 2 >sa0
3652 3695
3747 3747gat nor 1 2 >sa0
3696 3649
3748 3748gat nor 2 2 >sa0 >sa1
3697 3698
3749 3748f01 from 3748gat >sa0
3750 3748f02 from 3748gat >sa0
3751 3751gat nor 3 2 >sa0 >sa1
3701 1196
3752 3751f01 from 3751gat >sa0
3753 3751f02 from 3751gat >sa0
3754 3751f03 from 3751gat >sa0
3755 3755gat nor 1 2 >sa0
3660 3703
3756 3756gat nor 1 2 >sa0
3704 1243
3757 3757gat nor 2 2 >sa0 >sa1
3549 3705
3758 3757f01 from 3757gat >sa0
3759 3757f02 from 3757gat >sa0
3760 3760gat nor 3 2 >sa0 >sa1
3708 569
3761 3760f01 from 3760gat >sa0
3762 3760f02 from 3760gat >sa0
3763 3760f03 from 3760gat >sa0
3764 3764gat nor 3 2 >sa0 >sa1
3711 617
3765 3764f01 from 3764gat >sa0
3766 3764f02 from 3764gat >sa0
3767 3764f03 from 3764gat >sa0
3768 3768gat nor 3 2 >sa0 >sa1
3714 665
3769 3768f01 from 3768gat >sa0
3770 3768f02 from 3768gat >sa0
3771 3768f03 from 3768gat >sa0
3772 3772gat nor 3 2 >sa0 >sa1
3717 713
3773 3772f01 from 3772gat >sa0
3774 3772f02 from 3772gat >sa0
3775 3772f03 from 3772gat >sa0
3776 3776gat nor 3 2 >sa0 >sa1
3720 761
3777 3776f01 from 3776gat >sa0
3778 3776f02 from 3776gat >sa0
3779 3776f03 from 3776gat >sa0
3780 3780gat nor 3 2 >sa0 >sa1
3723 809
3781 3780f01 from 3780gat >sa0
3782 3780f02 from 3780gat >sa0
3783 3780f03 from 3780gat >sa0
3784 3784gat nor 3 2 >sa0 >sa1
3726 857
3785 3784f01 from 3784gat >sa0
3786 3784f02 from 3784gat >sa0
3787 3784f03 from 3784gat >sa0
3788 3788gat nor 3 2 >sa0 >sa1
3729 905
3789 3788f01 from 3788gat >sa0
3790 3788f02 from 3788gat >sa0
3791 3788f03 from 3788gat >sa0
3792 3792gat nor 1 2 >sa0
3679 3731
3793 3793gat nor 1 2 >sa0
3732 952
3794 3794gat nor 2 2 >sa0 >sa1
3578 3733
3795 3794f01 from 3794gat >sa0
3796 3794f02 from 3794gat >sa0
3797 3797gat nor 2 2 >sa0 >sa1
3734 3735
3798 3797f01 from 3797gat >sa0
3799 3797f02 from 3797gat >sa0
3800 3800gat nor 3 2 >sa0 >sa1
3740 3737
3801 3800f01 from 3800gat >sa0
3802 3800f02 from 3800gat >sa0
3803 3800f03 from 3800gat >sa0
3804 3804gat nor 1 2 >sa0
3692 3744
3805 3805gat nor 1 2 >sa0
3745 3689
3806 3806gat nor 2 2 >sa0 >sa1
3746 3747
3807 3806f01 from 3806gat >sa0
3808 3806f02 from 3806gat >sa0
3809 3809gat nor 3 2 >sa0 >sa1
3750 1148
3810 3809f01 from 3809gat >sa0
3811 3809f02 from 3809gat >sa0
3812 3809f03 from 3809gat >sa0
3813 3813gat nor 1 2 >sa0
3700 3752
3814 3814gat nor 1 2 >sa0
3753 1195
3815 3815gat nor 2 2 >sa0 >sa1
3599 3754
3816 3815f01 from 3815gat >sa0
3817 3815f02 from 3815gat >sa0
3818 3818gat nor 2 2 >sa0 >sa1
3755 3756
3819 3818f01 from 3818gat >sa0
3820 3818f02 from 3818gat >sa0
3821 3821gat nor 3 2 >sa0 >sa1
1291 3758
3822 3821f01 from 3821gat >sa0
3823 3821f02 from 3821gat >sa0
3824 3821f03 from 3821gat >sa0
3825 3825gat nor 1 2 >sa0
3707 3761
3826 3826gat nor 1 2 >sa0
3762 568
3827 3827gat nor 2 2 >sa0 >sa1
3605 3763
3828 3827f01 from 3827gat >sa0
3829 3827f02 from 3827gat >sa0
3830 3830gat nor 1 2 >sa0
3710 3765
3831 3831gat nor 1 2 >sa0
3766 616
3832 3832gat nor 2 2 >sa0 >sa1
3609 3767
3833 3832f01 from 3832gat >sa0
3834 3832f02 from 3832gat >sa0
3835 3835gat nor 1 2 >sa0
3713 3769
3836 3836gat nor 1 2 >sa0
3770 664
3837 3837gat nor 2 2 >sa0 >sa1
3613 3771
3838 3837f01 from 3837gat >sa0
3839 3837f02 from 3837gat >sa0
3840 3840gat nor 1 2 >sa0
3716 3773
3841 3841gat nor 1 2 >sa0
3774 712
3842 3842gat nor 2 2 >sa0 >sa1
3617 3775
3843 3842f01 from 3842gat >sa0
3844 3842f02 from 3842gat >sa0
3845 3845gat nor 1 2 >sa0
3719 3777
3846 3846gat nor 1 2 >sa0
3778 760
3847 3847gat nor 2 2 >sa0 >sa1
3621 3779
3848 3847f01 from 3847gat >sa0
3849 3847f02 from 3847gat >sa0
3850 3850gat nor 1 2 >sa0
3722 3781
3851 3851gat nor 1 2 >sa0
3782 808
3852 3852gat nor 2 2 >sa0 >sa1
3625 3783
3853 3852f01 from 3852gat >sa0
3854 3852f02 from 3852gat >sa0
3855 3855gat nor 1 2 >sa0
3725 3785
3856 3856gat nor 1 2 >sa0
3786 856
3857 3857gat nor 2 2 >sa0 >sa1
3629 3787
3858 3857f01 from 3857gat >sa0
3859 3857f02 from 3857gat >sa0
3860 3860gat nor 1 2 >sa0
3728 3789
3861 3861gat nor 1 2 >sa0
3790 904
3862 3862gat nor 2 2 >sa0 >sa1
3633 3791
3863 3862f01 from 3862gat >sa0
3864 3862f02 from 3862gat >sa0
3865 3865gat nor 2 2 >sa0 >sa1
3792 3793
3866 3865f01 from 3865gat >sa0
3867 3865f02 from 3865gat >sa0
3868 3868gat nor 3 2 >sa0 >sa1
3798 3795
3869 3868f01 from 3868gat >sa0
3870 3868f02 from 3868gat >sa0
3871 3868f03 from 3868gat >sa0
3872 3872gat nor 1 2 >sa0
3741 3802
3873 3873gat nor 1 2 >sa0
3803 3738
3874 3874gat nor 2 2 >sa0 >sa1
3804 3805
3875 3874f01 from 3874gat >sa0
3876 3874f02 from 3874gat >sa0
3877 3877gat nor 3 2 >sa0 >sa1
3808 1100
3878 3877f01 from 3877gat >sa0
3879 3877f02 from 3877gat >sa0
3880 3877f03 from 3877gat >sa0
3881 3881gat nor 1 2 >sa0
3749 3810
3882 3882gat nor 1 2 >sa0
3811 1147
3883 3883gat nor 2 2 >sa0 >sa1
3654 3812
3884 3883f01 from 3883gat >sa0
3885 3883f02 from 3883gat >sa0
3886 3886gat nor 2 2 >sa0 >sa1
3813 3814
3887 3886f01 from 3886gat >sa0
3888 3886f02 from 3886gat >sa0
3889 3889gat nor 3 2 >sa0 >sa1
3819 3816
3890 3889f01 from 3889gat >sa0
3891 3889f02 from 3889gat >sa0
3892 3889f03 from 3889gat >sa0
3893 3893gat nor 1 2 >sa0
1292 3823
3894 3894gat nor 1 2 >sa0
3824 3759
3895 3895gat nor 0 2 >sa0 >sa1
3825 3826
3896 3896gat nor 2 2 >sa0 >sa1
3830 3831
3897 3896f01 from 3896gat >sa0
3898 3896f02 from 3896gat >sa0
3899 3899gat nor 2 2 >sa0 >sa1
3835 3836
3900 3899f01 from 3899gat >sa0
3901 3899f02 from 3899gat >sa0
3902 3902gat nor 2 2 >sa0 >sa1
3840 3841
3903 3902f01 from 3902gat >sa0
3904 3902f02 from 3902gat >sa0
3905 3905gat nor 2 2 >sa0 >sa1
3845 3846
3906 3905f01 from 3905gat >sa0
3907 3905f02 from 3905gat >sa0
3908 3908gat nor 2 2 >sa0 >sa1
3850 3851
3909 3908f01 from 3908gat >sa0
3910 3908f02 from 3908gat >sa0
3911 3911gat nor 2 2 >sa0 >sa1
3855 3856
3912 3911f01 from 3911gat >sa0
3913 3911f02 from 3911gat >sa0
3914 3914gat nor 2 2 >sa0 >sa1
3860 3861
3915 3914f01 from 3914gat >sa0
3916 3914f02 from 3914gat >sa0
3917 3917gat nor 3 2 >sa0 >sa1
3866 3863
3918 3917f01 from 3917gat >sa0
3919 3917f02 from 3917gat >sa0
3920 3917f03 from 3917gat >sa0
3921 3921gat nor 1 2 >sa0
3799 3870
3922 3922gat nor 1 2 >sa0
3871 3796
3923 3923gat nor 2 2 >sa0 >sa1
3872 3873
3924 3923f01 from 3923gat >sa0
3925 3923f02 from 3923gat >sa0
3926 3926gat nor 3 2 >sa0 >sa1
3876 1052
3927 3926f01 from 3926gat >sa0
3928 3926f02 from 3926gat >sa0
3929 3926f03 from 3926gat >sa0
3930 3930gat nor 1 2 >sa0
3807 3878
3931 3931gat nor 1 2 >sa0
3879 1099
3932 3932gat nor 2 2 >sa0 >sa1
3694 3880
3933 3932f01 from 3932gat >sa0
3934 3932f02 from 3932gat >sa0
3935 3935gat nor 2 2 >sa0 >sa1
3881 3882
3936 3935f01 from 3935gat >sa0
3937 3935f02 from 3935gat >sa0
3938 3938gat nor 3 2 >sa0 >sa1
3887 3884
3939 3938f01 from 3938gat >sa0
3940 3938f02 from 3938gat >sa0
3941 3938f03 from 3938gat >sa0
3942 3942gat nor 1 2 >sa0
3820 3891
3943 3943gat nor 1 2 >sa0
3892 3817
3944 3944gat nor 2 2 >sa0 >sa1
3893 3894
3945 3944f01 from 3944gat >sa0
3946 3944f02 from 3944gat >sa0
3947 3947gat nor 3 2 >sa0 >sa1
3897 3828
3948 3947f01 from 3947gat >sa0
3949 3947f02 from 3947gat >sa0
3950 3947f03 from 3947gat >sa0
3951 3951gat nor 3 2 >sa0 >sa1
3900 3833
3952 3951f01 from 3951gat >sa0
3953 3951f02 from 3951gat >sa0
3954 3951f03 from 3951gat >sa0
3955 3955gat nor 3 2 >sa0 >sa1
3903 3838
3956 3955f01 from 3955gat >sa0
3957 3955f02 from 3955gat >sa0
3958 3955f03 from 3955gat >sa0
3959 3959gat nor 3 2 >sa0 >sa1
3906 3843
3960 3959f01 from 3959gat >sa0
3961 3959f02 from 3959gat >sa0
3962 3959f03 from 3959gat >sa0
3963 3963gat nor 3 2 >sa0 >sa1
3909 3848
3964 3963f01 from 3963gat >sa0
3965 3963f02 from 3963gat >sa0
3966 3963f03 from 3963gat >sa0
3967 3967gat nor 3 2 >sa0 >sa1
3912 3853
3968 3967f01 from 3967gat >sa0
3969 3967f02 from 3967gat >sa0
3970 3967f03 from 3967gat >sa0
3971 3971gat nor 3 2 >sa0 >sa1
3915 3858
3972 3971f01 from 3971gat >sa0
3973 3971f02 from 3971gat >sa0
3974 3971f03 from 3971gat >sa0
3975 3975gat nor 1 2 >sa0
3867 3919
3976 3976gat nor 1 2 >sa0
3920 3864
3977 3977gat nor 2 2 >sa0 >sa1
3921 3922
3978 3977f01 from 3977gat >sa0
3979 3977f02 from 3977gat >sa0
3980 3980gat nor 3 2 >sa0 >sa1
3925 1004
3981 3980f01 from 3980gat >sa0
3982 3980f02 from 3980gat >sa0
3983 3980f03 from 3980gat >sa0
3984 3984gat nor 1 2 >sa0
3875 3927
3985 3985gat nor 1 2 >sa0
3928 1051
3986 3986gat nor 2 2 >sa0 >sa1
3743 3929
3987 3986f01 from 3986gat >sa0
3988 3986f02 from 3986gat >sa0
3989 3989gat nor 2 2 >sa0 >sa1
3930 3931
3990 3989f01 from 3989gat >sa0
3991 3989f02 from 3989gat >sa0
3992 3992gat nor 3 2 >sa0 >sa1
3936 3933
3993 3992f01 from 3992gat >sa0
3994 3992f02 from 3992gat >sa0
3995 3992f03 from 3992gat >sa0
3996 3996gat nor 1 2 >sa0
3888 3940
3997 3997gat nor 1 2 >sa0
3941 3885
3998 3998gat nor 2 2 >sa0 >sa1
3942 3943
3999 3998f01 from 3998gat >sa0
4000 3998f02 from 3998gat >sa0
4001 4001gat nor 3 2 >sa0 >sa1
3946 1247
4002 4001f01 from 4001gat >sa0
4003 4001f02 from 4001gat >sa0
4004 4001f03 from 4001gat >sa0
4005 4005gat nor 1 2 >sa0
3898 3949
4006 4006gat nor 1 2 >sa0
3950 3829
4007 4007gat nor 1 2 >sa0
3901 3953
4008 4008gat nor 1 2 >sa0
3954 3834
4009 4009gat nor 1 2 >sa0
3904 3957
4010 4010gat nor 1 2 >sa0
3958 3839
4011 4011gat nor 1 2 >sa0
3907 3961
4012 4012gat nor 1 2 >sa0
3962 3844
4013 4013gat nor 1 2 >sa0
3910 3965
4014 4014gat nor 1 2 >sa0
3966 3849
4015 4015gat nor 1 2 >sa0
3913 3969
4016 4016gat nor 1 2 >sa0
3970 3854
4017 4017gat nor 1 2 >sa0
3916 3973
4018 4018gat nor 1 2 >sa0
3974 3859
4019 4019gat nor 2 2 >sa0 >sa1
3975 3976
4020 4019f01 from 4019gat >sa0
4021 4019f02 from 4019gat >sa0
4022 4022gat nor 3 2 >sa0 >sa1
3979 956
4023 4022f01 from 4022gat >sa0
4024 4022f02 from 4022gat >sa0
4025 4022f03 from 4022gat >sa0
4026 4026gat nor 1 2 >sa0
3924 3981
4027 4027gat nor 1 2 >sa0
3982 1003
4028 4028gat nor 2 2 >sa0 >sa1
3801 3983
4029 4028f01 from 4028gat >sa0
4030 4028f02 from 4028gat >sa0
4031 4031gat nor 2 2 >sa0 >sa1
3984 3985
4032 4031f01 from 4031gat >sa0
4033 4031f02 from 4031gat >sa0
4034 4034gat nor 3 2 >sa0 >sa1
3990 3987
4035 4034f01 from 4034gat >sa0
4036 4034f02 from 4034gat >sa0
4037 4034f03 from 4034gat >sa0
4038 4038gat nor 1 2 >sa0
3937 3994
4039 4039gat nor 1 2 >sa0
3995 3934
4040 4040gat nor 2 2 >sa0 >sa1
3996 3997
4041 4040f01 from 4040gat >sa0
4042 4040f02 from 4040gat >sa0
4043 4043gat nor 3 2 >sa0 >sa1
4000 1199
4044 4043f01 from 4043gat >sa0
4045 4043f02 from 4043gat >sa0
4046 4043f03 from 4043gat >sa0
4047 4047gat nor 1 2 >sa0
3945 4002
4048 4048gat nor 1 2 >sa0
4003 1246
4049 4049gat nor 2 2 >sa0 >sa1
3822 4004
4050 4049f01 from 4049gat >sa0
4051 4049f02 from 4049gat >sa0
4052 4052gat nor 2 2 >sa0 >sa1
4005 4006
4053 4052f01 from 4052gat >sa0
4054 4052f02 from 4052gat >sa0
4055 4055gat nor 2 2 >sa0 >sa1
4007 4008
4056 4055f01 from 4055gat >sa0
4057 4055f02 from 4055gat >sa0
4058 4058gat nor 2 2 >sa0 >sa1
4009 4010
4059 4058f01 from 4058gat >sa0
4060 4058f02 from 4058gat >sa0
4061 4061gat nor 2 2 >sa0 >sa1
4011 4012
4062 4061f01 from 4061gat >sa0
4063 4061f02 from 4061gat >sa0
4064 4064gat nor 2 2 >sa0 >sa1
4013 4014
4065 4064f01 from 4064gat >sa0
4066 4064f02 from 4064gat >sa0
4067 4067gat nor 2 2 >sa0 >sa1
4015 4016
4068 4067f01 from 4067gat >sa0
4069 4067f02 from 4067gat >sa0
4070 4070gat nor 2 2 >sa0 >sa1
4017 4018
4071 4070f01 from 4070gat >sa0
4072 4070f02 from 4070gat >sa0
4073 4073gat nor 3 2 >sa0 >sa1
4021 908
4074 4073f01 from 4073gat >sa0
4075 4073f02 from 4073gat >sa0
4076 4073f03 from 4073gat >sa0
4077 4077gat nor 1 2 >sa0
3978 4023
4078 4078gat nor 1 2 >sa0
4024 955
4079 4079gat nor 2 2 >sa0 >sa1
3869 4025
4080 4079f01 from 4079gat >sa0
4081 4079f02 from 4079gat >sa0
4082 4082gat nor 2 2 >sa0 >sa1
4026 4027
4083 4082f01 from 4082gat >sa0
4084 4082f02 from 4082gat >sa0
4085 4085gat nor 3 2 >sa0 >sa1
4032 4029
4086 4085f01 from 4085gat >sa0
4087 4085f02 from 4085gat >sa0
4088 4085f03 from 4085gat >sa0
4089 4089gat nor 1 2 >sa0
3991 4036
4090 4090gat nor 1 2 >sa0
4037 3988
4091 4091gat nor 2 2 >sa0 >sa1
4038 4039
4092 4091f01 from 4091gat >sa0
4093 4091f02 from 4091gat >sa0
4094 4094gat nor 3 2 >sa0 >sa1
4042 1151
4095 4094f01 from 4094gat >sa0
4096 4094f02 from 4094gat >sa0
4097 4094f03 from 4094gat >sa0
4098 4098gat nor 1 2 >sa0
3999 4044
4099 4099gat nor 1 2 >sa0
4045 1198
4100 4100gat nor 2 2 >sa0 >sa1
3890 4046
4101 4100f01 from 4100gat >sa0
4102 4100f02 from 4100gat >sa0
4103 4103gat nor 2 2 >sa0 >sa1
4047 4048
4104 4103f01 from 4103gat >sa0
4105 4103f02 from 4103gat >sa0
4106 4106gat nor 3 2 >sa0 >sa1
1294 4050
4107 4106f01 from 4106gat >sa0
4108 4106f02 from 4106gat >sa0
4109 4106f03 from 4106gat >sa0
4110 4110gat nor 3 2 >sa0 >sa1
4054 572
4111 4110f01 from 4110gat >sa0
4112 4110f02 from 4110gat >sa0
4113 4110f03 from 4110gat >sa0
4114 4114gat nor 3 2 >sa0 >sa1
4057 620
4115 4114f01 from 4114gat >sa0
4116 4114f02 from 4114gat >sa0
4117 4114f03 from 4114gat >sa0
4118 4118gat nor 3 2 >sa0 >sa1
4060 668
4119 4118f01 from 4118gat >sa0
4120 4118f02 from 4118gat >sa0
4121 4118f03 from 4118gat >sa0
4122 4122gat nor 3 2 >sa0 >sa1
4063 716
4123 4122f01 from 4122gat >sa0
4124 4122f02 from 4122gat >sa0
4125 4122f03 from 4122gat >sa0
4126 4126gat nor 3 2 >sa0 >sa1
4066 764
4127 4126f01 from 4126gat >sa0
4128 4126f02 from 4126gat >sa0
4129 4126f03 from 4126gat >sa0
4130 4130gat nor 3 2 >sa0 >sa1
4069 812
4131 4130f01 from 4130gat >sa0
4132 4130f02 from 4130gat >sa0
4133 4130f03 from 4130gat >sa0
4134 4134gat nor 3 2 >sa0 >sa1
4072 860
4135 4134f01 from 4134gat >sa0
4136 4134f02 from 4134gat >sa0
4137 4134f03 from 4134gat >sa0
4138 4138gat nor 1 2 >sa0
4020 4074
4139 4139gat nor 1 2 >sa0
4075 907
4140 4140gat nor 2 2 >sa0 >sa1
3918 4076
4141 4140f01 from 4140gat >sa0
4142 4140f02 from 4140gat >sa0
4143 4143gat nor 2 2 >sa0 >sa1
4077 4078
4144 4143f01 from 4143gat >sa0
4145 4143f02 from 4143gat >sa0
4146 4146gat nor 3 2 >sa0 >sa1
4083 4080
4147 4146f01 from 4146gat >sa0
4148 4146f02 from 4146gat >sa0
4149 4146f03 from 4146gat >sa0
4150 4150gat nor 1 2 >sa0
4033 4087
4151 4151gat nor 1 2 >sa0
4088 4030
4152 4152gat nor 2 2 >sa0 >sa1
4089 4090
4153 4152f01 from 4152gat >sa0
4154 4152f02 from 4152gat >sa0
4155 4155gat nor 3 2 >sa0 >sa1
4093 1103
4156 4155f01 from 4155gat >sa0
4157 4155f02 from 4155gat >sa0
4158 4155f03 from 4155gat >sa0
4159 4159gat nor 1 2 >sa0
4041 4095
4160 4160gat nor 1 2 >sa0
4096 1150
4161 4161gat nor 2 2 >sa0 >sa1
3939 4097
4162 4161f01 from 4161gat >sa0
4163 4161f02 from 4161gat >sa0
4164 4164gat nor 2 2 >sa0 >sa1
4098 4099
4165 4164f01 from 4164gat >sa0
4166 4164f02 from 4164gat >sa0
4167 4167gat nor 3 2 >sa0 >sa1
4104 4101
4168 4167f01 from 4167gat >sa0
4169 4167f02 from 4167gat >sa0
4170 4167f03 from 4167gat >sa0
4171 4171gat nor 1 2 >sa0
1295 4108
4172 4172gat nor 1 2 >sa0
4109 4051
4173 4173gat nor 1 2 >sa0
4053 4111
4174 4174gat nor 1 2 >sa0
4112 571
4175 4175gat nor 2 2 >sa0 >sa1
3948 4113
4176 4175f01 from 4175gat >sa0
4177 4175f02 from 4175gat >sa0
4178 4178gat nor 1 2 >sa0
4056 4115
4179 4179gat nor 1 2 >sa0
4116 619
4180 4180gat nor 2 2 >sa0 >sa1
3952 4117
4181 4180f01 from 4180gat >sa0
4182 4180f02 from 4180gat >sa0
4183 4183gat nor 1 2 >sa0
4059 4119
4184 4184gat nor 1 2 >sa0
4120 667
4185 4185gat nor 2 2 >sa0 >sa1
3956 4121
4186 4185f01 from 4185gat >sa0
4187 4185f02 from 4185gat >sa0
4188 4188gat nor 1 2 >sa0
4062 4123
4189 4189gat nor 1 2 >sa0
4124 715
4190 4190gat nor 2 2 >sa0 >sa1
3960 4125
4191 4190f01 from 4190gat >sa0
4192 4190f02 from 4190gat >sa0
4193 4193gat nor 1 2 >sa0
4065 4127
4194 4194gat nor 1 2 >sa0
4128 763
4195 4195gat nor 2 2 >sa0 >sa1
3964 4129
4196 4195f01 from 4195gat >sa0
4197 4195f02 from 4195gat >sa0
4198 4198gat nor 1 2 >sa0
4068 4131
4199 4199gat nor 1 2 >sa0
4132 811
4200 4200gat nor 2 2 >sa0 >sa1
3968 4133
4201 4200f01 from 4200gat >sa0
4202 4200f02 from 4200gat >sa0
4203 4203gat nor 1 2 >sa0
4071 4135
4204 4204gat nor 1 2 >sa0
4136 859
4205 4205gat nor 2 2 >sa0 >sa1
3972 4137
4206 4205f01 from 4205gat >sa0
4207 4205f02 from 4205gat >sa0
4208 4208gat nor 2 2 >sa0 >sa1
4138 4139
4209 4208f01 from 4208gat >sa0
4210 4208f02 from 4208gat >sa0
4211 4211gat nor 3 2 >sa0 >sa1
4144 4141
4212 4211f01 from 4211gat >sa0
4213 4211f02 from 4211gat >sa0
4214 4211f03 from 4211gat >sa0
4215 4215gat nor 1 2 >sa0
4084 4148
4216 4216gat nor 1 2 >sa0
4149 4081
4217 4217gat nor 2 2 >sa0 >sa1
4150 4151
4218 4217f01 from 4217gat >sa0
4219 4217f02 from 4217gat >sa0
4220 4220gat nor 3 2 >sa0 >sa1
4154 1055
4221 4220f01 from 4220gat >sa0
4222 4220f02 from 4220gat >sa0
4223 4220f03 from 4220gat >sa0
4224 4224gat nor 1 2 >sa0
4092 4156
4225 4225gat nor 1 2 >sa0
4157 1102
4226 4226gat nor 2 2 >sa0 >sa1
3993 4158
4227 4226f01 from 4226gat >sa0
4228 4226f02 from 4226gat >sa0
4229 4229gat nor 2 2 >sa0 >sa1
4159 4160
4230 4229f01 from 4229gat >sa0
4231 4229f02 from 4229gat >sa0
4232 4232gat nor 3 2 >sa0 >sa1
4165 4162
4233 4232f01 from 4232gat >sa0
4234 4232f02 from 4232gat >sa0
4235 4232f03 from 4232gat >sa0
4236 4236gat nor 1 2 >sa0
4105 4169
4237 4237gat nor 1 2 >sa0
4170 4102
4238 4238gat nor 2 2 >sa0 >sa1
4171 4172
4239 4238f01 from 4238gat >sa0
4240 4238f02 from 4238gat >sa0
4241 4241gat nor 0 2 >sa0 >sa1
4173 4174
4242 4242gat nor 2 2 >sa0 >sa1
4178 4179
4243 4242f01 from 4242gat >sa0
4244 4242f02 from 4242gat >sa0
4245 4245gat nor 2 2 >sa0 >sa1
4183 4184
4246 4245f01 from 4245gat >sa0
4247 4245f02 from 4245gat >sa0
4248 4248gat nor 2 2 >sa0 >sa1
4188 4189
4249 4248f01 from 4248gat >sa0
4250 4248f02 from 4248gat >sa0
4251 4251gat nor 2 2 >sa0 >sa1
4193 4194
4252 4251f01 from 4251gat >sa0
4253 4251f02 from 4251gat >sa0
4254 4254gat nor 2 2 >sa0 >sa1
4198 4199
4255 4254f01 from 4254gat >sa0
4256 4254f02 from 4254gat >sa0
4257 4257gat nor 2 2 >sa0 >sa1
4203 4204
4258 4257f01 from 4257gat >sa0
4259 4257f02 from 4257gat >sa0
4260 4260gat nor 3 2 >sa0 >sa1
4209 4206
4261 4260f01 from 4260gat >sa0
4262 4260f02 from 4260gat >sa0
4263 4260f03 from 4260gat >sa0
4264 4264gat nor 1 2 >sa0
4145 4213
4265 4265gat nor 1 2 >sa0
4214 4142
4266 4266gat nor 2 2 >sa0 >sa1
4215 4216
4267 4266f01 from 4266gat >sa0
4268 4266f02 from 4266gat >sa0
4269 4269gat nor 3 2 >sa0 >sa1
4219 1007
4270 4269f01 from 4269gat >sa0
4271 4269f02 from 4269gat >sa0
4272 4269f03 from 4269gat >sa0
4273 4273gat nor 1 2 >sa0
4153 4221
4274 4274gat nor 1 2 >sa0
4222 1054
4275 4275gat nor 2 2 >sa0 >sa1
4035 4223
4276 4275f01 from 4275gat >sa0
4277 4275f02 from 4275gat >sa0
4278 4278gat nor 2 2 >sa0 >sa1
4224 4225
4279 4278f01 from 4278gat >sa0
4280 4278f02 from 4278gat >sa0
4281 4281gat nor 3 2 >sa0 >sa1
4230 4227
4282 4281f01 from 4281gat >sa0
4283 4281f02 from 4281gat >sa0
4284 4281f03 from 4281gat >sa0
4285 4285gat nor 1 2 >sa0
4166 4234
4286 4286gat nor 1 2 >sa0
4235 4163
4287 4287gat nor 2 2 >sa0 >sa1
4236 4237
4288 4287f01 from 4287gat >sa0
4289 4287f02 from 4287gat >sa0
4290 4290gat nor 3 2 >sa0 >sa1
4240 1250
4291 4290f01 from 4290gat >sa0
4292 4290f02 from 4290gat >sa0
4293 4290f03 from 4290gat >sa0
4294 4294gat nor 3 2 >sa0 >sa1
4243 4176
4295 4294f01 from 4294gat >sa0
4296 4294f02 from 4294gat >sa0
4297 4294f03 from 4294gat >sa0
4298 4298gat nor 3 2 >sa0 >sa1
4246 4181
4299 4298f01 from 4298gat >sa0
4300 4298f02 from 4298gat >sa0
4301 4298f03 from 4298gat >sa0
4302 4302gat nor 3 2 >sa0 >sa1
4249 4186
4303 4302f01 from 4302gat >sa0
4304 4302f02 from 4302gat >sa0
4305 4302f03 from 4302gat >sa0
4306 4306gat nor 3 2 >sa0 >sa1
4252 4191
4307 4306f01 from 4306gat >sa0
4308 4306f02 from 4306gat >sa0
4309 4306f03 from 4306gat >sa0
4310 4310gat nor 3 2 >sa0 >sa1
4255 4196
4311 4310f01 from 4310gat >sa0
4312 4310f02 from 4310gat >sa0
4313 4310f03 from 4310gat >sa0
4314 4314gat nor 3 2 >sa0 >sa1
4258 4201
4315 4314f01 from 4314gat >sa0
4316 4314f02 from 4314gat >sa0
4317 4314f03 from 4314gat >sa0
4318 4318gat nor 1 2 >sa0
4210 4262
4319 4319gat nor 1 2 >sa0
4263 4207
4320 4320gat nor 2 2 >sa0 >sa1
4264 4265
4321 4320f01 from 4320gat >sa0
4322 4320f02 from 4320gat >sa0
4323 4323gat nor 3 2 >sa0 >sa1
4268 959
4324 4323f01 from 4323gat >sa0
4325 4323f02 from 4323gat >sa0
4326 4323f03 from 4323gat >sa0
4327 4327gat nor 1 2 >sa0
4218 4270
4328 4328gat nor 1 2 >sa0
4271 1006
4329 4329gat nor 2 2 >sa0 >sa1
4086 4272
4330 4329f01 from 4329gat >sa0
4331 4329f02 from 4329gat >sa0
4332 4332gat nor 2 2 >sa0 >sa1
4273 4274
4333 4332f01 from 4332gat >sa0
4334 4332f02 from 4332gat >sa0
4335 4335gat nor 3 2 >sa0 >sa1
4279 4276
4336 4335f01 from 4335gat >sa0
4337 4335f02 from 4335gat >sa0
4338 4335f03 from 4335gat >sa0
4339 4339gat nor 1 2 >sa0
4231 4283
4340 4340gat nor 1 2 >sa0
4284 4228
4341 4341gat nor 2 2 >sa0 >sa1
4285 4286
4342 4341f01 from 4341gat >sa0
4343 4341f02 from 4341gat >sa0
4344 4344gat nor 3 2 >sa0 >sa1
4289 1202
4345 4344f01 from 4344gat >sa0
4346 4344f02 from 4344gat >sa0
4347 4344f03 from 4344gat >sa0
4348 4348gat nor 1 2 >sa0
4239 4291
4349 4349gat nor 1 2 >sa0
4292 1249
4350 4350gat nor 2 2 >sa0 >sa1
4107 4293
4351 4350f01 from 4350gat >sa0
4352 4350f02 from 4350gat >sa0
4353 4353gat nor 1 2 >sa0
4244 4296
4354 4354gat nor 1 2 >sa0
4297 4177
4355 4355gat nor 1 2 >sa0
4247 4300
4356 4356gat nor 1 2 >sa0
4301 4182
4357 4357gat nor 1 2 >sa0
4250 4304
4358 4358gat nor 1 2 >sa0
4305 4187
4359 4359gat nor 1 2 >sa0
4253 4308
4360 4360gat nor 1 2 >sa0
4309 4192
4361 4361gat nor 1 2 >sa0
4256 4312
4362 4362gat nor 1 2 >sa0
4313 4197
4363 4363gat nor 1 2 >sa0
4259 4316
4364 4364gat nor 1 2 >sa0
4317 4202
4365 4365gat nor 2 2 >sa0 >sa1
4318 4319
4366 4365f01 from 4365gat >sa0
4367 4365f02 from 4365gat >sa0
4368 4368gat nor 3 2 >sa0 >sa1
4322 911
4369 4368f01 from 4368gat >sa0
4370 4368f02 from 4368gat >sa0
4371 4368f03 from 4368gat >sa0
4372 4372gat nor 1 2 >sa0
4267 4324
4373 4373gat nor 1 2 >sa0
4325 958
4374 4374gat nor 2 2 >sa0 >sa1
4147 4326
4375 4374f01 from 4374gat >sa0
4376 4374f02 from 4374gat >sa0
4377 4377gat nor 2 2 >sa0 >sa1
4327 4328
4378 4377f01 from 4377gat >sa0
4379 4377f02 from 4377gat >sa0
4380 4380gat nor 3 2 >sa0 >sa1
4333 4330
4381 4380f01 from 4380gat >sa0
4382 4380f02 from 4380gat >sa0
4383 4380f03 from 4380gat >sa0
4384 4384gat nor 1 2 >sa0
4280 4337
4385 4385gat nor 1 2 >sa0
4338 4277
4386 4386gat nor 2 2 >sa0 >sa1
4339 4340
4387 4386f01 from 4386gat >sa0
4388 4386f02 from 4386gat >sa0
4389 4389gat nor 3 2 >sa0 >sa1
4343 1154
4390 4389f01 from 4389gat >sa0
4391 4389f02 from 4389gat >sa0
4392 4389f03 from 4389gat >sa0
4393 4393gat nor 1 2 >sa0
4288 4345
4394 4394gat nor 1 2 >sa0
4346 1201
4395 4395gat nor 2 2 >sa0 >sa1
4168 4347
4396 4395f01 from 4395gat >sa0
4397 4395f02 from 4395gat >sa0
4398 4398gat nor 2 2 >sa0 >sa1
4348 4349
4399 4398f01 from 4398gat >sa0
4400 4398f02 from 4398gat >sa0
4401 4401gat nor 3 2 >sa0 >sa1
1297 4351
4402 4401f01 from 4401gat >sa0
4403 4401f02 from 4401gat >sa0
4404 4401f03 from 4401gat >sa0
4405 4405gat nor 2 2 >sa0 >sa1
4353 4354
4406 4405f01 from 4405gat >sa0
4407 4405f02 from 4405gat >sa0
4408 4408gat nor 2 2 >sa0 >sa1
4355 4356
4409 4408f01 from 4408gat >sa0
4410 4408f02 from 4408gat >sa0
4411 4411gat nor 2 2 >sa0 >sa1
4357 4358
4412 4411f01 from 4411gat >sa0
4413 4411f02 from 4411gat >sa0
4414 4414gat nor 2 2 >sa0 >sa1
4359 4360
4415 4414f01 from 4414gat >sa0
4416 4414f02 from 4414gat >sa0
4417 4417gat nor 2 2 >sa0 >sa1
4361 4362
4418 4417f01 from 4417gat >sa0
4419 4417f02 from 4417gat >sa0
4420 4420gat nor 2 2 >sa0 >sa1
4363 4364
4421 4420f01 from 4420gat >sa0
4422 4420f02 from 4420gat >sa0
4423 4423gat nor 3 2 >sa0 >sa1
4367 863
4424 4423f01 from 4423gat >sa0
4425 4423f02 from 4423gat >sa0
4426 4423f03 from 4423gat >sa0
4427 4427gat nor 1 2 >sa0
4321 4369
4428 4428gat nor 1 2 >sa0
4370 910
4429 4429gat nor 2 2 >sa0 >sa1
4212 4371
4430 4429f01 from 4429gat >sa0
4431 4429f02 from 4429gat >sa0
4432 4432gat nor 2 2 >sa0 >sa1
4372 4373
4433 4432f01 from 4432gat >sa0
4434 4432f02 from 4432gat >sa0
4435 4435gat nor 3 2 >sa0 >sa1
4378 4375
4436 4435f01 from 4435gat >sa0
4437 4435f02 from 4435gat >sa0
4438 4435f03 from 4435gat >sa0
4439 4439gat nor 1 2 >sa0
4334 4382
4440 4440gat nor 1 2 >sa0
4383 4331
4441 4441gat nor 2 2 >sa0 >sa1
4384 4385
4442 4441f01 from 4441gat >sa0
4443 4441f02 from 4441gat >sa0
4444 4444gat nor 3 2 >sa0 >sa1
4388 1106
4445 4444f01 from 4444gat >sa0
4446 4444f02 from 4444gat >sa0
4447 4444f03 from 4444gat >sa0
4448 4448gat nor 1 2 >sa0
4342 4390
4449 4449gat nor 1 2 >sa0
4391 1153
4450 4450gat nor 2 2 >sa0 >sa1
4233 4392
4451 4450f01 from 4450gat >sa0
4452 4450f02 from 4450gat >sa0
4453 4453gat nor 2 2 >sa0 >sa1
4393 4394
4454 4453f01 from 4453gat >sa0
4455 4453f02 from 4453gat >sa0
4456 4456gat nor 3 2 >sa0 >sa1
4399 4396
4457 4456f01 from 4456gat >sa0
4458 4456f02 from 4456gat >sa0
4459 4456f03 from 4456gat >sa0
4460 4460gat nor 1 2 >sa0
1298 4403
4461 4461gat nor 1 2 >sa0
4404 4352
4462 4462gat nor 3 2 >sa0 >sa1
4407 575
4463 4462f01 from 4462gat >sa0
4464 4462f02 from 4462gat >sa0
4465 4462f03 from 4462gat >sa0
4466 4466gat nor 3 2 >sa0 >sa1
4410 623
4467 4466f01 from 4466gat >sa0
4468 4466f02 from 4466gat >sa0
4469 4466f03 from 4466gat >sa0
4470 4470gat nor 3 2 >sa0 >sa1
4413 671
4471 4470f01 from 4470gat >sa0
4472 4470f02 from 4470gat >sa0
4473 4470f03 from 4470gat >sa0
4474 4474gat nor 3 2 >sa0 >sa1
4416 719
4475 4474f01 from 4474gat >sa0
4476 4474f02 from 4474gat >sa0
4477 4474f03 from 4474gat >sa0
4478 4478gat nor 3 2 >sa0 >sa1
4419 767
4479 4478f01 from 4478gat >sa0
4480 4478f02 from 4478gat >sa0
4481 4478f03 from 4478gat >sa0
4482 4482gat nor 3 2 >sa0 >sa1
4422 815
4483 4482f01 from 4482gat >sa0
4484 4482f02 from 4482gat >sa0
4485 4482f03 from 4482gat >sa0
4486 4486gat nor 1 2 >sa0
4366 4424
4487 4487gat nor 1 2 >sa0
4425 862
4488 4488gat nor 2 2 >sa0 >sa1
4261 4426
4489 4488f01 from 4488gat >sa0
4490 4488f02 from 4488gat >sa0
4491 4491gat nor 2 2 >sa0 >sa1
4427 4428
4492 4491f01 from 4491gat >sa0
4493 4491f02 from 4491gat >sa0
4494 4494gat nor 3 2 >sa0 >sa1
4433 4430
4495 4494f01 from 4494gat >sa0
4496 4494f02 from 4494gat >sa0
4497 4494f03 from 4494gat >sa0
4498 4498gat nor 1 2 >sa0
4379 4437
4499 4499gat nor 1 2 >sa0
4438 4376
4500 4500gat nor 2 2 >sa0 >sa1
4439 4440
4501 4500f01 from 4500gat >sa0
4502 4500f02 from 4500gat >sa0
4503 4503gat nor 3 2 >sa0 >sa1
4443 1058
4504 4503f01 from 4503gat >sa0
4505 4503f02 from 4503gat >sa0
4506 4503f03 from 4503gat >sa0
4507 4507gat nor 1 2 >sa0
4387 4445
4508 4508gat nor 1 2 >sa0
4446 1105
4509 4509gat nor 2 2 >sa0 >sa1
4282 4447
4510 4509f01 from 4509gat >sa0
4511 4509f02 from 4509gat >sa0
4512 4512gat nor 2 2 >sa0 >sa1
4448 4449
4513 4512f01 from 4512gat >sa0
4514 4512f02 from 4512gat >sa0
4515 4515gat nor 3 2 >sa0 >sa1
4454 4451
4516 4515f01 from 4515gat >sa0
4517 4515f02 from 4515gat >sa0
4518 4515f03 from 4515gat >sa0
4519 4519gat nor 1 2 >sa0
4400 4458
4520 4520gat nor 1 2 >sa0
4459 4397
4521 4521gat nor 2 2 >sa0 >sa1
4460 4461
4522 4521f01 from 4521gat >sa0
4523 4521f02 from 4521gat >sa0
4524 4524gat nor 1 2 >sa0
4406 4463
4525 4525gat nor 1 2 >sa0
4464 574
4526 4526gat nor 2 2 >sa0 >sa1
4295 4465
4527 4526f01 from 4526gat >sa0
4528 4526f02 from 4526gat >sa0
4529 4529gat nor 1 2 >sa0
4409 4467
4530 4530gat nor 1 2 >sa0
4468 622
4531 4531gat nor 2 2 >sa0 >sa1
4299 4469
4532 4531f01 from 4531gat >sa0
4533 4531f02 from 4531gat >sa0
4534 4534gat nor 1 2 >sa0
4412 4471
4535 4535gat nor 1 2 >sa0
4472 670
4536 4536gat nor 2 2 >sa0 >sa1
4303 4473
4537 4536f01 from 4536gat >sa0
4538 4536f02 from 4536gat >sa0
4539 4539gat nor 1 2 >sa0
4415 4475
4540 4540gat nor 1 2 >sa0
4476 718
4541 4541gat nor 2 2 >sa0 >sa1
4307 4477
4542 4541f01 from 4541gat >sa0
4543 4541f02 from 4541gat >sa0
4544 4544gat nor 1 2 >sa0
4418 4479
4545 4545gat nor 1 2 >sa0
4480 766
4546 4546gat nor 2 2 >sa0 >sa1
4311 4481
4547 4546f01 from 4546gat >sa0
4548 4546f02 from 4546gat >sa0
4549 4549gat nor 1 2 >sa0
4421 4483
4550 4550gat nor 1 2 >sa0
4484 814
4551 4551gat nor 2 2 >sa0 >sa1
4315 4485
4552 4551f01 from 4551gat >sa0
4553 4551f02 from 4551gat >sa0
4554 4554gat nor 2 2 >sa0 >sa1
4486 4487
4555 4554f01 from 4554gat >sa0
4556 4554f02 from 4554gat >sa0
4557 4557gat nor 3 2 >sa0 >sa1
4492 4489
4558 4557f01 from 4557gat >sa0
4559 4557f02 from 4557gat >sa0
4560 4557f03 from 4557gat >sa0
4561 4561gat nor 1 2 >sa0
4434 4496
4562 4562gat nor 1 2 >sa0
4497 4431
4563 4563gat nor 2 2 >sa0 >sa1
4498 4499
4564 4563f01 from 4563gat >sa0
4565 4563f02 from 4563gat >sa0
4566 4566gat nor 3 2 >sa0 >sa1
4502 1010
4567 4566f01 from 4566gat >sa0
4568 4566f02 from 4566gat >sa0
4569 4566f03 from 4566gat >sa0
4570 4570gat nor 1 2 >sa0
4442 4504
4571 4571gat nor 1 2 >sa0
4505 1057
4572 4572gat nor 2 2 >sa0 >sa1
4336 4506
4573 4572f01 from 4572gat >sa0
4574 4572f02 from 4572gat >sa0
4575 4575gat nor 2 2 >sa0 >sa1
4507 4508
4576 4575f01 from 4575gat >sa0
4577 4575f02 from 4575gat >sa0
4578 4578gat nor 3 2 >sa0 >sa1
4513 4510
4579 4578f01 from 4578gat >sa0
4580 4578f02 from 4578gat >sa0
4581 4578f03 from 4578gat >sa0
4582 4582gat nor 1 2 >sa0
4455 4517
4583 4583gat nor 1 2 >sa0
4518 4452
4584 4584gat nor 2 2 >sa0 >sa1
4519 4520
4585 4584f01 from 4584gat >sa0
4586 4584f02 from 4584gat >sa0
4587 4587gat nor 3 2 >sa0 >sa1
4523 1253
4588 4587f01 from 4587gat >sa0
4589 4587f02 from 4587gat >sa0
4590 4587f03 from 4587gat >sa0
4591 4591gat nor 0 2 >sa0 >sa1
4524 4525
4592 4592gat nor 2 2 >sa0 >sa1
4529 4530
4593 4592f01 from 4592gat >sa0
4594 4592f02 from 4592gat >sa0
4595 4595gat nor 2 2 >sa0 >sa1
4534 4535
4596 4595f01 from 4595gat >sa0
4597 4595f02 from 4595gat >sa0
4598 4598gat nor 2 2 >sa0 >sa1
4539 4540
4599 4598f01 from 4598gat >sa0
4600 4598f02 from 4598gat >sa0
4601 4601gat nor 2 2 >sa0 >sa1
4544 4545
4602 4601f01 from 4601gat >sa0
4603 4601f02 from 4601gat >sa0
4604 4604gat nor 2 2 >sa0 >sa1
4549 4550
4605 4604f01 from 4604gat >sa0
4606 4604f02 from 4604gat >sa0
4607 4607gat nor 3 2 >sa0 >sa1
4555 4552
4608 4607f01 from 4607gat >sa0
4609 4607f02 from 4607gat >sa0
4610 4607f03 from 4607gat >sa0
4611 4611gat nor 1 2 >sa0
4493 4559
4612 4612gat nor 1 2 >sa0
4560 4490
4613 4613gat nor 2 2 >sa0 >sa1
4561 4562
4614 4613f01 from 4613gat >sa0
4615 4613f02 from 4613gat >sa0
4616 4616gat nor 3 2 >sa0 >sa1
4565 962
4617 4616f01 from 4616gat >sa0
4618 4616f02 from 4616gat >sa0
4619 4616f03 from 4616gat >sa0
4620 4620gat nor 1 2 >sa0
4501 4567
4621 4621gat nor 1 2 >sa0
4568 1009
4622 4622gat nor 2 2 >sa0 >sa1
4381 4569
4623 4622f01 from 4622gat >sa0
4624 4622f02 from 4622gat >sa0
4625 4625gat nor 2 2 >sa0 >sa1
4570 4571
4626 4625f01 from 4625gat >sa0
4627 4625f02 from 4625gat >sa0
4628 4628gat nor 3 2 >sa0 >sa1
4576 4573
4629 4628f01 from 4628gat >sa0
4630 4628f02 from 4628gat >sa0
4631 4628f03 from 4628gat >sa0
4632 4632gat nor 1 2 >sa0
4514 4580
4633 4633gat nor 1 2 >sa0
4581 4511
4634 4634gat nor 2 2 >sa0 >sa1
4582 4583
4635 4634f01 from 4634gat >sa0
4636 4634f02 from 4634gat >sa0
4637 4637gat nor 3 2 >sa0 >sa1
4586 1205
4638 4637f01 from 4637gat >sa0
4639 4637f02 from 4637gat >sa0
4640 4637f03 from 4637gat >sa0
4641 4641gat nor 1 2 >sa0
4522 4588
4642 4642gat nor 1 2 >sa0
4589 1252
4643 4643gat nor 2 2 >sa0 >sa1
4402 4590
4644 4643f01 from 4643gat >sa0
4645 4643f02 from 4643gat >sa0
4646 4646gat nor 3 2 >sa0 >sa1
4593 4527
4647 4646f01 from 4646gat >sa0
4648 4646f02 from 4646gat >sa0
4649 4646f03 from 4646gat >sa0
4650 4650gat nor 3 2 >sa0 >sa1
4596 4532
4651 4650f01 from 4650gat >sa0
4652 4650f02 from 4650gat >sa0
4653 4650f03 from 4650gat >sa0
4654 4654gat nor 3 2 >sa0 >sa1
4599 4537
4655 4654f01 from 4654gat >sa0
4656 4654f02 from 4654gat >sa0
4657 4654f03 from 4654gat >sa0
4658 4658gat nor 3 2 >sa0 >sa1
4602 4542
4659 4658f01 from 4658gat >sa0
4660 4658f02 from 4658gat >sa0
4661 4658f03 from 4658gat >sa0
4662 4662gat nor 3 2 >sa0 >sa1
4605 4547
4663 4662f01 from 4662gat >sa0
4664 4662f02 from 4662gat >sa0
4665 4662f03 from 4662gat >sa0
4666 4666gat nor 1 2 >sa0
4556 4609
4667 4667gat nor 1 2 >sa0
4610 4553
4668 4668gat nor 2 2 >sa0 >sa1
4611 4612
4669 4668f01 from 4668gat >sa0
4670 4668f02 from 4668gat >sa0
4671 4671gat nor 3 2 >sa0 >sa1
4615 914
4672 4671f01 from 4671gat >sa0
4673 4671f02 from 4671gat >sa0
4674 4671f03 from 4671gat >sa0
4675 4675gat nor 1 2 >sa0
4564 4617
4676 4676gat nor 1 2 >sa0
4618 961
4677 4677gat nor 2 2 >sa0 >sa1
4436 4619
4678 4677f01 from 4677gat >sa0
4679 4677f02 from 4677gat >sa0
4680 4680gat nor 2 2 >sa0 >sa1
4620 4621
4681 4680f01 from 4680gat >sa0
4682 4680f02 from 4680gat >sa0
4683 4683gat nor 3 2 >sa0 >sa1
4626 4623
4684 4683f01 from 4683gat >sa0
4685 4683f02 from 4683gat >sa0
4686 4683f03 from 4683gat >sa0
4687 4687gat nor 1 2 >sa0
4577 4630
4688 4688gat nor 1 2 >sa0
4631 4574
4689 4689gat nor 2 2 >sa0 >sa1
4632 4633
4690 4689f01 from 4689gat >sa0
4691 4689f02 from 4689gat >sa0
4692 4692gat nor 3 2 >sa0 >sa1
4636 1157
4693 4692f01 from 4692gat >sa0
4694 4692f02 from 4692gat >sa0
4695 4692f03 from 4692gat >sa0
4696 4696gat nor 1 2 >sa0
4585 4638
4697 4697gat nor 1 2 >sa0
4639 1204
4698 4698gat nor 2 2 >sa0 >sa1
4457 4640
4699 4698f01 from 4698gat >sa0
4700 4698f02 from 4698gat >sa0
4701 4701gat nor 2 2 >sa0 >sa1
4641 4642
4702 4701f01 from 4701gat >sa0
4703 4701f02 from 4701gat >sa0
4704 4704gat nor 3 2 >sa0 >sa1
1300 4644
4705 4704f01 from 4704gat >sa0
4706 4704f02 from 4704gat >sa0
4707 4704f03 from 4704gat >sa0
4708 4708gat nor 1 2 >sa0
4594 4648
4709 4709gat nor 1 2 >sa0
4649 4528
4710 4710gat nor 1 2 >sa0
4597 4652
4711 4711gat nor 1 2 >sa0
4653 4533
4712 4712gat nor 1 2 >sa0
4600 4656
4713 4713gat nor 1 2 >sa0
4657 4538
4714 4714gat nor 1 2 >sa0
4603 4660
4715 4715gat nor 1 2 >sa0
4661 4543
4716 4716gat nor 1 2 >sa0
4606 4664
4717 4717gat nor 1 2 >sa0
4665 4548
4718 4718gat nor 2 2 >sa0 >sa1
4666 4667
4719 4718f01 from 4718gat >sa0
4720 4718f02 from 4718gat >sa0
4721 4721gat nor 3 2 >sa0 >sa1
4670 866
4722 4721f01 from 4721gat >sa0
4723 4721f02 from 4721gat >sa0
4724 4721f03 from 4721gat >sa0
4725 4725gat nor 1 2 >sa0
4614 4672
4726 4726gat nor 1 2 >sa0
4673 913
4727 4727gat nor 2 2 >sa0 >sa1
4495 4674
4728 4727f01 from 4727gat >sa0
4729 4727f02 from 4727gat >sa0
4730 4730gat nor 2 2 >sa0 >sa1
4675 4676
4731 4730f01 from 4730gat >sa0
4732 4730f02 from 4730gat >sa0
4733 4733gat nor 3 2 >sa0 >sa1
4681 4678
4734 4733f01 from 4733gat >sa0
4735 4733f02 from 4733gat >sa0
4736 4733f03 from 4733gat >sa0
4737 4737gat nor 1 2 >sa0
4627 4685
4738 4738gat nor 1 2 >sa0
4686 4624
4739 4739gat nor 2 2 >sa0 >sa1
4687 4688
4740 4739f01 from 4739gat >sa0
4741 4739f02 from 4739gat >sa0
4742 4742gat nor 3 2 >sa0 >sa1
4691 1109
4743 4742f01 from 4742gat >sa0
4744 4742f02 from 4742gat >sa0
4745 4742f03 from 4742gat >sa0
4746 4746gat nor 1 2 >sa0
4635 4693
4747 4747gat nor 1 2 >sa0
4694 1156
4748 4748gat nor 2 2 >sa0 >sa1
4516 4695
4749 4748f01 from 4748gat >sa0
4750 4748f02 from 4748gat >sa0
4751 4751gat nor 2 2 >sa0 >sa1
4696 4697
4752 4751f01 from 4751gat >sa0
4753 4751f02 from 4751gat >sa0
4754 4754gat nor 3 2 >sa0 >sa1
4702 4699
4755 4754f01 from 4754gat >sa0
4756 4754f02 from 4754gat >sa0
4757 4754f03 from 4754gat >sa0
4758 4758gat nor 1 2 >sa0
1301 4706
4759 4759gat nor 1 2 >sa0
4707 4645
4760 4760gat nor 2 2 >sa0 >sa1
4708 4709
4761 4760f01 from 4760gat >sa0
4762 4760f02 from 4760gat >sa0
4763 4763gat nor 2 2 >sa0 >sa1
4710 4711
4764 4763f01 from 4763gat >sa0
4765 4763f02 from 4763gat >sa0
4766 4766gat nor 2 2 >sa0 >sa1
4712 4713
4767 4766f01 from 4766gat >sa0
4768 4766f02 from 4766gat >sa0
4769 4769gat nor 2 2 >sa0 >sa1
4714 4715
4770 4769f01 from 4769gat >sa0
4771 4769f02 from 4769gat >sa0
4772 4772gat nor 2 2 >sa0 >sa1
4716 4717
4773 4772f01 from 4772gat >sa0
4774 4772f02 from 4772gat >sa0
4775 4775gat nor 3 2 >sa0 >sa1
4720 818
4776 4775f01 from 4775gat >sa0
4777 4775f02 from 4775gat >sa0
4778 4775f03 from 4775gat >sa0
4779 4779gat nor 1 2 >sa0
4669 4722
4780 4780gat nor 1 2 >sa0
4723 865
4781 4781gat nor 2 2 >sa0 >sa1
4558 4724
4782 4781f01 from 4781gat >sa0
4783 4781f02 from 4781gat >sa0
4784 4784gat nor 2 2 >sa0 >sa1
4725 4726
4785 4784f01 from 4784gat >sa0
4786 4784f02 from 4784gat >sa0
4787 4787gat nor 3 2 >sa0 >sa1
4731 4728
4788 4787f01 from 4787gat >sa0
4789 4787f02 from 4787gat >sa0
4790 4787f03 from 4787gat >sa0
4791 4791gat nor 1 2 >sa0
4682 4735
4792 4792gat nor 1 2 >sa0
4736 4679
4793 4793gat nor 2 2 >sa0 >sa1
4737 4738
4794 4793f01 from 4793gat >sa0
4795 4793f02 from 4793gat >sa0
4796 4796gat nor 3 2 >sa0 >sa1
4741 1061
4797 4796f01 from 4796gat >sa0
4798 4796f02 from 4796gat >sa0
4799 4796f03 from 4796gat >sa0
4800 4800gat nor 1 2 >sa0
4690 4743
4801 4801gat nor 1 2 >sa0
4744 1108
4802 4802gat nor 2 2 >sa0 >sa1
4579 4745
4803 4802f01 from 4802gat >sa0
4804 4802f02 from 4802gat >sa0
4805 4805gat nor 2 2 >sa0 >sa1
4746 4747
4806 4805f01 from 4805gat >sa0
4807 4805f02 from 4805gat >sa0
4808 4808gat nor 3 2 >sa0 >sa1
4752 4749
4809 4808f01 from 4808gat >sa0
4810 4808f02 from 4808gat >sa0
4811 4808f03 from 4808gat >sa0
4812 4812gat nor 1 2 >sa0
4703 4756
4813 4813gat nor 1 2 >sa0
4757 4700
4814 4814gat nor 2 2 >sa0 >sa1
4758 4759
4815 4814f01 from 4814gat >sa0
4816 4814f02 from 4814gat >sa0
4817 4817gat nor 3 2 >sa0 >sa1
4762 578
4818 4817f01 from 4817gat >sa0
4819 4817f02 from 4817gat >sa0
4820 4817f03 from 4817gat >sa0
4821 4821gat nor 3 2 >sa0 >sa1
4765 626
4822 4821f01 from 4821gat >sa0
4823 4821f02 from 4821gat >sa0
4824 4821f03 from 4821gat >sa0
4825 4825gat nor 3 2 >sa0 >sa1
4768 674
4826 4825f01 from 4825gat >sa0
4827 4825f02 from 4825gat >sa0
4828 4825f03 from 4825gat >sa0
4829 4829gat nor 3 2 >sa0 >sa1
4771 722
4830 4829f01 from 4829gat >sa0
4831 4829f02 from 4829gat >sa0
4832 4829f03 from 4829gat >sa0
4833 4833gat nor 3 2 >sa0 >sa1
4774 770
4834 4833f01 from 4833gat >sa0
4835 4833f02 from 4833gat >sa0
4836 4833f03 from 4833gat >sa0
4837 4837gat nor 1 2 >sa0
4719 4776
4838 4838gat nor 1 2 >sa0
4777 817
4839 4839gat nor 2 2 >sa0 >sa1
4608 4778
4840 4839f01 from 4839gat >sa0
4841 4839f02 from 4839gat >sa0
4842 4842gat nor 2 2 >sa0 >sa1
4779 4780
4843 4842f01 from 4842gat >sa0
4844 4842f02 from 4842gat >sa0
4845 4845gat nor 3 2 >sa0 >sa1
4785 4782
4846 4845f01 from 4845gat >sa0
4847 4845f02 from 4845gat >sa0
4848 4845f03 from 4845gat >sa0
4849 4849gat nor 1 2 >sa0
4732 4789
4850 4850gat nor 1 2 >sa0
4790 4729
4851 4851gat nor 2 2 >sa0 >sa1
4791 4792
4852 4851f01 from 4851gat >sa0
4853 4851f02 from 4851gat >sa0
4854 4854gat nor 3 2 >sa0 >sa1
4795 1013
4855 4854f01 from 4854gat >sa0
4856 4854f02 from 4854gat >sa0
4857 4854f03 from 4854gat >sa0
4858 4858gat nor 1 2 >sa0
4740 4797
4859 4859gat nor 1 2 >sa0
4798 1060
4860 4860gat nor 2 2 >sa0 >sa1
4629 4799
4861 4860f01 from 4860gat >sa0
4862 4860f02 from 4860gat >sa0
4863 4863gat nor 2 2 >sa0 >sa1
4800 4801
4864 4863f01 from 4863gat >sa0
4865 4863f02 from 4863gat >sa0
4866 4866gat nor 3 2 >sa0 >sa1
4806 4803
4867 4866f01 from 4866gat >sa0
4868 4866f02 from 4866gat >sa0
4869 4866f03 from 4866gat >sa0
4870 4870gat nor 1 2 >sa0
4753 4810
4871 4871gat nor 1 2 >sa0
4811 4750
4872 4872gat nor 2 2 >sa0 >sa1
4812 4813
4873 4872f01 from 4872gat >sa0
4874 4872f02 from 4872gat >sa0
4875 4875gat nor 3 2 >sa0 >sa1
4816 1256
4876 4875f01 from 4875gat >sa0
4877 4875f02 from 4875gat >sa0
4878 4875f03 from 4875gat >sa0
4879 4879gat nor 1 2 >sa0
4761 4818
4880 4880gat nor 1 2 >sa0
4819 577
4881 4881gat nor 2 2 >sa0 >sa1
4647 4820
4882 4881f01 from 4881gat >sa0
4883 4881f02 from 4881gat >sa0
4884 4884gat nor 1 2 >sa0
4764 4822
4885 4885gat nor 1 2 >sa0
4823 625
4886 4886gat nor 2 2 >sa0 >sa1
4651 4824
4887 4886f01 from 4886gat >sa0
4888 4886f02 from 4886gat >sa0
4889 4889gat nor 1 2 >sa0
4767 4826
4890 4890gat nor 1 2 >sa0
4827 673
4891 4891gat nor 2 2 >sa0 >sa1
4655 4828
4892 4891f01 from 4891gat >sa0
4893 4891f02 from 4891gat >sa0
4894 4894gat nor 1 2 >sa0
4770 4830
4895 4895gat nor 1 2 >sa0
4831 721
4896 4896gat nor 2 2 >sa0 >sa1
4659 4832
4897 4896f01 from 4896gat >sa0
4898 4896f02 from 4896gat >sa0
4899 4899gat nor 1 2 >sa0
4773 4834
4900 4900gat nor 1 2 >sa0
4835 769
4901 4901gat nor 2 2 >sa0 >sa1
4663 4836
4902 4901f01 from 4901gat >sa0
4903 4901f02 from 4901gat >sa0
4904 4904gat nor 2 2 >sa0 >sa1
4837 4838
4905 4904f01 from 4904gat >sa0
4906 4904f02 from 4904gat >sa0
4907 4907gat nor 3 2 >sa0 >sa1
4843 4840
4908 4907f01 from 4907gat >sa0
4909 4907f02 from 4907gat >sa0
4910 4907f03 from 4907gat >sa0
4911 4911gat nor 1 2 >sa0
4786 4847
4912 4912gat nor 1 2 >sa0
4848 4783
4913 4913gat nor 2 2 >sa0 >sa1
4849 4850
4914 4913f01 from 4913gat >sa0
4915 4913f02 from 4913gat >sa0
4916 4916gat nor 3 2 >sa0 >sa1
4853 965
4917 4916f01 from 4916gat >sa0
4918 4916f02 from 4916gat >sa0
4919 4916f03 from 4916gat >sa0
4920 4920gat nor 1 2 >sa0
4794 4855
4921 4921gat nor 1 2 >sa0
4856 1012
4922 4922gat nor 2 2 >sa0 >sa1
4684 4857
4923 4922f01 from 4922gat >sa0
4924 4922f02 from 4922gat >sa0
4925 4925gat nor 2 2 >sa0 >sa1
4858 4859
4926 4925f01 from 4925gat >sa0
4927 4925f02 from 4925gat >sa0
4928 4928gat nor 3 2 >sa0 >sa1
4864 4861
4929 4928f01 from 4928gat >sa0
4930 4928f02 from 4928gat >sa0
4931 4928f03 from 4928gat >sa0
4932 4932gat nor 1 2 >sa0
4807 4868
4933 4933gat nor 1 2 >sa0
4869 4804
4934 4934gat nor 2 2 >sa0 >sa1
4870 4871
4935 4934f01 from 4934gat >sa0
4936 4934f02 from 4934gat >sa0
4937 4937gat nor 3 2 >sa0 >sa1
4874 1208
4938 4937f01 from 4937gat >sa0
4939 4937f02 from 4937gat >sa0
4940 4937f03 from 4937gat >sa0
4941 4941gat nor 1 2 >sa0
4815 4876
4942 4942gat nor 1 2 >sa0
4877 1255
4943 4943gat nor 2 2 >sa0 >sa1
4705 4878
4944 4943f01 from 4943gat >sa0
4945 4943f02 from 4943gat >sa0
4946 4946gat nor 0 2 >sa0 >sa1
4879 4880
4947 4947gat nor 2 2 >sa0 >sa1
4884 4885
4948 4947f01 from 4947gat >sa0
4949 4947f02 from 4947gat >sa0
4950 4950gat nor 2 2 >sa0 >sa1
4889 4890
4951 4950f01 from 4950gat >sa0
4952 4950f02 from 4950gat >sa0
4953 4953gat nor 2 2 >sa0 >sa1
4894 4895
4954 4953f01 from 4953gat >sa0
4955 4953f02 from 4953gat >sa0
4956 4956gat nor 2 2 >sa0 >sa1
4899 4900
4957 4956f01 from 4956gat >sa0
4958 4956f02 from 4956gat >sa0
4959 4959gat nor 3 2 >sa0 >sa1
4905 4902
4960 4959f01 from 4959gat >sa0
4961 4959f02 from 4959gat >sa0
4962 4959f03 from 4959gat >sa0
4963 4963gat nor 1 2 >sa0
4844 4909
4964 4964gat nor 1 2 >sa0
4910 4841
4965 4965gat nor 2 2 >sa0 >sa1
4911 4912
4966 4965f01 from 4965gat >sa0
4967 4965f02 from 4965gat >sa0
4968 4968gat nor 3 2 >sa0 >sa1
4915 917
4969 4968f01 from 4968gat >sa0
4970 4968f02 from 4968gat >sa0
4971 4968f03 from 4968gat >sa0
4972 4972gat nor 1 2 >sa0
4852 4917
4973 4973gat nor 1 2 >sa0
4918 964
4974 4974gat nor 2 2 >sa0 >sa1
4734 4919
4975 4974f01 from 4974gat >sa0
4976 4974f02 from 4974gat >sa0
4977 4977gat nor 2 2 >sa0 >sa1
4920 4921
4978 4977f01 from 4977gat >sa0
4979 4977f02 from 4977gat >sa0
4980 4980gat nor 3 2 >sa0 >sa1
4926 4923
4981 4980f01 from 4980gat >sa0
4982 4980f02 from 4980gat >sa0
4983 4980f03 from 4980gat >sa0
4984 4984gat nor 1 2 >sa0
4865 4930
4985 4985gat nor 1 2 >sa0
4931 4862
4986 4986gat nor 2 2 >sa0 >sa1
4932 4933
4987 4986f01 from 4986gat >sa0
4988 4986f02 from 4986gat >sa0
4989 4989gat nor 3 2 >sa0 >sa1
4936 1160
4990 4989f01 from 4989gat >sa0
4991 4989f02 from 4989gat >sa0
4992 4989f03 from 4989gat >sa0
4993 4993gat nor 1 2 >sa0
4873 4938
4994 4994gat nor 1 2 >sa0
4939 1207
4995 4995gat nor 2 2 >sa0 >sa1
4755 4940
4996 4995f01 from 4995gat >sa0
4997 4995f02 from 4995gat >sa0
4998 4998gat nor 2 2 >sa0 >sa1
4941 4942
4999 4998f01 from 4998gat >sa0
5000 4998f02 from 4998gat >sa0
5001 5001gat nor 3 2 >sa0 >sa1
1303 4944
5002 5001f01 from 5001gat >sa0
5003 5001f02 from 5001gat >sa0
5004 5001f03 from 5001gat >sa0
5005 5005gat nor 3 2 >sa0 >sa1
4948 4882
5006 5005f01 from 5005gat >sa0
5007 5005f02 from 5005gat >sa0
5008 5005f03 from 5005gat >sa0
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4951 4887
5010 5009f01 from 5009gat >sa0
5011 5009f02 from 5009gat >sa0
5012 5009f03 from 5009gat >sa0
5013 5013gat nor 3 2 >sa0 >sa1
4954 4892
5014 5013f01 from 5013gat >sa0
5015 5013f02 from 5013gat >sa0
5016 5013f03 from 5013gat >sa0
5017 5017gat nor 3 2 >sa0 >sa1
4957 4897
5018 5017f01 from 5017gat >sa0
5019 5017f02 from 5017gat >sa0
5020 5017f03 from 5017gat >sa0
5021 5021gat nor 1 2 >sa0
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4962 4903
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4963 4964
5024 5023f01 from 5023gat >sa0
5025 5023f02 from 5023gat >sa0
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4967 869
5027 5026f01 from 5026gat >sa0
5028 5026f02 from 5026gat >sa0
5029 5026f03 from 5026gat >sa0
5030 5030gat nor 1 2 >sa0
4914 4969
5031 5031gat nor 1 2 >sa0
4970 916
5032 5032gat nor 2 2 >sa0 >sa1
4788 4971
5033 5032f01 from 5032gat >sa0
5034 5032f02 from 5032gat >sa0
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4972 4973
5036 5035f01 from 5035gat >sa0
5037 5035f02 from 5035gat >sa0
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4978 4975
5039 5038f01 from 5038gat >sa0
5040 5038f02 from 5038gat >sa0
5041 5038f03 from 5038gat >sa0
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4927 4982
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4983 4924
5044 5044gat nor 2 2 >sa0 >sa1
4984 4985
5045 5044f01 from 5044gat >sa0
5046 5044f02 from 5044gat >sa0
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4988 1112
5048 5047f01 from 5047gat >sa0
5049 5047f02 from 5047gat >sa0
5050 5047f03 from 5047gat >sa0
5051 5051gat nor 1 2 >sa0
4935 4990
5052 5052gat nor 1 2 >sa0
4991 1159
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4809 4992
5054 5053f01 from 5053gat >sa0
5055 5053f02 from 5053gat >sa0
5056 5056gat nor 2 2 >sa0 >sa1
4993 4994
5057 5056f01 from 5056gat >sa0
5058 5056f02 from 5056gat >sa0
5059 5059gat nor 3 2 >sa0 >sa1
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5060 5059f01 from 5059gat >sa0
5061 5059f02 from 5059gat >sa0
5062 5059f03 from 5059gat >sa0
5063 5063gat nor 1 2 >sa0
1304 5003
5064 5064gat nor 1 2 >sa0
5004 4945
5065 5065gat nor 1 2 >sa0
4949 5007
5066 5066gat nor 1 2 >sa0
5008 4883
5067 5067gat nor 1 2 >sa0
4952 5011
5068 5068gat nor 1 2 >sa0
5012 4888
5069 5069gat nor 1 2 >sa0
4955 5015
5070 5070gat nor 1 2 >sa0
5016 4893
5071 5071gat nor 1 2 >sa0
4958 5019
5072 5072gat nor 1 2 >sa0
5020 4898
5073 5073gat nor 2 2 >sa0 >sa1
5021 5022
5074 5073f01 from 5073gat >sa0
5075 5073f02 from 5073gat >sa0
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5025 821
5077 5076f01 from 5076gat >sa0
5078 5076f02 from 5076gat >sa0
5079 5076f03 from 5076gat >sa0
5080 5080gat nor 1 2 >sa0
4966 5027
5081 5081gat nor 1 2 >sa0
5028 868
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4846 5029
5083 5082f01 from 5082gat >sa0
5084 5082f02 from 5082gat >sa0
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5030 5031
5086 5085f01 from 5085gat >sa0
5087 5085f02 from 5085gat >sa0
5088 5088gat nor 3 2 >sa0 >sa1
5036 5033
5089 5088f01 from 5088gat >sa0
5090 5088f02 from 5088gat >sa0
5091 5088f03 from 5088gat >sa0
5092 5092gat nor 1 2 >sa0
4979 5040
5093 5093gat nor 1 2 >sa0
5041 4976
5094 5094gat nor 2 2 >sa0 >sa1
5042 5043
5095 5094f01 from 5094gat >sa0
5096 5094f02 from 5094gat >sa0
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5046 1064
5098 5097f01 from 5097gat >sa0
5099 5097f02 from 5097gat >sa0
5100 5097f03 from 5097gat >sa0
5101 5101gat nor 1 2 >sa0
4987 5048
5102 5102gat nor 1 2 >sa0
5049 1111
5103 5103gat nor 2 2 >sa0 >sa1
4867 5050
5104 5103f01 from 5103gat >sa0
5105 5103f02 from 5103gat >sa0
5106 5106gat nor 2 2 >sa0 >sa1
5051 5052
5107 5106f01 from 5106gat >sa0
5108 5106f02 from 5106gat >sa0
5109 5109gat nor 3 2 >sa0 >sa1
5057 5054
5110 5109f01 from 5109gat >sa0
5111 5109f02 from 5109gat >sa0
5112 5109f03 from 5109gat >sa0
5113 5113gat nor 1 2 >sa0
5000 5061
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5062 4997
5115 5115gat nor 2 2 >sa0 >sa1
5063 5064
5116 5115f01 from 5115gat >sa0
5117 5115f02 from 5115gat >sa0
5118 5118gat nor 2 2 >sa0 >sa1
5065 5066
5119 5118f01 from 5118gat >sa0
5120 5118f02 from 5118gat >sa0
5121 5121gat nor 2 2 >sa0 >sa1
5067 5068
5122 5121f01 from 5121gat >sa0
5123 5121f02 from 5121gat >sa0
5124 5124gat nor 2 2 >sa0 >sa1
5069 5070
5125 5124f01 from 5124gat >sa0
5126 5124f02 from 5124gat >sa0
5127 5127gat nor 2 2 >sa0 >sa1
5071 5072
5128 5127f01 from 5127gat >sa0
5129 5127f02 from 5127gat >sa0
5130 5130gat nor 3 2 >sa0 >sa1
5075 773
5131 5130f01 from 5130gat >sa0
5132 5130f02 from 5130gat >sa0
5133 5130f03 from 5130gat >sa0
5134 5134gat nor 1 2 >sa0
5024 5077
5135 5135gat nor 1 2 >sa0
5078 820
5136 5136gat nor 2 2 >sa0 >sa1
4908 5079
5137 5136f01 from 5136gat >sa0
5138 5136f02 from 5136gat >sa0
5139 5139gat nor 2 2 >sa0 >sa1
5080 5081
5140 5139f01 from 5139gat >sa0
5141 5139f02 from 5139gat >sa0
5142 5142gat nor 3 2 >sa0 >sa1
5086 5083
5143 5142f01 from 5142gat >sa0
5144 5142f02 from 5142gat >sa0
5145 5142f03 from 5142gat >sa0
5146 5146gat nor 1 2 >sa0
5037 5090
5147 5147gat nor 1 2 >sa0
5091 5034
5148 5148gat nor 2 2 >sa0 >sa1
5092 5093
5149 5148f01 from 5148gat >sa0
5150 5148f02 from 5148gat >sa0
5151 5151gat nor 3 2 >sa0 >sa1
5096 1016
5152 5151f01 from 5151gat >sa0
5153 5151f02 from 5151gat >sa0
5154 5151f03 from 5151gat >sa0
5155 5155gat nor 1 2 >sa0
5045 5098
5156 5156gat nor 1 2 >sa0
5099 1063
5157 5157gat nor 2 2 >sa0 >sa1
4929 5100
5158 5157f01 from 5157gat >sa0
5159 5157f02 from 5157gat >sa0
5160 5160gat nor 2 2 >sa0 >sa1
5101 5102
5161 5160f01 from 5160gat >sa0
5162 5160f02 from 5160gat >sa0
5163 5163gat nor 3 2 >sa0 >sa1
5107 5104
5164 5163f01 from 5163gat >sa0
5165 5163f02 from 5163gat >sa0
5166 5163f03 from 5163gat >sa0
5167 5167gat nor 1 2 >sa0
5058 5111
5168 5168gat nor 1 2 >sa0
5112 5055
5169 5169gat nor 2 2 >sa0 >sa1
5113 5114
5170 5169f01 from 5169gat >sa0
5171 5169f02 from 5169gat >sa0
5172 5172gat nor 3 2 >sa0 >sa1
5117 1259
5173 5172f01 from 5172gat >sa0
5174 5172f02 from 5172gat >sa0
5175 5172f03 from 5172gat >sa0
5176 5176gat nor 3 2 >sa0 >sa1
5120 581
5177 5176f01 from 5176gat >sa0
5178 5176f02 from 5176gat >sa0
5179 5176f03 from 5176gat >sa0
5180 5180gat nor 3 2 >sa0 >sa1
5123 629
5181 5180f01 from 5180gat >sa0
5182 5180f02 from 5180gat >sa0
5183 5180f03 from 5180gat >sa0
5184 5184gat nor 3 2 >sa0 >sa1
5126 677
5185 5184f01 from 5184gat >sa0
5186 5184f02 from 5184gat >sa0
5187 5184f03 from 5184gat >sa0
5188 5188gat nor 3 2 >sa0 >sa1
5129 725
5189 5188f01 from 5188gat >sa0
5190 5188f02 from 5188gat >sa0
5191 5188f03 from 5188gat >sa0
5192 5192gat nor 1 2 >sa0
5074 5131
5193 5193gat nor 1 2 >sa0
5132 772
5194 5194gat nor 2 2 >sa0 >sa1
4960 5133
5195 5194f01 from 5194gat >sa0
5196 5194f02 from 5194gat >sa0
5197 5197gat nor 2 2 >sa0 >sa1
5134 5135
5198 5197f01 from 5197gat >sa0
5199 5197f02 from 5197gat >sa0
5200 5200gat nor 3 2 >sa0 >sa1
5140 5137
5201 5200f01 from 5200gat >sa0
5202 5200f02 from 5200gat >sa0
5203 5200f03 from 5200gat >sa0
5204 5204gat nor 1 2 >sa0
5087 5144
5205 5205gat nor 1 2 >sa0
5145 5084
5206 5206gat nor 2 2 >sa0 >sa1
5146 5147
5207 5206f01 from 5206gat >sa0
5208 5206f02 from 5206gat >sa0
5209 5209gat nor 3 2 >sa0 >sa1
5150 968
5210 5209f01 from 5209gat >sa0
5211 5209f02 from 5209gat >sa0
5212 5209f03 from 5209gat >sa0
5213 5213gat nor 1 2 >sa0
5095 5152
5214 5214gat nor 1 2 >sa0
5153 1015
5215 5215gat nor 2 2 >sa0 >sa1
4981 5154
5216 5215f01 from 5215gat >sa0
5217 5215f02 from 5215gat >sa0
5218 5218gat nor 2 2 >sa0 >sa1
5155 5156
5219 5218f01 from 5218gat >sa0
5220 5218f02 from 5218gat >sa0
5221 5221gat nor 3 2 >sa0 >sa1
5161 5158
5222 5221f01 from 5221gat >sa0
5223 5221f02 from 5221gat >sa0
5224 5221f03 from 5221gat >sa0
5225 5225gat nor 1 2 >sa0
5108 5165
5226 5226gat nor 1 2 >sa0
5166 5105
5227 5227gat nor 2 2 >sa0 >sa1
5167 5168
5228 5227f01 from 5227gat >sa0
5229 5227f02 from 5227gat >sa0
5230 5230gat nor 3 2 >sa0 >sa1
5171 1211
5231 5230f01 from 5230gat >sa0
5232 5230f02 from 5230gat >sa0
5233 5230f03 from 5230gat >sa0
5234 5234gat nor 1 2 >sa0
5116 5173
5235 5235gat nor 1 2 >sa0
5174 1258
5236 5236gat nor 2 2 >sa0 >sa1
5002 5175
5237 5236f01 from 5236gat >sa0
5238 5236f02 from 5236gat >sa0
5239 5239gat nor 1 2 >sa0
5119 5177
5240 5240gat nor 1 2 >sa0
5178 580
5241 5241gat nor 2 2 >sa0 >sa1
5006 5179
5242 5241f01 from 5241gat >sa0
5243 5241f02 from 5241gat >sa0
5244 5244gat nor 1 2 >sa0
5122 5181
5245 5245gat nor 1 2 >sa0
5182 628
5246 5246gat nor 2 2 >sa0 >sa1
5010 5183
5247 5246f01 from 5246gat >sa0
5248 5246f02 from 5246gat >sa0
5249 5249gat nor 1 2 >sa0
5125 5185
5250 5250gat nor 1 2 >sa0
5186 676
5251 5251gat nor 2 2 >sa0 >sa1
5014 5187
5252 5251f01 from 5251gat >sa0
5253 5251f02 from 5251gat >sa0
5254 5254gat nor 1 2 >sa0
5128 5189
5255 5255gat nor 1 2 >sa0
5190 724
5256 5256gat nor 2 2 >sa0 >sa1
5018 5191
5257 5256f01 from 5256gat >sa0
5258 5256f02 from 5256gat >sa0
5259 5259gat nor 2 2 >sa0 >sa1
5192 5193
5260 5259f01 from 5259gat >sa0
5261 5259f02 from 5259gat >sa0
5262 5262gat nor 3 2 >sa0 >sa1
5198 5195
5263 5262f01 from 5262gat >sa0
5264 5262f02 from 5262gat >sa0
5265 5262f03 from 5262gat >sa0
5266 5266gat nor 1 2 >sa0
5141 5202
5267 5267gat nor 1 2 >sa0
5203 5138
5268 5268gat nor 2 2 >sa0 >sa1
5204 5205
5269 5268f01 from 5268gat >sa0
5270 5268f02 from 5268gat >sa0
5271 5271gat nor 3 2 >sa0 >sa1
5208 920
5272 5271f01 from 5271gat >sa0
5273 5271f02 from 5271gat >sa0
5274 5271f03 from 5271gat >sa0
5275 5275gat nor 1 2 >sa0
5149 5210
5276 5276gat nor 1 2 >sa0
5211 967
5277 5277gat nor 2 2 >sa0 >sa1
5039 5212
5278 5277f01 from 5277gat >sa0
5279 5277f02 from 5277gat >sa0
5280 5280gat nor 2 2 >sa0 >sa1
5213 5214
5281 5280f01 from 5280gat >sa0
5282 5280f02 from 5280gat >sa0
5283 5283gat nor 3 2 >sa0 >sa1
5219 5216
5284 5283f01 from 5283gat >sa0
5285 5283f02 from 5283gat >sa0
5286 5283f03 from 5283gat >sa0
5287 5287gat nor 1 2 >sa0
5162 5223
5288 5288gat nor 1 2 >sa0
5224 5159
5289 5289gat nor 2 2 >sa0 >sa1
5225 5226
5290 5289f01 from 5289gat >sa0
5291 5289f02 from 5289gat >sa0
5292 5292gat nor 3 2 >sa0 >sa1
5229 1163
5293 5292f01 from 5292gat >sa0
5294 5292f02 from 5292gat >sa0
5295 5292f03 from 5292gat >sa0
5296 5296gat nor 1 2 >sa0
5170 5231
5297 5297gat nor 1 2 >sa0
5232 1210
5298 5298gat nor 2 2 >sa0 >sa1
5060 5233
5299 5298f01 from 5298gat >sa0
5300 5298f02 from 5298gat >sa0
5301 5301gat nor 2 2 >sa0 >sa1
5234 5235
5302 5301f01 from 5301gat >sa0
5303 5301f02 from 5301gat >sa0
5304 5304gat nor 3 2 >sa0 >sa1
1306 5237
5305 5304f01 from 5304gat >sa0
5306 5304f02 from 5304gat >sa0
5307 5304f03 from 5304gat >sa0
5308 5308gat nor 0 2 >sa0 >sa1
5239 5240
5309 5309gat nor 2 2 >sa0 >sa1
5244 5245
5310 5309f01 from 5309gat >sa0
5311 5309f02 from 5309gat >sa0
5312 5312gat nor 2 2 >sa0 >sa1
5249 5250
5313 5312f01 from 5312gat >sa0
5314 5312f02 from 5312gat >sa0
5315 5315gat nor 2 2 >sa0 >sa1
5254 5255
5316 5315f01 from 5315gat >sa0
5317 5315f02 from 5315gat >sa0
5318 5318gat nor 3 2 >sa0 >sa1
5260 5257
5319 5318f01 from 5318gat >sa0
5320 5318f02 from 5318gat >sa0
5321 5318f03 from 5318gat >sa0
5322 5322gat nor 1 2 >sa0
5199 5264
5323 5323gat nor 1 2 >sa0
5265 5196
5324 5324gat nor 2 2 >sa0 >sa1
5266 5267
5325 5324f01 from 5324gat >sa0
5326 5324f02 from 5324gat >sa0
5327 5327gat nor 3 2 >sa0 >sa1
5270 872
5328 5327f01 from 5327gat >sa0
5329 5327f02 from 5327gat >sa0
5330 5327f03 from 5327gat >sa0
5331 5331gat nor 1 2 >sa0
5207 5272
5332 5332gat nor 1 2 >sa0
5273 919
5333 5333gat nor 2 2 >sa0 >sa1
5089 5274
5334 5333f01 from 5333gat >sa0
5335 5333f02 from 5333gat >sa0
5336 5336gat nor 2 2 >sa0 >sa1
5275 5276
5337 5336f01 from 5336gat >sa0
5338 5336f02 from 5336gat >sa0
5339 5339gat nor 3 2 >sa0 >sa1
5281 5278
5340 5339f01 from 5339gat >sa0
5341 5339f02 from 5339gat >sa0
5342 5339f03 from 5339gat >sa0
5343 5343gat nor 1 2 >sa0
5220 5285
5344 5344gat nor 1 2 >sa0
5286 5217
5345 5345gat nor 2 2 >sa0 >sa1
5287 5288
5346 5345f01 from 5345gat >sa0
5347 5345f02 from 5345gat >sa0
5348 5348gat nor 3 2 >sa0 >sa1
5291 1115
5349 5348f01 from 5348gat >sa0
5350 5348f02 from 5348gat >sa0
5351 5348f03 from 5348gat >sa0
5352 5352gat nor 1 2 >sa0
5228 5293
5353 5353gat nor 1 2 >sa0
5294 1162
5354 5354gat nor 2 2 >sa0 >sa1
5110 5295
5355 5354f01 from 5354gat >sa0
5356 5354f02 from 5354gat >sa0
5357 5357gat nor 2 2 >sa0 >sa1
5296 5297
5358 5357f01 from 5357gat >sa0
5359 5357f02 from 5357gat >sa0
5360 5360gat nor 3 2 >sa0 >sa1
5302 5299
5361 5360f01 from 5360gat >sa0
5362 5360f02 from 5360gat >sa0
5363 5360f03 from 5360gat >sa0
5364 5364gat nor 1 2 >sa0
1307 5306
5365 5365gat nor 1 2 >sa0
5307 5238
5366 5366gat nor 3 2 >sa0 >sa1
5310 5242
5367 5366f01 from 5366gat >sa0
5368 5366f02 from 5366gat >sa0
5369 5366f03 from 5366gat >sa0
5370 5370gat nor 3 2 >sa0 >sa1
5313 5247
5371 5370f01 from 5370gat >sa0
5372 5370f02 from 5370gat >sa0
5373 5370f03 from 5370gat >sa0
5374 5374gat nor 3 2 >sa0 >sa1
5316 5252
5375 5374f01 from 5374gat >sa0
5376 5374f02 from 5374gat >sa0
5377 5374f03 from 5374gat >sa0
5378 5378gat nor 1 2 >sa0
5261 5320
5379 5379gat nor 1 2 >sa0
5321 5258
5380 5380gat nor 2 2 >sa0 >sa1
5322 5323
5381 5380f01 from 5380gat >sa0
5382 5380f02 from 5380gat >sa0
5383 5383gat nor 3 2 >sa0 >sa1
5326 824
5384 5383f01 from 5383gat >sa0
5385 5383f02 from 5383gat >sa0
5386 5383f03 from 5383gat >sa0
5387 5387gat nor 1 2 >sa0
5269 5328
5388 5388gat nor 1 2 >sa0
5329 871
5389 5389gat nor 2 2 >sa0 >sa1
5143 5330
5390 5389f01 from 5389gat >sa0
5391 5389f02 from 5389gat >sa0
5392 5392gat nor 2 2 >sa0 >sa1
5331 5332
5393 5392f01 from 5392gat >sa0
5394 5392f02 from 5392gat >sa0
5395 5395gat nor 3 2 >sa0 >sa1
5337 5334
5396 5395f01 from 5395gat >sa0
5397 5395f02 from 5395gat >sa0
5398 5395f03 from 5395gat >sa0
5399 5399gat nor 1 2 >sa0
5282 5341
5400 5400gat nor 1 2 >sa0
5342 5279
5401 5401gat nor 2 2 >sa0 >sa1
5343 5344
5402 5401f01 from 5401gat >sa0
5403 5401f02 from 5401gat >sa0
5404 5404gat nor 3 2 >sa0 >sa1
5347 1067
5405 5404f01 from 5404gat >sa0
5406 5404f02 from 5404gat >sa0
5407 5404f03 from 5404gat >sa0
5408 5408gat nor 1 2 >sa0
5290 5349
5409 5409gat nor 1 2 >sa0
5350 1114
5410 5410gat nor 2 2 >sa0 >sa1
5164 5351
5411 5410f01 from 5410gat >sa0
5412 5410f02 from 5410gat >sa0
5413 5413gat nor 2 2 >sa0 >sa1
5352 5353
5414 5413f01 from 5413gat >sa0
5415 5413f02 from 5413gat >sa0
5416 5416gat nor 3 2 >sa0 >sa1
5358 5355
5417 5416f01 from 5416gat >sa0
5418 5416f02 from 5416gat >sa0
5419 5416f03 from 5416gat >sa0
5420 5420gat nor 1 2 >sa0
5303 5362
5421 5421gat nor 1 2 >sa0
5363 5300
5422 5422gat nor 2 2 >sa0 >sa1
5364 5365
5423 5422f01 from 5422gat >sa0
5424 5422f02 from 5422gat >sa0
5425 5425gat nor 1 2 >sa0
5311 5368
5426 5426gat nor 1 2 >sa0
5369 5243
5427 5427gat nor 1 2 >sa0
5314 5372
5428 5428gat nor 1 2 >sa0
5373 5248
5429 5429gat nor 1 2 >sa0
5317 5376
5430 5430gat nor 1 2 >sa0
5377 5253
5431 5431gat nor 2 2 >sa0 >sa1
5378 5379
5432 5431f01 from 5431gat >sa0
5433 5431f02 from 5431gat >sa0
5434 5434gat nor 3 2 >sa0 >sa1
5382 776
5435 5434f01 from 5434gat >sa0
5436 5434f02 from 5434gat >sa0
5437 5434f03 from 5434gat >sa0
5438 5438gat nor 1 2 >sa0
5325 5384
5439 5439gat nor 1 2 >sa0
5385 823
5440 5440gat nor 2 2 >sa0 >sa1
5201 5386
5441 5440f01 from 5440gat >sa0
5442 5440f02 from 5440gat >sa0
5443 5443gat nor 2 2 >sa0 >sa1
5387 5388
5444 5443f01 from 5443gat >sa0
5445 5443f02 from 5443gat >sa0
5446 5446gat nor 3 2 >sa0 >sa1
5393 5390
5447 5446f01 from 5446gat >sa0
5448 5446f02 from 5446gat >sa0
5449 5446f03 from 5446gat >sa0
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5399 5400
5453 5452f01 from 5452gat >sa0
5454 5452f02 from 5452gat >sa0
5455 5455gat nor 3 2 >sa0 >sa1
5403 1019
5456 5455f01 from 5455gat >sa0
5457 5455f02 from 5455gat >sa0
5458 5455f03 from 5455gat >sa0
5459 5459gat nor 1 2 >sa0
5346 5405
5460 5460gat nor 1 2 >sa0
5406 1066
5461 5461gat nor 2 2 >sa0 >sa1
5222 5407
5462 5461f01 from 5461gat >sa0
5463 5461f02 from 5461gat >sa0
5464 5464gat nor 2 2 >sa0 >sa1
5408 5409
5465 5464f01 from 5464gat >sa0
5466 5464f02 from 5464gat >sa0
5467 5467gat nor 3 2 >sa0 >sa1
5414 5411
5468 5467f01 from 5467gat >sa0
5469 5467f02 from 5467gat >sa0
5470 5467f03 from 5467gat >sa0
5471 5471gat nor 1 2 >sa0
5359 5418
5472 5472gat nor 1 2 >sa0
5419 5356
5473 5473gat nor 2 2 >sa0 >sa1
5420 5421
5474 5473f01 from 5473gat >sa0
5475 5473f02 from 5473gat >sa0
5476 5476gat nor 3 2 >sa0 >sa1
5424 1262
5477 5476f01 from 5476gat >sa0
5478 5476f02 from 5476gat >sa0
5479 5476f03 from 5476gat >sa0
5480 5480gat nor 2 2 >sa0 >sa1
5425 5426
5481 5480f01 from 5480gat >sa0
5482 5480f02 from 5480gat >sa0
5483 5483gat nor 2 2 >sa0 >sa1
5427 5428
5484 5483f01 from 5483gat >sa0
5485 5483f02 from 5483gat >sa0
5486 5486gat nor 2 2 >sa0 >sa1
5429 5430
5487 5486f01 from 5486gat >sa0
5488 5486f02 from 5486gat >sa0
5489 5489gat nor 3 2 >sa0 >sa1
5433 728
5490 5489f01 from 5489gat >sa0
5491 5489f02 from 5489gat >sa0
5492 5489f03 from 5489gat >sa0
5493 5493gat nor 1 2 >sa0
5381 5435
5494 5494gat nor 1 2 >sa0
5436 775
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5263 5437
5496 5495f01 from 5495gat >sa0
5497 5495f02 from 5495gat >sa0
5498 5498gat nor 2 2 >sa0 >sa1
5438 5439
5499 5498f01 from 5498gat >sa0
5500 5498f02 from 5498gat >sa0
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5444 5441
5502 5501f01 from 5501gat >sa0
5503 5501f02 from 5501gat >sa0
5504 5501f03 from 5501gat >sa0
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5449 5391
5507 5507gat nor 2 2 >sa0 >sa1
5450 5451
5508 5507f01 from 5507gat >sa0
5509 5507f02 from 5507gat >sa0
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5511 5510f01 from 5510gat >sa0
5512 5510f02 from 5510gat >sa0
5513 5510f03 from 5510gat >sa0
5514 5514gat nor 1 2 >sa0
5402 5456
5515 5515gat nor 1 2 >sa0
5457 1018
5516 5516gat nor 2 2 >sa0 >sa1
5284 5458
5517 5516f01 from 5516gat >sa0
5518 5516f02 from 5516gat >sa0
5519 5519gat nor 2 2 >sa0 >sa1
5459 5460
5520 5519f01 from 5519gat >sa0
5521 5519f02 from 5519gat >sa0
5522 5522gat nor 3 2 >sa0 >sa1
5465 5462
5523 5522f01 from 5522gat >sa0
5524 5522f02 from 5522gat >sa0
5525 5522f03 from 5522gat >sa0
5526 5526gat nor 1 2 >sa0
5415 5469
5527 5527gat nor 1 2 >sa0
5470 5412
5528 5528gat nor 2 2 >sa0 >sa1
5471 5472
5529 5528f01 from 5528gat >sa0
5530 5528f02 from 5528gat >sa0
5531 5531gat nor 3 2 >sa0 >sa1
5475 1214
5532 5531f01 from 5531gat >sa0
5533 5531f02 from 5531gat >sa0
5534 5531f03 from 5531gat >sa0
5535 5535gat nor 1 2 >sa0
5423 5477
5536 5536gat nor 1 2 >sa0
5478 1261
5537 5537gat nor 2 2 >sa0 >sa1
5305 5479
5538 5537f01 from 5537gat >sa0
5539 5537f02 from 5537gat >sa0
5540 5540gat nor 3 2 >sa0 >sa1
5482 584
5541 5540f01 from 5540gat >sa0
5542 5540f02 from 5540gat >sa0
5543 5540f03 from 5540gat >sa0
5544 5544gat nor 3 2 >sa0 >sa1
5485 632
5545 5544f01 from 5544gat >sa0
5546 5544f02 from 5544gat >sa0
5547 5544f03 from 5544gat >sa0
5548 5548gat nor 3 2 >sa0 >sa1
5488 680
5549 5548f01 from 5548gat >sa0
5550 5548f02 from 5548gat >sa0
5551 5548f03 from 5548gat >sa0
5552 5552gat nor 1 2 >sa0
5432 5490
5553 5553gat nor 1 2 >sa0
5491 727
5554 5554gat nor 2 2 >sa0 >sa1
5319 5492
5555 5554f01 from 5554gat >sa0
5556 5554f02 from 5554gat >sa0
5557 5557gat nor 2 2 >sa0 >sa1
5493 5494
5558 5557f01 from 5557gat >sa0
5559 5557f02 from 5557gat >sa0
5560 5560gat nor 3 2 >sa0 >sa1
5499 5496
5561 5560f01 from 5560gat >sa0
5562 5560f02 from 5560gat >sa0
5563 5560f03 from 5560gat >sa0
5564 5564gat nor 1 2 >sa0
5445 5503
5565 5565gat nor 1 2 >sa0
5504 5442
5566 5566gat nor 2 2 >sa0 >sa1
5505 5506
5567 5566f01 from 5566gat >sa0
5568 5566f02 from 5566gat >sa0
5569 5569gat nor 3 2 >sa0 >sa1
5509 923
5570 5569f01 from 5569gat >sa0
5571 5569f02 from 5569gat >sa0
5572 5569f03 from 5569gat >sa0
5573 5573gat nor 1 2 >sa0
5453 5511
5574 5574gat nor 1 2 >sa0
5512 970
5575 5575gat nor 2 2 >sa0 >sa1
5340 5513
5576 5575f01 from 5575gat >sa0
5577 5575f02 from 5575gat >sa0
5578 5578gat nor 2 2 >sa0 >sa1
5514 5515
5579 5578f01 from 5578gat >sa0
5580 5578f02 from 5578gat >sa0
5581 5581gat nor 3 2 >sa0 >sa1
5520 5517
5582 5581f01 from 5581gat >sa0
5583 5581f02 from 5581gat >sa0
5584 5581f03 from 5581gat >sa0
5585 5585gat nor 1 2 >sa0
5466 5524
5586 5586gat nor 1 2 >sa0
5525 5463
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5526 5527
5588 5587f01 from 5587gat >sa0
5589 5587f02 from 5587gat >sa0
5590 5590gat nor 3 2 >sa0 >sa1
5530 1166
5591 5590f01 from 5590gat >sa0
5592 5590f02 from 5590gat >sa0
5593 5590f03 from 5590gat >sa0
5594 5594gat nor 1 2 >sa0
5474 5532
5595 5595gat nor 1 2 >sa0
5533 1213
5596 5596gat nor 2 2 >sa0 >sa1
5361 5534
5597 5596f01 from 5596gat >sa0
5598 5596f02 from 5596gat >sa0
5599 5599gat nor 2 2 >sa0 >sa1
5535 5536
5600 5599f01 from 5599gat >sa0
5601 5599f02 from 5599gat >sa0
5602 5602gat nor 3 2 >sa0 >sa1
1309 5538
5603 5602f01 from 5602gat >sa0
5604 5602f02 from 5602gat >sa0
5605 5602f03 from 5602gat >sa0
5606 5606gat nor 1 2 >sa0
5481 5541
5607 5607gat nor 1 2 >sa0
5542 583
5608 5608gat nor 2 2 >sa0 >sa1
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5609 5608f01 from 5608gat >sa0
5610 5608f02 from 5608gat >sa0
5611 5611gat nor 1 2 >sa0
5484 5545
5612 5612gat nor 1 2 >sa0
5546 631
5613 5613gat nor 2 2 >sa0 >sa1
5371 5547
5614 5613f01 from 5613gat >sa0
5615 5613f02 from 5613gat >sa0
5616 5616gat nor 1 2 >sa0
5487 5549
5617 5617gat nor 1 2 >sa0
5550 679
5618 5618gat nor 2 2 >sa0 >sa1
5375 5551
5619 5618f01 from 5618gat >sa0
5620 5618f02 from 5618gat >sa0
5621 5621gat nor 2 2 >sa0 >sa1
5552 5553
5622 5621f01 from 5621gat >sa0
5623 5621f02 from 5621gat >sa0
5624 5624gat nor 3 2 >sa0 >sa1
5558 5555
5625 5624f01 from 5624gat >sa0
5626 5624f02 from 5624gat >sa0
5627 5624f03 from 5624gat >sa0
5628 5628gat nor 1 2 >sa0
5500 5562
5629 5629gat nor 1 2 >sa0
5563 5497
5630 5630gat nor 2 2 >sa0 >sa1
5564 5565
5631 5630f01 from 5630gat >sa0
5632 5630f02 from 5630gat >sa0
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5568 875
5634 5633f01 from 5633gat >sa0
5635 5633f02 from 5633gat >sa0
5636 5633f03 from 5633gat >sa0
5637 5637gat nor 1 2 >sa0
5508 5570
5638 5638gat nor 1 2 >sa0
5571 922
5639 5639gat nor 2 2 >sa0 >sa1
5396 5572
5640 5639f01 from 5639gat >sa0
5641 5639f02 from 5639gat >sa0
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5573 5574
5643 5642f01 from 5642gat >sa0
5644 5642f02 from 5642gat >sa0
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5579 5576
5646 5645f01 from 5645gat >sa0
5647 5645f02 from 5645gat >sa0
5648 5645f03 from 5645gat >sa0
5649 5649gat nor 1 2 >sa0
5521 5583
5650 5650gat nor 1 2 >sa0
5584 5518
5651 5651gat nor 2 2 >sa0 >sa1
5585 5586
5652 5651f01 from 5651gat >sa0
5653 5651f02 from 5651gat >sa0
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5589 1118
5655 5654f01 from 5654gat >sa0
5656 5654f02 from 5654gat >sa0
5657 5654f03 from 5654gat >sa0
5658 5658gat nor 1 2 >sa0
5529 5591
5659 5659gat nor 1 2 >sa0
5592 1165
5660 5660gat nor 2 2 >sa0 >sa1
5417 5593
5661 5660f01 from 5660gat >sa0
5662 5660f02 from 5660gat >sa0
5663 5663gat nor 2 2 >sa0 >sa1
5594 5595
5664 5663f01 from 5663gat >sa0
5665 5663f02 from 5663gat >sa0
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5600 5597
5667 5666f01 from 5666gat >sa0
5668 5666f02 from 5666gat >sa0
5669 5666f03 from 5666gat >sa0
5670 5670gat nor 1 2 >sa0
1310 5604
5671 5671gat nor 1 2 >sa0
5605 5539
5672 5672gat nor 0 2 >sa0 >sa1
5606 5607
5673 5673gat nor 2 2 >sa0 >sa1
5611 5612
5674 5673f01 from 5673gat >sa0
5675 5673f02 from 5673gat >sa0
5676 5676gat nor 2 2 >sa0 >sa1
5616 5617
5677 5676f01 from 5676gat >sa0
5678 5676f02 from 5676gat >sa0
5679 5679gat nor 3 2 >sa0 >sa1
5622 5619
5680 5679f01 from 5679gat >sa0
5681 5679f02 from 5679gat >sa0
5682 5679f03 from 5679gat >sa0
5683 5683gat nor 1 2 >sa0
5559 5626
5684 5684gat nor 1 2 >sa0
5627 5556
5685 5685gat nor 2 2 >sa0 >sa1
5628 5629
5686 5685f01 from 5685gat >sa0
5687 5685f02 from 5685gat >sa0
5688 5688gat nor 3 2 >sa0 >sa1
5632 827
5689 5688f01 from 5688gat >sa0
5690 5688f02 from 5688gat >sa0
5691 5688f03 from 5688gat >sa0
5692 5692gat nor 1 2 >sa0
5567 5634
5693 5693gat nor 1 2 >sa0
5635 874
5694 5694gat nor 2 2 >sa0 >sa1
5447 5636
5695 5694f01 from 5694gat >sa0
5696 5694f02 from 5694gat >sa0
5697 5697gat nor 2 2 >sa0 >sa1
5637 5638
5698 5697f01 from 5697gat >sa0
5699 5697f02 from 5697gat >sa0
5700 5700gat nor 3 2 >sa0 >sa1
5643 5640
5701 5700f01 from 5700gat >sa0
5702 5700f02 from 5700gat >sa0
5703 5700f03 from 5700gat >sa0
5704 5704gat nor 1 2 >sa0
5580 5647
5705 5705gat nor 1 2 >sa0
5648 5577
5706 5706gat nor 2 2 >sa0 >sa1
5649 5650
5707 5706f01 from 5706gat >sa0
5708 5706f02 from 5706gat >sa0
5709 5709gat nor 3 2 >sa0 >sa1
5653 1070
5710 5709f01 from 5709gat >sa0
5711 5709f02 from 5709gat >sa0
5712 5709f03 from 5709gat >sa0
5713 5713gat nor 1 2 >sa0
5588 5655
5714 5714gat nor 1 2 >sa0
5656 1117
5715 5715gat nor 2 2 >sa0 >sa1
5468 5657
5716 5715f01 from 5715gat >sa0
5717 5715f02 from 5715gat >sa0
5718 5718gat nor 2 2 >sa0 >sa1
5658 5659
5719 5718f01 from 5718gat >sa0
5720 5718f02 from 5718gat >sa0
5721 5721gat nor 3 2 >sa0 >sa1
5664 5661
5722 5721f01 from 5721gat >sa0
5723 5721f02 from 5721gat >sa0
5724 5721f03 from 5721gat >sa0
5725 5725gat nor 1 2 >sa0
5601 5668
5726 5726gat nor 1 2 >sa0
5669 5598
5727 5727gat nor 2 2 >sa0 >sa1
5670 5671
5728 5727f01 from 5727gat >sa0
5729 5727f02 from 5727gat >sa0
5730 5730gat nor 3 2 >sa0 >sa1
5674 5609
5731 5730f01 from 5730gat >sa0
5732 5730f02 from 5730gat >sa0
5733 5730f03 from 5730gat >sa0
5734 5734gat nor 3 2 >sa0 >sa1
5677 5614
5735 5734f01 from 5734gat >sa0
5736 5734f02 from 5734gat >sa0
5737 5734f03 from 5734gat >sa0
5738 5738gat nor 1 2 >sa0
5623 5681
5739 5739gat nor 1 2 >sa0
5682 5620
5740 5740gat nor 2 2 >sa0 >sa1
5683 5684
5741 5740f01 from 5740gat >sa0
5742 5740f02 from 5740gat >sa0
5743 5743gat nor 3 2 >sa0 >sa1
5687 779
5744 5743f01 from 5743gat >sa0
5745 5743f02 from 5743gat >sa0
5746 5743f03 from 5743gat >sa0
5747 5747gat nor 1 2 >sa0
5631 5689
5748 5748gat nor 1 2 >sa0
5690 826
5749 5749gat nor 2 2 >sa0 >sa1
5502 5691
5750 5749f01 from 5749gat >sa0
5751 5749f02 from 5749gat >sa0
5752 5752gat nor 2 2 >sa0 >sa1
5692 5693
5753 5752f01 from 5752gat >sa0
5754 5752f02 from 5752gat >sa0
5755 5755gat nor 3 2 >sa0 >sa1
5698 5695
5756 5755f01 from 5755gat >sa0
5757 5755f02 from 5755gat >sa0
5758 5755f03 from 5755gat >sa0
5759 5759gat nor 1 2 >sa0
5644 5702
5760 5760gat nor 1 2 >sa0
5703 5641
5761 5761gat nor 2 2 >sa0 >sa1
5704 5705
5762 5761f01 from 5761gat >sa0
5763 5761f02 from 5761gat >sa0
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5765 5764f01 from 5764gat >sa0
5766 5764f02 from 5764gat >sa0
5767 5764f03 from 5764gat >sa0
5768 5768gat nor 1 2 >sa0
5652 5710
5769 5769gat nor 1 2 >sa0
5711 1069
5770 5770gat nor 2 2 >sa0 >sa1
5523 5712
5771 5770f01 from 5770gat >sa0
5772 5770f02 from 5770gat >sa0
5773 5773gat nor 2 2 >sa0 >sa1
5713 5714
5774 5773f01 from 5773gat >sa0
5775 5773f02 from 5773gat >sa0
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5719 5716
5777 5776f01 from 5776gat >sa0
5778 5776f02 from 5776gat >sa0
5779 5776f03 from 5776gat >sa0
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5665 5723
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5724 5662
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5725 5726
5783 5782f01 from 5782gat >sa0
5784 5782f02 from 5782gat >sa0
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5675 5732
5786 5786gat nor 1 2 >sa0
5733 5610
5787 5787gat nor 1 2 >sa0
5678 5736
5788 5788gat nor 1 2 >sa0
5737 5615
5789 5789gat nor 2 2 >sa0 >sa1
5738 5739
5790 5789f01 from 5789gat >sa0
5791 5789f02 from 5789gat >sa0
5792 5792gat nor 3 2 >sa0 >sa1
5742 731
5793 5792f01 from 5792gat >sa0
5794 5792f02 from 5792gat >sa0
5795 5792f03 from 5792gat >sa0
5796 5796gat nor 1 2 >sa0
5686 5744
5797 5797gat nor 1 2 >sa0
5745 778
5798 5798gat nor 2 2 >sa0 >sa1
5561 5746
5799 5798f01 from 5798gat >sa0
5800 5798f02 from 5798gat >sa0
5801 5801gat nor 2 2 >sa0 >sa1
5747 5748
5802 5801f01 from 5801gat >sa0
5803 5801f02 from 5801gat >sa0
5804 5804gat nor 3 2 >sa0 >sa1
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5805 5804f01 from 5804gat >sa0
5806 5804f02 from 5804gat >sa0
5807 5804f03 from 5804gat >sa0
5808 5808gat nor 1 2 >sa0
5699 5757
5809 5809gat nor 1 2 >sa0
5758 5696
5810 5810gat nor 2 2 >sa0 >sa1
5759 5760
5811 5810f01 from 5810gat >sa0
5812 5810f02 from 5810gat >sa0
5813 5813gat nor 3 2 >sa0 >sa1
5763 974
5814 5813f01 from 5813gat >sa0
5815 5813f02 from 5813gat >sa0
5816 5813f03 from 5813gat >sa0
5817 5817gat nor 1 2 >sa0
5707 5765
5818 5818gat nor 1 2 >sa0
5766 1021
5819 5819gat nor 2 2 >sa0 >sa1
5582 5767
5820 5819f01 from 5819gat >sa0
5821 5819f02 from 5819gat >sa0
5822 5822gat nor 2 2 >sa0 >sa1
5768 5769
5823 5822f01 from 5822gat >sa0
5824 5822f02 from 5822gat >sa0
5825 5825gat nor 3 2 >sa0 >sa1
5774 5771
5826 5825f01 from 5825gat >sa0
5827 5825f02 from 5825gat >sa0
5828 5825f03 from 5825gat >sa0
5829 5829gat nor 1 2 >sa0
5720 5778
5830 5830gat nor 1 2 >sa0
5779 5717
5831 5831gat nor 2 2 >sa0 >sa1
5780 5781
5832 5831f01 from 5831gat >sa0
5833 5831f02 from 5831gat >sa0
5834 5834gat nor 2 2 >sa0 >sa1
5785 5786
5835 5834f01 from 5834gat >sa0
5836 5834f02 from 5834gat >sa0
5837 5837gat nor 2 2 >sa0 >sa1
5787 5788
5838 5837f01 from 5837gat >sa0
5839 5837f02 from 5837gat >sa0
5840 5840gat nor 3 2 >sa0 >sa1
5791 683
5841 5840f01 from 5840gat >sa0
5842 5840f02 from 5840gat >sa0
5843 5840f03 from 5840gat >sa0
5844 5844gat nor 1 2 >sa0
5741 5793
5845 5845gat nor 1 2 >sa0
5794 730
5846 5846gat nor 2 2 >sa0 >sa1
5625 5795
5847 5846f01 from 5846gat >sa0
5848 5846f02 from 5846gat >sa0
5849 5849gat nor 2 2 >sa0 >sa1
5796 5797
5850 5849f01 from 5849gat >sa0
5851 5849f02 from 5849gat >sa0
5852 5852gat nor 3 2 >sa0 >sa1
5802 5799
5853 5852f01 from 5852gat >sa0
5854 5852f02 from 5852gat >sa0
5855 5852f03 from 5852gat >sa0
5856 5856gat nor 1 2 >sa0
5754 5806
5857 5857gat nor 1 2 >sa0
5807 5751
5858 5858gat nor 2 2 >sa0 >sa1
5808 5809
5859 5858f01 from 5858gat >sa0
5860 5858f02 from 5858gat >sa0
5861 5861gat nor 3 2 >sa0 >sa1
5812 926
5862 5861f01 from 5861gat >sa0
5863 5861f02 from 5861gat >sa0
5864 5861f03 from 5861gat >sa0
5865 5865gat nor 1 2 >sa0
5762 5814
5866 5866gat nor 1 2 >sa0
5815 973
5867 5867gat nor 2 2 >sa0 >sa1
5646 5816
5868 5867f01 from 5867gat >sa0
5869 5867f02 from 5867gat >sa0
5870 5870gat nor 2 2 >sa0 >sa1
5817 5818
5871 5870f01 from 5870gat >sa0
5872 5870f02 from 5870gat >sa0
5873 5873gat nor 3 2 >sa0 >sa1
5823 5820
5874 5873f01 from 5873gat >sa0
5875 5873f02 from 5873gat >sa0
5876 5873f03 from 5873gat >sa0
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5775 5827
5878 5878gat nor 1 2 >sa0
5828 5772
5879 5879gat nor 2 2 >sa0 >sa1
5829 5830
5880 5879f01 from 5879gat >sa0
5881 5879f02 from 5879gat >sa0
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5836 587
5883 5882f01 from 5882gat >sa0
5884 5882f02 from 5882gat >sa0
5885 5882f03 from 5882gat >sa0
5886 5886gat nor 3 2 >sa0 >sa1
5839 635
5887 5886f01 from 5886gat >sa0
5888 5886f02 from 5886gat >sa0
5889 5886f03 from 5886gat >sa0
5890 5890gat nor 1 2 >sa0
5790 5841
5891 5891gat nor 1 2 >sa0
5842 682
5892 5892gat nor 2 2 >sa0 >sa1
5680 5843
5893 5892f01 from 5892gat >sa0
5894 5892f02 from 5892gat >sa0
5895 5895gat nor 2 2 >sa0 >sa1
5844 5845
5896 5895f01 from 5895gat >sa0
5897 5895f02 from 5895gat >sa0
5898 5898gat nor 3 2 >sa0 >sa1
5850 5847
5899 5898f01 from 5898gat >sa0
5900 5898f02 from 5898gat >sa0
5901 5898f03 from 5898gat >sa0
5902 5902gat nor 1 2 >sa0
5803 5854
5903 5903gat nor 1 2 >sa0
5855 5800
5904 5904gat nor 2 2 >sa0 >sa1
5856 5857
5905 5904f01 from 5904gat >sa0
5906 5904f02 from 5904gat >sa0
5907 5907gat nor 3 2 >sa0 >sa1
5860 878
5908 5907f01 from 5907gat >sa0
5909 5907f02 from 5907gat >sa0
5910 5907f03 from 5907gat >sa0
5911 5911gat nor 1 2 >sa0
5811 5862
5912 5912gat nor 1 2 >sa0
5863 925
5913 5913gat nor 2 2 >sa0 >sa1
5701 5864
5914 5913f01 from 5913gat >sa0
5915 5913f02 from 5913gat >sa0
5916 5916gat nor 2 2 >sa0 >sa1
5865 5866
5917 5916f01 from 5916gat >sa0
5918 5916f02 from 5916gat >sa0
5919 5919gat nor 3 2 >sa0 >sa1
5871 5868
5920 5919f01 from 5919gat >sa0
5921 5919f02 from 5919gat >sa0
5922 5919f03 from 5919gat >sa0
5923 5923gat nor 1 2 >sa0
5824 5875
5924 5924gat nor 1 2 >sa0
5876 5821
5925 5925gat nor 2 2 >sa0 >sa1
5877 5878
5926 5925f01 from 5925gat >sa0
5927 5925f02 from 5925gat >sa0
5928 5928gat nor 1 2 >sa0
5835 5883
5929 5929gat nor 1 2 >sa0
5884 586
5930 5930gat nor 2 2 >sa0 >sa1
5731 5885
5931 5930f01 from 5930gat >sa0
5932 5930f02 from 5930gat >sa0
5933 5933gat nor 1 2 >sa0
5838 5887
5934 5934gat nor 1 2 >sa0
5888 634
5935 5935gat nor 2 2 >sa0 >sa1
5735 5889
5936 5935f01 from 5935gat >sa0
5937 5935f02 from 5935gat >sa0
5938 5938gat nor 2 2 >sa0 >sa1
5890 5891
5939 5938f01 from 5938gat >sa0
5940 5938f02 from 5938gat >sa0
5941 5941gat nor 3 2 >sa0 >sa1
5896 5893
5942 5941f01 from 5941gat >sa0
5943 5941f02 from 5941gat >sa0
5944 5941f03 from 5941gat >sa0
5945 5945gat nor 1 2 >sa0
5851 5900
5946 5946gat nor 1 2 >sa0
5901 5848
5947 5947gat nor 2 2 >sa0 >sa1
5902 5903
5948 5947f01 from 5947gat >sa0
5949 5947f02 from 5947gat >sa0
5950 5950gat nor 3 2 >sa0 >sa1
5906 830
5951 5950f01 from 5950gat >sa0
5952 5950f02 from 5950gat >sa0
5953 5950f03 from 5950gat >sa0
5954 5954gat nor 1 2 >sa0
5859 5908
5955 5955gat nor 1 2 >sa0
5909 877
5956 5956gat nor 2 2 >sa0 >sa1
5756 5910
5957 5956f01 from 5956gat >sa0
5958 5956f02 from 5956gat >sa0
5959 5959gat nor 2 2 >sa0 >sa1
5911 5912
5960 5959f01 from 5959gat >sa0
5961 5959f02 from 5959gat >sa0
5962 5962gat nor 3 2 >sa0 >sa1
5917 5914
5963 5962f01 from 5962gat >sa0
5964 5962f02 from 5962gat >sa0
5965 5962f03 from 5962gat >sa0
5966 5966gat nor 1 2 >sa0
5872 5921
5967 5967gat nor 1 2 >sa0
5922 5869
5968 5968gat nor 2 2 >sa0 >sa1
5923 5924
5969 5968f01 from 5968gat >sa0
5970 5968f02 from 5968gat >sa0
5971 5971gat nor 0 2 >sa0 >sa1
5928 5929
5972 5972gat nor 2 2 >sa0 >sa1
5933 5934
5973 5972f01 from 5972gat >sa0
5974 5972f02 from 5972gat >sa0
5975 5975gat nor 3 2 >sa0 >sa1
5939 5936
5976 5975f01 from 5975gat >sa0
5977 5975f02 from 5975gat >sa0
5978 5975f03 from 5975gat >sa0
5979 5979gat nor 1 2 >sa0
5897 5943
5980 5980gat nor 1 2 >sa0
5944 5894
5981 5981gat nor 2 2 >sa0 >sa1
5945 5946
5982 5981f01 from 5981gat >sa0
5983 5981f02 from 5981gat >sa0
5984 5984gat nor 3 2 >sa0 >sa1
5949 782
5985 5984f01 from 5984gat >sa0
5986 5984f02 from 5984gat >sa0
5987 5984f03 from 5984gat >sa0
5988 5988gat nor 1 2 >sa0
5905 5951
5989 5989gat nor 1 2 >sa0
5952 829
5990 5990gat nor 2 2 >sa0 >sa1
5805 5953
5991 5990f01 from 5990gat >sa0
5992 5990f02 from 5990gat >sa0
5993 5993gat nor 2 2 >sa0 >sa1
5954 5955
5994 5993f01 from 5993gat >sa0
5995 5993f02 from 5993gat >sa0
5996 5996gat nor 3 2 >sa0 >sa1
5960 5957
5997 5996f01 from 5996gat >sa0
5998 5996f02 from 5996gat >sa0
5999 5996f03 from 5996gat >sa0
6000 6000gat nor 1 2 >sa0
5918 5964
6001 6001gat nor 1 2 >sa0
5965 5915
6002 6002gat nor 2 2 >sa0 >sa1
5966 5967
6003 6002f01 from 6002gat >sa0
6004 6002f02 from 6002gat >sa0
6005 6005gat nor 3 2 >sa0 >sa1
5973 5931
6006 6005f01 from 6005gat >sa0
6007 6005f02 from 6005gat >sa0
6008 6005f03 from 6005gat >sa0
6009 6009gat nor 1 2 >sa0
5940 5977
6010 6010gat nor 1 2 >sa0
5978 5937
6011 6011gat nor 2 2 >sa0 >sa1
5979 5980
6012 6011f01 from 6011gat >sa0
6013 6011f02 from 6011gat >sa0
6014 6014gat nor 3 2 >sa0 >sa1
5983 734
6015 6014f01 from 6014gat >sa0
6016 6014f02 from 6014gat >sa0
6017 6014f03 from 6014gat >sa0
6018 6018gat nor 1 2 >sa0
5948 5985
6019 6019gat nor 1 2 >sa0
5986 781
6020 6020gat nor 2 2 >sa0 >sa1
5853 5987
6021 6020f01 from 6020gat >sa0
6022 6020f02 from 6020gat >sa0
6023 6023gat nor 2 2 >sa0 >sa1
5988 5989
6024 6023f01 from 6023gat >sa0
6025 6023f02 from 6023gat >sa0
6026 6026gat nor 3 2 >sa0 >sa1
5994 5991
6027 6026f01 from 6026gat >sa0
6028 6026f02 from 6026gat >sa0
6029 6026f03 from 6026gat >sa0
6030 6030gat nor 1 2 >sa0
5961 5998
6031 6031gat nor 1 2 >sa0
5999 5958
6032 6032gat nor 2 2 >sa0 >sa1
6000 6001
6033 6032f01 from 6032gat >sa0
6034 6032f02 from 6032gat >sa0
6035 6035gat nor 1 2 >sa0
5974 6007
6036 6036gat nor 1 2 >sa0
6008 5932
6037 6037gat nor 2 2 >sa0 >sa1
6009 6010
6038 6037f01 from 6037gat >sa0
6039 6037f02 from 6037gat >sa0
6040 6040gat nor 3 2 >sa0 >sa1
6013 686
6041 6040f01 from 6040gat >sa0
6042 6040f02 from 6040gat >sa0
6043 6040f03 from 6040gat >sa0
6044 6044gat nor 1 2 >sa0
5982 6015
6045 6045gat nor 1 2 >sa0
6016 733
6046 6046gat nor 2 2 >sa0 >sa1
5899 6017
6047 6046f01 from 6046gat >sa0
6048 6046f02 from 6046gat >sa0
6049 6049gat nor 2 2 >sa0 >sa1
6018 6019
6050 6049f01 from 6049gat >sa0
6051 6049f02 from 6049gat >sa0
6052 6052gat nor 3 2 >sa0 >sa1
6024 6021
6053 6052f01 from 6052gat >sa0
6054 6052f02 from 6052gat >sa0
6055 6052f03 from 6052gat >sa0
6056 6056gat nor 1 2 >sa0
5995 6028
6057 6057gat nor 1 2 >sa0
6029 5992
6058 6058gat nor 2 2 >sa0 >sa1
6030 6031
6059 6058f01 from 6058gat >sa0
6060 6058f02 from 6058gat >sa0
6061 6061gat nor 2 2 >sa0 >sa1
6035 6036
6062 6061f01 from 6061gat >sa0
6063 6061f02 from 6061gat >sa0
6064 6064gat nor 3 2 >sa0 >sa1
6039 638
6065 6064f01 from 6064gat >sa0
6066 6064f02 from 6064gat >sa0
6067 6064f03 from 6064gat >sa0
6068 6068gat nor 1 2 >sa0
6012 6041
6069 6069gat nor 1 2 >sa0
6042 685
6070 6070gat nor 2 2 >sa0 >sa1
5942 6043
6071 6070f01 from 6070gat >sa0
6072 6070f02 from 6070gat >sa0
6073 6073gat nor 2 2 >sa0 >sa1
6044 6045
6074 6073f01 from 6073gat >sa0
6075 6073f02 from 6073gat >sa0
6076 6076gat nor 3 2 >sa0 >sa1
6050 6047
6077 6076f01 from 6076gat >sa0
6078 6076f02 from 6076gat >sa0
6079 6076f03 from 6076gat >sa0
6080 6080gat nor 1 2 >sa0
6025 6054
6081 6081gat nor 1 2 >sa0
6055 6022
6082 6082gat nor 2 2 >sa0 >sa1
6056 6057
6083 6082f01 from 6082gat >sa0
6084 6082f02 from 6082gat >sa0
6085 6085gat nor 3 2 >sa0 >sa1
6063 590
6086 6085f01 from 6085gat >sa0
6087 6085f02 from 6085gat >sa0
6088 6085f03 from 6085gat >sa0
6089 6089gat nor 1 2 >sa0
6038 6065
6090 6090gat nor 1 2 >sa0
6066 637
6091 6091gat nor 2 2 >sa0 >sa1
5976 6067
6092 6091f01 from 6091gat >sa0
6093 6091f02 from 6091gat >sa0
6094 6094gat nor 2 2 >sa0 >sa1
6068 6069
6095 6094f01 from 6094gat >sa0
6096 6094f02 from 6094gat >sa0
6097 6097gat nor 3 2 >sa0 >sa1
6074 6071
6098 6097f01 from 6097gat >sa0
6099 6097f02 from 6097gat >sa0
6100 6097f03 from 6097gat >sa0
6101 6101gat nor 1 2 >sa0
6051 6078
6102 6102gat nor 1 2 >sa0
6079 6048
6103 6103gat nor 2 2 >sa0 >sa1
6080 6081
6104 6103f01 from 6103gat >sa0
6105 6103f02 from 6103gat >sa0
6106 6106gat nor 1 2 >sa0
6062 6086
6107 6107gat nor 1 2 >sa0
6087 589
6108 6108gat nor 2 2 >sa0 >sa1
6006 6088
6109 6108f01 from 6108gat >sa0
6110 6108f02 from 6108gat >sa0
6111 6111gat nor 2 2 >sa0 >sa1
6089 6090
6112 6111f01 from 6111gat >sa0
6113 6111f02 from 6111gat >sa0
6114 6114gat nor 3 2 >sa0 >sa1
6095 6092
6115 6114f01 from 6114gat >sa0
6116 6114f02 from 6114gat >sa0
6117 6114f03 from 6114gat >sa0
6118 6118gat nor 1 2 >sa0
6075 6099
6119 6119gat nor 1 2 >sa0
6100 6072
6120 6120gat nor 2 2 >sa0 >sa1
6101 6102
6121 6120f01 from 6120gat >sa0
6122 6120f02 from 6120gat >sa0
6123 6123gat nor 0 2 >sa0 >sa1
6106 6107
6124 6124gat nor 3 2 >sa0 >sa1
6112 6109
6125 6124f01 from 6124gat >sa0
6126 6124f02 from 6124gat >sa0
6127 6124f03 from 6124gat >sa0
6128 6128gat nor 1 2 >sa0
6096 6116
6129 6129gat nor 1 2 >sa0
6117 6093
6130 6130gat nor 2 2 >sa0 >sa1
6118 6119
6131 6130f01 from 6130gat >sa0
6132 6130f02 from 6130gat >sa0
6133 6133gat nor 1 2 >sa0
6113 6126
6134 6134gat nor 1 2 >sa0
6127 6110
6135 6135gat nor 2 2 >sa0 >sa1
6128 6129
6136 6135f01 from 6135gat >sa0
6137 6135f02 from 6135gat >sa0
6138 6138gat nor 2 2 >sa0 >sa1
6133 6134
6139 6138f01 from 6138gat >sa0
6140 6138f02 from 6138gat
6141 6141gat not 3 1 >sa0 >sa1
6140
6142 6141f01 from 6141gat >sa0
6143 6141f02 from 6141gat
6144 6141f03 from 6141gat >sa0
6145 6145gat nor 1 2 >sa0
6139 6142
6146 6146gat not 1 1 >sa0
6143
6147 6147gat nor 2 2 >sa0 >sa1
6125 6144
6148 6147f01 from 6147gat >sa0
6149 6147f02 from 6147gat >sa0
6150 6150gat nor 0 2 >sa0 >sa1
6145 6146
6151 6151gat nor 3 2 >sa0 >sa1
6137 6149
6152 6151f01 from 6151gat >sa0
6153 6151f02 from 6151gat >sa0
6154 6151f03 from 6151gat >sa0
6155 6155gat nor 1 2 >sa0
6136 6152
6156 6156gat nor 1 2 >sa0
6153 6148
6157 6157gat nor 2 2 >sa0 >sa1
6115 6154
6158 6157f01 from 6157gat >sa0
6159 6157f02 from 6157gat >sa0
6160 6160gat nor 0 2 >sa0 >sa1
6155 6156
6161 6161gat nor 3 2 >sa0 >sa1
6132 6159
6162 6161f01 from 6161gat >sa0
6163 6161f02 from 6161gat >sa0
6164 6161f03 from 6161gat >sa0
6165 6165gat nor 1 2 >sa0
6131 6162
6166 6166gat nor 1 2 >sa0
6163 6158
6167 6167gat nor 2 2 >sa0 >sa1
6098 6164
6168 6167f01 from 6167gat >sa0
6169 6167f02 from 6167gat >sa0
6170 6170gat nor 0 2 >sa0 >sa1
6165 6166
6171 6171gat nor 3 2 >sa0 >sa1
6122 6169
6172 6171f01 from 6171gat >sa0
6173 6171f02 from 6171gat >sa0
6174 6171f03 from 6171gat >sa0
6175 6175gat nor 1 2 >sa0
6121 6172
6176 6176gat nor 1 2 >sa0
6173 6168
6177 6177gat nor 2 2 >sa0 >sa1
6077 6174
6178 6177f01 from 6177gat >sa0
6179 6177f02 from 6177gat >sa0
6180 6180gat nor 0 2 >sa0 >sa1
6175 6176
6181 6181gat nor 3 2 >sa0 >sa1
6105 6179
6182 6181f01 from 6181gat >sa0
6183 6181f02 from 6181gat >sa0
6184 6181f03 from 6181gat >sa0
6185 6185gat nor 1 2 >sa0
6104 6182
6186 6186gat nor 1 2 >sa0
6183 6178
6187 6187gat nor 2 2 >sa0 >sa1
6053 6184
6188 6187f01 from 6187gat >sa0
6189 6187f02 from 6187gat >sa0
6190 6190gat nor 0 2 >sa0 >sa1
6185 6186
6191 6191gat nor 3 2 >sa0 >sa1
6084 6189
6192 6191f01 from 6191gat >sa0
6193 6191f02 from 6191gat >sa0
6194 6191f03 from 6191gat >sa0
6195 6195gat nor 1 2 >sa0
6083 6192
6196 6196gat nor 1 2 >sa0
6193 6188
6197 6197gat nor 2 2 >sa0 >sa1
6027 6194
6198 6197f01 from 6197gat >sa0
6199 6197f02 from 6197gat >sa0
6200 6200gat nor 0 2 >sa0 >sa1
6195 6196
6201 6201gat nor 3 2 >sa0 >sa1
6060 6199
6202 6201f01 from 6201gat >sa0
6203 6201f02 from 6201gat >sa0
6204 6201f03 from 6201gat >sa0
6205 6205gat nor 1 2 >sa0
6059 6202
6206 6206gat nor 1 2 >sa0
6203 6198
6207 6207gat nor 2 2 >sa0 >sa1
5997 6204
6208 6207f01 from 6207gat >sa0
6209 6207f02 from 6207gat >sa0
6210 6210gat nor 0 2 >sa0 >sa1
6205 6206
6211 6211gat nor 3 2 >sa0 >sa1
6034 6209
6212 6211f01 from 6211gat >sa0
6213 6211f02 from 6211gat >sa0
6214 6211f03 from 6211gat >sa0
6215 6215gat nor 1 2 >sa0
6033 6212
6216 6216gat nor 1 2 >sa0
6213 6208
6217 6217gat nor 2 2 >sa0 >sa1
5963 6214
6218 6217f01 from 6217gat >sa0
6219 6217f02 from 6217gat >sa0
6220 6220gat nor 0 2 >sa0 >sa1
6215 6216
6221 6221gat nor 3 2 >sa0 >sa1
6004 6219
6222 6221f01 from 6221gat >sa0
6223 6221f02 from 6221gat >sa0
6224 6221f03 from 6221gat >sa0
6225 6225gat nor 1 2 >sa0
6003 6222
6226 6226gat nor 1 2 >sa0
6223 6218
6227 6227gat nor 2 2 >sa0 >sa1
5920 6224
6228 6227f01 from 6227gat >sa0
6229 6227f02 from 6227gat >sa0
6230 6230gat nor 0 2 >sa0 >sa1
6225 6226
6231 6231gat nor 3 2 >sa0 >sa1
5970 6229
6232 6231f01 from 6231gat >sa0
6233 6231f02 from 6231gat >sa0
6234 6231f03 from 6231gat >sa0
6235 6235gat nor 1 2 >sa0
5969 6232
6236 6236gat nor 1 2 >sa0
6233 6228
6237 6237gat nor 2 2 >sa0 >sa1
5874 6234
6238 6237f01 from 6237gat >sa0
6239 6237f02 from 6237gat >sa0
6240 6240gat nor 0 2 >sa0 >sa1
6235 6236
6241 6241gat nor 3 2 >sa0 >sa1
5927 6239
6242 6241f01 from 6241gat >sa0
6243 6241f02 from 6241gat >sa0
6244 6241f03 from 6241gat >sa0
6245 6245gat nor 1 2 >sa0
5926 6242
6246 6246gat nor 1 2 >sa0
6243 6238
6247 6247gat nor 2 2 >sa0 >sa1
5826 6244
6248 6247f01 from 6247gat >sa0
6249 6247f02 from 6247gat >sa0
6250 6250gat nor 0 2 >sa0 >sa1
6245 6246
6251 6251gat nor 3 2 >sa0 >sa1
5881 6249
6252 6251f01 from 6251gat >sa0
6253 6251f02 from 6251gat >sa0
6254 6251f03 from 6251gat >sa0
6255 6255gat nor 1 2 >sa0
5880 6252
6256 6256gat nor 1 2 >sa0
6253 6248
6257 6257gat nor 2 2 >sa0 >sa1
5777 6254
6258 6257f01 from 6257gat >sa0
6259 6257f02 from 6257gat >sa0
6260 6260gat nor 0 2 >sa0 >sa1
6255 6256
6261 6261gat nor 3 2 >sa0 >sa1
5833 6259
6262 6261f01 from 6261gat >sa0
6263 6261f02 from 6261gat >sa0
6264 6261f03 from 6261gat >sa0
6265 6265gat nor 1 2 >sa0
5832 6262
6266 6266gat nor 1 2 >sa0
6263 6258
6267 6267gat nor 2 2 >sa0 >sa1
5722 6264
6268 6267f01 from 6267gat >sa0
6269 6267f02 from 6267gat >sa0
6270 6270gat nor 0 2 >sa0 >sa1
6265 6266
6271 6271gat nor 3 2 >sa0 >sa1
5784 6269
6272 6271f01 from 6271gat >sa0
6273 6271f02 from 6271gat >sa0
6274 6271f03 from 6271gat >sa0
6275 6275gat nor 1 2 >sa0
5783 6272
6276 6276gat nor 1 2 >sa0
6273 6268
6277 6277gat nor 2 2 >sa0 >sa1
5667 6274
6278 6277f01 from 6277gat >sa0
6279 6277f02 from 6277gat >sa0
6280 6280gat nor 0 2 >sa0 >sa1
6275 6276
6281 6281gat nor 3 2 >sa0 >sa1
5729 6279
6282 6281f01 from 6281gat >sa0
6283 6281f02 from 6281gat >sa0
6284 6281f03 from 6281gat >sa0
6285 6285gat nor 1 2 >sa0
5728 6282
6286 6286gat nor 1 2 >sa0
6283 6278
6287 6287gat nor 0 2 >sa0 >sa1
5603 6284
6288 6288gat nor 0 2 >sa0 >sa1
6285 6286
|
Added c6288.tests.
> > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 | 01010101010101011111111111111111 10101010101010101111111111111111 01010101010101011101111111111111 10101010101010101101111111111111 11011011011011011111111111111111 01101101101101101111111111111111 10110110110110111111111111111111 11111111111111111101010101010101 11111111111111110110101010101010 11111111111111101101010101010101 11111111111111100110101010101010 11111111111111110000000000000000 |
Added c6288.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 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/****************************************************************************
* *
* VERILOG HIGH-LEVEL DESCRIPTION OF THE ISCAS-85 BENCHMARK CIRCUIT c6288 *
* *
* Function: 16 x 16 Multiplier *
* *
* Written by: Mark C. Hansen *
* *
* Last modified: Nov 12, 1997 *
* *
****************************************************************************/
module Circuit6288 (in256, in239, in222, in205, in188, in171, in154, in137,
in120, in103, in86, in69, in52, in35, in18, in1,
in528, in511, in494, in477, in460, in443, in426, in409,
in392, in375, in358, in341, in324, in307, in290, in273,
out6287, out6288, out6280, out6270,
out6260, out6250, out6240, out6230,
out6220, out6210, out6200, out6190,
out6180, out6170, out6160, out6150,
out6123, out5971, out5672, out5308,
out4946, out4591, out4241, out3895,
out3552, out3211, out2877, out2548,
out2223, out1901, out1581, out545);
input in256, in239, in222, in205, in188, in171, in154, in137,
in120, in103, in86, in69, in52, in35, in18, in1,
in528, in511, in494, in477, in460, in443, in426, in409,
in392, in375, in358, in341, in324, in307, in290, in273;
output out6287, out6288, out6280, out6270,
out6260, out6250, out6240, out6230,
out6220, out6210, out6200, out6190,
out6180, out6170, out6160, out6150,
out6123, out5971, out5672, out5308,
out4946, out4591, out4241, out3895,
out3552, out3211, out2877, out2548,
out2223, out1901, out1581, out545;
wire [15:0] A, B;
wire [31:0] P;
assign
A[15:0] = {in256, in239, in222, in205, in188, in171, in154, in137,
in120, in103, in86, in69, in52, in35, in18, in1},
B[15:0] = {in528, in511, in494, in477, in460, in443, in426, in409,
in392, in375, in358, in341, in324, in307, in290, in273},
{out6287, out6288, out6280, out6270,
out6260, out6250, out6240, out6230,
out6220, out6210, out6200, out6190,
out6180, out6170, out6160, out6150,
out6123, out5971, out5672, out5308,
out4946, out4591, out4241, out3895,
out3552, out3211, out2877, out2548,
out2223, out1901, out1581, out545} = P[31:0];
TopLevel6288 Ckt6288 (A, B, P);
endmodule /* Circuit6288 */
/*************************************************************************/
module TopLevel6288 (A, B, P);
input[15:0] A, B;
output[31:0] P;
wire C14_15, S14_15, S13_15, S12_15,
S11_15, S10_15, S9_15, S8_15,
S7_15, S6_15, S5_15, S4_15,
S3_15, S2_15, S1_15, S0_15,
S0_14, S0_13, S0_12, S0_11,
S0_10, S0_9, S0_8, S0_7,
S0_6, S0_5, S0_4, S0_3,
S0_2, S0_1, S0_0, A0B0;
assign
P[31:0] = {C14_15, S14_15, S13_15, S12_15,
S11_15, S10_15, S9_15, S8_15,
S7_15, S6_15, S5_15, S4_15,
S3_15, S2_15, S1_15, S0_15,
S0_14, S0_13, S0_12, S0_11,
S0_10, S0_9, S0_8, S0_7,
S0_6, S0_5, S0_4, S0_3,
S0_2, S0_1, S0_0, A0B0};
and GA0B0(A0B0, A[0], B[0]);
and GA0B1(A0B1, A[0], B[1]);
and GA0B2(A0B2, A[0], B[2]);
and GA0B3(A0B3, A[0], B[3]);
and GA0B4(A0B4, A[0], B[4]);
and GA0B5(A0B5, A[0], B[5]);
and GA0B6(A0B6, A[0], B[6]);
and GA0B7(A0B7, A[0], B[7]);
and GA0B8(A0B8, A[0], B[8]);
and GA0B9(A0B9, A[0], B[9]);
and GA0B10(A0B10, A[0], B[10]);
and GA0B11(A0B11, A[0], B[11]);
and GA0B12(A0B12, A[0], B[12]);
and GA0B13(A0B13, A[0], B[13]);
and GA0B14(A0B14, A[0], B[14]);
and GA0B15(A0B15, A[0], B[15]);
and GA1B0(A1B0, A[1], B[0]);
and GA1B1(A1B1, A[1], B[1]);
and GA1B2(A1B2, A[1], B[2]);
and GA1B3(A1B3, A[1], B[3]);
and GA1B4(A1B4, A[1], B[4]);
and GA1B5(A1B5, A[1], B[5]);
and GA1B6(A1B6, A[1], B[6]);
and GA1B7(A1B7, A[1], B[7]);
and GA1B8(A1B8, A[1], B[8]);
and GA1B9(A1B9, A[1], B[9]);
and GA1B10(A1B10, A[1], B[10]);
and GA1B11(A1B11, A[1], B[11]);
and GA1B12(A1B12, A[1], B[12]);
and GA1B13(A1B13, A[1], B[13]);
and GA1B14(A1B14, A[1], B[14]);
and GA1B15(A1B15, A[1], B[15]);
and GA2B0(A2B0, A[2], B[0]);
and GA2B1(A2B1, A[2], B[1]);
and GA2B2(A2B2, A[2], B[2]);
and GA2B3(A2B3, A[2], B[3]);
and GA2B4(A2B4, A[2], B[4]);
and GA2B5(A2B5, A[2], B[5]);
and GA2B6(A2B6, A[2], B[6]);
and GA2B7(A2B7, A[2], B[7]);
and GA2B8(A2B8, A[2], B[8]);
and GA2B9(A2B9, A[2], B[9]);
and GA2B10(A2B10, A[2], B[10]);
and GA2B11(A2B11, A[2], B[11]);
and GA2B12(A2B12, A[2], B[12]);
and GA2B13(A2B13, A[2], B[13]);
and GA2B14(A2B14, A[2], B[14]);
and GA2B15(A2B15, A[2], B[15]);
and GA3B0(A3B0, A[3], B[0]);
and GA3B1(A3B1, A[3], B[1]);
and GA3B2(A3B2, A[3], B[2]);
and GA3B3(A3B3, A[3], B[3]);
and GA3B4(A3B4, A[3], B[4]);
and GA3B5(A3B5, A[3], B[5]);
and GA3B6(A3B6, A[3], B[6]);
and GA3B7(A3B7, A[3], B[7]);
and GA3B8(A3B8, A[3], B[8]);
and GA3B9(A3B9, A[3], B[9]);
and GA3B10(A3B10, A[3], B[10]);
and GA3B11(A3B11, A[3], B[11]);
and GA3B12(A3B12, A[3], B[12]);
and GA3B13(A3B13, A[3], B[13]);
and GA3B14(A3B14, A[3], B[14]);
and GA3B15(A3B15, A[3], B[15]);
and GA4B0(A4B0, A[4], B[0]);
and GA4B1(A4B1, A[4], B[1]);
and GA4B2(A4B2, A[4], B[2]);
and GA4B3(A4B3, A[4], B[3]);
and GA4B4(A4B4, A[4], B[4]);
and GA4B5(A4B5, A[4], B[5]);
and GA4B6(A4B6, A[4], B[6]);
and GA4B7(A4B7, A[4], B[7]);
and GA4B8(A4B8, A[4], B[8]);
and GA4B9(A4B9, A[4], B[9]);
and GA4B10(A4B10, A[4], B[10]);
and GA4B11(A4B11, A[4], B[11]);
and GA4B12(A4B12, A[4], B[12]);
and GA4B13(A4B13, A[4], B[13]);
and GA4B14(A4B14, A[4], B[14]);
and GA4B15(A4B15, A[4], B[15]);
and GA5B0(A5B0, A[5], B[0]);
and GA5B1(A5B1, A[5], B[1]);
and GA5B2(A5B2, A[5], B[2]);
and GA5B3(A5B3, A[5], B[3]);
and GA5B4(A5B4, A[5], B[4]);
and GA5B5(A5B5, A[5], B[5]);
and GA5B6(A5B6, A[5], B[6]);
and GA5B7(A5B7, A[5], B[7]);
and GA5B8(A5B8, A[5], B[8]);
and GA5B9(A5B9, A[5], B[9]);
and GA5B10(A5B10, A[5], B[10]);
and GA5B11(A5B11, A[5], B[11]);
and GA5B12(A5B12, A[5], B[12]);
and GA5B13(A5B13, A[5], B[13]);
and GA5B14(A5B14, A[5], B[14]);
and GA5B15(A5B15, A[5], B[15]);
and GA6B0(A6B0, A[6], B[0]);
and GA6B1(A6B1, A[6], B[1]);
and GA6B2(A6B2, A[6], B[2]);
and GA6B3(A6B3, A[6], B[3]);
and GA6B4(A6B4, A[6], B[4]);
and GA6B5(A6B5, A[6], B[5]);
and GA6B6(A6B6, A[6], B[6]);
and GA6B7(A6B7, A[6], B[7]);
and GA6B8(A6B8, A[6], B[8]);
and GA6B9(A6B9, A[6], B[9]);
and GA6B10(A6B10, A[6], B[10]);
and GA6B11(A6B11, A[6], B[11]);
and GA6B12(A6B12, A[6], B[12]);
and GA6B13(A6B13, A[6], B[13]);
and GA6B14(A6B14, A[6], B[14]);
and GA6B15(A6B15, A[6], B[15]);
and GA7B0(A7B0, A[7], B[0]);
and GA7B1(A7B1, A[7], B[1]);
and GA7B2(A7B2, A[7], B[2]);
and GA7B3(A7B3, A[7], B[3]);
and GA7B4(A7B4, A[7], B[4]);
and GA7B5(A7B5, A[7], B[5]);
and GA7B6(A7B6, A[7], B[6]);
and GA7B7(A7B7, A[7], B[7]);
and GA7B8(A7B8, A[7], B[8]);
and GA7B9(A7B9, A[7], B[9]);
and GA7B10(A7B10, A[7], B[10]);
and GA7B11(A7B11, A[7], B[11]);
and GA7B12(A7B12, A[7], B[12]);
and GA7B13(A7B13, A[7], B[13]);
and GA7B14(A7B14, A[7], B[14]);
and GA7B15(A7B15, A[7], B[15]);
and GA8B0(A8B0, A[8], B[0]);
and GA8B1(A8B1, A[8], B[1]);
and GA8B2(A8B2, A[8], B[2]);
and GA8B3(A8B3, A[8], B[3]);
and GA8B4(A8B4, A[8], B[4]);
and GA8B5(A8B5, A[8], B[5]);
and GA8B6(A8B6, A[8], B[6]);
and GA8B7(A8B7, A[8], B[7]);
and GA8B8(A8B8, A[8], B[8]);
and GA8B9(A8B9, A[8], B[9]);
and GA8B10(A8B10, A[8], B[10]);
and GA8B11(A8B11, A[8], B[11]);
and GA8B12(A8B12, A[8], B[12]);
and GA8B13(A8B13, A[8], B[13]);
and GA8B14(A8B14, A[8], B[14]);
and GA8B15(A8B15, A[8], B[15]);
and GA9B0(A9B0, A[9], B[0]);
and GA9B1(A9B1, A[9], B[1]);
and GA9B2(A9B2, A[9], B[2]);
and GA9B3(A9B3, A[9], B[3]);
and GA9B4(A9B4, A[9], B[4]);
and GA9B5(A9B5, A[9], B[5]);
and GA9B6(A9B6, A[9], B[6]);
and GA9B7(A9B7, A[9], B[7]);
and GA9B8(A9B8, A[9], B[8]);
and GA9B9(A9B9, A[9], B[9]);
and GA9B10(A9B10, A[9], B[10]);
and GA9B11(A9B11, A[9], B[11]);
and GA9B12(A9B12, A[9], B[12]);
and GA9B13(A9B13, A[9], B[13]);
and GA9B14(A9B14, A[9], B[14]);
and GA9B15(A9B15, A[9], B[15]);
and GA10B0(A10B0, A[10], B[0]);
and GA10B1(A10B1, A[10], B[1]);
and GA10B2(A10B2, A[10], B[2]);
and GA10B3(A10B3, A[10], B[3]);
and GA10B4(A10B4, A[10], B[4]);
and GA10B5(A10B5, A[10], B[5]);
and GA10B6(A10B6, A[10], B[6]);
and GA10B7(A10B7, A[10], B[7]);
and GA10B8(A10B8, A[10], B[8]);
and GA10B9(A10B9, A[10], B[9]);
and GA10B10(A10B10, A[10], B[10]);
and GA10B11(A10B11, A[10], B[11]);
and GA10B12(A10B12, A[10], B[12]);
and GA10B13(A10B13, A[10], B[13]);
and GA10B14(A10B14, A[10], B[14]);
and GA10B15(A10B15, A[10], B[15]);
and GA11B0(A11B0, A[11], B[0]);
and GA11B1(A11B1, A[11], B[1]);
and GA11B2(A11B2, A[11], B[2]);
and GA11B3(A11B3, A[11], B[3]);
and GA11B4(A11B4, A[11], B[4]);
and GA11B5(A11B5, A[11], B[5]);
and GA11B6(A11B6, A[11], B[6]);
and GA11B7(A11B7, A[11], B[7]);
and GA11B8(A11B8, A[11], B[8]);
and GA11B9(A11B9, A[11], B[9]);
and GA11B10(A11B10, A[11], B[10]);
and GA11B11(A11B11, A[11], B[11]);
and GA11B12(A11B12, A[11], B[12]);
and GA11B13(A11B13, A[11], B[13]);
and GA11B14(A11B14, A[11], B[14]);
and GA11B15(A11B15, A[11], B[15]);
and GA12B0(A12B0, A[12], B[0]);
and GA12B1(A12B1, A[12], B[1]);
and GA12B2(A12B2, A[12], B[2]);
and GA12B3(A12B3, A[12], B[3]);
and GA12B4(A12B4, A[12], B[4]);
and GA12B5(A12B5, A[12], B[5]);
and GA12B6(A12B6, A[12], B[6]);
and GA12B7(A12B7, A[12], B[7]);
and GA12B8(A12B8, A[12], B[8]);
and GA12B9(A12B9, A[12], B[9]);
and GA12B10(A12B10, A[12], B[10]);
and GA12B11(A12B11, A[12], B[11]);
and GA12B12(A12B12, A[12], B[12]);
and GA12B13(A12B13, A[12], B[13]);
and GA12B14(A12B14, A[12], B[14]);
and GA12B15(A12B15, A[12], B[15]);
and GA13B0(A13B0, A[13], B[0]);
and GA13B1(A13B1, A[13], B[1]);
and GA13B2(A13B2, A[13], B[2]);
and GA13B3(A13B3, A[13], B[3]);
and GA13B4(A13B4, A[13], B[4]);
and GA13B5(A13B5, A[13], B[5]);
and GA13B6(A13B6, A[13], B[6]);
and GA13B7(A13B7, A[13], B[7]);
and GA13B8(A13B8, A[13], B[8]);
and GA13B9(A13B9, A[13], B[9]);
and GA13B10(A13B10, A[13], B[10]);
and GA13B11(A13B11, A[13], B[11]);
and GA13B12(A13B12, A[13], B[12]);
and GA13B13(A13B13, A[13], B[13]);
and GA13B14(A13B14, A[13], B[14]);
and GA13B15(A13B15, A[13], B[15]);
and GA14B0(A14B0, A[14], B[0]);
and GA14B1(A14B1, A[14], B[1]);
and GA14B2(A14B2, A[14], B[2]);
and GA14B3(A14B3, A[14], B[3]);
and GA14B4(A14B4, A[14], B[4]);
and GA14B5(A14B5, A[14], B[5]);
and GA14B6(A14B6, A[14], B[6]);
and GA14B7(A14B7, A[14], B[7]);
and GA14B8(A14B8, A[14], B[8]);
and GA14B9(A14B9, A[14], B[9]);
and GA14B10(A14B10, A[14], B[10]);
and GA14B11(A14B11, A[14], B[11]);
and GA14B12(A14B12, A[14], B[12]);
and GA14B13(A14B13, A[14], B[13]);
and GA14B14(A14B14, A[14], B[14]);
and GA14B15(A14B15, A[14], B[15]);
and GA15B0(A15B0, A[15], B[0]);
and GA15B1(A15B1, A[15], B[1]);
and GA15B2(A15B2, A[15], B[2]);
and GA15B3(A15B3, A[15], B[3]);
and GA15B4(A15B4, A[15], B[4]);
and GA15B5(A15B5, A[15], B[5]);
and GA15B6(A15B6, A[15], B[6]);
and GA15B7(A15B7, A[15], B[7]);
and GA15B8(A15B8, A[15], B[8]);
and GA15B9(A15B9, A[15], B[9]);
and GA15B10(A15B10, A[15], B[10]);
and GA15B11(A15B11, A[15], B[11]);
and GA15B12(A15B12, A[15], B[12]);
and GA15B13(A15B13, A[15], B[13]);
and GA15B14(A15B14, A[15], B[14]);
and GA15B15(A15B15, A[15], B[15]);
/* HA MHA0_0(S0_0,C0_0,A1B0,A0B1); */
not gn1_0_0(n1_0_0, A1B0);
not gn2_0_0(n2_0_0, n1_0_0);
nor gn3_0_0(n3_0_0, A1B0, n1_0_0);
nor gn4_0_0(n4_0_0, n2_0_0, n3_0_0);
nor gn5_0_0(n5_0_0, A0B1, n4_0_0);
nor gn6_0_0(n6_0_0, A0B1, n5_0_0);
nor gn7_0_0(n7_0_0, n4_0_0, n5_0_0);
nor gn8_0_0(S0_0, n6_0_0, n7_0_0);
nor gn9_0_0(C0_0, n1_0_0, n5_0_0);
/* HA MHA1_0(S1_0,C1_0,A2B0,A1B1); */
not gn1_1_0(n1_1_0, A2B0);
not gn2_1_0(n2_1_0, n1_1_0);
nor gn3_1_0(n3_1_0, A2B0, n1_1_0);
nor gn4_1_0(n4_1_0, n2_1_0, n3_1_0);
nor gn5_1_0(n5_1_0, A1B1, n4_1_0);
nor gn6_1_0(n6_1_0, A1B1, n5_1_0);
nor gn7_1_0(n7_1_0, n4_1_0, n5_1_0);
nor gn8_1_0(S1_0, n6_1_0, n7_1_0);
nor gn9_1_0(C1_0, n1_1_0, n5_1_0);
/* HA MHA2_0(S2_0,C2_0,A3B0,A2B1); */
not gn1_2_0(n1_2_0, A3B0);
not gn2_2_0(n2_2_0, n1_2_0);
nor gn3_2_0(n3_2_0, A3B0, n1_2_0);
nor gn4_2_0(n4_2_0, n2_2_0, n3_2_0);
nor gn5_2_0(n5_2_0, A2B1, n4_2_0);
nor gn6_2_0(n6_2_0, A2B1, n5_2_0);
nor gn7_2_0(n7_2_0, n4_2_0, n5_2_0);
nor gn8_2_0(S2_0, n6_2_0, n7_2_0);
nor gn9_2_0(C2_0, n1_2_0, n5_2_0);
/* HA MHA3_0(S3_0,C3_0,A4B0,A3B1); */
not gn1_3_0(n1_3_0, A4B0);
not gn2_3_0(n2_3_0, n1_3_0);
nor gn3_3_0(n3_3_0, A4B0, n1_3_0);
nor gn4_3_0(n4_3_0, n2_3_0, n3_3_0);
nor gn5_3_0(n5_3_0, A3B1, n4_3_0);
nor gn6_3_0(n6_3_0, A3B1, n5_3_0);
nor gn7_3_0(n7_3_0, n4_3_0, n5_3_0);
nor gn8_3_0(S3_0, n6_3_0, n7_3_0);
nor gn9_3_0(C3_0, n1_3_0, n5_3_0);
/* HA MHA4_0(S4_0,C4_0,A5B0,A4B1); */
not gn1_4_0(n1_4_0, A5B0);
not gn2_4_0(n2_4_0, n1_4_0);
nor gn3_4_0(n3_4_0, A5B0, n1_4_0);
nor gn4_4_0(n4_4_0, n2_4_0, n3_4_0);
nor gn5_4_0(n5_4_0, A4B1, n4_4_0);
nor gn6_4_0(n6_4_0, A4B1, n5_4_0);
nor gn7_4_0(n7_4_0, n4_4_0, n5_4_0);
nor gn8_4_0(S4_0, n6_4_0, n7_4_0);
nor gn9_4_0(C4_0, n1_4_0, n5_4_0);
/* HA MHA5_0(S5_0,C5_0,A6B0,A5B1); */
not gn1_5_0(n1_5_0, A6B0);
not gn2_5_0(n2_5_0, n1_5_0);
nor gn3_5_0(n3_5_0, A6B0, n1_5_0);
nor gn4_5_0(n4_5_0, n2_5_0, n3_5_0);
nor gn5_5_0(n5_5_0, A5B1, n4_5_0);
nor gn6_5_0(n6_5_0, A5B1, n5_5_0);
nor gn7_5_0(n7_5_0, n4_5_0, n5_5_0);
nor gn8_5_0(S5_0, n6_5_0, n7_5_0);
nor gn9_5_0(C5_0, n1_5_0, n5_5_0);
/* HA MHA6_0(S6_0,C6_0,A7B0,A6B1); */
not gn1_6_0(n1_6_0, A7B0);
not gn2_6_0(n2_6_0, n1_6_0);
nor gn3_6_0(n3_6_0, A7B0, n1_6_0);
nor gn4_6_0(n4_6_0, n2_6_0, n3_6_0);
nor gn5_6_0(n5_6_0, A6B1, n4_6_0);
nor gn6_6_0(n6_6_0, A6B1, n5_6_0);
nor gn7_6_0(n7_6_0, n4_6_0, n5_6_0);
nor gn8_6_0(S6_0, n6_6_0, n7_6_0);
nor gn9_6_0(C6_0, n1_6_0, n5_6_0);
/* HA MHA7_0(S7_0,C7_0,A8B0,A7B1); */
not gn1_7_0(n1_7_0, A8B0);
not gn2_7_0(n2_7_0, n1_7_0);
nor gn3_7_0(n3_7_0, A8B0, n1_7_0);
nor gn4_7_0(n4_7_0, n2_7_0, n3_7_0);
nor gn5_7_0(n5_7_0, A7B1, n4_7_0);
nor gn6_7_0(n6_7_0, A7B1, n5_7_0);
nor gn7_7_0(n7_7_0, n4_7_0, n5_7_0);
nor gn8_7_0(S7_0, n6_7_0, n7_7_0);
nor gn9_7_0(C7_0, n1_7_0, n5_7_0);
/* HA MHA8_0(S8_0,C8_0,A9B0,A8B1); */
not gn1_8_0(n1_8_0, A9B0);
not gn2_8_0(n2_8_0, n1_8_0);
nor gn3_8_0(n3_8_0, A9B0, n1_8_0);
nor gn4_8_0(n4_8_0, n2_8_0, n3_8_0);
nor gn5_8_0(n5_8_0, A8B1, n4_8_0);
nor gn6_8_0(n6_8_0, A8B1, n5_8_0);
nor gn7_8_0(n7_8_0, n4_8_0, n5_8_0);
nor gn8_8_0(S8_0, n6_8_0, n7_8_0);
nor gn9_8_0(C8_0, n1_8_0, n5_8_0);
/* HA MHA9_0(S9_0,C9_0,A10B0,A9B1); */
not gn1_9_0(n1_9_0, A10B0);
not gn2_9_0(n2_9_0, n1_9_0);
nor gn3_9_0(n3_9_0, A10B0, n1_9_0);
nor gn4_9_0(n4_9_0, n2_9_0, n3_9_0);
nor gn5_9_0(n5_9_0, A9B1, n4_9_0);
nor gn6_9_0(n6_9_0, A9B1, n5_9_0);
nor gn7_9_0(n7_9_0, n4_9_0, n5_9_0);
nor gn8_9_0(S9_0, n6_9_0, n7_9_0);
nor gn9_9_0(C9_0, n1_9_0, n5_9_0);
/* HA MHA10_0(S10_0,C10_0,A11B0,A10B1); */
not gn1_10_0(n1_10_0, A11B0);
not gn2_10_0(n2_10_0, n1_10_0);
nor gn3_10_0(n3_10_0, A11B0, n1_10_0);
nor gn4_10_0(n4_10_0, n2_10_0, n3_10_0);
nor gn5_10_0(n5_10_0, A10B1, n4_10_0);
nor gn6_10_0(n6_10_0, A10B1, n5_10_0);
nor gn7_10_0(n7_10_0, n4_10_0, n5_10_0);
nor gn8_10_0(S10_0, n6_10_0, n7_10_0);
nor gn9_10_0(C10_0, n1_10_0, n5_10_0);
/* HA MHA11_0(S11_0,C11_0,A12B0,A11B1); */
not gn1_11_0(n1_11_0, A12B0);
not gn2_11_0(n2_11_0, n1_11_0);
nor gn3_11_0(n3_11_0, A12B0, n1_11_0);
nor gn4_11_0(n4_11_0, n2_11_0, n3_11_0);
nor gn5_11_0(n5_11_0, A11B1, n4_11_0);
nor gn6_11_0(n6_11_0, A11B1, n5_11_0);
nor gn7_11_0(n7_11_0, n4_11_0, n5_11_0);
nor gn8_11_0(S11_0, n6_11_0, n7_11_0);
nor gn9_11_0(C11_0, n1_11_0, n5_11_0);
/* HA MHA12_0(S12_0,C12_0,A13B0,A12B1); */
not gn1_12_0(n1_12_0, A13B0);
not gn2_12_0(n2_12_0, n1_12_0);
nor gn3_12_0(n3_12_0, A13B0, n1_12_0);
nor gn4_12_0(n4_12_0, n2_12_0, n3_12_0);
nor gn5_12_0(n5_12_0, A12B1, n4_12_0);
nor gn6_12_0(n6_12_0, A12B1, n5_12_0);
nor gn7_12_0(n7_12_0, n4_12_0, n5_12_0);
nor gn8_12_0(S12_0, n6_12_0, n7_12_0);
nor gn9_12_0(C12_0, n1_12_0, n5_12_0);
/* HA MHA13_0(S13_0,C13_0,A14B0,A13B1); */
not gn1_13_0(n1_13_0, A14B0);
not gn2_13_0(n2_13_0, n1_13_0);
nor gn3_13_0(n3_13_0, A14B0, n1_13_0);
nor gn4_13_0(n4_13_0, n2_13_0, n3_13_0);
nor gn5_13_0(n5_13_0, A13B1, n4_13_0);
nor gn6_13_0(n6_13_0, A13B1, n5_13_0);
nor gn7_13_0(n7_13_0, n4_13_0, n5_13_0);
nor gn8_13_0(S13_0, n6_13_0, n7_13_0);
nor gn9_13_0(C13_0, n1_13_0, n5_13_0);
/* HA MHA14_0(S14_0,C14_0,A15B0,A14B1); */
not gn1_14_0(n1_14_0, A15B0);
not gn2_14_0(n2_14_0, n1_14_0);
nor gn3_14_0(n3_14_0, A15B0, n1_14_0);
nor gn4_14_0(n4_14_0, n2_14_0, n3_14_0);
nor gn5_14_0(n5_14_0, A14B1, n4_14_0);
nor gn6_14_0(n6_14_0, A14B1, n5_14_0);
nor gn7_14_0(n7_14_0, n4_14_0, n5_14_0);
nor gn8_14_0(S14_0, n6_14_0, n7_14_0);
nor gn9_14_0(C14_0, n1_14_0, n5_14_0);
/* FA MFA0_1(S0_1,C0_1,S1_0,C0_0,A0B2); */
nor gn1_0_1(n1_0_1, S1_0, C0_0);
nor gn2_0_1(n2_0_1, n1_0_1, C0_0);
nor gn3_0_1(n3_0_1, S1_0, n1_0_1);
nor gn4_0_1(n4_0_1, n2_0_1, n3_0_1);
nor gn5_0_1(n5_0_1, A0B2, n4_0_1);
nor gn6_0_1(n6_0_1, A0B2, n5_0_1);
nor gn7_0_1(n7_0_1, n4_0_1, n5_0_1);
nor gn8_0_1(S0_1, n6_0_1, n7_0_1);
nor gn9_0_1(C0_1, n1_0_1, n5_0_1);
/* FA MFA1_1(S1_1,C1_1,S2_0,C1_0,A1B2); */
nor gn1_1_1(n1_1_1, S2_0, C1_0);
nor gn2_1_1(n2_1_1, n1_1_1, C1_0);
nor gn3_1_1(n3_1_1, S2_0, n1_1_1);
nor gn4_1_1(n4_1_1, n2_1_1, n3_1_1);
nor gn5_1_1(n5_1_1, A1B2, n4_1_1);
nor gn6_1_1(n6_1_1, A1B2, n5_1_1);
nor gn7_1_1(n7_1_1, n4_1_1, n5_1_1);
nor gn8_1_1(S1_1, n6_1_1, n7_1_1);
nor gn9_1_1(C1_1, n1_1_1, n5_1_1);
/* FA MFA2_1(S2_1,C2_1,S3_0,C2_0,A2B2); */
nor gn1_2_1(n1_2_1, S3_0, C2_0);
nor gn2_2_1(n2_2_1, n1_2_1, C2_0);
nor gn3_2_1(n3_2_1, S3_0, n1_2_1);
nor gn4_2_1(n4_2_1, n2_2_1, n3_2_1);
nor gn5_2_1(n5_2_1, A2B2, n4_2_1);
nor gn6_2_1(n6_2_1, A2B2, n5_2_1);
nor gn7_2_1(n7_2_1, n4_2_1, n5_2_1);
nor gn8_2_1(S2_1, n6_2_1, n7_2_1);
nor gn9_2_1(C2_1, n1_2_1, n5_2_1);
/* FA MFA3_1(S3_1,C3_1,S4_0,C3_0,A3B2); */
nor gn1_3_1(n1_3_1, S4_0, C3_0);
nor gn2_3_1(n2_3_1, n1_3_1, C3_0);
nor gn3_3_1(n3_3_1, S4_0, n1_3_1);
nor gn4_3_1(n4_3_1, n2_3_1, n3_3_1);
nor gn5_3_1(n5_3_1, A3B2, n4_3_1);
nor gn6_3_1(n6_3_1, A3B2, n5_3_1);
nor gn7_3_1(n7_3_1, n4_3_1, n5_3_1);
nor gn8_3_1(S3_1, n6_3_1, n7_3_1);
nor gn9_3_1(C3_1, n1_3_1, n5_3_1);
/* FA MFA4_1(S4_1,C4_1,S5_0,C4_0,A4B2); */
nor gn1_4_1(n1_4_1, S5_0, C4_0);
nor gn2_4_1(n2_4_1, n1_4_1, C4_0);
nor gn3_4_1(n3_4_1, S5_0, n1_4_1);
nor gn4_4_1(n4_4_1, n2_4_1, n3_4_1);
nor gn5_4_1(n5_4_1, A4B2, n4_4_1);
nor gn6_4_1(n6_4_1, A4B2, n5_4_1);
nor gn7_4_1(n7_4_1, n4_4_1, n5_4_1);
nor gn8_4_1(S4_1, n6_4_1, n7_4_1);
nor gn9_4_1(C4_1, n1_4_1, n5_4_1);
/* FA MFA5_1(S5_1,C5_1,S6_0,C5_0,A5B2); */
nor gn1_5_1(n1_5_1, S6_0, C5_0);
nor gn2_5_1(n2_5_1, n1_5_1, C5_0);
nor gn3_5_1(n3_5_1, S6_0, n1_5_1);
nor gn4_5_1(n4_5_1, n2_5_1, n3_5_1);
nor gn5_5_1(n5_5_1, A5B2, n4_5_1);
nor gn6_5_1(n6_5_1, A5B2, n5_5_1);
nor gn7_5_1(n7_5_1, n4_5_1, n5_5_1);
nor gn8_5_1(S5_1, n6_5_1, n7_5_1);
nor gn9_5_1(C5_1, n1_5_1, n5_5_1);
/* FA MFA6_1(S6_1,C6_1,S7_0,C6_0,A6B2); */
nor gn1_6_1(n1_6_1, S7_0, C6_0);
nor gn2_6_1(n2_6_1, n1_6_1, C6_0);
nor gn3_6_1(n3_6_1, S7_0, n1_6_1);
nor gn4_6_1(n4_6_1, n2_6_1, n3_6_1);
nor gn5_6_1(n5_6_1, A6B2, n4_6_1);
nor gn6_6_1(n6_6_1, A6B2, n5_6_1);
nor gn7_6_1(n7_6_1, n4_6_1, n5_6_1);
nor gn8_6_1(S6_1, n6_6_1, n7_6_1);
nor gn9_6_1(C6_1, n1_6_1, n5_6_1);
/* FA MFA7_1(S7_1,C7_1,S8_0,C7_0,A7B2); */
nor gn1_7_1(n1_7_1, S8_0, C7_0);
nor gn2_7_1(n2_7_1, n1_7_1, C7_0);
nor gn3_7_1(n3_7_1, S8_0, n1_7_1);
nor gn4_7_1(n4_7_1, n2_7_1, n3_7_1);
nor gn5_7_1(n5_7_1, A7B2, n4_7_1);
nor gn6_7_1(n6_7_1, A7B2, n5_7_1);
nor gn7_7_1(n7_7_1, n4_7_1, n5_7_1);
nor gn8_7_1(S7_1, n6_7_1, n7_7_1);
nor gn9_7_1(C7_1, n1_7_1, n5_7_1);
/* FA MFA8_1(S8_1,C8_1,S9_0,C8_0,A8B2); */
nor gn1_8_1(n1_8_1, S9_0, C8_0);
nor gn2_8_1(n2_8_1, n1_8_1, C8_0);
nor gn3_8_1(n3_8_1, S9_0, n1_8_1);
nor gn4_8_1(n4_8_1, n2_8_1, n3_8_1);
nor gn5_8_1(n5_8_1, A8B2, n4_8_1);
nor gn6_8_1(n6_8_1, A8B2, n5_8_1);
nor gn7_8_1(n7_8_1, n4_8_1, n5_8_1);
nor gn8_8_1(S8_1, n6_8_1, n7_8_1);
nor gn9_8_1(C8_1, n1_8_1, n5_8_1);
/* FA MFA9_1(S9_1,C9_1,S10_0,C9_0,A9B2); */
nor gn1_9_1(n1_9_1, S10_0, C9_0);
nor gn2_9_1(n2_9_1, n1_9_1, C9_0);
nor gn3_9_1(n3_9_1, S10_0, n1_9_1);
nor gn4_9_1(n4_9_1, n2_9_1, n3_9_1);
nor gn5_9_1(n5_9_1, A9B2, n4_9_1);
nor gn6_9_1(n6_9_1, A9B2, n5_9_1);
nor gn7_9_1(n7_9_1, n4_9_1, n5_9_1);
nor gn8_9_1(S9_1, n6_9_1, n7_9_1);
nor gn9_9_1(C9_1, n1_9_1, n5_9_1);
/* FA MFA10_1(S10_1,C10_1,S11_0,C10_0,A10B2); */
nor gn1_10_1(n1_10_1, S11_0, C10_0);
nor gn2_10_1(n2_10_1, n1_10_1, C10_0);
nor gn3_10_1(n3_10_1, S11_0, n1_10_1);
nor gn4_10_1(n4_10_1, n2_10_1, n3_10_1);
nor gn5_10_1(n5_10_1, A10B2, n4_10_1);
nor gn6_10_1(n6_10_1, A10B2, n5_10_1);
nor gn7_10_1(n7_10_1, n4_10_1, n5_10_1);
nor gn8_10_1(S10_1, n6_10_1, n7_10_1);
nor gn9_10_1(C10_1, n1_10_1, n5_10_1);
/* FA MFA11_1(S11_1,C11_1,S12_0,C11_0,A11B2); */
nor gn1_11_1(n1_11_1, S12_0, C11_0);
nor gn2_11_1(n2_11_1, n1_11_1, C11_0);
nor gn3_11_1(n3_11_1, S12_0, n1_11_1);
nor gn4_11_1(n4_11_1, n2_11_1, n3_11_1);
nor gn5_11_1(n5_11_1, A11B2, n4_11_1);
nor gn6_11_1(n6_11_1, A11B2, n5_11_1);
nor gn7_11_1(n7_11_1, n4_11_1, n5_11_1);
nor gn8_11_1(S11_1, n6_11_1, n7_11_1);
nor gn9_11_1(C11_1, n1_11_1, n5_11_1);
/* FA MFA12_1(S12_1,C12_1,S13_0,C12_0,A12B2); */
nor gn1_12_1(n1_12_1, S13_0, C12_0);
nor gn2_12_1(n2_12_1, n1_12_1, C12_0);
nor gn3_12_1(n3_12_1, S13_0, n1_12_1);
nor gn4_12_1(n4_12_1, n2_12_1, n3_12_1);
nor gn5_12_1(n5_12_1, A12B2, n4_12_1);
nor gn6_12_1(n6_12_1, A12B2, n5_12_1);
nor gn7_12_1(n7_12_1, n4_12_1, n5_12_1);
nor gn8_12_1(S12_1, n6_12_1, n7_12_1);
nor gn9_12_1(C12_1, n1_12_1, n5_12_1);
/* FA MFA13_1(S13_1,C13_1,S14_0,C13_0,A13B2); */
nor gn1_13_1(n1_13_1, S14_0, C13_0);
nor gn2_13_1(n2_13_1, n1_13_1, C13_0);
nor gn3_13_1(n3_13_1, S14_0, n1_13_1);
nor gn4_13_1(n4_13_1, n2_13_1, n3_13_1);
nor gn5_13_1(n5_13_1, A13B2, n4_13_1);
nor gn6_13_1(n6_13_1, A13B2, n5_13_1);
nor gn7_13_1(n7_13_1, n4_13_1, n5_13_1);
nor gn8_13_1(S13_1, n6_13_1, n7_13_1);
nor gn9_13_1(C13_1, n1_13_1, n5_13_1);
/* FA MFA14_1(S14_1,C14_1,A15B1,C14_0,A14B2); */
nor gn1_14_1(n1_14_1, A15B1, C14_0);
nor gn2_14_1(n2_14_1, n1_14_1, C14_0);
nor gn3_14_1(n3_14_1, A15B1, n1_14_1);
nor gn4_14_1(n4_14_1, n2_14_1, n3_14_1);
nor gn5_14_1(n5_14_1, A14B2, n4_14_1);
nor gn6_14_1(n6_14_1, A14B2, n5_14_1);
nor gn7_14_1(n7_14_1, n4_14_1, n5_14_1);
nor gn8_14_1(S14_1, n6_14_1, n7_14_1);
nor gn9_14_1(C14_1, n1_14_1, n5_14_1);
/* FA MFA0_2(S0_2,C0_2,S1_1,C0_1,A0B3); */
nor gn1_0_2(n1_0_2, S1_1, C0_1);
nor gn2_0_2(n2_0_2, n1_0_2, C0_1);
nor gn3_0_2(n3_0_2, S1_1, n1_0_2);
nor gn4_0_2(n4_0_2, n2_0_2, n3_0_2);
nor gn5_0_2(n5_0_2, A0B3, n4_0_2);
nor gn6_0_2(n6_0_2, A0B3, n5_0_2);
nor gn7_0_2(n7_0_2, n4_0_2, n5_0_2);
nor gn8_0_2(S0_2, n6_0_2, n7_0_2);
nor gn9_0_2(C0_2, n1_0_2, n5_0_2);
/* FA MFA1_2(S1_2,C1_2,S2_1,C1_1,A1B3); */
nor gn1_1_2(n1_1_2, S2_1, C1_1);
nor gn2_1_2(n2_1_2, n1_1_2, C1_1);
nor gn3_1_2(n3_1_2, S2_1, n1_1_2);
nor gn4_1_2(n4_1_2, n2_1_2, n3_1_2);
nor gn5_1_2(n5_1_2, A1B3, n4_1_2);
nor gn6_1_2(n6_1_2, A1B3, n5_1_2);
nor gn7_1_2(n7_1_2, n4_1_2, n5_1_2);
nor gn8_1_2(S1_2, n6_1_2, n7_1_2);
nor gn9_1_2(C1_2, n1_1_2, n5_1_2);
/* FA MFA2_2(S2_2,C2_2,S3_1,C2_1,A2B3); */
nor gn1_2_2(n1_2_2, S3_1, C2_1);
nor gn2_2_2(n2_2_2, n1_2_2, C2_1);
nor gn3_2_2(n3_2_2, S3_1, n1_2_2);
nor gn4_2_2(n4_2_2, n2_2_2, n3_2_2);
nor gn5_2_2(n5_2_2, A2B3, n4_2_2);
nor gn6_2_2(n6_2_2, A2B3, n5_2_2);
nor gn7_2_2(n7_2_2, n4_2_2, n5_2_2);
nor gn8_2_2(S2_2, n6_2_2, n7_2_2);
nor gn9_2_2(C2_2, n1_2_2, n5_2_2);
/* FA MFA3_2(S3_2,C3_2,S4_1,C3_1,A3B3); */
nor gn1_3_2(n1_3_2, S4_1, C3_1);
nor gn2_3_2(n2_3_2, n1_3_2, C3_1);
nor gn3_3_2(n3_3_2, S4_1, n1_3_2);
nor gn4_3_2(n4_3_2, n2_3_2, n3_3_2);
nor gn5_3_2(n5_3_2, A3B3, n4_3_2);
nor gn6_3_2(n6_3_2, A3B3, n5_3_2);
nor gn7_3_2(n7_3_2, n4_3_2, n5_3_2);
nor gn8_3_2(S3_2, n6_3_2, n7_3_2);
nor gn9_3_2(C3_2, n1_3_2, n5_3_2);
/* FA MFA4_2(S4_2,C4_2,S5_1,C4_1,A4B3); */
nor gn1_4_2(n1_4_2, S5_1, C4_1);
nor gn2_4_2(n2_4_2, n1_4_2, C4_1);
nor gn3_4_2(n3_4_2, S5_1, n1_4_2);
nor gn4_4_2(n4_4_2, n2_4_2, n3_4_2);
nor gn5_4_2(n5_4_2, A4B3, n4_4_2);
nor gn6_4_2(n6_4_2, A4B3, n5_4_2);
nor gn7_4_2(n7_4_2, n4_4_2, n5_4_2);
nor gn8_4_2(S4_2, n6_4_2, n7_4_2);
nor gn9_4_2(C4_2, n1_4_2, n5_4_2);
/* FA MFA5_2(S5_2,C5_2,S6_1,C5_1,A5B3); */
nor gn1_5_2(n1_5_2, S6_1, C5_1);
nor gn2_5_2(n2_5_2, n1_5_2, C5_1);
nor gn3_5_2(n3_5_2, S6_1, n1_5_2);
nor gn4_5_2(n4_5_2, n2_5_2, n3_5_2);
nor gn5_5_2(n5_5_2, A5B3, n4_5_2);
nor gn6_5_2(n6_5_2, A5B3, n5_5_2);
nor gn7_5_2(n7_5_2, n4_5_2, n5_5_2);
nor gn8_5_2(S5_2, n6_5_2, n7_5_2);
nor gn9_5_2(C5_2, n1_5_2, n5_5_2);
/* FA MFA6_2(S6_2,C6_2,S7_1,C6_1,A6B3); */
nor gn1_6_2(n1_6_2, S7_1, C6_1);
nor gn2_6_2(n2_6_2, n1_6_2, C6_1);
nor gn3_6_2(n3_6_2, S7_1, n1_6_2);
nor gn4_6_2(n4_6_2, n2_6_2, n3_6_2);
nor gn5_6_2(n5_6_2, A6B3, n4_6_2);
nor gn6_6_2(n6_6_2, A6B3, n5_6_2);
nor gn7_6_2(n7_6_2, n4_6_2, n5_6_2);
nor gn8_6_2(S6_2, n6_6_2, n7_6_2);
nor gn9_6_2(C6_2, n1_6_2, n5_6_2);
/* FA MFA7_2(S7_2,C7_2,S8_1,C7_1,A7B3); */
nor gn1_7_2(n1_7_2, S8_1, C7_1);
nor gn2_7_2(n2_7_2, n1_7_2, C7_1);
nor gn3_7_2(n3_7_2, S8_1, n1_7_2);
nor gn4_7_2(n4_7_2, n2_7_2, n3_7_2);
nor gn5_7_2(n5_7_2, A7B3, n4_7_2);
nor gn6_7_2(n6_7_2, A7B3, n5_7_2);
nor gn7_7_2(n7_7_2, n4_7_2, n5_7_2);
nor gn8_7_2(S7_2, n6_7_2, n7_7_2);
nor gn9_7_2(C7_2, n1_7_2, n5_7_2);
/* FA MFA8_2(S8_2,C8_2,S9_1,C8_1,A8B3); */
nor gn1_8_2(n1_8_2, S9_1, C8_1);
nor gn2_8_2(n2_8_2, n1_8_2, C8_1);
nor gn3_8_2(n3_8_2, S9_1, n1_8_2);
nor gn4_8_2(n4_8_2, n2_8_2, n3_8_2);
nor gn5_8_2(n5_8_2, A8B3, n4_8_2);
nor gn6_8_2(n6_8_2, A8B3, n5_8_2);
nor gn7_8_2(n7_8_2, n4_8_2, n5_8_2);
nor gn8_8_2(S8_2, n6_8_2, n7_8_2);
nor gn9_8_2(C8_2, n1_8_2, n5_8_2);
/* FA MFA9_2(S9_2,C9_2,S10_1,C9_1,A9B3); */
nor gn1_9_2(n1_9_2, S10_1, C9_1);
nor gn2_9_2(n2_9_2, n1_9_2, C9_1);
nor gn3_9_2(n3_9_2, S10_1, n1_9_2);
nor gn4_9_2(n4_9_2, n2_9_2, n3_9_2);
nor gn5_9_2(n5_9_2, A9B3, n4_9_2);
nor gn6_9_2(n6_9_2, A9B3, n5_9_2);
nor gn7_9_2(n7_9_2, n4_9_2, n5_9_2);
nor gn8_9_2(S9_2, n6_9_2, n7_9_2);
nor gn9_9_2(C9_2, n1_9_2, n5_9_2);
/* FA MFA10_2(S10_2,C10_2,S11_1,C10_1,A10B3); */
nor gn1_10_2(n1_10_2, S11_1, C10_1);
nor gn2_10_2(n2_10_2, n1_10_2, C10_1);
nor gn3_10_2(n3_10_2, S11_1, n1_10_2);
nor gn4_10_2(n4_10_2, n2_10_2, n3_10_2);
nor gn5_10_2(n5_10_2, A10B3, n4_10_2);
nor gn6_10_2(n6_10_2, A10B3, n5_10_2);
nor gn7_10_2(n7_10_2, n4_10_2, n5_10_2);
nor gn8_10_2(S10_2, n6_10_2, n7_10_2);
nor gn9_10_2(C10_2, n1_10_2, n5_10_2);
/* FA MFA11_2(S11_2,C11_2,S12_1,C11_1,A11B3); */
nor gn1_11_2(n1_11_2, S12_1, C11_1);
nor gn2_11_2(n2_11_2, n1_11_2, C11_1);
nor gn3_11_2(n3_11_2, S12_1, n1_11_2);
nor gn4_11_2(n4_11_2, n2_11_2, n3_11_2);
nor gn5_11_2(n5_11_2, A11B3, n4_11_2);
nor gn6_11_2(n6_11_2, A11B3, n5_11_2);
nor gn7_11_2(n7_11_2, n4_11_2, n5_11_2);
nor gn8_11_2(S11_2, n6_11_2, n7_11_2);
nor gn9_11_2(C11_2, n1_11_2, n5_11_2);
/* FA MFA12_2(S12_2,C12_2,S13_1,C12_1,A12B3); */
nor gn1_12_2(n1_12_2, S13_1, C12_1);
nor gn2_12_2(n2_12_2, n1_12_2, C12_1);
nor gn3_12_2(n3_12_2, S13_1, n1_12_2);
nor gn4_12_2(n4_12_2, n2_12_2, n3_12_2);
nor gn5_12_2(n5_12_2, A12B3, n4_12_2);
nor gn6_12_2(n6_12_2, A12B3, n5_12_2);
nor gn7_12_2(n7_12_2, n4_12_2, n5_12_2);
nor gn8_12_2(S12_2, n6_12_2, n7_12_2);
nor gn9_12_2(C12_2, n1_12_2, n5_12_2);
/* FA MFA13_2(S13_2,C13_2,S14_1,C13_1,A13B3); */
nor gn1_13_2(n1_13_2, S14_1, C13_1);
nor gn2_13_2(n2_13_2, n1_13_2, C13_1);
nor gn3_13_2(n3_13_2, S14_1, n1_13_2);
nor gn4_13_2(n4_13_2, n2_13_2, n3_13_2);
nor gn5_13_2(n5_13_2, A13B3, n4_13_2);
nor gn6_13_2(n6_13_2, A13B3, n5_13_2);
nor gn7_13_2(n7_13_2, n4_13_2, n5_13_2);
nor gn8_13_2(S13_2, n6_13_2, n7_13_2);
nor gn9_13_2(C13_2, n1_13_2, n5_13_2);
/* FA MFA14_2(S14_2,C14_2,A15B2,C14_1,A14B3); */
nor gn1_14_2(n1_14_2, A15B2, C14_1);
nor gn2_14_2(n2_14_2, n1_14_2, C14_1);
nor gn3_14_2(n3_14_2, A15B2, n1_14_2);
nor gn4_14_2(n4_14_2, n2_14_2, n3_14_2);
nor gn5_14_2(n5_14_2, A14B3, n4_14_2);
nor gn6_14_2(n6_14_2, A14B3, n5_14_2);
nor gn7_14_2(n7_14_2, n4_14_2, n5_14_2);
nor gn8_14_2(S14_2, n6_14_2, n7_14_2);
nor gn9_14_2(C14_2, n1_14_2, n5_14_2);
/* FA MFA0_3(S0_3,C0_3,S1_2,C0_2,A0B4); */
nor gn1_0_3(n1_0_3, S1_2, C0_2);
nor gn2_0_3(n2_0_3, n1_0_3, C0_2);
nor gn3_0_3(n3_0_3, S1_2, n1_0_3);
nor gn4_0_3(n4_0_3, n2_0_3, n3_0_3);
nor gn5_0_3(n5_0_3, A0B4, n4_0_3);
nor gn6_0_3(n6_0_3, A0B4, n5_0_3);
nor gn7_0_3(n7_0_3, n4_0_3, n5_0_3);
nor gn8_0_3(S0_3, n6_0_3, n7_0_3);
nor gn9_0_3(C0_3, n1_0_3, n5_0_3);
/* FA MFA1_3(S1_3,C1_3,S2_2,C1_2,A1B4); */
nor gn1_1_3(n1_1_3, S2_2, C1_2);
nor gn2_1_3(n2_1_3, n1_1_3, C1_2);
nor gn3_1_3(n3_1_3, S2_2, n1_1_3);
nor gn4_1_3(n4_1_3, n2_1_3, n3_1_3);
nor gn5_1_3(n5_1_3, A1B4, n4_1_3);
nor gn6_1_3(n6_1_3, A1B4, n5_1_3);
nor gn7_1_3(n7_1_3, n4_1_3, n5_1_3);
nor gn8_1_3(S1_3, n6_1_3, n7_1_3);
nor gn9_1_3(C1_3, n1_1_3, n5_1_3);
/* FA MFA2_3(S2_3,C2_3,S3_2,C2_2,A2B4); */
nor gn1_2_3(n1_2_3, S3_2, C2_2);
nor gn2_2_3(n2_2_3, n1_2_3, C2_2);
nor gn3_2_3(n3_2_3, S3_2, n1_2_3);
nor gn4_2_3(n4_2_3, n2_2_3, n3_2_3);
nor gn5_2_3(n5_2_3, A2B4, n4_2_3);
nor gn6_2_3(n6_2_3, A2B4, n5_2_3);
nor gn7_2_3(n7_2_3, n4_2_3, n5_2_3);
nor gn8_2_3(S2_3, n6_2_3, n7_2_3);
nor gn9_2_3(C2_3, n1_2_3, n5_2_3);
/* FA MFA3_3(S3_3,C3_3,S4_2,C3_2,A3B4); */
nor gn1_3_3(n1_3_3, S4_2, C3_2);
nor gn2_3_3(n2_3_3, n1_3_3, C3_2);
nor gn3_3_3(n3_3_3, S4_2, n1_3_3);
nor gn4_3_3(n4_3_3, n2_3_3, n3_3_3);
nor gn5_3_3(n5_3_3, A3B4, n4_3_3);
nor gn6_3_3(n6_3_3, A3B4, n5_3_3);
nor gn7_3_3(n7_3_3, n4_3_3, n5_3_3);
nor gn8_3_3(S3_3, n6_3_3, n7_3_3);
nor gn9_3_3(C3_3, n1_3_3, n5_3_3);
/* FA MFA4_3(S4_3,C4_3,S5_2,C4_2,A4B4); */
nor gn1_4_3(n1_4_3, S5_2, C4_2);
nor gn2_4_3(n2_4_3, n1_4_3, C4_2);
nor gn3_4_3(n3_4_3, S5_2, n1_4_3);
nor gn4_4_3(n4_4_3, n2_4_3, n3_4_3);
nor gn5_4_3(n5_4_3, A4B4, n4_4_3);
nor gn6_4_3(n6_4_3, A4B4, n5_4_3);
nor gn7_4_3(n7_4_3, n4_4_3, n5_4_3);
nor gn8_4_3(S4_3, n6_4_3, n7_4_3);
nor gn9_4_3(C4_3, n1_4_3, n5_4_3);
/* FA MFA5_3(S5_3,C5_3,S6_2,C5_2,A5B4); */
nor gn1_5_3(n1_5_3, S6_2, C5_2);
nor gn2_5_3(n2_5_3, n1_5_3, C5_2);
nor gn3_5_3(n3_5_3, S6_2, n1_5_3);
nor gn4_5_3(n4_5_3, n2_5_3, n3_5_3);
nor gn5_5_3(n5_5_3, A5B4, n4_5_3);
nor gn6_5_3(n6_5_3, A5B4, n5_5_3);
nor gn7_5_3(n7_5_3, n4_5_3, n5_5_3);
nor gn8_5_3(S5_3, n6_5_3, n7_5_3);
nor gn9_5_3(C5_3, n1_5_3, n5_5_3);
/* FA MFA6_3(S6_3,C6_3,S7_2,C6_2,A6B4); */
nor gn1_6_3(n1_6_3, S7_2, C6_2);
nor gn2_6_3(n2_6_3, n1_6_3, C6_2);
nor gn3_6_3(n3_6_3, S7_2, n1_6_3);
nor gn4_6_3(n4_6_3, n2_6_3, n3_6_3);
nor gn5_6_3(n5_6_3, A6B4, n4_6_3);
nor gn6_6_3(n6_6_3, A6B4, n5_6_3);
nor gn7_6_3(n7_6_3, n4_6_3, n5_6_3);
nor gn8_6_3(S6_3, n6_6_3, n7_6_3);
nor gn9_6_3(C6_3, n1_6_3, n5_6_3);
/* FA MFA7_3(S7_3,C7_3,S8_2,C7_2,A7B4); */
nor gn1_7_3(n1_7_3, S8_2, C7_2);
nor gn2_7_3(n2_7_3, n1_7_3, C7_2);
nor gn3_7_3(n3_7_3, S8_2, n1_7_3);
nor gn4_7_3(n4_7_3, n2_7_3, n3_7_3);
nor gn5_7_3(n5_7_3, A7B4, n4_7_3);
nor gn6_7_3(n6_7_3, A7B4, n5_7_3);
nor gn7_7_3(n7_7_3, n4_7_3, n5_7_3);
nor gn8_7_3(S7_3, n6_7_3, n7_7_3);
nor gn9_7_3(C7_3, n1_7_3, n5_7_3);
/* FA MFA8_3(S8_3,C8_3,S9_2,C8_2,A8B4); */
nor gn1_8_3(n1_8_3, S9_2, C8_2);
nor gn2_8_3(n2_8_3, n1_8_3, C8_2);
nor gn3_8_3(n3_8_3, S9_2, n1_8_3);
nor gn4_8_3(n4_8_3, n2_8_3, n3_8_3);
nor gn5_8_3(n5_8_3, A8B4, n4_8_3);
nor gn6_8_3(n6_8_3, A8B4, n5_8_3);
nor gn7_8_3(n7_8_3, n4_8_3, n5_8_3);
nor gn8_8_3(S8_3, n6_8_3, n7_8_3);
nor gn9_8_3(C8_3, n1_8_3, n5_8_3);
/* FA MFA9_3(S9_3,C9_3,S10_2,C9_2,A9B4); */
nor gn1_9_3(n1_9_3, S10_2, C9_2);
nor gn2_9_3(n2_9_3, n1_9_3, C9_2);
nor gn3_9_3(n3_9_3, S10_2, n1_9_3);
nor gn4_9_3(n4_9_3, n2_9_3, n3_9_3);
nor gn5_9_3(n5_9_3, A9B4, n4_9_3);
nor gn6_9_3(n6_9_3, A9B4, n5_9_3);
nor gn7_9_3(n7_9_3, n4_9_3, n5_9_3);
nor gn8_9_3(S9_3, n6_9_3, n7_9_3);
nor gn9_9_3(C9_3, n1_9_3, n5_9_3);
/* FA MFA10_3(S10_3,C10_3,S11_2,C10_2,A10B4); */
nor gn1_10_3(n1_10_3, S11_2, C10_2);
nor gn2_10_3(n2_10_3, n1_10_3, C10_2);
nor gn3_10_3(n3_10_3, S11_2, n1_10_3);
nor gn4_10_3(n4_10_3, n2_10_3, n3_10_3);
nor gn5_10_3(n5_10_3, A10B4, n4_10_3);
nor gn6_10_3(n6_10_3, A10B4, n5_10_3);
nor gn7_10_3(n7_10_3, n4_10_3, n5_10_3);
nor gn8_10_3(S10_3, n6_10_3, n7_10_3);
nor gn9_10_3(C10_3, n1_10_3, n5_10_3);
/* FA MFA11_3(S11_3,C11_3,S12_2,C11_2,A11B4); */
nor gn1_11_3(n1_11_3, S12_2, C11_2);
nor gn2_11_3(n2_11_3, n1_11_3, C11_2);
nor gn3_11_3(n3_11_3, S12_2, n1_11_3);
nor gn4_11_3(n4_11_3, n2_11_3, n3_11_3);
nor gn5_11_3(n5_11_3, A11B4, n4_11_3);
nor gn6_11_3(n6_11_3, A11B4, n5_11_3);
nor gn7_11_3(n7_11_3, n4_11_3, n5_11_3);
nor gn8_11_3(S11_3, n6_11_3, n7_11_3);
nor gn9_11_3(C11_3, n1_11_3, n5_11_3);
/* FA MFA12_3(S12_3,C12_3,S13_2,C12_2,A12B4); */
nor gn1_12_3(n1_12_3, S13_2, C12_2);
nor gn2_12_3(n2_12_3, n1_12_3, C12_2);
nor gn3_12_3(n3_12_3, S13_2, n1_12_3);
nor gn4_12_3(n4_12_3, n2_12_3, n3_12_3);
nor gn5_12_3(n5_12_3, A12B4, n4_12_3);
nor gn6_12_3(n6_12_3, A12B4, n5_12_3);
nor gn7_12_3(n7_12_3, n4_12_3, n5_12_3);
nor gn8_12_3(S12_3, n6_12_3, n7_12_3);
nor gn9_12_3(C12_3, n1_12_3, n5_12_3);
/* FA MFA13_3(S13_3,C13_3,S14_2,C13_2,A13B4); */
nor gn1_13_3(n1_13_3, S14_2, C13_2);
nor gn2_13_3(n2_13_3, n1_13_3, C13_2);
nor gn3_13_3(n3_13_3, S14_2, n1_13_3);
nor gn4_13_3(n4_13_3, n2_13_3, n3_13_3);
nor gn5_13_3(n5_13_3, A13B4, n4_13_3);
nor gn6_13_3(n6_13_3, A13B4, n5_13_3);
nor gn7_13_3(n7_13_3, n4_13_3, n5_13_3);
nor gn8_13_3(S13_3, n6_13_3, n7_13_3);
nor gn9_13_3(C13_3, n1_13_3, n5_13_3);
/* FA MFA14_3(S14_3,C14_3,A15B3,C14_2,A14B4); */
nor gn1_14_3(n1_14_3, A15B3, C14_2);
nor gn2_14_3(n2_14_3, n1_14_3, C14_2);
nor gn3_14_3(n3_14_3, A15B3, n1_14_3);
nor gn4_14_3(n4_14_3, n2_14_3, n3_14_3);
nor gn5_14_3(n5_14_3, A14B4, n4_14_3);
nor gn6_14_3(n6_14_3, A14B4, n5_14_3);
nor gn7_14_3(n7_14_3, n4_14_3, n5_14_3);
nor gn8_14_3(S14_3, n6_14_3, n7_14_3);
nor gn9_14_3(C14_3, n1_14_3, n5_14_3);
/* FA MFA0_4(S0_4,C0_4,S1_3,C0_3,A0B5); */
nor gn1_0_4(n1_0_4, S1_3, C0_3);
nor gn2_0_4(n2_0_4, n1_0_4, C0_3);
nor gn3_0_4(n3_0_4, S1_3, n1_0_4);
nor gn4_0_4(n4_0_4, n2_0_4, n3_0_4);
nor gn5_0_4(n5_0_4, A0B5, n4_0_4);
nor gn6_0_4(n6_0_4, A0B5, n5_0_4);
nor gn7_0_4(n7_0_4, n4_0_4, n5_0_4);
nor gn8_0_4(S0_4, n6_0_4, n7_0_4);
nor gn9_0_4(C0_4, n1_0_4, n5_0_4);
/* FA MFA1_4(S1_4,C1_4,S2_3,C1_3,A1B5); */
nor gn1_1_4(n1_1_4, S2_3, C1_3);
nor gn2_1_4(n2_1_4, n1_1_4, C1_3);
nor gn3_1_4(n3_1_4, S2_3, n1_1_4);
nor gn4_1_4(n4_1_4, n2_1_4, n3_1_4);
nor gn5_1_4(n5_1_4, A1B5, n4_1_4);
nor gn6_1_4(n6_1_4, A1B5, n5_1_4);
nor gn7_1_4(n7_1_4, n4_1_4, n5_1_4);
nor gn8_1_4(S1_4, n6_1_4, n7_1_4);
nor gn9_1_4(C1_4, n1_1_4, n5_1_4);
/* FA MFA2_4(S2_4,C2_4,S3_3,C2_3,A2B5); */
nor gn1_2_4(n1_2_4, S3_3, C2_3);
nor gn2_2_4(n2_2_4, n1_2_4, C2_3);
nor gn3_2_4(n3_2_4, S3_3, n1_2_4);
nor gn4_2_4(n4_2_4, n2_2_4, n3_2_4);
nor gn5_2_4(n5_2_4, A2B5, n4_2_4);
nor gn6_2_4(n6_2_4, A2B5, n5_2_4);
nor gn7_2_4(n7_2_4, n4_2_4, n5_2_4);
nor gn8_2_4(S2_4, n6_2_4, n7_2_4);
nor gn9_2_4(C2_4, n1_2_4, n5_2_4);
/* FA MFA3_4(S3_4,C3_4,S4_3,C3_3,A3B5); */
nor gn1_3_4(n1_3_4, S4_3, C3_3);
nor gn2_3_4(n2_3_4, n1_3_4, C3_3);
nor gn3_3_4(n3_3_4, S4_3, n1_3_4);
nor gn4_3_4(n4_3_4, n2_3_4, n3_3_4);
nor gn5_3_4(n5_3_4, A3B5, n4_3_4);
nor gn6_3_4(n6_3_4, A3B5, n5_3_4);
nor gn7_3_4(n7_3_4, n4_3_4, n5_3_4);
nor gn8_3_4(S3_4, n6_3_4, n7_3_4);
nor gn9_3_4(C3_4, n1_3_4, n5_3_4);
/* FA MFA4_4(S4_4,C4_4,S5_3,C4_3,A4B5); */
nor gn1_4_4(n1_4_4, S5_3, C4_3);
nor gn2_4_4(n2_4_4, n1_4_4, C4_3);
nor gn3_4_4(n3_4_4, S5_3, n1_4_4);
nor gn4_4_4(n4_4_4, n2_4_4, n3_4_4);
nor gn5_4_4(n5_4_4, A4B5, n4_4_4);
nor gn6_4_4(n6_4_4, A4B5, n5_4_4);
nor gn7_4_4(n7_4_4, n4_4_4, n5_4_4);
nor gn8_4_4(S4_4, n6_4_4, n7_4_4);
nor gn9_4_4(C4_4, n1_4_4, n5_4_4);
/* FA MFA5_4(S5_4,C5_4,S6_3,C5_3,A5B5); */
nor gn1_5_4(n1_5_4, S6_3, C5_3);
nor gn2_5_4(n2_5_4, n1_5_4, C5_3);
nor gn3_5_4(n3_5_4, S6_3, n1_5_4);
nor gn4_5_4(n4_5_4, n2_5_4, n3_5_4);
nor gn5_5_4(n5_5_4, A5B5, n4_5_4);
nor gn6_5_4(n6_5_4, A5B5, n5_5_4);
nor gn7_5_4(n7_5_4, n4_5_4, n5_5_4);
nor gn8_5_4(S5_4, n6_5_4, n7_5_4);
nor gn9_5_4(C5_4, n1_5_4, n5_5_4);
/* FA MFA6_4(S6_4,C6_4,S7_3,C6_3,A6B5); */
nor gn1_6_4(n1_6_4, S7_3, C6_3);
nor gn2_6_4(n2_6_4, n1_6_4, C6_3);
nor gn3_6_4(n3_6_4, S7_3, n1_6_4);
nor gn4_6_4(n4_6_4, n2_6_4, n3_6_4);
nor gn5_6_4(n5_6_4, A6B5, n4_6_4);
nor gn6_6_4(n6_6_4, A6B5, n5_6_4);
nor gn7_6_4(n7_6_4, n4_6_4, n5_6_4);
nor gn8_6_4(S6_4, n6_6_4, n7_6_4);
nor gn9_6_4(C6_4, n1_6_4, n5_6_4);
/* FA MFA7_4(S7_4,C7_4,S8_3,C7_3,A7B5); */
nor gn1_7_4(n1_7_4, S8_3, C7_3);
nor gn2_7_4(n2_7_4, n1_7_4, C7_3);
nor gn3_7_4(n3_7_4, S8_3, n1_7_4);
nor gn4_7_4(n4_7_4, n2_7_4, n3_7_4);
nor gn5_7_4(n5_7_4, A7B5, n4_7_4);
nor gn6_7_4(n6_7_4, A7B5, n5_7_4);
nor gn7_7_4(n7_7_4, n4_7_4, n5_7_4);
nor gn8_7_4(S7_4, n6_7_4, n7_7_4);
nor gn9_7_4(C7_4, n1_7_4, n5_7_4);
/* FA MFA8_4(S8_4,C8_4,S9_3,C8_3,A8B5); */
nor gn1_8_4(n1_8_4, S9_3, C8_3);
nor gn2_8_4(n2_8_4, n1_8_4, C8_3);
nor gn3_8_4(n3_8_4, S9_3, n1_8_4);
nor gn4_8_4(n4_8_4, n2_8_4, n3_8_4);
nor gn5_8_4(n5_8_4, A8B5, n4_8_4);
nor gn6_8_4(n6_8_4, A8B5, n5_8_4);
nor gn7_8_4(n7_8_4, n4_8_4, n5_8_4);
nor gn8_8_4(S8_4, n6_8_4, n7_8_4);
nor gn9_8_4(C8_4, n1_8_4, n5_8_4);
/* FA MFA9_4(S9_4,C9_4,S10_3,C9_3,A9B5); */
nor gn1_9_4(n1_9_4, S10_3, C9_3);
nor gn2_9_4(n2_9_4, n1_9_4, C9_3);
nor gn3_9_4(n3_9_4, S10_3, n1_9_4);
nor gn4_9_4(n4_9_4, n2_9_4, n3_9_4);
nor gn5_9_4(n5_9_4, A9B5, n4_9_4);
nor gn6_9_4(n6_9_4, A9B5, n5_9_4);
nor gn7_9_4(n7_9_4, n4_9_4, n5_9_4);
nor gn8_9_4(S9_4, n6_9_4, n7_9_4);
nor gn9_9_4(C9_4, n1_9_4, n5_9_4);
/* FA MFA10_4(S10_4,C10_4,S11_3,C10_3,A10B5); */
nor gn1_10_4(n1_10_4, S11_3, C10_3);
nor gn2_10_4(n2_10_4, n1_10_4, C10_3);
nor gn3_10_4(n3_10_4, S11_3, n1_10_4);
nor gn4_10_4(n4_10_4, n2_10_4, n3_10_4);
nor gn5_10_4(n5_10_4, A10B5, n4_10_4);
nor gn6_10_4(n6_10_4, A10B5, n5_10_4);
nor gn7_10_4(n7_10_4, n4_10_4, n5_10_4);
nor gn8_10_4(S10_4, n6_10_4, n7_10_4);
nor gn9_10_4(C10_4, n1_10_4, n5_10_4);
/* FA MFA11_4(S11_4,C11_4,S12_3,C11_3,A11B5); */
nor gn1_11_4(n1_11_4, S12_3, C11_3);
nor gn2_11_4(n2_11_4, n1_11_4, C11_3);
nor gn3_11_4(n3_11_4, S12_3, n1_11_4);
nor gn4_11_4(n4_11_4, n2_11_4, n3_11_4);
nor gn5_11_4(n5_11_4, A11B5, n4_11_4);
nor gn6_11_4(n6_11_4, A11B5, n5_11_4);
nor gn7_11_4(n7_11_4, n4_11_4, n5_11_4);
nor gn8_11_4(S11_4, n6_11_4, n7_11_4);
nor gn9_11_4(C11_4, n1_11_4, n5_11_4);
/* FA MFA12_4(S12_4,C12_4,S13_3,C12_3,A12B5); */
nor gn1_12_4(n1_12_4, S13_3, C12_3);
nor gn2_12_4(n2_12_4, n1_12_4, C12_3);
nor gn3_12_4(n3_12_4, S13_3, n1_12_4);
nor gn4_12_4(n4_12_4, n2_12_4, n3_12_4);
nor gn5_12_4(n5_12_4, A12B5, n4_12_4);
nor gn6_12_4(n6_12_4, A12B5, n5_12_4);
nor gn7_12_4(n7_12_4, n4_12_4, n5_12_4);
nor gn8_12_4(S12_4, n6_12_4, n7_12_4);
nor gn9_12_4(C12_4, n1_12_4, n5_12_4);
/* FA MFA13_4(S13_4,C13_4,S14_3,C13_3,A13B5); */
nor gn1_13_4(n1_13_4, S14_3, C13_3);
nor gn2_13_4(n2_13_4, n1_13_4, C13_3);
nor gn3_13_4(n3_13_4, S14_3, n1_13_4);
nor gn4_13_4(n4_13_4, n2_13_4, n3_13_4);
nor gn5_13_4(n5_13_4, A13B5, n4_13_4);
nor gn6_13_4(n6_13_4, A13B5, n5_13_4);
nor gn7_13_4(n7_13_4, n4_13_4, n5_13_4);
nor gn8_13_4(S13_4, n6_13_4, n7_13_4);
nor gn9_13_4(C13_4, n1_13_4, n5_13_4);
/* FA MFA14_4(S14_4,C14_4,A15B4,C14_3,A14B5); */
nor gn1_14_4(n1_14_4, A15B4, C14_3);
nor gn2_14_4(n2_14_4, n1_14_4, C14_3);
nor gn3_14_4(n3_14_4, A15B4, n1_14_4);
nor gn4_14_4(n4_14_4, n2_14_4, n3_14_4);
nor gn5_14_4(n5_14_4, A14B5, n4_14_4);
nor gn6_14_4(n6_14_4, A14B5, n5_14_4);
nor gn7_14_4(n7_14_4, n4_14_4, n5_14_4);
nor gn8_14_4(S14_4, n6_14_4, n7_14_4);
nor gn9_14_4(C14_4, n1_14_4, n5_14_4);
/* FA MFA0_5(S0_5,C0_5,S1_4,C0_4,A0B6); */
nor gn1_0_5(n1_0_5, S1_4, C0_4);
nor gn2_0_5(n2_0_5, n1_0_5, C0_4);
nor gn3_0_5(n3_0_5, S1_4, n1_0_5);
nor gn4_0_5(n4_0_5, n2_0_5, n3_0_5);
nor gn5_0_5(n5_0_5, A0B6, n4_0_5);
nor gn6_0_5(n6_0_5, A0B6, n5_0_5);
nor gn7_0_5(n7_0_5, n4_0_5, n5_0_5);
nor gn8_0_5(S0_5, n6_0_5, n7_0_5);
nor gn9_0_5(C0_5, n1_0_5, n5_0_5);
/* FA MFA1_5(S1_5,C1_5,S2_4,C1_4,A1B6); */
nor gn1_1_5(n1_1_5, S2_4, C1_4);
nor gn2_1_5(n2_1_5, n1_1_5, C1_4);
nor gn3_1_5(n3_1_5, S2_4, n1_1_5);
nor gn4_1_5(n4_1_5, n2_1_5, n3_1_5);
nor gn5_1_5(n5_1_5, A1B6, n4_1_5);
nor gn6_1_5(n6_1_5, A1B6, n5_1_5);
nor gn7_1_5(n7_1_5, n4_1_5, n5_1_5);
nor gn8_1_5(S1_5, n6_1_5, n7_1_5);
nor gn9_1_5(C1_5, n1_1_5, n5_1_5);
/* FA MFA2_5(S2_5,C2_5,S3_4,C2_4,A2B6); */
nor gn1_2_5(n1_2_5, S3_4, C2_4);
nor gn2_2_5(n2_2_5, n1_2_5, C2_4);
nor gn3_2_5(n3_2_5, S3_4, n1_2_5);
nor gn4_2_5(n4_2_5, n2_2_5, n3_2_5);
nor gn5_2_5(n5_2_5, A2B6, n4_2_5);
nor gn6_2_5(n6_2_5, A2B6, n5_2_5);
nor gn7_2_5(n7_2_5, n4_2_5, n5_2_5);
nor gn8_2_5(S2_5, n6_2_5, n7_2_5);
nor gn9_2_5(C2_5, n1_2_5, n5_2_5);
/* FA MFA3_5(S3_5,C3_5,S4_4,C3_4,A3B6); */
nor gn1_3_5(n1_3_5, S4_4, C3_4);
nor gn2_3_5(n2_3_5, n1_3_5, C3_4);
nor gn3_3_5(n3_3_5, S4_4, n1_3_5);
nor gn4_3_5(n4_3_5, n2_3_5, n3_3_5);
nor gn5_3_5(n5_3_5, A3B6, n4_3_5);
nor gn6_3_5(n6_3_5, A3B6, n5_3_5);
nor gn7_3_5(n7_3_5, n4_3_5, n5_3_5);
nor gn8_3_5(S3_5, n6_3_5, n7_3_5);
nor gn9_3_5(C3_5, n1_3_5, n5_3_5);
/* FA MFA4_5(S4_5,C4_5,S5_4,C4_4,A4B6); */
nor gn1_4_5(n1_4_5, S5_4, C4_4);
nor gn2_4_5(n2_4_5, n1_4_5, C4_4);
nor gn3_4_5(n3_4_5, S5_4, n1_4_5);
nor gn4_4_5(n4_4_5, n2_4_5, n3_4_5);
nor gn5_4_5(n5_4_5, A4B6, n4_4_5);
nor gn6_4_5(n6_4_5, A4B6, n5_4_5);
nor gn7_4_5(n7_4_5, n4_4_5, n5_4_5);
nor gn8_4_5(S4_5, n6_4_5, n7_4_5);
nor gn9_4_5(C4_5, n1_4_5, n5_4_5);
/* FA MFA5_5(S5_5,C5_5,S6_4,C5_4,A5B6); */
nor gn1_5_5(n1_5_5, S6_4, C5_4);
nor gn2_5_5(n2_5_5, n1_5_5, C5_4);
nor gn3_5_5(n3_5_5, S6_4, n1_5_5);
nor gn4_5_5(n4_5_5, n2_5_5, n3_5_5);
nor gn5_5_5(n5_5_5, A5B6, n4_5_5);
nor gn6_5_5(n6_5_5, A5B6, n5_5_5);
nor gn7_5_5(n7_5_5, n4_5_5, n5_5_5);
nor gn8_5_5(S5_5, n6_5_5, n7_5_5);
nor gn9_5_5(C5_5, n1_5_5, n5_5_5);
/* FA MFA6_5(S6_5,C6_5,S7_4,C6_4,A6B6); */
nor gn1_6_5(n1_6_5, S7_4, C6_4);
nor gn2_6_5(n2_6_5, n1_6_5, C6_4);
nor gn3_6_5(n3_6_5, S7_4, n1_6_5);
nor gn4_6_5(n4_6_5, n2_6_5, n3_6_5);
nor gn5_6_5(n5_6_5, A6B6, n4_6_5);
nor gn6_6_5(n6_6_5, A6B6, n5_6_5);
nor gn7_6_5(n7_6_5, n4_6_5, n5_6_5);
nor gn8_6_5(S6_5, n6_6_5, n7_6_5);
nor gn9_6_5(C6_5, n1_6_5, n5_6_5);
/* FA MFA7_5(S7_5,C7_5,S8_4,C7_4,A7B6); */
nor gn1_7_5(n1_7_5, S8_4, C7_4);
nor gn2_7_5(n2_7_5, n1_7_5, C7_4);
nor gn3_7_5(n3_7_5, S8_4, n1_7_5);
nor gn4_7_5(n4_7_5, n2_7_5, n3_7_5);
nor gn5_7_5(n5_7_5, A7B6, n4_7_5);
nor gn6_7_5(n6_7_5, A7B6, n5_7_5);
nor gn7_7_5(n7_7_5, n4_7_5, n5_7_5);
nor gn8_7_5(S7_5, n6_7_5, n7_7_5);
nor gn9_7_5(C7_5, n1_7_5, n5_7_5);
/* FA MFA8_5(S8_5,C8_5,S9_4,C8_4,A8B6); */
nor gn1_8_5(n1_8_5, S9_4, C8_4);
nor gn2_8_5(n2_8_5, n1_8_5, C8_4);
nor gn3_8_5(n3_8_5, S9_4, n1_8_5);
nor gn4_8_5(n4_8_5, n2_8_5, n3_8_5);
nor gn5_8_5(n5_8_5, A8B6, n4_8_5);
nor gn6_8_5(n6_8_5, A8B6, n5_8_5);
nor gn7_8_5(n7_8_5, n4_8_5, n5_8_5);
nor gn8_8_5(S8_5, n6_8_5, n7_8_5);
nor gn9_8_5(C8_5, n1_8_5, n5_8_5);
/* FA MFA9_5(S9_5,C9_5,S10_4,C9_4,A9B6); */
nor gn1_9_5(n1_9_5, S10_4, C9_4);
nor gn2_9_5(n2_9_5, n1_9_5, C9_4);
nor gn3_9_5(n3_9_5, S10_4, n1_9_5);
nor gn4_9_5(n4_9_5, n2_9_5, n3_9_5);
nor gn5_9_5(n5_9_5, A9B6, n4_9_5);
nor gn6_9_5(n6_9_5, A9B6, n5_9_5);
nor gn7_9_5(n7_9_5, n4_9_5, n5_9_5);
nor gn8_9_5(S9_5, n6_9_5, n7_9_5);
nor gn9_9_5(C9_5, n1_9_5, n5_9_5);
/* FA MFA10_5(S10_5,C10_5,S11_4,C10_4,A10B6); */
nor gn1_10_5(n1_10_5, S11_4, C10_4);
nor gn2_10_5(n2_10_5, n1_10_5, C10_4);
nor gn3_10_5(n3_10_5, S11_4, n1_10_5);
nor gn4_10_5(n4_10_5, n2_10_5, n3_10_5);
nor gn5_10_5(n5_10_5, A10B6, n4_10_5);
nor gn6_10_5(n6_10_5, A10B6, n5_10_5);
nor gn7_10_5(n7_10_5, n4_10_5, n5_10_5);
nor gn8_10_5(S10_5, n6_10_5, n7_10_5);
nor gn9_10_5(C10_5, n1_10_5, n5_10_5);
/* FA MFA11_5(S11_5,C11_5,S12_4,C11_4,A11B6); */
nor gn1_11_5(n1_11_5, S12_4, C11_4);
nor gn2_11_5(n2_11_5, n1_11_5, C11_4);
nor gn3_11_5(n3_11_5, S12_4, n1_11_5);
nor gn4_11_5(n4_11_5, n2_11_5, n3_11_5);
nor gn5_11_5(n5_11_5, A11B6, n4_11_5);
nor gn6_11_5(n6_11_5, A11B6, n5_11_5);
nor gn7_11_5(n7_11_5, n4_11_5, n5_11_5);
nor gn8_11_5(S11_5, n6_11_5, n7_11_5);
nor gn9_11_5(C11_5, n1_11_5, n5_11_5);
/* FA MFA12_5(S12_5,C12_5,S13_4,C12_4,A12B6); */
nor gn1_12_5(n1_12_5, S13_4, C12_4);
nor gn2_12_5(n2_12_5, n1_12_5, C12_4);
nor gn3_12_5(n3_12_5, S13_4, n1_12_5);
nor gn4_12_5(n4_12_5, n2_12_5, n3_12_5);
nor gn5_12_5(n5_12_5, A12B6, n4_12_5);
nor gn6_12_5(n6_12_5, A12B6, n5_12_5);
nor gn7_12_5(n7_12_5, n4_12_5, n5_12_5);
nor gn8_12_5(S12_5, n6_12_5, n7_12_5);
nor gn9_12_5(C12_5, n1_12_5, n5_12_5);
/* FA MFA13_5(S13_5,C13_5,S14_4,C13_4,A13B6); */
nor gn1_13_5(n1_13_5, S14_4, C13_4);
nor gn2_13_5(n2_13_5, n1_13_5, C13_4);
nor gn3_13_5(n3_13_5, S14_4, n1_13_5);
nor gn4_13_5(n4_13_5, n2_13_5, n3_13_5);
nor gn5_13_5(n5_13_5, A13B6, n4_13_5);
nor gn6_13_5(n6_13_5, A13B6, n5_13_5);
nor gn7_13_5(n7_13_5, n4_13_5, n5_13_5);
nor gn8_13_5(S13_5, n6_13_5, n7_13_5);
nor gn9_13_5(C13_5, n1_13_5, n5_13_5);
/* FA MFA14_5(S14_5,C14_5,A15B5,C14_4,A14B6); */
nor gn1_14_5(n1_14_5, A15B5, C14_4);
nor gn2_14_5(n2_14_5, n1_14_5, C14_4);
nor gn3_14_5(n3_14_5, A15B5, n1_14_5);
nor gn4_14_5(n4_14_5, n2_14_5, n3_14_5);
nor gn5_14_5(n5_14_5, A14B6, n4_14_5);
nor gn6_14_5(n6_14_5, A14B6, n5_14_5);
nor gn7_14_5(n7_14_5, n4_14_5, n5_14_5);
nor gn8_14_5(S14_5, n6_14_5, n7_14_5);
nor gn9_14_5(C14_5, n1_14_5, n5_14_5);
/* FA MFA0_6(S0_6,C0_6,S1_5,C0_5,A0B7); */
nor gn1_0_6(n1_0_6, S1_5, C0_5);
nor gn2_0_6(n2_0_6, n1_0_6, C0_5);
nor gn3_0_6(n3_0_6, S1_5, n1_0_6);
nor gn4_0_6(n4_0_6, n2_0_6, n3_0_6);
nor gn5_0_6(n5_0_6, A0B7, n4_0_6);
nor gn6_0_6(n6_0_6, A0B7, n5_0_6);
nor gn7_0_6(n7_0_6, n4_0_6, n5_0_6);
nor gn8_0_6(S0_6, n6_0_6, n7_0_6);
nor gn9_0_6(C0_6, n1_0_6, n5_0_6);
/* FA MFA1_6(S1_6,C1_6,S2_5,C1_5,A1B7); */
nor gn1_1_6(n1_1_6, S2_5, C1_5);
nor gn2_1_6(n2_1_6, n1_1_6, C1_5);
nor gn3_1_6(n3_1_6, S2_5, n1_1_6);
nor gn4_1_6(n4_1_6, n2_1_6, n3_1_6);
nor gn5_1_6(n5_1_6, A1B7, n4_1_6);
nor gn6_1_6(n6_1_6, A1B7, n5_1_6);
nor gn7_1_6(n7_1_6, n4_1_6, n5_1_6);
nor gn8_1_6(S1_6, n6_1_6, n7_1_6);
nor gn9_1_6(C1_6, n1_1_6, n5_1_6);
/* FA MFA2_6(S2_6,C2_6,S3_5,C2_5,A2B7); */
nor gn1_2_6(n1_2_6, S3_5, C2_5);
nor gn2_2_6(n2_2_6, n1_2_6, C2_5);
nor gn3_2_6(n3_2_6, S3_5, n1_2_6);
nor gn4_2_6(n4_2_6, n2_2_6, n3_2_6);
nor gn5_2_6(n5_2_6, A2B7, n4_2_6);
nor gn6_2_6(n6_2_6, A2B7, n5_2_6);
nor gn7_2_6(n7_2_6, n4_2_6, n5_2_6);
nor gn8_2_6(S2_6, n6_2_6, n7_2_6);
nor gn9_2_6(C2_6, n1_2_6, n5_2_6);
/* FA MFA3_6(S3_6,C3_6,S4_5,C3_5,A3B7); */
nor gn1_3_6(n1_3_6, S4_5, C3_5);
nor gn2_3_6(n2_3_6, n1_3_6, C3_5);
nor gn3_3_6(n3_3_6, S4_5, n1_3_6);
nor gn4_3_6(n4_3_6, n2_3_6, n3_3_6);
nor gn5_3_6(n5_3_6, A3B7, n4_3_6);
nor gn6_3_6(n6_3_6, A3B7, n5_3_6);
nor gn7_3_6(n7_3_6, n4_3_6, n5_3_6);
nor gn8_3_6(S3_6, n6_3_6, n7_3_6);
nor gn9_3_6(C3_6, n1_3_6, n5_3_6);
/* FA MFA4_6(S4_6,C4_6,S5_5,C4_5,A4B7); */
nor gn1_4_6(n1_4_6, S5_5, C4_5);
nor gn2_4_6(n2_4_6, n1_4_6, C4_5);
nor gn3_4_6(n3_4_6, S5_5, n1_4_6);
nor gn4_4_6(n4_4_6, n2_4_6, n3_4_6);
nor gn5_4_6(n5_4_6, A4B7, n4_4_6);
nor gn6_4_6(n6_4_6, A4B7, n5_4_6);
nor gn7_4_6(n7_4_6, n4_4_6, n5_4_6);
nor gn8_4_6(S4_6, n6_4_6, n7_4_6);
nor gn9_4_6(C4_6, n1_4_6, n5_4_6);
/* FA MFA5_6(S5_6,C5_6,S6_5,C5_5,A5B7); */
nor gn1_5_6(n1_5_6, S6_5, C5_5);
nor gn2_5_6(n2_5_6, n1_5_6, C5_5);
nor gn3_5_6(n3_5_6, S6_5, n1_5_6);
nor gn4_5_6(n4_5_6, n2_5_6, n3_5_6);
nor gn5_5_6(n5_5_6, A5B7, n4_5_6);
nor gn6_5_6(n6_5_6, A5B7, n5_5_6);
nor gn7_5_6(n7_5_6, n4_5_6, n5_5_6);
nor gn8_5_6(S5_6, n6_5_6, n7_5_6);
nor gn9_5_6(C5_6, n1_5_6, n5_5_6);
/* FA MFA6_6(S6_6,C6_6,S7_5,C6_5,A6B7); */
nor gn1_6_6(n1_6_6, S7_5, C6_5);
nor gn2_6_6(n2_6_6, n1_6_6, C6_5);
nor gn3_6_6(n3_6_6, S7_5, n1_6_6);
nor gn4_6_6(n4_6_6, n2_6_6, n3_6_6);
nor gn5_6_6(n5_6_6, A6B7, n4_6_6);
nor gn6_6_6(n6_6_6, A6B7, n5_6_6);
nor gn7_6_6(n7_6_6, n4_6_6, n5_6_6);
nor gn8_6_6(S6_6, n6_6_6, n7_6_6);
nor gn9_6_6(C6_6, n1_6_6, n5_6_6);
/* FA MFA7_6(S7_6,C7_6,S8_5,C7_5,A7B7); */
nor gn1_7_6(n1_7_6, S8_5, C7_5);
nor gn2_7_6(n2_7_6, n1_7_6, C7_5);
nor gn3_7_6(n3_7_6, S8_5, n1_7_6);
nor gn4_7_6(n4_7_6, n2_7_6, n3_7_6);
nor gn5_7_6(n5_7_6, A7B7, n4_7_6);
nor gn6_7_6(n6_7_6, A7B7, n5_7_6);
nor gn7_7_6(n7_7_6, n4_7_6, n5_7_6);
nor gn8_7_6(S7_6, n6_7_6, n7_7_6);
nor gn9_7_6(C7_6, n1_7_6, n5_7_6);
/* FA MFA8_6(S8_6,C8_6,S9_5,C8_5,A8B7); */
nor gn1_8_6(n1_8_6, S9_5, C8_5);
nor gn2_8_6(n2_8_6, n1_8_6, C8_5);
nor gn3_8_6(n3_8_6, S9_5, n1_8_6);
nor gn4_8_6(n4_8_6, n2_8_6, n3_8_6);
nor gn5_8_6(n5_8_6, A8B7, n4_8_6);
nor gn6_8_6(n6_8_6, A8B7, n5_8_6);
nor gn7_8_6(n7_8_6, n4_8_6, n5_8_6);
nor gn8_8_6(S8_6, n6_8_6, n7_8_6);
nor gn9_8_6(C8_6, n1_8_6, n5_8_6);
/* FA MFA9_6(S9_6,C9_6,S10_5,C9_5,A9B7); */
nor gn1_9_6(n1_9_6, S10_5, C9_5);
nor gn2_9_6(n2_9_6, n1_9_6, C9_5);
nor gn3_9_6(n3_9_6, S10_5, n1_9_6);
nor gn4_9_6(n4_9_6, n2_9_6, n3_9_6);
nor gn5_9_6(n5_9_6, A9B7, n4_9_6);
nor gn6_9_6(n6_9_6, A9B7, n5_9_6);
nor gn7_9_6(n7_9_6, n4_9_6, n5_9_6);
nor gn8_9_6(S9_6, n6_9_6, n7_9_6);
nor gn9_9_6(C9_6, n1_9_6, n5_9_6);
/* FA MFA10_6(S10_6,C10_6,S11_5,C10_5,A10B7); */
nor gn1_10_6(n1_10_6, S11_5, C10_5);
nor gn2_10_6(n2_10_6, n1_10_6, C10_5);
nor gn3_10_6(n3_10_6, S11_5, n1_10_6);
nor gn4_10_6(n4_10_6, n2_10_6, n3_10_6);
nor gn5_10_6(n5_10_6, A10B7, n4_10_6);
nor gn6_10_6(n6_10_6, A10B7, n5_10_6);
nor gn7_10_6(n7_10_6, n4_10_6, n5_10_6);
nor gn8_10_6(S10_6, n6_10_6, n7_10_6);
nor gn9_10_6(C10_6, n1_10_6, n5_10_6);
/* FA MFA11_6(S11_6,C11_6,S12_5,C11_5,A11B7); */
nor gn1_11_6(n1_11_6, S12_5, C11_5);
nor gn2_11_6(n2_11_6, n1_11_6, C11_5);
nor gn3_11_6(n3_11_6, S12_5, n1_11_6);
nor gn4_11_6(n4_11_6, n2_11_6, n3_11_6);
nor gn5_11_6(n5_11_6, A11B7, n4_11_6);
nor gn6_11_6(n6_11_6, A11B7, n5_11_6);
nor gn7_11_6(n7_11_6, n4_11_6, n5_11_6);
nor gn8_11_6(S11_6, n6_11_6, n7_11_6);
nor gn9_11_6(C11_6, n1_11_6, n5_11_6);
/* FA MFA12_6(S12_6,C12_6,S13_5,C12_5,A12B7); */
nor gn1_12_6(n1_12_6, S13_5, C12_5);
nor gn2_12_6(n2_12_6, n1_12_6, C12_5);
nor gn3_12_6(n3_12_6, S13_5, n1_12_6);
nor gn4_12_6(n4_12_6, n2_12_6, n3_12_6);
nor gn5_12_6(n5_12_6, A12B7, n4_12_6);
nor gn6_12_6(n6_12_6, A12B7, n5_12_6);
nor gn7_12_6(n7_12_6, n4_12_6, n5_12_6);
nor gn8_12_6(S12_6, n6_12_6, n7_12_6);
nor gn9_12_6(C12_6, n1_12_6, n5_12_6);
/* FA MFA13_6(S13_6,C13_6,S14_5,C13_5,A13B7); */
nor gn1_13_6(n1_13_6, S14_5, C13_5);
nor gn2_13_6(n2_13_6, n1_13_6, C13_5);
nor gn3_13_6(n3_13_6, S14_5, n1_13_6);
nor gn4_13_6(n4_13_6, n2_13_6, n3_13_6);
nor gn5_13_6(n5_13_6, A13B7, n4_13_6);
nor gn6_13_6(n6_13_6, A13B7, n5_13_6);
nor gn7_13_6(n7_13_6, n4_13_6, n5_13_6);
nor gn8_13_6(S13_6, n6_13_6, n7_13_6);
nor gn9_13_6(C13_6, n1_13_6, n5_13_6);
/* FA MFA14_6(S14_6,C14_6,A15B6,C14_5,A14B7); */
nor gn1_14_6(n1_14_6, A15B6, C14_5);
nor gn2_14_6(n2_14_6, n1_14_6, C14_5);
nor gn3_14_6(n3_14_6, A15B6, n1_14_6);
nor gn4_14_6(n4_14_6, n2_14_6, n3_14_6);
nor gn5_14_6(n5_14_6, A14B7, n4_14_6);
nor gn6_14_6(n6_14_6, A14B7, n5_14_6);
nor gn7_14_6(n7_14_6, n4_14_6, n5_14_6);
nor gn8_14_6(S14_6, n6_14_6, n7_14_6);
nor gn9_14_6(C14_6, n1_14_6, n5_14_6);
/* FA MFA0_7(S0_7,C0_7,S1_6,C0_6,A0B8); */
nor gn1_0_7(n1_0_7, S1_6, C0_6);
nor gn2_0_7(n2_0_7, n1_0_7, C0_6);
nor gn3_0_7(n3_0_7, S1_6, n1_0_7);
nor gn4_0_7(n4_0_7, n2_0_7, n3_0_7);
nor gn5_0_7(n5_0_7, A0B8, n4_0_7);
nor gn6_0_7(n6_0_7, A0B8, n5_0_7);
nor gn7_0_7(n7_0_7, n4_0_7, n5_0_7);
nor gn8_0_7(S0_7, n6_0_7, n7_0_7);
nor gn9_0_7(C0_7, n1_0_7, n5_0_7);
/* FA MFA1_7(S1_7,C1_7,S2_6,C1_6,A1B8); */
nor gn1_1_7(n1_1_7, S2_6, C1_6);
nor gn2_1_7(n2_1_7, n1_1_7, C1_6);
nor gn3_1_7(n3_1_7, S2_6, n1_1_7);
nor gn4_1_7(n4_1_7, n2_1_7, n3_1_7);
nor gn5_1_7(n5_1_7, A1B8, n4_1_7);
nor gn6_1_7(n6_1_7, A1B8, n5_1_7);
nor gn7_1_7(n7_1_7, n4_1_7, n5_1_7);
nor gn8_1_7(S1_7, n6_1_7, n7_1_7);
nor gn9_1_7(C1_7, n1_1_7, n5_1_7);
/* FA MFA2_7(S2_7,C2_7,S3_6,C2_6,A2B8); */
nor gn1_2_7(n1_2_7, S3_6, C2_6);
nor gn2_2_7(n2_2_7, n1_2_7, C2_6);
nor gn3_2_7(n3_2_7, S3_6, n1_2_7);
nor gn4_2_7(n4_2_7, n2_2_7, n3_2_7);
nor gn5_2_7(n5_2_7, A2B8, n4_2_7);
nor gn6_2_7(n6_2_7, A2B8, n5_2_7);
nor gn7_2_7(n7_2_7, n4_2_7, n5_2_7);
nor gn8_2_7(S2_7, n6_2_7, n7_2_7);
nor gn9_2_7(C2_7, n1_2_7, n5_2_7);
/* FA MFA3_7(S3_7,C3_7,S4_6,C3_6,A3B8); */
nor gn1_3_7(n1_3_7, S4_6, C3_6);
nor gn2_3_7(n2_3_7, n1_3_7, C3_6);
nor gn3_3_7(n3_3_7, S4_6, n1_3_7);
nor gn4_3_7(n4_3_7, n2_3_7, n3_3_7);
nor gn5_3_7(n5_3_7, A3B8, n4_3_7);
nor gn6_3_7(n6_3_7, A3B8, n5_3_7);
nor gn7_3_7(n7_3_7, n4_3_7, n5_3_7);
nor gn8_3_7(S3_7, n6_3_7, n7_3_7);
nor gn9_3_7(C3_7, n1_3_7, n5_3_7);
/* FA MFA4_7(S4_7,C4_7,S5_6,C4_6,A4B8); */
nor gn1_4_7(n1_4_7, S5_6, C4_6);
nor gn2_4_7(n2_4_7, n1_4_7, C4_6);
nor gn3_4_7(n3_4_7, S5_6, n1_4_7);
nor gn4_4_7(n4_4_7, n2_4_7, n3_4_7);
nor gn5_4_7(n5_4_7, A4B8, n4_4_7);
nor gn6_4_7(n6_4_7, A4B8, n5_4_7);
nor gn7_4_7(n7_4_7, n4_4_7, n5_4_7);
nor gn8_4_7(S4_7, n6_4_7, n7_4_7);
nor gn9_4_7(C4_7, n1_4_7, n5_4_7);
/* FA MFA5_7(S5_7,C5_7,S6_6,C5_6,A5B8); */
nor gn1_5_7(n1_5_7, S6_6, C5_6);
nor gn2_5_7(n2_5_7, n1_5_7, C5_6);
nor gn3_5_7(n3_5_7, S6_6, n1_5_7);
nor gn4_5_7(n4_5_7, n2_5_7, n3_5_7);
nor gn5_5_7(n5_5_7, A5B8, n4_5_7);
nor gn6_5_7(n6_5_7, A5B8, n5_5_7);
nor gn7_5_7(n7_5_7, n4_5_7, n5_5_7);
nor gn8_5_7(S5_7, n6_5_7, n7_5_7);
nor gn9_5_7(C5_7, n1_5_7, n5_5_7);
/* FA MFA6_7(S6_7,C6_7,S7_6,C6_6,A6B8); */
nor gn1_6_7(n1_6_7, S7_6, C6_6);
nor gn2_6_7(n2_6_7, n1_6_7, C6_6);
nor gn3_6_7(n3_6_7, S7_6, n1_6_7);
nor gn4_6_7(n4_6_7, n2_6_7, n3_6_7);
nor gn5_6_7(n5_6_7, A6B8, n4_6_7);
nor gn6_6_7(n6_6_7, A6B8, n5_6_7);
nor gn7_6_7(n7_6_7, n4_6_7, n5_6_7);
nor gn8_6_7(S6_7, n6_6_7, n7_6_7);
nor gn9_6_7(C6_7, n1_6_7, n5_6_7);
/* FA MFA7_7(S7_7,C7_7,S8_6,C7_6,A7B8); */
nor gn1_7_7(n1_7_7, S8_6, C7_6);
nor gn2_7_7(n2_7_7, n1_7_7, C7_6);
nor gn3_7_7(n3_7_7, S8_6, n1_7_7);
nor gn4_7_7(n4_7_7, n2_7_7, n3_7_7);
nor gn5_7_7(n5_7_7, A7B8, n4_7_7);
nor gn6_7_7(n6_7_7, A7B8, n5_7_7);
nor gn7_7_7(n7_7_7, n4_7_7, n5_7_7);
nor gn8_7_7(S7_7, n6_7_7, n7_7_7);
nor gn9_7_7(C7_7, n1_7_7, n5_7_7);
/* FA MFA8_7(S8_7,C8_7,S9_6,C8_6,A8B8); */
nor gn1_8_7(n1_8_7, S9_6, C8_6);
nor gn2_8_7(n2_8_7, n1_8_7, C8_6);
nor gn3_8_7(n3_8_7, S9_6, n1_8_7);
nor gn4_8_7(n4_8_7, n2_8_7, n3_8_7);
nor gn5_8_7(n5_8_7, A8B8, n4_8_7);
nor gn6_8_7(n6_8_7, A8B8, n5_8_7);
nor gn7_8_7(n7_8_7, n4_8_7, n5_8_7);
nor gn8_8_7(S8_7, n6_8_7, n7_8_7);
nor gn9_8_7(C8_7, n1_8_7, n5_8_7);
/* FA MFA9_7(S9_7,C9_7,S10_6,C9_6,A9B8); */
nor gn1_9_7(n1_9_7, S10_6, C9_6);
nor gn2_9_7(n2_9_7, n1_9_7, C9_6);
nor gn3_9_7(n3_9_7, S10_6, n1_9_7);
nor gn4_9_7(n4_9_7, n2_9_7, n3_9_7);
nor gn5_9_7(n5_9_7, A9B8, n4_9_7);
nor gn6_9_7(n6_9_7, A9B8, n5_9_7);
nor gn7_9_7(n7_9_7, n4_9_7, n5_9_7);
nor gn8_9_7(S9_7, n6_9_7, n7_9_7);
nor gn9_9_7(C9_7, n1_9_7, n5_9_7);
/* FA MFA10_7(S10_7,C10_7,S11_6,C10_6,A10B8); */
nor gn1_10_7(n1_10_7, S11_6, C10_6);
nor gn2_10_7(n2_10_7, n1_10_7, C10_6);
nor gn3_10_7(n3_10_7, S11_6, n1_10_7);
nor gn4_10_7(n4_10_7, n2_10_7, n3_10_7);
nor gn5_10_7(n5_10_7, A10B8, n4_10_7);
nor gn6_10_7(n6_10_7, A10B8, n5_10_7);
nor gn7_10_7(n7_10_7, n4_10_7, n5_10_7);
nor gn8_10_7(S10_7, n6_10_7, n7_10_7);
nor gn9_10_7(C10_7, n1_10_7, n5_10_7);
/* FA MFA11_7(S11_7,C11_7,S12_6,C11_6,A11B8); */
nor gn1_11_7(n1_11_7, S12_6, C11_6);
nor gn2_11_7(n2_11_7, n1_11_7, C11_6);
nor gn3_11_7(n3_11_7, S12_6, n1_11_7);
nor gn4_11_7(n4_11_7, n2_11_7, n3_11_7);
nor gn5_11_7(n5_11_7, A11B8, n4_11_7);
nor gn6_11_7(n6_11_7, A11B8, n5_11_7);
nor gn7_11_7(n7_11_7, n4_11_7, n5_11_7);
nor gn8_11_7(S11_7, n6_11_7, n7_11_7);
nor gn9_11_7(C11_7, n1_11_7, n5_11_7);
/* FA MFA12_7(S12_7,C12_7,S13_6,C12_6,A12B8); */
nor gn1_12_7(n1_12_7, S13_6, C12_6);
nor gn2_12_7(n2_12_7, n1_12_7, C12_6);
nor gn3_12_7(n3_12_7, S13_6, n1_12_7);
nor gn4_12_7(n4_12_7, n2_12_7, n3_12_7);
nor gn5_12_7(n5_12_7, A12B8, n4_12_7);
nor gn6_12_7(n6_12_7, A12B8, n5_12_7);
nor gn7_12_7(n7_12_7, n4_12_7, n5_12_7);
nor gn8_12_7(S12_7, n6_12_7, n7_12_7);
nor gn9_12_7(C12_7, n1_12_7, n5_12_7);
/* FA MFA13_7(S13_7,C13_7,S14_6,C13_6,A13B8); */
nor gn1_13_7(n1_13_7, S14_6, C13_6);
nor gn2_13_7(n2_13_7, n1_13_7, C13_6);
nor gn3_13_7(n3_13_7, S14_6, n1_13_7);
nor gn4_13_7(n4_13_7, n2_13_7, n3_13_7);
nor gn5_13_7(n5_13_7, A13B8, n4_13_7);
nor gn6_13_7(n6_13_7, A13B8, n5_13_7);
nor gn7_13_7(n7_13_7, n4_13_7, n5_13_7);
nor gn8_13_7(S13_7, n6_13_7, n7_13_7);
nor gn9_13_7(C13_7, n1_13_7, n5_13_7);
/* FA MFA14_7(S14_7,C14_7,A15B7,C14_6,A14B8); */
nor gn1_14_7(n1_14_7, A15B7, C14_6);
nor gn2_14_7(n2_14_7, n1_14_7, C14_6);
nor gn3_14_7(n3_14_7, A15B7, n1_14_7);
nor gn4_14_7(n4_14_7, n2_14_7, n3_14_7);
nor gn5_14_7(n5_14_7, A14B8, n4_14_7);
nor gn6_14_7(n6_14_7, A14B8, n5_14_7);
nor gn7_14_7(n7_14_7, n4_14_7, n5_14_7);
nor gn8_14_7(S14_7, n6_14_7, n7_14_7);
nor gn9_14_7(C14_7, n1_14_7, n5_14_7);
/* FA MFA0_8(S0_8,C0_8,S1_7,C0_7,A0B9); */
nor gn1_0_8(n1_0_8, S1_7, C0_7);
nor gn2_0_8(n2_0_8, n1_0_8, C0_7);
nor gn3_0_8(n3_0_8, S1_7, n1_0_8);
nor gn4_0_8(n4_0_8, n2_0_8, n3_0_8);
nor gn5_0_8(n5_0_8, A0B9, n4_0_8);
nor gn6_0_8(n6_0_8, A0B9, n5_0_8);
nor gn7_0_8(n7_0_8, n4_0_8, n5_0_8);
nor gn8_0_8(S0_8, n6_0_8, n7_0_8);
nor gn9_0_8(C0_8, n1_0_8, n5_0_8);
/* FA MFA1_8(S1_8,C1_8,S2_7,C1_7,A1B9); */
nor gn1_1_8(n1_1_8, S2_7, C1_7);
nor gn2_1_8(n2_1_8, n1_1_8, C1_7);
nor gn3_1_8(n3_1_8, S2_7, n1_1_8);
nor gn4_1_8(n4_1_8, n2_1_8, n3_1_8);
nor gn5_1_8(n5_1_8, A1B9, n4_1_8);
nor gn6_1_8(n6_1_8, A1B9, n5_1_8);
nor gn7_1_8(n7_1_8, n4_1_8, n5_1_8);
nor gn8_1_8(S1_8, n6_1_8, n7_1_8);
nor gn9_1_8(C1_8, n1_1_8, n5_1_8);
/* FA MFA2_8(S2_8,C2_8,S3_7,C2_7,A2B9); */
nor gn1_2_8(n1_2_8, S3_7, C2_7);
nor gn2_2_8(n2_2_8, n1_2_8, C2_7);
nor gn3_2_8(n3_2_8, S3_7, n1_2_8);
nor gn4_2_8(n4_2_8, n2_2_8, n3_2_8);
nor gn5_2_8(n5_2_8, A2B9, n4_2_8);
nor gn6_2_8(n6_2_8, A2B9, n5_2_8);
nor gn7_2_8(n7_2_8, n4_2_8, n5_2_8);
nor gn8_2_8(S2_8, n6_2_8, n7_2_8);
nor gn9_2_8(C2_8, n1_2_8, n5_2_8);
/* FA MFA3_8(S3_8,C3_8,S4_7,C3_7,A3B9); */
nor gn1_3_8(n1_3_8, S4_7, C3_7);
nor gn2_3_8(n2_3_8, n1_3_8, C3_7);
nor gn3_3_8(n3_3_8, S4_7, n1_3_8);
nor gn4_3_8(n4_3_8, n2_3_8, n3_3_8);
nor gn5_3_8(n5_3_8, A3B9, n4_3_8);
nor gn6_3_8(n6_3_8, A3B9, n5_3_8);
nor gn7_3_8(n7_3_8, n4_3_8, n5_3_8);
nor gn8_3_8(S3_8, n6_3_8, n7_3_8);
nor gn9_3_8(C3_8, n1_3_8, n5_3_8);
/* FA MFA4_8(S4_8,C4_8,S5_7,C4_7,A4B9); */
nor gn1_4_8(n1_4_8, S5_7, C4_7);
nor gn2_4_8(n2_4_8, n1_4_8, C4_7);
nor gn3_4_8(n3_4_8, S5_7, n1_4_8);
nor gn4_4_8(n4_4_8, n2_4_8, n3_4_8);
nor gn5_4_8(n5_4_8, A4B9, n4_4_8);
nor gn6_4_8(n6_4_8, A4B9, n5_4_8);
nor gn7_4_8(n7_4_8, n4_4_8, n5_4_8);
nor gn8_4_8(S4_8, n6_4_8, n7_4_8);
nor gn9_4_8(C4_8, n1_4_8, n5_4_8);
/* FA MFA5_8(S5_8,C5_8,S6_7,C5_7,A5B9); */
nor gn1_5_8(n1_5_8, S6_7, C5_7);
nor gn2_5_8(n2_5_8, n1_5_8, C5_7);
nor gn3_5_8(n3_5_8, S6_7, n1_5_8);
nor gn4_5_8(n4_5_8, n2_5_8, n3_5_8);
nor gn5_5_8(n5_5_8, A5B9, n4_5_8);
nor gn6_5_8(n6_5_8, A5B9, n5_5_8);
nor gn7_5_8(n7_5_8, n4_5_8, n5_5_8);
nor gn8_5_8(S5_8, n6_5_8, n7_5_8);
nor gn9_5_8(C5_8, n1_5_8, n5_5_8);
/* FA MFA6_8(S6_8,C6_8,S7_7,C6_7,A6B9); */
nor gn1_6_8(n1_6_8, S7_7, C6_7);
nor gn2_6_8(n2_6_8, n1_6_8, C6_7);
nor gn3_6_8(n3_6_8, S7_7, n1_6_8);
nor gn4_6_8(n4_6_8, n2_6_8, n3_6_8);
nor gn5_6_8(n5_6_8, A6B9, n4_6_8);
nor gn6_6_8(n6_6_8, A6B9, n5_6_8);
nor gn7_6_8(n7_6_8, n4_6_8, n5_6_8);
nor gn8_6_8(S6_8, n6_6_8, n7_6_8);
nor gn9_6_8(C6_8, n1_6_8, n5_6_8);
/* FA MFA7_8(S7_8,C7_8,S8_7,C7_7,A7B9); */
nor gn1_7_8(n1_7_8, S8_7, C7_7);
nor gn2_7_8(n2_7_8, n1_7_8, C7_7);
nor gn3_7_8(n3_7_8, S8_7, n1_7_8);
nor gn4_7_8(n4_7_8, n2_7_8, n3_7_8);
nor gn5_7_8(n5_7_8, A7B9, n4_7_8);
nor gn6_7_8(n6_7_8, A7B9, n5_7_8);
nor gn7_7_8(n7_7_8, n4_7_8, n5_7_8);
nor gn8_7_8(S7_8, n6_7_8, n7_7_8);
nor gn9_7_8(C7_8, n1_7_8, n5_7_8);
/* FA MFA8_8(S8_8,C8_8,S9_7,C8_7,A8B9); */
nor gn1_8_8(n1_8_8, S9_7, C8_7);
nor gn2_8_8(n2_8_8, n1_8_8, C8_7);
nor gn3_8_8(n3_8_8, S9_7, n1_8_8);
nor gn4_8_8(n4_8_8, n2_8_8, n3_8_8);
nor gn5_8_8(n5_8_8, A8B9, n4_8_8);
nor gn6_8_8(n6_8_8, A8B9, n5_8_8);
nor gn7_8_8(n7_8_8, n4_8_8, n5_8_8);
nor gn8_8_8(S8_8, n6_8_8, n7_8_8);
nor gn9_8_8(C8_8, n1_8_8, n5_8_8);
/* FA MFA9_8(S9_8,C9_8,S10_7,C9_7,A9B9); */
nor gn1_9_8(n1_9_8, S10_7, C9_7);
nor gn2_9_8(n2_9_8, n1_9_8, C9_7);
nor gn3_9_8(n3_9_8, S10_7, n1_9_8);
nor gn4_9_8(n4_9_8, n2_9_8, n3_9_8);
nor gn5_9_8(n5_9_8, A9B9, n4_9_8);
nor gn6_9_8(n6_9_8, A9B9, n5_9_8);
nor gn7_9_8(n7_9_8, n4_9_8, n5_9_8);
nor gn8_9_8(S9_8, n6_9_8, n7_9_8);
nor gn9_9_8(C9_8, n1_9_8, n5_9_8);
/* FA MFA10_8(S10_8,C10_8,S11_7,C10_7,A10B9); */
nor gn1_10_8(n1_10_8, S11_7, C10_7);
nor gn2_10_8(n2_10_8, n1_10_8, C10_7);
nor gn3_10_8(n3_10_8, S11_7, n1_10_8);
nor gn4_10_8(n4_10_8, n2_10_8, n3_10_8);
nor gn5_10_8(n5_10_8, A10B9, n4_10_8);
nor gn6_10_8(n6_10_8, A10B9, n5_10_8);
nor gn7_10_8(n7_10_8, n4_10_8, n5_10_8);
nor gn8_10_8(S10_8, n6_10_8, n7_10_8);
nor gn9_10_8(C10_8, n1_10_8, n5_10_8);
/* FA MFA11_8(S11_8,C11_8,S12_7,C11_7,A11B9); */
nor gn1_11_8(n1_11_8, S12_7, C11_7);
nor gn2_11_8(n2_11_8, n1_11_8, C11_7);
nor gn3_11_8(n3_11_8, S12_7, n1_11_8);
nor gn4_11_8(n4_11_8, n2_11_8, n3_11_8);
nor gn5_11_8(n5_11_8, A11B9, n4_11_8);
nor gn6_11_8(n6_11_8, A11B9, n5_11_8);
nor gn7_11_8(n7_11_8, n4_11_8, n5_11_8);
nor gn8_11_8(S11_8, n6_11_8, n7_11_8);
nor gn9_11_8(C11_8, n1_11_8, n5_11_8);
/* FA MFA12_8(S12_8,C12_8,S13_7,C12_7,A12B9); */
nor gn1_12_8(n1_12_8, S13_7, C12_7);
nor gn2_12_8(n2_12_8, n1_12_8, C12_7);
nor gn3_12_8(n3_12_8, S13_7, n1_12_8);
nor gn4_12_8(n4_12_8, n2_12_8, n3_12_8);
nor gn5_12_8(n5_12_8, A12B9, n4_12_8);
nor gn6_12_8(n6_12_8, A12B9, n5_12_8);
nor gn7_12_8(n7_12_8, n4_12_8, n5_12_8);
nor gn8_12_8(S12_8, n6_12_8, n7_12_8);
nor gn9_12_8(C12_8, n1_12_8, n5_12_8);
/* FA MFA13_8(S13_8,C13_8,S14_7,C13_7,A13B9); */
nor gn1_13_8(n1_13_8, S14_7, C13_7);
nor gn2_13_8(n2_13_8, n1_13_8, C13_7);
nor gn3_13_8(n3_13_8, S14_7, n1_13_8);
nor gn4_13_8(n4_13_8, n2_13_8, n3_13_8);
nor gn5_13_8(n5_13_8, A13B9, n4_13_8);
nor gn6_13_8(n6_13_8, A13B9, n5_13_8);
nor gn7_13_8(n7_13_8, n4_13_8, n5_13_8);
nor gn8_13_8(S13_8, n6_13_8, n7_13_8);
nor gn9_13_8(C13_8, n1_13_8, n5_13_8);
/* FA MFA14_8(S14_8,C14_8,A15B8,C14_7,A14B9); */
nor gn1_14_8(n1_14_8, A15B8, C14_7);
nor gn2_14_8(n2_14_8, n1_14_8, C14_7);
nor gn3_14_8(n3_14_8, A15B8, n1_14_8);
nor gn4_14_8(n4_14_8, n2_14_8, n3_14_8);
nor gn5_14_8(n5_14_8, A14B9, n4_14_8);
nor gn6_14_8(n6_14_8, A14B9, n5_14_8);
nor gn7_14_8(n7_14_8, n4_14_8, n5_14_8);
nor gn8_14_8(S14_8, n6_14_8, n7_14_8);
nor gn9_14_8(C14_8, n1_14_8, n5_14_8);
/* FA MFA0_9(S0_9,C0_9,S1_8,C0_8,A0B10); */
nor gn1_0_9(n1_0_9, S1_8, C0_8);
nor gn2_0_9(n2_0_9, n1_0_9, C0_8);
nor gn3_0_9(n3_0_9, S1_8, n1_0_9);
nor gn4_0_9(n4_0_9, n2_0_9, n3_0_9);
nor gn5_0_9(n5_0_9, A0B10, n4_0_9);
nor gn6_0_9(n6_0_9, A0B10, n5_0_9);
nor gn7_0_9(n7_0_9, n4_0_9, n5_0_9);
nor gn8_0_9(S0_9, n6_0_9, n7_0_9);
nor gn9_0_9(C0_9, n1_0_9, n5_0_9);
/* FA MFA1_9(S1_9,C1_9,S2_8,C1_8,A1B10); */
nor gn1_1_9(n1_1_9, S2_8, C1_8);
nor gn2_1_9(n2_1_9, n1_1_9, C1_8);
nor gn3_1_9(n3_1_9, S2_8, n1_1_9);
nor gn4_1_9(n4_1_9, n2_1_9, n3_1_9);
nor gn5_1_9(n5_1_9, A1B10, n4_1_9);
nor gn6_1_9(n6_1_9, A1B10, n5_1_9);
nor gn7_1_9(n7_1_9, n4_1_9, n5_1_9);
nor gn8_1_9(S1_9, n6_1_9, n7_1_9);
nor gn9_1_9(C1_9, n1_1_9, n5_1_9);
/* FA MFA2_9(S2_9,C2_9,S3_8,C2_8,A2B10); */
nor gn1_2_9(n1_2_9, S3_8, C2_8);
nor gn2_2_9(n2_2_9, n1_2_9, C2_8);
nor gn3_2_9(n3_2_9, S3_8, n1_2_9);
nor gn4_2_9(n4_2_9, n2_2_9, n3_2_9);
nor gn5_2_9(n5_2_9, A2B10, n4_2_9);
nor gn6_2_9(n6_2_9, A2B10, n5_2_9);
nor gn7_2_9(n7_2_9, n4_2_9, n5_2_9);
nor gn8_2_9(S2_9, n6_2_9, n7_2_9);
nor gn9_2_9(C2_9, n1_2_9, n5_2_9);
/* FA MFA3_9(S3_9,C3_9,S4_8,C3_8,A3B10); */
nor gn1_3_9(n1_3_9, S4_8, C3_8);
nor gn2_3_9(n2_3_9, n1_3_9, C3_8);
nor gn3_3_9(n3_3_9, S4_8, n1_3_9);
nor gn4_3_9(n4_3_9, n2_3_9, n3_3_9);
nor gn5_3_9(n5_3_9, A3B10, n4_3_9);
nor gn6_3_9(n6_3_9, A3B10, n5_3_9);
nor gn7_3_9(n7_3_9, n4_3_9, n5_3_9);
nor gn8_3_9(S3_9, n6_3_9, n7_3_9);
nor gn9_3_9(C3_9, n1_3_9, n5_3_9);
/* FA MFA4_9(S4_9,C4_9,S5_8,C4_8,A4B10); */
nor gn1_4_9(n1_4_9, S5_8, C4_8);
nor gn2_4_9(n2_4_9, n1_4_9, C4_8);
nor gn3_4_9(n3_4_9, S5_8, n1_4_9);
nor gn4_4_9(n4_4_9, n2_4_9, n3_4_9);
nor gn5_4_9(n5_4_9, A4B10, n4_4_9);
nor gn6_4_9(n6_4_9, A4B10, n5_4_9);
nor gn7_4_9(n7_4_9, n4_4_9, n5_4_9);
nor gn8_4_9(S4_9, n6_4_9, n7_4_9);
nor gn9_4_9(C4_9, n1_4_9, n5_4_9);
/* FA MFA5_9(S5_9,C5_9,S6_8,C5_8,A5B10); */
nor gn1_5_9(n1_5_9, S6_8, C5_8);
nor gn2_5_9(n2_5_9, n1_5_9, C5_8);
nor gn3_5_9(n3_5_9, S6_8, n1_5_9);
nor gn4_5_9(n4_5_9, n2_5_9, n3_5_9);
nor gn5_5_9(n5_5_9, A5B10, n4_5_9);
nor gn6_5_9(n6_5_9, A5B10, n5_5_9);
nor gn7_5_9(n7_5_9, n4_5_9, n5_5_9);
nor gn8_5_9(S5_9, n6_5_9, n7_5_9);
nor gn9_5_9(C5_9, n1_5_9, n5_5_9);
/* FA MFA6_9(S6_9,C6_9,S7_8,C6_8,A6B10); */
nor gn1_6_9(n1_6_9, S7_8, C6_8);
nor gn2_6_9(n2_6_9, n1_6_9, C6_8);
nor gn3_6_9(n3_6_9, S7_8, n1_6_9);
nor gn4_6_9(n4_6_9, n2_6_9, n3_6_9);
nor gn5_6_9(n5_6_9, A6B10, n4_6_9);
nor gn6_6_9(n6_6_9, A6B10, n5_6_9);
nor gn7_6_9(n7_6_9, n4_6_9, n5_6_9);
nor gn8_6_9(S6_9, n6_6_9, n7_6_9);
nor gn9_6_9(C6_9, n1_6_9, n5_6_9);
/* FA MFA7_9(S7_9,C7_9,S8_8,C7_8,A7B10); */
nor gn1_7_9(n1_7_9, S8_8, C7_8);
nor gn2_7_9(n2_7_9, n1_7_9, C7_8);
nor gn3_7_9(n3_7_9, S8_8, n1_7_9);
nor gn4_7_9(n4_7_9, n2_7_9, n3_7_9);
nor gn5_7_9(n5_7_9, A7B10, n4_7_9);
nor gn6_7_9(n6_7_9, A7B10, n5_7_9);
nor gn7_7_9(n7_7_9, n4_7_9, n5_7_9);
nor gn8_7_9(S7_9, n6_7_9, n7_7_9);
nor gn9_7_9(C7_9, n1_7_9, n5_7_9);
/* FA MFA8_9(S8_9,C8_9,S9_8,C8_8,A8B10); */
nor gn1_8_9(n1_8_9, S9_8, C8_8);
nor gn2_8_9(n2_8_9, n1_8_9, C8_8);
nor gn3_8_9(n3_8_9, S9_8, n1_8_9);
nor gn4_8_9(n4_8_9, n2_8_9, n3_8_9);
nor gn5_8_9(n5_8_9, A8B10, n4_8_9);
nor gn6_8_9(n6_8_9, A8B10, n5_8_9);
nor gn7_8_9(n7_8_9, n4_8_9, n5_8_9);
nor gn8_8_9(S8_9, n6_8_9, n7_8_9);
nor gn9_8_9(C8_9, n1_8_9, n5_8_9);
/* FA MFA9_9(S9_9,C9_9,S10_8,C9_8,A9B10); */
nor gn1_9_9(n1_9_9, S10_8, C9_8);
nor gn2_9_9(n2_9_9, n1_9_9, C9_8);
nor gn3_9_9(n3_9_9, S10_8, n1_9_9);
nor gn4_9_9(n4_9_9, n2_9_9, n3_9_9);
nor gn5_9_9(n5_9_9, A9B10, n4_9_9);
nor gn6_9_9(n6_9_9, A9B10, n5_9_9);
nor gn7_9_9(n7_9_9, n4_9_9, n5_9_9);
nor gn8_9_9(S9_9, n6_9_9, n7_9_9);
nor gn9_9_9(C9_9, n1_9_9, n5_9_9);
/* FA MFA10_9(S10_9,C10_9,S11_8,C10_8,A10B10); */
nor gn1_10_9(n1_10_9, S11_8, C10_8);
nor gn2_10_9(n2_10_9, n1_10_9, C10_8);
nor gn3_10_9(n3_10_9, S11_8, n1_10_9);
nor gn4_10_9(n4_10_9, n2_10_9, n3_10_9);
nor gn5_10_9(n5_10_9, A10B10, n4_10_9);
nor gn6_10_9(n6_10_9, A10B10, n5_10_9);
nor gn7_10_9(n7_10_9, n4_10_9, n5_10_9);
nor gn8_10_9(S10_9, n6_10_9, n7_10_9);
nor gn9_10_9(C10_9, n1_10_9, n5_10_9);
/* FA MFA11_9(S11_9,C11_9,S12_8,C11_8,A11B10); */
nor gn1_11_9(n1_11_9, S12_8, C11_8);
nor gn2_11_9(n2_11_9, n1_11_9, C11_8);
nor gn3_11_9(n3_11_9, S12_8, n1_11_9);
nor gn4_11_9(n4_11_9, n2_11_9, n3_11_9);
nor gn5_11_9(n5_11_9, A11B10, n4_11_9);
nor gn6_11_9(n6_11_9, A11B10, n5_11_9);
nor gn7_11_9(n7_11_9, n4_11_9, n5_11_9);
nor gn8_11_9(S11_9, n6_11_9, n7_11_9);
nor gn9_11_9(C11_9, n1_11_9, n5_11_9);
/* FA MFA12_9(S12_9,C12_9,S13_8,C12_8,A12B10); */
nor gn1_12_9(n1_12_9, S13_8, C12_8);
nor gn2_12_9(n2_12_9, n1_12_9, C12_8);
nor gn3_12_9(n3_12_9, S13_8, n1_12_9);
nor gn4_12_9(n4_12_9, n2_12_9, n3_12_9);
nor gn5_12_9(n5_12_9, A12B10, n4_12_9);
nor gn6_12_9(n6_12_9, A12B10, n5_12_9);
nor gn7_12_9(n7_12_9, n4_12_9, n5_12_9);
nor gn8_12_9(S12_9, n6_12_9, n7_12_9);
nor gn9_12_9(C12_9, n1_12_9, n5_12_9);
/* FA MFA13_9(S13_9,C13_9,S14_8,C13_8,A13B10); */
nor gn1_13_9(n1_13_9, S14_8, C13_8);
nor gn2_13_9(n2_13_9, n1_13_9, C13_8);
nor gn3_13_9(n3_13_9, S14_8, n1_13_9);
nor gn4_13_9(n4_13_9, n2_13_9, n3_13_9);
nor gn5_13_9(n5_13_9, A13B10, n4_13_9);
nor gn6_13_9(n6_13_9, A13B10, n5_13_9);
nor gn7_13_9(n7_13_9, n4_13_9, n5_13_9);
nor gn8_13_9(S13_9, n6_13_9, n7_13_9);
nor gn9_13_9(C13_9, n1_13_9, n5_13_9);
/* FA MFA14_9(S14_9,C14_9,A15B9,C14_8,A14B10); */
nor gn1_14_9(n1_14_9, A15B9, C14_8);
nor gn2_14_9(n2_14_9, n1_14_9, C14_8);
nor gn3_14_9(n3_14_9, A15B9, n1_14_9);
nor gn4_14_9(n4_14_9, n2_14_9, n3_14_9);
nor gn5_14_9(n5_14_9, A14B10, n4_14_9);
nor gn6_14_9(n6_14_9, A14B10, n5_14_9);
nor gn7_14_9(n7_14_9, n4_14_9, n5_14_9);
nor gn8_14_9(S14_9, n6_14_9, n7_14_9);
nor gn9_14_9(C14_9, n1_14_9, n5_14_9);
/* FA MFA0_10(S0_10,C0_10,S1_9,C0_9,A0B11); */
nor gn1_0_10(n1_0_10, S1_9, C0_9);
nor gn2_0_10(n2_0_10, n1_0_10, C0_9);
nor gn3_0_10(n3_0_10, S1_9, n1_0_10);
nor gn4_0_10(n4_0_10, n2_0_10, n3_0_10);
nor gn5_0_10(n5_0_10, A0B11, n4_0_10);
nor gn6_0_10(n6_0_10, A0B11, n5_0_10);
nor gn7_0_10(n7_0_10, n4_0_10, n5_0_10);
nor gn8_0_10(S0_10, n6_0_10, n7_0_10);
nor gn9_0_10(C0_10, n1_0_10, n5_0_10);
/* FA MFA1_10(S1_10,C1_10,S2_9,C1_9,A1B11); */
nor gn1_1_10(n1_1_10, S2_9, C1_9);
nor gn2_1_10(n2_1_10, n1_1_10, C1_9);
nor gn3_1_10(n3_1_10, S2_9, n1_1_10);
nor gn4_1_10(n4_1_10, n2_1_10, n3_1_10);
nor gn5_1_10(n5_1_10, A1B11, n4_1_10);
nor gn6_1_10(n6_1_10, A1B11, n5_1_10);
nor gn7_1_10(n7_1_10, n4_1_10, n5_1_10);
nor gn8_1_10(S1_10, n6_1_10, n7_1_10);
nor gn9_1_10(C1_10, n1_1_10, n5_1_10);
/* FA MFA2_10(S2_10,C2_10,S3_9,C2_9,A2B11); */
nor gn1_2_10(n1_2_10, S3_9, C2_9);
nor gn2_2_10(n2_2_10, n1_2_10, C2_9);
nor gn3_2_10(n3_2_10, S3_9, n1_2_10);
nor gn4_2_10(n4_2_10, n2_2_10, n3_2_10);
nor gn5_2_10(n5_2_10, A2B11, n4_2_10);
nor gn6_2_10(n6_2_10, A2B11, n5_2_10);
nor gn7_2_10(n7_2_10, n4_2_10, n5_2_10);
nor gn8_2_10(S2_10, n6_2_10, n7_2_10);
nor gn9_2_10(C2_10, n1_2_10, n5_2_10);
/* FA MFA3_10(S3_10,C3_10,S4_9,C3_9,A3B11); */
nor gn1_3_10(n1_3_10, S4_9, C3_9);
nor gn2_3_10(n2_3_10, n1_3_10, C3_9);
nor gn3_3_10(n3_3_10, S4_9, n1_3_10);
nor gn4_3_10(n4_3_10, n2_3_10, n3_3_10);
nor gn5_3_10(n5_3_10, A3B11, n4_3_10);
nor gn6_3_10(n6_3_10, A3B11, n5_3_10);
nor gn7_3_10(n7_3_10, n4_3_10, n5_3_10);
nor gn8_3_10(S3_10, n6_3_10, n7_3_10);
nor gn9_3_10(C3_10, n1_3_10, n5_3_10);
/* FA MFA4_10(S4_10,C4_10,S5_9,C4_9,A4B11); */
nor gn1_4_10(n1_4_10, S5_9, C4_9);
nor gn2_4_10(n2_4_10, n1_4_10, C4_9);
nor gn3_4_10(n3_4_10, S5_9, n1_4_10);
nor gn4_4_10(n4_4_10, n2_4_10, n3_4_10);
nor gn5_4_10(n5_4_10, A4B11, n4_4_10);
nor gn6_4_10(n6_4_10, A4B11, n5_4_10);
nor gn7_4_10(n7_4_10, n4_4_10, n5_4_10);
nor gn8_4_10(S4_10, n6_4_10, n7_4_10);
nor gn9_4_10(C4_10, n1_4_10, n5_4_10);
/* FA MFA5_10(S5_10,C5_10,S6_9,C5_9,A5B11); */
nor gn1_5_10(n1_5_10, S6_9, C5_9);
nor gn2_5_10(n2_5_10, n1_5_10, C5_9);
nor gn3_5_10(n3_5_10, S6_9, n1_5_10);
nor gn4_5_10(n4_5_10, n2_5_10, n3_5_10);
nor gn5_5_10(n5_5_10, A5B11, n4_5_10);
nor gn6_5_10(n6_5_10, A5B11, n5_5_10);
nor gn7_5_10(n7_5_10, n4_5_10, n5_5_10);
nor gn8_5_10(S5_10, n6_5_10, n7_5_10);
nor gn9_5_10(C5_10, n1_5_10, n5_5_10);
/* FA MFA6_10(S6_10,C6_10,S7_9,C6_9,A6B11); */
nor gn1_6_10(n1_6_10, S7_9, C6_9);
nor gn2_6_10(n2_6_10, n1_6_10, C6_9);
nor gn3_6_10(n3_6_10, S7_9, n1_6_10);
nor gn4_6_10(n4_6_10, n2_6_10, n3_6_10);
nor gn5_6_10(n5_6_10, A6B11, n4_6_10);
nor gn6_6_10(n6_6_10, A6B11, n5_6_10);
nor gn7_6_10(n7_6_10, n4_6_10, n5_6_10);
nor gn8_6_10(S6_10, n6_6_10, n7_6_10);
nor gn9_6_10(C6_10, n1_6_10, n5_6_10);
/* FA MFA7_10(S7_10,C7_10,S8_9,C7_9,A7B11); */
nor gn1_7_10(n1_7_10, S8_9, C7_9);
nor gn2_7_10(n2_7_10, n1_7_10, C7_9);
nor gn3_7_10(n3_7_10, S8_9, n1_7_10);
nor gn4_7_10(n4_7_10, n2_7_10, n3_7_10);
nor gn5_7_10(n5_7_10, A7B11, n4_7_10);
nor gn6_7_10(n6_7_10, A7B11, n5_7_10);
nor gn7_7_10(n7_7_10, n4_7_10, n5_7_10);
nor gn8_7_10(S7_10, n6_7_10, n7_7_10);
nor gn9_7_10(C7_10, n1_7_10, n5_7_10);
/* FA MFA8_10(S8_10,C8_10,S9_9,C8_9,A8B11); */
nor gn1_8_10(n1_8_10, S9_9, C8_9);
nor gn2_8_10(n2_8_10, n1_8_10, C8_9);
nor gn3_8_10(n3_8_10, S9_9, n1_8_10);
nor gn4_8_10(n4_8_10, n2_8_10, n3_8_10);
nor gn5_8_10(n5_8_10, A8B11, n4_8_10);
nor gn6_8_10(n6_8_10, A8B11, n5_8_10);
nor gn7_8_10(n7_8_10, n4_8_10, n5_8_10);
nor gn8_8_10(S8_10, n6_8_10, n7_8_10);
nor gn9_8_10(C8_10, n1_8_10, n5_8_10);
/* FA MFA9_10(S9_10,C9_10,S10_9,C9_9,A9B11); */
nor gn1_9_10(n1_9_10, S10_9, C9_9);
nor gn2_9_10(n2_9_10, n1_9_10, C9_9);
nor gn3_9_10(n3_9_10, S10_9, n1_9_10);
nor gn4_9_10(n4_9_10, n2_9_10, n3_9_10);
nor gn5_9_10(n5_9_10, A9B11, n4_9_10);
nor gn6_9_10(n6_9_10, A9B11, n5_9_10);
nor gn7_9_10(n7_9_10, n4_9_10, n5_9_10);
nor gn8_9_10(S9_10, n6_9_10, n7_9_10);
nor gn9_9_10(C9_10, n1_9_10, n5_9_10);
/* FA MFA10_10(S10_10,C10_10,S11_9,C10_9,A10B11); */
nor gn1_10_10(n1_10_10, S11_9, C10_9);
nor gn2_10_10(n2_10_10, n1_10_10, C10_9);
nor gn3_10_10(n3_10_10, S11_9, n1_10_10);
nor gn4_10_10(n4_10_10, n2_10_10, n3_10_10);
nor gn5_10_10(n5_10_10, A10B11, n4_10_10);
nor gn6_10_10(n6_10_10, A10B11, n5_10_10);
nor gn7_10_10(n7_10_10, n4_10_10, n5_10_10);
nor gn8_10_10(S10_10, n6_10_10, n7_10_10);
nor gn9_10_10(C10_10, n1_10_10, n5_10_10);
/* FA MFA11_10(S11_10,C11_10,S12_9,C11_9,A11B11); */
nor gn1_11_10(n1_11_10, S12_9, C11_9);
nor gn2_11_10(n2_11_10, n1_11_10, C11_9);
nor gn3_11_10(n3_11_10, S12_9, n1_11_10);
nor gn4_11_10(n4_11_10, n2_11_10, n3_11_10);
nor gn5_11_10(n5_11_10, A11B11, n4_11_10);
nor gn6_11_10(n6_11_10, A11B11, n5_11_10);
nor gn7_11_10(n7_11_10, n4_11_10, n5_11_10);
nor gn8_11_10(S11_10, n6_11_10, n7_11_10);
nor gn9_11_10(C11_10, n1_11_10, n5_11_10);
/* FA MFA12_10(S12_10,C12_10,S13_9,C12_9,A12B11); */
nor gn1_12_10(n1_12_10, S13_9, C12_9);
nor gn2_12_10(n2_12_10, n1_12_10, C12_9);
nor gn3_12_10(n3_12_10, S13_9, n1_12_10);
nor gn4_12_10(n4_12_10, n2_12_10, n3_12_10);
nor gn5_12_10(n5_12_10, A12B11, n4_12_10);
nor gn6_12_10(n6_12_10, A12B11, n5_12_10);
nor gn7_12_10(n7_12_10, n4_12_10, n5_12_10);
nor gn8_12_10(S12_10, n6_12_10, n7_12_10);
nor gn9_12_10(C12_10, n1_12_10, n5_12_10);
/* FA MFA13_10(S13_10,C13_10,S14_9,C13_9,A13B11); */
nor gn1_13_10(n1_13_10, S14_9, C13_9);
nor gn2_13_10(n2_13_10, n1_13_10, C13_9);
nor gn3_13_10(n3_13_10, S14_9, n1_13_10);
nor gn4_13_10(n4_13_10, n2_13_10, n3_13_10);
nor gn5_13_10(n5_13_10, A13B11, n4_13_10);
nor gn6_13_10(n6_13_10, A13B11, n5_13_10);
nor gn7_13_10(n7_13_10, n4_13_10, n5_13_10);
nor gn8_13_10(S13_10, n6_13_10, n7_13_10);
nor gn9_13_10(C13_10, n1_13_10, n5_13_10);
/* FA MFA14_10(S14_10,C14_10,A15B10,C14_9,A14B11); */
nor gn1_14_10(n1_14_10, A15B10, C14_9);
nor gn2_14_10(n2_14_10, n1_14_10, C14_9);
nor gn3_14_10(n3_14_10, A15B10, n1_14_10);
nor gn4_14_10(n4_14_10, n2_14_10, n3_14_10);
nor gn5_14_10(n5_14_10, A14B11, n4_14_10);
nor gn6_14_10(n6_14_10, A14B11, n5_14_10);
nor gn7_14_10(n7_14_10, n4_14_10, n5_14_10);
nor gn8_14_10(S14_10, n6_14_10, n7_14_10);
nor gn9_14_10(C14_10, n1_14_10, n5_14_10);
/* FA MFA0_11(S0_11,C0_11,S1_10,C0_10,A0B12); */
nor gn1_0_11(n1_0_11, S1_10, C0_10);
nor gn2_0_11(n2_0_11, n1_0_11, C0_10);
nor gn3_0_11(n3_0_11, S1_10, n1_0_11);
nor gn4_0_11(n4_0_11, n2_0_11, n3_0_11);
nor gn5_0_11(n5_0_11, A0B12, n4_0_11);
nor gn6_0_11(n6_0_11, A0B12, n5_0_11);
nor gn7_0_11(n7_0_11, n4_0_11, n5_0_11);
nor gn8_0_11(S0_11, n6_0_11, n7_0_11);
nor gn9_0_11(C0_11, n1_0_11, n5_0_11);
/* FA MFA1_11(S1_11,C1_11,S2_10,C1_10,A1B12); */
nor gn1_1_11(n1_1_11, S2_10, C1_10);
nor gn2_1_11(n2_1_11, n1_1_11, C1_10);
nor gn3_1_11(n3_1_11, S2_10, n1_1_11);
nor gn4_1_11(n4_1_11, n2_1_11, n3_1_11);
nor gn5_1_11(n5_1_11, A1B12, n4_1_11);
nor gn6_1_11(n6_1_11, A1B12, n5_1_11);
nor gn7_1_11(n7_1_11, n4_1_11, n5_1_11);
nor gn8_1_11(S1_11, n6_1_11, n7_1_11);
nor gn9_1_11(C1_11, n1_1_11, n5_1_11);
/* FA MFA2_11(S2_11,C2_11,S3_10,C2_10,A2B12); */
nor gn1_2_11(n1_2_11, S3_10, C2_10);
nor gn2_2_11(n2_2_11, n1_2_11, C2_10);
nor gn3_2_11(n3_2_11, S3_10, n1_2_11);
nor gn4_2_11(n4_2_11, n2_2_11, n3_2_11);
nor gn5_2_11(n5_2_11, A2B12, n4_2_11);
nor gn6_2_11(n6_2_11, A2B12, n5_2_11);
nor gn7_2_11(n7_2_11, n4_2_11, n5_2_11);
nor gn8_2_11(S2_11, n6_2_11, n7_2_11);
nor gn9_2_11(C2_11, n1_2_11, n5_2_11);
/* FA MFA3_11(S3_11,C3_11,S4_10,C3_10,A3B12); */
nor gn1_3_11(n1_3_11, S4_10, C3_10);
nor gn2_3_11(n2_3_11, n1_3_11, C3_10);
nor gn3_3_11(n3_3_11, S4_10, n1_3_11);
nor gn4_3_11(n4_3_11, n2_3_11, n3_3_11);
nor gn5_3_11(n5_3_11, A3B12, n4_3_11);
nor gn6_3_11(n6_3_11, A3B12, n5_3_11);
nor gn7_3_11(n7_3_11, n4_3_11, n5_3_11);
nor gn8_3_11(S3_11, n6_3_11, n7_3_11);
nor gn9_3_11(C3_11, n1_3_11, n5_3_11);
/* FA MFA4_11(S4_11,C4_11,S5_10,C4_10,A4B12); */
nor gn1_4_11(n1_4_11, S5_10, C4_10);
nor gn2_4_11(n2_4_11, n1_4_11, C4_10);
nor gn3_4_11(n3_4_11, S5_10, n1_4_11);
nor gn4_4_11(n4_4_11, n2_4_11, n3_4_11);
nor gn5_4_11(n5_4_11, A4B12, n4_4_11);
nor gn6_4_11(n6_4_11, A4B12, n5_4_11);
nor gn7_4_11(n7_4_11, n4_4_11, n5_4_11);
nor gn8_4_11(S4_11, n6_4_11, n7_4_11);
nor gn9_4_11(C4_11, n1_4_11, n5_4_11);
/* FA MFA5_11(S5_11,C5_11,S6_10,C5_10,A5B12); */
nor gn1_5_11(n1_5_11, S6_10, C5_10);
nor gn2_5_11(n2_5_11, n1_5_11, C5_10);
nor gn3_5_11(n3_5_11, S6_10, n1_5_11);
nor gn4_5_11(n4_5_11, n2_5_11, n3_5_11);
nor gn5_5_11(n5_5_11, A5B12, n4_5_11);
nor gn6_5_11(n6_5_11, A5B12, n5_5_11);
nor gn7_5_11(n7_5_11, n4_5_11, n5_5_11);
nor gn8_5_11(S5_11, n6_5_11, n7_5_11);
nor gn9_5_11(C5_11, n1_5_11, n5_5_11);
/* FA MFA6_11(S6_11,C6_11,S7_10,C6_10,A6B12); */
nor gn1_6_11(n1_6_11, S7_10, C6_10);
nor gn2_6_11(n2_6_11, n1_6_11, C6_10);
nor gn3_6_11(n3_6_11, S7_10, n1_6_11);
nor gn4_6_11(n4_6_11, n2_6_11, n3_6_11);
nor gn5_6_11(n5_6_11, A6B12, n4_6_11);
nor gn6_6_11(n6_6_11, A6B12, n5_6_11);
nor gn7_6_11(n7_6_11, n4_6_11, n5_6_11);
nor gn8_6_11(S6_11, n6_6_11, n7_6_11);
nor gn9_6_11(C6_11, n1_6_11, n5_6_11);
/* FA MFA7_11(S7_11,C7_11,S8_10,C7_10,A7B12); */
nor gn1_7_11(n1_7_11, S8_10, C7_10);
nor gn2_7_11(n2_7_11, n1_7_11, C7_10);
nor gn3_7_11(n3_7_11, S8_10, n1_7_11);
nor gn4_7_11(n4_7_11, n2_7_11, n3_7_11);
nor gn5_7_11(n5_7_11, A7B12, n4_7_11);
nor gn6_7_11(n6_7_11, A7B12, n5_7_11);
nor gn7_7_11(n7_7_11, n4_7_11, n5_7_11);
nor gn8_7_11(S7_11, n6_7_11, n7_7_11);
nor gn9_7_11(C7_11, n1_7_11, n5_7_11);
/* FA MFA8_11(S8_11,C8_11,S9_10,C8_10,A8B12); */
nor gn1_8_11(n1_8_11, S9_10, C8_10);
nor gn2_8_11(n2_8_11, n1_8_11, C8_10);
nor gn3_8_11(n3_8_11, S9_10, n1_8_11);
nor gn4_8_11(n4_8_11, n2_8_11, n3_8_11);
nor gn5_8_11(n5_8_11, A8B12, n4_8_11);
nor gn6_8_11(n6_8_11, A8B12, n5_8_11);
nor gn7_8_11(n7_8_11, n4_8_11, n5_8_11);
nor gn8_8_11(S8_11, n6_8_11, n7_8_11);
nor gn9_8_11(C8_11, n1_8_11, n5_8_11);
/* FA MFA9_11(S9_11,C9_11,S10_10,C9_10,A9B12); */
nor gn1_9_11(n1_9_11, S10_10, C9_10);
nor gn2_9_11(n2_9_11, n1_9_11, C9_10);
nor gn3_9_11(n3_9_11, S10_10, n1_9_11);
nor gn4_9_11(n4_9_11, n2_9_11, n3_9_11);
nor gn5_9_11(n5_9_11, A9B12, n4_9_11);
nor gn6_9_11(n6_9_11, A9B12, n5_9_11);
nor gn7_9_11(n7_9_11, n4_9_11, n5_9_11);
nor gn8_9_11(S9_11, n6_9_11, n7_9_11);
nor gn9_9_11(C9_11, n1_9_11, n5_9_11);
/* FA MFA10_11(S10_11,C10_11,S11_10,C10_10,A10B12); */
nor gn1_10_11(n1_10_11, S11_10, C10_10);
nor gn2_10_11(n2_10_11, n1_10_11, C10_10);
nor gn3_10_11(n3_10_11, S11_10, n1_10_11);
nor gn4_10_11(n4_10_11, n2_10_11, n3_10_11);
nor gn5_10_11(n5_10_11, A10B12, n4_10_11);
nor gn6_10_11(n6_10_11, A10B12, n5_10_11);
nor gn7_10_11(n7_10_11, n4_10_11, n5_10_11);
nor gn8_10_11(S10_11, n6_10_11, n7_10_11);
nor gn9_10_11(C10_11, n1_10_11, n5_10_11);
/* FA MFA11_11(S11_11,C11_11,S12_10,C11_10,A11B12); */
nor gn1_11_11(n1_11_11, S12_10, C11_10);
nor gn2_11_11(n2_11_11, n1_11_11, C11_10);
nor gn3_11_11(n3_11_11, S12_10, n1_11_11);
nor gn4_11_11(n4_11_11, n2_11_11, n3_11_11);
nor gn5_11_11(n5_11_11, A11B12, n4_11_11);
nor gn6_11_11(n6_11_11, A11B12, n5_11_11);
nor gn7_11_11(n7_11_11, n4_11_11, n5_11_11);
nor gn8_11_11(S11_11, n6_11_11, n7_11_11);
nor gn9_11_11(C11_11, n1_11_11, n5_11_11);
/* FA MFA12_11(S12_11,C12_11,S13_10,C12_10,A12B12); */
nor gn1_12_11(n1_12_11, S13_10, C12_10);
nor gn2_12_11(n2_12_11, n1_12_11, C12_10);
nor gn3_12_11(n3_12_11, S13_10, n1_12_11);
nor gn4_12_11(n4_12_11, n2_12_11, n3_12_11);
nor gn5_12_11(n5_12_11, A12B12, n4_12_11);
nor gn6_12_11(n6_12_11, A12B12, n5_12_11);
nor gn7_12_11(n7_12_11, n4_12_11, n5_12_11);
nor gn8_12_11(S12_11, n6_12_11, n7_12_11);
nor gn9_12_11(C12_11, n1_12_11, n5_12_11);
/* FA MFA13_11(S13_11,C13_11,S14_10,C13_10,A13B12); */
nor gn1_13_11(n1_13_11, S14_10, C13_10);
nor gn2_13_11(n2_13_11, n1_13_11, C13_10);
nor gn3_13_11(n3_13_11, S14_10, n1_13_11);
nor gn4_13_11(n4_13_11, n2_13_11, n3_13_11);
nor gn5_13_11(n5_13_11, A13B12, n4_13_11);
nor gn6_13_11(n6_13_11, A13B12, n5_13_11);
nor gn7_13_11(n7_13_11, n4_13_11, n5_13_11);
nor gn8_13_11(S13_11, n6_13_11, n7_13_11);
nor gn9_13_11(C13_11, n1_13_11, n5_13_11);
/* FA MFA14_11(S14_11,C14_11,A15B11,C14_10,A14B12); */
nor gn1_14_11(n1_14_11, A15B11, C14_10);
nor gn2_14_11(n2_14_11, n1_14_11, C14_10);
nor gn3_14_11(n3_14_11, A15B11, n1_14_11);
nor gn4_14_11(n4_14_11, n2_14_11, n3_14_11);
nor gn5_14_11(n5_14_11, A14B12, n4_14_11);
nor gn6_14_11(n6_14_11, A14B12, n5_14_11);
nor gn7_14_11(n7_14_11, n4_14_11, n5_14_11);
nor gn8_14_11(S14_11, n6_14_11, n7_14_11);
nor gn9_14_11(C14_11, n1_14_11, n5_14_11);
/* FA MFA0_12(S0_12,C0_12,S1_11,C0_11,A0B13); */
nor gn1_0_12(n1_0_12, S1_11, C0_11);
nor gn2_0_12(n2_0_12, n1_0_12, C0_11);
nor gn3_0_12(n3_0_12, S1_11, n1_0_12);
nor gn4_0_12(n4_0_12, n2_0_12, n3_0_12);
nor gn5_0_12(n5_0_12, A0B13, n4_0_12);
nor gn6_0_12(n6_0_12, A0B13, n5_0_12);
nor gn7_0_12(n7_0_12, n4_0_12, n5_0_12);
nor gn8_0_12(S0_12, n6_0_12, n7_0_12);
nor gn9_0_12(C0_12, n1_0_12, n5_0_12);
/* FA MFA1_12(S1_12,C1_12,S2_11,C1_11,A1B13); */
nor gn1_1_12(n1_1_12, S2_11, C1_11);
nor gn2_1_12(n2_1_12, n1_1_12, C1_11);
nor gn3_1_12(n3_1_12, S2_11, n1_1_12);
nor gn4_1_12(n4_1_12, n2_1_12, n3_1_12);
nor gn5_1_12(n5_1_12, A1B13, n4_1_12);
nor gn6_1_12(n6_1_12, A1B13, n5_1_12);
nor gn7_1_12(n7_1_12, n4_1_12, n5_1_12);
nor gn8_1_12(S1_12, n6_1_12, n7_1_12);
nor gn9_1_12(C1_12, n1_1_12, n5_1_12);
/* FA MFA2_12(S2_12,C2_12,S3_11,C2_11,A2B13); */
nor gn1_2_12(n1_2_12, S3_11, C2_11);
nor gn2_2_12(n2_2_12, n1_2_12, C2_11);
nor gn3_2_12(n3_2_12, S3_11, n1_2_12);
nor gn4_2_12(n4_2_12, n2_2_12, n3_2_12);
nor gn5_2_12(n5_2_12, A2B13, n4_2_12);
nor gn6_2_12(n6_2_12, A2B13, n5_2_12);
nor gn7_2_12(n7_2_12, n4_2_12, n5_2_12);
nor gn8_2_12(S2_12, n6_2_12, n7_2_12);
nor gn9_2_12(C2_12, n1_2_12, n5_2_12);
/* FA MFA3_12(S3_12,C3_12,S4_11,C3_11,A3B13); */
nor gn1_3_12(n1_3_12, S4_11, C3_11);
nor gn2_3_12(n2_3_12, n1_3_12, C3_11);
nor gn3_3_12(n3_3_12, S4_11, n1_3_12);
nor gn4_3_12(n4_3_12, n2_3_12, n3_3_12);
nor gn5_3_12(n5_3_12, A3B13, n4_3_12);
nor gn6_3_12(n6_3_12, A3B13, n5_3_12);
nor gn7_3_12(n7_3_12, n4_3_12, n5_3_12);
nor gn8_3_12(S3_12, n6_3_12, n7_3_12);
nor gn9_3_12(C3_12, n1_3_12, n5_3_12);
/* FA MFA4_12(S4_12,C4_12,S5_11,C4_11,A4B13); */
nor gn1_4_12(n1_4_12, S5_11, C4_11);
nor gn2_4_12(n2_4_12, n1_4_12, C4_11);
nor gn3_4_12(n3_4_12, S5_11, n1_4_12);
nor gn4_4_12(n4_4_12, n2_4_12, n3_4_12);
nor gn5_4_12(n5_4_12, A4B13, n4_4_12);
nor gn6_4_12(n6_4_12, A4B13, n5_4_12);
nor gn7_4_12(n7_4_12, n4_4_12, n5_4_12);
nor gn8_4_12(S4_12, n6_4_12, n7_4_12);
nor gn9_4_12(C4_12, n1_4_12, n5_4_12);
/* FA MFA5_12(S5_12,C5_12,S6_11,C5_11,A5B13); */
nor gn1_5_12(n1_5_12, S6_11, C5_11);
nor gn2_5_12(n2_5_12, n1_5_12, C5_11);
nor gn3_5_12(n3_5_12, S6_11, n1_5_12);
nor gn4_5_12(n4_5_12, n2_5_12, n3_5_12);
nor gn5_5_12(n5_5_12, A5B13, n4_5_12);
nor gn6_5_12(n6_5_12, A5B13, n5_5_12);
nor gn7_5_12(n7_5_12, n4_5_12, n5_5_12);
nor gn8_5_12(S5_12, n6_5_12, n7_5_12);
nor gn9_5_12(C5_12, n1_5_12, n5_5_12);
/* FA MFA6_12(S6_12,C6_12,S7_11,C6_11,A6B13); */
nor gn1_6_12(n1_6_12, S7_11, C6_11);
nor gn2_6_12(n2_6_12, n1_6_12, C6_11);
nor gn3_6_12(n3_6_12, S7_11, n1_6_12);
nor gn4_6_12(n4_6_12, n2_6_12, n3_6_12);
nor gn5_6_12(n5_6_12, A6B13, n4_6_12);
nor gn6_6_12(n6_6_12, A6B13, n5_6_12);
nor gn7_6_12(n7_6_12, n4_6_12, n5_6_12);
nor gn8_6_12(S6_12, n6_6_12, n7_6_12);
nor gn9_6_12(C6_12, n1_6_12, n5_6_12);
/* FA MFA7_12(S7_12,C7_12,S8_11,C7_11,A7B13); */
nor gn1_7_12(n1_7_12, S8_11, C7_11);
nor gn2_7_12(n2_7_12, n1_7_12, C7_11);
nor gn3_7_12(n3_7_12, S8_11, n1_7_12);
nor gn4_7_12(n4_7_12, n2_7_12, n3_7_12);
nor gn5_7_12(n5_7_12, A7B13, n4_7_12);
nor gn6_7_12(n6_7_12, A7B13, n5_7_12);
nor gn7_7_12(n7_7_12, n4_7_12, n5_7_12);
nor gn8_7_12(S7_12, n6_7_12, n7_7_12);
nor gn9_7_12(C7_12, n1_7_12, n5_7_12);
/* FA MFA8_12(S8_12,C8_12,S9_11,C8_11,A8B13); */
nor gn1_8_12(n1_8_12, S9_11, C8_11);
nor gn2_8_12(n2_8_12, n1_8_12, C8_11);
nor gn3_8_12(n3_8_12, S9_11, n1_8_12);
nor gn4_8_12(n4_8_12, n2_8_12, n3_8_12);
nor gn5_8_12(n5_8_12, A8B13, n4_8_12);
nor gn6_8_12(n6_8_12, A8B13, n5_8_12);
nor gn7_8_12(n7_8_12, n4_8_12, n5_8_12);
nor gn8_8_12(S8_12, n6_8_12, n7_8_12);
nor gn9_8_12(C8_12, n1_8_12, n5_8_12);
/* FA MFA9_12(S9_12,C9_12,S10_11,C9_11,A9B13); */
nor gn1_9_12(n1_9_12, S10_11, C9_11);
nor gn2_9_12(n2_9_12, n1_9_12, C9_11);
nor gn3_9_12(n3_9_12, S10_11, n1_9_12);
nor gn4_9_12(n4_9_12, n2_9_12, n3_9_12);
nor gn5_9_12(n5_9_12, A9B13, n4_9_12);
nor gn6_9_12(n6_9_12, A9B13, n5_9_12);
nor gn7_9_12(n7_9_12, n4_9_12, n5_9_12);
nor gn8_9_12(S9_12, n6_9_12, n7_9_12);
nor gn9_9_12(C9_12, n1_9_12, n5_9_12);
/* FA MFA10_12(S10_12,C10_12,S11_11,C10_11,A10B13); */
nor gn1_10_12(n1_10_12, S11_11, C10_11);
nor gn2_10_12(n2_10_12, n1_10_12, C10_11);
nor gn3_10_12(n3_10_12, S11_11, n1_10_12);
nor gn4_10_12(n4_10_12, n2_10_12, n3_10_12);
nor gn5_10_12(n5_10_12, A10B13, n4_10_12);
nor gn6_10_12(n6_10_12, A10B13, n5_10_12);
nor gn7_10_12(n7_10_12, n4_10_12, n5_10_12);
nor gn8_10_12(S10_12, n6_10_12, n7_10_12);
nor gn9_10_12(C10_12, n1_10_12, n5_10_12);
/* FA MFA11_12(S11_12,C11_12,S12_11,C11_11,A11B13); */
nor gn1_11_12(n1_11_12, S12_11, C11_11);
nor gn2_11_12(n2_11_12, n1_11_12, C11_11);
nor gn3_11_12(n3_11_12, S12_11, n1_11_12);
nor gn4_11_12(n4_11_12, n2_11_12, n3_11_12);
nor gn5_11_12(n5_11_12, A11B13, n4_11_12);
nor gn6_11_12(n6_11_12, A11B13, n5_11_12);
nor gn7_11_12(n7_11_12, n4_11_12, n5_11_12);
nor gn8_11_12(S11_12, n6_11_12, n7_11_12);
nor gn9_11_12(C11_12, n1_11_12, n5_11_12);
/* FA MFA12_12(S12_12,C12_12,S13_11,C12_11,A12B13); */
nor gn1_12_12(n1_12_12, S13_11, C12_11);
nor gn2_12_12(n2_12_12, n1_12_12, C12_11);
nor gn3_12_12(n3_12_12, S13_11, n1_12_12);
nor gn4_12_12(n4_12_12, n2_12_12, n3_12_12);
nor gn5_12_12(n5_12_12, A12B13, n4_12_12);
nor gn6_12_12(n6_12_12, A12B13, n5_12_12);
nor gn7_12_12(n7_12_12, n4_12_12, n5_12_12);
nor gn8_12_12(S12_12, n6_12_12, n7_12_12);
nor gn9_12_12(C12_12, n1_12_12, n5_12_12);
/* FA MFA13_12(S13_12,C13_12,S14_11,C13_11,A13B13); */
nor gn1_13_12(n1_13_12, S14_11, C13_11);
nor gn2_13_12(n2_13_12, n1_13_12, C13_11);
nor gn3_13_12(n3_13_12, S14_11, n1_13_12);
nor gn4_13_12(n4_13_12, n2_13_12, n3_13_12);
nor gn5_13_12(n5_13_12, A13B13, n4_13_12);
nor gn6_13_12(n6_13_12, A13B13, n5_13_12);
nor gn7_13_12(n7_13_12, n4_13_12, n5_13_12);
nor gn8_13_12(S13_12, n6_13_12, n7_13_12);
nor gn9_13_12(C13_12, n1_13_12, n5_13_12);
/* FA MFA14_12(S14_12,C14_12,A15B12,C14_11,A14B13); */
nor gn1_14_12(n1_14_12, A15B12, C14_11);
nor gn2_14_12(n2_14_12, n1_14_12, C14_11);
nor gn3_14_12(n3_14_12, A15B12, n1_14_12);
nor gn4_14_12(n4_14_12, n2_14_12, n3_14_12);
nor gn5_14_12(n5_14_12, A14B13, n4_14_12);
nor gn6_14_12(n6_14_12, A14B13, n5_14_12);
nor gn7_14_12(n7_14_12, n4_14_12, n5_14_12);
nor gn8_14_12(S14_12, n6_14_12, n7_14_12);
nor gn9_14_12(C14_12, n1_14_12, n5_14_12);
/* FA MFA0_13(S0_13,C0_13,S1_12,C0_12,A0B14); */
nor gn1_0_13(n1_0_13, S1_12, C0_12);
nor gn2_0_13(n2_0_13, n1_0_13, C0_12);
nor gn3_0_13(n3_0_13, S1_12, n1_0_13);
nor gn4_0_13(n4_0_13, n2_0_13, n3_0_13);
nor gn5_0_13(n5_0_13, A0B14, n4_0_13);
nor gn6_0_13(n6_0_13, A0B14, n5_0_13);
nor gn7_0_13(n7_0_13, n4_0_13, n5_0_13);
nor gn8_0_13(S0_13, n6_0_13, n7_0_13);
nor gn9_0_13(C0_13, n1_0_13, n5_0_13);
/* FA MFA1_13(S1_13,C1_13,S2_12,C1_12,A1B14); */
nor gn1_1_13(n1_1_13, S2_12, C1_12);
nor gn2_1_13(n2_1_13, n1_1_13, C1_12);
nor gn3_1_13(n3_1_13, S2_12, n1_1_13);
nor gn4_1_13(n4_1_13, n2_1_13, n3_1_13);
nor gn5_1_13(n5_1_13, A1B14, n4_1_13);
nor gn6_1_13(n6_1_13, A1B14, n5_1_13);
nor gn7_1_13(n7_1_13, n4_1_13, n5_1_13);
nor gn8_1_13(S1_13, n6_1_13, n7_1_13);
nor gn9_1_13(C1_13, n1_1_13, n5_1_13);
/* FA MFA2_13(S2_13,C2_13,S3_12,C2_12,A2B14); */
nor gn1_2_13(n1_2_13, S3_12, C2_12);
nor gn2_2_13(n2_2_13, n1_2_13, C2_12);
nor gn3_2_13(n3_2_13, S3_12, n1_2_13);
nor gn4_2_13(n4_2_13, n2_2_13, n3_2_13);
nor gn5_2_13(n5_2_13, A2B14, n4_2_13);
nor gn6_2_13(n6_2_13, A2B14, n5_2_13);
nor gn7_2_13(n7_2_13, n4_2_13, n5_2_13);
nor gn8_2_13(S2_13, n6_2_13, n7_2_13);
nor gn9_2_13(C2_13, n1_2_13, n5_2_13);
/* FA MFA3_13(S3_13,C3_13,S4_12,C3_12,A3B14); */
nor gn1_3_13(n1_3_13, S4_12, C3_12);
nor gn2_3_13(n2_3_13, n1_3_13, C3_12);
nor gn3_3_13(n3_3_13, S4_12, n1_3_13);
nor gn4_3_13(n4_3_13, n2_3_13, n3_3_13);
nor gn5_3_13(n5_3_13, A3B14, n4_3_13);
nor gn6_3_13(n6_3_13, A3B14, n5_3_13);
nor gn7_3_13(n7_3_13, n4_3_13, n5_3_13);
nor gn8_3_13(S3_13, n6_3_13, n7_3_13);
nor gn9_3_13(C3_13, n1_3_13, n5_3_13);
/* FA MFA4_13(S4_13,C4_13,S5_12,C4_12,A4B14); */
nor gn1_4_13(n1_4_13, S5_12, C4_12);
nor gn2_4_13(n2_4_13, n1_4_13, C4_12);
nor gn3_4_13(n3_4_13, S5_12, n1_4_13);
nor gn4_4_13(n4_4_13, n2_4_13, n3_4_13);
nor gn5_4_13(n5_4_13, A4B14, n4_4_13);
nor gn6_4_13(n6_4_13, A4B14, n5_4_13);
nor gn7_4_13(n7_4_13, n4_4_13, n5_4_13);
nor gn8_4_13(S4_13, n6_4_13, n7_4_13);
nor gn9_4_13(C4_13, n1_4_13, n5_4_13);
/* FA MFA5_13(S5_13,C5_13,S6_12,C5_12,A5B14); */
nor gn1_5_13(n1_5_13, S6_12, C5_12);
nor gn2_5_13(n2_5_13, n1_5_13, C5_12);
nor gn3_5_13(n3_5_13, S6_12, n1_5_13);
nor gn4_5_13(n4_5_13, n2_5_13, n3_5_13);
nor gn5_5_13(n5_5_13, A5B14, n4_5_13);
nor gn6_5_13(n6_5_13, A5B14, n5_5_13);
nor gn7_5_13(n7_5_13, n4_5_13, n5_5_13);
nor gn8_5_13(S5_13, n6_5_13, n7_5_13);
nor gn9_5_13(C5_13, n1_5_13, n5_5_13);
/* FA MFA6_13(S6_13,C6_13,S7_12,C6_12,A6B14); */
nor gn1_6_13(n1_6_13, S7_12, C6_12);
nor gn2_6_13(n2_6_13, n1_6_13, C6_12);
nor gn3_6_13(n3_6_13, S7_12, n1_6_13);
nor gn4_6_13(n4_6_13, n2_6_13, n3_6_13);
nor gn5_6_13(n5_6_13, A6B14, n4_6_13);
nor gn6_6_13(n6_6_13, A6B14, n5_6_13);
nor gn7_6_13(n7_6_13, n4_6_13, n5_6_13);
nor gn8_6_13(S6_13, n6_6_13, n7_6_13);
nor gn9_6_13(C6_13, n1_6_13, n5_6_13);
/* FA MFA7_13(S7_13,C7_13,S8_12,C7_12,A7B14); */
nor gn1_7_13(n1_7_13, S8_12, C7_12);
nor gn2_7_13(n2_7_13, n1_7_13, C7_12);
nor gn3_7_13(n3_7_13, S8_12, n1_7_13);
nor gn4_7_13(n4_7_13, n2_7_13, n3_7_13);
nor gn5_7_13(n5_7_13, A7B14, n4_7_13);
nor gn6_7_13(n6_7_13, A7B14, n5_7_13);
nor gn7_7_13(n7_7_13, n4_7_13, n5_7_13);
nor gn8_7_13(S7_13, n6_7_13, n7_7_13);
nor gn9_7_13(C7_13, n1_7_13, n5_7_13);
/* FA MFA8_13(S8_13,C8_13,S9_12,C8_12,A8B14); */
nor gn1_8_13(n1_8_13, S9_12, C8_12);
nor gn2_8_13(n2_8_13, n1_8_13, C8_12);
nor gn3_8_13(n3_8_13, S9_12, n1_8_13);
nor gn4_8_13(n4_8_13, n2_8_13, n3_8_13);
nor gn5_8_13(n5_8_13, A8B14, n4_8_13);
nor gn6_8_13(n6_8_13, A8B14, n5_8_13);
nor gn7_8_13(n7_8_13, n4_8_13, n5_8_13);
nor gn8_8_13(S8_13, n6_8_13, n7_8_13);
nor gn9_8_13(C8_13, n1_8_13, n5_8_13);
/* FA MFA9_13(S9_13,C9_13,S10_12,C9_12,A9B14); */
nor gn1_9_13(n1_9_13, S10_12, C9_12);
nor gn2_9_13(n2_9_13, n1_9_13, C9_12);
nor gn3_9_13(n3_9_13, S10_12, n1_9_13);
nor gn4_9_13(n4_9_13, n2_9_13, n3_9_13);
nor gn5_9_13(n5_9_13, A9B14, n4_9_13);
nor gn6_9_13(n6_9_13, A9B14, n5_9_13);
nor gn7_9_13(n7_9_13, n4_9_13, n5_9_13);
nor gn8_9_13(S9_13, n6_9_13, n7_9_13);
nor gn9_9_13(C9_13, n1_9_13, n5_9_13);
/* FA MFA10_13(S10_13,C10_13,S11_12,C10_12,A10B14); */
nor gn1_10_13(n1_10_13, S11_12, C10_12);
nor gn2_10_13(n2_10_13, n1_10_13, C10_12);
nor gn3_10_13(n3_10_13, S11_12, n1_10_13);
nor gn4_10_13(n4_10_13, n2_10_13, n3_10_13);
nor gn5_10_13(n5_10_13, A10B14, n4_10_13);
nor gn6_10_13(n6_10_13, A10B14, n5_10_13);
nor gn7_10_13(n7_10_13, n4_10_13, n5_10_13);
nor gn8_10_13(S10_13, n6_10_13, n7_10_13);
nor gn9_10_13(C10_13, n1_10_13, n5_10_13);
/* FA MFA11_13(S11_13,C11_13,S12_12,C11_12,A11B14); */
nor gn1_11_13(n1_11_13, S12_12, C11_12);
nor gn2_11_13(n2_11_13, n1_11_13, C11_12);
nor gn3_11_13(n3_11_13, S12_12, n1_11_13);
nor gn4_11_13(n4_11_13, n2_11_13, n3_11_13);
nor gn5_11_13(n5_11_13, A11B14, n4_11_13);
nor gn6_11_13(n6_11_13, A11B14, n5_11_13);
nor gn7_11_13(n7_11_13, n4_11_13, n5_11_13);
nor gn8_11_13(S11_13, n6_11_13, n7_11_13);
nor gn9_11_13(C11_13, n1_11_13, n5_11_13);
/* FA MFA12_13(S12_13,C12_13,S13_12,C12_12,A12B14); */
nor gn1_12_13(n1_12_13, S13_12, C12_12);
nor gn2_12_13(n2_12_13, n1_12_13, C12_12);
nor gn3_12_13(n3_12_13, S13_12, n1_12_13);
nor gn4_12_13(n4_12_13, n2_12_13, n3_12_13);
nor gn5_12_13(n5_12_13, A12B14, n4_12_13);
nor gn6_12_13(n6_12_13, A12B14, n5_12_13);
nor gn7_12_13(n7_12_13, n4_12_13, n5_12_13);
nor gn8_12_13(S12_13, n6_12_13, n7_12_13);
nor gn9_12_13(C12_13, n1_12_13, n5_12_13);
/* FA MFA13_13(S13_13,C13_13,S14_12,C13_12,A13B14); */
nor gn1_13_13(n1_13_13, S14_12, C13_12);
nor gn2_13_13(n2_13_13, n1_13_13, C13_12);
nor gn3_13_13(n3_13_13, S14_12, n1_13_13);
nor gn4_13_13(n4_13_13, n2_13_13, n3_13_13);
nor gn5_13_13(n5_13_13, A13B14, n4_13_13);
nor gn6_13_13(n6_13_13, A13B14, n5_13_13);
nor gn7_13_13(n7_13_13, n4_13_13, n5_13_13);
nor gn8_13_13(S13_13, n6_13_13, n7_13_13);
nor gn9_13_13(C13_13, n1_13_13, n5_13_13);
/* FA MFA14_13(S14_13,C14_13,A15B13,C14_12,A14B14); */
nor gn1_14_13(n1_14_13, A15B13, C14_12);
nor gn2_14_13(n2_14_13, n1_14_13, C14_12);
nor gn3_14_13(n3_14_13, A15B13, n1_14_13);
nor gn4_14_13(n4_14_13, n2_14_13, n3_14_13);
nor gn5_14_13(n5_14_13, A14B14, n4_14_13);
nor gn6_14_13(n6_14_13, A14B14, n5_14_13);
nor gn7_14_13(n7_14_13, n4_14_13, n5_14_13);
nor gn8_14_13(S14_13, n6_14_13, n7_14_13);
nor gn9_14_13(C14_13, n1_14_13, n5_14_13);
/* FA MFA0_14(S0_14,C0_14,S1_13,C0_13,A0B15); */
nor gn1_0_14(n1_0_14, S1_13, C0_13);
nor gn2_0_14(n2_0_14, n1_0_14, C0_13);
nor gn3_0_14(n3_0_14, S1_13, n1_0_14);
nor gn4_0_14(n4_0_14, n2_0_14, n3_0_14);
nor gn5_0_14(n5_0_14, A0B15, n4_0_14);
nor gn6_0_14(n6_0_14, A0B15, n5_0_14);
nor gn7_0_14(n7_0_14, n4_0_14, n5_0_14);
nor gn8_0_14(S0_14, n6_0_14, n7_0_14);
nor gn9_0_14(C0_14, n1_0_14, n5_0_14);
/* FA MFA1_14(S1_14,C1_14,S2_13,C1_13,A1B15); */
nor gn1_1_14(n1_1_14, S2_13, C1_13);
nor gn2_1_14(n2_1_14, n1_1_14, C1_13);
nor gn3_1_14(n3_1_14, S2_13, n1_1_14);
nor gn4_1_14(n4_1_14, n2_1_14, n3_1_14);
nor gn5_1_14(n5_1_14, A1B15, n4_1_14);
nor gn6_1_14(n6_1_14, A1B15, n5_1_14);
nor gn7_1_14(n7_1_14, n4_1_14, n5_1_14);
nor gn8_1_14(S1_14, n6_1_14, n7_1_14);
nor gn9_1_14(C1_14, n1_1_14, n5_1_14);
/* FA MFA2_14(S2_14,C2_14,S3_13,C2_13,A2B15); */
nor gn1_2_14(n1_2_14, S3_13, C2_13);
nor gn2_2_14(n2_2_14, n1_2_14, C2_13);
nor gn3_2_14(n3_2_14, S3_13, n1_2_14);
nor gn4_2_14(n4_2_14, n2_2_14, n3_2_14);
nor gn5_2_14(n5_2_14, A2B15, n4_2_14);
nor gn6_2_14(n6_2_14, A2B15, n5_2_14);
nor gn7_2_14(n7_2_14, n4_2_14, n5_2_14);
nor gn8_2_14(S2_14, n6_2_14, n7_2_14);
nor gn9_2_14(C2_14, n1_2_14, n5_2_14);
/* FA MFA3_14(S3_14,C3_14,S4_13,C3_13,A3B15); */
nor gn1_3_14(n1_3_14, S4_13, C3_13);
nor gn2_3_14(n2_3_14, n1_3_14, C3_13);
nor gn3_3_14(n3_3_14, S4_13, n1_3_14);
nor gn4_3_14(n4_3_14, n2_3_14, n3_3_14);
nor gn5_3_14(n5_3_14, A3B15, n4_3_14);
nor gn6_3_14(n6_3_14, A3B15, n5_3_14);
nor gn7_3_14(n7_3_14, n4_3_14, n5_3_14);
nor gn8_3_14(S3_14, n6_3_14, n7_3_14);
nor gn9_3_14(C3_14, n1_3_14, n5_3_14);
/* FA MFA4_14(S4_14,C4_14,S5_13,C4_13,A4B15); */
nor gn1_4_14(n1_4_14, S5_13, C4_13);
nor gn2_4_14(n2_4_14, n1_4_14, C4_13);
nor gn3_4_14(n3_4_14, S5_13, n1_4_14);
nor gn4_4_14(n4_4_14, n2_4_14, n3_4_14);
nor gn5_4_14(n5_4_14, A4B15, n4_4_14);
nor gn6_4_14(n6_4_14, A4B15, n5_4_14);
nor gn7_4_14(n7_4_14, n4_4_14, n5_4_14);
nor gn8_4_14(S4_14, n6_4_14, n7_4_14);
nor gn9_4_14(C4_14, n1_4_14, n5_4_14);
/* FA MFA5_14(S5_14,C5_14,S6_13,C5_13,A5B15); */
nor gn1_5_14(n1_5_14, S6_13, C5_13);
nor gn2_5_14(n2_5_14, n1_5_14, C5_13);
nor gn3_5_14(n3_5_14, S6_13, n1_5_14);
nor gn4_5_14(n4_5_14, n2_5_14, n3_5_14);
nor gn5_5_14(n5_5_14, A5B15, n4_5_14);
nor gn6_5_14(n6_5_14, A5B15, n5_5_14);
nor gn7_5_14(n7_5_14, n4_5_14, n5_5_14);
nor gn8_5_14(S5_14, n6_5_14, n7_5_14);
nor gn9_5_14(C5_14, n1_5_14, n5_5_14);
/* FA MFA6_14(S6_14,C6_14,S7_13,C6_13,A6B15); */
nor gn1_6_14(n1_6_14, S7_13, C6_13);
nor gn2_6_14(n2_6_14, n1_6_14, C6_13);
nor gn3_6_14(n3_6_14, S7_13, n1_6_14);
nor gn4_6_14(n4_6_14, n2_6_14, n3_6_14);
nor gn5_6_14(n5_6_14, A6B15, n4_6_14);
nor gn6_6_14(n6_6_14, A6B15, n5_6_14);
nor gn7_6_14(n7_6_14, n4_6_14, n5_6_14);
nor gn8_6_14(S6_14, n6_6_14, n7_6_14);
nor gn9_6_14(C6_14, n1_6_14, n5_6_14);
/* FA MFA7_14(S7_14,C7_14,S8_13,C7_13,A7B15); */
nor gn1_7_14(n1_7_14, S8_13, C7_13);
nor gn2_7_14(n2_7_14, n1_7_14, C7_13);
nor gn3_7_14(n3_7_14, S8_13, n1_7_14);
nor gn4_7_14(n4_7_14, n2_7_14, n3_7_14);
nor gn5_7_14(n5_7_14, A7B15, n4_7_14);
nor gn6_7_14(n6_7_14, A7B15, n5_7_14);
nor gn7_7_14(n7_7_14, n4_7_14, n5_7_14);
nor gn8_7_14(S7_14, n6_7_14, n7_7_14);
nor gn9_7_14(C7_14, n1_7_14, n5_7_14);
/* FA MFA8_14(S8_14,C8_14,S9_13,C8_13,A8B15); */
nor gn1_8_14(n1_8_14, S9_13, C8_13);
nor gn2_8_14(n2_8_14, n1_8_14, C8_13);
nor gn3_8_14(n3_8_14, S9_13, n1_8_14);
nor gn4_8_14(n4_8_14, n2_8_14, n3_8_14);
nor gn5_8_14(n5_8_14, A8B15, n4_8_14);
nor gn6_8_14(n6_8_14, A8B15, n5_8_14);
nor gn7_8_14(n7_8_14, n4_8_14, n5_8_14);
nor gn8_8_14(S8_14, n6_8_14, n7_8_14);
nor gn9_8_14(C8_14, n1_8_14, n5_8_14);
/* FA MFA9_14(S9_14,C9_14,S10_13,C9_13,A9B15); */
nor gn1_9_14(n1_9_14, S10_13, C9_13);
nor gn2_9_14(n2_9_14, n1_9_14, C9_13);
nor gn3_9_14(n3_9_14, S10_13, n1_9_14);
nor gn4_9_14(n4_9_14, n2_9_14, n3_9_14);
nor gn5_9_14(n5_9_14, A9B15, n4_9_14);
nor gn6_9_14(n6_9_14, A9B15, n5_9_14);
nor gn7_9_14(n7_9_14, n4_9_14, n5_9_14);
nor gn8_9_14(S9_14, n6_9_14, n7_9_14);
nor gn9_9_14(C9_14, n1_9_14, n5_9_14);
/* FA MFA10_14(S10_14,C10_14,S11_13,C10_13,A10B15); */
nor gn1_10_14(n1_10_14, S11_13, C10_13);
nor gn2_10_14(n2_10_14, n1_10_14, C10_13);
nor gn3_10_14(n3_10_14, S11_13, n1_10_14);
nor gn4_10_14(n4_10_14, n2_10_14, n3_10_14);
nor gn5_10_14(n5_10_14, A10B15, n4_10_14);
nor gn6_10_14(n6_10_14, A10B15, n5_10_14);
nor gn7_10_14(n7_10_14, n4_10_14, n5_10_14);
nor gn8_10_14(S10_14, n6_10_14, n7_10_14);
nor gn9_10_14(C10_14, n1_10_14, n5_10_14);
/* FA MFA11_14(S11_14,C11_14,S12_13,C11_13,A11B15); */
nor gn1_11_14(n1_11_14, S12_13, C11_13);
nor gn2_11_14(n2_11_14, n1_11_14, C11_13);
nor gn3_11_14(n3_11_14, S12_13, n1_11_14);
nor gn4_11_14(n4_11_14, n2_11_14, n3_11_14);
nor gn5_11_14(n5_11_14, A11B15, n4_11_14);
nor gn6_11_14(n6_11_14, A11B15, n5_11_14);
nor gn7_11_14(n7_11_14, n4_11_14, n5_11_14);
nor gn8_11_14(S11_14, n6_11_14, n7_11_14);
nor gn9_11_14(C11_14, n1_11_14, n5_11_14);
/* FA MFA12_14(S12_14,C12_14,S13_13,C12_13,A12B15); */
nor gn1_12_14(n1_12_14, S13_13, C12_13);
nor gn2_12_14(n2_12_14, n1_12_14, C12_13);
nor gn3_12_14(n3_12_14, S13_13, n1_12_14);
nor gn4_12_14(n4_12_14, n2_12_14, n3_12_14);
nor gn5_12_14(n5_12_14, A12B15, n4_12_14);
nor gn6_12_14(n6_12_14, A12B15, n5_12_14);
nor gn7_12_14(n7_12_14, n4_12_14, n5_12_14);
nor gn8_12_14(S12_14, n6_12_14, n7_12_14);
nor gn9_12_14(C12_14, n1_12_14, n5_12_14);
/* FA MFA13_14(S13_14,C13_14,S14_13,C13_13,A13B15); */
nor gn1_13_14(n1_13_14, S14_13, C13_13);
nor gn2_13_14(n2_13_14, n1_13_14, C13_13);
nor gn3_13_14(n3_13_14, S14_13, n1_13_14);
nor gn4_13_14(n4_13_14, n2_13_14, n3_13_14);
nor gn5_13_14(n5_13_14, A13B15, n4_13_14);
nor gn6_13_14(n6_13_14, A13B15, n5_13_14);
nor gn7_13_14(n7_13_14, n4_13_14, n5_13_14);
nor gn8_13_14(S13_14, n6_13_14, n7_13_14);
nor gn9_13_14(C13_14, n1_13_14, n5_13_14);
/* FA MFA14_14(S14_14,C14_14,A15B14,C14_13,A14B15); */
nor gn1_14_14(n1_14_14, A15B14, C14_13);
nor gn2_14_14(n2_14_14, n1_14_14, C14_13);
nor gn3_14_14(n3_14_14, A15B14, n1_14_14);
nor gn4_14_14(n4_14_14, n2_14_14, n3_14_14);
nor gn5_14_14(n5_14_14, A14B15, n4_14_14);
nor gn6_14_14(n6_14_14, A14B15, n5_14_14);
nor gn7_14_14(n7_14_14, n4_14_14, n5_14_14);
nor gn8_14_14(S14_14, n6_14_14, n7_14_14);
nor gn9_14_14(C14_14, n1_14_14, n5_14_14);
/* HA MHA0_15(S0_15,C0_15,S1_14,C0_14); */
nor gn1_0_15(n1_0_15, S1_14, C0_14);
nor gn2_0_15(n2_0_15, n1_0_15, C0_14);
nor gn3_0_15(n3_0_15, S1_14, n1_0_15);
nor gn4_0_15(n4_0_15, n2_0_15, n3_0_15);
not gn5_0_15(n5_0_15, n4_0_15);
not gn6_0_15(n6_0_15, n5_0_15);
nor gn7_0_15(n7_0_15, n4_0_15, n5_0_15);
nor gn8_0_15(S0_15, n6_0_15, n7_0_15);
nor gn9_0_15(C0_15, n1_0_15, n5_0_15);
/* FA MFA1_15(S1_15,C1_15,S2_14,C1_14,C0_15); */
nor gn1_1_15(n1_1_15, S2_14, C1_14);
nor gn2_1_15(n2_1_15, n1_1_15, C1_14);
nor gn3_1_15(n3_1_15, S2_14, n1_1_15);
nor gn4_1_15(n4_1_15, n2_1_15, n3_1_15);
nor gn5_1_15(n5_1_15, C0_15, n4_1_15);
nor gn6_1_15(n6_1_15, C0_15, n5_1_15);
nor gn7_1_15(n7_1_15, n4_1_15, n5_1_15);
nor gn8_1_15(S1_15, n6_1_15, n7_1_15);
nor gn9_1_15(C1_15, n1_1_15, n5_1_15);
/* FA MFA2_15(S2_15,C2_15,S3_14,C2_14,C1_15); */
nor gn1_2_15(n1_2_15, S3_14, C2_14);
nor gn2_2_15(n2_2_15, n1_2_15, C2_14);
nor gn3_2_15(n3_2_15, S3_14, n1_2_15);
nor gn4_2_15(n4_2_15, n2_2_15, n3_2_15);
nor gn5_2_15(n5_2_15, C1_15, n4_2_15);
nor gn6_2_15(n6_2_15, C1_15, n5_2_15);
nor gn7_2_15(n7_2_15, n4_2_15, n5_2_15);
nor gn8_2_15(S2_15, n6_2_15, n7_2_15);
nor gn9_2_15(C2_15, n1_2_15, n5_2_15);
/* FA MFA3_15(S3_15,C3_15,S4_14,C3_14,C2_15); */
nor gn1_3_15(n1_3_15, S4_14, C3_14);
nor gn2_3_15(n2_3_15, n1_3_15, C3_14);
nor gn3_3_15(n3_3_15, S4_14, n1_3_15);
nor gn4_3_15(n4_3_15, n2_3_15, n3_3_15);
nor gn5_3_15(n5_3_15, C2_15, n4_3_15);
nor gn6_3_15(n6_3_15, C2_15, n5_3_15);
nor gn7_3_15(n7_3_15, n4_3_15, n5_3_15);
nor gn8_3_15(S3_15, n6_3_15, n7_3_15);
nor gn9_3_15(C3_15, n1_3_15, n5_3_15);
/* FA MFA4_15(S4_15,C4_15,S5_14,C4_14,C3_15); */
nor gn1_4_15(n1_4_15, S5_14, C4_14);
nor gn2_4_15(n2_4_15, n1_4_15, C4_14);
nor gn3_4_15(n3_4_15, S5_14, n1_4_15);
nor gn4_4_15(n4_4_15, n2_4_15, n3_4_15);
nor gn5_4_15(n5_4_15, C3_15, n4_4_15);
nor gn6_4_15(n6_4_15, C3_15, n5_4_15);
nor gn7_4_15(n7_4_15, n4_4_15, n5_4_15);
nor gn8_4_15(S4_15, n6_4_15, n7_4_15);
nor gn9_4_15(C4_15, n1_4_15, n5_4_15);
/* FA MFA5_15(S5_15,C5_15,S6_14,C5_14,C4_15); */
nor gn1_5_15(n1_5_15, S6_14, C5_14);
nor gn2_5_15(n2_5_15, n1_5_15, C5_14);
nor gn3_5_15(n3_5_15, S6_14, n1_5_15);
nor gn4_5_15(n4_5_15, n2_5_15, n3_5_15);
nor gn5_5_15(n5_5_15, C4_15, n4_5_15);
nor gn6_5_15(n6_5_15, C4_15, n5_5_15);
nor gn7_5_15(n7_5_15, n4_5_15, n5_5_15);
nor gn8_5_15(S5_15, n6_5_15, n7_5_15);
nor gn9_5_15(C5_15, n1_5_15, n5_5_15);
/* FA MFA6_15(S6_15,C6_15,S7_14,C6_14,C5_15); */
nor gn1_6_15(n1_6_15, S7_14, C6_14);
nor gn2_6_15(n2_6_15, n1_6_15, C6_14);
nor gn3_6_15(n3_6_15, S7_14, n1_6_15);
nor gn4_6_15(n4_6_15, n2_6_15, n3_6_15);
nor gn5_6_15(n5_6_15, C5_15, n4_6_15);
nor gn6_6_15(n6_6_15, C5_15, n5_6_15);
nor gn7_6_15(n7_6_15, n4_6_15, n5_6_15);
nor gn8_6_15(S6_15, n6_6_15, n7_6_15);
nor gn9_6_15(C6_15, n1_6_15, n5_6_15);
/* FA MFA7_15(S7_15,C7_15,S8_14,C7_14,C6_15); */
nor gn1_7_15(n1_7_15, S8_14, C7_14);
nor gn2_7_15(n2_7_15, n1_7_15, C7_14);
nor gn3_7_15(n3_7_15, S8_14, n1_7_15);
nor gn4_7_15(n4_7_15, n2_7_15, n3_7_15);
nor gn5_7_15(n5_7_15, C6_15, n4_7_15);
nor gn6_7_15(n6_7_15, C6_15, n5_7_15);
nor gn7_7_15(n7_7_15, n4_7_15, n5_7_15);
nor gn8_7_15(S7_15, n6_7_15, n7_7_15);
nor gn9_7_15(C7_15, n1_7_15, n5_7_15);
/* FA MFA8_15(S8_15,C8_15,S9_14,C8_14,C7_15); */
nor gn1_8_15(n1_8_15, S9_14, C8_14);
nor gn2_8_15(n2_8_15, n1_8_15, C8_14);
nor gn3_8_15(n3_8_15, S9_14, n1_8_15);
nor gn4_8_15(n4_8_15, n2_8_15, n3_8_15);
nor gn5_8_15(n5_8_15, C7_15, n4_8_15);
nor gn6_8_15(n6_8_15, C7_15, n5_8_15);
nor gn7_8_15(n7_8_15, n4_8_15, n5_8_15);
nor gn8_8_15(S8_15, n6_8_15, n7_8_15);
nor gn9_8_15(C8_15, n1_8_15, n5_8_15);
/* FA MFA9_15(S9_15,C9_15,S10_14,C9_14,C8_15); */
nor gn1_9_15(n1_9_15, S10_14, C9_14);
nor gn2_9_15(n2_9_15, n1_9_15, C9_14);
nor gn3_9_15(n3_9_15, S10_14, n1_9_15);
nor gn4_9_15(n4_9_15, n2_9_15, n3_9_15);
nor gn5_9_15(n5_9_15, C8_15, n4_9_15);
nor gn6_9_15(n6_9_15, C8_15, n5_9_15);
nor gn7_9_15(n7_9_15, n4_9_15, n5_9_15);
nor gn8_9_15(S9_15, n6_9_15, n7_9_15);
nor gn9_9_15(C9_15, n1_9_15, n5_9_15);
/* FA MFA10_15(S10_15,C10_15,S11_14,C10_14,C9_15); */
nor gn1_10_15(n1_10_15, S11_14, C10_14);
nor gn2_10_15(n2_10_15, n1_10_15, C10_14);
nor gn3_10_15(n3_10_15, S11_14, n1_10_15);
nor gn4_10_15(n4_10_15, n2_10_15, n3_10_15);
nor gn5_10_15(n5_10_15, C9_15, n4_10_15);
nor gn6_10_15(n6_10_15, C9_15, n5_10_15);
nor gn7_10_15(n7_10_15, n4_10_15, n5_10_15);
nor gn8_10_15(S10_15, n6_10_15, n7_10_15);
nor gn9_10_15(C10_15, n1_10_15, n5_10_15);
/* FA MFA11_15(S11_15,C11_15,S12_14,C11_14,C10_15); */
nor gn1_11_15(n1_11_15, S12_14, C11_14);
nor gn2_11_15(n2_11_15, n1_11_15, C11_14);
nor gn3_11_15(n3_11_15, S12_14, n1_11_15);
nor gn4_11_15(n4_11_15, n2_11_15, n3_11_15);
nor gn5_11_15(n5_11_15, C10_15, n4_11_15);
nor gn6_11_15(n6_11_15, C10_15, n5_11_15);
nor gn7_11_15(n7_11_15, n4_11_15, n5_11_15);
nor gn8_11_15(S11_15, n6_11_15, n7_11_15);
nor gn9_11_15(C11_15, n1_11_15, n5_11_15);
/* FA MFA12_15(S12_15,C12_15,S13_14,C12_14,C11_15); */
nor gn1_12_15(n1_12_15, S13_14, C12_14);
nor gn2_12_15(n2_12_15, n1_12_15, C12_14);
nor gn3_12_15(n3_12_15, S13_14, n1_12_15);
nor gn4_12_15(n4_12_15, n2_12_15, n3_12_15);
nor gn5_12_15(n5_12_15, C11_15, n4_12_15);
nor gn6_12_15(n6_12_15, C11_15, n5_12_15);
nor gn7_12_15(n7_12_15, n4_12_15, n5_12_15);
nor gn8_12_15(S12_15, n6_12_15, n7_12_15);
nor gn9_12_15(C12_15, n1_12_15, n5_12_15);
/* FA MFA13_15(S13_15,C13_15,S14_14,C13_14,C12_15); */
nor gn1_13_15(n1_13_15, S14_14, C13_14);
nor gn2_13_15(n2_13_15, n1_13_15, C13_14);
nor gn3_13_15(n3_13_15, S14_14, n1_13_15);
nor gn4_13_15(n4_13_15, n2_13_15, n3_13_15);
nor gn5_13_15(n5_13_15, C12_15, n4_13_15);
nor gn6_13_15(n6_13_15, C12_15, n5_13_15);
nor gn7_13_15(n7_13_15, n4_13_15, n5_13_15);
nor gn8_13_15(S13_15, n6_13_15, n7_13_15);
nor gn9_13_15(C13_15, n1_13_15, n5_13_15);
/* FA MFA14_15(S14_15,C14_15,A15B15,C14_14,C13_15); */
nor gn1_14_15(n1_14_15, A15B15, C14_14);
nor gn2_14_15(n2_14_15, n1_14_15, C14_14);
nor gn3_14_15(n3_14_15, A15B15, n1_14_15);
nor gn4_14_15(n4_14_15, n2_14_15, n3_14_15);
nor gn5_14_15(n5_14_15, C13_15, n4_14_15);
nor gn6_14_15(n6_14_15, C13_15, n5_14_15);
nor gn7_14_15(n7_14_15, n4_14_15, n5_14_15);
nor gn8_14_15(S14_15, n6_14_15, n7_14_15);
nor gn9_14_15(C14_15, n1_14_15, n5_14_15);
endmodule /* TopLevel6288 */
/*************************************************************************/
|
Added c6288alt.gif.
cannot compute difference between binary files
Added c6288alt.html.
> > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c6288alt</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\Program Files\Microsoft Office\Office\HTML.DOT"> </HEAD> <BODY TEXT="#000000" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C6288 16x16 Multiplier</P> <P ALIGN="CENTER">Alternate Depiction</P> <P ALIGN="CENTER"> </P> </B></FONT><P ALIGN="CENTER"><IMG SRC="c6288alt.gif" WIDTH=713 HEIGHT=497></P></BODY> </HTML> |
Added c6288b.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 |
/****************************************************************************
* *
* VERILOG BEHAVIORAL DESCRIPTION OF THE ISCAS-85 BENCHMARK CIRCUIT c6288 *
* *
* Function: 16 x 16 Multiplier *
* *
* Written by: Mark C. Hansen *
* *
* Last modified: Nov 12, 1997 *
* *
****************************************************************************/
module Circuit6288h (in256, in239, in222, in205, in188, in171, in154, in137,
in120, in103, in86, in69, in52, in35, in18, in1,
in528, in511, in494, in477, in460, in443, in426, in409,
in392, in375, in358, in341, in324, in307, in290, in273,
out6287, out6288, out6280, out6270,
out6260, out6250, out6240, out6230,
out6220, out6210, out6200, out6190,
out6180, out6170, out6160, out6150,
out6123, out5971, out5672, out5308,
out4946, out4591, out4241, out3895,
out3552, out3211, out2877, out2548,
out2223, out1901, out1581, out545);
input in256, in239, in222, in205, in188, in171, in154, in137,
in120, in103, in86, in69, in52, in35, in18, in1,
in528, in511, in494, in477, in460, in443, in426, in409,
in392, in375, in358, in341, in324, in307, in290, in273;
output out6287, out6288, out6280, out6270,
out6260, out6250, out6240, out6230,
out6220, out6210, out6200, out6190,
out6180, out6170, out6160, out6150,
out6123, out5971, out5672, out5308,
out4946, out4591, out4241, out3895,
out3552, out3211, out2877, out2548,
out2223, out1901, out1581, out545;
wire [15:0] A, B;
wire [31:0] P;
assign
A[15:0] = {in256, in239, in222, in205, in188, in171, in154, in137,
in120, in103, in86, in69, in52, in35, in18, in1},
B[15:0] = {in528, in511, in494, in477, in460, in443, in426, in409,
in392, in375, in358, in341, in324, in307, in290, in273},
{out6287, out6288, out6280, out6270,
out6260, out6250, out6240, out6230,
out6220, out6210, out6200, out6190,
out6180, out6170, out6160, out6150,
out6123, out5971, out5672, out5308,
out4946, out4591, out4241, out3895,
out3552, out3211, out2877, out2548,
out2223, out1901, out1581, out545} = P[31:0];
TopLevel6288b Ckt6288b (A, B, P);
endmodule /* Circuit6288b */
/*************************************************************************/
module TopLevel6288b (A, B, P);
input[15:0] A, B;
output[31:0] P;
assign P = A*B;
endmodule /* TopLevel6288b */
/*************************************************************************/
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Added c6288bus.html.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c6288bus</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\Program Files\Microsoft Office\Office\HTML.DOT"> </HEAD> <BODY TEXT="#000000" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C6288 16x16 Multiplier</P> <P ALIGN="CENTER">Bus Translations</P> </B></FONT><P ALIGN="CENTER"> </P> <TABLE BORDER CELLSPACING=1 WIDTH=802> <TR><TD WIDTH="14%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997592"></A><B>I/O Busses</B></TD> <TD WIDTH="14%" VALIGN="MIDDLE"> <B><P ALIGN="CENTER"><A NAME="pgfId_997594"></A>Function</B></TD> <TD WIDTH="73%" VALIGN="MIDDLE"> <B><P ALIGN="CENTER"><A NAME="pgfId_997599"></A>ISCAS-85 Netlist Numbers </B></TD> </TR> <TR><TD WIDTH="14%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997601"></A>A[15:0]</TD> <TD WIDTH="14%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997603"></A>A bus</TD> <TD WIDTH="73%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997605"></A>256, 239, 222, 205, 188, 171, 154, 137, 120, 103, 86, 69, 52, 35, 18, 1</TD> </TR> <TR><TD WIDTH="14%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997607"></A>B[15:0]</TD> <TD WIDTH="14%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997609"></A>B bus</TD> <TD WIDTH="73%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997611"></A>528, 511, 494, 477, 460, 443, 426, 409, 392, 375, 358, 341, 324, 307, 290, 273</TD> </TR> <TR><TD WIDTH="14%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997613"></A>P[31:0]</TD> <TD WIDTH="14%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997615"></A>Product bus</TD> <TD WIDTH="73%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997617"></A>6287, 6288, 6280, 6270,6260, 6250, 6240, 6230, 6220, 6210, 6200, 6190,6180, 6170, 6160, 6150, 6123, 5971, 5672, 5308, 4946, 4591, 4241, 3895, 3552, 3211, 2877, 2548, 2223, 1901, 1581, 545</TD> </TR> </TABLE> <P> </P> <P> </P></BODY> </HTML> |
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> > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c6288fa</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\Program Files\Microsoft Office\Office\HTML.DOT"> </HEAD> <BODY TEXT="#000000" LINK="#0000ff" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C6288 16x16 Multiplier</P> <P ALIGN="CENTER">Full Adder Module</P> </B></FONT><P ALIGN="CENTER">The 15 top-row half adders lack the C_i input; each has two inverters at locations V. The single half adder in the bottom row lacks the B input, thereby acquiring two inverters at locations W.</P> <B><FONT SIZE=5><P ALIGN="CENTER"> </P> </B></FONT><P ALIGN="CENTER"><IMG SRC="c6288fa.gif" WIDTH=640 HEIGHT=367></P> <P ALIGN="CENTER"> </P></BODY> </HTML> |
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML EXPERIMENTAL 970324//EN">
<HTML>
<HEAD>
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<LINK REL="STYLESHEET" HREF="c7552.css">
<TITLE>
High-Level Model of c7552
</TITLE>
</HEAD>
<BODY BGCOLOR="#ffffff">
<DIV>
<H1 CLASS="Title">
<A NAME="pgfId=933994">
</A>
High-Level Model of c7552</H1>
<br>
<P>
<B> Statistics: </B> 207 inputs; 108 outputs; 3512 gates</P>
<P>
<B> Function: </B> 34-bit adder and magnitude comparator with input parity checking</P>
<P>
This benchmark circuit contains a 34-bit adder (M5), a 34-bit magnitude comparator (M8) using another 34-bit adder, and a parity checker (M9). Each of the XA, YA, and YB buses is fed by a set of 2:1 multiplexers controlled by the Sel input. Bits 31-22 of XA and YB can be set to logic 0 with the Mask input. The two adders M5 and M8 are identical, and are of carry select type, as are those of c5315. They consist of alternating 4- and 5-bit blocks, with the last block being 2 bits. The comparator (M8) of this benchmark is similar to that of c2670. It performs the comparison YB>XB (if Sel=0) or YB>!YA1 (if Sel=1) by calculating YB+!XB (if Sel=0) or YB+!YA1 (if Sel=1) (Note: the input bus YA1 is assumed to be inverted). The comparator has an output (CoutY) for the whole 34-bit inputs as well as an output (CoutY_17) for the 17-bit portion of its inputs. Module M7 calculates the parity for the following four parts of the adder output SumX: SumX[8:0], SumX[17:9], SumX[26:18], SumX[33:27]. Module M9 appears to be a type of sanity checker that calculates the AND of the parities of all its inputs.</P>
<br>
<A HREF="#pgfId=1015521">
<B>Inputs/Outputs vs. Netlist numbers</B></A>
<HR>
<B><P>Models:</P></B>
<UL>
<LI>I. Original ISCAS gate-level netlist
<UL>
<LI><A HREF="c7552.isc">in ISCAS-89 format</A> </LI>
<LI><A HREF="c7552gate.v">in Verilog</A></LI>
</UL>
</LI>
<LI>II. <A HREF="c7552high.v">Verilog hierarchical netlist</A>
(functionally equivalent to I) </LI>
<LI>III. <A HREF="flat7552.v">Verilog flat netlist </A>
(flat version of II; functionally equivalent to I,
but with minor structural differences) </LI>
</UL>
<HR>
<DIV>
<MAP NAME="c7552-1">
</MAP>
<IMG SRC="c7552-1.gif" USEMAP="#c7552-1">
</DIV>
<br>
<B>Detailed bus definitions:</B>
<P CLASS="Body">
- XA:</P>
<UL>
<LI CLASS="Bulleted">
XA[21:0] = XA0[21:0] if Sel=0, XA1[21:0] if Sel=1</LI>
<LI CLASS="Bulleted">
XA[31:22] = XA0[21:0].Mask if Sel=0, XA1[21:0].Mask if Sel=1</LI>
<LI CLASS="Bulleted">
XA[32] = XA[33] = XYAext</LI>
</UL>
<P CLASS="Body">
- NotXB: </P>
<UL>
<LI CLASS="Bulleted">
NotXB[0] = ! XB[0] if Sel=1, <B>logic 0</B> if Sel=0</LI>
<LI CLASS="Bulleted">
NotXB[31:1] = ! XB[31:1]</LI>
<LI CLASS="Bulleted">
NotXB[33:32] = ! ( XB[33:32]. XYBext )</LI>
</UL>
<P CLASS="Body">
- YA:</P>
<UL>
<LI CLASS="Bulleted">
YA[0] = <B>logic 1</B> if Sel=0, YA1[0] if Sel=1</LI>
<LI CLASS="Bulleted">
YA[31:1] = NotXB[31:1] if Sel=0, YA1[31:1] if Sel=1</LI>
<LI CLASS="Bulleted">
YA[32] = YA[33] = XYAext.</LI>
</UL>
<P CLASS="Body">
- YB:</P>
<UL>
<LI CLASS="Bulleted">
YB[21:0] = YB0[21:0] if Sel=0, XA1[21:0] if Sel=1</LI>
<LI CLASS="Bulleted">
YB[31:22] = YB0[21:0].Mask if Sel=0, XA1[21:0].Mask if Sel=1</LI>
<LI CLASS="Bulleted">
YB[33:32] = YB0[33:32] + ! XYBext</LI>
</UL>
- XBbuf[33:0] = XB[33:0]</P>
- PCYA0buf[3:0] = { PCYA0[6], PCYA0[3], PCYA0[2], PCYA0[0] }</P>
<HR>
<br>
<DIV>
<IMG SRC="c7552-2.gif" USEMAP="#c7552-1">
</DIV>
<br>
<DIV>
<IMG SRC="c7552-3.gif" USEMAP="#c7552-1">
</DIV>
<br>
<DIV>
<IMG SRC="c7552-4.gif" USEMAP="#c7552-1">
</DIV>
<br>
<DIV>
<IMG SRC="c7552-5.gif" USEMAP="#c7552-1">
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<br>
<br>
<br>
<br>
<A NAME="pgfId=1015521">
</A>
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<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=1015522">
</A>
Input</P>
</TH>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="CellHeading">
<A NAME="pgfId=1015524">
</A>
Netlist numbers</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015526">
</A>
XA0[31:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015528">
</A>
213, 214, 215, 216, 209, 153, 154, 155, 156, 157, 158, 159, 160, 151, 219, 220,
221, 222, 223, 224, 225, 226, 217, 231, 232, 233, 234, 235, 236, 237, 238, <B>logic 0</B></P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015531">
</A>
XA1[31:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015533">
</A>
10 *{<B>logic 1</B>}, 135, 144, 138, 147, 66, 50,
32, 35, 47, 121, 94, 97, 118, 100, 124, 127, 130, 103, 23, 26, 29, 41</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015536">
</A>
XB[33:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015538">
</A>
1496, 1492, 1486, 1480, 106, 1469, 1462, 2256, 2253, 2247, 2239, 2236, 2230, 2224, 2218, 2211, 4437,
4432, 4427, 4420, 4415, 4410, 4405, 4400, 4394, 3749, 3743, 3737, 3729, 3723, 3717, 3711, 3705, 3701</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015541">
</A>
YA1[31:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015543">
</A>
88, 112, 87, 111, 113, 110, 109, 86, 63, 64, 85, 84, 83, 65, 62, 61,
60, 79, 80, 81, 59, 78, 77, 56, 55, 54, 53, 73, 75, 76, 74, 70</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015546">
</A>
YB0[33:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015548">
</A>
2204, 1455, 166, 167, 168, 169, <B>logic 1</B>, 173, 174, 175, 176, 177, 178, 179, 180, 171, 189,
190, 191, 192, 193, 194, 195, 196, 187, 200, 201, 202, 203, 204, 205, 206, 207, <B>logic 0</B></P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015551">
</A>
!Sel</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015553">
</A>
18</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015555">
</A>
CinX, CinY</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015557">
</A>
4526, 89</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015559">
</A>
Mask=!Mask1+!Mask2</P>
<P CLASS="CellBodyL">
<A NAME="pgfId=1015560">
</A>
Mask1, Mask2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015562">
</A>
</P>
<P CLASS="CellBodyL">
<A NAME="pgfId=1015563">
</A>
112, 9</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015565">
</A>
XYAext, XYBext</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015567">
</A>
38, 4528</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015569">
</A>
PCXA0[6:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015571">
</A>
<B>logic 1</B>, 211, 212, 161, 227, 239, 229</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015573">
</A>
PCXA1[6:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015575">
</A>
3*{<B>logic 1</B>}, 141, 115, 44, 41</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015577">
</A>
PCYA0[6:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015579">
</A>
1459, 1496, 1492, 2208, 4398, 3701, 3698</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015581">
</A>
PCYA1[6:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015583">
</A>
114, 2204, 1455, 82, 58, 70, 69</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015585">
</A>
PCYB0[6:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015587">
</A>
170, 164, 165, 181, 197, 208, 198</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015589">
</A>
StrbIn[15:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015591">
</A>
199, 188, 172, 162, 186, 185, 182, 183, 230, 218, 152, 210, 240, 228, 184, 150</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015593">
</A>
MiscIn[7:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="CellBodyL">
<A NAME="pgfId=1015595">
</A>
57, 5, 133, 134, 1197, 15, 163, 1</P>
</TD>
</TR>
</TABLE>
<TABLE BORDER="1">
<TR>
<TH ROWSPAN="1" COLSPAN="1">
<P>
Output</P>
</TD>
<TH ROWSPAN="1" COLSPAN="1">
<P>
Netlist numbers</P>
</TH>
</P>
</TR>
<TR>
<P>
<TD ROWSPAN="1" COLSPAN="1">
<P>
SumX[33:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P>
469, 471, 327, 330, 333, 336, 324, 298, 301, 304, 307, 310, 313, 316, 319, 295, 347,
350, 353, 356, 359, 362, 365, 368, 344, 376, 379, 382, 385, 388, 391, 394, 397, 373</P>
</TD>
</P>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P>
!SumPar[3:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P>
338, 321, 370, 399</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P>
CoutX1, CoutX2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P>
(270, 246)<A HREF="#pgfId=1015519" CLASS="footnote">
*</A>
, (273, 276)<A HREF="#pgfId=1015519" CLASS="footnote">
*</A></P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P>
CoutY1, CoutY2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P>
(258, 264)<A HREF="#pgfId=1015519" CLASS="footnote">
*</A>
, 249</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P>
CoutY_17</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P>
252</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P>
ParCheck[3:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P>
416, 414, 412, 418</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P>
XBbuf[33:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P>
440, 438, 442, 444, 446, 448, 436, 480, 482, 484, 486, 488, 490, 492, 494, 478, 524,
526, 528, 530, 532, 534, 536, 538, 522, 544, 546, 548, 550, 552, 554, 556, 558, 542</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P>
StrbOut</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P>
410, 408. 406, 404</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P>
PCYA0buf[3:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P>
450, 496, 540, 560</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P>
MiscOut[5:0]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P>
402, 289, 292, 279, 278, 2</P>
</TD>
</TR>
</TABLE>
<br>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="TableFootnote">
<SPAN CLASS="footnoteNumber">
*</SPAN>
<A NAME="pgfId=1015519">
</A>
(a,b): a,b are identical outputs.</P>
<br>
<P>
<A HREF="#pgfId=933994">
Go to top of this file</A></P>
<P>
<A HREF="../benchmark.html">
Go back to the Benchmark List</A></P>
</DIV>
</DIV>
</BODY>
</HTML>
|
Added c7552/c7552.isc.
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 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3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 | # combinational logic example "c7552" #------------------------------------------------------------- # # # total number of lines in the netlist .............. 7552 # simplistically reduced equivalent fault set size = 7550 # lines from primary input gates ....... 207 # lines from primary output gates ....... 108 # lines from interior gate outputs ...... 3405 # lines from ** 1300 ** fanout stems ... 3833 # # avg_fanin = 1.75, max_fanin = 5 # avg_fanout = 2.95, max_fanout = 15 # # # # # INPUT(1) #... primary input INPUT(5) #... primary input INPUT(9) #... primary input INPUT(12) #... primary input INPUT(15) #... primary input INPUT(18) #... primary input INPUT(23) #... primary input INPUT(26) #... primary input INPUT(29) #... primary input INPUT(32) #... primary input INPUT(35) #... primary input INPUT(38) #... primary input INPUT(41) #... primary input INPUT(44) #... primary input INPUT(47) #... primary input INPUT(50) #... primary input INPUT(53) #... primary input INPUT(54) #... primary input INPUT(55) #... primary input INPUT(56) #... primary input INPUT(57) #... primary input INPUT(58) #... primary input INPUT(59) #... primary input INPUT(60) #... primary input INPUT(61) #... primary input INPUT(62) #... primary input INPUT(63) #... primary input INPUT(64) #... primary input INPUT(65) #... primary input INPUT(66) #... primary input INPUT(69) #... primary input INPUT(70) #... primary input INPUT(73) #... primary input INPUT(74) #... primary input INPUT(75) #... primary input INPUT(76) #... primary input INPUT(77) #... primary input INPUT(78) #... primary input INPUT(79) #... primary input INPUT(80) #... primary input INPUT(81) #... primary input INPUT(82) #... primary input INPUT(83) #... primary input INPUT(84) #... primary input INPUT(85) #... primary input INPUT(86) #... primary input INPUT(87) #... primary input INPUT(88) #... primary input INPUT(89) #... primary input INPUT(94) #... primary input INPUT(97) #... primary input INPUT(100) #... primary input INPUT(103) #... primary input INPUT(106) #... primary input INPUT(109) #... primary input INPUT(110) #... primary input INPUT(111) #... primary input INPUT(112) #... primary input INPUT(113) #... primary input INPUT(114) #... primary input INPUT(115) #... primary input INPUT(118) #... primary input INPUT(121) #... primary input INPUT(124) #... primary input INPUT(127) #... primary input INPUT(130) #... primary input INPUT(133) #... primary input INPUT(134) #... primary input INPUT(135) #... primary input INPUT(138) #... primary input INPUT(141) #... primary input INPUT(144) #... primary input INPUT(147) #... primary input INPUT(150) #... primary input INPUT(151) #... primary input INPUT(152) #... primary input INPUT(153) #... primary input INPUT(154) #... primary input INPUT(155) #... primary input INPUT(156) #... primary input INPUT(157) #... primary input INPUT(158) #... primary input INPUT(159) #... primary input INPUT(160) #... primary input INPUT(161) #... primary input INPUT(162) #... primary input INPUT(163) #... primary input INPUT(164) #... primary input INPUT(165) #... primary input INPUT(166) #... primary input INPUT(167) #... primary input INPUT(168) #... primary input INPUT(169) #... primary input INPUT(170) #... primary input INPUT(171) #... primary input INPUT(172) #... primary input INPUT(173) #... primary input INPUT(174) #... primary input INPUT(175) #... primary input INPUT(176) #... primary input INPUT(177) #... primary input INPUT(178) #... primary input INPUT(179) #... primary input INPUT(180) #... primary input INPUT(181) #... primary input INPUT(182) #... primary input INPUT(183) #... primary input INPUT(184) #... primary input INPUT(185) #... primary input INPUT(186) #... primary input INPUT(187) #... primary input INPUT(188) #... primary input INPUT(189) #... primary input INPUT(190) #... primary input INPUT(191) #... primary input INPUT(192) #... primary input INPUT(193) #... primary input INPUT(194) #... primary input INPUT(195) #... primary input INPUT(196) #... primary input INPUT(197) #... primary input INPUT(198) #... primary input INPUT(199) #... primary input INPUT(200) #... primary input INPUT(201) #... primary input INPUT(202) #... primary input INPUT(203) #... primary input INPUT(204) #... primary input INPUT(205) #... primary input INPUT(206) #... primary input INPUT(207) #... primary input INPUT(208) #... primary input INPUT(209) #... primary input INPUT(210) #... primary input INPUT(211) #... primary input INPUT(212) #... primary input INPUT(213) #... primary input INPUT(214) #... primary input INPUT(215) #... primary input INPUT(216) #... primary input INPUT(217) #... primary input INPUT(218) #... primary input INPUT(219) #... primary input INPUT(220) #... primary input INPUT(221) #... primary input INPUT(222) #... primary input INPUT(223) #... primary input INPUT(224) #... primary input INPUT(225) #... primary input INPUT(226) #... primary input INPUT(227) #... primary input INPUT(228) #... primary input INPUT(229) #... primary input INPUT(230) #... primary input INPUT(231) #... primary input INPUT(232) #... primary input INPUT(233) #... primary input INPUT(234) #... primary input INPUT(235) #... primary input INPUT(236) #... primary input INPUT(237) #... primary input INPUT(238) #... primary input INPUT(239) #... primary input INPUT(240) #... primary input INPUT(339) #... primary input INPUT(1197) #... primary input INPUT(1455) #... primary input INPUT(1459) #... primary input INPUT(1462) #... primary input INPUT(1469) #... primary input INPUT(1480) #... primary input INPUT(1486) #... primary input INPUT(1492) #... primary input INPUT(1496) #... primary input INPUT(2204) #... primary input INPUT(2208) #... primary input INPUT(2211) #... primary input INPUT(2218) #... primary input INPUT(2224) #... primary input INPUT(2230) #... primary input INPUT(2236) #... primary input INPUT(2239) #... primary input INPUT(2247) #... primary input INPUT(2253) #... primary input INPUT(2256) #... primary input INPUT(3698) #... primary input INPUT(3701) #... primary input INPUT(3705) #... primary input INPUT(3711) #... primary input INPUT(3717) #... primary input INPUT(3723) #... primary input INPUT(3729) #... primary input INPUT(3737) #... primary input INPUT(3743) #... primary input INPUT(3749) #... primary input INPUT(4393) #... primary input INPUT(4394) #... primary input INPUT(4400) #... primary input INPUT(4405) #... primary input INPUT(4410) #... primary input INPUT(4415) #... primary input INPUT(4420) #... primary input INPUT(4427) #... primary input INPUT(4432) #... primary input INPUT(4437) #... primary input INPUT(4526) #... primary input INPUT(4528) #... primary input # # OUTPUT(339) #... primary output OUTPUT(2) #... primary output OUTPUT(3) #... primary output OUTPUT(450) #... primary output OUTPUT(448) #... primary output OUTPUT(444) #... primary output OUTPUT(442) #... primary output OUTPUT(440) #... primary output OUTPUT(438) #... primary output OUTPUT(496) #... primary output OUTPUT(494) #... primary output OUTPUT(492) #... primary output OUTPUT(490) #... primary output OUTPUT(488) #... primary output OUTPUT(486) #... primary output OUTPUT(484) #... primary output OUTPUT(482) #... primary output OUTPUT(480) #... primary output OUTPUT(560) #... primary output OUTPUT(542) #... primary output OUTPUT(558) #... primary output OUTPUT(556) #... primary output OUTPUT(554) #... primary output OUTPUT(552) #... primary output OUTPUT(550) #... primary output OUTPUT(548) #... primary output OUTPUT(546) #... primary output OUTPUT(544) #... primary output OUTPUT(540) #... primary output OUTPUT(538) #... primary output OUTPUT(536) #... primary output OUTPUT(534) #... primary output OUTPUT(532) #... primary output OUTPUT(530) #... primary output OUTPUT(528) #... primary output OUTPUT(526) #... primary output OUTPUT(524) #... primary output OUTPUT(279) #... primary output OUTPUT(436) #... primary output OUTPUT(478) #... primary output OUTPUT(522) #... primary output OUTPUT(402) #... primary output OUTPUT(404) #... primary output OUTPUT(406) #... primary output OUTPUT(408) #... primary output OUTPUT(410) #... primary output OUTPUT(432) #... primary output OUTPUT(446) #... primary output OUTPUT(284) #... primary output OUTPUT(286) #... primary output OUTPUT(289) #... primary output OUTPUT(292) #... primary output OUTPUT(341) #... primary output OUTPUT(281) #... primary output OUTPUT(453) #... primary output OUTPUT(278) #... primary output OUTPUT(373) #... primary output OUTPUT(246) #... primary output OUTPUT(258) #... primary output OUTPUT(264) #... primary output OUTPUT(270) #... primary output OUTPUT(388) #... primary output OUTPUT(391) #... primary output OUTPUT(394) #... primary output OUTPUT(397) #... primary output OUTPUT(376) #... primary output OUTPUT(379) #... primary output OUTPUT(382) #... primary output OUTPUT(385) #... primary output OUTPUT(412) #... primary output OUTPUT(414) #... primary output OUTPUT(416) #... primary output OUTPUT(249) #... primary output OUTPUT(295) #... primary output OUTPUT(324) #... primary output OUTPUT(252) #... primary output OUTPUT(276) #... primary output OUTPUT(310) #... primary output OUTPUT(313) #... primary output OUTPUT(316) #... primary output OUTPUT(319) #... primary output OUTPUT(327) #... primary output OUTPUT(330) #... primary output OUTPUT(333) #... primary output OUTPUT(336) #... primary output OUTPUT(418) #... primary output OUTPUT(273) #... primary output OUTPUT(298) #... primary output OUTPUT(301) #... primary output OUTPUT(304) #... primary output OUTPUT(307) #... primary output OUTPUT(344) #... primary output OUTPUT(422) #... primary output OUTPUT(469) #... primary output OUTPUT(419) #... primary output OUTPUT(471) #... primary output OUTPUT(359) #... primary output OUTPUT(362) #... primary output OUTPUT(365) #... primary output OUTPUT(368) #... primary output OUTPUT(347) #... primary output OUTPUT(350) #... primary output OUTPUT(353) #... primary output OUTPUT(356) #... primary output OUTPUT(321) #... primary output OUTPUT(338) #... primary output OUTPUT(370) #... primary output OUTPUT(399) #... primary output # # # Output Type Inputs... # ------ ---- --------- 2 = buff( 1) 3 = buff( 1) 400 = not( 57) 1184 = and( 134, 133) 450 = buff( 1459) 448 = buff( 1469) 444 = buff( 1480) 442 = buff( 1486) 440 = buff( 1492) 438 = buff( 1496) 1501 = and( 162, 172, 188, 199) 496 = buff( 2208) 494 = buff( 2218) 492 = buff( 2224) 490 = buff( 2230) 488 = buff( 2236) 486 = buff( 2239) 484 = buff( 2247) 482 = buff( 2253) 480 = buff( 2256) 2857 = and( 150, 184, 228, 240) 560 = buff( 3698) 542 = buff( 3701) 558 = buff( 3705) 556 = buff( 3711) 554 = buff( 3717) 552 = buff( 3723) 550 = buff( 3729) 548 = buff( 3737) 546 = buff( 3743) 544 = buff( 3749) 540 = buff( 4393) 538 = buff( 4400) 536 = buff( 4405) 534 = buff( 4410) 532 = buff( 4415) 530 = buff( 4420) 528 = buff( 4427) 526 = buff( 4432) 524 = buff( 4437) 4442 = and( 183, 182, 185, 186) 4514 = and( 210, 152, 218, 230) 279 = not( 15) 401 = not( 5) 573 = buff( 1) 574 = not( 5) 575 = not( 5) 1178 = not( 2236) 1186 = not( 2253) 1192 = not( 2256) 1198 = buff( 38) 1205 = buff( 15) 1206 = nand( 12, 9) 1207 = nand( 12, 9) 1210 = buff( 38) 1458 = not( 1455) 1461 = not( 1459) 436 = buff( 1462) 1464 = not( 1462) 1471 = not( 1469) 1475 = buff( 106) 1482 = not( 1480) 1488 = not( 1486) 1495 = not( 1492) 1499 = not( 1496) 1500 = not( 106) 1503 = buff( 18) 1512 = buff( 18) 1518 = and( 4528, 1492) 1524 = buff( 18) 1535 = not( 18) 1541 = nand( 4528, 1496) 2207 = not( 2204) 2210 = not( 2208) 478 = buff( 2211) 2213 = not( 2211) 2220 = not( 2218) 2226 = not( 2224) 2232 = not( 2230) 2238 = not( 2236) 2241 = not( 2239) 2249 = not( 2247) 2255 = not( 2253) 2258 = not( 2256) 2828 = buff( 4526) 3700 = not( 3698) 3703 = not( 3701) 3707 = not( 3705) 3713 = not( 3711) 3719 = not( 3717) 3725 = not( 3723) 3731 = not( 3729) 3739 = not( 3737) 3745 = not( 3743) 3751 = not( 3749) 4121 = not( 4393) 522 = buff( 4394) 4396 = not( 4394) 4402 = not( 4400) 4407 = not( 4405) 4412 = not( 4410) 4417 = not( 4415) 4422 = not( 4420) 4429 = not( 4427) 4434 = not( 4432) 4439 = not( 4437) 4833 = buff( 4526) 402 = nand( 400, 401) 404 = not( 2857) 406 = not( 4514) 408 = not( 4442) 410 = not( 1501) 2876 = and( 2857, 4514) 2878 = and( 4442, 1501) 432 = buff( 573) 446 = buff( 1475) 1519 = not( 1518) 2871 = and( 4528, 1458) 2883 = nand( 4528, 2207) 280 = and( 1184, 575) 284 = nand( 1197, 574) 286 = not( 1205) 289 = nand( 1197, 574) 292 = nand( 1184, 575) 341 = not( 1205) 4839 = not( 4833) 572 = buff( 573) 581 = buff( 1206) 587 = buff( 1512) 601 = buff( 1206) 606 = buff( 1512) 650 = buff( 1206) 657 = buff( 1512) 671 = buff( 1207) 678 = buff( 1503) 777 = and( 1541, 1198) 1115 = and( 1541, 1198) 1336 = buff( 1512) 1350 = buff( 1503) 1477 = not( 1475) 1507 = not( 1503) 1514 = not( 1512) 1530 = not( 1524) 2259 = buff( 1535) 2833 = not( 2828) 2872 = not( 2871) 2886 = buff( 1207) 2892 = buff( 1503) 2905 = buff( 1207) 2909 = buff( 1503) 3622 = buff( 1524) 3635 = buff( 1524) 3755 = buff( 1535) 4640 = buff( 1524) 4653 = buff( 1524) 4873 = buff( 1541) 4876 = buff( 1198) 4881 = buff( 1488) 4889 = buff( 1482) 4905 = buff( 1471) 4916 = buff( 1198) 4921 = buff( 1464) 5175 = buff( 1541) 5178 = buff( 1198) 5186 = buff( 1198) 5191 = buff( 1488) 5199 = buff( 1482) 5215 = buff( 1471) 5223 = buff( 1464) 5393 = buff( 1192) 5401 = buff( 1186) 5409 = buff( 2249) 5417 = buff( 1178) 5425 = buff( 2232) 5433 = buff( 2226) 5441 = buff( 2220) 5449 = buff( 2241) 5457 = buff( 2213) 5745 = buff( 1192) 5753 = buff( 1186) 5761 = buff( 2249) 5769 = buff( 2241) 5777 = buff( 1178) 5785 = buff( 2232) 5793 = buff( 2226) 5801 = buff( 2220) 5809 = buff( 2213) 5865 = buff( 3751) 5873 = buff( 3745) 5881 = buff( 3739) 5889 = buff( 3731) 5897 = buff( 3725) 5905 = buff( 3719) 5913 = buff( 3713) 5921 = buff( 3707) 5985 = buff( 3751) 5993 = buff( 3745) 6001 = buff( 3739) 6009 = buff( 3725) 6017 = buff( 3719) 6025 = buff( 3713) 6033 = buff( 3707) 6041 = buff( 3731) 6514 = buff( 1210) 6554 = buff( 1210) 6567 = buff( 4439) 6575 = buff( 4434) 6583 = buff( 4429) 6591 = buff( 4422) 6599 = buff( 4417) 6607 = buff( 4412) 6615 = buff( 4407) 6623 = buff( 4402) 6631 = buff( 4396) 6853 = buff( 4439) 6861 = buff( 4434) 6869 = buff( 4429) 6877 = buff( 4417) 6885 = buff( 4412) 6893 = buff( 4407) 6901 = buff( 4402) 6909 = buff( 4422) 6917 = buff( 4396) 281 = not( 280) 453 = buff( 572) 784 = and( 1519, 1198) 1014 = and( 1198, 1519) 3221 = and( 2883, 1210) 4913 = buff( 1519) 4929 = nor( 1519, 1198) 5183 = buff( 1519) 5231 = nor( 1198, 1519) 6511 = buff( 2883) 278 = and( 163, 572) 615 = and( 170, 587) 594 = not( 587) 611 = not( 606) 617 = and( 169, 587) 619 = and( 168, 587) 621 = and( 167, 587) 623 = and( 166, 606) 625 = and( 165, 606) 627 = and( 164, 606) 664 = not( 657) 685 = not( 678) 691 = and( 177, 657) 693 = and( 176, 657) 695 = and( 175, 657) 697 = and( 174, 657) 699 = and( 173, 657) 701 = and( 157, 678) 703 = and( 156, 678) 705 = and( 155, 678) 707 = and( 154, 678) 709 = and( 153, 678) 4879 = not( 4873) 4880 = not( 4876) 4887 = not( 4881) 4895 = not( 4889) 4911 = not( 4905) 4920 = not( 4916) 4927 = not( 4921) 5181 = not( 5175) 5182 = not( 5178) 5190 = not( 5186) 5197 = not( 5191) 5205 = not( 5199) 5221 = not( 5215) 5229 = not( 5223) 1343 = not( 1336) 1357 = not( 1350) 1364 = and( 181, 1336) 1366 = and( 171, 1336) 1368 = and( 180, 1336) 1370 = and( 179, 1336) 1372 = and( 178, 1336) 1374 = and( 161, 1350) 1376 = and( 151, 1350) 1378 = and( 160, 1350) 1380 = and( 159, 1350) 1382 = and( 158, 1350) 5399 = not( 5393) 5407 = not( 5401) 5415 = not( 5409) 5423 = not( 5417) 5431 = not( 5425) 5439 = not( 5433) 5447 = not( 5441) 5455 = not( 5449) 5463 = not( 5457) 5751 = not( 5745) 5759 = not( 5753) 5767 = not( 5761) 5775 = not( 5769) 5783 = not( 5777) 5791 = not( 5785) 5799 = not( 5793) 5807 = not( 5801) 5815 = not( 5809) 2019 = buff( 1514) 2032 = buff( 1507) 2117 = buff( 1514) 2130 = buff( 1507) 2266 = not( 2259) 2272 = buff( 1507) 2286 = and( 44, 2259) 2288 = and( 41, 2259) 2290 = and( 29, 2259) 2292 = and( 26, 2259) 2294 = and( 23, 2259) 5871 = not( 5865) 5879 = not( 5873) 5887 = not( 5881) 5895 = not( 5889) 5903 = not( 5897) 5911 = not( 5905) 5919 = not( 5913) 5927 = not( 5921) 5991 = not( 5985) 5999 = not( 5993) 6007 = not( 6001) 6015 = not( 6009) 6023 = not( 6017) 6031 = not( 6025) 6039 = not( 6033) 6047 = not( 6041) 2899 = not( 2892) 2914 = not( 2909) 2919 = and( 209, 2892) 2921 = and( 216, 2892) 2923 = and( 215, 2892) 2925 = and( 214, 2892) 2927 = and( 213, 2909) 2929 = and( 212, 2909) 2931 = and( 211, 2909) 6518 = not( 6514) 3173 = and( 2872, 1210) 6558 = not( 6554) 6573 = not( 6567) 6581 = not( 6575) 6589 = not( 6583) 6597 = not( 6591) 6605 = not( 6599) 6613 = not( 6607) 6621 = not( 6615) 6629 = not( 6623) 6637 = not( 6631) 3629 = not( 3622) 3642 = not( 3635) 3649 = and( 1461, 3622) 3651 = and( 1464, 3622) 3653 = and( 1471, 3622) 3655 = and( 1500, 3622) 3657 = and( 1482, 3622) 3659 = and( 1488, 3635) 3661 = and( 1495, 3635) 3663 = and( 1499, 3635) 3762 = not( 3755) 3768 = buff( 1507) 3782 = and( 47, 3755) 3784 = and( 35, 3755) 3786 = and( 32, 3755) 3788 = and( 50, 3755) 3790 = and( 66, 3755) 6859 = not( 6853) 6867 = not( 6861) 6875 = not( 6869) 6883 = not( 6877) 6891 = not( 6885) 6899 = not( 6893) 6907 = not( 6901) 6915 = not( 6909) 6923 = not( 6917) 4094 = buff( 1530) 4107 = buff( 1530) 4444 = buff( 1530) 4457 = buff( 1530) 4647 = not( 4640) 4660 = not( 4653) 4667 = and( 2210, 4640) 4669 = and( 2213, 4640) 4671 = and( 2220, 4640) 4673 = and( 2226, 4640) 4675 = and( 2232, 4640) 4677 = and( 2238, 4653) 4679 = and( 2241, 4653) 4681 = and( 2249, 4653) 4683 = and( 2255, 4653) 4685 = and( 2258, 4653) 4897 = buff( 1477) 5207 = buff( 1477) 6551 = buff( 2872) 763 = nand( 4876, 4879) 764 = nand( 4873, 4880) 4919 = not( 4913) 886 = nand( 4913, 4920) 1005 = nand( 5178, 5181) 1006 = nand( 5175, 5182) 5189 = not( 5183) 1018 = nand( 5183, 5190) 5237 = not( 5231) 6517 = not( 6511) 3169 = nand( 6511, 6518) 4935 = not( 4929) 4970 = buff( 784) 5239 = buff( 1014) 577 = or( 594, 615) 616 = or( 594, 587) 618 = or( 594, 617) 620 = or( 594, 619) 622 = or( 594, 621) 624 = or( 611, 623) 626 = or( 611, 625) 628 = or( 611, 627) 692 = or( 664, 691) 694 = or( 664, 693) 696 = or( 664, 695) 698 = or( 664, 697) 700 = or( 664, 699) 702 = or( 685, 701) 704 = or( 685, 703) 706 = or( 685, 705) 708 = or( 685, 707) 710 = or( 685, 709) 765 = nand( 763, 764) 4903 = not( 4897) 885 = nand( 4916, 4919) 1007 = nand( 1005, 1006) 1017 = nand( 5186, 5189) 5213 = not( 5207) 1363 = and( 141, 1343) 1365 = and( 147, 1343) 1367 = and( 138, 1343) 1369 = and( 144, 1343) 1371 = and( 135, 1343) 1373 = and( 141, 1357) 1375 = and( 147, 1357) 1377 = and( 138, 1357) 1379 = and( 144, 1357) 1381 = and( 135, 1357) 2026 = not( 2019) 2039 = not( 2032) 2046 = and( 103, 2019) 2048 = and( 130, 2019) 2050 = and( 127, 2019) 2052 = and( 124, 2019) 2054 = and( 100, 2019) 2056 = and( 103, 2032) 2058 = and( 130, 2032) 2060 = and( 127, 2032) 2062 = and( 124, 2032) 2064 = and( 100, 2032) 2124 = not( 2117) 2137 = not( 2130) 2144 = and( 115, 2117) 2146 = and( 118, 2117) 2148 = and( 97, 2117) 2150 = and( 94, 2117) 2152 = and( 121, 2117) 2154 = and( 115, 2130) 2156 = and( 118, 2130) 2158 = and( 97, 2130) 2160 = and( 94, 2130) 2162 = and( 121, 2130) 2279 = not( 2272) 2285 = and( 208, 2266) 2287 = and( 198, 2266) 2289 = and( 207, 2266) 2291 = and( 206, 2266) 2293 = and( 205, 2266) 2296 = and( 44, 2272) 2298 = and( 41, 2272) 2300 = and( 29, 2272) 2302 = and( 26, 2272) 2304 = and( 23, 2272) 2918 = or( 2899, 2892) 2920 = or( 2899, 2919) 2922 = or( 2899, 2921) 2924 = or( 2899, 2923) 2926 = or( 2899, 2925) 2928 = or( 2914, 2927) 2930 = or( 2914, 2929) 2932 = or( 2914, 2931) 3168 = nand( 6514, 6517) 6557 = not( 6551) 3211 = nand( 6551, 6558) 3648 = and( 114, 3629) 3650 = and( 113, 3629) 3652 = and( 111, 3629) 3654 = and( 87, 3629) 3656 = and( 112, 3629) 3658 = and( 88, 3642) 3660 = and( 1455, 3642) 3662 = and( 2204, 3642) 3665 = and( 3703, 3642) 3666 = and( 70, 3642) 3775 = not( 3768) 3781 = and( 193, 3762) 3783 = and( 192, 3762) 3785 = and( 191, 3762) 3787 = and( 190, 3762) 3789 = and( 189, 3762) 3792 = and( 47, 3768) 3794 = and( 35, 3768) 3796 = and( 32, 3768) 3798 = and( 50, 3768) 3800 = and( 66, 3768) 4101 = not( 4094) 4114 = not( 4107) 4123 = and( 58, 4094) 4126 = and( 77, 4094) 4129 = and( 78, 4094) 4132 = and( 59, 4094) 4135 = and( 81, 4094) 4138 = and( 80, 4107) 4141 = and( 79, 4107) 4144 = and( 60, 4107) 4147 = and( 61, 4107) 4150 = and( 62, 4107) 4451 = not( 4444) 4464 = not( 4457) 4471 = and( 69, 4444) 4473 = and( 70, 4444) 4475 = and( 74, 4444) 4477 = and( 76, 4444) 4479 = and( 75, 4444) 4481 = and( 73, 4457) 4483 = and( 53, 4457) 4485 = and( 54, 4457) 4487 = and( 55, 4457) 4489 = and( 56, 4457) 4666 = and( 82, 4647) 4668 = and( 65, 4647) 4670 = and( 83, 4647) 4672 = and( 84, 4647) 4674 = and( 85, 4647) 4676 = and( 64, 4660) 4678 = and( 63, 4660) 4680 = and( 86, 4660) 4682 = and( 109, 4660) 4684 = and( 110, 4660) 579 = and( 577, 581) 629 = and( 616, 581) 633 = and( 618, 581) 637 = and( 620, 581) 641 = and( 622, 581) 645 = and( 624, 601) 711 = and( 692, 650) 715 = and( 694, 650) 719 = and( 696, 650) 723 = and( 698, 650) 727 = and( 700, 650) 731 = and( 702, 671) 737 = and( 704, 671) 745 = and( 706, 671) 751 = and( 708, 671) 757 = and( 710, 671) 887 = nand( 885, 886) 1019 = nand( 1017, 1018) 5245 = not( 5239) 1383 = or( 1365, 1366) 1387 = or( 1367, 1368) 1391 = or( 1369, 1370) 1395 = or( 1371, 1372) 1399 = or( 1375, 1376) 1406 = or( 1377, 1378) 1412 = or( 1379, 1380) 1418 = or( 1381, 1382) 2305 = or( 2287, 2288) 2308 = or( 2289, 2290) 2312 = or( 2291, 2292) 2316 = or( 2293, 2294) 2933 = and( 2920, 2886) 2938 = and( 2922, 2886) 2942 = and( 2924, 2886) 2946 = and( 2926, 2886) 2950 = and( 2928, 2905) 3170 = nand( 3168, 3169) 3210 = nand( 6554, 6557) 3667 = or( 3650, 3651) 3670 = or( 3652, 3653) 3673 = or( 3654, 3655) 3676 = or( 3656, 3657) 3679 = or( 3658, 3659) 3682 = or( 3665, 3635) 3686 = or( 3666, 3635) 3801 = or( 3781, 3782) 3804 = or( 3783, 3784) 3807 = or( 3785, 3786) 3810 = or( 3787, 3788) 3813 = or( 3789, 3790) 4525 = and( 2918, 2886) 4686 = or( 4668, 4669) 4689 = or( 4670, 4671) 4692 = or( 4672, 4673) 4695 = or( 4674, 4675) 4698 = or( 4676, 4677) 4701 = or( 4678, 4679) 4704 = or( 4680, 4681) 4707 = or( 4682, 4683) 4710 = or( 4684, 4685) 4976 = not( 4970) 5271 = and( 2932, 2905) 5274 = and( 2930, 2905) 5305 = and( 628, 601) 5308 = and( 626, 601) 5318 = or( 1373, 1374) 6690 = or( 3648, 3649) 6711 = or( 3662, 3663) 6714 = or( 3660, 3661) 7252 = or( 2285, 2286) 7296 = or( 1363, 1364) 7466 = or( 4666, 4667) 907 = and( 765, 784) 913 = and( 765, 784) 915 = and( 765, 784) 916 = and( 765, 784) 1116 = and( 1007, 1014) 2045 = and( 204, 2026) 2047 = and( 203, 2026) 2049 = and( 202, 2026) 2051 = and( 201, 2026) 2053 = and( 200, 2026) 2055 = and( 235, 2039) 2057 = and( 234, 2039) 2059 = and( 233, 2039) 2061 = and( 232, 2039) 2063 = and( 231, 2039) 2143 = and( 197, 2124) 2145 = and( 187, 2124) 2147 = and( 196, 2124) 2149 = and( 195, 2124) 2151 = and( 194, 2124) 2153 = and( 227, 2137) 2155 = and( 217, 2137) 2157 = and( 226, 2137) 2159 = and( 225, 2137) 2161 = and( 224, 2137) 2295 = and( 239, 2279) 2297 = and( 229, 2279) 2299 = and( 238, 2279) 2301 = and( 237, 2279) 2303 = and( 236, 2279) 3212 = nand( 3210, 3211) 3791 = and( 223, 3775) 3793 = and( 222, 3775) 3795 = and( 221, 3775) 3797 = and( 220, 3775) 3799 = and( 219, 3775) 4122 = and( 4121, 4101) 4125 = and( 4396, 4101) 4128 = and( 4402, 4101) 4131 = and( 4407, 4101) 4134 = and( 4412, 4101) 4137 = and( 4417, 4114) 4140 = and( 4422, 4114) 4143 = and( 4429, 4114) 4146 = and( 4434, 4114) 4149 = and( 4439, 4114) 4470 = and( 3700, 4451) 4472 = and( 3703, 4451) 4474 = and( 3707, 4451) 4476 = and( 3713, 4451) 4478 = and( 3719, 4451) 4480 = and( 3725, 4464) 4482 = and( 3731, 4464) 4484 = and( 3739, 4464) 4486 = and( 3745, 4464) 4488 = and( 3751, 4464) 4962 = buff( 765) 5003 = buff( 765) 5234 = buff( 1007) 5242 = buff( 1007) 5250 = not( 4525) 5284 = not( 579) 802 = and( 1488, 2950) 821 = and( 1482, 2946) 845 = and( 1477, 2942) 868 = and( 1471, 2938) 877 = and( 1464, 2933) 902 = and( 887, 765) 908 = or( 777, 907) 914 = and( 887, 765) 917 = or( 777, 916) 953 = and( 887, 765) 1023 = not( 1019) 1035 = and( 1488, 2950) 1050 = and( 1482, 2946) 1068 = and( 1477, 2942) 1086 = and( 1471, 2938) 1102 = and( 1464, 2933) 1108 = and( 1019, 1007) 1117 = or( 1115, 1116) 5322 = not( 5318) 1553 = and( 1192, 757) 1567 = and( 1186, 751) 1584 = and( 2249, 745) 1590 = and( 2241, 737) 1606 = and( 1178, 731) 1624 = and( 2232, 1418) 1647 = and( 2226, 1412) 1669 = and( 2220, 1406) 1677 = and( 2213, 1399) 1802 = and( 1192, 757) 1816 = and( 1186, 751) 1834 = and( 2249, 745) 1841 = and( 737, 2241) 1866 = and( 1178, 731) 1880 = and( 2232, 1418) 1897 = and( 2226, 1412) 1914 = and( 2220, 1406) 1929 = and( 2213, 1399) 2065 = or( 2045, 2046) 2069 = or( 2047, 2048) 2073 = or( 2049, 2050) 2077 = or( 2051, 2052) 2081 = or( 2053, 2054) 2085 = or( 2055, 2056) 2091 = or( 2057, 2058) 2099 = or( 2059, 2060) 2105 = or( 2061, 2062) 2111 = or( 2063, 2064) 2163 = or( 2145, 2146) 2167 = or( 2147, 2148) 2171 = or( 2149, 2150) 2175 = or( 2151, 2152) 2179 = or( 2155, 2156) 2186 = or( 2157, 2158) 2192 = or( 2159, 2160) 2198 = or( 2161, 2162) 2320 = or( 2297, 2298) 2323 = or( 2299, 2300) 2329 = or( 2301, 2302) 2335 = or( 2303, 2304) 2962 = and( 4710, 727) 2970 = and( 4707, 723) 2977 = and( 4704, 719) 2979 = and( 4701, 715) 2989 = and( 4698, 711) 2998 = and( 4695, 1395) 3006 = and( 4692, 1391) 3013 = and( 4689, 1387) 3015 = and( 4686, 1383) 3183 = and( 3679, 645) 3192 = and( 3676, 641) 3200 = and( 3673, 637) 3207 = and( 3670, 633) 3209 = and( 3667, 629) 3216 = and( 3212, 3170) 3222 = and( 3170, 3173) 6694 = not( 6690) 3695 = and( 1535, 2305) 3816 = or( 3791, 3792) 3821 = or( 3793, 3794) 3828 = or( 3795, 3796) 3833 = or( 3797, 3798) 3838 = or( 3799, 3800) 4151 = or( 4125, 4126) 4154 = or( 4128, 4129) 4157 = or( 4131, 4132) 4160 = or( 4134, 4135) 4163 = or( 4137, 4138) 4166 = or( 4140, 4141) 4169 = or( 4143, 4144) 4172 = or( 4146, 4147) 4175 = or( 4149, 4150) 7256 = not( 7252) 7300 = not( 7296) 4490 = or( 4474, 4475) 4493 = or( 4476, 4477) 4496 = or( 4478, 4479) 4499 = or( 4480, 4481) 4502 = or( 4482, 4483) 4505 = or( 4484, 4485) 4508 = or( 4486, 4487) 4511 = or( 4488, 4489) 7470 = not( 7466) 4884 = buff( 2950) 4892 = buff( 2946) 4900 = buff( 2942) 4908 = buff( 2938) 4924 = buff( 2933) 4952 = buff( 887) 4983 = nor( 777, 915) 4993 = buff( 887) 5011 = nor( 1464, 2933) 5194 = buff( 2950) 5202 = buff( 2946) 5210 = buff( 2942) 5218 = buff( 2938) 5226 = buff( 2933) 5247 = buff( 2933) 5255 = buff( 2942) 5258 = buff( 2938) 5263 = buff( 2950) 5266 = buff( 2946) 5277 = not( 5271) 5278 = not( 5274) 5281 = buff( 629) 5289 = buff( 637) 5292 = buff( 633) 5297 = buff( 645) 5300 = buff( 641) 5311 = not( 5305) 5312 = not( 5308) 5315 = buff( 1399) 5323 = buff( 1412) 5326 = buff( 1406) 5331 = buff( 731) 5334 = buff( 1418) 5339 = buff( 745) 5342 = buff( 737) 5349 = buff( 757) 5352 = buff( 751) 5396 = buff( 757) 5404 = buff( 751) 5412 = buff( 745) 5420 = buff( 731) 5428 = buff( 1418) 5436 = buff( 1412) 5444 = buff( 1406) 5452 = buff( 737) 5460 = buff( 1399) 5465 = nor( 2241, 737) 5581 = nor( 2213, 1399) 5748 = buff( 757) 5756 = buff( 751) 5764 = buff( 745) 5772 = buff( 737) 5780 = buff( 731) 5788 = buff( 1418) 5796 = buff( 1412) 5804 = buff( 1406) 5812 = buff( 1399) 5849 = nor( 737, 2241) 5929 = buff( 3682) 6049 = buff( 3682) 6367 = buff( 4710) 6370 = buff( 727) 6375 = buff( 4707) 6378 = buff( 723) 6383 = buff( 4704) 6386 = buff( 719) 6391 = buff( 4698) 6394 = buff( 711) 6399 = buff( 4695) 6402 = buff( 1395) 6407 = buff( 4692) 6410 = buff( 1391) 6415 = buff( 4689) 6418 = buff( 1387) 6423 = buff( 4701) 6426 = buff( 715) 6431 = buff( 4686) 6434 = buff( 1383) 6442 = buff( 3813) 6450 = buff( 3810) 6458 = buff( 3807) 6466 = buff( 3801) 6498 = buff( 3804) 6519 = buff( 3679) 6522 = buff( 645) 6527 = buff( 3676) 6530 = buff( 641) 6535 = buff( 3673) 6538 = buff( 637) 6543 = buff( 3670) 6546 = buff( 633) 6559 = buff( 3667) 6562 = buff( 629) 6687 = buff( 3667) 6695 = buff( 3673) 6698 = buff( 3670) 6703 = buff( 3679) 6706 = buff( 3676) 6717 = not( 6711) 6718 = not( 6714) 6724 = or( 2153, 2154) 6768 = or( 2295, 2296) 7208 = or( 2143, 2144) 7221 = buff( 3801) 7229 = buff( 3807) 7232 = buff( 3804) 7239 = buff( 3813) 7242 = buff( 3810) 7249 = buff( 2305) 7257 = buff( 2312) 7260 = buff( 2308) 7268 = buff( 2316) 7293 = buff( 1383) 7301 = buff( 1391) 7304 = buff( 1387) 7309 = buff( 711) 7312 = buff( 1395) 7317 = buff( 719) 7320 = buff( 715) 7327 = buff( 727) 7330 = buff( 723) 7396 = buff( 2316) 7404 = buff( 2312) 7412 = buff( 2308) 7425 = buff( 3686) 7463 = buff( 4686) 7471 = buff( 4692) 7474 = buff( 4689) 7479 = buff( 4698) 7482 = buff( 4695) 7487 = buff( 4704) 7490 = buff( 4701) 7497 = buff( 4710) 7500 = buff( 4707) 7507 = or( 4472, 4473) 7510 = or( 4470, 4471) 7554 = or( 4122, 4123) 1152 = nand( 5234, 5237) 5238 = not( 5234) 1156 = nand( 5242, 5245) 5246 = not( 5242) 5254 = not( 5250) 5288 = not( 5284) 3223 = or( 3221, 3222) 4942 = or( 777, 913, 914) 4966 = not( 4962) 5007 = not( 5003) 5279 = nand( 5274, 5277) 5280 = nand( 5271, 5278) 5313 = nand( 5308, 5311) 5314 = nand( 5305, 5312) 6719 = nand( 6714, 6717) 6720 = nand( 6711, 6718) 790 = nand( 4884, 4887) 4888 = not( 4884) 803 = nand( 4892, 4895) 4896 = not( 4892) 825 = nand( 4900, 4903) 4904 = not( 4900) 851 = nand( 4908, 4911) 4912 = not( 4908) 893 = nand( 4924, 4927) 4928 = not( 4924) 906 = not( 902) 912 = not( 908) 1024 = nand( 5194, 5197) 5198 = not( 5194) 1036 = nand( 5202, 5205) 5206 = not( 5202) 1053 = nand( 5210, 5213) 5214 = not( 5210) 1072 = nand( 5218, 5221) 5222 = not( 5218) 1091 = nand( 5226, 5229) 5230 = not( 5226) 1112 = not( 1108) 1121 = not( 1117) 1153 = nand( 5231, 5238) 1157 = nand( 5239, 5246) 5253 = not( 5247) 1216 = nand( 5247, 5254) 5261 = not( 5255) 5262 = not( 5258) 5269 = not( 5263) 5270 = not( 5266) 5287 = not( 5281) 1239 = nand( 5281, 5288) 5295 = not( 5289) 5296 = not( 5292) 5303 = not( 5297) 5304 = not( 5300) 5321 = not( 5315) 1262 = nand( 5315, 5322) 5329 = not( 5323) 5330 = not( 5326) 5337 = not( 5331) 5338 = not( 5334) 1544 = nand( 5396, 5399) 5400 = not( 5396) 1554 = nand( 5404, 5407) 5408 = not( 5404) 1571 = nand( 5412, 5415) 5416 = not( 5412) 1596 = nand( 5420, 5423) 5424 = not( 5420) 1607 = nand( 5428, 5431) 5432 = not( 5428) 1628 = nand( 5436, 5439) 5440 = not( 5436) 1653 = nand( 5444, 5447) 5448 = not( 5444) 1685 = nand( 5452, 5455) 5456 = not( 5452) 1693 = nand( 5460, 5463) 5464 = not( 5460) 1793 = nand( 5748, 5751) 5752 = not( 5748) 1803 = nand( 5756, 5759) 5760 = not( 5756) 1820 = nand( 5764, 5767) 5768 = not( 5764) 1848 = nand( 5772, 5775) 5776 = not( 5772) 1857 = nand( 5780, 5783) 5784 = not( 5780) 1867 = nand( 5788, 5791) 5792 = not( 5788) 1883 = nand( 5796, 5799) 5800 = not( 5796) 1901 = nand( 5804, 5807) 5808 = not( 5804) 1919 = nand( 5812, 5815) 5816 = not( 5812) 5855 = not( 5849) 2351 = and( 3751, 2111) 2366 = and( 3745, 2105) 2384 = and( 3739, 2099) 2391 = and( 2091, 3731) 2417 = and( 3725, 2085) 2431 = and( 3719, 2335) 2448 = and( 3713, 2329) 2465 = and( 3707, 2323) 5935 = not( 5929) 2597 = and( 3751, 2111) 2612 = and( 3745, 2105) 2629 = and( 3739, 2099) 2635 = and( 3731, 2091) 2652 = and( 3725, 2085) 2670 = and( 3719, 2335) 2693 = and( 3713, 2329) 2715 = and( 3707, 2323) 6055 = not( 6049) 6373 = not( 6367) 6374 = not( 6370) 6381 = not( 6375) 6382 = not( 6378) 6389 = not( 6383) 6390 = not( 6386) 6397 = not( 6391) 6398 = not( 6394) 6405 = not( 6399) 6406 = not( 6402) 6413 = not( 6407) 6414 = not( 6410) 6421 = not( 6415) 6422 = not( 6418) 6429 = not( 6423) 6430 = not( 6426) 6437 = not( 6431) 6438 = not( 6434) 6446 = not( 6442) 3059 = and( 4175, 3813) 6454 = not( 6450) 3068 = and( 4172, 3810) 6462 = not( 6458) 3076 = and( 4169, 3807) 3079 = and( 4166, 3804) 6470 = not( 6466) 3090 = and( 4163, 3801) 3099 = and( 4160, 2175) 3107 = and( 4157, 2171) 3114 = and( 4154, 2167) 3116 = and( 4151, 2163) 6502 = not( 6498) 6525 = not( 6519) 6526 = not( 6522) 6533 = not( 6527) 6534 = not( 6530) 6541 = not( 6535) 6542 = not( 6538) 6549 = not( 6543) 6550 = not( 6546) 6565 = not( 6559) 6566 = not( 6562) 3220 = not( 3216) 3292 = and( 4439, 3838) 3308 = and( 4434, 3833) 3327 = and( 4429, 3828) 3335 = and( 3821, 4422) 3362 = and( 4417, 3816) 3376 = and( 4412, 2198) 3393 = and( 4407, 2192) 3410 = and( 4402, 2186) 3425 = and( 4396, 2179) 6693 = not( 6687) 3503 = nand( 6687, 6694) 6701 = not( 6695) 6702 = not( 6698) 6709 = not( 6703) 6710 = not( 6706) 6728 = not( 6724) 6772 = not( 6768) 3853 = and( 4439, 3838) 3868 = and( 4434, 3833) 3885 = and( 4429, 3828) 3891 = and( 4422, 3821) 3908 = and( 4417, 3816) 3926 = and( 4412, 2198) 3949 = and( 4407, 2192) 3971 = and( 4402, 2186) 3979 = and( 4396, 2179) 7212 = not( 7208) 7227 = not( 7221) 7255 = not( 7249) 4202 = nand( 7249, 7256) 7263 = not( 7257) 7264 = not( 7260) 7272 = not( 7268) 7299 = not( 7293) 4225 = nand( 7293, 7300) 7307 = not( 7301) 7308 = not( 7304) 7315 = not( 7309) 7316 = not( 7312) 4297 = and( 4511, 2081) 4305 = and( 4508, 2077) 4312 = and( 4505, 2073) 4314 = and( 4502, 2069) 4324 = and( 4499, 2065) 7400 = not( 7396) 4333 = and( 4496, 2316) 7408 = not( 7404) 4341 = and( 4493, 2312) 7416 = not( 7412) 4348 = and( 4490, 2308) 4349 = and( 3686, 3695) 7431 = not( 7425) 4389 = and( 2320, 1535) 7469 = not( 7463) 4530 = nand( 7463, 7470) 7477 = not( 7471) 7478 = not( 7474) 7485 = not( 7479) 7486 = not( 7482) 7513 = not( 7507) 7514 = not( 7510) 7558 = not( 7554) 4932 = or( 917, 953) 4956 = not( 4952) 4973 = not( 917) 4987 = not( 4983) 4997 = not( 4993) 5017 = not( 5011) 5099 = buff( 877) 5345 = not( 5339) 5346 = not( 5342) 5355 = not( 5349) 5356 = not( 5352) 5372 = nand( 5279, 5280) 5380 = nand( 5313, 5314) 5471 = not( 5465) 5523 = buff( 1590) 5587 = not( 5581) 5669 = buff( 1677) 5857 = buff( 1841) 5868 = buff( 2111) 5876 = buff( 2105) 5884 = buff( 2099) 5892 = buff( 2091) 5900 = buff( 2085) 5908 = buff( 2335) 5916 = buff( 2329) 5924 = buff( 2323) 5969 = nor( 2091, 3731) 5988 = buff( 2111) 5996 = buff( 2105) 6004 = buff( 2099) 6012 = buff( 2085) 6020 = buff( 2335) 6028 = buff( 2329) 6036 = buff( 2323) 6044 = buff( 2091) 6057 = nor( 3731, 2091) 6439 = buff( 4175) 6447 = buff( 4172) 6455 = buff( 4169) 6463 = buff( 4163) 6471 = buff( 4160) 6474 = buff( 2175) 6479 = buff( 4157) 6482 = buff( 2171) 6487 = buff( 4154) 6490 = buff( 2167) 6495 = buff( 4166) 6503 = buff( 4151) 6506 = buff( 2163) 6570 = buff( 3838) 6578 = buff( 3833) 6586 = buff( 3828) 6594 = buff( 3821) 6602 = buff( 3816) 6610 = buff( 2198) 6618 = buff( 2192) 6626 = buff( 2186) 6634 = buff( 2179) 6671 = nor( 3821, 4422) 6721 = buff( 2179) 6729 = buff( 2192) 6732 = buff( 2186) 6737 = buff( 3816) 6740 = buff( 2198) 6745 = buff( 3828) 6748 = buff( 3821) 6755 = buff( 3838) 6758 = buff( 3833) 6765 = buff( 2320) 6773 = buff( 2329) 6776 = buff( 2323) 6781 = buff( 2085) 6784 = buff( 2335) 6789 = buff( 2099) 6792 = buff( 2091) 6799 = buff( 2111) 6802 = buff( 2105) 6832 = nand( 6719, 6720) 6856 = buff( 3838) 6864 = buff( 3833) 6872 = buff( 3828) 6880 = buff( 3816) 6888 = buff( 2198) 6896 = buff( 2192) 6904 = buff( 2186) 6912 = buff( 3821) 6920 = buff( 2179) 6925 = nor( 4422, 3821) 7041 = nor( 4396, 2179) 7205 = buff( 2163) 7213 = buff( 2171) 7216 = buff( 2167) 7224 = buff( 2175) 7235 = not( 7229) 7236 = not( 7232) 7245 = not( 7239) 7246 = not( 7242) 7265 = buff( 2065) 7273 = buff( 2073) 7276 = buff( 2069) 7283 = buff( 2081) 7286 = buff( 2077) 7323 = not( 7317) 7324 = not( 7320) 7333 = not( 7327) 7334 = not( 7330) 7361 = buff( 4511) 7364 = buff( 2081) 7369 = buff( 4508) 7372 = buff( 2077) 7377 = buff( 4505) 7380 = buff( 2073) 7385 = buff( 4499) 7388 = buff( 2065) 7393 = buff( 4496) 7401 = buff( 4493) 7409 = buff( 4490) 7417 = buff( 4502) 7420 = buff( 2069) 7428 = buff( 3695) 7493 = not( 7487) 7494 = not( 7490) 7503 = not( 7497) 7504 = not( 7500) 7515 = buff( 4493) 7518 = buff( 4490) 7523 = buff( 4499) 7526 = buff( 4496) 7531 = buff( 4505) 7534 = buff( 4502) 7541 = buff( 4511) 7544 = buff( 4508) 7551 = buff( 4151) 7559 = buff( 4157) 7562 = buff( 4154) 7567 = buff( 4163) 7570 = buff( 4160) 7575 = buff( 4169) 7578 = buff( 4166) 7585 = buff( 4175) 7588 = buff( 4172) 1176 = nand( 1121, 1112) 957 = nand( 912, 906) 791 = nand( 4881, 4888) 804 = nand( 4889, 4896) 826 = nand( 4897, 4904) 852 = nand( 4905, 4912) 894 = nand( 4921, 4928) 1025 = nand( 5191, 5198) 1037 = nand( 5199, 5206) 1054 = nand( 5207, 5214) 1073 = nand( 5215, 5222) 1092 = nand( 5223, 5230) 1154 = nand( 1152, 1153) 1158 = nand( 1156, 1157) 1215 = nand( 5250, 5253) 1224 = nand( 5258, 5261) 1225 = nand( 5255, 5262) 1233 = nand( 5266, 5269) 1234 = nand( 5263, 5270) 1238 = nand( 5284, 5287) 1247 = nand( 5292, 5295) 1248 = nand( 5289, 5296) 1256 = nand( 5300, 5303) 1257 = nand( 5297, 5304) 1261 = nand( 5318, 5321) 1270 = nand( 5326, 5329) 1271 = nand( 5323, 5330) 1279 = nand( 5334, 5337) 1280 = nand( 5331, 5338) 1545 = nand( 5393, 5400) 1555 = nand( 5401, 5408) 1572 = nand( 5409, 5416) 1597 = nand( 5417, 5424) 1608 = nand( 5425, 5432) 1629 = nand( 5433, 5440) 1654 = nand( 5441, 5448) 1686 = nand( 5449, 5456) 1694 = nand( 5457, 5464) 1794 = nand( 5745, 5752) 1804 = nand( 5753, 5760) 1821 = nand( 5761, 5768) 1849 = nand( 5769, 5776) 1858 = nand( 5777, 5784) 1868 = nand( 5785, 5792) 1884 = nand( 5793, 5800) 1902 = nand( 5801, 5808) 1920 = nand( 5809, 5816) 2954 = nand( 6370, 6373) 2955 = nand( 6367, 6374) 2963 = nand( 6378, 6381) 2964 = nand( 6375, 6382) 2971 = nand( 6386, 6389) 2972 = nand( 6383, 6390) 2980 = nand( 6394, 6397) 2981 = nand( 6391, 6398) 2990 = nand( 6402, 6405) 2991 = nand( 6399, 6406) 2999 = nand( 6410, 6413) 3000 = nand( 6407, 6414) 3007 = nand( 6418, 6421) 3008 = nand( 6415, 6422) 3016 = nand( 6426, 6429) 3017 = nand( 6423, 6430) 3019 = nand( 6434, 6437) 3020 = nand( 6431, 6438) 3174 = nand( 6522, 6525) 3175 = nand( 6519, 6526) 3184 = nand( 6530, 6533) 3185 = nand( 6527, 6534) 3193 = nand( 6538, 6541) 3194 = nand( 6535, 6542) 3201 = nand( 6546, 6549) 3202 = nand( 6543, 6550) 3213 = nand( 6562, 6565) 3214 = nand( 6559, 6566) 3227 = not( 3223) 3502 = nand( 6690, 6693) 3511 = nand( 6698, 6701) 3512 = nand( 6695, 6702) 3520 = nand( 6706, 6709) 3521 = nand( 6703, 6710) 4201 = nand( 7252, 7255) 4210 = nand( 7260, 7263) 4211 = nand( 7257, 7264) 4224 = nand( 7296, 7299) 4233 = nand( 7304, 7307) 4234 = nand( 7301, 7308) 4242 = nand( 7312, 7315) 4243 = nand( 7309, 7316) 4529 = nand( 7466, 7469) 4538 = nand( 7474, 7477) 4539 = nand( 7471, 7478) 4547 = nand( 7482, 7485) 4548 = nand( 7479, 7486) 4552 = nand( 7510, 7513) 4553 = nand( 7507, 7514) 4946 = not( 4942) 5347 = nand( 5342, 5345) 5348 = nand( 5339, 5346) 5357 = nand( 5352, 5355) 5358 = nand( 5349, 5356) 7237 = nand( 7232, 7235) 7238 = nand( 7229, 7236) 7247 = nand( 7242, 7245) 7248 = nand( 7239, 7246) 7325 = nand( 7320, 7323) 7326 = nand( 7317, 7324) 7335 = nand( 7330, 7333) 7336 = nand( 7327, 7334) 7495 = nand( 7490, 7493) 7496 = nand( 7487, 7494) 7505 = nand( 7500, 7503) 7506 = nand( 7497, 7504) 3244 = nand( 3227, 3220) 792 = nand( 790, 791) 805 = nand( 803, 804) 827 = nand( 825, 826) 853 = nand( 851, 852) 895 = nand( 893, 894) 1026 = nand( 1024, 1025) 1038 = nand( 1036, 1037) 1055 = nand( 1053, 1054) 1074 = nand( 1072, 1073) 1093 = nand( 1091, 1092) 1155 = not( 1154) 1217 = nand( 1215, 1216) 1226 = nand( 1224, 1225) 1235 = nand( 1233, 1234) 1240 = nand( 1238, 1239) 1249 = nand( 1247, 1248) 1258 = nand( 1256, 1257) 1263 = nand( 1261, 1262) 1272 = nand( 1270, 1271) 1281 = nand( 1279, 1280) 5376 = not( 5372) 5384 = not( 5380) 1546 = nand( 1544, 1545) 1556 = nand( 1554, 1555) 1573 = nand( 1571, 1572) 1598 = nand( 1596, 1597) 1609 = nand( 1607, 1608) 1630 = nand( 1628, 1629) 1655 = nand( 1653, 1654) 1687 = nand( 1685, 1686) 1695 = nand( 1693, 1694) 1795 = nand( 1793, 1794) 1805 = nand( 1803, 1804) 1822 = nand( 1820, 1821) 1850 = nand( 1848, 1849) 1859 = nand( 1857, 1858) 1869 = nand( 1867, 1868) 1885 = nand( 1883, 1884) 1903 = nand( 1901, 1902) 1921 = nand( 1919, 1920) 5863 = not( 5857) 2341 = nand( 5868, 5871) 5872 = not( 5868) 2352 = nand( 5876, 5879) 5880 = not( 5876) 2370 = nand( 5884, 5887) 5888 = not( 5884) 2398 = nand( 5892, 5895) 5896 = not( 5892) 2407 = nand( 5900, 5903) 5904 = not( 5900) 2418 = nand( 5908, 5911) 5912 = not( 5908) 2434 = nand( 5916, 5919) 5920 = not( 5916) 2452 = nand( 5924, 5927) 5928 = not( 5924) 2481 = and( 3682, 4389) 5975 = not( 5969) 2587 = nand( 5988, 5991) 5992 = not( 5988) 2598 = nand( 5996, 5999) 6000 = not( 5996) 2616 = nand( 6004, 6007) 6008 = not( 6004) 2641 = nand( 6012, 6015) 6016 = not( 6012) 2653 = nand( 6020, 6023) 6024 = not( 6020) 2674 = nand( 6028, 6031) 6032 = not( 6028) 2699 = nand( 6036, 6039) 6040 = not( 6036) 2724 = and( 3682, 4389) 2732 = nand( 6044, 6047) 6048 = not( 6044) 2956 = nand( 2954, 2955) 2965 = nand( 2963, 2964) 2973 = nand( 2971, 2972) 2982 = nand( 2980, 2981) 2992 = nand( 2990, 2991) 3001 = nand( 2999, 3000) 3009 = nand( 3007, 3008) 3018 = nand( 3016, 3017) 3021 = nand( 3019, 3020) 6445 = not( 6439) 3051 = nand( 6439, 6446) 6453 = not( 6447) 3061 = nand( 6447, 6454) 6461 = not( 6455) 3070 = nand( 6455, 6462) 6469 = not( 6463) 3081 = nand( 6463, 6470) 6477 = not( 6471) 6478 = not( 6474) 6485 = not( 6479) 6486 = not( 6482) 6493 = not( 6487) 6494 = not( 6490) 6501 = not( 6495) 3118 = nand( 6495, 6502) 6509 = not( 6503) 6510 = not( 6506) 3176 = nand( 3174, 3175) 3186 = nand( 3184, 3185) 3195 = nand( 3193, 3194) 3203 = nand( 3201, 3202) 3215 = nand( 3213, 3214) 3281 = nand( 6570, 6573) 6574 = not( 6570) 3293 = nand( 6578, 6581) 6582 = not( 6578) 3312 = nand( 6586, 6589) 6590 = not( 6586) 3342 = nand( 6594, 6597) 6598 = not( 6594) 3351 = nand( 6602, 6605) 6606 = not( 6602) 3363 = nand( 6610, 6613) 6614 = not( 6610) 3379 = nand( 6618, 6621) 6622 = not( 6618) 3397 = nand( 6626, 6629) 6630 = not( 6626) 3415 = nand( 6634, 6637) 6638 = not( 6634) 6677 = not( 6671) 3504 = nand( 3502, 3503) 3513 = nand( 3511, 3512) 3522 = nand( 3520, 3521) 6727 = not( 6721) 3526 = nand( 6721, 6728) 6735 = not( 6729) 6736 = not( 6732) 6743 = not( 6737) 6744 = not( 6740) 6771 = not( 6765) 3549 = nand( 6765, 6772) 6779 = not( 6773) 6780 = not( 6776) 6787 = not( 6781) 6788 = not( 6784) 6836 = not( 6832) 3843 = nand( 6856, 6859) 6860 = not( 6856) 3854 = nand( 6864, 6867) 6868 = not( 6864) 3872 = nand( 6872, 6875) 6876 = not( 6872) 3897 = nand( 6880, 6883) 6884 = not( 6880) 3909 = nand( 6888, 6891) 6892 = not( 6888) 3930 = nand( 6896, 6899) 6900 = not( 6896) 3955 = nand( 6904, 6907) 6908 = not( 6904) 3987 = nand( 6912, 6915) 6916 = not( 6912) 3995 = nand( 6920, 6923) 6924 = not( 6920) 7211 = not( 7205) 4179 = nand( 7205, 7212) 7219 = not( 7213) 7220 = not( 7216) 4196 = nand( 7224, 7227) 7228 = not( 7224) 4203 = nand( 4201, 4202) 4212 = nand( 4210, 4211) 7271 = not( 7265) 4220 = nand( 7265, 7272) 4226 = nand( 4224, 4225) 4235 = nand( 4233, 4234) 4244 = nand( 4242, 4243) 7367 = not( 7361) 7368 = not( 7364) 7375 = not( 7369) 7376 = not( 7372) 7383 = not( 7377) 7384 = not( 7380) 7391 = not( 7385) 7392 = not( 7388) 7399 = not( 7393) 4326 = nand( 7393, 7400) 7407 = not( 7401) 4335 = nand( 7401, 7408) 7415 = not( 7409) 4343 = nand( 7409, 7416) 7423 = not( 7417) 7424 = not( 7420) 4353 = nand( 7428, 7431) 7432 = not( 7428) 4531 = nand( 4529, 4530) 4540 = nand( 4538, 4539) 4549 = nand( 4547, 4548) 4554 = nand( 4552, 4553) 7521 = not( 7515) 7522 = not( 7518) 7529 = not( 7523) 7530 = not( 7526) 7557 = not( 7551) 4576 = nand( 7551, 7558) 7565 = not( 7559) 7566 = not( 7562) 7573 = not( 7567) 7574 = not( 7570) 4936 = not( 4932) 4937 = nand( 4932, 4935) 4977 = not( 4973) 4978 = nand( 4973, 4976) 5105 = not( 5099) 5359 = nand( 5357, 5358) 5362 = nand( 5347, 5348) 5529 = not( 5523) 5675 = not( 5669) 5932 = buff( 4389) 5977 = buff( 2391) 6052 = buff( 4389) 6063 = not( 6057) 6115 = buff( 2635) 6173 = nor( 3682, 4389) 6679 = buff( 3335) 6751 = not( 6745) 6752 = not( 6748) 6761 = not( 6755) 6762 = not( 6758) 6795 = not( 6789) 6796 = not( 6792) 6805 = not( 6799) 6806 = not( 6802) 6931 = not( 6925) 6983 = buff( 3891) 7047 = not( 7041) 7129 = buff( 3979) 7279 = not( 7273) 7280 = not( 7276) 7289 = not( 7283) 7290 = not( 7286) 7337 = nand( 7247, 7248) 7340 = nand( 7237, 7238) 7353 = nand( 7335, 7336) 7356 = nand( 7325, 7326) 7537 = not( 7531) 7538 = not( 7534) 7547 = not( 7541) 7548 = not( 7544) 7581 = not( 7575) 7582 = not( 7578) 7591 = not( 7585) 7592 = not( 7588) 7595 = nand( 7505, 7506) 7598 = nand( 7495, 7496) 2342 = nand( 5865, 5872) 2353 = nand( 5873, 5880) 2371 = nand( 5881, 5888) 2399 = nand( 5889, 5896) 2408 = nand( 5897, 5904) 2419 = nand( 5905, 5912) 2435 = nand( 5913, 5920) 2453 = nand( 5921, 5928) 2588 = nand( 5985, 5992) 2599 = nand( 5993, 6000) 2617 = nand( 6001, 6008) 2642 = nand( 6009, 6016) 2654 = nand( 6017, 6024) 2675 = nand( 6025, 6032) 2700 = nand( 6033, 6040) 2733 = nand( 6041, 6048) 3050 = nand( 6442, 6445) 3060 = nand( 6450, 6453) 3069 = nand( 6458, 6461) 3080 = nand( 6466, 6469) 3091 = nand( 6474, 6477) 3092 = nand( 6471, 6478) 3100 = nand( 6482, 6485) 3101 = nand( 6479, 6486) 3108 = nand( 6490, 6493) 3109 = nand( 6487, 6494) 3117 = nand( 6498, 6501) 3120 = nand( 6506, 6509) 3121 = nand( 6503, 6510) 3282 = nand( 6567, 6574) 3294 = nand( 6575, 6582) 3313 = nand( 6583, 6590) 3343 = nand( 6591, 6598) 3352 = nand( 6599, 6606) 3364 = nand( 6607, 6614) 3380 = nand( 6615, 6622) 3398 = nand( 6623, 6630) 3416 = nand( 6631, 6638) 3525 = nand( 6724, 6727) 3534 = nand( 6732, 6735) 3535 = nand( 6729, 6736) 3543 = nand( 6740, 6743) 3544 = nand( 6737, 6744) 3548 = nand( 6768, 6771) 3557 = nand( 6776, 6779) 3558 = nand( 6773, 6780) 3566 = nand( 6784, 6787) 3567 = nand( 6781, 6788) 3844 = nand( 6853, 6860) 3855 = nand( 6861, 6868) 3873 = nand( 6869, 6876) 3898 = nand( 6877, 6884) 3910 = nand( 6885, 6892) 3931 = nand( 6893, 6900) 3956 = nand( 6901, 6908) 3988 = nand( 6909, 6916) 3996 = nand( 6917, 6924) 4178 = nand( 7208, 7211) 4187 = nand( 7216, 7219) 4188 = nand( 7213, 7220) 4197 = nand( 7221, 7228) 4219 = nand( 7268, 7271) 4289 = nand( 7364, 7367) 4290 = nand( 7361, 7368) 4298 = nand( 7372, 7375) 4299 = nand( 7369, 7376) 4306 = nand( 7380, 7383) 4307 = nand( 7377, 7384) 4315 = nand( 7388, 7391) 4316 = nand( 7385, 7392) 4325 = nand( 7396, 7399) 4334 = nand( 7404, 7407) 4342 = nand( 7412, 7415) 4350 = nand( 7420, 7423) 4351 = nand( 7417, 7424) 4354 = nand( 7425, 7432) 4561 = nand( 7518, 7521) 4562 = nand( 7515, 7522) 4570 = nand( 7526, 7529) 4571 = nand( 7523, 7530) 4575 = nand( 7554, 7557) 4584 = nand( 7562, 7565) 4585 = nand( 7559, 7566) 4593 = nand( 7570, 7573) 4594 = nand( 7567, 7574) 4938 = nand( 4929, 4936) 4979 = nand( 4970, 4977) 6753 = nand( 6748, 6751) 6754 = nand( 6745, 6752) 6763 = nand( 6758, 6761) 6764 = nand( 6755, 6762) 6797 = nand( 6792, 6795) 6798 = nand( 6789, 6796) 6807 = nand( 6802, 6805) 6808 = nand( 6799, 6806) 7281 = nand( 7276, 7279) 7282 = nand( 7273, 7280) 7291 = nand( 7286, 7289) 7292 = nand( 7283, 7290) 7539 = nand( 7534, 7537) 7540 = nand( 7531, 7538) 7549 = nand( 7544, 7547) 7550 = nand( 7541, 7548) 7583 = nand( 7578, 7581) 7584 = nand( 7575, 7582) 7593 = nand( 7588, 7591) 7594 = nand( 7585, 7592) 1856 = not( 1850) 920 = and( 895, 853, 827, 805, 792) 925 = and( 792, 821) 926 = and( 805, 792, 845) 927 = and( 827, 792, 868, 805) 928 = and( 853, 827, 792, 877, 805) 937 = and( 805, 845) 938 = and( 827, 868, 805) 939 = and( 853, 827, 877, 805) 940 = and( 895, 827, 805, 853) 941 = and( 805, 845) 942 = and( 827, 868, 805) 943 = and( 853, 827, 877, 805) 944 = and( 827, 868) 945 = and( 853, 827, 877) 946 = and( 895, 827, 853) 947 = and( 827, 868) 948 = and( 853, 827, 877) 949 = and( 853, 877) 956 = and( 895, 853) 1122 = and( 1038, 1093, 1055, 1026, 1074) 1125 = and( 1026, 1050) 1126 = and( 1038, 1026, 1068) 1127 = and( 1055, 1026, 1086, 1038) 1128 = and( 1074, 1055, 1026, 1102, 1038) 1132 = and( 1038, 1068) 1133 = and( 1055, 1086, 1038) 1134 = and( 1074, 1055, 1102, 1038) 1137 = and( 1086, 1055) 1138 = and( 1074, 1055, 1102) 1141 = and( 1074, 1102) 1221 = not( 1217) 1230 = not( 1226) 1244 = not( 1240) 1253 = not( 1249) 1267 = not( 1263) 1276 = not( 1272) 1284 = buff( 1235) 1288 = buff( 1235) 1292 = buff( 1258) 1296 = buff( 1258) 1300 = buff( 1281) 1304 = buff( 1281) 1702 = and( 1687, 1573, 1556, 1546) 1705 = and( 1546, 1567) 1706 = and( 1556, 1546, 1584) 1707 = and( 1573, 1546, 1590, 1556) 1709 = and( 1556, 1584) 1710 = and( 1573, 1590, 1556) 1711 = and( 1687, 1573, 1556) 1712 = and( 1556, 1584) 1713 = and( 1573, 1590, 1556) 1714 = and( 1573, 1590) 1718 = and( 1695, 1655, 1630, 1609, 1598) 1722 = and( 1598, 1624) 1723 = and( 1609, 1598, 1647) 1724 = and( 1630, 1598, 1669, 1609) 1725 = and( 1655, 1630, 1598, 1677, 1609) 1733 = and( 1609, 1647) 1734 = and( 1630, 1669, 1609) 1735 = and( 1655, 1630, 1677, 1609) 1736 = and( 1695, 1630, 1609, 1655) 1737 = and( 1609, 1647) 1738 = and( 1630, 1669, 1609) 1739 = and( 1655, 1630, 1677, 1609) 1740 = and( 1630, 1669) 1741 = and( 1655, 1630, 1677) 1742 = and( 1695, 1630, 1655) 1743 = and( 1630, 1669) 1744 = and( 1655, 1630, 1677) 1745 = and( 1655, 1677) 1749 = and( 1687, 1573) 1750 = and( 1695, 1655) 1935 = and( 1805, 1850, 1822, 1795) 1938 = and( 1795, 1816) 1939 = and( 1805, 1795, 1834) 1940 = and( 1822, 1795, 1841, 1805) 1942 = and( 1805, 1834) 1943 = and( 1822, 1841, 1805) 1944 = and( 1850, 1822, 1805) 1945 = and( 1805, 1834) 1946 = and( 1841, 1822, 1805) 1947 = and( 1822, 1841) 1948 = and( 1850, 1822) 1949 = and( 1822, 1841) 1950 = and( 1869, 1921, 1885, 1859, 1903) 1953 = and( 1859, 1880) 1954 = and( 1869, 1859, 1897) 1955 = and( 1885, 1859, 1914, 1869) 1956 = and( 1903, 1885, 1859, 1929, 1869) 1960 = and( 1869, 1897) 1961 = and( 1885, 1914, 1869) 1962 = and( 1903, 1885, 1929, 1869) 1965 = and( 1914, 1885) 1966 = and( 1903, 1885, 1929) 1969 = and( 1903, 1929) 2343 = nand( 2341, 2342) 2354 = nand( 2352, 2353) 2372 = nand( 2370, 2371) 2400 = nand( 2398, 2399) 2409 = nand( 2407, 2408) 2420 = nand( 2418, 2419) 2436 = nand( 2434, 2435) 2454 = nand( 2452, 2453) 2470 = nand( 5932, 5935) 5936 = not( 5932) 5983 = not( 5977) 2589 = nand( 2587, 2588) 2600 = nand( 2598, 2599) 2618 = nand( 2616, 2617) 2643 = nand( 2641, 2642) 2655 = nand( 2653, 2654) 2676 = nand( 2674, 2675) 2701 = nand( 2699, 2700) 2734 = nand( 2732, 2733) 2740 = nand( 6052, 6055) 6056 = not( 6052) 3022 = and( 3018, 2973, 2965, 2956) 3025 = and( 2956, 2970) 3026 = and( 2965, 2956, 2977) 3027 = and( 2973, 2956, 2979, 2965) 3029 = and( 3021, 3009, 3001, 2992, 2982) 3030 = and( 2982, 2998) 3031 = and( 2992, 2982, 3006) 3032 = and( 3001, 2982, 3013, 2992) 3033 = and( 3009, 3001, 2982, 3015, 2992) 3052 = nand( 3050, 3051) 3062 = nand( 3060, 3061) 3071 = nand( 3069, 3070) 3082 = nand( 3080, 3081) 3093 = nand( 3091, 3092) 3102 = nand( 3100, 3101) 3110 = nand( 3108, 3109) 3119 = nand( 3117, 3118) 3122 = nand( 3120, 3121) 3228 = and( 3215, 3203, 3195, 3186, 3176) 3231 = and( 3176, 3192) 3232 = and( 3186, 3176, 3200) 3233 = and( 3195, 3176, 3207, 3186) 3234 = and( 3203, 3195, 3176, 3209, 3186) 3283 = nand( 3281, 3282) 3295 = nand( 3293, 3294) 3314 = nand( 3312, 3313) 3344 = nand( 3342, 3343) 3353 = nand( 3351, 3352) 3365 = nand( 3363, 3364) 3381 = nand( 3379, 3380) 3399 = nand( 3397, 3398) 3417 = nand( 3415, 3416) 6685 = not( 6679) 3508 = not( 3504) 3517 = not( 3513) 3527 = nand( 3525, 3526) 3536 = nand( 3534, 3535) 3545 = nand( 3543, 3544) 3550 = nand( 3548, 3549) 3559 = nand( 3557, 3558) 3568 = nand( 3566, 3567) 3571 = buff( 3522) 3575 = buff( 3522) 3845 = nand( 3843, 3844) 3856 = nand( 3854, 3855) 3874 = nand( 3872, 3873) 3899 = nand( 3897, 3898) 3911 = nand( 3909, 3910) 3932 = nand( 3930, 3931) 3957 = nand( 3955, 3956) 3989 = nand( 3987, 3988) 3997 = nand( 3995, 3996) 4180 = nand( 4178, 4179) 4189 = nand( 4187, 4188) 4198 = nand( 4196, 4197) 4207 = not( 4203) 4216 = not( 4212) 4221 = nand( 4219, 4220) 4230 = not( 4226) 4239 = not( 4235) 4263 = buff( 4244) 4267 = buff( 4244) 4291 = nand( 4289, 4290) 4300 = nand( 4298, 4299) 4308 = nand( 4306, 4307) 4317 = nand( 4315, 4316) 4327 = nand( 4325, 4326) 4336 = nand( 4334, 4335) 4344 = nand( 4342, 4343) 4352 = nand( 4350, 4351) 4355 = nand( 4353, 4354) 4535 = not( 4531) 4544 = not( 4540) 4558 = not( 4554) 4563 = nand( 4561, 4562) 4572 = nand( 4570, 4571) 4577 = nand( 4575, 4576) 4586 = nand( 4584, 4585) 4595 = nand( 4593, 4594) 4598 = buff( 4549) 4602 = buff( 4549) 4716 = buff( 1921) 4724 = buff( 1859) 4732 = buff( 1869) 4740 = buff( 1885) 4748 = buff( 1903) 4756 = buff( 1093) 4764 = buff( 1026) 4772 = buff( 1038) 4780 = buff( 1055) 4788 = buff( 1074) 4939 = nand( 4937, 4938) 4980 = nand( 4978, 4979) 5044 = buff( 895) 5054 = buff( 853) 5064 = buff( 792) 5074 = buff( 827) 5084 = buff( 805) 5094 = buff( 805) 5132 = buff( 895) 5142 = buff( 853) 5152 = buff( 792) 5162 = buff( 827) 5365 = not( 5359) 5366 = not( 5362) 5488 = buff( 1687) 5498 = buff( 1573) 5508 = buff( 1546) 5518 = buff( 1556) 5546 = buff( 1687) 5556 = buff( 1573) 5566 = buff( 1546) 5576 = buff( 1556) 5614 = buff( 1695) 5624 = buff( 1655) 5634 = buff( 1598) 5644 = buff( 1630) 5654 = buff( 1609) 5664 = buff( 1609) 5702 = buff( 1695) 5712 = buff( 1655) 5722 = buff( 1598) 5732 = buff( 1630) 5820 = buff( 1795) 5828 = buff( 1795) 5836 = buff( 1805) 5844 = buff( 1805) 5852 = buff( 1822) 5860 = buff( 1822) 6121 = not( 6115) 6179 = not( 6173) 6261 = buff( 2724) 7359 = not( 7353) 7360 = not( 7356) 7343 = not( 7337) 7344 = not( 7340) 6809 = nand( 6763, 6764) 6812 = nand( 6753, 6754) 6819 = nand( 6807, 6808) 6822 = nand( 6797, 6798) 6989 = not( 6983) 7135 = not( 7129) 7345 = nand( 7291, 7292) 7348 = nand( 7281, 7282) 7601 = not( 7595) 7602 = not( 7598) 7603 = nand( 7549, 7550) 7606 = nand( 7539, 7540) 7611 = nand( 7593, 7594) 7614 = nand( 7583, 7584) 929 = or( 802, 925, 926, 927, 928) 950 = or( 868, 949) 1129 = or( 1035, 1125, 1126, 1127, 1128) 1708 = or( 1553, 1705, 1706, 1707) 1715 = or( 1584, 1714) 1726 = or( 1606, 1722, 1723, 1724, 1725) 1746 = or( 1669, 1745) 1941 = or( 1802, 1938, 1939, 1940) 1957 = or( 1866, 1953, 1954, 1955, 1956) 2471 = nand( 5929, 5936) 2741 = nand( 6049, 6056) 3028 = or( 2962, 3025, 3026, 3027) 3034 = or( 2989, 3030, 3031, 3032, 3033) 3235 = or( 3183, 3231, 3232, 3233, 3234) 5014 = or( 845, 944, 945, 946) 5034 = or( 821, 937, 938, 939, 940) 5102 = nor( 845, 947, 948) 5122 = nor( 821, 941, 942, 943) 5367 = nand( 5362, 5365) 5368 = nand( 5359, 5366) 5478 = or( 1567, 1709, 1710, 1711) 5536 = nor( 1567, 1712, 1713) 5584 = or( 1647, 1740, 1741, 1742) 5604 = or( 1624, 1733, 1734, 1735, 1736) 5672 = nor( 1647, 1743, 1744) 5692 = nor( 1624, 1737, 1738, 1739) 5817 = or( 1816, 1942, 1943, 1944) 5825 = nor( 1816, 1945, 1946) 5833 = or( 1834, 1947, 1948) 5841 = nor( 1834, 1949) 6340 = nand( 7356, 7359) 6341 = nand( 7353, 7360) 6350 = nand( 7340, 7343) 6351 = nand( 7337, 7344) 7436 = nand( 7598, 7601) 7437 = nand( 7595, 7602) 4720 = not( 4716) 4728 = not( 4724) 4736 = not( 4732) 4744 = not( 4740) 4752 = not( 4748) 4760 = not( 4756) 4768 = not( 4764) 4776 = not( 4772) 4784 = not( 4780) 4792 = not( 4788) 3350 = not( 3344) 2406 = not( 2400) 924 = not( 920) 5088 = not( 5084) 5098 = not( 5094) 997 = and( 902, 920) 1146 = and( 1108, 1122) 1287 = not( 1284) 1291 = not( 1288) 1295 = not( 1292) 1299 = not( 1296) 1303 = not( 1300) 1307 = not( 1304) 1309 = and( 1226, 1217, 1284) 1312 = and( 1230, 1221, 1288) 1315 = and( 1249, 1240, 1292) 1318 = and( 1253, 1244, 1296) 1321 = and( 1272, 1263, 1300) 1324 = and( 1276, 1267, 1304) 1721 = not( 1718) 5522 = not( 5518) 5580 = not( 5576) 5658 = not( 5654) 5668 = not( 5664) 1788 = and( 1702, 1718) 1974 = and( 1935, 1950) 5824 = not( 5820) 5832 = not( 5828) 5840 = not( 5836) 5848 = not( 5844) 1999 = nand( 5852, 5855) 5856 = not( 5852) 2003 = nand( 5860, 5863) 5864 = not( 5860) 2472 = nand( 2470, 2471) 2487 = and( 2354, 2400, 2372, 2343) 2492 = and( 2343, 2366) 2493 = and( 2354, 2343, 2384) 2494 = and( 2372, 2343, 2391, 2354) 2500 = and( 2354, 2384) 2501 = and( 2372, 2391, 2354) 2502 = and( 2400, 2372, 2354) 2503 = and( 2354, 2384) 2504 = and( 2391, 2372, 2354) 2505 = and( 2372, 2391) 2506 = and( 2400, 2372) 2507 = and( 2372, 2391) 2511 = and( 2409, 2431) 2512 = and( 2420, 2409, 2448) 2513 = and( 2436, 2409, 2465, 2420) 2514 = and( 2454, 2436, 2409, 2481, 2420) 2518 = and( 2420, 2448) 2519 = and( 2436, 2465, 2420) 2520 = and( 2454, 2436, 2481, 2420) 2523 = and( 2465, 2436) 2524 = and( 2454, 2436, 2481) 2527 = and( 2454, 2481) 2742 = nand( 2740, 2741) 2749 = and( 2734, 2618, 2600, 2589) 2754 = and( 2589, 2612) 2755 = and( 2600, 2589, 2629) 2756 = and( 2618, 2589, 2635, 2600) 2762 = and( 2600, 2629) 2763 = and( 2618, 2635, 2600) 2764 = and( 2734, 2618, 2600) 2765 = and( 2600, 2629) 2766 = and( 2618, 2635, 2600) 2767 = and( 2618, 2635) 2776 = and( 2643, 2670) 2777 = and( 2655, 2643, 2693) 2778 = and( 2676, 2643, 2715, 2655) 2779 = and( 2701, 2676, 2643, 2724, 2655) 2788 = and( 2655, 2693) 2789 = and( 2676, 2715, 2655) 2790 = and( 2701, 2676, 2724, 2655) 2792 = and( 2655, 2693) 2793 = and( 2676, 2715, 2655) 2794 = and( 2701, 2676, 2724, 2655) 2795 = and( 2676, 2715) 2796 = and( 2701, 2676, 2724) 2798 = and( 2676, 2715) 2799 = and( 2701, 2676, 2724) 2800 = and( 2701, 2724) 2804 = and( 2734, 2618) 3035 = and( 3022, 3029) 3045 = and( 3022, 3034) 3123 = and( 3119, 3071, 3062, 3052) 3128 = and( 3052, 3068) 3129 = and( 3062, 3052, 3076) 3130 = and( 3071, 3052, 3079, 3062) 3136 = and( 3122, 3110, 3102, 3093, 3082) 3139 = and( 3082, 3099) 3140 = and( 3093, 3082, 3107) 3141 = and( 3102, 3082, 3114, 3093) 3142 = and( 3110, 3102, 3082, 3116, 3093) 3249 = and( 3216, 3228) 3431 = and( 3295, 3344, 3314, 3283) 3434 = and( 3283, 3308) 3435 = and( 3295, 3283, 3327) 3436 = and( 3314, 3283, 3335, 3295) 3438 = and( 3295, 3327) 3439 = and( 3314, 3335, 3295) 3440 = and( 3344, 3314, 3295) 3441 = and( 3295, 3327) 3442 = and( 3335, 3314, 3295) 3443 = and( 3314, 3335) 3444 = and( 3344, 3314) 3445 = and( 3314, 3335) 3446 = and( 3365, 3417, 3381, 3353, 3399) 3449 = and( 3353, 3376) 3450 = and( 3365, 3353, 3393) 3451 = and( 3381, 3353, 3410, 3365) 3452 = and( 3399, 3381, 3353, 3425, 3365) 3456 = and( 3365, 3393) 3457 = and( 3381, 3410, 3365) 3458 = and( 3399, 3381, 3425, 3365) 3460 = and( 3410, 3381) 3461 = and( 3399, 3381, 3425) 3463 = and( 3399, 3425) 3531 = not( 3527) 3540 = not( 3536) 3554 = not( 3550) 3563 = not( 3559) 3574 = not( 3571) 3578 = not( 3575) 3579 = buff( 3545) 3583 = buff( 3545) 3587 = buff( 3568) 3591 = buff( 3568) 3596 = and( 3513, 3504, 3571) 3599 = and( 3517, 3508, 3575) 4004 = and( 3989, 3874, 3856, 3845) 4007 = and( 3845, 3868) 4008 = and( 3856, 3845, 3885) 4009 = and( 3874, 3845, 3891, 3856) 4011 = and( 3856, 3885) 4012 = and( 3874, 3891, 3856) 4013 = and( 3989, 3874, 3856) 4014 = and( 3856, 3885) 4015 = and( 3874, 3891, 3856) 4016 = and( 3874, 3891) 4020 = and( 3997, 3957, 3932, 3911, 3899) 4024 = and( 3899, 3926) 4025 = and( 3911, 3899, 3949) 4026 = and( 3932, 3899, 3971, 3911) 4027 = and( 3957, 3932, 3899, 3979, 3911) 4035 = and( 3911, 3949) 4036 = and( 3932, 3971, 3911) 4037 = and( 3957, 3932, 3979, 3911) 4038 = and( 3997, 3932, 3911, 3957) 4039 = and( 3911, 3949) 4040 = and( 3932, 3971, 3911) 4041 = and( 3957, 3932, 3979, 3911) 4042 = and( 3932, 3971) 4043 = and( 3957, 3932, 3979) 4044 = and( 3997, 3932, 3957) 4045 = and( 3932, 3971) 4046 = and( 3957, 3932, 3979) 4047 = and( 3957, 3979) 4051 = and( 3989, 3874) 4052 = and( 3997, 3957) 4184 = not( 4180) 4193 = not( 4189) 4247 = buff( 4198) 4251 = buff( 4198) 4255 = buff( 4221) 4259 = buff( 4221) 4266 = not( 4263) 4270 = not( 4267) 4284 = and( 4235, 4226, 4263) 4287 = and( 4239, 4230, 4267) 4356 = and( 4352, 4308, 4300, 4291) 4361 = and( 4291, 4305) 4362 = and( 4300, 4291, 4312) 4363 = and( 4308, 4291, 4314, 4300) 4369 = and( 4355, 4344, 4336, 4327, 4317) 4372 = and( 4317, 4333) 4373 = and( 4327, 4317, 4341) 4374 = and( 4336, 4317, 4348, 4327) 4375 = and( 4344, 4336, 4317, 4349, 4327) 4567 = not( 4563) 4581 = not( 4577) 4590 = not( 4586) 4601 = not( 4598) 4605 = not( 4602) 4606 = buff( 4572) 4610 = buff( 4572) 4614 = buff( 4595) 4618 = buff( 4595) 4623 = and( 4540, 4531, 4598) 4626 = and( 4544, 4535, 4602) 4796 = buff( 3417) 4804 = buff( 3353) 4812 = buff( 3365) 4820 = buff( 3381) 4828 = buff( 3399) 4844 = buff( 2409) 4852 = buff( 2420) 4860 = buff( 2436) 4868 = buff( 2454) 4945 = not( 4939) 4948 = nand( 4939, 4946) 4986 = not( 4980) 4989 = nand( 4980, 4987) 5048 = not( 5044) 5058 = not( 5054) 5068 = not( 5064) 5078 = not( 5074) 5166 = not( 5162) 5136 = not( 5132) 5146 = not( 5142) 5156 = not( 5152) 5388 = nand( 5367, 5368) 5492 = not( 5488) 5502 = not( 5498) 5512 = not( 5508) 5550 = not( 5546) 5560 = not( 5556) 5570 = not( 5566) 5618 = not( 5614) 5628 = not( 5624) 5638 = not( 5634) 5648 = not( 5644) 5736 = not( 5732) 5706 = not( 5702) 5716 = not( 5712) 5726 = not( 5722) 5940 = buff( 2343) 5948 = buff( 2343) 5956 = buff( 2354) 5964 = buff( 2354) 5972 = buff( 2372) 5980 = buff( 2372) 6080 = buff( 2734) 6090 = buff( 2618) 6100 = buff( 2589) 6110 = buff( 2600) 6138 = buff( 2734) 6148 = buff( 2618) 6158 = buff( 2589) 6168 = buff( 2600) 6216 = buff( 2701) 6226 = buff( 2643) 6236 = buff( 2676) 6246 = buff( 2655) 6256 = buff( 2655) 6267 = not( 6261) 6304 = buff( 2701) 6314 = buff( 2643) 6324 = buff( 2676) 6342 = nand( 6340, 6341) 6352 = nand( 6350, 6351) 7351 = not( 7345) 7352 = not( 7348) 6642 = buff( 3283) 6650 = buff( 3283) 6658 = buff( 3295) 6666 = buff( 3295) 6674 = buff( 3314) 6682 = buff( 3314) 6815 = not( 6809) 6816 = not( 6812) 6825 = not( 6819) 6826 = not( 6822) 6948 = buff( 3989) 6958 = buff( 3874) 6968 = buff( 3845) 6978 = buff( 3856) 7006 = buff( 3989) 7016 = buff( 3874) 7026 = buff( 3845) 7036 = buff( 3856) 7074 = buff( 3997) 7084 = buff( 3957) 7094 = buff( 3899) 7104 = buff( 3932) 7114 = buff( 3911) 7124 = buff( 3911) 7162 = buff( 3997) 7172 = buff( 3957) 7182 = buff( 3899) 7192 = buff( 3932) 7438 = nand( 7436, 7437) 7617 = not( 7611) 7618 = not( 7614) 7609 = not( 7603) 7610 = not( 7606) 1151 = and( 1129, 1108) 1002 = and( 902, 929) 933 = not( 929) 1308 = and( 1221, 1226, 1287) 1311 = and( 1217, 1230, 1291) 1314 = and( 1244, 1249, 1295) 1317 = and( 1240, 1253, 1299) 1320 = and( 1267, 1272, 1303) 1323 = and( 1263, 1276, 1307) 1730 = not( 1726) 1789 = and( 1702, 1726) 1981 = and( 1957, 1935) 5823 = not( 5817) 1986 = nand( 5817, 5824) 5831 = not( 5825) 1989 = nand( 5825, 5832) 5839 = not( 5833) 1993 = nand( 5833, 5840) 5847 = not( 5841) 1996 = nand( 5841, 5848) 2000 = nand( 5849, 5856) 2004 = nand( 5857, 5864) 2495 = or( 2351, 2492, 2493, 2494) 2515 = or( 2417, 2511, 2512, 2513, 2514) 2757 = or( 2597, 2754, 2755, 2756) 2768 = or( 2629, 2767) 2780 = or( 2652, 2776, 2777, 2778, 2779) 2801 = or( 2715, 2800) 3046 = or( 3028, 3045) 3131 = or( 3059, 3128, 3129, 3130) 3143 = or( 3090, 3139, 3140, 3141, 3142) 3238 = not( 3235) 3258 = and( 3216, 3235) 3437 = or( 3292, 3434, 3435, 3436) 3453 = or( 3362, 3449, 3450, 3451, 3452) 3595 = and( 3508, 3513, 3574) 3598 = and( 3504, 3517, 3578) 4010 = or( 3853, 4007, 4008, 4009) 4017 = or( 3885, 4016) 4028 = or( 3908, 4024, 4025, 4026, 4027) 4048 = or( 3971, 4047) 4283 = and( 4230, 4235, 4266) 4286 = and( 4226, 4239, 4270) 4364 = or( 4297, 4361, 4362, 4363) 4376 = or( 4324, 4372, 4373, 4374, 4375) 4622 = and( 4535, 4540, 4601) 4625 = and( 4531, 4544, 4605) 4947 = nand( 4942, 4945) 4988 = nand( 4983, 4986) 5018 = not( 5014) 5019 = nand( 5014, 5017) 5024 = or( 950, 956) 5038 = not( 5034) 5106 = not( 5102) 5107 = nand( 5102, 5105) 5112 = not( 950) 5126 = not( 5122) 5468 = or( 1715, 1749) 5482 = not( 5478) 5526 = not( 1715) 5540 = not( 5536) 5588 = not( 5584) 5589 = nand( 5584, 5587) 5594 = or( 1746, 1750) 5608 = not( 5604) 5676 = not( 5672) 5677 = nand( 5672, 5675) 5682 = not( 1746) 5696 = not( 5692) 5937 = or( 2366, 2500, 2501, 2502) 5945 = nor( 2366, 2503, 2504) 5953 = or( 2384, 2505, 2506) 5961 = nor( 2384, 2507) 6070 = or( 2612, 2762, 2763, 2764) 6128 = nor( 2612, 2765, 2766) 6264 = nor( 2693, 2798, 2799) 6284 = nor( 2670, 2792, 2793, 2794) 6360 = nand( 7348, 7351) 6361 = nand( 7345, 7352) 6639 = or( 3308, 3438, 3439, 3440) 6647 = nor( 3308, 3441, 3442) 6655 = or( 3327, 3443, 3444) 6663 = nor( 3327, 3445) 6817 = nand( 6812, 6815) 6818 = nand( 6809, 6816) 6827 = nand( 6822, 6825) 6828 = nand( 6819, 6826) 6938 = or( 3868, 4011, 4012, 4013) 6996 = nor( 3868, 4014, 4015) 7044 = or( 3949, 4042, 4043, 4044) 7064 = or( 3926, 4035, 4036, 4037, 4038) 7132 = nor( 3949, 4045, 4046) 7152 = nor( 3926, 4039, 4040, 4041) 7446 = nand( 7614, 7617) 7447 = nand( 7611, 7618) 7456 = nand( 7606, 7609) 7457 = nand( 7603, 7610) 241 = or( 1117, 1151) 265 = or( 908, 1002) 2005 = nand( 2003, 2004) 4800 = not( 4796) 4808 = not( 4804) 4816 = not( 4812) 4824 = not( 4820) 4832 = not( 4828) 4848 = not( 4844) 4856 = not( 4852) 4864 = not( 4860) 4872 = not( 4868) 1310 = nor( 1308, 1309) 1313 = nor( 1311, 1312) 1316 = nor( 1314, 1315) 1319 = nor( 1317, 1318) 1322 = nor( 1320, 1321) 1325 = nor( 1323, 1324) 5392 = not( 5388) 1790 = or( 1708, 1789) 1982 = or( 1941, 1981) 1985 = nand( 5820, 5823) 1988 = nand( 5828, 5831) 1992 = nand( 5836, 5839) 1995 = nand( 5844, 5847) 2001 = nand( 1999, 2000) 2491 = not( 2487) 2508 = and( 2420, 2472, 2436, 2409, 2454) 2522 = and( 4526, 2472, 2436, 2454, 2420) 2526 = and( 4526, 2472, 2436, 2454) 2529 = and( 4526, 2472, 2454) 2531 = and( 4526, 2472) 5944 = not( 5940) 5952 = not( 5948) 5960 = not( 5956) 5968 = not( 5964) 2555 = nand( 5972, 5975) 5976 = not( 5972) 2559 = nand( 5980, 5983) 5984 = not( 5980) 2753 = not( 2749) 2771 = and( 2742, 2701, 2676, 2655, 2643) 2791 = and( 2742, 2676, 2655, 2701) 2797 = and( 2742, 2676, 2701) 2807 = and( 2742, 2701) 6114 = not( 6110) 6172 = not( 6168) 6250 = not( 6246) 6260 = not( 6256) 6346 = not( 6342) 6356 = not( 6352) 3127 = not( 3123) 3156 = and( 3123, 3136) 3259 = or( 3223, 3258) 3466 = and( 3431, 3446) 6646 = not( 6642) 6654 = not( 6650) 6662 = not( 6658) 6670 = not( 6666) 3483 = nand( 6674, 6677) 6678 = not( 6674) 3487 = nand( 6682, 6685) 6686 = not( 6682) 3582 = not( 3579) 3586 = not( 3583) 3590 = not( 3587) 3594 = not( 3591) 3597 = nor( 3595, 3596) 3600 = nor( 3598, 3599) 3602 = and( 3536, 3527, 3579) 3605 = and( 3540, 3531, 3583) 3608 = and( 3559, 3550, 3587) 3611 = and( 3563, 3554, 3591) 4023 = not( 4020) 6982 = not( 6978) 7040 = not( 7036) 7118 = not( 7114) 7128 = not( 7124) 4089 = and( 4004, 4020) 4250 = not( 4247) 4254 = not( 4251) 4258 = not( 4255) 4262 = not( 4259) 4272 = and( 4189, 4180, 4247) 4275 = and( 4193, 4184, 4251) 4278 = and( 4212, 4203, 4255) 4281 = and( 4216, 4207, 4259) 4285 = nor( 4283, 4284) 4288 = nor( 4286, 4287) 4360 = not( 4356) 4380 = nand( 4369, 89) 4386 = and( 4356, 4369) 7442 = not( 7438) 4609 = not( 4606) 4613 = not( 4610) 4617 = not( 4614) 4621 = not( 4618) 4624 = nor( 4622, 4623) 4627 = nor( 4625, 4626) 4629 = and( 4563, 4554, 4606) 4632 = and( 4567, 4558, 4610) 4635 = and( 4586, 4577, 4614) 4638 = and( 4590, 4581, 4618) 4836 = buff( 2472) 4949 = nand( 4947, 4948) 4990 = nand( 4988, 4989) 5020 = nand( 5011, 5018) 5108 = nand( 5099, 5106) 5590 = nand( 5581, 5588) 5678 = nand( 5669, 5676) 6084 = not( 6080) 6094 = not( 6090) 6104 = not( 6100) 6142 = not( 6138) 6152 = not( 6148) 6162 = not( 6158) 6206 = buff( 2742) 6220 = not( 6216) 6230 = not( 6226) 6240 = not( 6236) 6328 = not( 6324) 6294 = buff( 2742) 6308 = not( 6304) 6318 = not( 6314) 6362 = nand( 6360, 6361) 6840 = nand( 6817, 6818) 6848 = nand( 6827, 6828) 6952 = not( 6948) 6962 = not( 6958) 6972 = not( 6968) 7010 = not( 7006) 7020 = not( 7016) 7030 = not( 7026) 7078 = not( 7074) 7088 = not( 7084) 7098 = not( 7094) 7108 = not( 7104) 7196 = not( 7192) 7166 = not( 7162) 7176 = not( 7172) 7186 = not( 7182) 7448 = nand( 7446, 7447) 7458 = nand( 7456, 7457) 254 = and( 3046, 3249) 260 = and( 3046, 3249) 1987 = nand( 1985, 1986) 1994 = nand( 1992, 1993) 2002 = not( 2001) 962 = and( 933, 924) 1751 = and( 1730, 1721) 1990 = nand( 1988, 1989) 1997 = nand( 1995, 1996) 2499 = not( 2495) 2536 = and( 2515, 2487) 5943 = not( 5937) 2542 = nand( 5937, 5944) 5951 = not( 5945) 2545 = nand( 5945, 5952) 5959 = not( 5953) 2549 = nand( 5953, 5960) 5967 = not( 5961) 2552 = nand( 5961, 5968) 2556 = nand( 5969, 5976) 2560 = nand( 5977, 5984) 2761 = not( 2757) 2784 = not( 2780) 2853 = and( 2749, 2780) 3135 = not( 3131) 3146 = not( 3143) 3163 = and( 3123, 3143) 3467 = and( 3453, 3431) 6645 = not( 6639) 3470 = nand( 6639, 6646) 6653 = not( 6647) 3473 = nand( 6647, 6654) 6661 = not( 6655) 3477 = nand( 6655, 6662) 6669 = not( 6663) 3480 = nand( 6663, 6670) 3484 = nand( 6671, 6678) 3488 = nand( 6679, 6686) 3601 = and( 3531, 3536, 3582) 3604 = and( 3527, 3540, 3586) 3607 = and( 3554, 3559, 3590) 3610 = and( 3550, 3563, 3594) 4032 = not( 4028) 4090 = and( 4004, 4028) 4271 = and( 4184, 4189, 4250) 4274 = and( 4180, 4193, 4254) 4277 = and( 4207, 4212, 4258) 4280 = and( 4203, 4216, 4262) 4368 = not( 4364) 4379 = not( 4376) 4387 = and( 4356, 4376) 4628 = and( 4558, 4563, 4609) 4631 = and( 4554, 4567, 4613) 4634 = and( 4581, 4586, 4617) 4637 = and( 4577, 4590, 4621) 4841 = or( 2431, 2518, 2519, 2520, 2522) 4849 = or( 2448, 2523, 2524, 2526) 4857 = or( 2465, 2527, 2529) 4865 = or( 2481, 2531) 5021 = nand( 5019, 5020) 5028 = not( 5024) 5109 = nand( 5107, 5108) 5116 = not( 5112) 5369 = nand( 1313, 1310) 5377 = nand( 1319, 1316) 5385 = nand( 1325, 1322) 5472 = not( 5468) 5473 = nand( 5468, 5471) 5530 = not( 5526) 5531 = nand( 5526, 5529) 5591 = nand( 5589, 5590) 5598 = not( 5594) 5679 = nand( 5677, 5678) 5686 = not( 5682) 6060 = or( 2768, 2804) 6074 = not( 6070) 6118 = not( 2768) 6132 = not( 6128) 6176 = or( 2693, 2795, 2796, 2797) 6186 = or( 2801, 2807) 6196 = or( 2670, 2788, 2789, 2790, 2791) 6268 = not( 6264) 6269 = nand( 6264, 6267) 6274 = not( 2801) 6288 = not( 6284) 6337 = nand( 4288, 4285) 6829 = nand( 3600, 3597) 6928 = or( 4017, 4051) 6942 = not( 6938) 6986 = not( 4017) 7000 = not( 6996) 7048 = not( 7044) 7049 = nand( 7044, 7047) 7054 = or( 4048, 4052) 7068 = not( 7064) 7136 = not( 7132) 7137 = nand( 7132, 7135) 7142 = not( 4048) 7156 = not( 7152) 7433 = nand( 4627, 4624) 242 = and( 1982, 1146) 3151 = nand( 3135, 3127) 257 = and( 89, 4386, 3156, 3035, 3249) 263 = and( 89, 4386, 3156, 3035, 3249) 266 = and( 1790, 997) 1991 = not( 1990) 1998 = not( 1997) 3489 = nand( 3487, 3488) 371 = nand( 4836, 4839) 4840 = not( 4836) 2561 = nand( 2559, 2560) 2532 = and( 2487, 2508) 2537 = or( 2495, 2536) 2541 = nand( 5940, 5943) 2544 = nand( 5948, 5951) 2548 = nand( 5956, 5959) 2551 = nand( 5964, 5967) 2557 = nand( 2555, 2556) 2563 = and( 2508, 4526) 2577 = nand( 2499, 2491) 2775 = not( 2771) 2806 = nand( 2771, 4526) 2808 = nand( 2761, 2753) 2852 = and( 2749, 2771) 2854 = or( 2757, 2853) 6366 = not( 6362) 4381 = nand( 4368, 4360) 3164 = or( 3131, 3163) 3241 = and( 89, 4386, 3156, 3035) 3468 = or( 3437, 3467) 3469 = nand( 6642, 6645) 3472 = nand( 6650, 6653) 3476 = nand( 6658, 6661) 3479 = nand( 6666, 6669) 3485 = nand( 3483, 3484) 3603 = nor( 3601, 3602) 3606 = nor( 3604, 3605) 3609 = nor( 3607, 3608) 3612 = nor( 3610, 3611) 6844 = not( 6840) 6852 = not( 6848) 4091 = or( 4010, 4090) 4273 = nor( 4271, 4272) 4276 = nor( 4274, 4275) 4279 = nor( 4277, 4278) 4282 = nor( 4280, 4281) 4382 = and( 4379, 4380) 4388 = or( 4364, 4387) 7452 = not( 7448) 7462 = not( 7458) 4630 = nor( 4628, 4629) 4633 = nor( 4631, 4632) 4636 = nor( 4634, 4635) 4639 = nor( 4637, 4638) 4955 = not( 4949) 4958 = nand( 4949, 4956) 4996 = not( 4990) 4999 = nand( 4990, 4997) 5474 = nand( 5465, 5472) 5532 = nand( 5523, 5530) 6210 = not( 6206) 6270 = nand( 6261, 6268) 6298 = not( 6294) 7050 = nand( 7041, 7048) 7138 = nand( 7129, 7136) 3471 = nand( 3469, 3470) 3478 = nand( 3476, 3477) 3486 = not( 3485) 372 = nand( 4833, 4840) 2543 = nand( 2541, 2542) 2550 = nand( 2548, 2549) 2558 = not( 2557) 4847 = not( 4841) 387 = nand( 4841, 4848) 4855 = not( 4849) 390 = nand( 4849, 4856) 4863 = not( 4857) 393 = nand( 4857, 4864) 4871 = not( 4865) 396 = nand( 4865, 4872) 965 = not( 962) 5375 = not( 5369) 1327 = nand( 5369, 5376) 5383 = not( 5377) 1330 = nand( 5377, 5384) 5391 = not( 5385) 1333 = nand( 5385, 5392) 1754 = not( 1751) 2546 = nand( 2544, 2545) 2553 = nand( 2551, 2552) 2564 = or( 2515, 2563) 2809 = and( 2784, 2806) 2813 = and( 2784, 2775) 6345 = not( 6337) 2860 = nand( 6337, 6346) 3474 = nand( 3472, 3473) 3481 = nand( 3479, 3480) 6835 = not( 6829) 3614 = nand( 6829, 6836) 4053 = and( 4032, 4023) 7441 = not( 7433) 4516 = nand( 7433, 7442) 4957 = nand( 4952, 4955) 4998 = nand( 4993, 4996) 5027 = not( 5021) 5030 = nand( 5021, 5028) 5115 = not( 5109) 5118 = nand( 5109, 5116) 5475 = nand( 5473, 5474) 5533 = nand( 5531, 5532) 5597 = not( 5591) 5600 = nand( 5591, 5598) 5685 = not( 5679) 5688 = nand( 5679, 5686) 6064 = not( 6060) 6065 = nand( 6060, 6063) 6122 = not( 6118) 6123 = nand( 6118, 6121) 6180 = not( 6176) 6181 = nand( 6176, 6179) 6190 = not( 6186) 6200 = not( 6196) 6271 = nand( 6269, 6270) 6278 = not( 6274) 6347 = nand( 4276, 4273) 6357 = nand( 4282, 4279) 6837 = nand( 3606, 3603) 6845 = nand( 3612, 3609) 6932 = not( 6928) 6933 = nand( 6928, 6931) 6990 = not( 6986) 6991 = nand( 6986, 6989) 7051 = nand( 7049, 7050) 7058 = not( 7054) 7139 = nand( 7137, 7138) 7146 = not( 7142) 7443 = nand( 4639, 4636) 7453 = nand( 4633, 4630) 243 = and( 3468, 1974, 1146) 244 = and( 2537, 3466, 1974, 1146) 245 = and( 4526, 2532, 3466, 1974, 1146) 255 = and( 3164, 3035, 3249) 256 = and( 4388, 3156, 3035, 3249) 261 = and( 3164, 3035, 3249) 262 = and( 4388, 3156, 3035, 3249) 267 = and( 4091, 1788, 997) 268 = and( 2854, 4089, 1788, 997) 269 = and( 4526, 2852, 4089, 1788, 997) 3475 = not( 3474) 3482 = not( 3481) 373 = nand( 371, 372) 2547 = not( 2546) 2554 = not( 2553) 386 = nand( 4844, 4847) 389 = nand( 4852, 4855) 392 = nand( 4860, 4863) 395 = nand( 4868, 4871) 1326 = nand( 5372, 5375) 1329 = nand( 5380, 5383) 1332 = nand( 5388, 5391) 1436 = and( 4091, 1788) 1440 = and( 2854, 4089, 1788) 1445 = and( 4526, 2852, 4089, 1788) 1450 = and( 2854, 4089) 1454 = and( 4526, 2852, 4089) 2859 = nand( 6342, 6345) 4385 = not( 4382) 3148 = and( 4382, 4364) 3239 = and( 3164, 3035) 3240 = and( 4388, 3156, 3035) 3265 = and( 3468, 1974) 3267 = and( 2537, 3466, 1974) 3270 = and( 4526, 2532, 3466, 1974) 3274 = and( 2537, 3466) 3277 = and( 4526, 2532, 3466) 3613 = nand( 6832, 6835) 4515 = nand( 7438, 7441) 4959 = nand( 4957, 4958) 5000 = nand( 4998, 4999) 5029 = nand( 5024, 5027) 5117 = nand( 5112, 5115) 5599 = nand( 5594, 5597) 5687 = nand( 5682, 5685) 6066 = nand( 6057, 6064) 6124 = nand( 6115, 6122) 6182 = nand( 6173, 6180) 6934 = nand( 6925, 6932) 6992 = nand( 6983, 6990) 246 = or( 241, 242, 243, 244, 245) 258 = or( 3259, 254, 255, 256, 257) 264 = or( 3259, 260, 261, 262, 263) 270 = or( 265, 266, 267, 268, 269) 375 = and( 2564, 2543) 378 = and( 2564, 2550) 381 = and( 2564, 2558) 384 = and( 2564, 2406) 388 = nand( 386, 387) 391 = nand( 389, 390) 394 = nand( 392, 393) 397 = nand( 395, 396) 1328 = nand( 1326, 1327) 1331 = nand( 1329, 1330) 1334 = nand( 1332, 1333) 1447 = or( 1790, 1436, 1440, 1445) 1766 = or( 4091, 1450, 1454) 2571 = not( 2564) 2579 = and( 2577, 2564) 2812 = not( 2809) 2816 = not( 2813) 2851 = and( 2809, 2757) 2861 = nand( 2859, 2860) 6355 = not( 6347) 2863 = nand( 6347, 6356) 6365 = not( 6357) 2866 = nand( 6357, 6366) 3147 = and( 4381, 4385) 3242 = or( 3046, 3239, 3240, 3241) 3271 = or( 1982, 3265, 3267, 3270) 3279 = or( 3468, 3274, 3277) 3615 = nand( 3613, 3614) 6843 = not( 6837) 3617 = nand( 6837, 6844) 6851 = not( 6845) 3620 = nand( 6845, 6852) 4056 = not( 4053) 4517 = nand( 4515, 4516) 7451 = not( 7443) 4519 = nand( 7443, 7452) 7461 = not( 7453) 4522 = nand( 7453, 7462) 5031 = nand( 5029, 5030) 5119 = nand( 5117, 5118) 5481 = not( 5475) 5484 = nand( 5475, 5482) 5539 = not( 5533) 5542 = nand( 5533, 5540) 5601 = nand( 5599, 5600) 5689 = nand( 5687, 5688) 6067 = nand( 6065, 6066) 6125 = nand( 6123, 6124) 6183 = nand( 6181, 6182) 6277 = not( 6271) 6280 = nand( 6271, 6278) 6935 = nand( 6933, 6934) 6993 = nand( 6991, 6992) 7057 = not( 7051) 7060 = nand( 7051, 7058) 7145 = not( 7139) 7148 = nand( 7139, 7146) 4968 = nand( 4959, 4966) 5009 = nand( 5000, 5007) 2850 = and( 2808, 2812) 2862 = nand( 6352, 6355) 2865 = nand( 6362, 6365) 3149 = or( 3147, 3148) 3243 = nand( 3228, 3242) 3616 = nand( 6840, 6843) 3619 = nand( 6848, 6851) 4518 = nand( 7448, 7451) 4521 = nand( 7458, 7461) 4965 = not( 4959) 5006 = not( 5000) 5483 = nand( 5478, 5481) 5541 = nand( 5536, 5539) 6279 = nand( 6274, 6277) 7059 = nand( 7054, 7057) 7147 = nand( 7142, 7145) 374 = and( 2547, 2571) 377 = and( 2554, 2571) 380 = and( 2561, 2571) 383 = and( 2400, 2571) 955 = nand( 920, 1447) 4967 = nand( 4962, 4965) 5008 = nand( 5003, 5006) 975 = buff( 1447) 1136 = and( 3271, 1093, 1055, 1074, 1038) 1140 = and( 3271, 1093, 1055, 1074) 1143 = and( 3271, 1093, 1074) 1145 = and( 3271, 1093) 1160 = and( 1122, 3271) 1771 = not( 1766) 1964 = and( 3279, 1921, 1885, 1903, 1869) 1968 = and( 3279, 1921, 1885, 1903) 1971 = and( 3279, 1921, 1903) 1973 = and( 3279, 1921) 2007 = and( 1950, 3279) 2578 = and( 2495, 2571) 2864 = nand( 2862, 2863) 2867 = nand( 2865, 2866) 3150 = nand( 3136, 3149) 3245 = and( 3238, 3243) 3618 = nand( 3616, 3617) 3621 = nand( 3619, 3620) 4067 = or( 2850, 2851) 4520 = nand( 4518, 4519) 4523 = nand( 4521, 4522) 4713 = buff( 3279) 4753 = buff( 3271) 5037 = not( 5031) 5040 = nand( 5031, 5038) 5125 = not( 5119) 5128 = nand( 5119, 5126) 5485 = nand( 5483, 5484) 5543 = nand( 5541, 5542) 5607 = not( 5601) 5610 = nand( 5601, 5608) 5695 = not( 5689) 5698 = nand( 5689, 5696) 6073 = not( 6067) 6076 = nand( 6067, 6074) 6131 = not( 6125) 6134 = nand( 6125, 6132) 6189 = not( 6183) 6192 = nand( 6183, 6190) 6281 = nand( 6279, 6280) 6941 = not( 6935) 6944 = nand( 6935, 6942) 6999 = not( 6993) 7002 = nand( 6993, 7000) 7061 = nand( 7059, 7060) 7149 = nand( 7147, 7148) 376 = or( 374, 375) 379 = or( 377, 378) 382 = or( 380, 381) 385 = or( 383, 384) 958 = and( 933, 955) 967 = nand( 4967, 4968) 971 = nand( 5008, 5009) 1161 = or( 1129, 1160) 2008 = or( 1957, 2007) 2580 = or( 2578, 2579) 2868 = and( 1331, 2861, 2864, 2867) 3152 = and( 3146, 3150) 4443 = and( 1328, 1334, 3618, 3621) 4524 = and( 3615, 4517, 4520, 4523) 4721 = or( 1880, 1960, 1961, 1962, 1964) 4729 = or( 1897, 1965, 1966, 1968) 4737 = or( 1914, 1969, 1971) 4745 = or( 1929, 1973) 4761 = or( 1050, 1132, 1133, 1134, 1136) 4769 = or( 1068, 1137, 1138, 1140) 4777 = or( 1086, 1141, 1143) 4785 = or( 1102, 1145) 5039 = nand( 5034, 5037) 5127 = nand( 5122, 5125) 5609 = nand( 5604, 5607) 5697 = nand( 5692, 5695) 6075 = nand( 6070, 6073) 6133 = nand( 6128, 6131) 6191 = nand( 6186, 6189) 6943 = nand( 6938, 6941) 7001 = nand( 6996, 6999) 3248 = not( 3245) 248 = and( 3245, 3223) 4719 = not( 4713) 294 = nand( 4713, 4720) 4759 = not( 4753) 323 = nand( 4753, 4760) 980 = not( 975) 4072 = not( 4067) 5041 = nand( 5039, 5040) 5129 = nand( 5127, 5128) 5491 = not( 5485) 5494 = nand( 5485, 5492) 5549 = not( 5543) 5552 = nand( 5543, 5550) 5611 = nand( 5609, 5610) 5699 = nand( 5697, 5698) 6077 = nand( 6075, 6076) 6135 = nand( 6133, 6134) 6193 = nand( 6191, 6192) 6287 = not( 6281) 6290 = nand( 6281, 6288) 6945 = nand( 6943, 6944) 7003 = nand( 7001, 7002) 7067 = not( 7061) 7070 = nand( 7061, 7068) 7155 = not( 7149) 7158 = nand( 7149, 7156) 247 = and( 3244, 3248) 3155 = not( 3152) 251 = and( 3152, 3131) 272 = and( 1176, 1161) 961 = not( 958) 275 = and( 958, 908) 293 = nand( 4716, 4719) 297 = and( 2008, 1987) 300 = and( 2008, 1994) 303 = and( 2008, 2002) 306 = and( 2008, 1856) 4727 = not( 4721) 309 = nand( 4721, 4728) 4735 = not( 4729) 312 = nand( 4729, 4736) 4743 = not( 4737) 315 = nand( 4737, 4744) 4751 = not( 4745) 318 = nand( 4745, 4752) 322 = nand( 4756, 4759) 4767 = not( 4761) 326 = nand( 4761, 4768) 4775 = not( 4769) 329 = nand( 4769, 4776) 4783 = not( 4777) 332 = nand( 4777, 4784) 4791 = not( 4785) 335 = nand( 4785, 4792) 412 = not( 4443) 414 = not( 4524) 416 = not( 2868) 2881 = and( 4443, 4524, 2868) 993 = and( 971, 962, 975) 994 = and( 967, 965, 975) 1166 = not( 1161) 1171 = and( 1161, 1155) 1174 = and( 1161, 1023) 2014 = not( 2008) 3459 = and( 2580, 3417, 3381, 3399, 3365) 3462 = and( 2580, 3417, 3381, 3399) 3464 = and( 2580, 3417, 3399) 3465 = and( 2580, 3417) 3490 = and( 3446, 2580) 4793 = buff( 2580) 5493 = nand( 5488, 5491) 5551 = nand( 5546, 5549) 6289 = nand( 6284, 6287) 7069 = nand( 7064, 7067) 7157 = nand( 7152, 7155) 249 = or( 247, 248) 250 = and( 3151, 3155) 274 = and( 957, 961) 295 = nand( 293, 294) 308 = nand( 4724, 4727) 311 = nand( 4732, 4735) 314 = nand( 4740, 4743) 317 = nand( 4748, 4751) 324 = nand( 322, 323) 325 = nand( 4764, 4767) 328 = nand( 4772, 4775) 331 = nand( 4780, 4783) 334 = nand( 4788, 4791) 417 = and( 2876, 2878, 2881) 991 = and( 971, 933, 980) 992 = and( 967, 929, 980) 3491 = or( 3453, 3490) 4801 = or( 3376, 3456, 3457, 3458, 3459) 4809 = or( 3393, 3460, 3461, 3462) 4817 = or( 3410, 3463, 3464) 4825 = or( 3425, 3465) 5047 = not( 5041) 5050 = nand( 5041, 5048) 5135 = not( 5129) 5138 = nand( 5129, 5136) 5495 = nand( 5493, 5494) 5553 = nand( 5551, 5552) 5617 = not( 5611) 5620 = nand( 5611, 5618) 5705 = not( 5699) 5708 = nand( 5699, 5706) 6083 = not( 6077) 6086 = nand( 6077, 6084) 6141 = not( 6135) 6144 = nand( 6135, 6142) 6199 = not( 6193) 6202 = nand( 6193, 6200) 6291 = nand( 6289, 6290) 6951 = not( 6945) 6954 = nand( 6945, 6952) 7009 = not( 7003) 7012 = nand( 7003, 7010) 7071 = nand( 7069, 7070) 7159 = nand( 7157, 7158) 252 = or( 250, 251) 271 = and( 1117, 1166) 276 = or( 274, 275) 296 = and( 1991, 2014) 299 = and( 1998, 2014) 302 = and( 2005, 2014) 305 = and( 1850, 2014) 310 = nand( 308, 309) 313 = nand( 311, 312) 316 = nand( 314, 315) 319 = nand( 317, 318) 327 = nand( 325, 326) 330 = nand( 328, 329) 333 = nand( 331, 332) 336 = nand( 334, 335) 4799 = not( 4793) 343 = nand( 4793, 4800) 418 = not( 417) 1170 = and( 1158, 1166) 1173 = and( 1019, 1166) 5049 = nand( 5044, 5047) 5137 = nand( 5132, 5135) 5167 = or( 991, 992, 993, 994) 5619 = nand( 5614, 5617) 5707 = nand( 5702, 5705) 6085 = nand( 6080, 6083) 6143 = nand( 6138, 6141) 6201 = nand( 6196, 6199) 6953 = nand( 6948, 6951) 7011 = nand( 7006, 7009) 273 = or( 271, 272) 298 = or( 296, 297) 301 = or( 299, 300) 304 = or( 302, 303) 307 = or( 305, 306) 342 = nand( 4796, 4799) 346 = and( 3491, 3471) 349 = and( 3491, 3478) 352 = and( 3491, 3486) 355 = and( 3491, 3350) 4807 = not( 4801) 358 = nand( 4801, 4808) 4815 = not( 4809) 361 = nand( 4809, 4816) 4823 = not( 4817) 364 = nand( 4817, 4824) 4831 = not( 4825) 367 = nand( 4825, 4832) 1172 = or( 1170, 1171) 1175 = or( 1173, 1174) 3497 = not( 3491) 5051 = nand( 5049, 5050) 5139 = nand( 5137, 5138) 5501 = not( 5495) 5504 = nand( 5495, 5502) 5559 = not( 5553) 5562 = nand( 5553, 5560) 5621 = nand( 5619, 5620) 5709 = nand( 5707, 5708) 6087 = nand( 6085, 6086) 6145 = nand( 6143, 6144) 6203 = nand( 6201, 6202) 6297 = not( 6291) 6300 = nand( 6291, 6298) 6955 = nand( 6953, 6954) 7013 = nand( 7011, 7012) 7077 = not( 7071) 7080 = nand( 7071, 7078) 7165 = not( 7159) 7168 = nand( 7159, 7166) 344 = nand( 342, 343) 357 = nand( 4804, 4807) 360 = nand( 4812, 4815) 363 = nand( 4820, 4823) 366 = nand( 4828, 4831) 5173 = not( 5167) 422 = buff( 1172) 469 = buff( 1172) 419 = buff( 1175) 471 = buff( 1175) 5503 = nand( 5498, 5501) 5561 = nand( 5556, 5559) 6299 = nand( 6294, 6297) 7079 = nand( 7074, 7077) 7167 = nand( 7162, 7165) 345 = and( 3475, 3497) 348 = and( 3482, 3497) 351 = and( 3489, 3497) 354 = and( 3344, 3497) 359 = nand( 357, 358) 362 = nand( 360, 361) 365 = nand( 363, 364) 368 = nand( 366, 367) 5057 = not( 5051) 5060 = nand( 5051, 5058) 5145 = not( 5139) 5148 = nand( 5139, 5146) 5505 = nand( 5503, 5504) 5563 = nand( 5561, 5562) 5627 = not( 5621) 5630 = nand( 5621, 5628) 5715 = not( 5709) 5718 = nand( 5709, 5716) 6093 = not( 6087) 6096 = nand( 6087, 6094) 6151 = not( 6145) 6154 = nand( 6145, 6152) 6209 = not( 6203) 6212 = nand( 6203, 6210) 6301 = nand( 6299, 6300) 6961 = not( 6955) 6964 = nand( 6955, 6962) 7019 = not( 7013) 7022 = nand( 7013, 7020) 7081 = nand( 7079, 7080) 7169 = nand( 7167, 7168) 347 = or( 345, 346) 350 = or( 348, 349) 353 = or( 351, 352) 356 = or( 354, 355) 5059 = nand( 5054, 5057) 5147 = nand( 5142, 5145) 5629 = nand( 5624, 5627) 5717 = nand( 5712, 5715) 6095 = nand( 6090, 6093) 6153 = nand( 6148, 6151) 6211 = nand( 6206, 6209) 6963 = nand( 6958, 6961) 7021 = nand( 7016, 7019) 5061 = nand( 5059, 5060) 5149 = nand( 5147, 5148) 5511 = not( 5505) 5514 = nand( 5505, 5512) 5569 = not( 5563) 5572 = nand( 5563, 5570) 5631 = nand( 5629, 5630) 5719 = nand( 5717, 5718) 6097 = nand( 6095, 6096) 6155 = nand( 6153, 6154) 6213 = nand( 6211, 6212) 6307 = not( 6301) 6310 = nand( 6301, 6308) 6965 = nand( 6963, 6964) 7023 = nand( 7021, 7022) 7087 = not( 7081) 7090 = nand( 7081, 7088) 7175 = not( 7169) 7178 = nand( 7169, 7176) 5513 = nand( 5508, 5511) 5571 = nand( 5566, 5569) 6309 = nand( 6304, 6307) 7089 = nand( 7084, 7087) 7177 = nand( 7172, 7175) 5067 = not( 5061) 5070 = nand( 5061, 5068) 5155 = not( 5149) 5158 = nand( 5149, 5156) 5515 = nand( 5513, 5514) 5573 = nand( 5571, 5572) 5637 = not( 5631) 5640 = nand( 5631, 5638) 5725 = not( 5719) 5728 = nand( 5719, 5726) 6103 = not( 6097) 6106 = nand( 6097, 6104) 6161 = not( 6155) 6164 = nand( 6155, 6162) 6219 = not( 6213) 6222 = nand( 6213, 6220) 6311 = nand( 6309, 6310) 6971 = not( 6965) 6974 = nand( 6965, 6972) 7029 = not( 7023) 7032 = nand( 7023, 7030) 7091 = nand( 7089, 7090) 7179 = nand( 7177, 7178) 5069 = nand( 5064, 5067) 5157 = nand( 5152, 5155) 5639 = nand( 5634, 5637) 5727 = nand( 5722, 5725) 6105 = nand( 6100, 6103) 6163 = nand( 6158, 6161) 6221 = nand( 6216, 6219) 6973 = nand( 6968, 6971) 7031 = nand( 7026, 7029) 5521 = not( 5515) 1756 = nand( 5515, 5522) 5579 = not( 5573) 1761 = nand( 5573, 5580) 5071 = nand( 5069, 5070) 5159 = nand( 5157, 5158) 5641 = nand( 5639, 5640) 5729 = nand( 5727, 5728) 6107 = nand( 6105, 6106) 6165 = nand( 6163, 6164) 6223 = nand( 6221, 6222) 6317 = not( 6311) 6320 = nand( 6311, 6318) 6975 = nand( 6973, 6974) 7033 = nand( 7031, 7032) 7097 = not( 7091) 7100 = nand( 7091, 7098) 7185 = not( 7179) 7188 = nand( 7179, 7186) 1755 = nand( 5518, 5521) 1760 = nand( 5576, 5579) 6319 = nand( 6314, 6317) 7099 = nand( 7094, 7097) 7187 = nand( 7182, 7185) 1757 = nand( 1755, 1756) 1762 = nand( 1760, 1761) 6113 = not( 6107) 2818 = nand( 6107, 6114) 6171 = not( 6165) 2823 = nand( 6165, 6172) 6981 = not( 6975) 4058 = nand( 6975, 6982) 7039 = not( 7033) 4063 = nand( 7033, 7040) 5077 = not( 5071) 5080 = nand( 5071, 5078) 5165 = not( 5159) 5090 = nand( 5159, 5166) 5647 = not( 5641) 5650 = nand( 5641, 5648) 5735 = not( 5729) 5660 = nand( 5729, 5736) 6229 = not( 6223) 6232 = nand( 6223, 6230) 6321 = nand( 6319, 6320) 7101 = nand( 7099, 7100) 7189 = nand( 7187, 7188) 2817 = nand( 6110, 6113) 2822 = nand( 6168, 6171) 4057 = nand( 6978, 6981) 4062 = nand( 7036, 7039) 5079 = nand( 5074, 5077) 5089 = nand( 5162, 5165) 5649 = nand( 5644, 5647) 5659 = nand( 5732, 5735) 6231 = nand( 6226, 6229) 1782 = and( 1762, 1730, 1771) 1783 = and( 1757, 1726, 1771) 1784 = and( 1762, 1751, 1766) 1785 = and( 1757, 1754, 1766) 2819 = nand( 2817, 2818) 2824 = nand( 2822, 2823) 4059 = nand( 4057, 4058) 4064 = nand( 4062, 4063) 5081 = nand( 5079, 5080) 5091 = nand( 5089, 5090) 5651 = nand( 5649, 5650) 5661 = nand( 5659, 5660) 6233 = nand( 6231, 6232) 6327 = not( 6321) 6252 = nand( 6321, 6328) 7107 = not( 7101) 7110 = nand( 7101, 7108) 7195 = not( 7189) 7120 = nand( 7189, 7196) 5737 = or( 1782, 1783, 1784, 1785) 6251 = nand( 6324, 6327) 7109 = nand( 7104, 7107) 7119 = nand( 7192, 7195) 5087 = not( 5081) 985 = nand( 5081, 5088) 5097 = not( 5091) 988 = nand( 5091, 5098) 5657 = not( 5651) 1776 = nand( 5651, 5658) 5667 = not( 5661) 1779 = nand( 5661, 5668) 2844 = and( 2824, 2784, 2833) 2845 = and( 2819, 2780, 2833) 2846 = and( 2824, 2813, 2828) 2847 = and( 2819, 2816, 2828) 4083 = and( 4064, 4032, 4072) 4084 = and( 4059, 4028, 4072) 4085 = and( 4064, 4053, 4067) 4086 = and( 4059, 4056, 4067) 6239 = not( 6233) 6242 = nand( 6233, 6240) 6253 = nand( 6251, 6252) 7111 = nand( 7109, 7110) 7121 = nand( 7119, 7120) 984 = nand( 5084, 5087) 987 = nand( 5094, 5097) 1775 = nand( 5654, 5657) 1778 = nand( 5664, 5667) 5743 = not( 5737) 6241 = nand( 6236, 6239) 6329 = or( 2844, 2845, 2846, 2847) 7197 = or( 4083, 4084, 4085, 4086) 986 = nand( 984, 985) 989 = nand( 987, 988) 1777 = nand( 1775, 1776) 1780 = nand( 1778, 1779) 6259 = not( 6253) 2841 = nand( 6253, 6260) 7117 = not( 7111) 4077 = nand( 7111, 7118) 7127 = not( 7121) 4080 = nand( 7121, 7128) 6243 = nand( 6241, 6242) 990 = not( 989) 996 = and( 975, 986) 1781 = not( 1780) 1787 = and( 1766, 1777) 2840 = nand( 6256, 6259) 6335 = not( 6329) 4076 = nand( 7114, 7117) 4079 = nand( 7124, 7127) 7203 = not( 7197) 995 = and( 990, 980) 1786 = and( 1781, 1771) 6249 = not( 6243) 2838 = nand( 6243, 6250) 2842 = nand( 2840, 2841) 4078 = nand( 4076, 4077) 4081 = nand( 4079, 4080) 2837 = nand( 6246, 6249) 2843 = not( 2842) 4082 = not( 4081) 4088 = and( 4067, 4078) 5170 = or( 995, 996) 5740 = or( 1786, 1787) 2839 = nand( 2837, 2838) 2848 = and( 2843, 2833) 4087 = and( 4082, 4072) 1791 = nand( 5740, 5743) 1003 = nand( 5170, 5173) 5174 = not( 5170) 5744 = not( 5740) 2849 = and( 2828, 2839) 7200 = or( 4087, 4088) 1792 = nand( 5737, 5744) 1004 = nand( 5167, 5174) 6332 = or( 2848, 2849) 320 = nand( 1791, 1792) 337 = nand( 1003, 1004) 4092 = nand( 7200, 7203) 7204 = not( 7200) 321 = not( 320) 338 = not( 337) 4093 = nand( 7197, 7204) 2855 = nand( 6332, 6335) 6336 = not( 6332) 369 = nand( 4092, 4093) 2856 = nand( 6329, 6336) 370 = not( 369) 398 = nand( 2855, 2856) 399 = not( 398) |
Added c7552/c7552gate.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 |
/****************************************************************************
* *
* VERILOG VERSION of ORIGINAL NETLIST for c7552 *
* *
* *
* Generated by: Hakan Yalcin (hyalcin@cadence.com) *
* *
* Sep 16, 1998 *
* *
****************************************************************************/
module c7552g (
L213, L214, L215, L216, L209, L153, L154,
L155, L156, L157, L158, L159, L160, L151, L219,
L220, L221, L222, L223, L224, L225, L226, L217,
L231, L232, L233, L234, L235, L236, L237, L238,
L135, L144, L138, L147, L66, L50, L32, L35,
L47, L121, L94, L97, L118, L100, L124, L127,
L130, L103, L23, L26, L29, L41, L1486, L1480,
L106, L1469, L1462, L2256, L2253, L2247, L2239, L2236,
L2230, L2224, L2218, L2211, L4437, L4432, L4427, L4420,
L4415, L4410, L4405, L4400, L4394, L3749, L3743, L3737,
L3729, L3723, L3717, L3711, L3705, L88, L112, L87,
L111, L113, L110, L109, L86, L63, L64, L85,
L84, L83, L65, L62, L61, L60, L79, L80,
L81, L59, L78, L77, L56, L55, L54, L53,
L73, L75, L76, L74, L166, L167, L168, L169,
L173, L174, L175, L176, L177, L178, L179, L180,
L171, L189, L190, L191, L192, L193, L194, L195,
L196, L187, L200, L201, L202, L203, L204, L205,
L206, L207, L18, L12, L9, L4526, L89, L38,
L4528, L211, L212, L161, L227, L239, L229, L141,
L115, L44, L1459, L1496, L1492, L2208, L4393, L3701,
L3698, L114, L2204, L1455, L82, L58, L70, L69,
L170, L164, L165, L181, L197, L208, L198, L199,
L188, L172, L162, L186, L185, L182, L183, L230,
L218, L152, L210, L240, L228, L184, L150, L1,
L163, L15, L1197, L134, L133, L5, L57, L339,
L469, L471, L327, L330, L333, L336, L324,
L298, L301, L304, L307, L310, L313, L316, L319,
L295, L347, L350, L353, L356, L359, L362, L365,
L368, L344, L376, L379, L382, L385, L388, L391,
L394, L397, L373, L419, L422, L270, L246, L273,
L276, L258, L264, L249, L252, L338, L321, L370,
L399, L416, L414, L412, L418, L410, L408, L406,
L404, L440, L438, L442, L444, L446, L448, L436,
L480, L482, L484, L486, L488, L490, L492, L494,
L478, L524, L526, L528, L530, L532, L534, L536,
L538, L522, L544, L546, L548, L550, L552, L554,
L556, L558, L542, L450, L496, L540, L560, L402,
L289, L292, L279, L278, L2, L3, L432, L453,
L286, L341, L281, L284, L339o);
input
L213, L214, L215, L216, L209, L153, L154,
L155, L156, L157, L158, L159, L160, L151, L219,
L220, L221, L222, L223, L224, L225, L226, L217,
L231, L232, L233, L234, L235, L236, L237, L238,
L135, L144, L138, L147, L66, L50, L32, L35,
L47, L121, L94, L97, L118, L100, L124, L127,
L130, L103, L23, L26, L29, L41, L1486, L1480,
L106, L1469, L1462, L2256, L2253, L2247, L2239, L2236,
L2230, L2224, L2218, L2211, L4437, L4432, L4427, L4420,
L4415, L4410, L4405, L4400, L4394, L3749, L3743, L3737,
L3729, L3723, L3717, L3711, L3705, L88, L112, L87,
L111, L113, L110, L109, L86, L63, L64, L85,
L84, L83, L65, L62, L61, L60, L79, L80,
L81, L59, L78, L77, L56, L55, L54, L53,
L73, L75, L76, L74, L166, L167, L168, L169,
L173, L174, L175, L176, L177, L178, L179, L180,
L171, L189, L190, L191, L192, L193, L194, L195,
L196, L187, L200, L201, L202, L203, L204, L205,
L206, L207, L18, L12, L9, L4526, L89, L38,
L4528, L211, L212, L161, L227, L239, L229, L141,
L115, L44, L1459, L1496, L1492, L2208, L4393, L3701,
L3698, L114, L2204, L1455, L82, L58, L70, L69,
L170, L164, L165, L181, L197, L208, L198, L199,
L188, L172, L162, L186, L185, L182, L183, L230,
L218, L152, L210, L240, L228, L184, L150, L1,
L163, L15, L1197, L134, L133, L5, L57, L339;
output
L469, L471, L327, L330, L333, L336, L324,
L298, L301, L304, L307, L310, L313, L316, L319,
L295, L347, L350, L353, L356, L359, L362, L365,
L368, L344, L376, L379, L382, L385, L388, L391,
L394, L397, L373, L419, L422, L270, L246, L273,
L276, L258, L264, L249, L252, L338, L321, L370,
L399, L416, L414, L412, L418, L410, L408, L406,
L404, L440, L438, L442, L444, L446, L448, L436,
L480, L482, L484, L486, L488, L490, L492, L494,
L478, L524, L526, L528, L530, L532, L534, L536,
L538, L522, L544, L546, L548, L550, L552, L554,
L556, L558, L542, L450, L496, L540, L560, L402,
L289, L292, L279, L278, L2, L3, L432, L453,
L286, L341, L281, L284, L339o;
assign L339o = L339;
buffer U2 ( L1, L2 );
buffer U3 ( L1, L3 );
inv U4 ( L57, L400 );
and2 U5 ( L134, L133, L1184 );
buffer U6 ( L1459, L450 );
buffer U7 ( L1469, L448 );
buffer U8 ( L1480, L444 );
buffer U9 ( L1486, L442 );
buffer U10 ( L1492, L440 );
buffer U11 ( L1496, L438 );
and4 U12 ( L162, L172, L188, L199, L1501 );
buffer U13 ( L2208, L496 );
buffer U14 ( L2218, L494 );
buffer U15 ( L2224, L492 );
buffer U16 ( L2230, L490 );
buffer U17 ( L2236, L488 );
buffer U18 ( L2239, L486 );
buffer U19 ( L2247, L484 );
buffer U20 ( L2253, L482 );
buffer U21 ( L2256, L480 );
and4 U22 ( L150, L184, L228, L240, L2857 );
buffer U23 ( L3698, L560 );
buffer U24 ( L3701, L542 );
buffer U25 ( L3705, L558 );
buffer U26 ( L3711, L556 );
buffer U27 ( L3717, L554 );
buffer U28 ( L3723, L552 );
buffer U29 ( L3729, L550 );
buffer U30 ( L3737, L548 );
buffer U31 ( L3743, L546 );
buffer U32 ( L3749, L544 );
buffer U33 ( L4393, L540 );
buffer U34 ( L4400, L538 );
buffer U35 ( L4405, L536 );
buffer U36 ( L4410, L534 );
buffer U37 ( L4415, L532 );
buffer U38 ( L4420, L530 );
buffer U39 ( L4427, L528 );
buffer U40 ( L4432, L526 );
buffer U41 ( L4437, L524 );
and4 U42 ( L183, L182, L185, L186, L4442 );
and4 U43 ( L210, L152, L218, L230, L4514 );
inv U44 ( L15, L279 );
inv U45 ( L5, L401 );
buffer U46 ( L1, L573 );
inv U47 ( L5, L574 );
inv U48 ( L5, L575 );
inv U49 ( L2236, L1178 );
inv U50 ( L2253, L1186 );
inv U51 ( L2256, L1192 );
buffer U52 ( L38, L1198 );
buffer U53 ( L15, L1205 );
nand2 U54 ( L12, L9, L1206 );
nand2 U55 ( L12, L9, L1207 );
buffer U56 ( L38, L1210 );
inv U57 ( L1455, L1458 );
inv U58 ( L1459, L1461 );
buffer U59 ( L1462, L436 );
inv U60 ( L1462, L1464 );
inv U61 ( L1469, L1471 );
buffer U62 ( L106, L1475 );
inv U63 ( L1480, L1482 );
inv U64 ( L1486, L1488 );
inv U65 ( L1492, L1495 );
inv U66 ( L1496, L1499 );
inv U67 ( L106, L1500 );
buffer U68 ( L18, L1503 );
buffer U69 ( L18, L1512 );
and2 U70 ( L4528, L1492, L1518 );
buffer U71 ( L18, L1524 );
inv U72 ( L18, L1535 );
nand2 U73 ( L4528, L1496, L1541 );
inv U74 ( L2204, L2207 );
inv U75 ( L2208, L2210 );
buffer U76 ( L2211, L478 );
inv U77 ( L2211, L2213 );
inv U78 ( L2218, L2220 );
inv U79 ( L2224, L2226 );
inv U80 ( L2230, L2232 );
inv U81 ( L2236, L2238 );
inv U82 ( L2239, L2241 );
inv U83 ( L2247, L2249 );
inv U84 ( L2253, L2255 );
inv U85 ( L2256, L2258 );
buffer U86 ( L4526, L2828 );
inv U87 ( L3698, L3700 );
inv U88 ( L3701, L3703 );
inv U89 ( L3705, L3707 );
inv U90 ( L3711, L3713 );
inv U91 ( L3717, L3719 );
inv U92 ( L3723, L3725 );
inv U93 ( L3729, L3731 );
inv U94 ( L3737, L3739 );
inv U95 ( L3743, L3745 );
inv U96 ( L3749, L3751 );
inv U97 ( L4393, L4121 );
buffer U98 ( L4394, L522 );
inv U99 ( L4394, L4396 );
inv U100 ( L4400, L4402 );
inv U101 ( L4405, L4407 );
inv U102 ( L4410, L4412 );
inv U103 ( L4415, L4417 );
inv U104 ( L4420, L4422 );
inv U105 ( L4427, L4429 );
inv U106 ( L4432, L4434 );
inv U107 ( L4437, L4439 );
buffer U108 ( L4526, L4833 );
nand2 U109 ( L400, L401, L402 );
inv U110 ( L2857, L404 );
inv U111 ( L4514, L406 );
inv U112 ( L4442, L408 );
inv U113 ( L1501, L410 );
and2 U114 ( L2857, L4514, L2876 );
and2 U115 ( L4442, L1501, L2878 );
buffer U116 ( L573, L432 );
buffer U117 ( L1475, L446 );
inv U118 ( L1518, L1519 );
and2 U119 ( L4528, L1458, L2871 );
nand2 U120 ( L4528, L2207, L2883 );
and2 U121 ( L1184, L575, L280 );
nand2 U122 ( L1197, L574, L284 );
inv U123 ( L1205, L286 );
nand2 U124 ( L1197, L574, L289 );
nand2 U125 ( L1184, L575, L292 );
inv U126 ( L1205, L341 );
inv U127 ( L4833, L4839 );
buffer U128 ( L573, L572 );
buffer U129 ( L1206, L581 );
buffer U130 ( L1512, L587 );
buffer U131 ( L1206, L601 );
buffer U132 ( L1512, L606 );
buffer U133 ( L1206, L650 );
buffer U134 ( L1512, L657 );
buffer U135 ( L1207, L671 );
buffer U136 ( L1503, L678 );
and2 U137 ( L1541, L1198, L777 );
and2 U138 ( L1541, L1198, L1115 );
buffer U139 ( L1512, L1336 );
buffer U140 ( L1503, L1350 );
inv U141 ( L1475, L1477 );
inv U142 ( L1503, L1507 );
inv U143 ( L1512, L1514 );
inv U144 ( L1524, L1530 );
buffer U145 ( L1535, L2259 );
inv U146 ( L2828, L2833 );
inv U147 ( L2871, L2872 );
buffer U148 ( L1207, L2886 );
buffer U149 ( L1503, L2892 );
buffer U150 ( L1207, L2905 );
buffer U151 ( L1503, L2909 );
buffer U152 ( L1524, L3622 );
buffer U153 ( L1524, L3635 );
buffer U154 ( L1535, L3755 );
buffer U155 ( L1524, L4640 );
buffer U156 ( L1524, L4653 );
buffer U157 ( L1541, L4873 );
buffer U158 ( L1198, L4876 );
buffer U159 ( L1488, L4881 );
buffer U160 ( L1482, L4889 );
buffer U161 ( L1471, L4905 );
buffer U162 ( L1198, L4916 );
buffer U163 ( L1464, L4921 );
buffer U164 ( L1541, L5175 );
buffer U165 ( L1198, L5178 );
buffer U166 ( L1198, L5186 );
buffer U167 ( L1488, L5191 );
buffer U168 ( L1482, L5199 );
buffer U169 ( L1471, L5215 );
buffer U170 ( L1464, L5223 );
buffer U171 ( L1192, L5393 );
buffer U172 ( L1186, L5401 );
buffer U173 ( L2249, L5409 );
buffer U174 ( L1178, L5417 );
buffer U175 ( L2232, L5425 );
buffer U176 ( L2226, L5433 );
buffer U177 ( L2220, L5441 );
buffer U178 ( L2241, L5449 );
buffer U179 ( L2213, L5457 );
buffer U180 ( L1192, L5745 );
buffer U181 ( L1186, L5753 );
buffer U182 ( L2249, L5761 );
buffer U183 ( L2241, L5769 );
buffer U184 ( L1178, L5777 );
buffer U185 ( L2232, L5785 );
buffer U186 ( L2226, L5793 );
buffer U187 ( L2220, L5801 );
buffer U188 ( L2213, L5809 );
buffer U189 ( L3751, L5865 );
buffer U190 ( L3745, L5873 );
buffer U191 ( L3739, L5881 );
buffer U192 ( L3731, L5889 );
buffer U193 ( L3725, L5897 );
buffer U194 ( L3719, L5905 );
buffer U195 ( L3713, L5913 );
buffer U196 ( L3707, L5921 );
buffer U197 ( L3751, L5985 );
buffer U198 ( L3745, L5993 );
buffer U199 ( L3739, L6001 );
buffer U200 ( L3725, L6009 );
buffer U201 ( L3719, L6017 );
buffer U202 ( L3713, L6025 );
buffer U203 ( L3707, L6033 );
buffer U204 ( L3731, L6041 );
buffer U205 ( L1210, L6514 );
buffer U206 ( L1210, L6554 );
buffer U207 ( L4439, L6567 );
buffer U208 ( L4434, L6575 );
buffer U209 ( L4429, L6583 );
buffer U210 ( L4422, L6591 );
buffer U211 ( L4417, L6599 );
buffer U212 ( L4412, L6607 );
buffer U213 ( L4407, L6615 );
buffer U214 ( L4402, L6623 );
buffer U215 ( L4396, L6631 );
buffer U216 ( L4439, L6853 );
buffer U217 ( L4434, L6861 );
buffer U218 ( L4429, L6869 );
buffer U219 ( L4417, L6877 );
buffer U220 ( L4412, L6885 );
buffer U221 ( L4407, L6893 );
buffer U222 ( L4402, L6901 );
buffer U223 ( L4422, L6909 );
buffer U224 ( L4396, L6917 );
inv U225 ( L280, L281 );
buffer U226 ( L572, L453 );
and2 U227 ( L1519, L1198, L784 );
and2 U228 ( L1198, L1519, L1014 );
and2 U229 ( L2883, L1210, L3221 );
buffer U230 ( L1519, L4913 );
nor2 U231 ( L1519, L1198, L4929 );
buffer U232 ( L1519, L5183 );
nor2 U233 ( L1198, L1519, L5231 );
buffer U234 ( L2883, L6511 );
and2 U235 ( L163, L572, L278 );
and2 U236 ( L170, L587, L615 );
inv U237 ( L587, L594 );
inv U238 ( L606, L611 );
and2 U239 ( L169, L587, L617 );
and2 U240 ( L168, L587, L619 );
and2 U241 ( L167, L587, L621 );
and2 U242 ( L166, L606, L623 );
and2 U243 ( L165, L606, L625 );
and2 U244 ( L164, L606, L627 );
inv U245 ( L657, L664 );
inv U246 ( L678, L685 );
and2 U247 ( L177, L657, L691 );
and2 U248 ( L176, L657, L693 );
and2 U249 ( L175, L657, L695 );
and2 U250 ( L174, L657, L697 );
and2 U251 ( L173, L657, L699 );
and2 U252 ( L157, L678, L701 );
and2 U253 ( L156, L678, L703 );
and2 U254 ( L155, L678, L705 );
and2 U255 ( L154, L678, L707 );
and2 U256 ( L153, L678, L709 );
inv U257 ( L4873, L4879 );
inv U258 ( L4876, L4880 );
inv U259 ( L4881, L4887 );
inv U260 ( L4889, L4895 );
inv U261 ( L4905, L4911 );
inv U262 ( L4916, L4920 );
inv U263 ( L4921, L4927 );
inv U264 ( L5175, L5181 );
inv U265 ( L5178, L5182 );
inv U266 ( L5186, L5190 );
inv U267 ( L5191, L5197 );
inv U268 ( L5199, L5205 );
inv U269 ( L5215, L5221 );
inv U270 ( L5223, L5229 );
inv U271 ( L1336, L1343 );
inv U272 ( L1350, L1357 );
and2 U273 ( L181, L1336, L1364 );
and2 U274 ( L171, L1336, L1366 );
and2 U275 ( L180, L1336, L1368 );
and2 U276 ( L179, L1336, L1370 );
and2 U277 ( L178, L1336, L1372 );
and2 U278 ( L161, L1350, L1374 );
and2 U279 ( L151, L1350, L1376 );
and2 U280 ( L160, L1350, L1378 );
and2 U281 ( L159, L1350, L1380 );
and2 U282 ( L158, L1350, L1382 );
inv U283 ( L5393, L5399 );
inv U284 ( L5401, L5407 );
inv U285 ( L5409, L5415 );
inv U286 ( L5417, L5423 );
inv U287 ( L5425, L5431 );
inv U288 ( L5433, L5439 );
inv U289 ( L5441, L5447 );
inv U290 ( L5449, L5455 );
inv U291 ( L5457, L5463 );
inv U292 ( L5745, L5751 );
inv U293 ( L5753, L5759 );
inv U294 ( L5761, L5767 );
inv U295 ( L5769, L5775 );
inv U296 ( L5777, L5783 );
inv U297 ( L5785, L5791 );
inv U298 ( L5793, L5799 );
inv U299 ( L5801, L5807 );
inv U300 ( L5809, L5815 );
buffer U301 ( L1514, L2019 );
buffer U302 ( L1507, L2032 );
buffer U303 ( L1514, L2117 );
buffer U304 ( L1507, L2130 );
inv U305 ( L2259, L2266 );
buffer U306 ( L1507, L2272 );
and2 U307 ( L44, L2259, L2286 );
and2 U308 ( L41, L2259, L2288 );
and2 U309 ( L29, L2259, L2290 );
and2 U310 ( L26, L2259, L2292 );
and2 U311 ( L23, L2259, L2294 );
inv U312 ( L5865, L5871 );
inv U313 ( L5873, L5879 );
inv U314 ( L5881, L5887 );
inv U315 ( L5889, L5895 );
inv U316 ( L5897, L5903 );
inv U317 ( L5905, L5911 );
inv U318 ( L5913, L5919 );
inv U319 ( L5921, L5927 );
inv U320 ( L5985, L5991 );
inv U321 ( L5993, L5999 );
inv U322 ( L6001, L6007 );
inv U323 ( L6009, L6015 );
inv U324 ( L6017, L6023 );
inv U325 ( L6025, L6031 );
inv U326 ( L6033, L6039 );
inv U327 ( L6041, L6047 );
inv U328 ( L2892, L2899 );
inv U329 ( L2909, L2914 );
and2 U330 ( L209, L2892, L2919 );
and2 U331 ( L216, L2892, L2921 );
and2 U332 ( L215, L2892, L2923 );
and2 U333 ( L214, L2892, L2925 );
and2 U334 ( L213, L2909, L2927 );
and2 U335 ( L212, L2909, L2929 );
and2 U336 ( L211, L2909, L2931 );
inv U337 ( L6514, L6518 );
and2 U338 ( L2872, L1210, L3173 );
inv U339 ( L6554, L6558 );
inv U340 ( L6567, L6573 );
inv U341 ( L6575, L6581 );
inv U342 ( L6583, L6589 );
inv U343 ( L6591, L6597 );
inv U344 ( L6599, L6605 );
inv U345 ( L6607, L6613 );
inv U346 ( L6615, L6621 );
inv U347 ( L6623, L6629 );
inv U348 ( L6631, L6637 );
inv U349 ( L3622, L3629 );
inv U350 ( L3635, L3642 );
and2 U351 ( L1461, L3622, L3649 );
and2 U352 ( L1464, L3622, L3651 );
and2 U353 ( L1471, L3622, L3653 );
and2 U354 ( L1500, L3622, L3655 );
and2 U355 ( L1482, L3622, L3657 );
and2 U356 ( L1488, L3635, L3659 );
and2 U357 ( L1495, L3635, L3661 );
and2 U358 ( L1499, L3635, L3663 );
inv U359 ( L3755, L3762 );
buffer U360 ( L1507, L3768 );
and2 U361 ( L47, L3755, L3782 );
and2 U362 ( L35, L3755, L3784 );
and2 U363 ( L32, L3755, L3786 );
and2 U364 ( L50, L3755, L3788 );
and2 U365 ( L66, L3755, L3790 );
inv U366 ( L6853, L6859 );
inv U367 ( L6861, L6867 );
inv U368 ( L6869, L6875 );
inv U369 ( L6877, L6883 );
inv U370 ( L6885, L6891 );
inv U371 ( L6893, L6899 );
inv U372 ( L6901, L6907 );
inv U373 ( L6909, L6915 );
inv U374 ( L6917, L6923 );
buffer U375 ( L1530, L4094 );
buffer U376 ( L1530, L4107 );
buffer U377 ( L1530, L4444 );
buffer U378 ( L1530, L4457 );
inv U379 ( L4640, L4647 );
inv U380 ( L4653, L4660 );
and2 U381 ( L2210, L4640, L4667 );
and2 U382 ( L2213, L4640, L4669 );
and2 U383 ( L2220, L4640, L4671 );
and2 U384 ( L2226, L4640, L4673 );
and2 U385 ( L2232, L4640, L4675 );
and2 U386 ( L2238, L4653, L4677 );
and2 U387 ( L2241, L4653, L4679 );
and2 U388 ( L2249, L4653, L4681 );
and2 U389 ( L2255, L4653, L4683 );
and2 U390 ( L2258, L4653, L4685 );
buffer U391 ( L1477, L4897 );
buffer U392 ( L1477, L5207 );
buffer U393 ( L2872, L6551 );
nand2 U394 ( L4876, L4879, L763 );
nand2 U395 ( L4873, L4880, L764 );
inv U396 ( L4913, L4919 );
nand2 U397 ( L4913, L4920, L886 );
nand2 U398 ( L5178, L5181, L1005 );
nand2 U399 ( L5175, L5182, L1006 );
inv U400 ( L5183, L5189 );
nand2 U401 ( L5183, L5190, L1018 );
inv U402 ( L5231, L5237 );
inv U403 ( L6511, L6517 );
nand2 U404 ( L6511, L6518, L3169 );
inv U405 ( L4929, L4935 );
buffer U406 ( L784, L4970 );
buffer U407 ( L1014, L5239 );
or2 U408 ( L594, L615, L577 );
or2 U409 ( L594, L587, L616 );
or2 U410 ( L594, L617, L618 );
or2 U411 ( L594, L619, L620 );
or2 U412 ( L594, L621, L622 );
or2 U413 ( L611, L623, L624 );
or2 U414 ( L611, L625, L626 );
or2 U415 ( L611, L627, L628 );
or2 U416 ( L664, L691, L692 );
or2 U417 ( L664, L693, L694 );
or2 U418 ( L664, L695, L696 );
or2 U419 ( L664, L697, L698 );
or2 U420 ( L664, L699, L700 );
or2 U421 ( L685, L701, L702 );
or2 U422 ( L685, L703, L704 );
or2 U423 ( L685, L705, L706 );
or2 U424 ( L685, L707, L708 );
or2 U425 ( L685, L709, L710 );
nand2 U426 ( L763, L764, L765 );
inv U427 ( L4897, L4903 );
nand2 U428 ( L4916, L4919, L885 );
nand2 U429 ( L1005, L1006, L1007 );
nand2 U430 ( L5186, L5189, L1017 );
inv U431 ( L5207, L5213 );
and2 U432 ( L141, L1343, L1363 );
and2 U433 ( L147, L1343, L1365 );
and2 U434 ( L138, L1343, L1367 );
and2 U435 ( L144, L1343, L1369 );
and2 U436 ( L135, L1343, L1371 );
and2 U437 ( L141, L1357, L1373 );
and2 U438 ( L147, L1357, L1375 );
and2 U439 ( L138, L1357, L1377 );
and2 U440 ( L144, L1357, L1379 );
and2 U441 ( L135, L1357, L1381 );
inv U442 ( L2019, L2026 );
inv U443 ( L2032, L2039 );
and2 U444 ( L103, L2019, L2046 );
and2 U445 ( L130, L2019, L2048 );
and2 U446 ( L127, L2019, L2050 );
and2 U447 ( L124, L2019, L2052 );
and2 U448 ( L100, L2019, L2054 );
and2 U449 ( L103, L2032, L2056 );
and2 U450 ( L130, L2032, L2058 );
and2 U451 ( L127, L2032, L2060 );
and2 U452 ( L124, L2032, L2062 );
and2 U453 ( L100, L2032, L2064 );
inv U454 ( L2117, L2124 );
inv U455 ( L2130, L2137 );
and2 U456 ( L115, L2117, L2144 );
and2 U457 ( L118, L2117, L2146 );
and2 U458 ( L97, L2117, L2148 );
and2 U459 ( L94, L2117, L2150 );
and2 U460 ( L121, L2117, L2152 );
and2 U461 ( L115, L2130, L2154 );
and2 U462 ( L118, L2130, L2156 );
and2 U463 ( L97, L2130, L2158 );
and2 U464 ( L94, L2130, L2160 );
and2 U465 ( L121, L2130, L2162 );
inv U466 ( L2272, L2279 );
and2 U467 ( L208, L2266, L2285 );
and2 U468 ( L198, L2266, L2287 );
and2 U469 ( L207, L2266, L2289 );
and2 U470 ( L206, L2266, L2291 );
and2 U471 ( L205, L2266, L2293 );
and2 U472 ( L44, L2272, L2296 );
and2 U473 ( L41, L2272, L2298 );
and2 U474 ( L29, L2272, L2300 );
and2 U475 ( L26, L2272, L2302 );
and2 U476 ( L23, L2272, L2304 );
or2 U477 ( L2899, L2892, L2918 );
or2 U478 ( L2899, L2919, L2920 );
or2 U479 ( L2899, L2921, L2922 );
or2 U480 ( L2899, L2923, L2924 );
or2 U481 ( L2899, L2925, L2926 );
or2 U482 ( L2914, L2927, L2928 );
or2 U483 ( L2914, L2929, L2930 );
or2 U484 ( L2914, L2931, L2932 );
nand2 U485 ( L6514, L6517, L3168 );
inv U486 ( L6551, L6557 );
nand2 U487 ( L6551, L6558, L3211 );
and2 U488 ( L114, L3629, L3648 );
and2 U489 ( L113, L3629, L3650 );
and2 U490 ( L111, L3629, L3652 );
and2 U491 ( L87, L3629, L3654 );
and2 U492 ( L112, L3629, L3656 );
and2 U493 ( L88, L3642, L3658 );
and2 U494 ( L1455, L3642, L3660 );
and2 U495 ( L2204, L3642, L3662 );
and2 U496 ( L3703, L3642, L3665 );
and2 U497 ( L70, L3642, L3666 );
inv U498 ( L3768, L3775 );
and2 U499 ( L193, L3762, L3781 );
and2 U500 ( L192, L3762, L3783 );
and2 U501 ( L191, L3762, L3785 );
and2 U502 ( L190, L3762, L3787 );
and2 U503 ( L189, L3762, L3789 );
and2 U504 ( L47, L3768, L3792 );
and2 U505 ( L35, L3768, L3794 );
and2 U506 ( L32, L3768, L3796 );
and2 U507 ( L50, L3768, L3798 );
and2 U508 ( L66, L3768, L3800 );
inv U509 ( L4094, L4101 );
inv U510 ( L4107, L4114 );
and2 U511 ( L58, L4094, L4123 );
and2 U512 ( L77, L4094, L4126 );
and2 U513 ( L78, L4094, L4129 );
and2 U514 ( L59, L4094, L4132 );
and2 U515 ( L81, L4094, L4135 );
and2 U516 ( L80, L4107, L4138 );
and2 U517 ( L79, L4107, L4141 );
and2 U518 ( L60, L4107, L4144 );
and2 U519 ( L61, L4107, L4147 );
and2 U520 ( L62, L4107, L4150 );
inv U521 ( L4444, L4451 );
inv U522 ( L4457, L4464 );
and2 U523 ( L69, L4444, L4471 );
and2 U524 ( L70, L4444, L4473 );
and2 U525 ( L74, L4444, L4475 );
and2 U526 ( L76, L4444, L4477 );
and2 U527 ( L75, L4444, L4479 );
and2 U528 ( L73, L4457, L4481 );
and2 U529 ( L53, L4457, L4483 );
and2 U530 ( L54, L4457, L4485 );
and2 U531 ( L55, L4457, L4487 );
and2 U532 ( L56, L4457, L4489 );
and2 U533 ( L82, L4647, L4666 );
and2 U534 ( L65, L4647, L4668 );
and2 U535 ( L83, L4647, L4670 );
and2 U536 ( L84, L4647, L4672 );
and2 U537 ( L85, L4647, L4674 );
and2 U538 ( L64, L4660, L4676 );
and2 U539 ( L63, L4660, L4678 );
and2 U540 ( L86, L4660, L4680 );
and2 U541 ( L109, L4660, L4682 );
and2 U542 ( L110, L4660, L4684 );
and2 U543 ( L577, L581, L579 );
and2 U544 ( L616, L581, L629 );
and2 U545 ( L618, L581, L633 );
and2 U546 ( L620, L581, L637 );
and2 U547 ( L622, L581, L641 );
and2 U548 ( L624, L601, L645 );
and2 U549 ( L692, L650, L711 );
and2 U550 ( L694, L650, L715 );
and2 U551 ( L696, L650, L719 );
and2 U552 ( L698, L650, L723 );
and2 U553 ( L700, L650, L727 );
and2 U554 ( L702, L671, L731 );
and2 U555 ( L704, L671, L737 );
and2 U556 ( L706, L671, L745 );
and2 U557 ( L708, L671, L751 );
and2 U558 ( L710, L671, L757 );
nand2 U559 ( L885, L886, L887 );
nand2 U560 ( L1017, L1018, L1019 );
inv U561 ( L5239, L5245 );
or2 U562 ( L1365, L1366, L1383 );
or2 U563 ( L1367, L1368, L1387 );
or2 U564 ( L1369, L1370, L1391 );
or2 U565 ( L1371, L1372, L1395 );
or2 U566 ( L1375, L1376, L1399 );
or2 U567 ( L1377, L1378, L1406 );
or2 U568 ( L1379, L1380, L1412 );
or2 U569 ( L1381, L1382, L1418 );
or2 U570 ( L2287, L2288, L2305 );
or2 U571 ( L2289, L2290, L2308 );
or2 U572 ( L2291, L2292, L2312 );
or2 U573 ( L2293, L2294, L2316 );
and2 U574 ( L2920, L2886, L2933 );
and2 U575 ( L2922, L2886, L2938 );
and2 U576 ( L2924, L2886, L2942 );
and2 U577 ( L2926, L2886, L2946 );
and2 U578 ( L2928, L2905, L2950 );
nand2 U579 ( L3168, L3169, L3170 );
nand2 U580 ( L6554, L6557, L3210 );
or2 U581 ( L3650, L3651, L3667 );
or2 U582 ( L3652, L3653, L3670 );
or2 U583 ( L3654, L3655, L3673 );
or2 U584 ( L3656, L3657, L3676 );
or2 U585 ( L3658, L3659, L3679 );
or2 U586 ( L3665, L3635, L3682 );
or2 U587 ( L3666, L3635, L3686 );
or2 U588 ( L3781, L3782, L3801 );
or2 U589 ( L3783, L3784, L3804 );
or2 U590 ( L3785, L3786, L3807 );
or2 U591 ( L3787, L3788, L3810 );
or2 U592 ( L3789, L3790, L3813 );
and2 U593 ( L2918, L2886, L4525 );
or2 U594 ( L4668, L4669, L4686 );
or2 U595 ( L4670, L4671, L4689 );
or2 U596 ( L4672, L4673, L4692 );
or2 U597 ( L4674, L4675, L4695 );
or2 U598 ( L4676, L4677, L4698 );
or2 U599 ( L4678, L4679, L4701 );
or2 U600 ( L4680, L4681, L4704 );
or2 U601 ( L4682, L4683, L4707 );
or2 U602 ( L4684, L4685, L4710 );
inv U603 ( L4970, L4976 );
and2 U604 ( L2932, L2905, L5271 );
and2 U605 ( L2930, L2905, L5274 );
and2 U606 ( L628, L601, L5305 );
and2 U607 ( L626, L601, L5308 );
or2 U608 ( L1373, L1374, L5318 );
or2 U609 ( L3648, L3649, L6690 );
or2 U610 ( L3662, L3663, L6711 );
or2 U611 ( L3660, L3661, L6714 );
or2 U612 ( L2285, L2286, L7252 );
or2 U613 ( L1363, L1364, L7296 );
or2 U614 ( L4666, L4667, L7466 );
and2 U615 ( L765, L784, L907 );
and2 U616 ( L765, L784, L913 );
and2 U617 ( L765, L784, L915 );
and2 U618 ( L765, L784, L916 );
and2 U619 ( L1007, L1014, L1116 );
and2 U620 ( L204, L2026, L2045 );
and2 U621 ( L203, L2026, L2047 );
and2 U622 ( L202, L2026, L2049 );
and2 U623 ( L201, L2026, L2051 );
and2 U624 ( L200, L2026, L2053 );
and2 U625 ( L235, L2039, L2055 );
and2 U626 ( L234, L2039, L2057 );
and2 U627 ( L233, L2039, L2059 );
and2 U628 ( L232, L2039, L2061 );
and2 U629 ( L231, L2039, L2063 );
and2 U630 ( L197, L2124, L2143 );
and2 U631 ( L187, L2124, L2145 );
and2 U632 ( L196, L2124, L2147 );
and2 U633 ( L195, L2124, L2149 );
and2 U634 ( L194, L2124, L2151 );
and2 U635 ( L227, L2137, L2153 );
and2 U636 ( L217, L2137, L2155 );
and2 U637 ( L226, L2137, L2157 );
and2 U638 ( L225, L2137, L2159 );
and2 U639 ( L224, L2137, L2161 );
and2 U640 ( L239, L2279, L2295 );
and2 U641 ( L229, L2279, L2297 );
and2 U642 ( L238, L2279, L2299 );
and2 U643 ( L237, L2279, L2301 );
and2 U644 ( L236, L2279, L2303 );
nand2 U645 ( L3210, L3211, L3212 );
and2 U646 ( L223, L3775, L3791 );
and2 U647 ( L222, L3775, L3793 );
and2 U648 ( L221, L3775, L3795 );
and2 U649 ( L220, L3775, L3797 );
and2 U650 ( L219, L3775, L3799 );
and2 U651 ( L4121, L4101, L4122 );
and2 U652 ( L4396, L4101, L4125 );
and2 U653 ( L4402, L4101, L4128 );
and2 U654 ( L4407, L4101, L4131 );
and2 U655 ( L4412, L4101, L4134 );
and2 U656 ( L4417, L4114, L4137 );
and2 U657 ( L4422, L4114, L4140 );
and2 U658 ( L4429, L4114, L4143 );
and2 U659 ( L4434, L4114, L4146 );
and2 U660 ( L4439, L4114, L4149 );
and2 U661 ( L3700, L4451, L4470 );
and2 U662 ( L3703, L4451, L4472 );
and2 U663 ( L3707, L4451, L4474 );
and2 U664 ( L3713, L4451, L4476 );
and2 U665 ( L3719, L4451, L4478 );
and2 U666 ( L3725, L4464, L4480 );
and2 U667 ( L3731, L4464, L4482 );
and2 U668 ( L3739, L4464, L4484 );
and2 U669 ( L3745, L4464, L4486 );
and2 U670 ( L3751, L4464, L4488 );
buffer U671 ( L765, L4962 );
buffer U672 ( L765, L5003 );
buffer U673 ( L1007, L5234 );
buffer U674 ( L1007, L5242 );
inv U675 ( L4525, L5250 );
inv U676 ( L579, L5284 );
and2 U677 ( L1488, L2950, L802 );
and2 U678 ( L1482, L2946, L821 );
and2 U679 ( L1477, L2942, L845 );
and2 U680 ( L1471, L2938, L868 );
and2 U681 ( L1464, L2933, L877 );
and2 U682 ( L887, L765, L902 );
or2 U683 ( L777, L907, L908 );
and2 U684 ( L887, L765, L914 );
or2 U685 ( L777, L916, L917 );
and2 U686 ( L887, L765, L953 );
inv U687 ( L1019, L1023 );
and2 U688 ( L1488, L2950, L1035 );
and2 U689 ( L1482, L2946, L1050 );
and2 U690 ( L1477, L2942, L1068 );
and2 U691 ( L1471, L2938, L1086 );
and2 U692 ( L1464, L2933, L1102 );
and2 U693 ( L1019, L1007, L1108 );
or2 U694 ( L1115, L1116, L1117 );
inv U695 ( L5318, L5322 );
and2 U696 ( L1192, L757, L1553 );
and2 U697 ( L1186, L751, L1567 );
and2 U698 ( L2249, L745, L1584 );
and2 U699 ( L2241, L737, L1590 );
and2 U700 ( L1178, L731, L1606 );
and2 U701 ( L2232, L1418, L1624 );
and2 U702 ( L2226, L1412, L1647 );
and2 U703 ( L2220, L1406, L1669 );
and2 U704 ( L2213, L1399, L1677 );
and2 U705 ( L1192, L757, L1802 );
and2 U706 ( L1186, L751, L1816 );
and2 U707 ( L2249, L745, L1834 );
and2 U708 ( L737, L2241, L1841 );
and2 U709 ( L1178, L731, L1866 );
and2 U710 ( L2232, L1418, L1880 );
and2 U711 ( L2226, L1412, L1897 );
and2 U712 ( L2220, L1406, L1914 );
and2 U713 ( L2213, L1399, L1929 );
or2 U714 ( L2045, L2046, L2065 );
or2 U715 ( L2047, L2048, L2069 );
or2 U716 ( L2049, L2050, L2073 );
or2 U717 ( L2051, L2052, L2077 );
or2 U718 ( L2053, L2054, L2081 );
or2 U719 ( L2055, L2056, L2085 );
or2 U720 ( L2057, L2058, L2091 );
or2 U721 ( L2059, L2060, L2099 );
or2 U722 ( L2061, L2062, L2105 );
or2 U723 ( L2063, L2064, L2111 );
or2 U724 ( L2145, L2146, L2163 );
or2 U725 ( L2147, L2148, L2167 );
or2 U726 ( L2149, L2150, L2171 );
or2 U727 ( L2151, L2152, L2175 );
or2 U728 ( L2155, L2156, L2179 );
or2 U729 ( L2157, L2158, L2186 );
or2 U730 ( L2159, L2160, L2192 );
or2 U731 ( L2161, L2162, L2198 );
or2 U732 ( L2297, L2298, L2320 );
or2 U733 ( L2299, L2300, L2323 );
or2 U734 ( L2301, L2302, L2329 );
or2 U735 ( L2303, L2304, L2335 );
and2 U736 ( L4710, L727, L2962 );
and2 U737 ( L4707, L723, L2970 );
and2 U738 ( L4704, L719, L2977 );
and2 U739 ( L4701, L715, L2979 );
and2 U740 ( L4698, L711, L2989 );
and2 U741 ( L4695, L1395, L2998 );
and2 U742 ( L4692, L1391, L3006 );
and2 U743 ( L4689, L1387, L3013 );
and2 U744 ( L4686, L1383, L3015 );
and2 U745 ( L3679, L645, L3183 );
and2 U746 ( L3676, L641, L3192 );
and2 U747 ( L3673, L637, L3200 );
and2 U748 ( L3670, L633, L3207 );
and2 U749 ( L3667, L629, L3209 );
and2 U750 ( L3212, L3170, L3216 );
and2 U751 ( L3170, L3173, L3222 );
inv U752 ( L6690, L6694 );
and2 U753 ( L1535, L2305, L3695 );
or2 U754 ( L3791, L3792, L3816 );
or2 U755 ( L3793, L3794, L3821 );
or2 U756 ( L3795, L3796, L3828 );
or2 U757 ( L3797, L3798, L3833 );
or2 U758 ( L3799, L3800, L3838 );
or2 U759 ( L4125, L4126, L4151 );
or2 U760 ( L4128, L4129, L4154 );
or2 U761 ( L4131, L4132, L4157 );
or2 U762 ( L4134, L4135, L4160 );
or2 U763 ( L4137, L4138, L4163 );
or2 U764 ( L4140, L4141, L4166 );
or2 U765 ( L4143, L4144, L4169 );
or2 U766 ( L4146, L4147, L4172 );
or2 U767 ( L4149, L4150, L4175 );
inv U768 ( L7252, L7256 );
inv U769 ( L7296, L7300 );
or2 U770 ( L4474, L4475, L4490 );
or2 U771 ( L4476, L4477, L4493 );
or2 U772 ( L4478, L4479, L4496 );
or2 U773 ( L4480, L4481, L4499 );
or2 U774 ( L4482, L4483, L4502 );
or2 U775 ( L4484, L4485, L4505 );
or2 U776 ( L4486, L4487, L4508 );
or2 U777 ( L4488, L4489, L4511 );
inv U778 ( L7466, L7470 );
buffer U779 ( L2950, L4884 );
buffer U780 ( L2946, L4892 );
buffer U781 ( L2942, L4900 );
buffer U782 ( L2938, L4908 );
buffer U783 ( L2933, L4924 );
buffer U784 ( L887, L4952 );
nor2 U785 ( L777, L915, L4983 );
buffer U786 ( L887, L4993 );
nor2 U787 ( L1464, L2933, L5011 );
buffer U788 ( L2950, L5194 );
buffer U789 ( L2946, L5202 );
buffer U790 ( L2942, L5210 );
buffer U791 ( L2938, L5218 );
buffer U792 ( L2933, L5226 );
buffer U793 ( L2933, L5247 );
buffer U794 ( L2942, L5255 );
buffer U795 ( L2938, L5258 );
buffer U796 ( L2950, L5263 );
buffer U797 ( L2946, L5266 );
inv U798 ( L5271, L5277 );
inv U799 ( L5274, L5278 );
buffer U800 ( L629, L5281 );
buffer U801 ( L637, L5289 );
buffer U802 ( L633, L5292 );
buffer U803 ( L645, L5297 );
buffer U804 ( L641, L5300 );
inv U805 ( L5305, L5311 );
inv U806 ( L5308, L5312 );
buffer U807 ( L1399, L5315 );
buffer U808 ( L1412, L5323 );
buffer U809 ( L1406, L5326 );
buffer U810 ( L731, L5331 );
buffer U811 ( L1418, L5334 );
buffer U812 ( L745, L5339 );
buffer U813 ( L737, L5342 );
buffer U814 ( L757, L5349 );
buffer U815 ( L751, L5352 );
buffer U816 ( L757, L5396 );
buffer U817 ( L751, L5404 );
buffer U818 ( L745, L5412 );
buffer U819 ( L731, L5420 );
buffer U820 ( L1418, L5428 );
buffer U821 ( L1412, L5436 );
buffer U822 ( L1406, L5444 );
buffer U823 ( L737, L5452 );
buffer U824 ( L1399, L5460 );
nor2 U825 ( L2241, L737, L5465 );
nor2 U826 ( L2213, L1399, L5581 );
buffer U827 ( L757, L5748 );
buffer U828 ( L751, L5756 );
buffer U829 ( L745, L5764 );
buffer U830 ( L737, L5772 );
buffer U831 ( L731, L5780 );
buffer U832 ( L1418, L5788 );
buffer U833 ( L1412, L5796 );
buffer U834 ( L1406, L5804 );
buffer U835 ( L1399, L5812 );
nor2 U836 ( L737, L2241, L5849 );
buffer U837 ( L3682, L5929 );
buffer U838 ( L3682, L6049 );
buffer U839 ( L4710, L6367 );
buffer U840 ( L727, L6370 );
buffer U841 ( L4707, L6375 );
buffer U842 ( L723, L6378 );
buffer U843 ( L4704, L6383 );
buffer U844 ( L719, L6386 );
buffer U845 ( L4698, L6391 );
buffer U846 ( L711, L6394 );
buffer U847 ( L4695, L6399 );
buffer U848 ( L1395, L6402 );
buffer U849 ( L4692, L6407 );
buffer U850 ( L1391, L6410 );
buffer U851 ( L4689, L6415 );
buffer U852 ( L1387, L6418 );
buffer U853 ( L4701, L6423 );
buffer U854 ( L715, L6426 );
buffer U855 ( L4686, L6431 );
buffer U856 ( L1383, L6434 );
buffer U857 ( L3813, L6442 );
buffer U858 ( L3810, L6450 );
buffer U859 ( L3807, L6458 );
buffer U860 ( L3801, L6466 );
buffer U861 ( L3804, L6498 );
buffer U862 ( L3679, L6519 );
buffer U863 ( L645, L6522 );
buffer U864 ( L3676, L6527 );
buffer U865 ( L641, L6530 );
buffer U866 ( L3673, L6535 );
buffer U867 ( L637, L6538 );
buffer U868 ( L3670, L6543 );
buffer U869 ( L633, L6546 );
buffer U870 ( L3667, L6559 );
buffer U871 ( L629, L6562 );
buffer U872 ( L3667, L6687 );
buffer U873 ( L3673, L6695 );
buffer U874 ( L3670, L6698 );
buffer U875 ( L3679, L6703 );
buffer U876 ( L3676, L6706 );
inv U877 ( L6711, L6717 );
inv U878 ( L6714, L6718 );
or2 U879 ( L2153, L2154, L6724 );
or2 U880 ( L2295, L2296, L6768 );
or2 U881 ( L2143, L2144, L7208 );
buffer U882 ( L3801, L7221 );
buffer U883 ( L3807, L7229 );
buffer U884 ( L3804, L7232 );
buffer U885 ( L3813, L7239 );
buffer U886 ( L3810, L7242 );
buffer U887 ( L2305, L7249 );
buffer U888 ( L2312, L7257 );
buffer U889 ( L2308, L7260 );
buffer U890 ( L2316, L7268 );
buffer U891 ( L1383, L7293 );
buffer U892 ( L1391, L7301 );
buffer U893 ( L1387, L7304 );
buffer U894 ( L711, L7309 );
buffer U895 ( L1395, L7312 );
buffer U896 ( L719, L7317 );
buffer U897 ( L715, L7320 );
buffer U898 ( L727, L7327 );
buffer U899 ( L723, L7330 );
buffer U900 ( L2316, L7396 );
buffer U901 ( L2312, L7404 );
buffer U902 ( L2308, L7412 );
buffer U903 ( L3686, L7425 );
buffer U904 ( L4686, L7463 );
buffer U905 ( L4692, L7471 );
buffer U906 ( L4689, L7474 );
buffer U907 ( L4698, L7479 );
buffer U908 ( L4695, L7482 );
buffer U909 ( L4704, L7487 );
buffer U910 ( L4701, L7490 );
buffer U911 ( L4710, L7497 );
buffer U912 ( L4707, L7500 );
or2 U913 ( L4472, L4473, L7507 );
or2 U914 ( L4470, L4471, L7510 );
or2 U915 ( L4122, L4123, L7554 );
nand2 U916 ( L5234, L5237, L1152 );
inv U917 ( L5234, L5238 );
nand2 U918 ( L5242, L5245, L1156 );
inv U919 ( L5242, L5246 );
inv U920 ( L5250, L5254 );
inv U921 ( L5284, L5288 );
or2 U922 ( L3221, L3222, L3223 );
or3 U923 ( L777, L913, L914, L4942 );
inv U924 ( L4962, L4966 );
inv U925 ( L5003, L5007 );
nand2 U926 ( L5274, L5277, L5279 );
nand2 U927 ( L5271, L5278, L5280 );
nand2 U928 ( L5308, L5311, L5313 );
nand2 U929 ( L5305, L5312, L5314 );
nand2 U930 ( L6714, L6717, L6719 );
nand2 U931 ( L6711, L6718, L6720 );
nand2 U932 ( L4884, L4887, L790 );
inv U933 ( L4884, L4888 );
nand2 U934 ( L4892, L4895, L803 );
inv U935 ( L4892, L4896 );
nand2 U936 ( L4900, L4903, L825 );
inv U937 ( L4900, L4904 );
nand2 U938 ( L4908, L4911, L851 );
inv U939 ( L4908, L4912 );
nand2 U940 ( L4924, L4927, L893 );
inv U941 ( L4924, L4928 );
inv U942 ( L902, L906 );
inv U943 ( L908, L912 );
nand2 U944 ( L5194, L5197, L1024 );
inv U945 ( L5194, L5198 );
nand2 U946 ( L5202, L5205, L1036 );
inv U947 ( L5202, L5206 );
nand2 U948 ( L5210, L5213, L1053 );
inv U949 ( L5210, L5214 );
nand2 U950 ( L5218, L5221, L1072 );
inv U951 ( L5218, L5222 );
nand2 U952 ( L5226, L5229, L1091 );
inv U953 ( L5226, L5230 );
inv U954 ( L1108, L1112 );
inv U955 ( L1117, L1121 );
nand2 U956 ( L5231, L5238, L1153 );
nand2 U957 ( L5239, L5246, L1157 );
inv U958 ( L5247, L5253 );
nand2 U959 ( L5247, L5254, L1216 );
inv U960 ( L5255, L5261 );
inv U961 ( L5258, L5262 );
inv U962 ( L5263, L5269 );
inv U963 ( L5266, L5270 );
inv U964 ( L5281, L5287 );
nand2 U965 ( L5281, L5288, L1239 );
inv U966 ( L5289, L5295 );
inv U967 ( L5292, L5296 );
inv U968 ( L5297, L5303 );
inv U969 ( L5300, L5304 );
inv U970 ( L5315, L5321 );
nand2 U971 ( L5315, L5322, L1262 );
inv U972 ( L5323, L5329 );
inv U973 ( L5326, L5330 );
inv U974 ( L5331, L5337 );
inv U975 ( L5334, L5338 );
nand2 U976 ( L5396, L5399, L1544 );
inv U977 ( L5396, L5400 );
nand2 U978 ( L5404, L5407, L1554 );
inv U979 ( L5404, L5408 );
nand2 U980 ( L5412, L5415, L1571 );
inv U981 ( L5412, L5416 );
nand2 U982 ( L5420, L5423, L1596 );
inv U983 ( L5420, L5424 );
nand2 U984 ( L5428, L5431, L1607 );
inv U985 ( L5428, L5432 );
nand2 U986 ( L5436, L5439, L1628 );
inv U987 ( L5436, L5440 );
nand2 U988 ( L5444, L5447, L1653 );
inv U989 ( L5444, L5448 );
nand2 U990 ( L5452, L5455, L1685 );
inv U991 ( L5452, L5456 );
nand2 U992 ( L5460, L5463, L1693 );
inv U993 ( L5460, L5464 );
nand2 U994 ( L5748, L5751, L1793 );
inv U995 ( L5748, L5752 );
nand2 U996 ( L5756, L5759, L1803 );
inv U997 ( L5756, L5760 );
nand2 U998 ( L5764, L5767, L1820 );
inv U999 ( L5764, L5768 );
nand2 U1000 ( L5772, L5775, L1848 );
inv U1001 ( L5772, L5776 );
nand2 U1002 ( L5780, L5783, L1857 );
inv U1003 ( L5780, L5784 );
nand2 U1004 ( L5788, L5791, L1867 );
inv U1005 ( L5788, L5792 );
nand2 U1006 ( L5796, L5799, L1883 );
inv U1007 ( L5796, L5800 );
nand2 U1008 ( L5804, L5807, L1901 );
inv U1009 ( L5804, L5808 );
nand2 U1010 ( L5812, L5815, L1919 );
inv U1011 ( L5812, L5816 );
inv U1012 ( L5849, L5855 );
and2 U1013 ( L3751, L2111, L2351 );
and2 U1014 ( L3745, L2105, L2366 );
and2 U1015 ( L3739, L2099, L2384 );
and2 U1016 ( L2091, L3731, L2391 );
and2 U1017 ( L3725, L2085, L2417 );
and2 U1018 ( L3719, L2335, L2431 );
and2 U1019 ( L3713, L2329, L2448 );
and2 U1020 ( L3707, L2323, L2465 );
inv U1021 ( L5929, L5935 );
and2 U1022 ( L3751, L2111, L2597 );
and2 U1023 ( L3745, L2105, L2612 );
and2 U1024 ( L3739, L2099, L2629 );
and2 U1025 ( L3731, L2091, L2635 );
and2 U1026 ( L3725, L2085, L2652 );
and2 U1027 ( L3719, L2335, L2670 );
and2 U1028 ( L3713, L2329, L2693 );
and2 U1029 ( L3707, L2323, L2715 );
inv U1030 ( L6049, L6055 );
inv U1031 ( L6367, L6373 );
inv U1032 ( L6370, L6374 );
inv U1033 ( L6375, L6381 );
inv U1034 ( L6378, L6382 );
inv U1035 ( L6383, L6389 );
inv U1036 ( L6386, L6390 );
inv U1037 ( L6391, L6397 );
inv U1038 ( L6394, L6398 );
inv U1039 ( L6399, L6405 );
inv U1040 ( L6402, L6406 );
inv U1041 ( L6407, L6413 );
inv U1042 ( L6410, L6414 );
inv U1043 ( L6415, L6421 );
inv U1044 ( L6418, L6422 );
inv U1045 ( L6423, L6429 );
inv U1046 ( L6426, L6430 );
inv U1047 ( L6431, L6437 );
inv U1048 ( L6434, L6438 );
inv U1049 ( L6442, L6446 );
and2 U1050 ( L4175, L3813, L3059 );
inv U1051 ( L6450, L6454 );
and2 U1052 ( L4172, L3810, L3068 );
inv U1053 ( L6458, L6462 );
and2 U1054 ( L4169, L3807, L3076 );
and2 U1055 ( L4166, L3804, L3079 );
inv U1056 ( L6466, L6470 );
and2 U1057 ( L4163, L3801, L3090 );
and2 U1058 ( L4160, L2175, L3099 );
and2 U1059 ( L4157, L2171, L3107 );
and2 U1060 ( L4154, L2167, L3114 );
and2 U1061 ( L4151, L2163, L3116 );
inv U1062 ( L6498, L6502 );
inv U1063 ( L6519, L6525 );
inv U1064 ( L6522, L6526 );
inv U1065 ( L6527, L6533 );
inv U1066 ( L6530, L6534 );
inv U1067 ( L6535, L6541 );
inv U1068 ( L6538, L6542 );
inv U1069 ( L6543, L6549 );
inv U1070 ( L6546, L6550 );
inv U1071 ( L6559, L6565 );
inv U1072 ( L6562, L6566 );
inv U1073 ( L3216, L3220 );
and2 U1074 ( L4439, L3838, L3292 );
and2 U1075 ( L4434, L3833, L3308 );
and2 U1076 ( L4429, L3828, L3327 );
and2 U1077 ( L3821, L4422, L3335 );
and2 U1078 ( L4417, L3816, L3362 );
and2 U1079 ( L4412, L2198, L3376 );
and2 U1080 ( L4407, L2192, L3393 );
and2 U1081 ( L4402, L2186, L3410 );
and2 U1082 ( L4396, L2179, L3425 );
inv U1083 ( L6687, L6693 );
nand2 U1084 ( L6687, L6694, L3503 );
inv U1085 ( L6695, L6701 );
inv U1086 ( L6698, L6702 );
inv U1087 ( L6703, L6709 );
inv U1088 ( L6706, L6710 );
inv U1089 ( L6724, L6728 );
inv U1090 ( L6768, L6772 );
and2 U1091 ( L4439, L3838, L3853 );
and2 U1092 ( L4434, L3833, L3868 );
and2 U1093 ( L4429, L3828, L3885 );
and2 U1094 ( L4422, L3821, L3891 );
and2 U1095 ( L4417, L3816, L3908 );
and2 U1096 ( L4412, L2198, L3926 );
and2 U1097 ( L4407, L2192, L3949 );
and2 U1098 ( L4402, L2186, L3971 );
and2 U1099 ( L4396, L2179, L3979 );
inv U1100 ( L7208, L7212 );
inv U1101 ( L7221, L7227 );
inv U1102 ( L7249, L7255 );
nand2 U1103 ( L7249, L7256, L4202 );
inv U1104 ( L7257, L7263 );
inv U1105 ( L7260, L7264 );
inv U1106 ( L7268, L7272 );
inv U1107 ( L7293, L7299 );
nand2 U1108 ( L7293, L7300, L4225 );
inv U1109 ( L7301, L7307 );
inv U1110 ( L7304, L7308 );
inv U1111 ( L7309, L7315 );
inv U1112 ( L7312, L7316 );
and2 U1113 ( L4511, L2081, L4297 );
and2 U1114 ( L4508, L2077, L4305 );
and2 U1115 ( L4505, L2073, L4312 );
and2 U1116 ( L4502, L2069, L4314 );
and2 U1117 ( L4499, L2065, L4324 );
inv U1118 ( L7396, L7400 );
and2 U1119 ( L4496, L2316, L4333 );
inv U1120 ( L7404, L7408 );
and2 U1121 ( L4493, L2312, L4341 );
inv U1122 ( L7412, L7416 );
and2 U1123 ( L4490, L2308, L4348 );
and2 U1124 ( L3686, L3695, L4349 );
inv U1125 ( L7425, L7431 );
and2 U1126 ( L2320, L1535, L4389 );
inv U1127 ( L7463, L7469 );
nand2 U1128 ( L7463, L7470, L4530 );
inv U1129 ( L7471, L7477 );
inv U1130 ( L7474, L7478 );
inv U1131 ( L7479, L7485 );
inv U1132 ( L7482, L7486 );
inv U1133 ( L7507, L7513 );
inv U1134 ( L7510, L7514 );
inv U1135 ( L7554, L7558 );
or2 U1136 ( L917, L953, L4932 );
inv U1137 ( L4952, L4956 );
inv U1138 ( L917, L4973 );
inv U1139 ( L4983, L4987 );
inv U1140 ( L4993, L4997 );
inv U1141 ( L5011, L5017 );
buffer U1142 ( L877, L5099 );
inv U1143 ( L5339, L5345 );
inv U1144 ( L5342, L5346 );
inv U1145 ( L5349, L5355 );
inv U1146 ( L5352, L5356 );
nand2 U1147 ( L5279, L5280, L5372 );
nand2 U1148 ( L5313, L5314, L5380 );
inv U1149 ( L5465, L5471 );
buffer U1150 ( L1590, L5523 );
inv U1151 ( L5581, L5587 );
buffer U1152 ( L1677, L5669 );
buffer U1153 ( L1841, L5857 );
buffer U1154 ( L2111, L5868 );
buffer U1155 ( L2105, L5876 );
buffer U1156 ( L2099, L5884 );
buffer U1157 ( L2091, L5892 );
buffer U1158 ( L2085, L5900 );
buffer U1159 ( L2335, L5908 );
buffer U1160 ( L2329, L5916 );
buffer U1161 ( L2323, L5924 );
nor2 U1162 ( L2091, L3731, L5969 );
buffer U1163 ( L2111, L5988 );
buffer U1164 ( L2105, L5996 );
buffer U1165 ( L2099, L6004 );
buffer U1166 ( L2085, L6012 );
buffer U1167 ( L2335, L6020 );
buffer U1168 ( L2329, L6028 );
buffer U1169 ( L2323, L6036 );
buffer U1170 ( L2091, L6044 );
nor2 U1171 ( L3731, L2091, L6057 );
buffer U1172 ( L4175, L6439 );
buffer U1173 ( L4172, L6447 );
buffer U1174 ( L4169, L6455 );
buffer U1175 ( L4163, L6463 );
buffer U1176 ( L4160, L6471 );
buffer U1177 ( L2175, L6474 );
buffer U1178 ( L4157, L6479 );
buffer U1179 ( L2171, L6482 );
buffer U1180 ( L4154, L6487 );
buffer U1181 ( L2167, L6490 );
buffer U1182 ( L4166, L6495 );
buffer U1183 ( L4151, L6503 );
buffer U1184 ( L2163, L6506 );
buffer U1185 ( L3838, L6570 );
buffer U1186 ( L3833, L6578 );
buffer U1187 ( L3828, L6586 );
buffer U1188 ( L3821, L6594 );
buffer U1189 ( L3816, L6602 );
buffer U1190 ( L2198, L6610 );
buffer U1191 ( L2192, L6618 );
buffer U1192 ( L2186, L6626 );
buffer U1193 ( L2179, L6634 );
nor2 U1194 ( L3821, L4422, L6671 );
buffer U1195 ( L2179, L6721 );
buffer U1196 ( L2192, L6729 );
buffer U1197 ( L2186, L6732 );
buffer U1198 ( L3816, L6737 );
buffer U1199 ( L2198, L6740 );
buffer U1200 ( L3828, L6745 );
buffer U1201 ( L3821, L6748 );
buffer U1202 ( L3838, L6755 );
buffer U1203 ( L3833, L6758 );
buffer U1204 ( L2320, L6765 );
buffer U1205 ( L2329, L6773 );
buffer U1206 ( L2323, L6776 );
buffer U1207 ( L2085, L6781 );
buffer U1208 ( L2335, L6784 );
buffer U1209 ( L2099, L6789 );
buffer U1210 ( L2091, L6792 );
buffer U1211 ( L2111, L6799 );
buffer U1212 ( L2105, L6802 );
nand2 U1213 ( L6719, L6720, L6832 );
buffer U1214 ( L3838, L6856 );
buffer U1215 ( L3833, L6864 );
buffer U1216 ( L3828, L6872 );
buffer U1217 ( L3816, L6880 );
buffer U1218 ( L2198, L6888 );
buffer U1219 ( L2192, L6896 );
buffer U1220 ( L2186, L6904 );
buffer U1221 ( L3821, L6912 );
buffer U1222 ( L2179, L6920 );
nor2 U1223 ( L4422, L3821, L6925 );
nor2 U1224 ( L4396, L2179, L7041 );
buffer U1225 ( L2163, L7205 );
buffer U1226 ( L2171, L7213 );
buffer U1227 ( L2167, L7216 );
buffer U1228 ( L2175, L7224 );
inv U1229 ( L7229, L7235 );
inv U1230 ( L7232, L7236 );
inv U1231 ( L7239, L7245 );
inv U1232 ( L7242, L7246 );
buffer U1233 ( L2065, L7265 );
buffer U1234 ( L2073, L7273 );
buffer U1235 ( L2069, L7276 );
buffer U1236 ( L2081, L7283 );
buffer U1237 ( L2077, L7286 );
inv U1238 ( L7317, L7323 );
inv U1239 ( L7320, L7324 );
inv U1240 ( L7327, L7333 );
inv U1241 ( L7330, L7334 );
buffer U1242 ( L4511, L7361 );
buffer U1243 ( L2081, L7364 );
buffer U1244 ( L4508, L7369 );
buffer U1245 ( L2077, L7372 );
buffer U1246 ( L4505, L7377 );
buffer U1247 ( L2073, L7380 );
buffer U1248 ( L4499, L7385 );
buffer U1249 ( L2065, L7388 );
buffer U1250 ( L4496, L7393 );
buffer U1251 ( L4493, L7401 );
buffer U1252 ( L4490, L7409 );
buffer U1253 ( L4502, L7417 );
buffer U1254 ( L2069, L7420 );
buffer U1255 ( L3695, L7428 );
inv U1256 ( L7487, L7493 );
inv U1257 ( L7490, L7494 );
inv U1258 ( L7497, L7503 );
inv U1259 ( L7500, L7504 );
buffer U1260 ( L4493, L7515 );
buffer U1261 ( L4490, L7518 );
buffer U1262 ( L4499, L7523 );
buffer U1263 ( L4496, L7526 );
buffer U1264 ( L4505, L7531 );
buffer U1265 ( L4502, L7534 );
buffer U1266 ( L4511, L7541 );
buffer U1267 ( L4508, L7544 );
buffer U1268 ( L4151, L7551 );
buffer U1269 ( L4157, L7559 );
buffer U1270 ( L4154, L7562 );
buffer U1271 ( L4163, L7567 );
buffer U1272 ( L4160, L7570 );
buffer U1273 ( L4169, L7575 );
buffer U1274 ( L4166, L7578 );
buffer U1275 ( L4175, L7585 );
buffer U1276 ( L4172, L7588 );
nand2 U1277 ( L1121, L1112, L1176 );
nand2 U1278 ( L912, L906, L957 );
nand2 U1279 ( L4881, L4888, L791 );
nand2 U1280 ( L4889, L4896, L804 );
nand2 U1281 ( L4897, L4904, L826 );
nand2 U1282 ( L4905, L4912, L852 );
nand2 U1283 ( L4921, L4928, L894 );
nand2 U1284 ( L5191, L5198, L1025 );
nand2 U1285 ( L5199, L5206, L1037 );
nand2 U1286 ( L5207, L5214, L1054 );
nand2 U1287 ( L5215, L5222, L1073 );
nand2 U1288 ( L5223, L5230, L1092 );
nand2 U1289 ( L1152, L1153, L1154 );
nand2 U1290 ( L1156, L1157, L1158 );
nand2 U1291 ( L5250, L5253, L1215 );
nand2 U1292 ( L5258, L5261, L1224 );
nand2 U1293 ( L5255, L5262, L1225 );
nand2 U1294 ( L5266, L5269, L1233 );
nand2 U1295 ( L5263, L5270, L1234 );
nand2 U1296 ( L5284, L5287, L1238 );
nand2 U1297 ( L5292, L5295, L1247 );
nand2 U1298 ( L5289, L5296, L1248 );
nand2 U1299 ( L5300, L5303, L1256 );
nand2 U1300 ( L5297, L5304, L1257 );
nand2 U1301 ( L5318, L5321, L1261 );
nand2 U1302 ( L5326, L5329, L1270 );
nand2 U1303 ( L5323, L5330, L1271 );
nand2 U1304 ( L5334, L5337, L1279 );
nand2 U1305 ( L5331, L5338, L1280 );
nand2 U1306 ( L5393, L5400, L1545 );
nand2 U1307 ( L5401, L5408, L1555 );
nand2 U1308 ( L5409, L5416, L1572 );
nand2 U1309 ( L5417, L5424, L1597 );
nand2 U1310 ( L5425, L5432, L1608 );
nand2 U1311 ( L5433, L5440, L1629 );
nand2 U1312 ( L5441, L5448, L1654 );
nand2 U1313 ( L5449, L5456, L1686 );
nand2 U1314 ( L5457, L5464, L1694 );
nand2 U1315 ( L5745, L5752, L1794 );
nand2 U1316 ( L5753, L5760, L1804 );
nand2 U1317 ( L5761, L5768, L1821 );
nand2 U1318 ( L5769, L5776, L1849 );
nand2 U1319 ( L5777, L5784, L1858 );
nand2 U1320 ( L5785, L5792, L1868 );
nand2 U1321 ( L5793, L5800, L1884 );
nand2 U1322 ( L5801, L5808, L1902 );
nand2 U1323 ( L5809, L5816, L1920 );
nand2 U1324 ( L6370, L6373, L2954 );
nand2 U1325 ( L6367, L6374, L2955 );
nand2 U1326 ( L6378, L6381, L2963 );
nand2 U1327 ( L6375, L6382, L2964 );
nand2 U1328 ( L6386, L6389, L2971 );
nand2 U1329 ( L6383, L6390, L2972 );
nand2 U1330 ( L6394, L6397, L2980 );
nand2 U1331 ( L6391, L6398, L2981 );
nand2 U1332 ( L6402, L6405, L2990 );
nand2 U1333 ( L6399, L6406, L2991 );
nand2 U1334 ( L6410, L6413, L2999 );
nand2 U1335 ( L6407, L6414, L3000 );
nand2 U1336 ( L6418, L6421, L3007 );
nand2 U1337 ( L6415, L6422, L3008 );
nand2 U1338 ( L6426, L6429, L3016 );
nand2 U1339 ( L6423, L6430, L3017 );
nand2 U1340 ( L6434, L6437, L3019 );
nand2 U1341 ( L6431, L6438, L3020 );
nand2 U1342 ( L6522, L6525, L3174 );
nand2 U1343 ( L6519, L6526, L3175 );
nand2 U1344 ( L6530, L6533, L3184 );
nand2 U1345 ( L6527, L6534, L3185 );
nand2 U1346 ( L6538, L6541, L3193 );
nand2 U1347 ( L6535, L6542, L3194 );
nand2 U1348 ( L6546, L6549, L3201 );
nand2 U1349 ( L6543, L6550, L3202 );
nand2 U1350 ( L6562, L6565, L3213 );
nand2 U1351 ( L6559, L6566, L3214 );
inv U1352 ( L3223, L3227 );
nand2 U1353 ( L6690, L6693, L3502 );
nand2 U1354 ( L6698, L6701, L3511 );
nand2 U1355 ( L6695, L6702, L3512 );
nand2 U1356 ( L6706, L6709, L3520 );
nand2 U1357 ( L6703, L6710, L3521 );
nand2 U1358 ( L7252, L7255, L4201 );
nand2 U1359 ( L7260, L7263, L4210 );
nand2 U1360 ( L7257, L7264, L4211 );
nand2 U1361 ( L7296, L7299, L4224 );
nand2 U1362 ( L7304, L7307, L4233 );
nand2 U1363 ( L7301, L7308, L4234 );
nand2 U1364 ( L7312, L7315, L4242 );
nand2 U1365 ( L7309, L7316, L4243 );
nand2 U1366 ( L7466, L7469, L4529 );
nand2 U1367 ( L7474, L7477, L4538 );
nand2 U1368 ( L7471, L7478, L4539 );
nand2 U1369 ( L7482, L7485, L4547 );
nand2 U1370 ( L7479, L7486, L4548 );
nand2 U1371 ( L7510, L7513, L4552 );
nand2 U1372 ( L7507, L7514, L4553 );
inv U1373 ( L4942, L4946 );
nand2 U1374 ( L5342, L5345, L5347 );
nand2 U1375 ( L5339, L5346, L5348 );
nand2 U1376 ( L5352, L5355, L5357 );
nand2 U1377 ( L5349, L5356, L5358 );
nand2 U1378 ( L7232, L7235, L7237 );
nand2 U1379 ( L7229, L7236, L7238 );
nand2 U1380 ( L7242, L7245, L7247 );
nand2 U1381 ( L7239, L7246, L7248 );
nand2 U1382 ( L7320, L7323, L7325 );
nand2 U1383 ( L7317, L7324, L7326 );
nand2 U1384 ( L7330, L7333, L7335 );
nand2 U1385 ( L7327, L7334, L7336 );
nand2 U1386 ( L7490, L7493, L7495 );
nand2 U1387 ( L7487, L7494, L7496 );
nand2 U1388 ( L7500, L7503, L7505 );
nand2 U1389 ( L7497, L7504, L7506 );
nand2 U1390 ( L3227, L3220, L3244 );
nand2 U1391 ( L790, L791, L792 );
nand2 U1392 ( L803, L804, L805 );
nand2 U1393 ( L825, L826, L827 );
nand2 U1394 ( L851, L852, L853 );
nand2 U1395 ( L893, L894, L895 );
nand2 U1396 ( L1024, L1025, L1026 );
nand2 U1397 ( L1036, L1037, L1038 );
nand2 U1398 ( L1053, L1054, L1055 );
nand2 U1399 ( L1072, L1073, L1074 );
nand2 U1400 ( L1091, L1092, L1093 );
inv U1401 ( L1154, L1155 );
nand2 U1402 ( L1215, L1216, L1217 );
nand2 U1403 ( L1224, L1225, L1226 );
nand2 U1404 ( L1233, L1234, L1235 );
nand2 U1405 ( L1238, L1239, L1240 );
nand2 U1406 ( L1247, L1248, L1249 );
nand2 U1407 ( L1256, L1257, L1258 );
nand2 U1408 ( L1261, L1262, L1263 );
nand2 U1409 ( L1270, L1271, L1272 );
nand2 U1410 ( L1279, L1280, L1281 );
inv U1411 ( L5372, L5376 );
inv U1412 ( L5380, L5384 );
nand2 U1413 ( L1544, L1545, L1546 );
nand2 U1414 ( L1554, L1555, L1556 );
nand2 U1415 ( L1571, L1572, L1573 );
nand2 U1416 ( L1596, L1597, L1598 );
nand2 U1417 ( L1607, L1608, L1609 );
nand2 U1418 ( L1628, L1629, L1630 );
nand2 U1419 ( L1653, L1654, L1655 );
nand2 U1420 ( L1685, L1686, L1687 );
nand2 U1421 ( L1693, L1694, L1695 );
nand2 U1422 ( L1793, L1794, L1795 );
nand2 U1423 ( L1803, L1804, L1805 );
nand2 U1424 ( L1820, L1821, L1822 );
nand2 U1425 ( L1848, L1849, L1850 );
nand2 U1426 ( L1857, L1858, L1859 );
nand2 U1427 ( L1867, L1868, L1869 );
nand2 U1428 ( L1883, L1884, L1885 );
nand2 U1429 ( L1901, L1902, L1903 );
nand2 U1430 ( L1919, L1920, L1921 );
inv U1431 ( L5857, L5863 );
nand2 U1432 ( L5868, L5871, L2341 );
inv U1433 ( L5868, L5872 );
nand2 U1434 ( L5876, L5879, L2352 );
inv U1435 ( L5876, L5880 );
nand2 U1436 ( L5884, L5887, L2370 );
inv U1437 ( L5884, L5888 );
nand2 U1438 ( L5892, L5895, L2398 );
inv U1439 ( L5892, L5896 );
nand2 U1440 ( L5900, L5903, L2407 );
inv U1441 ( L5900, L5904 );
nand2 U1442 ( L5908, L5911, L2418 );
inv U1443 ( L5908, L5912 );
nand2 U1444 ( L5916, L5919, L2434 );
inv U1445 ( L5916, L5920 );
nand2 U1446 ( L5924, L5927, L2452 );
inv U1447 ( L5924, L5928 );
and2 U1448 ( L3682, L4389, L2481 );
inv U1449 ( L5969, L5975 );
nand2 U1450 ( L5988, L5991, L2587 );
inv U1451 ( L5988, L5992 );
nand2 U1452 ( L5996, L5999, L2598 );
inv U1453 ( L5996, L6000 );
nand2 U1454 ( L6004, L6007, L2616 );
inv U1455 ( L6004, L6008 );
nand2 U1456 ( L6012, L6015, L2641 );
inv U1457 ( L6012, L6016 );
nand2 U1458 ( L6020, L6023, L2653 );
inv U1459 ( L6020, L6024 );
nand2 U1460 ( L6028, L6031, L2674 );
inv U1461 ( L6028, L6032 );
nand2 U1462 ( L6036, L6039, L2699 );
inv U1463 ( L6036, L6040 );
and2 U1464 ( L3682, L4389, L2724 );
nand2 U1465 ( L6044, L6047, L2732 );
inv U1466 ( L6044, L6048 );
nand2 U1467 ( L2954, L2955, L2956 );
nand2 U1468 ( L2963, L2964, L2965 );
nand2 U1469 ( L2971, L2972, L2973 );
nand2 U1470 ( L2980, L2981, L2982 );
nand2 U1471 ( L2990, L2991, L2992 );
nand2 U1472 ( L2999, L3000, L3001 );
nand2 U1473 ( L3007, L3008, L3009 );
nand2 U1474 ( L3016, L3017, L3018 );
nand2 U1475 ( L3019, L3020, L3021 );
inv U1476 ( L6439, L6445 );
nand2 U1477 ( L6439, L6446, L3051 );
inv U1478 ( L6447, L6453 );
nand2 U1479 ( L6447, L6454, L3061 );
inv U1480 ( L6455, L6461 );
nand2 U1481 ( L6455, L6462, L3070 );
inv U1482 ( L6463, L6469 );
nand2 U1483 ( L6463, L6470, L3081 );
inv U1484 ( L6471, L6477 );
inv U1485 ( L6474, L6478 );
inv U1486 ( L6479, L6485 );
inv U1487 ( L6482, L6486 );
inv U1488 ( L6487, L6493 );
inv U1489 ( L6490, L6494 );
inv U1490 ( L6495, L6501 );
nand2 U1491 ( L6495, L6502, L3118 );
inv U1492 ( L6503, L6509 );
inv U1493 ( L6506, L6510 );
nand2 U1494 ( L3174, L3175, L3176 );
nand2 U1495 ( L3184, L3185, L3186 );
nand2 U1496 ( L3193, L3194, L3195 );
nand2 U1497 ( L3201, L3202, L3203 );
nand2 U1498 ( L3213, L3214, L3215 );
nand2 U1499 ( L6570, L6573, L3281 );
inv U1500 ( L6570, L6574 );
nand2 U1501 ( L6578, L6581, L3293 );
inv U1502 ( L6578, L6582 );
nand2 U1503 ( L6586, L6589, L3312 );
inv U1504 ( L6586, L6590 );
nand2 U1505 ( L6594, L6597, L3342 );
inv U1506 ( L6594, L6598 );
nand2 U1507 ( L6602, L6605, L3351 );
inv U1508 ( L6602, L6606 );
nand2 U1509 ( L6610, L6613, L3363 );
inv U1510 ( L6610, L6614 );
nand2 U1511 ( L6618, L6621, L3379 );
inv U1512 ( L6618, L6622 );
nand2 U1513 ( L6626, L6629, L3397 );
inv U1514 ( L6626, L6630 );
nand2 U1515 ( L6634, L6637, L3415 );
inv U1516 ( L6634, L6638 );
inv U1517 ( L6671, L6677 );
nand2 U1518 ( L3502, L3503, L3504 );
nand2 U1519 ( L3511, L3512, L3513 );
nand2 U1520 ( L3520, L3521, L3522 );
inv U1521 ( L6721, L6727 );
nand2 U1522 ( L6721, L6728, L3526 );
inv U1523 ( L6729, L6735 );
inv U1524 ( L6732, L6736 );
inv U1525 ( L6737, L6743 );
inv U1526 ( L6740, L6744 );
inv U1527 ( L6765, L6771 );
nand2 U1528 ( L6765, L6772, L3549 );
inv U1529 ( L6773, L6779 );
inv U1530 ( L6776, L6780 );
inv U1531 ( L6781, L6787 );
inv U1532 ( L6784, L6788 );
inv U1533 ( L6832, L6836 );
nand2 U1534 ( L6856, L6859, L3843 );
inv U1535 ( L6856, L6860 );
nand2 U1536 ( L6864, L6867, L3854 );
inv U1537 ( L6864, L6868 );
nand2 U1538 ( L6872, L6875, L3872 );
inv U1539 ( L6872, L6876 );
nand2 U1540 ( L6880, L6883, L3897 );
inv U1541 ( L6880, L6884 );
nand2 U1542 ( L6888, L6891, L3909 );
inv U1543 ( L6888, L6892 );
nand2 U1544 ( L6896, L6899, L3930 );
inv U1545 ( L6896, L6900 );
nand2 U1546 ( L6904, L6907, L3955 );
inv U1547 ( L6904, L6908 );
nand2 U1548 ( L6912, L6915, L3987 );
inv U1549 ( L6912, L6916 );
nand2 U1550 ( L6920, L6923, L3995 );
inv U1551 ( L6920, L6924 );
inv U1552 ( L7205, L7211 );
nand2 U1553 ( L7205, L7212, L4179 );
inv U1554 ( L7213, L7219 );
inv U1555 ( L7216, L7220 );
nand2 U1556 ( L7224, L7227, L4196 );
inv U1557 ( L7224, L7228 );
nand2 U1558 ( L4201, L4202, L4203 );
nand2 U1559 ( L4210, L4211, L4212 );
inv U1560 ( L7265, L7271 );
nand2 U1561 ( L7265, L7272, L4220 );
nand2 U1562 ( L4224, L4225, L4226 );
nand2 U1563 ( L4233, L4234, L4235 );
nand2 U1564 ( L4242, L4243, L4244 );
inv U1565 ( L7361, L7367 );
inv U1566 ( L7364, L7368 );
inv U1567 ( L7369, L7375 );
inv U1568 ( L7372, L7376 );
inv U1569 ( L7377, L7383 );
inv U1570 ( L7380, L7384 );
inv U1571 ( L7385, L7391 );
inv U1572 ( L7388, L7392 );
inv U1573 ( L7393, L7399 );
nand2 U1574 ( L7393, L7400, L4326 );
inv U1575 ( L7401, L7407 );
nand2 U1576 ( L7401, L7408, L4335 );
inv U1577 ( L7409, L7415 );
nand2 U1578 ( L7409, L7416, L4343 );
inv U1579 ( L7417, L7423 );
inv U1580 ( L7420, L7424 );
nand2 U1581 ( L7428, L7431, L4353 );
inv U1582 ( L7428, L7432 );
nand2 U1583 ( L4529, L4530, L4531 );
nand2 U1584 ( L4538, L4539, L4540 );
nand2 U1585 ( L4547, L4548, L4549 );
nand2 U1586 ( L4552, L4553, L4554 );
inv U1587 ( L7515, L7521 );
inv U1588 ( L7518, L7522 );
inv U1589 ( L7523, L7529 );
inv U1590 ( L7526, L7530 );
inv U1591 ( L7551, L7557 );
nand2 U1592 ( L7551, L7558, L4576 );
inv U1593 ( L7559, L7565 );
inv U1594 ( L7562, L7566 );
inv U1595 ( L7567, L7573 );
inv U1596 ( L7570, L7574 );
inv U1597 ( L4932, L4936 );
nand2 U1598 ( L4932, L4935, L4937 );
inv U1599 ( L4973, L4977 );
nand2 U1600 ( L4973, L4976, L4978 );
inv U1601 ( L5099, L5105 );
nand2 U1602 ( L5357, L5358, L5359 );
nand2 U1603 ( L5347, L5348, L5362 );
inv U1604 ( L5523, L5529 );
inv U1605 ( L5669, L5675 );
buffer U1606 ( L4389, L5932 );
buffer U1607 ( L2391, L5977 );
buffer U1608 ( L4389, L6052 );
inv U1609 ( L6057, L6063 );
buffer U1610 ( L2635, L6115 );
nor2 U1611 ( L3682, L4389, L6173 );
buffer U1612 ( L3335, L6679 );
inv U1613 ( L6745, L6751 );
inv U1614 ( L6748, L6752 );
inv U1615 ( L6755, L6761 );
inv U1616 ( L6758, L6762 );
inv U1617 ( L6789, L6795 );
inv U1618 ( L6792, L6796 );
inv U1619 ( L6799, L6805 );
inv U1620 ( L6802, L6806 );
inv U1621 ( L6925, L6931 );
buffer U1622 ( L3891, L6983 );
inv U1623 ( L7041, L7047 );
buffer U1624 ( L3979, L7129 );
inv U1625 ( L7273, L7279 );
inv U1626 ( L7276, L7280 );
inv U1627 ( L7283, L7289 );
inv U1628 ( L7286, L7290 );
nand2 U1629 ( L7247, L7248, L7337 );
nand2 U1630 ( L7237, L7238, L7340 );
nand2 U1631 ( L7335, L7336, L7353 );
nand2 U1632 ( L7325, L7326, L7356 );
inv U1633 ( L7531, L7537 );
inv U1634 ( L7534, L7538 );
inv U1635 ( L7541, L7547 );
inv U1636 ( L7544, L7548 );
inv U1637 ( L7575, L7581 );
inv U1638 ( L7578, L7582 );
inv U1639 ( L7585, L7591 );
inv U1640 ( L7588, L7592 );
nand2 U1641 ( L7505, L7506, L7595 );
nand2 U1642 ( L7495, L7496, L7598 );
nand2 U1643 ( L5865, L5872, L2342 );
nand2 U1644 ( L5873, L5880, L2353 );
nand2 U1645 ( L5881, L5888, L2371 );
nand2 U1646 ( L5889, L5896, L2399 );
nand2 U1647 ( L5897, L5904, L2408 );
nand2 U1648 ( L5905, L5912, L2419 );
nand2 U1649 ( L5913, L5920, L2435 );
nand2 U1650 ( L5921, L5928, L2453 );
nand2 U1651 ( L5985, L5992, L2588 );
nand2 U1652 ( L5993, L6000, L2599 );
nand2 U1653 ( L6001, L6008, L2617 );
nand2 U1654 ( L6009, L6016, L2642 );
nand2 U1655 ( L6017, L6024, L2654 );
nand2 U1656 ( L6025, L6032, L2675 );
nand2 U1657 ( L6033, L6040, L2700 );
nand2 U1658 ( L6041, L6048, L2733 );
nand2 U1659 ( L6442, L6445, L3050 );
nand2 U1660 ( L6450, L6453, L3060 );
nand2 U1661 ( L6458, L6461, L3069 );
nand2 U1662 ( L6466, L6469, L3080 );
nand2 U1663 ( L6474, L6477, L3091 );
nand2 U1664 ( L6471, L6478, L3092 );
nand2 U1665 ( L6482, L6485, L3100 );
nand2 U1666 ( L6479, L6486, L3101 );
nand2 U1667 ( L6490, L6493, L3108 );
nand2 U1668 ( L6487, L6494, L3109 );
nand2 U1669 ( L6498, L6501, L3117 );
nand2 U1670 ( L6506, L6509, L3120 );
nand2 U1671 ( L6503, L6510, L3121 );
nand2 U1672 ( L6567, L6574, L3282 );
nand2 U1673 ( L6575, L6582, L3294 );
nand2 U1674 ( L6583, L6590, L3313 );
nand2 U1675 ( L6591, L6598, L3343 );
nand2 U1676 ( L6599, L6606, L3352 );
nand2 U1677 ( L6607, L6614, L3364 );
nand2 U1678 ( L6615, L6622, L3380 );
nand2 U1679 ( L6623, L6630, L3398 );
nand2 U1680 ( L6631, L6638, L3416 );
nand2 U1681 ( L6724, L6727, L3525 );
nand2 U1682 ( L6732, L6735, L3534 );
nand2 U1683 ( L6729, L6736, L3535 );
nand2 U1684 ( L6740, L6743, L3543 );
nand2 U1685 ( L6737, L6744, L3544 );
nand2 U1686 ( L6768, L6771, L3548 );
nand2 U1687 ( L6776, L6779, L3557 );
nand2 U1688 ( L6773, L6780, L3558 );
nand2 U1689 ( L6784, L6787, L3566 );
nand2 U1690 ( L6781, L6788, L3567 );
nand2 U1691 ( L6853, L6860, L3844 );
nand2 U1692 ( L6861, L6868, L3855 );
nand2 U1693 ( L6869, L6876, L3873 );
nand2 U1694 ( L6877, L6884, L3898 );
nand2 U1695 ( L6885, L6892, L3910 );
nand2 U1696 ( L6893, L6900, L3931 );
nand2 U1697 ( L6901, L6908, L3956 );
nand2 U1698 ( L6909, L6916, L3988 );
nand2 U1699 ( L6917, L6924, L3996 );
nand2 U1700 ( L7208, L7211, L4178 );
nand2 U1701 ( L7216, L7219, L4187 );
nand2 U1702 ( L7213, L7220, L4188 );
nand2 U1703 ( L7221, L7228, L4197 );
nand2 U1704 ( L7268, L7271, L4219 );
nand2 U1705 ( L7364, L7367, L4289 );
nand2 U1706 ( L7361, L7368, L4290 );
nand2 U1707 ( L7372, L7375, L4298 );
nand2 U1708 ( L7369, L7376, L4299 );
nand2 U1709 ( L7380, L7383, L4306 );
nand2 U1710 ( L7377, L7384, L4307 );
nand2 U1711 ( L7388, L7391, L4315 );
nand2 U1712 ( L7385, L7392, L4316 );
nand2 U1713 ( L7396, L7399, L4325 );
nand2 U1714 ( L7404, L7407, L4334 );
nand2 U1715 ( L7412, L7415, L4342 );
nand2 U1716 ( L7420, L7423, L4350 );
nand2 U1717 ( L7417, L7424, L4351 );
nand2 U1718 ( L7425, L7432, L4354 );
nand2 U1719 ( L7518, L7521, L4561 );
nand2 U1720 ( L7515, L7522, L4562 );
nand2 U1721 ( L7526, L7529, L4570 );
nand2 U1722 ( L7523, L7530, L4571 );
nand2 U1723 ( L7554, L7557, L4575 );
nand2 U1724 ( L7562, L7565, L4584 );
nand2 U1725 ( L7559, L7566, L4585 );
nand2 U1726 ( L7570, L7573, L4593 );
nand2 U1727 ( L7567, L7574, L4594 );
nand2 U1728 ( L4929, L4936, L4938 );
nand2 U1729 ( L4970, L4977, L4979 );
nand2 U1730 ( L6748, L6751, L6753 );
nand2 U1731 ( L6745, L6752, L6754 );
nand2 U1732 ( L6758, L6761, L6763 );
nand2 U1733 ( L6755, L6762, L6764 );
nand2 U1734 ( L6792, L6795, L6797 );
nand2 U1735 ( L6789, L6796, L6798 );
nand2 U1736 ( L6802, L6805, L6807 );
nand2 U1737 ( L6799, L6806, L6808 );
nand2 U1738 ( L7276, L7279, L7281 );
nand2 U1739 ( L7273, L7280, L7282 );
nand2 U1740 ( L7286, L7289, L7291 );
nand2 U1741 ( L7283, L7290, L7292 );
nand2 U1742 ( L7534, L7537, L7539 );
nand2 U1743 ( L7531, L7538, L7540 );
nand2 U1744 ( L7544, L7547, L7549 );
nand2 U1745 ( L7541, L7548, L7550 );
nand2 U1746 ( L7578, L7581, L7583 );
nand2 U1747 ( L7575, L7582, L7584 );
nand2 U1748 ( L7588, L7591, L7593 );
nand2 U1749 ( L7585, L7592, L7594 );
inv U1750 ( L1850, L1856 );
and5 U1751 ( L895, L853, L827, L805, L792, L920 );
and2 U1752 ( L792, L821, L925 );
and3 U1753 ( L805, L792, L845, L926 );
and4 U1754 ( L827, L792, L868, L805, L927 );
and5 U1755 ( L853, L827, L792, L877, L805, L928 );
and2 U1756 ( L805, L845, L937 );
and3 U1757 ( L827, L868, L805, L938 );
and4 U1758 ( L853, L827, L877, L805, L939 );
and4 U1759 ( L895, L827, L805, L853, L940 );
and2 U1760 ( L805, L845, L941 );
and3 U1761 ( L827, L868, L805, L942 );
and4 U1762 ( L853, L827, L877, L805, L943 );
and2 U1763 ( L827, L868, L944 );
and3 U1764 ( L853, L827, L877, L945 );
and3 U1765 ( L895, L827, L853, L946 );
and2 U1766 ( L827, L868, L947 );
and3 U1767 ( L853, L827, L877, L948 );
and2 U1768 ( L853, L877, L949 );
and2 U1769 ( L895, L853, L956 );
and5 U1770 ( L1038, L1093, L1055, L1026, L1074, L1122 );
and2 U1771 ( L1026, L1050, L1125 );
and3 U1772 ( L1038, L1026, L1068, L1126 );
and4 U1773 ( L1055, L1026, L1086, L1038, L1127 );
and5 U1774 ( L1074, L1055, L1026, L1102, L1038, L1128 );
and2 U1775 ( L1038, L1068, L1132 );
and3 U1776 ( L1055, L1086, L1038, L1133 );
and4 U1777 ( L1074, L1055, L1102, L1038, L1134 );
and2 U1778 ( L1086, L1055, L1137 );
and3 U1779 ( L1074, L1055, L1102, L1138 );
and2 U1780 ( L1074, L1102, L1141 );
inv U1781 ( L1217, L1221 );
inv U1782 ( L1226, L1230 );
inv U1783 ( L1240, L1244 );
inv U1784 ( L1249, L1253 );
inv U1785 ( L1263, L1267 );
inv U1786 ( L1272, L1276 );
buffer U1787 ( L1235, L1284 );
buffer U1788 ( L1235, L1288 );
buffer U1789 ( L1258, L1292 );
buffer U1790 ( L1258, L1296 );
buffer U1791 ( L1281, L1300 );
buffer U1792 ( L1281, L1304 );
and4 U1793 ( L1687, L1573, L1556, L1546, L1702 );
and2 U1794 ( L1546, L1567, L1705 );
and3 U1795 ( L1556, L1546, L1584, L1706 );
and4 U1796 ( L1573, L1546, L1590, L1556, L1707 );
and2 U1797 ( L1556, L1584, L1709 );
and3 U1798 ( L1573, L1590, L1556, L1710 );
and3 U1799 ( L1687, L1573, L1556, L1711 );
and2 U1800 ( L1556, L1584, L1712 );
and3 U1801 ( L1573, L1590, L1556, L1713 );
and2 U1802 ( L1573, L1590, L1714 );
and5 U1803 ( L1695, L1655, L1630, L1609, L1598, L1718 );
and2 U1804 ( L1598, L1624, L1722 );
and3 U1805 ( L1609, L1598, L1647, L1723 );
and4 U1806 ( L1630, L1598, L1669, L1609, L1724 );
and5 U1807 ( L1655, L1630, L1598, L1677, L1609, L1725 );
and2 U1808 ( L1609, L1647, L1733 );
and3 U1809 ( L1630, L1669, L1609, L1734 );
and4 U1810 ( L1655, L1630, L1677, L1609, L1735 );
and4 U1811 ( L1695, L1630, L1609, L1655, L1736 );
and2 U1812 ( L1609, L1647, L1737 );
and3 U1813 ( L1630, L1669, L1609, L1738 );
and4 U1814 ( L1655, L1630, L1677, L1609, L1739 );
and2 U1815 ( L1630, L1669, L1740 );
and3 U1816 ( L1655, L1630, L1677, L1741 );
and3 U1817 ( L1695, L1630, L1655, L1742 );
and2 U1818 ( L1630, L1669, L1743 );
and3 U1819 ( L1655, L1630, L1677, L1744 );
and2 U1820 ( L1655, L1677, L1745 );
and2 U1821 ( L1687, L1573, L1749 );
and2 U1822 ( L1695, L1655, L1750 );
and4 U1823 ( L1805, L1850, L1822, L1795, L1935 );
and2 U1824 ( L1795, L1816, L1938 );
and3 U1825 ( L1805, L1795, L1834, L1939 );
and4 U1826 ( L1822, L1795, L1841, L1805, L1940 );
and2 U1827 ( L1805, L1834, L1942 );
and3 U1828 ( L1822, L1841, L1805, L1943 );
and3 U1829 ( L1850, L1822, L1805, L1944 );
and2 U1830 ( L1805, L1834, L1945 );
and3 U1831 ( L1841, L1822, L1805, L1946 );
and2 U1832 ( L1822, L1841, L1947 );
and2 U1833 ( L1850, L1822, L1948 );
and2 U1834 ( L1822, L1841, L1949 );
and5 U1835 ( L1869, L1921, L1885, L1859, L1903, L1950 );
and2 U1836 ( L1859, L1880, L1953 );
and3 U1837 ( L1869, L1859, L1897, L1954 );
and4 U1838 ( L1885, L1859, L1914, L1869, L1955 );
and5 U1839 ( L1903, L1885, L1859, L1929, L1869, L1956 );
and2 U1840 ( L1869, L1897, L1960 );
and3 U1841 ( L1885, L1914, L1869, L1961 );
and4 U1842 ( L1903, L1885, L1929, L1869, L1962 );
and2 U1843 ( L1914, L1885, L1965 );
and3 U1844 ( L1903, L1885, L1929, L1966 );
and2 U1845 ( L1903, L1929, L1969 );
nand2 U1846 ( L2341, L2342, L2343 );
nand2 U1847 ( L2352, L2353, L2354 );
nand2 U1848 ( L2370, L2371, L2372 );
nand2 U1849 ( L2398, L2399, L2400 );
nand2 U1850 ( L2407, L2408, L2409 );
nand2 U1851 ( L2418, L2419, L2420 );
nand2 U1852 ( L2434, L2435, L2436 );
nand2 U1853 ( L2452, L2453, L2454 );
nand2 U1854 ( L5932, L5935, L2470 );
inv U1855 ( L5932, L5936 );
inv U1856 ( L5977, L5983 );
nand2 U1857 ( L2587, L2588, L2589 );
nand2 U1858 ( L2598, L2599, L2600 );
nand2 U1859 ( L2616, L2617, L2618 );
nand2 U1860 ( L2641, L2642, L2643 );
nand2 U1861 ( L2653, L2654, L2655 );
nand2 U1862 ( L2674, L2675, L2676 );
nand2 U1863 ( L2699, L2700, L2701 );
nand2 U1864 ( L2732, L2733, L2734 );
nand2 U1865 ( L6052, L6055, L2740 );
inv U1866 ( L6052, L6056 );
and4 U1867 ( L3018, L2973, L2965, L2956, L3022 );
and2 U1868 ( L2956, L2970, L3025 );
and3 U1869 ( L2965, L2956, L2977, L3026 );
and4 U1870 ( L2973, L2956, L2979, L2965, L3027 );
and5 U1871 ( L3021, L3009, L3001, L2992, L2982, L3029 );
and2 U1872 ( L2982, L2998, L3030 );
and3 U1873 ( L2992, L2982, L3006, L3031 );
and4 U1874 ( L3001, L2982, L3013, L2992, L3032 );
and5 U1875 ( L3009, L3001, L2982, L3015, L2992, L3033 );
nand2 U1876 ( L3050, L3051, L3052 );
nand2 U1877 ( L3060, L3061, L3062 );
nand2 U1878 ( L3069, L3070, L3071 );
nand2 U1879 ( L3080, L3081, L3082 );
nand2 U1880 ( L3091, L3092, L3093 );
nand2 U1881 ( L3100, L3101, L3102 );
nand2 U1882 ( L3108, L3109, L3110 );
nand2 U1883 ( L3117, L3118, L3119 );
nand2 U1884 ( L3120, L3121, L3122 );
and5 U1885 ( L3215, L3203, L3195, L3186, L3176, L3228 );
and2 U1886 ( L3176, L3192, L3231 );
and3 U1887 ( L3186, L3176, L3200, L3232 );
and4 U1888 ( L3195, L3176, L3207, L3186, L3233 );
and5 U1889 ( L3203, L3195, L3176, L3209, L3186, L3234 );
nand2 U1890 ( L3281, L3282, L3283 );
nand2 U1891 ( L3293, L3294, L3295 );
nand2 U1892 ( L3312, L3313, L3314 );
nand2 U1893 ( L3342, L3343, L3344 );
nand2 U1894 ( L3351, L3352, L3353 );
nand2 U1895 ( L3363, L3364, L3365 );
nand2 U1896 ( L3379, L3380, L3381 );
nand2 U1897 ( L3397, L3398, L3399 );
nand2 U1898 ( L3415, L3416, L3417 );
inv U1899 ( L6679, L6685 );
inv U1900 ( L3504, L3508 );
inv U1901 ( L3513, L3517 );
nand2 U1902 ( L3525, L3526, L3527 );
nand2 U1903 ( L3534, L3535, L3536 );
nand2 U1904 ( L3543, L3544, L3545 );
nand2 U1905 ( L3548, L3549, L3550 );
nand2 U1906 ( L3557, L3558, L3559 );
nand2 U1907 ( L3566, L3567, L3568 );
buffer U1908 ( L3522, L3571 );
buffer U1909 ( L3522, L3575 );
nand2 U1910 ( L3843, L3844, L3845 );
nand2 U1911 ( L3854, L3855, L3856 );
nand2 U1912 ( L3872, L3873, L3874 );
nand2 U1913 ( L3897, L3898, L3899 );
nand2 U1914 ( L3909, L3910, L3911 );
nand2 U1915 ( L3930, L3931, L3932 );
nand2 U1916 ( L3955, L3956, L3957 );
nand2 U1917 ( L3987, L3988, L3989 );
nand2 U1918 ( L3995, L3996, L3997 );
nand2 U1919 ( L4178, L4179, L4180 );
nand2 U1920 ( L4187, L4188, L4189 );
nand2 U1921 ( L4196, L4197, L4198 );
inv U1922 ( L4203, L4207 );
inv U1923 ( L4212, L4216 );
nand2 U1924 ( L4219, L4220, L4221 );
inv U1925 ( L4226, L4230 );
inv U1926 ( L4235, L4239 );
buffer U1927 ( L4244, L4263 );
buffer U1928 ( L4244, L4267 );
nand2 U1929 ( L4289, L4290, L4291 );
nand2 U1930 ( L4298, L4299, L4300 );
nand2 U1931 ( L4306, L4307, L4308 );
nand2 U1932 ( L4315, L4316, L4317 );
nand2 U1933 ( L4325, L4326, L4327 );
nand2 U1934 ( L4334, L4335, L4336 );
nand2 U1935 ( L4342, L4343, L4344 );
nand2 U1936 ( L4350, L4351, L4352 );
nand2 U1937 ( L4353, L4354, L4355 );
inv U1938 ( L4531, L4535 );
inv U1939 ( L4540, L4544 );
inv U1940 ( L4554, L4558 );
nand2 U1941 ( L4561, L4562, L4563 );
nand2 U1942 ( L4570, L4571, L4572 );
nand2 U1943 ( L4575, L4576, L4577 );
nand2 U1944 ( L4584, L4585, L4586 );
nand2 U1945 ( L4593, L4594, L4595 );
buffer U1946 ( L4549, L4598 );
buffer U1947 ( L4549, L4602 );
buffer U1948 ( L1921, L4716 );
buffer U1949 ( L1859, L4724 );
buffer U1950 ( L1869, L4732 );
buffer U1951 ( L1885, L4740 );
buffer U1952 ( L1903, L4748 );
buffer U1953 ( L1093, L4756 );
buffer U1954 ( L1026, L4764 );
buffer U1955 ( L1038, L4772 );
buffer U1956 ( L1055, L4780 );
buffer U1957 ( L1074, L4788 );
nand2 U1958 ( L4937, L4938, L4939 );
nand2 U1959 ( L4978, L4979, L4980 );
buffer U1960 ( L895, L5044 );
buffer U1961 ( L853, L5054 );
buffer U1962 ( L792, L5064 );
buffer U1963 ( L827, L5074 );
buffer U1964 ( L805, L5084 );
buffer U1965 ( L805, L5094 );
buffer U1966 ( L895, L5132 );
buffer U1967 ( L853, L5142 );
buffer U1968 ( L792, L5152 );
buffer U1969 ( L827, L5162 );
inv U1970 ( L5359, L5365 );
inv U1971 ( L5362, L5366 );
buffer U1972 ( L1687, L5488 );
buffer U1973 ( L1573, L5498 );
buffer U1974 ( L1546, L5508 );
buffer U1975 ( L1556, L5518 );
buffer U1976 ( L1687, L5546 );
buffer U1977 ( L1573, L5556 );
buffer U1978 ( L1546, L5566 );
buffer U1979 ( L1556, L5576 );
buffer U1980 ( L1695, L5614 );
buffer U1981 ( L1655, L5624 );
buffer U1982 ( L1598, L5634 );
buffer U1983 ( L1630, L5644 );
buffer U1984 ( L1609, L5654 );
buffer U1985 ( L1609, L5664 );
buffer U1986 ( L1695, L5702 );
buffer U1987 ( L1655, L5712 );
buffer U1988 ( L1598, L5722 );
buffer U1989 ( L1630, L5732 );
buffer U1990 ( L1795, L5820 );
buffer U1991 ( L1795, L5828 );
buffer U1992 ( L1805, L5836 );
buffer U1993 ( L1805, L5844 );
buffer U1994 ( L1822, L5852 );
buffer U1995 ( L1822, L5860 );
inv U1996 ( L6115, L6121 );
inv U1997 ( L6173, L6179 );
buffer U1998 ( L2724, L6261 );
inv U1999 ( L7353, L7359 );
inv U2000 ( L7356, L7360 );
inv U2001 ( L7337, L7343 );
inv U2002 ( L7340, L7344 );
nand2 U2003 ( L6763, L6764, L6809 );
nand2 U2004 ( L6753, L6754, L6812 );
nand2 U2005 ( L6807, L6808, L6819 );
nand2 U2006 ( L6797, L6798, L6822 );
inv U2007 ( L6983, L6989 );
inv U2008 ( L7129, L7135 );
nand2 U2009 ( L7291, L7292, L7345 );
nand2 U2010 ( L7281, L7282, L7348 );
inv U2011 ( L7595, L7601 );
inv U2012 ( L7598, L7602 );
nand2 U2013 ( L7549, L7550, L7603 );
nand2 U2014 ( L7539, L7540, L7606 );
nand2 U2015 ( L7593, L7594, L7611 );
nand2 U2016 ( L7583, L7584, L7614 );
or5 U2017 ( L802, L925, L926, L927, L928, L929 );
or2 U2018 ( L868, L949, L950 );
or5 U2019 ( L1035, L1125, L1126, L1127, L1128, L1129 );
or4 U2020 ( L1553, L1705, L1706, L1707, L1708 );
or2 U2021 ( L1584, L1714, L1715 );
or5 U2022 ( L1606, L1722, L1723, L1724, L1725, L1726 );
or2 U2023 ( L1669, L1745, L1746 );
or4 U2024 ( L1802, L1938, L1939, L1940, L1941 );
or5 U2025 ( L1866, L1953, L1954, L1955, L1956, L1957 );
nand2 U2026 ( L5929, L5936, L2471 );
nand2 U2027 ( L6049, L6056, L2741 );
or4 U2028 ( L2962, L3025, L3026, L3027, L3028 );
or5 U2029 ( L2989, L3030, L3031, L3032, L3033, L3034 );
or5 U2030 ( L3183, L3231, L3232, L3233, L3234, L3235 );
or4 U2031 ( L845, L944, L945, L946, L5014 );
or5 U2032 ( L821, L937, L938, L939, L940, L5034 );
nor3 U2033 ( L845, L947, L948, L5102 );
nor4 U2034 ( L821, L941, L942, L943, L5122 );
nand2 U2035 ( L5362, L5365, L5367 );
nand2 U2036 ( L5359, L5366, L5368 );
or4 U2037 ( L1567, L1709, L1710, L1711, L5478 );
nor3 U2038 ( L1567, L1712, L1713, L5536 );
or4 U2039 ( L1647, L1740, L1741, L1742, L5584 );
or5 U2040 ( L1624, L1733, L1734, L1735, L1736, L5604 );
nor3 U2041 ( L1647, L1743, L1744, L5672 );
nor4 U2042 ( L1624, L1737, L1738, L1739, L5692 );
or4 U2043 ( L1816, L1942, L1943, L1944, L5817 );
nor3 U2044 ( L1816, L1945, L1946, L5825 );
or3 U2045 ( L1834, L1947, L1948, L5833 );
nor2 U2046 ( L1834, L1949, L5841 );
nand2 U2047 ( L7356, L7359, L6340 );
nand2 U2048 ( L7353, L7360, L6341 );
nand2 U2049 ( L7340, L7343, L6350 );
nand2 U2050 ( L7337, L7344, L6351 );
nand2 U2051 ( L7598, L7601, L7436 );
nand2 U2052 ( L7595, L7602, L7437 );
inv U2053 ( L4716, L4720 );
inv U2054 ( L4724, L4728 );
inv U2055 ( L4732, L4736 );
inv U2056 ( L4740, L4744 );
inv U2057 ( L4748, L4752 );
inv U2058 ( L4756, L4760 );
inv U2059 ( L4764, L4768 );
inv U2060 ( L4772, L4776 );
inv U2061 ( L4780, L4784 );
inv U2062 ( L4788, L4792 );
inv U2063 ( L3344, L3350 );
inv U2064 ( L2400, L2406 );
inv U2065 ( L920, L924 );
inv U2066 ( L5084, L5088 );
inv U2067 ( L5094, L5098 );
and2 U2068 ( L902, L920, L997 );
and2 U2069 ( L1108, L1122, L1146 );
inv U2070 ( L1284, L1287 );
inv U2071 ( L1288, L1291 );
inv U2072 ( L1292, L1295 );
inv U2073 ( L1296, L1299 );
inv U2074 ( L1300, L1303 );
inv U2075 ( L1304, L1307 );
and3 U2076 ( L1226, L1217, L1284, L1309 );
and3 U2077 ( L1230, L1221, L1288, L1312 );
and3 U2078 ( L1249, L1240, L1292, L1315 );
and3 U2079 ( L1253, L1244, L1296, L1318 );
and3 U2080 ( L1272, L1263, L1300, L1321 );
and3 U2081 ( L1276, L1267, L1304, L1324 );
inv U2082 ( L1718, L1721 );
inv U2083 ( L5518, L5522 );
inv U2084 ( L5576, L5580 );
inv U2085 ( L5654, L5658 );
inv U2086 ( L5664, L5668 );
and2 U2087 ( L1702, L1718, L1788 );
and2 U2088 ( L1935, L1950, L1974 );
inv U2089 ( L5820, L5824 );
inv U2090 ( L5828, L5832 );
inv U2091 ( L5836, L5840 );
inv U2092 ( L5844, L5848 );
nand2 U2093 ( L5852, L5855, L1999 );
inv U2094 ( L5852, L5856 );
nand2 U2095 ( L5860, L5863, L2003 );
inv U2096 ( L5860, L5864 );
nand2 U2097 ( L2470, L2471, L2472 );
and4 U2098 ( L2354, L2400, L2372, L2343, L2487 );
and2 U2099 ( L2343, L2366, L2492 );
and3 U2100 ( L2354, L2343, L2384, L2493 );
and4 U2101 ( L2372, L2343, L2391, L2354, L2494 );
and2 U2102 ( L2354, L2384, L2500 );
and3 U2103 ( L2372, L2391, L2354, L2501 );
and3 U2104 ( L2400, L2372, L2354, L2502 );
and2 U2105 ( L2354, L2384, L2503 );
and3 U2106 ( L2391, L2372, L2354, L2504 );
and2 U2107 ( L2372, L2391, L2505 );
and2 U2108 ( L2400, L2372, L2506 );
and2 U2109 ( L2372, L2391, L2507 );
and2 U2110 ( L2409, L2431, L2511 );
and3 U2111 ( L2420, L2409, L2448, L2512 );
and4 U2112 ( L2436, L2409, L2465, L2420, L2513 );
and5 U2113 ( L2454, L2436, L2409, L2481, L2420, L2514 );
and2 U2114 ( L2420, L2448, L2518 );
and3 U2115 ( L2436, L2465, L2420, L2519 );
and4 U2116 ( L2454, L2436, L2481, L2420, L2520 );
and2 U2117 ( L2465, L2436, L2523 );
and3 U2118 ( L2454, L2436, L2481, L2524 );
and2 U2119 ( L2454, L2481, L2527 );
nand2 U2120 ( L2740, L2741, L2742 );
and4 U2121 ( L2734, L2618, L2600, L2589, L2749 );
and2 U2122 ( L2589, L2612, L2754 );
and3 U2123 ( L2600, L2589, L2629, L2755 );
and4 U2124 ( L2618, L2589, L2635, L2600, L2756 );
and2 U2125 ( L2600, L2629, L2762 );
and3 U2126 ( L2618, L2635, L2600, L2763 );
and3 U2127 ( L2734, L2618, L2600, L2764 );
and2 U2128 ( L2600, L2629, L2765 );
and3 U2129 ( L2618, L2635, L2600, L2766 );
and2 U2130 ( L2618, L2635, L2767 );
and2 U2131 ( L2643, L2670, L2776 );
and3 U2132 ( L2655, L2643, L2693, L2777 );
and4 U2133 ( L2676, L2643, L2715, L2655, L2778 );
and5 U2134 ( L2701, L2676, L2643, L2724, L2655, L2779 );
and2 U2135 ( L2655, L2693, L2788 );
and3 U2136 ( L2676, L2715, L2655, L2789 );
and4 U2137 ( L2701, L2676, L2724, L2655, L2790 );
and2 U2138 ( L2655, L2693, L2792 );
and3 U2139 ( L2676, L2715, L2655, L2793 );
and4 U2140 ( L2701, L2676, L2724, L2655, L2794 );
and2 U2141 ( L2676, L2715, L2795 );
and3 U2142 ( L2701, L2676, L2724, L2796 );
and2 U2143 ( L2676, L2715, L2798 );
and3 U2144 ( L2701, L2676, L2724, L2799 );
and2 U2145 ( L2701, L2724, L2800 );
and2 U2146 ( L2734, L2618, L2804 );
and2 U2147 ( L3022, L3029, L3035 );
and2 U2148 ( L3022, L3034, L3045 );
and4 U2149 ( L3119, L3071, L3062, L3052, L3123 );
and2 U2150 ( L3052, L3068, L3128 );
and3 U2151 ( L3062, L3052, L3076, L3129 );
and4 U2152 ( L3071, L3052, L3079, L3062, L3130 );
and5 U2153 ( L3122, L3110, L3102, L3093, L3082, L3136 );
and2 U2154 ( L3082, L3099, L3139 );
and3 U2155 ( L3093, L3082, L3107, L3140 );
and4 U2156 ( L3102, L3082, L3114, L3093, L3141 );
and5 U2157 ( L3110, L3102, L3082, L3116, L3093, L3142 );
and2 U2158 ( L3216, L3228, L3249 );
and4 U2159 ( L3295, L3344, L3314, L3283, L3431 );
and2 U2160 ( L3283, L3308, L3434 );
and3 U2161 ( L3295, L3283, L3327, L3435 );
and4 U2162 ( L3314, L3283, L3335, L3295, L3436 );
and2 U2163 ( L3295, L3327, L3438 );
and3 U2164 ( L3314, L3335, L3295, L3439 );
and3 U2165 ( L3344, L3314, L3295, L3440 );
and2 U2166 ( L3295, L3327, L3441 );
and3 U2167 ( L3335, L3314, L3295, L3442 );
and2 U2168 ( L3314, L3335, L3443 );
and2 U2169 ( L3344, L3314, L3444 );
and2 U2170 ( L3314, L3335, L3445 );
and5 U2171 ( L3365, L3417, L3381, L3353, L3399, L3446 );
and2 U2172 ( L3353, L3376, L3449 );
and3 U2173 ( L3365, L3353, L3393, L3450 );
and4 U2174 ( L3381, L3353, L3410, L3365, L3451 );
and5 U2175 ( L3399, L3381, L3353, L3425, L3365, L3452 );
and2 U2176 ( L3365, L3393, L3456 );
and3 U2177 ( L3381, L3410, L3365, L3457 );
and4 U2178 ( L3399, L3381, L3425, L3365, L3458 );
and2 U2179 ( L3410, L3381, L3460 );
and3 U2180 ( L3399, L3381, L3425, L3461 );
and2 U2181 ( L3399, L3425, L3463 );
inv U2182 ( L3527, L3531 );
inv U2183 ( L3536, L3540 );
inv U2184 ( L3550, L3554 );
inv U2185 ( L3559, L3563 );
inv U2186 ( L3571, L3574 );
inv U2187 ( L3575, L3578 );
buffer U2188 ( L3545, L3579 );
buffer U2189 ( L3545, L3583 );
buffer U2190 ( L3568, L3587 );
buffer U2191 ( L3568, L3591 );
and3 U2192 ( L3513, L3504, L3571, L3596 );
and3 U2193 ( L3517, L3508, L3575, L3599 );
and4 U2194 ( L3989, L3874, L3856, L3845, L4004 );
and2 U2195 ( L3845, L3868, L4007 );
and3 U2196 ( L3856, L3845, L3885, L4008 );
and4 U2197 ( L3874, L3845, L3891, L3856, L4009 );
and2 U2198 ( L3856, L3885, L4011 );
and3 U2199 ( L3874, L3891, L3856, L4012 );
and3 U2200 ( L3989, L3874, L3856, L4013 );
and2 U2201 ( L3856, L3885, L4014 );
and3 U2202 ( L3874, L3891, L3856, L4015 );
and2 U2203 ( L3874, L3891, L4016 );
and5 U2204 ( L3997, L3957, L3932, L3911, L3899, L4020 );
and2 U2205 ( L3899, L3926, L4024 );
and3 U2206 ( L3911, L3899, L3949, L4025 );
and4 U2207 ( L3932, L3899, L3971, L3911, L4026 );
and5 U2208 ( L3957, L3932, L3899, L3979, L3911, L4027 );
and2 U2209 ( L3911, L3949, L4035 );
and3 U2210 ( L3932, L3971, L3911, L4036 );
and4 U2211 ( L3957, L3932, L3979, L3911, L4037 );
and4 U2212 ( L3997, L3932, L3911, L3957, L4038 );
and2 U2213 ( L3911, L3949, L4039 );
and3 U2214 ( L3932, L3971, L3911, L4040 );
and4 U2215 ( L3957, L3932, L3979, L3911, L4041 );
and2 U2216 ( L3932, L3971, L4042 );
and3 U2217 ( L3957, L3932, L3979, L4043 );
and3 U2218 ( L3997, L3932, L3957, L4044 );
and2 U2219 ( L3932, L3971, L4045 );
and3 U2220 ( L3957, L3932, L3979, L4046 );
and2 U2221 ( L3957, L3979, L4047 );
and2 U2222 ( L3989, L3874, L4051 );
and2 U2223 ( L3997, L3957, L4052 );
inv U2224 ( L4180, L4184 );
inv U2225 ( L4189, L4193 );
buffer U2226 ( L4198, L4247 );
buffer U2227 ( L4198, L4251 );
buffer U2228 ( L4221, L4255 );
buffer U2229 ( L4221, L4259 );
inv U2230 ( L4263, L4266 );
inv U2231 ( L4267, L4270 );
and3 U2232 ( L4235, L4226, L4263, L4284 );
and3 U2233 ( L4239, L4230, L4267, L4287 );
and4 U2234 ( L4352, L4308, L4300, L4291, L4356 );
and2 U2235 ( L4291, L4305, L4361 );
and3 U2236 ( L4300, L4291, L4312, L4362 );
and4 U2237 ( L4308, L4291, L4314, L4300, L4363 );
and5 U2238 ( L4355, L4344, L4336, L4327, L4317, L4369 );
and2 U2239 ( L4317, L4333, L4372 );
and3 U2240 ( L4327, L4317, L4341, L4373 );
and4 U2241 ( L4336, L4317, L4348, L4327, L4374 );
and5 U2242 ( L4344, L4336, L4317, L4349, L4327, L4375 );
inv U2243 ( L4563, L4567 );
inv U2244 ( L4577, L4581 );
inv U2245 ( L4586, L4590 );
inv U2246 ( L4598, L4601 );
inv U2247 ( L4602, L4605 );
buffer U2248 ( L4572, L4606 );
buffer U2249 ( L4572, L4610 );
buffer U2250 ( L4595, L4614 );
buffer U2251 ( L4595, L4618 );
and3 U2252 ( L4540, L4531, L4598, L4623 );
and3 U2253 ( L4544, L4535, L4602, L4626 );
buffer U2254 ( L3417, L4796 );
buffer U2255 ( L3353, L4804 );
buffer U2256 ( L3365, L4812 );
buffer U2257 ( L3381, L4820 );
buffer U2258 ( L3399, L4828 );
buffer U2259 ( L2409, L4844 );
buffer U2260 ( L2420, L4852 );
buffer U2261 ( L2436, L4860 );
buffer U2262 ( L2454, L4868 );
inv U2263 ( L4939, L4945 );
nand2 U2264 ( L4939, L4946, L4948 );
inv U2265 ( L4980, L4986 );
nand2 U2266 ( L4980, L4987, L4989 );
inv U2267 ( L5044, L5048 );
inv U2268 ( L5054, L5058 );
inv U2269 ( L5064, L5068 );
inv U2270 ( L5074, L5078 );
inv U2271 ( L5162, L5166 );
inv U2272 ( L5132, L5136 );
inv U2273 ( L5142, L5146 );
inv U2274 ( L5152, L5156 );
nand2 U2275 ( L5367, L5368, L5388 );
inv U2276 ( L5488, L5492 );
inv U2277 ( L5498, L5502 );
inv U2278 ( L5508, L5512 );
inv U2279 ( L5546, L5550 );
inv U2280 ( L5556, L5560 );
inv U2281 ( L5566, L5570 );
inv U2282 ( L5614, L5618 );
inv U2283 ( L5624, L5628 );
inv U2284 ( L5634, L5638 );
inv U2285 ( L5644, L5648 );
inv U2286 ( L5732, L5736 );
inv U2287 ( L5702, L5706 );
inv U2288 ( L5712, L5716 );
inv U2289 ( L5722, L5726 );
buffer U2290 ( L2343, L5940 );
buffer U2291 ( L2343, L5948 );
buffer U2292 ( L2354, L5956 );
buffer U2293 ( L2354, L5964 );
buffer U2294 ( L2372, L5972 );
buffer U2295 ( L2372, L5980 );
buffer U2296 ( L2734, L6080 );
buffer U2297 ( L2618, L6090 );
buffer U2298 ( L2589, L6100 );
buffer U2299 ( L2600, L6110 );
buffer U2300 ( L2734, L6138 );
buffer U2301 ( L2618, L6148 );
buffer U2302 ( L2589, L6158 );
buffer U2303 ( L2600, L6168 );
buffer U2304 ( L2701, L6216 );
buffer U2305 ( L2643, L6226 );
buffer U2306 ( L2676, L6236 );
buffer U2307 ( L2655, L6246 );
buffer U2308 ( L2655, L6256 );
inv U2309 ( L6261, L6267 );
buffer U2310 ( L2701, L6304 );
buffer U2311 ( L2643, L6314 );
buffer U2312 ( L2676, L6324 );
nand2 U2313 ( L6340, L6341, L6342 );
nand2 U2314 ( L6350, L6351, L6352 );
inv U2315 ( L7345, L7351 );
inv U2316 ( L7348, L7352 );
buffer U2317 ( L3283, L6642 );
buffer U2318 ( L3283, L6650 );
buffer U2319 ( L3295, L6658 );
buffer U2320 ( L3295, L6666 );
buffer U2321 ( L3314, L6674 );
buffer U2322 ( L3314, L6682 );
inv U2323 ( L6809, L6815 );
inv U2324 ( L6812, L6816 );
inv U2325 ( L6819, L6825 );
inv U2326 ( L6822, L6826 );
buffer U2327 ( L3989, L6948 );
buffer U2328 ( L3874, L6958 );
buffer U2329 ( L3845, L6968 );
buffer U2330 ( L3856, L6978 );
buffer U2331 ( L3989, L7006 );
buffer U2332 ( L3874, L7016 );
buffer U2333 ( L3845, L7026 );
buffer U2334 ( L3856, L7036 );
buffer U2335 ( L3997, L7074 );
buffer U2336 ( L3957, L7084 );
buffer U2337 ( L3899, L7094 );
buffer U2338 ( L3932, L7104 );
buffer U2339 ( L3911, L7114 );
buffer U2340 ( L3911, L7124 );
buffer U2341 ( L3997, L7162 );
buffer U2342 ( L3957, L7172 );
buffer U2343 ( L3899, L7182 );
buffer U2344 ( L3932, L7192 );
nand2 U2345 ( L7436, L7437, L7438 );
inv U2346 ( L7611, L7617 );
inv U2347 ( L7614, L7618 );
inv U2348 ( L7603, L7609 );
inv U2349 ( L7606, L7610 );
and2 U2350 ( L1129, L1108, L1151 );
and2 U2351 ( L902, L929, L1002 );
inv U2352 ( L929, L933 );
and3 U2353 ( L1221, L1226, L1287, L1308 );
and3 U2354 ( L1217, L1230, L1291, L1311 );
and3 U2355 ( L1244, L1249, L1295, L1314 );
and3 U2356 ( L1240, L1253, L1299, L1317 );
and3 U2357 ( L1267, L1272, L1303, L1320 );
and3 U2358 ( L1263, L1276, L1307, L1323 );
inv U2359 ( L1726, L1730 );
and2 U2360 ( L1702, L1726, L1789 );
and2 U2361 ( L1957, L1935, L1981 );
inv U2362 ( L5817, L5823 );
nand2 U2363 ( L5817, L5824, L1986 );
inv U2364 ( L5825, L5831 );
nand2 U2365 ( L5825, L5832, L1989 );
inv U2366 ( L5833, L5839 );
nand2 U2367 ( L5833, L5840, L1993 );
inv U2368 ( L5841, L5847 );
nand2 U2369 ( L5841, L5848, L1996 );
nand2 U2370 ( L5849, L5856, L2000 );
nand2 U2371 ( L5857, L5864, L2004 );
or4 U2372 ( L2351, L2492, L2493, L2494, L2495 );
or5 U2373 ( L2417, L2511, L2512, L2513, L2514, L2515 );
or4 U2374 ( L2597, L2754, L2755, L2756, L2757 );
or2 U2375 ( L2629, L2767, L2768 );
or5 U2376 ( L2652, L2776, L2777, L2778, L2779, L2780 );
or2 U2377 ( L2715, L2800, L2801 );
or2 U2378 ( L3028, L3045, L3046 );
or4 U2379 ( L3059, L3128, L3129, L3130, L3131 );
or5 U2380 ( L3090, L3139, L3140, L3141, L3142, L3143 );
inv U2381 ( L3235, L3238 );
and2 U2382 ( L3216, L3235, L3258 );
or4 U2383 ( L3292, L3434, L3435, L3436, L3437 );
or5 U2384 ( L3362, L3449, L3450, L3451, L3452, L3453 );
and3 U2385 ( L3508, L3513, L3574, L3595 );
and3 U2386 ( L3504, L3517, L3578, L3598 );
or4 U2387 ( L3853, L4007, L4008, L4009, L4010 );
or2 U2388 ( L3885, L4016, L4017 );
or5 U2389 ( L3908, L4024, L4025, L4026, L4027, L4028 );
or2 U2390 ( L3971, L4047, L4048 );
and3 U2391 ( L4230, L4235, L4266, L4283 );
and3 U2392 ( L4226, L4239, L4270, L4286 );
or4 U2393 ( L4297, L4361, L4362, L4363, L4364 );
or5 U2394 ( L4324, L4372, L4373, L4374, L4375, L4376 );
and3 U2395 ( L4535, L4540, L4601, L4622 );
and3 U2396 ( L4531, L4544, L4605, L4625 );
nand2 U2397 ( L4942, L4945, L4947 );
nand2 U2398 ( L4983, L4986, L4988 );
inv U2399 ( L5014, L5018 );
nand2 U2400 ( L5014, L5017, L5019 );
or2 U2401 ( L950, L956, L5024 );
inv U2402 ( L5034, L5038 );
inv U2403 ( L5102, L5106 );
nand2 U2404 ( L5102, L5105, L5107 );
inv U2405 ( L950, L5112 );
inv U2406 ( L5122, L5126 );
or2 U2407 ( L1715, L1749, L5468 );
inv U2408 ( L5478, L5482 );
inv U2409 ( L1715, L5526 );
inv U2410 ( L5536, L5540 );
inv U2411 ( L5584, L5588 );
nand2 U2412 ( L5584, L5587, L5589 );
or2 U2413 ( L1746, L1750, L5594 );
inv U2414 ( L5604, L5608 );
inv U2415 ( L5672, L5676 );
nand2 U2416 ( L5672, L5675, L5677 );
inv U2417 ( L1746, L5682 );
inv U2418 ( L5692, L5696 );
or4 U2419 ( L2366, L2500, L2501, L2502, L5937 );
nor3 U2420 ( L2366, L2503, L2504, L5945 );
or3 U2421 ( L2384, L2505, L2506, L5953 );
nor2 U2422 ( L2384, L2507, L5961 );
or4 U2423 ( L2612, L2762, L2763, L2764, L6070 );
nor3 U2424 ( L2612, L2765, L2766, L6128 );
nor3 U2425 ( L2693, L2798, L2799, L6264 );
nor4 U2426 ( L2670, L2792, L2793, L2794, L6284 );
nand2 U2427 ( L7348, L7351, L6360 );
nand2 U2428 ( L7345, L7352, L6361 );
or4 U2429 ( L3308, L3438, L3439, L3440, L6639 );
nor3 U2430 ( L3308, L3441, L3442, L6647 );
or3 U2431 ( L3327, L3443, L3444, L6655 );
nor2 U2432 ( L3327, L3445, L6663 );
nand2 U2433 ( L6812, L6815, L6817 );
nand2 U2434 ( L6809, L6816, L6818 );
nand2 U2435 ( L6822, L6825, L6827 );
nand2 U2436 ( L6819, L6826, L6828 );
or4 U2437 ( L3868, L4011, L4012, L4013, L6938 );
nor3 U2438 ( L3868, L4014, L4015, L6996 );
or4 U2439 ( L3949, L4042, L4043, L4044, L7044 );
or5 U2440 ( L3926, L4035, L4036, L4037, L4038, L7064 );
nor3 U2441 ( L3949, L4045, L4046, L7132 );
nor4 U2442 ( L3926, L4039, L4040, L4041, L7152 );
nand2 U2443 ( L7614, L7617, L7446 );
nand2 U2444 ( L7611, L7618, L7447 );
nand2 U2445 ( L7606, L7609, L7456 );
nand2 U2446 ( L7603, L7610, L7457 );
or2 U2447 ( L1117, L1151, L241 );
or2 U2448 ( L908, L1002, L265 );
nand2 U2449 ( L2003, L2004, L2005 );
inv U2450 ( L4796, L4800 );
inv U2451 ( L4804, L4808 );
inv U2452 ( L4812, L4816 );
inv U2453 ( L4820, L4824 );
inv U2454 ( L4828, L4832 );
inv U2455 ( L4844, L4848 );
inv U2456 ( L4852, L4856 );
inv U2457 ( L4860, L4864 );
inv U2458 ( L4868, L4872 );
nor2 U2459 ( L1308, L1309, L1310 );
nor2 U2460 ( L1311, L1312, L1313 );
nor2 U2461 ( L1314, L1315, L1316 );
nor2 U2462 ( L1317, L1318, L1319 );
nor2 U2463 ( L1320, L1321, L1322 );
nor2 U2464 ( L1323, L1324, L1325 );
inv U2465 ( L5388, L5392 );
or2 U2466 ( L1708, L1789, L1790 );
or2 U2467 ( L1941, L1981, L1982 );
nand2 U2468 ( L5820, L5823, L1985 );
nand2 U2469 ( L5828, L5831, L1988 );
nand2 U2470 ( L5836, L5839, L1992 );
nand2 U2471 ( L5844, L5847, L1995 );
nand2 U2472 ( L1999, L2000, L2001 );
inv U2473 ( L2487, L2491 );
and5 U2474 ( L2420, L2472, L2436, L2409, L2454, L2508 );
and5 U2475 ( L4526, L2472, L2436, L2454, L2420, L2522 );
and4 U2476 ( L4526, L2472, L2436, L2454, L2526 );
and3 U2477 ( L4526, L2472, L2454, L2529 );
and2 U2478 ( L4526, L2472, L2531 );
inv U2479 ( L5940, L5944 );
inv U2480 ( L5948, L5952 );
inv U2481 ( L5956, L5960 );
inv U2482 ( L5964, L5968 );
nand2 U2483 ( L5972, L5975, L2555 );
inv U2484 ( L5972, L5976 );
nand2 U2485 ( L5980, L5983, L2559 );
inv U2486 ( L5980, L5984 );
inv U2487 ( L2749, L2753 );
and5 U2488 ( L2742, L2701, L2676, L2655, L2643, L2771 );
and4 U2489 ( L2742, L2676, L2655, L2701, L2791 );
and3 U2490 ( L2742, L2676, L2701, L2797 );
and2 U2491 ( L2742, L2701, L2807 );
inv U2492 ( L6110, L6114 );
inv U2493 ( L6168, L6172 );
inv U2494 ( L6246, L6250 );
inv U2495 ( L6256, L6260 );
inv U2496 ( L6342, L6346 );
inv U2497 ( L6352, L6356 );
inv U2498 ( L3123, L3127 );
and2 U2499 ( L3123, L3136, L3156 );
or2 U2500 ( L3223, L3258, L3259 );
and2 U2501 ( L3431, L3446, L3466 );
inv U2502 ( L6642, L6646 );
inv U2503 ( L6650, L6654 );
inv U2504 ( L6658, L6662 );
inv U2505 ( L6666, L6670 );
nand2 U2506 ( L6674, L6677, L3483 );
inv U2507 ( L6674, L6678 );
nand2 U2508 ( L6682, L6685, L3487 );
inv U2509 ( L6682, L6686 );
inv U2510 ( L3579, L3582 );
inv U2511 ( L3583, L3586 );
inv U2512 ( L3587, L3590 );
inv U2513 ( L3591, L3594 );
nor2 U2514 ( L3595, L3596, L3597 );
nor2 U2515 ( L3598, L3599, L3600 );
and3 U2516 ( L3536, L3527, L3579, L3602 );
and3 U2517 ( L3540, L3531, L3583, L3605 );
and3 U2518 ( L3559, L3550, L3587, L3608 );
and3 U2519 ( L3563, L3554, L3591, L3611 );
inv U2520 ( L4020, L4023 );
inv U2521 ( L6978, L6982 );
inv U2522 ( L7036, L7040 );
inv U2523 ( L7114, L7118 );
inv U2524 ( L7124, L7128 );
and2 U2525 ( L4004, L4020, L4089 );
inv U2526 ( L4247, L4250 );
inv U2527 ( L4251, L4254 );
inv U2528 ( L4255, L4258 );
inv U2529 ( L4259, L4262 );
and3 U2530 ( L4189, L4180, L4247, L4272 );
and3 U2531 ( L4193, L4184, L4251, L4275 );
and3 U2532 ( L4212, L4203, L4255, L4278 );
and3 U2533 ( L4216, L4207, L4259, L4281 );
nor2 U2534 ( L4283, L4284, L4285 );
nor2 U2535 ( L4286, L4287, L4288 );
inv U2536 ( L4356, L4360 );
nand2 U2537 ( L4369, L89, L4380 );
and2 U2538 ( L4356, L4369, L4386 );
inv U2539 ( L7438, L7442 );
inv U2540 ( L4606, L4609 );
inv U2541 ( L4610, L4613 );
inv U2542 ( L4614, L4617 );
inv U2543 ( L4618, L4621 );
nor2 U2544 ( L4622, L4623, L4624 );
nor2 U2545 ( L4625, L4626, L4627 );
and3 U2546 ( L4563, L4554, L4606, L4629 );
and3 U2547 ( L4567, L4558, L4610, L4632 );
and3 U2548 ( L4586, L4577, L4614, L4635 );
and3 U2549 ( L4590, L4581, L4618, L4638 );
buffer U2550 ( L2472, L4836 );
nand2 U2551 ( L4947, L4948, L4949 );
nand2 U2552 ( L4988, L4989, L4990 );
nand2 U2553 ( L5011, L5018, L5020 );
nand2 U2554 ( L5099, L5106, L5108 );
nand2 U2555 ( L5581, L5588, L5590 );
nand2 U2556 ( L5669, L5676, L5678 );
inv U2557 ( L6080, L6084 );
inv U2558 ( L6090, L6094 );
inv U2559 ( L6100, L6104 );
inv U2560 ( L6138, L6142 );
inv U2561 ( L6148, L6152 );
inv U2562 ( L6158, L6162 );
buffer U2563 ( L2742, L6206 );
inv U2564 ( L6216, L6220 );
inv U2565 ( L6226, L6230 );
inv U2566 ( L6236, L6240 );
inv U2567 ( L6324, L6328 );
buffer U2568 ( L2742, L6294 );
inv U2569 ( L6304, L6308 );
inv U2570 ( L6314, L6318 );
nand2 U2571 ( L6360, L6361, L6362 );
nand2 U2572 ( L6817, L6818, L6840 );
nand2 U2573 ( L6827, L6828, L6848 );
inv U2574 ( L6948, L6952 );
inv U2575 ( L6958, L6962 );
inv U2576 ( L6968, L6972 );
inv U2577 ( L7006, L7010 );
inv U2578 ( L7016, L7020 );
inv U2579 ( L7026, L7030 );
inv U2580 ( L7074, L7078 );
inv U2581 ( L7084, L7088 );
inv U2582 ( L7094, L7098 );
inv U2583 ( L7104, L7108 );
inv U2584 ( L7192, L7196 );
inv U2585 ( L7162, L7166 );
inv U2586 ( L7172, L7176 );
inv U2587 ( L7182, L7186 );
nand2 U2588 ( L7446, L7447, L7448 );
nand2 U2589 ( L7456, L7457, L7458 );
and2 U2590 ( L3046, L3249, L254 );
and2 U2591 ( L3046, L3249, L260 );
nand2 U2592 ( L1985, L1986, L1987 );
nand2 U2593 ( L1992, L1993, L1994 );
inv U2594 ( L2001, L2002 );
and2 U2595 ( L933, L924, L962 );
and2 U2596 ( L1730, L1721, L1751 );
nand2 U2597 ( L1988, L1989, L1990 );
nand2 U2598 ( L1995, L1996, L1997 );
inv U2599 ( L2495, L2499 );
and2 U2600 ( L2515, L2487, L2536 );
inv U2601 ( L5937, L5943 );
nand2 U2602 ( L5937, L5944, L2542 );
inv U2603 ( L5945, L5951 );
nand2 U2604 ( L5945, L5952, L2545 );
inv U2605 ( L5953, L5959 );
nand2 U2606 ( L5953, L5960, L2549 );
inv U2607 ( L5961, L5967 );
nand2 U2608 ( L5961, L5968, L2552 );
nand2 U2609 ( L5969, L5976, L2556 );
nand2 U2610 ( L5977, L5984, L2560 );
inv U2611 ( L2757, L2761 );
inv U2612 ( L2780, L2784 );
and2 U2613 ( L2749, L2780, L2853 );
inv U2614 ( L3131, L3135 );
inv U2615 ( L3143, L3146 );
and2 U2616 ( L3123, L3143, L3163 );
and2 U2617 ( L3453, L3431, L3467 );
inv U2618 ( L6639, L6645 );
nand2 U2619 ( L6639, L6646, L3470 );
inv U2620 ( L6647, L6653 );
nand2 U2621 ( L6647, L6654, L3473 );
inv U2622 ( L6655, L6661 );
nand2 U2623 ( L6655, L6662, L3477 );
inv U2624 ( L6663, L6669 );
nand2 U2625 ( L6663, L6670, L3480 );
nand2 U2626 ( L6671, L6678, L3484 );
nand2 U2627 ( L6679, L6686, L3488 );
and3 U2628 ( L3531, L3536, L3582, L3601 );
and3 U2629 ( L3527, L3540, L3586, L3604 );
and3 U2630 ( L3554, L3559, L3590, L3607 );
and3 U2631 ( L3550, L3563, L3594, L3610 );
inv U2632 ( L4028, L4032 );
and2 U2633 ( L4004, L4028, L4090 );
and3 U2634 ( L4184, L4189, L4250, L4271 );
and3 U2635 ( L4180, L4193, L4254, L4274 );
and3 U2636 ( L4207, L4212, L4258, L4277 );
and3 U2637 ( L4203, L4216, L4262, L4280 );
inv U2638 ( L4364, L4368 );
inv U2639 ( L4376, L4379 );
and2 U2640 ( L4356, L4376, L4387 );
and3 U2641 ( L4558, L4563, L4609, L4628 );
and3 U2642 ( L4554, L4567, L4613, L4631 );
and3 U2643 ( L4581, L4586, L4617, L4634 );
and3 U2644 ( L4577, L4590, L4621, L4637 );
or5 U2645 ( L2431, L2518, L2519, L2520, L2522, L4841 );
or4 U2646 ( L2448, L2523, L2524, L2526, L4849 );
or3 U2647 ( L2465, L2527, L2529, L4857 );
or2 U2648 ( L2481, L2531, L4865 );
nand2 U2649 ( L5019, L5020, L5021 );
inv U2650 ( L5024, L5028 );
nand2 U2651 ( L5107, L5108, L5109 );
inv U2652 ( L5112, L5116 );
nand2 U2653 ( L1313, L1310, L5369 );
nand2 U2654 ( L1319, L1316, L5377 );
nand2 U2655 ( L1325, L1322, L5385 );
inv U2656 ( L5468, L5472 );
nand2 U2657 ( L5468, L5471, L5473 );
inv U2658 ( L5526, L5530 );
nand2 U2659 ( L5526, L5529, L5531 );
nand2 U2660 ( L5589, L5590, L5591 );
inv U2661 ( L5594, L5598 );
nand2 U2662 ( L5677, L5678, L5679 );
inv U2663 ( L5682, L5686 );
or2 U2664 ( L2768, L2804, L6060 );
inv U2665 ( L6070, L6074 );
inv U2666 ( L2768, L6118 );
inv U2667 ( L6128, L6132 );
or4 U2668 ( L2693, L2795, L2796, L2797, L6176 );
or2 U2669 ( L2801, L2807, L6186 );
or5 U2670 ( L2670, L2788, L2789, L2790, L2791, L6196 );
inv U2671 ( L6264, L6268 );
nand2 U2672 ( L6264, L6267, L6269 );
inv U2673 ( L2801, L6274 );
inv U2674 ( L6284, L6288 );
nand2 U2675 ( L4288, L4285, L6337 );
nand2 U2676 ( L3600, L3597, L6829 );
or2 U2677 ( L4017, L4051, L6928 );
inv U2678 ( L6938, L6942 );
inv U2679 ( L4017, L6986 );
inv U2680 ( L6996, L7000 );
inv U2681 ( L7044, L7048 );
nand2 U2682 ( L7044, L7047, L7049 );
or2 U2683 ( L4048, L4052, L7054 );
inv U2684 ( L7064, L7068 );
inv U2685 ( L7132, L7136 );
nand2 U2686 ( L7132, L7135, L7137 );
inv U2687 ( L4048, L7142 );
inv U2688 ( L7152, L7156 );
nand2 U2689 ( L4627, L4624, L7433 );
and2 U2690 ( L1982, L1146, L242 );
nand2 U2691 ( L3135, L3127, L3151 );
and5 U2692 ( L89, L4386, L3156, L3035, L3249, L257 );
and5 U2693 ( L89, L4386, L3156, L3035, L3249, L263 );
and2 U2694 ( L1790, L997, L266 );
inv U2695 ( L1990, L1991 );
inv U2696 ( L1997, L1998 );
nand2 U2697 ( L3487, L3488, L3489 );
nand2 U2698 ( L4836, L4839, L371 );
inv U2699 ( L4836, L4840 );
nand2 U2700 ( L2559, L2560, L2561 );
and2 U2701 ( L2487, L2508, L2532 );
or2 U2702 ( L2495, L2536, L2537 );
nand2 U2703 ( L5940, L5943, L2541 );
nand2 U2704 ( L5948, L5951, L2544 );
nand2 U2705 ( L5956, L5959, L2548 );
nand2 U2706 ( L5964, L5967, L2551 );
nand2 U2707 ( L2555, L2556, L2557 );
and2 U2708 ( L2508, L4526, L2563 );
nand2 U2709 ( L2499, L2491, L2577 );
inv U2710 ( L2771, L2775 );
nand2 U2711 ( L2771, L4526, L2806 );
nand2 U2712 ( L2761, L2753, L2808 );
and2 U2713 ( L2749, L2771, L2852 );
or2 U2714 ( L2757, L2853, L2854 );
inv U2715 ( L6362, L6366 );
nand2 U2716 ( L4368, L4360, L4381 );
or2 U2717 ( L3131, L3163, L3164 );
and4 U2718 ( L89, L4386, L3156, L3035, L3241 );
or2 U2719 ( L3437, L3467, L3468 );
nand2 U2720 ( L6642, L6645, L3469 );
nand2 U2721 ( L6650, L6653, L3472 );
nand2 U2722 ( L6658, L6661, L3476 );
nand2 U2723 ( L6666, L6669, L3479 );
nand2 U2724 ( L3483, L3484, L3485 );
nor2 U2725 ( L3601, L3602, L3603 );
nor2 U2726 ( L3604, L3605, L3606 );
nor2 U2727 ( L3607, L3608, L3609 );
nor2 U2728 ( L3610, L3611, L3612 );
inv U2729 ( L6840, L6844 );
inv U2730 ( L6848, L6852 );
or2 U2731 ( L4010, L4090, L4091 );
nor2 U2732 ( L4271, L4272, L4273 );
nor2 U2733 ( L4274, L4275, L4276 );
nor2 U2734 ( L4277, L4278, L4279 );
nor2 U2735 ( L4280, L4281, L4282 );
and2 U2736 ( L4379, L4380, L4382 );
or2 U2737 ( L4364, L4387, L4388 );
inv U2738 ( L7448, L7452 );
inv U2739 ( L7458, L7462 );
nor2 U2740 ( L4628, L4629, L4630 );
nor2 U2741 ( L4631, L4632, L4633 );
nor2 U2742 ( L4634, L4635, L4636 );
nor2 U2743 ( L4637, L4638, L4639 );
inv U2744 ( L4949, L4955 );
nand2 U2745 ( L4949, L4956, L4958 );
inv U2746 ( L4990, L4996 );
nand2 U2747 ( L4990, L4997, L4999 );
nand2 U2748 ( L5465, L5472, L5474 );
nand2 U2749 ( L5523, L5530, L5532 );
inv U2750 ( L6206, L6210 );
nand2 U2751 ( L6261, L6268, L6270 );
inv U2752 ( L6294, L6298 );
nand2 U2753 ( L7041, L7048, L7050 );
nand2 U2754 ( L7129, L7136, L7138 );
nand2 U2755 ( L3469, L3470, L3471 );
nand2 U2756 ( L3476, L3477, L3478 );
inv U2757 ( L3485, L3486 );
nand2 U2758 ( L4833, L4840, L372 );
nand2 U2759 ( L2541, L2542, L2543 );
nand2 U2760 ( L2548, L2549, L2550 );
inv U2761 ( L2557, L2558 );
inv U2762 ( L4841, L4847 );
nand2 U2763 ( L4841, L4848, L387 );
inv U2764 ( L4849, L4855 );
nand2 U2765 ( L4849, L4856, L390 );
inv U2766 ( L4857, L4863 );
nand2 U2767 ( L4857, L4864, L393 );
inv U2768 ( L4865, L4871 );
nand2 U2769 ( L4865, L4872, L396 );
inv U2770 ( L962, L965 );
inv U2771 ( L5369, L5375 );
nand2 U2772 ( L5369, L5376, L1327 );
inv U2773 ( L5377, L5383 );
nand2 U2774 ( L5377, L5384, L1330 );
inv U2775 ( L5385, L5391 );
nand2 U2776 ( L5385, L5392, L1333 );
inv U2777 ( L1751, L1754 );
nand2 U2778 ( L2544, L2545, L2546 );
nand2 U2779 ( L2551, L2552, L2553 );
or2 U2780 ( L2515, L2563, L2564 );
and2 U2781 ( L2784, L2806, L2809 );
and2 U2782 ( L2784, L2775, L2813 );
inv U2783 ( L6337, L6345 );
nand2 U2784 ( L6337, L6346, L2860 );
nand2 U2785 ( L3472, L3473, L3474 );
nand2 U2786 ( L3479, L3480, L3481 );
inv U2787 ( L6829, L6835 );
nand2 U2788 ( L6829, L6836, L3614 );
and2 U2789 ( L4032, L4023, L4053 );
inv U2790 ( L7433, L7441 );
nand2 U2791 ( L7433, L7442, L4516 );
nand2 U2792 ( L4952, L4955, L4957 );
nand2 U2793 ( L4993, L4996, L4998 );
inv U2794 ( L5021, L5027 );
nand2 U2795 ( L5021, L5028, L5030 );
inv U2796 ( L5109, L5115 );
nand2 U2797 ( L5109, L5116, L5118 );
nand2 U2798 ( L5473, L5474, L5475 );
nand2 U2799 ( L5531, L5532, L5533 );
inv U2800 ( L5591, L5597 );
nand2 U2801 ( L5591, L5598, L5600 );
inv U2802 ( L5679, L5685 );
nand2 U2803 ( L5679, L5686, L5688 );
inv U2804 ( L6060, L6064 );
nand2 U2805 ( L6060, L6063, L6065 );
inv U2806 ( L6118, L6122 );
nand2 U2807 ( L6118, L6121, L6123 );
inv U2808 ( L6176, L6180 );
nand2 U2809 ( L6176, L6179, L6181 );
inv U2810 ( L6186, L6190 );
inv U2811 ( L6196, L6200 );
nand2 U2812 ( L6269, L6270, L6271 );
inv U2813 ( L6274, L6278 );
nand2 U2814 ( L4276, L4273, L6347 );
nand2 U2815 ( L4282, L4279, L6357 );
nand2 U2816 ( L3606, L3603, L6837 );
nand2 U2817 ( L3612, L3609, L6845 );
inv U2818 ( L6928, L6932 );
nand2 U2819 ( L6928, L6931, L6933 );
inv U2820 ( L6986, L6990 );
nand2 U2821 ( L6986, L6989, L6991 );
nand2 U2822 ( L7049, L7050, L7051 );
inv U2823 ( L7054, L7058 );
nand2 U2824 ( L7137, L7138, L7139 );
inv U2825 ( L7142, L7146 );
nand2 U2826 ( L4639, L4636, L7443 );
nand2 U2827 ( L4633, L4630, L7453 );
and3 U2828 ( L3468, L1974, L1146, L243 );
and4 U2829 ( L2537, L3466, L1974, L1146, L244 );
and5 U2830 ( L4526, L2532, L3466, L1974, L1146, L245 );
and3 U2831 ( L3164, L3035, L3249, L255 );
and4 U2832 ( L4388, L3156, L3035, L3249, L256 );
and3 U2833 ( L3164, L3035, L3249, L261 );
and4 U2834 ( L4388, L3156, L3035, L3249, L262 );
and3 U2835 ( L4091, L1788, L997, L267 );
and4 U2836 ( L2854, L4089, L1788, L997, L268 );
and5 U2837 ( L4526, L2852, L4089, L1788, L997, L269 );
inv U2838 ( L3474, L3475 );
inv U2839 ( L3481, L3482 );
nand2 U2840 ( L371, L372, L373 );
inv U2841 ( L2546, L2547 );
inv U2842 ( L2553, L2554 );
nand2 U2843 ( L4844, L4847, L386 );
nand2 U2844 ( L4852, L4855, L389 );
nand2 U2845 ( L4860, L4863, L392 );
nand2 U2846 ( L4868, L4871, L395 );
nand2 U2847 ( L5372, L5375, L1326 );
nand2 U2848 ( L5380, L5383, L1329 );
nand2 U2849 ( L5388, L5391, L1332 );
and2 U2850 ( L4091, L1788, L1436 );
and3 U2851 ( L2854, L4089, L1788, L1440 );
and4 U2852 ( L4526, L2852, L4089, L1788, L1445 );
and2 U2853 ( L2854, L4089, L1450 );
and3 U2854 ( L4526, L2852, L4089, L1454 );
nand2 U2855 ( L6342, L6345, L2859 );
inv U2856 ( L4382, L4385 );
and2 U2857 ( L4382, L4364, L3148 );
and2 U2858 ( L3164, L3035, L3239 );
and3 U2859 ( L4388, L3156, L3035, L3240 );
and2 U2860 ( L3468, L1974, L3265 );
and3 U2861 ( L2537, L3466, L1974, L3267 );
and4 U2862 ( L4526, L2532, L3466, L1974, L3270 );
and2 U2863 ( L2537, L3466, L3274 );
and3 U2864 ( L4526, L2532, L3466, L3277 );
nand2 U2865 ( L6832, L6835, L3613 );
nand2 U2866 ( L7438, L7441, L4515 );
nand2 U2867 ( L4957, L4958, L4959 );
nand2 U2868 ( L4998, L4999, L5000 );
nand2 U2869 ( L5024, L5027, L5029 );
nand2 U2870 ( L5112, L5115, L5117 );
nand2 U2871 ( L5594, L5597, L5599 );
nand2 U2872 ( L5682, L5685, L5687 );
nand2 U2873 ( L6057, L6064, L6066 );
nand2 U2874 ( L6115, L6122, L6124 );
nand2 U2875 ( L6173, L6180, L6182 );
nand2 U2876 ( L6925, L6932, L6934 );
nand2 U2877 ( L6983, L6990, L6992 );
or5 U2878 ( L241, L242, L243, L244, L245, L246 );
or5 U2879 ( L3259, L254, L255, L256, L257, L258 );
or5 U2880 ( L3259, L260, L261, L262, L263, L264 );
or5 U2881 ( L265, L266, L267, L268, L269, L270 );
and2 U2882 ( L2564, L2543, L375 );
and2 U2883 ( L2564, L2550, L378 );
and2 U2884 ( L2564, L2558, L381 );
and2 U2885 ( L2564, L2406, L384 );
nand2 U2886 ( L386, L387, L388 );
nand2 U2887 ( L389, L390, L391 );
nand2 U2888 ( L392, L393, L394 );
nand2 U2889 ( L395, L396, L397 );
nand2 U2890 ( L1326, L1327, L1328 );
nand2 U2891 ( L1329, L1330, L1331 );
nand2 U2892 ( L1332, L1333, L1334 );
or4 U2893 ( L1790, L1436, L1440, L1445, L1447 );
or3 U2894 ( L4091, L1450, L1454, L1766 );
inv U2895 ( L2564, L2571 );
and2 U2896 ( L2577, L2564, L2579 );
inv U2897 ( L2809, L2812 );
inv U2898 ( L2813, L2816 );
and2 U2899 ( L2809, L2757, L2851 );
nand2 U2900 ( L2859, L2860, L2861 );
inv U2901 ( L6347, L6355 );
nand2 U2902 ( L6347, L6356, L2863 );
inv U2903 ( L6357, L6365 );
nand2 U2904 ( L6357, L6366, L2866 );
and2 U2905 ( L4381, L4385, L3147 );
or4 U2906 ( L3046, L3239, L3240, L3241, L3242 );
or4 U2907 ( L1982, L3265, L3267, L3270, L3271 );
or3 U2908 ( L3468, L3274, L3277, L3279 );
nand2 U2909 ( L3613, L3614, L3615 );
inv U2910 ( L6837, L6843 );
nand2 U2911 ( L6837, L6844, L3617 );
inv U2912 ( L6845, L6851 );
nand2 U2913 ( L6845, L6852, L3620 );
inv U2914 ( L4053, L4056 );
nand2 U2915 ( L4515, L4516, L4517 );
inv U2916 ( L7443, L7451 );
nand2 U2917 ( L7443, L7452, L4519 );
inv U2918 ( L7453, L7461 );
nand2 U2919 ( L7453, L7462, L4522 );
nand2 U2920 ( L5029, L5030, L5031 );
nand2 U2921 ( L5117, L5118, L5119 );
inv U2922 ( L5475, L5481 );
nand2 U2923 ( L5475, L5482, L5484 );
inv U2924 ( L5533, L5539 );
nand2 U2925 ( L5533, L5540, L5542 );
nand2 U2926 ( L5599, L5600, L5601 );
nand2 U2927 ( L5687, L5688, L5689 );
nand2 U2928 ( L6065, L6066, L6067 );
nand2 U2929 ( L6123, L6124, L6125 );
nand2 U2930 ( L6181, L6182, L6183 );
inv U2931 ( L6271, L6277 );
nand2 U2932 ( L6271, L6278, L6280 );
nand2 U2933 ( L6933, L6934, L6935 );
nand2 U2934 ( L6991, L6992, L6993 );
inv U2935 ( L7051, L7057 );
nand2 U2936 ( L7051, L7058, L7060 );
inv U2937 ( L7139, L7145 );
nand2 U2938 ( L7139, L7146, L7148 );
nand2 U2939 ( L4959, L4966, L4968 );
nand2 U2940 ( L5000, L5007, L5009 );
and2 U2941 ( L2808, L2812, L2850 );
nand2 U2942 ( L6352, L6355, L2862 );
nand2 U2943 ( L6362, L6365, L2865 );
or2 U2944 ( L3147, L3148, L3149 );
nand2 U2945 ( L3228, L3242, L3243 );
nand2 U2946 ( L6840, L6843, L3616 );
nand2 U2947 ( L6848, L6851, L3619 );
nand2 U2948 ( L7448, L7451, L4518 );
nand2 U2949 ( L7458, L7461, L4521 );
inv U2950 ( L4959, L4965 );
inv U2951 ( L5000, L5006 );
nand2 U2952 ( L5478, L5481, L5483 );
nand2 U2953 ( L5536, L5539, L5541 );
nand2 U2954 ( L6274, L6277, L6279 );
nand2 U2955 ( L7054, L7057, L7059 );
nand2 U2956 ( L7142, L7145, L7147 );
and2 U2957 ( L2547, L2571, L374 );
and2 U2958 ( L2554, L2571, L377 );
and2 U2959 ( L2561, L2571, L380 );
and2 U2960 ( L2400, L2571, L383 );
nand2 U2961 ( L920, L1447, L955 );
nand2 U2962 ( L4962, L4965, L4967 );
nand2 U2963 ( L5003, L5006, L5008 );
buffer U2964 ( L1447, L975 );
and5 U2965 ( L3271, L1093, L1055, L1074, L1038, L1136 );
and4 U2966 ( L3271, L1093, L1055, L1074, L1140 );
and3 U2967 ( L3271, L1093, L1074, L1143 );
and2 U2968 ( L3271, L1093, L1145 );
and2 U2969 ( L1122, L3271, L1160 );
inv U2970 ( L1766, L1771 );
and5 U2971 ( L3279, L1921, L1885, L1903, L1869, L1964 );
and4 U2972 ( L3279, L1921, L1885, L1903, L1968 );
and3 U2973 ( L3279, L1921, L1903, L1971 );
and2 U2974 ( L3279, L1921, L1973 );
and2 U2975 ( L1950, L3279, L2007 );
and2 U2976 ( L2495, L2571, L2578 );
nand2 U2977 ( L2862, L2863, L2864 );
nand2 U2978 ( L2865, L2866, L2867 );
nand2 U2979 ( L3136, L3149, L3150 );
and2 U2980 ( L3238, L3243, L3245 );
nand2 U2981 ( L3616, L3617, L3618 );
nand2 U2982 ( L3619, L3620, L3621 );
or2 U2983 ( L2850, L2851, L4067 );
nand2 U2984 ( L4518, L4519, L4520 );
nand2 U2985 ( L4521, L4522, L4523 );
buffer U2986 ( L3279, L4713 );
buffer U2987 ( L3271, L4753 );
inv U2988 ( L5031, L5037 );
nand2 U2989 ( L5031, L5038, L5040 );
inv U2990 ( L5119, L5125 );
nand2 U2991 ( L5119, L5126, L5128 );
nand2 U2992 ( L5483, L5484, L5485 );
nand2 U2993 ( L5541, L5542, L5543 );
inv U2994 ( L5601, L5607 );
nand2 U2995 ( L5601, L5608, L5610 );
inv U2996 ( L5689, L5695 );
nand2 U2997 ( L5689, L5696, L5698 );
inv U2998 ( L6067, L6073 );
nand2 U2999 ( L6067, L6074, L6076 );
inv U3000 ( L6125, L6131 );
nand2 U3001 ( L6125, L6132, L6134 );
inv U3002 ( L6183, L6189 );
nand2 U3003 ( L6183, L6190, L6192 );
nand2 U3004 ( L6279, L6280, L6281 );
inv U3005 ( L6935, L6941 );
nand2 U3006 ( L6935, L6942, L6944 );
inv U3007 ( L6993, L6999 );
nand2 U3008 ( L6993, L7000, L7002 );
nand2 U3009 ( L7059, L7060, L7061 );
nand2 U3010 ( L7147, L7148, L7149 );
or2 U3011 ( L374, L375, L376 );
or2 U3012 ( L377, L378, L379 );
or2 U3013 ( L380, L381, L382 );
or2 U3014 ( L383, L384, L385 );
and2 U3015 ( L933, L955, L958 );
nand2 U3016 ( L4967, L4968, L967 );
nand2 U3017 ( L5008, L5009, L971 );
or2 U3018 ( L1129, L1160, L1161 );
or2 U3019 ( L1957, L2007, L2008 );
or2 U3020 ( L2578, L2579, L2580 );
and4 U3021 ( L1331, L2861, L2864, L2867, L2868 );
and2 U3022 ( L3146, L3150, L3152 );
and4 U3023 ( L1328, L1334, L3618, L3621, L4443 );
and4 U3024 ( L3615, L4517, L4520, L4523, L4524 );
or5 U3025 ( L1880, L1960, L1961, L1962, L1964, L4721 );
or4 U3026 ( L1897, L1965, L1966, L1968, L4729 );
or3 U3027 ( L1914, L1969, L1971, L4737 );
or2 U3028 ( L1929, L1973, L4745 );
or5 U3029 ( L1050, L1132, L1133, L1134, L1136, L4761 );
or4 U3030 ( L1068, L1137, L1138, L1140, L4769 );
or3 U3031 ( L1086, L1141, L1143, L4777 );
or2 U3032 ( L1102, L1145, L4785 );
nand2 U3033 ( L5034, L5037, L5039 );
nand2 U3034 ( L5122, L5125, L5127 );
nand2 U3035 ( L5604, L5607, L5609 );
nand2 U3036 ( L5692, L5695, L5697 );
nand2 U3037 ( L6070, L6073, L6075 );
nand2 U3038 ( L6128, L6131, L6133 );
nand2 U3039 ( L6186, L6189, L6191 );
nand2 U3040 ( L6938, L6941, L6943 );
nand2 U3041 ( L6996, L6999, L7001 );
inv U3042 ( L3245, L3248 );
and2 U3043 ( L3245, L3223, L248 );
inv U3044 ( L4713, L4719 );
nand2 U3045 ( L4713, L4720, L294 );
inv U3046 ( L4753, L4759 );
nand2 U3047 ( L4753, L4760, L323 );
inv U3048 ( L975, L980 );
inv U3049 ( L4067, L4072 );
nand2 U3050 ( L5039, L5040, L5041 );
nand2 U3051 ( L5127, L5128, L5129 );
inv U3052 ( L5485, L5491 );
nand2 U3053 ( L5485, L5492, L5494 );
inv U3054 ( L5543, L5549 );
nand2 U3055 ( L5543, L5550, L5552 );
nand2 U3056 ( L5609, L5610, L5611 );
nand2 U3057 ( L5697, L5698, L5699 );
nand2 U3058 ( L6075, L6076, L6077 );
nand2 U3059 ( L6133, L6134, L6135 );
nand2 U3060 ( L6191, L6192, L6193 );
inv U3061 ( L6281, L6287 );
nand2 U3062 ( L6281, L6288, L6290 );
nand2 U3063 ( L6943, L6944, L6945 );
nand2 U3064 ( L7001, L7002, L7003 );
inv U3065 ( L7061, L7067 );
nand2 U3066 ( L7061, L7068, L7070 );
inv U3067 ( L7149, L7155 );
nand2 U3068 ( L7149, L7156, L7158 );
and2 U3069 ( L3244, L3248, L247 );
inv U3070 ( L3152, L3155 );
and2 U3071 ( L3152, L3131, L251 );
and2 U3072 ( L1176, L1161, L272 );
inv U3073 ( L958, L961 );
and2 U3074 ( L958, L908, L275 );
nand2 U3075 ( L4716, L4719, L293 );
and2 U3076 ( L2008, L1987, L297 );
and2 U3077 ( L2008, L1994, L300 );
and2 U3078 ( L2008, L2002, L303 );
and2 U3079 ( L2008, L1856, L306 );
inv U3080 ( L4721, L4727 );
nand2 U3081 ( L4721, L4728, L309 );
inv U3082 ( L4729, L4735 );
nand2 U3083 ( L4729, L4736, L312 );
inv U3084 ( L4737, L4743 );
nand2 U3085 ( L4737, L4744, L315 );
inv U3086 ( L4745, L4751 );
nand2 U3087 ( L4745, L4752, L318 );
nand2 U3088 ( L4756, L4759, L322 );
inv U3089 ( L4761, L4767 );
nand2 U3090 ( L4761, L4768, L326 );
inv U3091 ( L4769, L4775 );
nand2 U3092 ( L4769, L4776, L329 );
inv U3093 ( L4777, L4783 );
nand2 U3094 ( L4777, L4784, L332 );
inv U3095 ( L4785, L4791 );
nand2 U3096 ( L4785, L4792, L335 );
inv U3097 ( L4443, L412 );
inv U3098 ( L4524, L414 );
inv U3099 ( L2868, L416 );
and3 U3100 ( L4443, L4524, L2868, L2881 );
and3 U3101 ( L971, L962, L975, L993 );
and3 U3102 ( L967, L965, L975, L994 );
inv U3103 ( L1161, L1166 );
and2 U3104 ( L1161, L1155, L1171 );
and2 U3105 ( L1161, L1023, L1174 );
inv U3106 ( L2008, L2014 );
and5 U3107 ( L2580, L3417, L3381, L3399, L3365, L3459 );
and4 U3108 ( L2580, L3417, L3381, L3399, L3462 );
and3 U3109 ( L2580, L3417, L3399, L3464 );
and2 U3110 ( L2580, L3417, L3465 );
and2 U3111 ( L3446, L2580, L3490 );
buffer U3112 ( L2580, L4793 );
nand2 U3113 ( L5488, L5491, L5493 );
nand2 U3114 ( L5546, L5549, L5551 );
nand2 U3115 ( L6284, L6287, L6289 );
nand2 U3116 ( L7064, L7067, L7069 );
nand2 U3117 ( L7152, L7155, L7157 );
or2 U3118 ( L247, L248, L249 );
and2 U3119 ( L3151, L3155, L250 );
and2 U3120 ( L957, L961, L274 );
nand2 U3121 ( L293, L294, L295 );
nand2 U3122 ( L4724, L4727, L308 );
nand2 U3123 ( L4732, L4735, L311 );
nand2 U3124 ( L4740, L4743, L314 );
nand2 U3125 ( L4748, L4751, L317 );
nand2 U3126 ( L322, L323, L324 );
nand2 U3127 ( L4764, L4767, L325 );
nand2 U3128 ( L4772, L4775, L328 );
nand2 U3129 ( L4780, L4783, L331 );
nand2 U3130 ( L4788, L4791, L334 );
and3 U3131 ( L2876, L2878, L2881, L417 );
and3 U3132 ( L971, L933, L980, L991 );
and3 U3133 ( L967, L929, L980, L992 );
or2 U3134 ( L3453, L3490, L3491 );
or5 U3135 ( L3376, L3456, L3457, L3458, L3459, L4801 );
or4 U3136 ( L3393, L3460, L3461, L3462, L4809 );
or3 U3137 ( L3410, L3463, L3464, L4817 );
or2 U3138 ( L3425, L3465, L4825 );
inv U3139 ( L5041, L5047 );
nand2 U3140 ( L5041, L5048, L5050 );
inv U3141 ( L5129, L5135 );
nand2 U3142 ( L5129, L5136, L5138 );
nand2 U3143 ( L5493, L5494, L5495 );
nand2 U3144 ( L5551, L5552, L5553 );
inv U3145 ( L5611, L5617 );
nand2 U3146 ( L5611, L5618, L5620 );
inv U3147 ( L5699, L5705 );
nand2 U3148 ( L5699, L5706, L5708 );
inv U3149 ( L6077, L6083 );
nand2 U3150 ( L6077, L6084, L6086 );
inv U3151 ( L6135, L6141 );
nand2 U3152 ( L6135, L6142, L6144 );
inv U3153 ( L6193, L6199 );
nand2 U3154 ( L6193, L6200, L6202 );
nand2 U3155 ( L6289, L6290, L6291 );
inv U3156 ( L6945, L6951 );
nand2 U3157 ( L6945, L6952, L6954 );
inv U3158 ( L7003, L7009 );
nand2 U3159 ( L7003, L7010, L7012 );
nand2 U3160 ( L7069, L7070, L7071 );
nand2 U3161 ( L7157, L7158, L7159 );
or2 U3162 ( L250, L251, L252 );
and2 U3163 ( L1117, L1166, L271 );
or2 U3164 ( L274, L275, L276 );
and2 U3165 ( L1991, L2014, L296 );
and2 U3166 ( L1998, L2014, L299 );
and2 U3167 ( L2005, L2014, L302 );
and2 U3168 ( L1850, L2014, L305 );
nand2 U3169 ( L308, L309, L310 );
nand2 U3170 ( L311, L312, L313 );
nand2 U3171 ( L314, L315, L316 );
nand2 U3172 ( L317, L318, L319 );
nand2 U3173 ( L325, L326, L327 );
nand2 U3174 ( L328, L329, L330 );
nand2 U3175 ( L331, L332, L333 );
nand2 U3176 ( L334, L335, L336 );
inv U3177 ( L4793, L4799 );
nand2 U3178 ( L4793, L4800, L343 );
inv U3179 ( L417, L418 );
and2 U3180 ( L1158, L1166, L1170 );
and2 U3181 ( L1019, L1166, L1173 );
nand2 U3182 ( L5044, L5047, L5049 );
nand2 U3183 ( L5132, L5135, L5137 );
or4 U3184 ( L991, L992, L993, L994, L5167 );
nand2 U3185 ( L5614, L5617, L5619 );
nand2 U3186 ( L5702, L5705, L5707 );
nand2 U3187 ( L6080, L6083, L6085 );
nand2 U3188 ( L6138, L6141, L6143 );
nand2 U3189 ( L6196, L6199, L6201 );
nand2 U3190 ( L6948, L6951, L6953 );
nand2 U3191 ( L7006, L7009, L7011 );
or2 U3192 ( L271, L272, L273 );
or2 U3193 ( L296, L297, L298 );
or2 U3194 ( L299, L300, L301 );
or2 U3195 ( L302, L303, L304 );
or2 U3196 ( L305, L306, L307 );
nand2 U3197 ( L4796, L4799, L342 );
and2 U3198 ( L3491, L3471, L346 );
and2 U3199 ( L3491, L3478, L349 );
and2 U3200 ( L3491, L3486, L352 );
and2 U3201 ( L3491, L3350, L355 );
inv U3202 ( L4801, L4807 );
nand2 U3203 ( L4801, L4808, L358 );
inv U3204 ( L4809, L4815 );
nand2 U3205 ( L4809, L4816, L361 );
inv U3206 ( L4817, L4823 );
nand2 U3207 ( L4817, L4824, L364 );
inv U3208 ( L4825, L4831 );
nand2 U3209 ( L4825, L4832, L367 );
or2 U3210 ( L1170, L1171, L1172 );
or2 U3211 ( L1173, L1174, L1175 );
inv U3212 ( L3491, L3497 );
nand2 U3213 ( L5049, L5050, L5051 );
nand2 U3214 ( L5137, L5138, L5139 );
inv U3215 ( L5495, L5501 );
nand2 U3216 ( L5495, L5502, L5504 );
inv U3217 ( L5553, L5559 );
nand2 U3218 ( L5553, L5560, L5562 );
nand2 U3219 ( L5619, L5620, L5621 );
nand2 U3220 ( L5707, L5708, L5709 );
nand2 U3221 ( L6085, L6086, L6087 );
nand2 U3222 ( L6143, L6144, L6145 );
nand2 U3223 ( L6201, L6202, L6203 );
inv U3224 ( L6291, L6297 );
nand2 U3225 ( L6291, L6298, L6300 );
nand2 U3226 ( L6953, L6954, L6955 );
nand2 U3227 ( L7011, L7012, L7013 );
inv U3228 ( L7071, L7077 );
nand2 U3229 ( L7071, L7078, L7080 );
inv U3230 ( L7159, L7165 );
nand2 U3231 ( L7159, L7166, L7168 );
nand2 U3232 ( L342, L343, L344 );
nand2 U3233 ( L4804, L4807, L357 );
nand2 U3234 ( L4812, L4815, L360 );
nand2 U3235 ( L4820, L4823, L363 );
nand2 U3236 ( L4828, L4831, L366 );
inv U3237 ( L5167, L5173 );
buffer U3238 ( L1172, L422 );
buffer U3239 ( L1172, L469 );
buffer U3240 ( L1175, L419 );
buffer U3241 ( L1175, L471 );
nand2 U3242 ( L5498, L5501, L5503 );
nand2 U3243 ( L5556, L5559, L5561 );
nand2 U3244 ( L6294, L6297, L6299 );
nand2 U3245 ( L7074, L7077, L7079 );
nand2 U3246 ( L7162, L7165, L7167 );
and2 U3247 ( L3475, L3497, L345 );
and2 U3248 ( L3482, L3497, L348 );
and2 U3249 ( L3489, L3497, L351 );
and2 U3250 ( L3344, L3497, L354 );
nand2 U3251 ( L357, L358, L359 );
nand2 U3252 ( L360, L361, L362 );
nand2 U3253 ( L363, L364, L365 );
nand2 U3254 ( L366, L367, L368 );
inv U3255 ( L5051, L5057 );
nand2 U3256 ( L5051, L5058, L5060 );
inv U3257 ( L5139, L5145 );
nand2 U3258 ( L5139, L5146, L5148 );
nand2 U3259 ( L5503, L5504, L5505 );
nand2 U3260 ( L5561, L5562, L5563 );
inv U3261 ( L5621, L5627 );
nand2 U3262 ( L5621, L5628, L5630 );
inv U3263 ( L5709, L5715 );
nand2 U3264 ( L5709, L5716, L5718 );
inv U3265 ( L6087, L6093 );
nand2 U3266 ( L6087, L6094, L6096 );
inv U3267 ( L6145, L6151 );
nand2 U3268 ( L6145, L6152, L6154 );
inv U3269 ( L6203, L6209 );
nand2 U3270 ( L6203, L6210, L6212 );
nand2 U3271 ( L6299, L6300, L6301 );
inv U3272 ( L6955, L6961 );
nand2 U3273 ( L6955, L6962, L6964 );
inv U3274 ( L7013, L7019 );
nand2 U3275 ( L7013, L7020, L7022 );
nand2 U3276 ( L7079, L7080, L7081 );
nand2 U3277 ( L7167, L7168, L7169 );
or2 U3278 ( L345, L346, L347 );
or2 U3279 ( L348, L349, L350 );
or2 U3280 ( L351, L352, L353 );
or2 U3281 ( L354, L355, L356 );
nand2 U3282 ( L5054, L5057, L5059 );
nand2 U3283 ( L5142, L5145, L5147 );
nand2 U3284 ( L5624, L5627, L5629 );
nand2 U3285 ( L5712, L5715, L5717 );
nand2 U3286 ( L6090, L6093, L6095 );
nand2 U3287 ( L6148, L6151, L6153 );
nand2 U3288 ( L6206, L6209, L6211 );
nand2 U3289 ( L6958, L6961, L6963 );
nand2 U3290 ( L7016, L7019, L7021 );
nand2 U3291 ( L5059, L5060, L5061 );
nand2 U3292 ( L5147, L5148, L5149 );
inv U3293 ( L5505, L5511 );
nand2 U3294 ( L5505, L5512, L5514 );
inv U3295 ( L5563, L5569 );
nand2 U3296 ( L5563, L5570, L5572 );
nand2 U3297 ( L5629, L5630, L5631 );
nand2 U3298 ( L5717, L5718, L5719 );
nand2 U3299 ( L6095, L6096, L6097 );
nand2 U3300 ( L6153, L6154, L6155 );
nand2 U3301 ( L6211, L6212, L6213 );
inv U3302 ( L6301, L6307 );
nand2 U3303 ( L6301, L6308, L6310 );
nand2 U3304 ( L6963, L6964, L6965 );
nand2 U3305 ( L7021, L7022, L7023 );
inv U3306 ( L7081, L7087 );
nand2 U3307 ( L7081, L7088, L7090 );
inv U3308 ( L7169, L7175 );
nand2 U3309 ( L7169, L7176, L7178 );
nand2 U3310 ( L5508, L5511, L5513 );
nand2 U3311 ( L5566, L5569, L5571 );
nand2 U3312 ( L6304, L6307, L6309 );
nand2 U3313 ( L7084, L7087, L7089 );
nand2 U3314 ( L7172, L7175, L7177 );
inv U3315 ( L5061, L5067 );
nand2 U3316 ( L5061, L5068, L5070 );
inv U3317 ( L5149, L5155 );
nand2 U3318 ( L5149, L5156, L5158 );
nand2 U3319 ( L5513, L5514, L5515 );
nand2 U3320 ( L5571, L5572, L5573 );
inv U3321 ( L5631, L5637 );
nand2 U3322 ( L5631, L5638, L5640 );
inv U3323 ( L5719, L5725 );
nand2 U3324 ( L5719, L5726, L5728 );
inv U3325 ( L6097, L6103 );
nand2 U3326 ( L6097, L6104, L6106 );
inv U3327 ( L6155, L6161 );
nand2 U3328 ( L6155, L6162, L6164 );
inv U3329 ( L6213, L6219 );
nand2 U3330 ( L6213, L6220, L6222 );
nand2 U3331 ( L6309, L6310, L6311 );
inv U3332 ( L6965, L6971 );
nand2 U3333 ( L6965, L6972, L6974 );
inv U3334 ( L7023, L7029 );
nand2 U3335 ( L7023, L7030, L7032 );
nand2 U3336 ( L7089, L7090, L7091 );
nand2 U3337 ( L7177, L7178, L7179 );
nand2 U3338 ( L5064, L5067, L5069 );
nand2 U3339 ( L5152, L5155, L5157 );
nand2 U3340 ( L5634, L5637, L5639 );
nand2 U3341 ( L5722, L5725, L5727 );
nand2 U3342 ( L6100, L6103, L6105 );
nand2 U3343 ( L6158, L6161, L6163 );
nand2 U3344 ( L6216, L6219, L6221 );
nand2 U3345 ( L6968, L6971, L6973 );
nand2 U3346 ( L7026, L7029, L7031 );
inv U3347 ( L5515, L5521 );
nand2 U3348 ( L5515, L5522, L1756 );
inv U3349 ( L5573, L5579 );
nand2 U3350 ( L5573, L5580, L1761 );
nand2 U3351 ( L5069, L5070, L5071 );
nand2 U3352 ( L5157, L5158, L5159 );
nand2 U3353 ( L5639, L5640, L5641 );
nand2 U3354 ( L5727, L5728, L5729 );
nand2 U3355 ( L6105, L6106, L6107 );
nand2 U3356 ( L6163, L6164, L6165 );
nand2 U3357 ( L6221, L6222, L6223 );
inv U3358 ( L6311, L6317 );
nand2 U3359 ( L6311, L6318, L6320 );
nand2 U3360 ( L6973, L6974, L6975 );
nand2 U3361 ( L7031, L7032, L7033 );
inv U3362 ( L7091, L7097 );
nand2 U3363 ( L7091, L7098, L7100 );
inv U3364 ( L7179, L7185 );
nand2 U3365 ( L7179, L7186, L7188 );
nand2 U3366 ( L5518, L5521, L1755 );
nand2 U3367 ( L5576, L5579, L1760 );
nand2 U3368 ( L6314, L6317, L6319 );
nand2 U3369 ( L7094, L7097, L7099 );
nand2 U3370 ( L7182, L7185, L7187 );
nand2 U3371 ( L1755, L1756, L1757 );
nand2 U3372 ( L1760, L1761, L1762 );
inv U3373 ( L6107, L6113 );
nand2 U3374 ( L6107, L6114, L2818 );
inv U3375 ( L6165, L6171 );
nand2 U3376 ( L6165, L6172, L2823 );
inv U3377 ( L6975, L6981 );
nand2 U3378 ( L6975, L6982, L4058 );
inv U3379 ( L7033, L7039 );
nand2 U3380 ( L7033, L7040, L4063 );
inv U3381 ( L5071, L5077 );
nand2 U3382 ( L5071, L5078, L5080 );
inv U3383 ( L5159, L5165 );
nand2 U3384 ( L5159, L5166, L5090 );
inv U3385 ( L5641, L5647 );
nand2 U3386 ( L5641, L5648, L5650 );
inv U3387 ( L5729, L5735 );
nand2 U3388 ( L5729, L5736, L5660 );
inv U3389 ( L6223, L6229 );
nand2 U3390 ( L6223, L6230, L6232 );
nand2 U3391 ( L6319, L6320, L6321 );
nand2 U3392 ( L7099, L7100, L7101 );
nand2 U3393 ( L7187, L7188, L7189 );
nand2 U3394 ( L6110, L6113, L2817 );
nand2 U3395 ( L6168, L6171, L2822 );
nand2 U3396 ( L6978, L6981, L4057 );
nand2 U3397 ( L7036, L7039, L4062 );
nand2 U3398 ( L5074, L5077, L5079 );
nand2 U3399 ( L5162, L5165, L5089 );
nand2 U3400 ( L5644, L5647, L5649 );
nand2 U3401 ( L5732, L5735, L5659 );
nand2 U3402 ( L6226, L6229, L6231 );
and3 U3403 ( L1762, L1730, L1771, L1782 );
and3 U3404 ( L1757, L1726, L1771, L1783 );
and3 U3405 ( L1762, L1751, L1766, L1784 );
and3 U3406 ( L1757, L1754, L1766, L1785 );
nand2 U3407 ( L2817, L2818, L2819 );
nand2 U3408 ( L2822, L2823, L2824 );
nand2 U3409 ( L4057, L4058, L4059 );
nand2 U3410 ( L4062, L4063, L4064 );
nand2 U3411 ( L5079, L5080, L5081 );
nand2 U3412 ( L5089, L5090, L5091 );
nand2 U3413 ( L5649, L5650, L5651 );
nand2 U3414 ( L5659, L5660, L5661 );
nand2 U3415 ( L6231, L6232, L6233 );
inv U3416 ( L6321, L6327 );
nand2 U3417 ( L6321, L6328, L6252 );
inv U3418 ( L7101, L7107 );
nand2 U3419 ( L7101, L7108, L7110 );
inv U3420 ( L7189, L7195 );
nand2 U3421 ( L7189, L7196, L7120 );
or4 U3422 ( L1782, L1783, L1784, L1785, L5737 );
nand2 U3423 ( L6324, L6327, L6251 );
nand2 U3424 ( L7104, L7107, L7109 );
nand2 U3425 ( L7192, L7195, L7119 );
inv U3426 ( L5081, L5087 );
nand2 U3427 ( L5081, L5088, L985 );
inv U3428 ( L5091, L5097 );
nand2 U3429 ( L5091, L5098, L988 );
inv U3430 ( L5651, L5657 );
nand2 U3431 ( L5651, L5658, L1776 );
inv U3432 ( L5661, L5667 );
nand2 U3433 ( L5661, L5668, L1779 );
and3 U3434 ( L2824, L2784, L2833, L2844 );
and3 U3435 ( L2819, L2780, L2833, L2845 );
and3 U3436 ( L2824, L2813, L2828, L2846 );
and3 U3437 ( L2819, L2816, L2828, L2847 );
and3 U3438 ( L4064, L4032, L4072, L4083 );
and3 U3439 ( L4059, L4028, L4072, L4084 );
and3 U3440 ( L4064, L4053, L4067, L4085 );
and3 U3441 ( L4059, L4056, L4067, L4086 );
inv U3442 ( L6233, L6239 );
nand2 U3443 ( L6233, L6240, L6242 );
nand2 U3444 ( L6251, L6252, L6253 );
nand2 U3445 ( L7109, L7110, L7111 );
nand2 U3446 ( L7119, L7120, L7121 );
nand2 U3447 ( L5084, L5087, L984 );
nand2 U3448 ( L5094, L5097, L987 );
nand2 U3449 ( L5654, L5657, L1775 );
nand2 U3450 ( L5664, L5667, L1778 );
inv U3451 ( L5737, L5743 );
nand2 U3452 ( L6236, L6239, L6241 );
or4 U3453 ( L2844, L2845, L2846, L2847, L6329 );
or4 U3454 ( L4083, L4084, L4085, L4086, L7197 );
nand2 U3455 ( L984, L985, L986 );
nand2 U3456 ( L987, L988, L989 );
nand2 U3457 ( L1775, L1776, L1777 );
nand2 U3458 ( L1778, L1779, L1780 );
inv U3459 ( L6253, L6259 );
nand2 U3460 ( L6253, L6260, L2841 );
inv U3461 ( L7111, L7117 );
nand2 U3462 ( L7111, L7118, L4077 );
inv U3463 ( L7121, L7127 );
nand2 U3464 ( L7121, L7128, L4080 );
nand2 U3465 ( L6241, L6242, L6243 );
inv U3466 ( L989, L990 );
and2 U3467 ( L975, L986, L996 );
inv U3468 ( L1780, L1781 );
and2 U3469 ( L1766, L1777, L1787 );
nand2 U3470 ( L6256, L6259, L2840 );
inv U3471 ( L6329, L6335 );
nand2 U3472 ( L7114, L7117, L4076 );
nand2 U3473 ( L7124, L7127, L4079 );
inv U3474 ( L7197, L7203 );
and2 U3475 ( L990, L980, L995 );
and2 U3476 ( L1781, L1771, L1786 );
inv U3477 ( L6243, L6249 );
nand2 U3478 ( L6243, L6250, L2838 );
nand2 U3479 ( L2840, L2841, L2842 );
nand2 U3480 ( L4076, L4077, L4078 );
nand2 U3481 ( L4079, L4080, L4081 );
nand2 U3482 ( L6246, L6249, L2837 );
inv U3483 ( L2842, L2843 );
inv U3484 ( L4081, L4082 );
and2 U3485 ( L4067, L4078, L4088 );
or2 U3486 ( L995, L996, L5170 );
or2 U3487 ( L1786, L1787, L5740 );
nand2 U3488 ( L2837, L2838, L2839 );
and2 U3489 ( L2843, L2833, L2848 );
and2 U3490 ( L4082, L4072, L4087 );
nand2 U3491 ( L5740, L5743, L1791 );
nand2 U3492 ( L5170, L5173, L1003 );
inv U3493 ( L5170, L5174 );
inv U3494 ( L5740, L5744 );
and2 U3495 ( L2828, L2839, L2849 );
or2 U3496 ( L4087, L4088, L7200 );
nand2 U3497 ( L5737, L5744, L1792 );
nand2 U3498 ( L5167, L5174, L1004 );
or2 U3499 ( L2848, L2849, L6332 );
nand2 U3500 ( L1791, L1792, L320 );
nand2 U3501 ( L1003, L1004, L337 );
nand2 U3502 ( L7200, L7203, L4092 );
inv U3503 ( L7200, L7204 );
inv U3504 ( L320, L321 );
inv U3505 ( L337, L338 );
nand2 U3506 ( L7197, L7204, L4093 );
nand2 U3507 ( L6332, L6335, L2855 );
inv U3508 ( L6332, L6336 );
nand2 U3509 ( L4092, L4093, L369 );
nand2 U3510 ( L6329, L6336, L2856 );
inv U3511 ( L369, L370 );
nand2 U3512 ( L2855, L2856, L398 );
inv U3513 ( L398, L399 );
endmodule
|
Added c7552/c7552high.v.
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 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/****************************************************************************
* *
* VERILOG HIGH-LEVEL DESCRIPTION OF THE ISCAS-85 BENCHMARK CIRCUIT c7552 *
* *
* *
* Written by : Hakan Yalcin (hyalcin@cadence.com) *
* Verified by : Jonathan David Hauke (jhauke@eecs.umich.edu) *
* *
* First created: Jan 21, 1997 *
* Last modified: Oct 20, 1998 *
* *
****************************************************************************/
module Circuit7552(
in213, in214, in215, in216, in209, in153, in154,
in155, in156, in157, in158, in159, in160, in151, in219,
in220, in221, in222, in223, in224, in225, in226, in217,
in231, in232, in233, in234, in235, in236, in237, in238,
in135, in144, in138, in147, in66, in50, in32, in35,
in47, in121, in94, in97, in118, in100, in124, in127,
in130, in103, in23, in26, in29, in41, in1486, in1480,
in106, in1469, in1462, in2256, in2253, in2247, in2239, in2236,
in2230, in2224, in2218, in2211, in4437, in4432, in4427, in4420,
in4415, in4410, in4405, in4400, in4394, in3749, in3743, in3737,
in3729, in3723, in3717, in3711, in3705, in88, in112, in87,
in111, in113, in110, in109, in86, in63, in64, in85,
in84, in83, in65, in62, in61, in60, in79, in80,
in81, in59, in78, in77, in56, in55, in54, in53,
in73, in75, in76, in74, in166, in167, in168, in169,
in173, in174, in175, in176, in177, in178, in179, in180,
in171, in189, in190, in191, in192, in193, in194, in195,
in196, in187, in200, in201, in202, in203, in204, in205,
in206, in207, in18, in12, in9, in4526, in89, in38,
in4528, in211, in212, in161, in227, in239, in229, in141,
in115, in44, in1459, in1496, in1492, in2208, in4393, in3701,
in3698, in114, in2204, in1455, in82, in58, in70, in69,
in170, in164, in165, in181, in197, in208, in198, in199,
in188, in172, in162, in186, in185, in182, in183, in230,
in218, in152, in210, in240, in228, in184, in150, in1,
in163, in15, in1197, in134, in133, in5, in57, in339,
out469, out471, out327, out330, out333, out336, out324,
out298, out301, out304, out307, out310, out313, out316, out319,
out295, out347, out350, out353, out356, out359, out362, out365,
out368, out344, out376, out379, out382, out385, out388, out391,
out394, out397, out373, out419, out422, out270, out246, out273,
out276, out258, out264, out249, out252, out338, out321, out370,
out399, out416, out414, out412, out418, out410, out408, out406,
out404, out440, out438, out442, out444, out446, out448, out436,
out480, out482, out484, out486, out488, out490, out492, out494,
out478, out524, out526, out528, out530, out532, out534, out536,
out538, out522, out544, out546, out548, out550, out552, out554,
out556, out558, out542, out450, out496, out540, out560, out402,
out289, out292, out279, out278, out2, out3, out432, out453,
out286, out341, out281, out284, out339);
input
in213, in214, in215, in216, in209, in153, in154,
in155, in156, in157, in158, in159, in160, in151, in219,
in220, in221, in222, in223, in224, in225, in226, in217,
in231, in232, in233, in234, in235, in236, in237, in238,
in135, in144, in138, in147, in66, in50, in32, in35,
in47, in121, in94, in97, in118, in100, in124, in127,
in130, in103, in23, in26, in29, in41, in1486, in1480,
in106, in1469, in1462, in2256, in2253, in2247, in2239, in2236,
in2230, in2224, in2218, in2211, in4437, in4432, in4427, in4420,
in4415, in4410, in4405, in4400, in4394, in3749, in3743, in3737,
in3729, in3723, in3717, in3711, in3705, in88, in112, in87,
in111, in113, in110, in109, in86, in63, in64, in85,
in84, in83, in65, in62, in61, in60, in79, in80,
in81, in59, in78, in77, in56, in55, in54, in53,
in73, in75, in76, in74, in166, in167, in168, in169,
in173, in174, in175, in176, in177, in178, in179, in180,
in171, in189, in190, in191, in192, in193, in194, in195,
in196, in187, in200, in201, in202, in203, in204, in205,
in206, in207, in18, in12, in9, in4526, in89, in38,
in4528, in211, in212, in161, in227, in239, in229, in141,
in115, in44, in1459, in1496, in1492, in2208, in4393, in3701,
in3698, in114, in2204, in1455, in82, in58, in70, in69,
in170, in164, in165, in181, in197, in208, in198, in199,
in188, in172, in162, in186, in185, in182, in183, in230,
in218, in152, in210, in240, in228, in184, in150, in1,
in163, in15, in1197, in134, in133, in5, in57, in339;
output
out469, out471, out327, out330, out333, out336, out324,
out298, out301, out304, out307, out310, out313, out316, out319,
out295, out347, out350, out353, out356, out359, out362, out365,
out368, out344, out376, out379, out382, out385, out388, out391,
out394, out397, out373, out419, out422, out270, out246, out273,
out276, out258, out264, out249, out252, out338, out321, out370,
out399, out416, out414, out412, out418, out410, out408, out406,
out404, out440, out438, out442, out444, out446, out448, out436,
out480, out482, out484, out486, out488, out490, out492, out494,
out478, out524, out526, out528, out530, out532, out534, out536,
out538, out522, out544, out546, out548, out550, out552, out554,
out556, out558, out542, out450, out496, out540, out560, out402,
out289, out292, out279, out278, out2, out3, out432, out453,
out286, out341, out281, out284, out339;
/*******************************/
wire VDD, GND;
assign
VDD = 1'b1,
GND = 1'b0;
wire [31:0] XA0bus, XA1bus;
wire [31:0] YA1bus;
wire [33:0] XBbus, YB0bus;
wire CinX, CinY;
wire NotMuxSel, ContBusMask0, ContBusMask1;
wire XYAext, XYBext;
wire [33:0] SumXbus;
wire [3:0] NotSumParbus;
wire CoutX1, CoutX2;
wire CoutY1, CoutY2, CoutY_17;
wire [6:0] PCXA0bus, PCXA1bus, PCYA0bus, PCYA1bus, PCYB0bus;
wire [3:0] ParCheck;
wire [33:0] XBbufbus;
wire [3:0] PCYA0bufbus;
wire [15:0] StrobeInbus;
wire [3:0] Not_StrobeOutbus;
wire [7:0] MiscInbus;
wire [5:0] MiscOutbus;
/*******************************/
// in229 is a redundant input for XA0bus[0]
assign
XA0bus[31:0] = { in213, in214, in215, in216, in209, in153, in154,
in155, in156, in157, in158, in159, in160, in151,
in219, in220, in221, in222, in223, in224, in225,
in226, in217, in231, in232, in233, in234, in235,
in236, in237, in238, GND };
assign
XA1bus[31:0] = { VDD, VDD, VDD, VDD, VDD, VDD, VDD, VDD, VDD, VDD,
in135, in144, in138, in147, in66, in50,
in32, in35, in47, in121, in94, in97, in118, in100,
in124, in127, in130, in103, in23, in26, in29, in41};
// a mux will be placed at bit 0 in module InvertXB
assign
XBbus[33:0] = { in1496, in1492,
in1486, in1480, in106, in1469, in1462, in2256, in2253,
in2247, in2239, in2236, in2230, in2224, in2218, in2211,
in4437, in4432, in4427, in4420, in4415, in4410, in4405,
in4400, in4394, in3749, in3743, in3737, in3729, in3723,
in3717, in3711, in3705, in3701 };
assign
YA1bus[31:0] = { in88, in112, in87, in111, in113, in110, in109, in86,
in63, in64, in85, in84, in83, in65, in62, in61, in60,
in79, in80, in81, in59, in78, in77, in56, in55, in54,
in53, in73, in75, in76, in74, in70};
assign
YB0bus[33:0] = { in2204, in1455,
in166, in167, in168, in169, VDD, in173, in174, in175,
in176, in177, in178, in179, in180, in171, in189, in190,
in191, in192, in193, in194, in195, in196, in187, in200,
in201, in202, in203, in204, in205, in206, in207, GND};
assign NotMuxSel = in18;
assign
ContBusMask0 = in12, ContBusMask1 = in9;
assign
CinX = in4526, CinY = in89;
assign
XYAext = in38, XYBext = in4528;
assign
PCXA0bus[6:0] = { VDD, in211, in212, in161, in227, in239, in229 },
PCXA1bus[6:0] = { VDD, VDD, VDD, in141, in115, in44, in41 },
PCYA0bus[6:0] = { in1459, in1496, in1492, in2208, in4393, in3701, in3698 },
PCYA1bus[6:0] = { in114, in2204, in1455, in82, in58, in70, in69 },
PCYB0bus[6:0] = { in170, in164, in165, in181, in197, in208, in198 };
assign
StrobeInbus[15:0] = { in199, in188, in172, in162, in186, in185,
in182, in183, in230, in218, in152, in210,
in240, in228, in184, in150 };
assign
MiscInbus[7:0] = { in57 , in5, in133, in134, in1197, in15, in163, in1 };
// outputs
assign
{ out469, out471, out327, out330, out333, out336,
out324, out298, out301, out304, out307, out310,
out313, out316, out319, out295, out347, out350,
out353, out356, out359, out362, out365, out368,
out344, out376, out379, out382, out385, out388,
out391, out394, out397, out373} = SumXbus[33:0];
assign out419 = SumXbus[32]; // identical to out471
assign out422 = SumXbus[33]; // identical to out469
assign out270 = CoutX1;
assign out246 = CoutX1; // identical to out270
assign out273 = CoutX2;
assign out276 = CoutX2;
assign out258 = CoutY1;
assign out264 = CoutY1; // identical to out258
assign out249 = CoutY2;
assign out252 = CoutY_17;
assign
{ out338, out321, out370, out399 } = NotSumParbus[3:0];
assign
{ out416, out414, out412, out418 } = ParCheck[3:0];
assign
{ out410, out408, out406, out404 } = Not_StrobeOutbus[3:0];
assign
{ out438, out440, out442, out444, out446, out448,
out436, out480, out482, out484, out486, out488,
out490, out492, out494, out478, out524, out526,
out528, out530, out532, out534, out536, out538,
out522, out544, out546, out548, out550, out552,
out554, out556, out558, out542 } = XBbufbus[33:0];
assign
{ out450, out496, out540, out560 } = PCYA0bufbus[3:0];
assign
{ out402, out289, out292, out279, out278, out2 } = MiscOutbus[5:0];
// equivalents of MiscOutbus lines
assign
out3 = MiscOutbus[0],
out432 = MiscOutbus[0],
out453 = MiscOutbus[0],
out286 = MiscOutbus[2],
out341 = MiscOutbus[2],
out281 = MiscOutbus[3],
out284 = MiscOutbus[4];
assign out339 = in339; // this line goes straight through
/* instantiate top level circuit */
TopLevel7552 Ckt7552( XA0bus, XA1bus, XBbus, YA1bus, YB0bus,
NotMuxSel, ContBusMask0, ContBusMask1,
XYAext, XYBext, CinX, CinY, StrobeInbus,
PCXA0bus, PCXA1bus, PCYA0bus, PCYA1bus, PCYB0bus,
SumXbus, NotSumParbus, CoutX1, CoutX2,
CoutY1, CoutY2, CoutY_17, ParCheck, Not_StrobeOutbus,
XBbufbus, PCYA0bufbus, MiscInbus, MiscOutbus );
endmodule // Circuit7552
/***************************************************************************/
/***************************************************************************/
module TopLevel7552( XA0bus, XA1bus, XBbus, YA1bus, YB0bus,
NotMuxSel, ContBusMask0, ContBusMask1,
XYAext, XYBext, CinX, CinY, StrobeInbus,
PCXA0bus, PCXA1bus, PCYA0bus, PCYA1bus, PCYB0bus,
SumXbus, NotSumParbus, CoutX1, CoutX2,
CoutY1, CoutY2, CoutY_17, ParCheck, Not_StrobeOutbus,
XBbufbus, PCYA0bufbus, MiscInbus, MiscOutbus );
input [31:0] XA0bus, XA1bus, YA1bus;
input [33:0] XBbus, YB0bus;
input NotMuxSel, ContBusMask0, ContBusMask1;
input XYAext, XYBext;
input CinX, CinY;
input [6:0] PCXA0bus, PCXA1bus, PCYA0bus, PCYA1bus, PCYB0bus;
input [15:0] StrobeInbus;
input [7:0] MiscInbus;
output [33:0] SumXbus;
output [3:0] NotSumParbus;
output CoutX1, CoutX2, CoutY1, CoutY2, CoutY_17;
output [3:0] ParCheck;
output [3:0] Not_StrobeOutbus;
output [33:0] XBbufbus;
output [3:0] PCYA0bufbus;
output [5:0] MiscOutbus;
wire MuxSel;
wire [33:0] XAbus, YAbus, YBbus, Not_XBbus;
wire [31:0] YA0bus, YB1bus;
wire [33:0] PropXbus, CarryXbus;
wire [33:0] LocalCarryXCin0, LocalCarryXCin1;
wire [3:0] PCYA0select;
assign YB1bus[31:0] = XA1bus[31:0];
nand2 M0( .A(ContBusMask0), .B(ContBusMask1), .Y(ContBusMask) );
inv M00( .A(NotMuxSel), .Y(MuxSel) );
// first input buses
MuxBusXA M1( XA0bus, XA1bus, MuxSel, ContBusMask, XYAext, XAbus);
InvertXB M2( XBbus, MuxSel, XYBext, Not_XBbus);
assign
YA0bus[0] = 1'b1,
YA0bus[31:1] = Not_XBbus[31:1];
MuxBusYA M3( YA0bus, YA1bus, MuxSel, XYAext, YAbus);
MuxBusYB M4( YB0bus, YB1bus, MuxSel, ContBusMask, XYBext, YBbus);
// adder with inputs XA & XB
AdderX34bit M5( XAbus, Not_XBbus, CinX, PropXbus,
LocalCarryXCin0, LocalCarryXCin1, CarryXbus, CoutX1, CoutX2);
GenerateSumX M6( PropXbus, CinX, LocalCarryXCin0, LocalCarryXCin1, CarryXbus,
SumXbus );
GenerateSumParity M7( PropXbus, CinX, LocalCarryXCin0, LocalCarryXCin1, CarryXbus,
NotSumParbus);
// adder with inputs YA & YB
AdderY34bit M8( YAbus, YBbus, CinY, CoutY1, CoutY2, CoutY_17 );
ParityModule M9( XAbus, YAbus, YBbus, MuxSel, ContBusMask, StrobeInbus,
PCXA0bus, PCXA1bus, PCYA0bus, PCYA1bus, PCYB0bus,
ParCheck, Not_StrobeOutbus );
Buffer34 M10( XBbus, XBbufbus );
assign PCYA0select = { PCYA0bus[6],PCYA0bus[3],PCYA0bus[2],PCYA0bus[0] };
Buffer4 M11( PCYA0select, PCYA0bufbus );
// Misc. logic -- just a few gates
MiscLogic M12( MiscInbus, MiscOutbus );
endmodule // TopLevel7552
/***************************************************************************
* Module: MuxBusXA
*
* Function: generate (34-bit) XAbus from (32-bit) XA0bus and XA1bus
* - XAbus[31:21] can be masked via ContBusMask.
* - XAbus[33:32] are connected to XYAext.
*
***************************************************************************/
module MuxBusXA( XA0bus, XA1bus, MuxSel, ContBusMask, XYAext, XAbus);
input [31:0] XA0bus, XA1bus;
input MuxSel, ContBusMask, XYAext;
output [33:0] XAbus;
Mux_and_Mask32 UM1_0( XA0bus, XA1bus, MuxSel, ContBusMask, XAbus[31:0]);
assign
XAbus[32] = XYAext,
XAbus[33] = XYAext;
endmodule // MuxBusXA
/******************************************************/
module Mux_and_Mask32( In1bus, In2bus, MuxSel, ContBusMask, Outbus);
input [31:0] In1bus, In2bus;
input MuxSel, ContBusMask;
output [31:0] Outbus;
wire [31:0] MuxOutbus;
Mux32 MM0( In1bus, In2bus, MuxSel, MuxOutbus);
assign Outbus[21:0] = MuxOutbus[21:0];
and2 MM1( .A(MuxOutbus[22]), .B(ContBusMask), .Y(Outbus[22]) ),
MM2( .A(MuxOutbus[23]), .B(ContBusMask), .Y(Outbus[23]) ),
MM3( .A(MuxOutbus[24]), .B(ContBusMask), .Y(Outbus[24]) ),
MM4( .A(MuxOutbus[25]), .B(ContBusMask), .Y(Outbus[25]) ),
MM5( .A(MuxOutbus[26]), .B(ContBusMask), .Y(Outbus[26]) ),
MM6( .A(MuxOutbus[27]), .B(ContBusMask), .Y(Outbus[27]) ),
MM7( .A(MuxOutbus[28]), .B(ContBusMask), .Y(Outbus[28]) ),
MM8( .A(MuxOutbus[29]), .B(ContBusMask), .Y(Outbus[29]) ),
MM9( .A(MuxOutbus[30]), .B(ContBusMask), .Y(Outbus[30]) ),
MM10( .A(MuxOutbus[31]), .B(ContBusMask), .Y(Outbus[31]) );
endmodule // Mux_and_Mask
/******************************************************/
module Mux32( In1bus, In2bus, MuxSel, Outbus);
input [31:0] In1bus, In2bus;
input MuxSel;
output [31:0] Outbus;
Mux8 Mux32_0( In1bus[7:0], In2bus[7:0], MuxSel, Outbus[7:0] ),
Mux32_1( In1bus[15:8], In2bus[15:8], MuxSel, Outbus[15:8] ),
Mux32_2( In1bus[23:16], In2bus[23:16], MuxSel, Outbus[23:16] ),
Mux32_3( In1bus[31:24], In2bus[31:24], MuxSel, Outbus[31:24] );
endmodule // Mux32
/******************************************************/
module Mux8( In1bus, In2bus, MuxSel, Outbus);
input [7:0] In1bus, In2bus;
input MuxSel;
output [7:0] Outbus;
Mux2_1 Mux8_0 ( In1bus[0], In2bus[0], MuxSel, Outbus[0]),
Mux8_1 ( In1bus[1], In2bus[1], MuxSel, Outbus[1]),
Mux8_2 ( In1bus[2], In2bus[2], MuxSel, Outbus[2]),
Mux8_3 ( In1bus[3], In2bus[3], MuxSel, Outbus[3]),
Mux8_4 ( In1bus[4], In2bus[4], MuxSel, Outbus[4]),
Mux8_5 ( In1bus[5], In2bus[5], MuxSel, Outbus[5]),
Mux8_6 ( In1bus[6], In2bus[6], MuxSel, Outbus[6]),
Mux8_7 ( In1bus[7], In2bus[7], MuxSel, Outbus[7]);
endmodule // Mux8
/***************************************************************************
* Module: InvertXB
*
* Function: invert the 34-bit input bus XBbus. Output: Not_XBbus
* - Not_XBbus[0] is a mux with inputs XBbus[0] and logic 1.
* - Not_XBbus[33:32] can be masked via XYBext.
*
***************************************************************************/
module InvertXB( XBbus, MuxSel, XYBext, Not_XBbus);
input [33:0] XBbus;
input MuxSel, XYBext;
output [33:0] Not_XBbus;
wire [33:0] AuxXBbus;
Mux2_1 UM2_0( 1'b0, XBbus[0], MuxSel, AuxXBbus[0] );
assign AuxXBbus[31:1] = XBbus[31:1];
and2 UM2_1( .A(XBbus[32]), .B(XYBext), .Y(AuxXBbus[32]) );
and2 UM2_2( .A(XBbus[33]), .B(XYBext), .Y(AuxXBbus[33]) );
Invert34 UM2_3( AuxXBbus, Not_XBbus);
endmodule // InvertXB
/******************************************************/
module Invert34( Inbus, Outbus );
input [33:0] Inbus;
output [33:0] Outbus;
Invert8 Inv34_0( Inbus[7:0], Outbus[7:0] ),
Inv34_1( Inbus[15:8], Outbus[15:8] ),
Inv34_2( Inbus[23:16], Outbus[23:16] ),
Inv34_3( Inbus[31:24], Outbus[31:24] );
inv Inv34_4( .A(Inbus[32]), .Y(Outbus[32]) ),
Inv34_5( .A(Inbus[33]), .Y(Outbus[33]) );
endmodule // Invert34
/******************************************************/
module Invert8( Inbus, Outbus );
input [7:0] Inbus;
output [7:0] Outbus;
inv Inv8_0( .A(Inbus[0]), .Y(Outbus[0]) ),
Inv8_1( .A(Inbus[1]), .Y(Outbus[1]) ),
Inv8_2( .A(Inbus[2]), .Y(Outbus[2]) ),
Inv8_3( .A(Inbus[3]), .Y(Outbus[3]) ),
Inv8_4( .A(Inbus[4]), .Y(Outbus[4]) ),
Inv8_5( .A(Inbus[5]), .Y(Outbus[5]) ),
Inv8_6( .A(Inbus[6]), .Y(Outbus[6]) ),
Inv8_7( .A(Inbus[7]), .Y(Outbus[7]) );
endmodule // Invert8
/***************************************************************************
* Module: MuxBusYA
*
* Function: generate (34-bit) YAbus from (32-bit) YA0bus and YA1bus.
* - YAbus[33:32] are connected to XYAext.
*
***************************************************************************/
module MuxBusYA( YA0bus, YA1bus, MuxSel, XYAext, YAbus);
input [31:0] YA0bus, YA1bus;
input MuxSel, XYAext;
output [33:0] YAbus;
Mux32 UM3_0( YA0bus, YA1bus, MuxSel, YAbus[31:0]);
assign
YAbus[32] = XYAext,
YAbus[33] = XYAext;
endmodule // MuxBusYA
/***************************************************************************
* Module: MuxBusYB
*
* Function: generate (34-bit) YBbus from (34-bit) YB0bus and (32-bit) YB1bus.
* - Like XAbus, YBbus[31:21] can be masked via ContBusMask.
* - YBbus[33:32] can also be masked with XYBext.
*
***************************************************************************/
module MuxBusYB( YB0bus, YB1bus, MuxSel, ContBusMask, XYBext, YBbus);
input [33:0] YB0bus;
input [31:0] YB1bus;
input MuxSel, ContBusMask, XYBext;
output [33:0] YBbus;
Mux_and_Mask32 UM4_0( YB0bus[31:0], YB1bus, MuxSel, ContBusMask, YBbus[31:0]);
inv UM4_1( .A(XYBext), .Y(NotXYBext) );
or2 UM4_2( .A(NotXYBext), .B(YB0bus[32]), .Y(YBbus[32]) ),
UM4_3( .A(NotXYBext), .B(YB0bus[33]), .Y(YBbus[33]) );
endmodule // MuxBusYB
/***************************************************************************
* Module: AdderX34bit
*
* Function: calculate CarryOutXbus from the sum of XAbus and XBbus.
* - LocalCarryXCin0 and LocalCarryXCin1 are carries within 5-, 4- and
* 2-bit groups with an assumed carry input of 0 and 1, respectively.
* - Notice: carry bits 5,6,7,14,15,16,23,24,25 and 32 do NOT EXIST!
* The pivot and local carries are used to compute the sum and
* sum-parity outputs for these bit positions.
* - CoutX1 is tied to CarryOutXbus[33], whereas CoutX2 is functionally
* identical, but calculated differently.
*
***************************************************************************/
module AdderX34bit( XAbus, XBbus, CinX, PropXbus, LocalCarryXCin0, LocalCarryXCin1,
CarryOutXbus, CoutX1, CoutX2);
input [33:0] XAbus, XBbus;
input CinX;
output [33:0] PropXbus;
output [33:0] LocalCarryXCin0, LocalCarryXCin1;
output [33:0] CarryOutXbus;
output CoutX1, CoutX2;
wire [33:0] GenXbus;
GenProp34 UM5_0( XAbus, XBbus, GenXbus, PropXbus);
CLA_CSA34 UM5_1( GenXbus, PropXbus, CinX,
LocalCarryXCin0, LocalCarryXCin1, CarryOutXbus, CoutX1, CoutX2);
endmodule // AdderX34bit
/******************************************************/
module GenProp34( InAbus, InBbus, Gbus, Pbus);
input [33:0] InAbus, InBbus;
output [33:0] Gbus, Pbus;
GenProp8 GP34_0( InAbus[7:0], InBbus[7:0], Gbus[7:0], Pbus[7:0]),
GP34_1( InAbus[15:8], InBbus[15:8], Gbus[15:8], Pbus[15:8]),
GP34_2( InAbus[23:16], InBbus[23:16], Gbus[23:16], Pbus[23:16]),
GP34_3( InAbus[31:24], InBbus[31:24], Gbus[31:24], Pbus[31:24]);
and2 GP34_4( .A(InAbus[32]), .B(InBbus[32]), .Y(Gbus[32]) ),
GP34_5( .A(InAbus[33]), .B(InBbus[33]), .Y(Gbus[33]) );
XOR2a GP34_6( .A(InAbus[32]), .B(InBbus[32]), .Y(Pbus[32]) ),
GP34_7( .A(InAbus[33]), .B(InBbus[33]), .Y(Pbus[33]) );
endmodule // GenProp34bit
/******************************************************/
module GenProp8( InAbus, InBbus, Gbus, Pbus);
input [7:0] InAbus, InBbus;
output [7:0] Gbus, Pbus;
and2 GenProp8_0( .A(InAbus[0]), .B(InBbus[0]), .Y(Gbus[0]) ),
GenProp8_1( .A(InAbus[1]), .B(InBbus[1]), .Y(Gbus[1]) ),
GenProp8_2( .A(InAbus[2]), .B(InBbus[2]), .Y(Gbus[2]) ),
GenProp8_3( .A(InAbus[3]), .B(InBbus[3]), .Y(Gbus[3]) ),
GenProp8_4( .A(InAbus[4]), .B(InBbus[4]), .Y(Gbus[4]) ),
GenProp8_5( .A(InAbus[5]), .B(InBbus[5]), .Y(Gbus[5]) ),
GenProp8_6( .A(InAbus[6]), .B(InBbus[6]), .Y(Gbus[6]) ),
GenProp8_7( .A(InAbus[7]), .B(InBbus[7]), .Y(Gbus[7]) );
XOR2a GenProp8_8( .A(InAbus[0]), .B(InBbus[0]), .Y(Pbus[0]) ),
GenProp8_9( .A(InAbus[1]), .B(InBbus[1]), .Y(Pbus[1]) ),
GenProp8_10( .A(InAbus[2]), .B(InBbus[2]), .Y(Pbus[2]) ),
GenProp8_11( .A(InAbus[3]), .B(InBbus[3]), .Y(Pbus[3]) ),
GenProp8_12( .A(InAbus[4]), .B(InBbus[4]), .Y(Pbus[4]) ),
GenProp8_13( .A(InAbus[5]), .B(InBbus[5]), .Y(Pbus[5]) ),
GenProp8_14( .A(InAbus[6]), .B(InBbus[6]), .Y(Pbus[6]) ),
GenProp8_15( .A(InAbus[7]), .B(InBbus[7]), .Y(Pbus[7]) );
endmodule // GenProp8
/******************************************************
* This 34-bit adder is used both by module AdderX34bit
* and by module AdderY4bit.
******************************************************/
module CLA_CSA34( Genbus, Propbus, Cin,
LocalCarryCin0, LocalCarryCin1, CarryOutbus, Cout1, Cout2);
input [33:0] Genbus, Propbus;
input Cin;
output [33:0] LocalCarryCin0, LocalCarryCin1;
output [33:0] CarryOutbus;
output Cout1, Cout2;
/* This 34-bit adder is partitioned into blocks of sizes 5, 4 and 2.
* Block boundaries:
* block #0 (5): bits [4:0]
* block #1 (4): bits [8:5]
* block #2 (5): bits [13:9]
* block #3 (4): bits [17:14]
* block #4 (5): bits [22:18]
* block #5 (4): bits [26:23]
* block #6 (5): bits [31:27]
* block #7 (2): bits [33:32]
* first calculate carries local to each block
- note: LocalCin0[j] means the carry OUT OF bit j (to bit j+1)
assuming the carry into that block=0
and LocalCin1[j] means the carry OUT OF bit j (to bit j+1)
assuming the carry into that block=1
*/
GenLocalCarry34 CC_0( Genbus, Propbus, LocalCarryCin0, LocalCarryCin1 );
// then generate global carry lines
// ... but carries are not explicitly generated for 4-bit blocks.
GenerateGlobalCarry34 CC_1( Genbus, Propbus, Cin, LocalCarryCin0, LocalCarryCin1,
CarryOutbus );
assign Cout1 = CarryOutbus[33];
Mux2_1 CC_2( LocalCarryCin0[33], LocalCarryCin1[33], CarryOutbus[31],
Cout2 );
endmodule // CLA_CSA34
/******************************************************/
/******************************************************/
module GenLocalCarry34( Gbus, Pbus, LocalC0, LocalC1 );
input [33:0] Gbus, Pbus;
output [33:0] LocalC0, LocalC1;
GenLocalCarry9 GLC34_0( Gbus[8:0], Pbus[8:0],
LocalC0[8:0], LocalC1[8:0] ),
GLC34_1( Gbus[17:9], Pbus[17:9],
LocalC0[17:9], LocalC1[17:9] ),
GLC34_2( Gbus[26:18], Pbus[26:18],
LocalC0[26:18], LocalC1[26:18] );
GenLocalCarry5 GLC34_3( Gbus[31:27], Pbus[31:27],
LocalC0[31:27], LocalC1[31:27] );
GenLocalCarry2 GLC34_4( Gbus[33:32], Pbus[33:32],
LocalC0[33:32], LocalC1[33:32] );
endmodule // GenLocalCarry34
/******************************************************/
module GenLocalCarry9( Gbus, Pbus, LocalC0, LocalC1 );
input [8:0] Gbus, Pbus;
output [8:0] LocalC0, LocalC1;
GenLocalCarry5 GLC9_0( Gbus[4:0], Pbus[4:0],
LocalC0[4:0], LocalC1[4:0] );
GenLocalCarry4 GLC9_4( Gbus[8:5], Pbus[8:5],
LocalC0[8:5], LocalC1[8:5] );
endmodule // GenLocalCarry9
/******************************************************/
module GenLocalCarry5( Gbus, Pbus, LocalC0, LocalC1 );
input [4:0] Gbus, Pbus;
output [4:0] LocalC0, LocalC1;
GenLocalCarry4 GLC5_0( Gbus[3:0], Pbus[3:0],
LocalC0[3:0], LocalC1[3:0] );
AND_OR5a GLC5_1( Gbus[4], Pbus[4], Gbus[3], Pbus[3], Gbus[2],
Pbus[2], Gbus[1], Pbus[1], Gbus[0],
LocalC0[4] );
AND_OR6b GLC5_2( Gbus[4], Pbus[4], Gbus[3], Pbus[3], Gbus[2],
Pbus[2], Gbus[1], Pbus[1], Gbus[0], Pbus[0],
LocalC1[4] );
endmodule // GenLocalCarry5
/******************************************************/
module GenLocalCarry4( Gbus, Pbus, LocalC0, LocalC1 );
input [3:0] Gbus, Pbus;
output [3:0] LocalC0, LocalC1;
assign LocalC0[0] = Gbus[0];
or2 GLC4_0( .A(Gbus[0]), .B(Pbus[0]), .Y(LocalC1[0]) );
AND_OR2 GLC4_1( Gbus[1], Pbus[1], Gbus[0], LocalC0[1] );
AND_OR3b GLC4_2( Gbus[1], Pbus[1], Gbus[0], Pbus[0], LocalC1[1] );
AND_OR3a GLC4_3( Gbus[2], Pbus[2], Gbus[1], Pbus[1], Gbus[0],
LocalC0[2] );
AND_OR4b GLC4_4( Gbus[2], Pbus[2], Gbus[1], Pbus[1], Gbus[0],
Pbus[0], LocalC1[2] );
AND_OR4a GLC4_5( Gbus[3], Pbus[3], Gbus[2], Pbus[2], Gbus[1],
Pbus[1], Gbus[0], LocalC0[3] );
AND_OR5b GLC4_6( Gbus[3], Pbus[3], Gbus[2], Pbus[2], Gbus[1],
Pbus[1], Gbus[0], Pbus[0], LocalC1[3] );
endmodule // GenLocalCarry4
/******************************************************/
module GenLocalCarry2( Gbus, Pbus, LocalC0, LocalC1 );
input [1:0] Gbus, Pbus;
output [1:0] LocalC0, LocalC1;
assign LocalC0[0] = Gbus[0];
or2 GLC2_0( .A(Gbus[0]), .B(Pbus[0]), .Y(LocalC1[0]) );
AND_OR2 GLC2_1( Gbus[1], Pbus[1], Gbus[0], LocalC0[1] );
AND_OR3b GLC2_2( Gbus[1], Pbus[1], Gbus[0], Pbus[0], LocalC1[1] );
endmodule // GenLocalCarry2
/******************************************************/
/******************************************************/
module GenerateGlobalCarry34( Gbus, Pbus, Cin, LocalC0, LocalC1,
CarryOutbus );
input [33:0] Gbus, Pbus;
input Cin;
input [33:0] LocalC0, LocalC1;
output [33:0] CarryOutbus;
// first calculate the global carry to each block called pivot carry.
CalcPivotCarry CGC34_0( Pbus, Cin, LocalC0, LocalC1, CarryOutbus );
/* Compute only the carries for the 5-bit blocks
The pivot carries will be used to select the correct Sum bits
for the 4-bit blocks */
CalcBlockCLA5 CGC34_1( Pbus[3:0], Gbus[3:0], Cin,
CarryOutbus[3:0] );
CalcBlockCLA5 CGC34_2( Pbus[12:9], Gbus[12:9], CarryOutbus[8],
CarryOutbus[12:9] );
CalcBlockCLA5 CGC34_3( Pbus[21:18], Gbus[21:18], CarryOutbus[17],
CarryOutbus[21:18] );
CalcBlockCLA5 CGC34_4( Pbus[30:27], Gbus[30:27], CarryOutbus[26],
CarryOutbus[30:27] );
endmodule // GenerateGlobalCarry34
/******************************************************/
module CalcPivotCarry( Pbus, Cin, LocalC0, LocalC1, CarryOutbus );
input [33:0] Pbus;
input Cin;
input [33:0] LocalC0, LocalC1;
output [33:0] CarryOutbus;
and5 CBC0( .A(Pbus[0]), .B(Pbus[1]), .C(Pbus[2]), .D(Pbus[3]),
.E(Pbus[4]), .Y(Prop4_0) );
and4 CBC1( .A(Pbus[5]), .B(Pbus[6]), .C(Pbus[7]), .D(Pbus[8]),
.Y(Prop8_5) );
and5 CBC2( .A(Pbus[9]), .B(Pbus[10]), .C(Pbus[11]), .D(Pbus[12]),
.E(Pbus[13]), .Y(Prop13_9) );
and4 CBC3( .A(Pbus[14]), .B(Pbus[15]), .C(Pbus[16]), .D(Pbus[17]),
.Y(Prop17_14) );
and5 CBC4( .A(Pbus[18]), .B(Pbus[19]), .C(Pbus[20]), .D(Pbus[21]),
.E(Pbus[22]), .Y(Prop22_18) );
and4 CBC5( .A(Pbus[23]), .B(Pbus[24]), .C(Pbus[25]), .D(Pbus[26]),
.Y(Prop26_23) );
and5 CBC6( .A(Pbus[27]), .B(Pbus[28]), .C(Pbus[29]), .D(Pbus[30]),
.E(Pbus[31]), .Y(Prop31_27) );
and2 CBC7( .A(Pbus[32]), .B(Pbus[33]), .Y(Prop33_32) );
and2 CBC8( .A(Prop4_0), .B(Prop8_5), .Y(Prop8_0) );
and2 CBC9( .A(Prop13_9), .B(Prop17_14), .Y(Prop17_9) );
and2 CBC10( .A(Prop22_18), .B(Prop26_23), .Y(Prop26_18) );
and2 CBC11( .A(Prop31_27), .B(Prop33_32), .Y(Prop33_27) );
// CarryOutbus[4]
AND_OR2 CBC12( LocalC0[4], Cin, Prop4_0, CarryOutbus[4]);
// CarryOutbus[8]
Mux2_1 CGC13( LocalC0[8], LocalC1[8], CarryOutbus[4],
CarryOutbus[8] );
// CarryOutbus[13]
AND_OR2 GGC14( LocalC0[13], CarryOutbus[8], Prop13_9,
CarryOutbus[13] );
// CarryOutbus[17]
AND_OR2 CGC15( LocalC0[17], LocalC0[13], Prop17_14,
LocalCarry17_9 );
AND_OR2 CGC16( LocalC0[8], LocalC0[4], Prop8_5, LocalCarry8_0 );
AND_OR3a CGC17( LocalCarry17_9, Prop17_9, LocalCarry8_0,
Prop8_0, Cin, CarryOutbus[17] );
// CarryOutbus[22]
AND_OR2 CGC18( LocalC0[22], CarryOutbus[17], Prop22_18,
CarryOutbus[22]);
// CarryOutbus[26]
AND_OR2 CGC19( LocalC0[26], LocalC0[22], Prop26_23,
LocalCarry26_18 );
AND_OR4a CGC20( LocalCarry26_18, Prop26_18, LocalCarry17_9,
Prop17_9, LocalCarry8_0, Prop8_0, Cin, CarryOutbus[26] );
// CarryOutbus[31]
AND_OR2 CGC21( LocalC0[31], CarryOutbus[26], Prop31_27,
CarryOutbus[31]);
// CarryOutbus[33] = CarryOutX
AND_OR2 CGC22( LocalC0[33], LocalC0[31], Prop33_32,
LocalCarry33_27 );
AND_OR5a CGC23( LocalCarry33_27, Prop33_27, LocalCarry26_18, Prop26_18,
LocalCarry17_9, Prop17_9, LocalCarry8_0, Prop8_0, Cin,
CarryOutbus[33] );
endmodule // CalcPivotCarry
/******************************************************/
module CalcBlockCLA5( Pbus, Gbus, Cin, Carrybus );
input [3:0] Pbus, Gbus;
input Cin;
output [3:0] Carrybus;
AND_OR2 CB5_0( Gbus[0], Pbus[0], Cin, Carrybus[0] );
AND_OR3a CB5_1( Gbus[1], Pbus[1], Gbus[0], Pbus[0], Cin, Carrybus[1] );
AND_OR4a CB5_2( Gbus[2], Pbus[2], Gbus[1], Pbus[1],
Gbus[0], Pbus[0], Cin, Carrybus[2] );
AND_OR5a CB5_3( Gbus[3], Pbus[3], Gbus[2], Pbus[2], Gbus[1], Pbus[1],
Gbus[0], Pbus[0], Cin, Carrybus[3] );
endmodule
/***************************************************************************
* Module: GenerateSumX
*
* Function: compute the SumX outputs using PropXbus and carry lines.
* - For 5-bit blocks, the sum[i] is simply computed by
* prop[i] XOR carry[i].
* - For 4-bit blocks, two sums are computed:
* prop[i] XOR LocalCarryCin0[i] and
* prop[i] XOR LocalCarryCin1[i].
* The pivot carry selects the correct sum.
* (This scheme is used to speed up the sum computation for
* such blocks, since the XOR delay is longer than the MUX delay.)
*
***************************************************************************/
module GenerateSumX( PropXbus, CinX, LocalCarryCin0, LocalCarryCin1, CarryXbus,
SumXbus );
input [33:0] PropXbus;
input CinX;
input [33:0] LocalCarryCin0, LocalCarryCin1, CarryXbus;
output [33:0] SumXbus;
wire [5:0] Cry5_0;
assign Cry5_0[0] = CinX,
Cry5_0[5:1] = CarryXbus[4:0];
CalcSumXor6 UM6_0( PropXbus[5:0], Cry5_0, SumXbus[5:0] );
CalcSumMux3 UM6_1( PropXbus[8:6], CarryXbus[4], LocalCarryCin0[7:5],
LocalCarryCin1[7:5], SumXbus[8:6] );
CalcSumXor6 UM6_2( PropXbus[14:9], CarryXbus[13:8], SumXbus[14:9] );
CalcSumMux3 UM6_3( PropXbus[17:15], CarryXbus[13], LocalCarryCin0[16:14],
LocalCarryCin1[16:14], SumXbus[17:15] );
CalcSumXor6 UM6_4( PropXbus[23:18], CarryXbus[22:17], SumXbus[23:18] );
CalcSumMux3 UM6_5( PropXbus[26:24], CarryXbus[22], LocalCarryCin0[25:23],
LocalCarryCin1[25:23], SumXbus[26:24] );
CalcSumXor6 UM6_6( PropXbus[32:27], CarryXbus[31:26], SumXbus[32:27] );
XOR2a UM6_7( .A(PropXbus[33]), .B(LocalCarryCin0[32]), .Y(Sum33_0) ),
UM6_8( .A(PropXbus[33]), .B(LocalCarryCin1[32]), .Y(Sum33_1) );
Mux2_1 UM6_9( Sum33_0, Sum33_1, CarryXbus[31], SumXbus[33] );
endmodule // GenerateSumX
/******************************************************/
module CalcSumXor6( Pbus, Carrybus, Sumbus );
input [5:0] Pbus;
input [5:0] Carrybus;
output [5:0] Sumbus;
XOR2a CSX6_0( .A(Pbus[0]), .B(Carrybus[0]), .Y(Sumbus[0]) ),
CSX6_1( .A(Pbus[1]), .B(Carrybus[1]), .Y(Sumbus[1]) ),
CSX6_2( .A(Pbus[2]), .B(Carrybus[2]), .Y(Sumbus[2]) ),
CSX6_3( .A(Pbus[3]), .B(Carrybus[3]), .Y(Sumbus[3]) ),
CSX6_4( .A(Pbus[4]), .B(Carrybus[4]), .Y(Sumbus[4]) ),
CSX6_5( .A(Pbus[5]), .B(Carrybus[5]), .Y(Sumbus[5]) );
endmodule // CalcSumXor6
/******************************************************/
module CalcSumMux3( Pbus, Cin, LocalCarryCin0, LocalCarryCin1, Sumbus );
input [2:0] Pbus;
input Cin;
input [2:0] LocalCarryCin0, LocalCarryCin1;
output [2:0] Sumbus;
wire [2:0] Sum0, Sum1;
XOR2a CSM4_0( .A(Pbus[0]), .B(LocalCarryCin0[0]), .Y(Sum0[0]) ),
CSM4_1( .A(Pbus[1]), .B(LocalCarryCin0[1]), .Y(Sum0[1]) ),
CSM4_2( .A(Pbus[2]), .B(LocalCarryCin0[2]), .Y(Sum0[2]) ),
CSM4_3( .A(Pbus[0]), .B(LocalCarryCin1[0]), .Y(Sum1[0]) ),
CSM4_4( .A(Pbus[1]), .B(LocalCarryCin1[1]), .Y(Sum1[1]) ),
CSM4_5( .A(Pbus[2]), .B(LocalCarryCin1[2]), .Y(Sum1[2]) );
Mux2_1 CSM4_6( Sum0[0], Sum1[0], Cin, Sumbus[0] ),
CSM4_7( Sum0[1], Sum1[1], Cin, Sumbus[1] ),
CSM4_8( Sum0[2], Sum1[2], Cin, Sumbus[2] );
endmodule // CalcSumMux3
/***************************************************************************
* Module: GenerateSumParity
*
* Function: compute the following four parity outputs:
* - NotSumParbus[0]: parity for SumX[8:0] (5+4)
* - NotSumParbus[1]: parity for SumX[17:9] (5+4)
* - NotSumParbus[2]: parity for SumX[26:18] (5+4)
* - NotSumParbus[3]: parity for SumX[33:27] (5+2)
*
* - For each case, two parities are computed, and
* the pivot carries select the correct one.
* (again, a method intended for increased speed.)
*
***************************************************************************/
module GenerateSumParity( Pbus, CinX, LocalC0, LocalC1, CarryXbus,
NotSumParbus);
input [33:0] Pbus;
input CinX;
input [33:0] LocalC0, LocalC1, CarryXbus;
output [3:0] NotSumParbus;
wire ParCin0b33_32, ParCin1b33_32armut;
SerialPar9nc GSP0( {Pbus[4:0], LocalC0[3:0]}, ParCin0b4_0);
SerialPar9c GSP1( {Pbus[4:0], LocalC1[3:0]}, ParCin1b4_0);
SerialPar7nc GSP2( {Pbus[8:5], LocalC0[7:5]}, ParCin0b8_5);
SerialPar7c GSP3( {Pbus[8:5], LocalC1[7:5]}, ParCin1b8_5);
SerialPar9nc GSP4( {Pbus[13:9], LocalC0[12:9]}, ParCin0b13_9);
SerialPar9c GSP5( {Pbus[13:9], LocalC1[12:9]}, ParCin1b13_9);
SerialPar7nc GSP6( {Pbus[17:14], LocalC0[16:14]}, ParCin0b17_14);
SerialPar7c GSP7( {Pbus[17:14], LocalC1[16:14]}, ParCin1b17_14);
SerialPar9nc GSP8( {Pbus[22:18], LocalC0[21:18]}, ParCin0b22_18);
SerialPar9c GSP9( {Pbus[22:18], LocalC1[21:18]}, ParCin1b22_18);
SerialPar7nc GSP10( {Pbus[26:23], LocalC0[25:23]}, ParCin0b26_23);
SerialPar7c GSP11( {Pbus[26:23], LocalC1[25:23]}, ParCin1b26_23);
SerialPar9nc GSP12( {Pbus[31:27], LocalC0[30:27]}, ParCin0b31_27);
SerialPar9c GSP13( {Pbus[31:27], LocalC1[30:27]}, ParCin1b31_27);
SerialPar3nc GSP14( {Pbus[33:32], LocalC0[32]}, ParCin0b33_32);
SerialPar3c GSP15( {Pbus[33:32], LocalC1[32]}, ParCin1b33_32armut);
SelectPar9 GSP16( ParCin0b4_0, ParCin1b4_0, ParCin0b8_5, ParCin1b8_5,
CinX, LocalC0[4], LocalC1[4],
NotSumParbus[0] );
SelectPar9 GSP17( ParCin0b13_9, ParCin1b13_9, ParCin0b17_14, ParCin1b17_14,
CarryXbus[8], LocalC0[13], LocalC1[13],
NotSumParbus[1] );
SelectPar9 GSP18( ParCin0b22_18, ParCin1b22_18, ParCin0b26_23, ParCin1b26_23,
CarryXbus[17], LocalC0[22], LocalC1[22],
NotSumParbus[2] );
SelectPar9 GSP19( ParCin0b31_27, ParCin1b31_27, ParCin0b33_32, ParCin1b33_32armut,
CarryXbus[26], LocalC0[31], LocalC1[31],
NotSumParbus[3] );
endmodule // GenerateSumParity
/******************************************************/
module SerialPar9nc( Inbus, Out);
input [8:0] Inbus;
output Out;
SerialPar7nc SP9nc0( Inbus[6:0], line0 );
XOR2a SP9nc1( .A(Inbus[7]), .B(line0), .Y(line1) ),
SP9nc2( .A(Inbus[8]), .B(line1), .Y(Out) );
endmodule // SerialPar9nc
/******************************************************/
module SerialPar9c( Inbus, Out);
input [8:0] Inbus;
output Out;
// Inbus[6] is inverted in SerialPar7c
SerialPar7c SP9nc0( Inbus[6:0], line0 );
XOR2a SP9nc1( .A(Inbus[7]), .B(line0), .Y(line1) ),
SP9nc2( .A(Inbus[8]), .B(line1), .Y(Out) );
endmodule // SerialPar9c
/******************************************************/
module SerialPar7nc( Inbus, Out);
input [6:0] Inbus;
output Out;
XOR2a SP7nc0( .A(Inbus[0]), .B(Inbus[1]), .Y(line0) ),
SP7nc1( .A(Inbus[2]), .B(line0), .Y(line1) ),
SP7nc2( .A(Inbus[3]), .B(line1), .Y(line2) ),
SP7nc3( .A(Inbus[4]), .B(line2), .Y(line3) ),
SP7nc4( .A(Inbus[5]), .B(line3), .Y(line4) ),
SP7nc5( .A(Inbus[6]), .B(line4), .Y(Out) );
endmodule // SerialPar7nc
/******************************************************/
module SerialPar7c( Inbus, Out);
input [6:0] Inbus;
output Out;
wire [6:0] NewInbus;
// invert one bit to complement the output
// -- Inbus[6] is chosen so the inverter is not on the longest path
inv SP7c0( .A(Inbus[6]), .Y(NewInbus[6]) );
assign NewInbus[5:0] = Inbus[5:0];
SerialPar7nc SP7c2( NewInbus, Out );
endmodule // SerialPar7c
/******************************************************/
module SerialPar3nc( Inbus, Out );
input [2:0] Inbus;
output Out;
XOR2a SP3nc0( .A(Inbus[0]), .B(Inbus[1]), .Y(line0) ),
SP3nc1( .A(Inbus[2]), .B(line0), .Y(Out) );
endmodule // CalcPar3nc
/******************************************************/
module SerialPar3c( Inbus, Out );
input [2:0] Inbus;
output Out;
inv SP3c0( .A(Inbus[2]), .Y(NotIn2) );
XOR2a SP3c1( .A(Inbus[0]), .B(Inbus[1]), .Y(line1) ),
SP3c2( .A(NotIn2), .B(line1), .Y(Out) );
endmodule // CalcPar3c
/******************************************************/
module SelectPar9( ParCin0Lo, ParCin1Lo, ParCin0Hi, ParCin1Hi,
Cin, LocalC0, LocalC1,
NotSumPar );
input ParCin0Lo, ParCin1Lo, ParCin0Hi, ParCin1Hi;
input Cin, LocalC0, LocalC1;
output NotSumPar;
Mux2_1 SPar0( ParCin0Lo, ParCin1Lo, Cin, line0),
SPar1( ParCin0Hi, ParCin1Hi, LocalC0, line1),
SPar2( ParCin0Hi, ParCin1Hi, LocalC1, line2),
SPar3( line1, line2, Cin, line3);
XOR2a SPar4( .A(line0), .B(line3), .Y(line4) );
inv SPar5( .A(line4), .Y(NotSumPar) );
endmodule // SelectPar9
/***************************************************************************
* Module: AdderY34bit
*
* Function: compute the carry output (CoutY1, CoutY2) from the addition
* of YAbus and YBbus.
* Note that, with one of the input buses complemented,
* the carry output indicates whether the complemented input is
* less than the other than.
* - CoutY_17 is the carry output from the center position (17).
*
***************************************************************************/
module AdderY34bit( YAbus, YBbus, CinY, CoutY1, CoutY2, CoutY_17 );
input [33:0] YAbus, YBbus;
input CinY;
output CoutY1, CoutY2, CoutY_17;
wire [33:0] GenYbus, PropYbus;
wire [33:0] CarryOutYbus;
wire [33:0] dummy0, dummy1;
GenProp34 UM8_0( YAbus, YBbus, GenYbus, PropYbus);
CLA_CSA34 UM8_1( .Genbus(GenYbus), .Propbus(PropYbus), .Cin(CinY),
.LocalCarryCin0(dummy0), .LocalCarryCin1(dummy1),
.CarryOutbus(CarryOutYbus), .Cout1(CoutY1), .Cout2(CoutY2) );
assign CoutY_17 = CarryOutYbus[17];
endmodule // AdderY34bit
/***************************************************************************
* Module: ParityModule
*
* Function: Check the parities of input buses XAbus, YAbus and YBbus.
* - These buses are augmented with PCXA0bus, PCXA1bus, PCYA0bus,
* and PCYA1bus, PCYB0bus.
* - StrobeK0_1 and StrobeK2_3 can mask the final AND (ParCheck[0]).
*
***************************************************************************/
module ParityModule( XAbus, YAbus, YBbus, MuxSel, ContBusMask, StrobeInbus,
PCXA0bus, PCXA1bus, PCYA0bus, PCYA1bus, PCYB0bus,
ParCheck, Not_StrobeOutbus );
input [33:0] XAbus, YAbus, YBbus;
input MuxSel, ContBusMask;
input [15:0] StrobeInbus;
input [6:0] PCXA0bus, PCXA1bus, PCYA0bus, PCYA1bus, PCYB0bus;
output [3:0] ParCheck;
output [3:0] Not_StrobeOutbus;
wire [6:0] PCXAbus, PCYAbus, PCYBbus, PCYB1bus;
wire StrobeK0_1, StrobeK2_3;
assign PCYB1bus[6:0] = PCXA1bus[6:0];
ParityStrobe UM9_0( StrobeInbus, StrobeK0_1, StrobeK2_3, Not_StrobeOutbus );
ParChkBuses UM9_1( PCXA0bus, PCXA1bus, PCYA0bus, PCYA1bus, PCYB0bus, PCYB1bus,
MuxSel, ContBusMask,
PCXAbus, PCYAbus, PCYBbus );
ParityChecker UM9_2( XAbus, YAbus, YBbus, PCXAbus, PCYAbus, PCYBbus,
StrobeK0_1, StrobeK2_3, ParCheck );
endmodule
/********************************************/
/********************************************/
module ParityStrobe( StrInbus, StrobeK0_1, StrobeK2_3,
Not_StrOutbus );
input [15:0] StrInbus;
output StrobeK0_1, StrobeK2_3;
output [3:0] Not_StrOutbus;
wire K0, K1, K2, K3;
and4 GS0( .A(StrInbus[0]), .B(StrInbus[1]), .C(StrInbus[2]),
.D(StrInbus[3]), .Y(K0) ),
GS1( .A(StrInbus[4]), .B(StrInbus[5]), .C(StrInbus[6]),
.D(StrInbus[7]), .Y(K1) ),
GS2( .A(StrInbus[8]), .B(StrInbus[9]), .C(StrInbus[10]),
.D(StrInbus[11]), .Y(K2) ),
GS3( .A(StrInbus[12]), .B(StrInbus[13]), .C(StrInbus[14]),
.D(StrInbus[15]), .Y(K3) );
and2 GS4( .A(K0), .B(K1), .Y(StrobeK0_1) ),
GS5( .A(K2), .B(K3), .Y(StrobeK2_3) );
inv GS6( .A(K0), .Y(Not_StrOutbus[0]) ),
GS7( .A(K1), .Y(Not_StrOutbus[1]) ),
GS8( .A(K2), .Y(Not_StrOutbus[2]) ),
GS9( .A(K3), .Y(Not_StrOutbus[3]) );
endmodule // ParityStrobe
/********************************************/
/********************************************/
module ParChkBuses( PCXA0bus, PCXA1bus, PCYA0bus, PCYA1bus, PCYB0bus, PCYB1bus,
MuxSel, ContBusMask,
PCXAbus, PCYAbus, PCYBbus );
input [6:0] PCXA0bus, PCXA1bus, PCYA0bus, PCYA1bus, PCYB0bus, PCYB1bus;
input MuxSel, ContBusMask;
output [6:0] PCXAbus, PCYAbus, PCYBbus;
wire [6:0] Not_PCYA0bus;
wire [6:0] PCXAtempbus, PCYBtempbus;
Invert7 PCB0( PCYA0bus, Not_PCYA0bus );
Mux7 PCB1( PCXA0bus, PCXA1bus, MuxSel, PCXAtempbus ),
PCB2( Not_PCYA0bus, PCYA1bus, MuxSel, PCYAbus ),
PCB3( PCYB0bus, PCYB1bus, MuxSel, PCYBtempbus );
Mask3_Not1 PCB4( PCXAtempbus, ContBusMask, PCXAbus ),
PCB5( PCYBtempbus, ContBusMask, PCYBbus );
endmodule // ParChkBuses
/********************************************/
module Mux7( In1bus, In2bus, MuxSel, Outbus);
input [6:0] In1bus, In2bus;
input MuxSel;
output [6:0] Outbus;
Mux2_1 Mux7_0 ( In1bus[0], In2bus[0], MuxSel, Outbus[0]),
Mux7_1 ( In1bus[1], In2bus[1], MuxSel, Outbus[1]),
Mux7_2 ( In1bus[2], In2bus[2], MuxSel, Outbus[2]),
Mux7_3 ( In1bus[3], In2bus[3], MuxSel, Outbus[3]),
Mux7_4 ( In1bus[4], In2bus[4], MuxSel, Outbus[4]),
Mux7_5 ( In1bus[5], In2bus[5], MuxSel, Outbus[5]),
Mux7_6 ( In1bus[6], In2bus[6], MuxSel, Outbus[6]);
endmodule // Mux7
/********************************************/
module Invert7( Inbus, Outbus );
input [6:0] Inbus;
output [6:0] Outbus;
inv Inv7_0( .A(Inbus[0]), .Y(Outbus[0]) ),
Inv7_1( .A(Inbus[1]), .Y(Outbus[1]) ),
Inv7_2( .A(Inbus[2]), .Y(Outbus[2]) ),
Inv7_3( .A(Inbus[3]), .Y(Outbus[3]) ),
Inv7_4( .A(Inbus[4]), .Y(Outbus[4]) ),
Inv7_5( .A(Inbus[5]), .Y(Outbus[5]) ),
Inv7_6( .A(Inbus[6]), .Y(Outbus[6]) );
endmodule // Invert7
/********************************************/
module Mask3_Not1( Inbus, ContBusMask, Outbus );
input [6:0] Inbus;
input ContBusMask;
output [6:0] Outbus;
assign Outbus[3:0] = Inbus[3:0];
and2 MN0( .A(Inbus[4]), .B(ContBusMask), .Y(Outbus[4]) ),
MN1( .A(Inbus[5]), .B(ContBusMask), .Y(Outbus[5]) );
and2 MN2( .A(Inbus[6]), .B(ContBusMask), .Y(line2) );
inv MN3( .A(line2), .Y(Outbus[6]) );
endmodule // Mask3_Not1
/********************************************/
/********************************************/
module ParityChecker( XAbus, YAbus, YBbus, PCXAbus, PCYAbus, PCYBbus,
StrobeK0_1, StrobeK2_3, ParCheck);
input [33:0] XAbus, YAbus, YBbus;
input [6:0] PCXAbus, PCYAbus, PCYBbus;
input StrobeK0_1, StrobeK2_3;
output [3:0] ParCheck;
ParityTree10bit ParC0( { XAbus[8:1],PCXAbus[1:0] }, XaP0),
ParC1( { XAbus[17:9],PCXAbus[2] }, XaP1),
ParC2( { XAbus[26:18],PCXAbus[3] }, XaP2);
ParityTree8bit ParC3( { XAbus[31:27],PCXAbus[6:4] }, XaP3);
ParityTree10bit ParC4( { YAbus[8:1],PCYAbus[1:0] }, YaP0),
ParC5( { YAbus[17:9],PCYAbus[2] }, YaP1),
ParC6( { YAbus[26:18],PCYAbus[3] }, YaP2);
ParityTree8bit ParC7( { YAbus[31:27],PCYAbus[6:4] }, YaP3);
ParityTree10bit ParC8( { YBbus[8:1],PCYBbus[1:0] }, YbP0),
ParC9( { YBbus[17:9],PCYBbus[2] }, YbP1),
ParC10({ YBbus[26:18],PCYBbus[3] }, YbP2);
ParityTree8bit ParC11({ YBbus[31:27],PCYBbus[6:4] }, YbP3);
and4 ParC12( .A(XaP0), .B(XaP1), .C(XaP2), .D(XaP3), .Y(XaP) ),
ParC13( .A(YaP0), .B(YaP1), .C(YaP2), .D(YaP3), .Y(YaP) ),
ParC14( .A(YbP0), .B(YbP1), .C(YbP2), .D(YbP3), .Y(YbP) );
and3 ParC15( .A(XaP), .B(YaP), .C(YbP), .Y(XYabP) ),
ParC16( .A(StrobeK0_1), .B(StrobeK2_3), .C(XYabP), .Y(NotPar0) );
inv ParC17( .A(NotPar0), .Y(ParCheck[0]) ),
ParC18( .A(XaP), .Y(ParCheck[1]) ),
ParC19( .A(YaP), .Y(ParCheck[2]) ),
ParC20( .A(YbP), .Y(ParCheck[3]) );
endmodule // ParityChecker
/********************************************/
module ParityTree10bit( Inbus, ParOut );
input [9:0] Inbus;
output ParOut;
XOR2a PT0( .A(Inbus[6]), .B(Inbus[7]), .Y(line0) ),
PT1( .A(Inbus[8]), .B(Inbus[9]), .Y(line1) ),
PT2( .A(Inbus[2]), .B(Inbus[3]), .Y(line2) ),
PT3( .A(Inbus[0]), .B(Inbus[1]), .Y(line3) ),
PT4( .A(Inbus[4]), .B(Inbus[5]), .Y(line4) );
XOR2a PT5( .A(line0), .B(line1), .Y(line5) );
XOR3a PT6( .A(line2), .B(line3), .C(line4), .Y(line6) );
XOR2a PT7( .A(line5), .B(line6), .Y(ParOut) );
endmodule // ParityTree10bit
/********************************************/
module ParityTree8bit( Inbus, ParOut );
input [7:0] Inbus;
output ParOut;
XOR2a PT0( .A(Inbus[0]), .B(Inbus[1]), .Y(line0) ),
PT1( .A(Inbus[2]), .B(Inbus[3]), .Y(line1) ),
PT2( .A(Inbus[4]), .B(Inbus[5]), .Y(line2) ),
PT3( .A(Inbus[6]), .B(Inbus[7]), .Y(line3) );
XOR3a PT4( .A(line1), .B(line2), .C(line3), .Y(line4) );
XOR2a PT5( .A(line0), .B(line4), .Y(ParOut) );
endmodule // ParityTree8bit
/***************************************************************************
* Module: Buffer34
***************************************************************************/
module Buffer34( Inbus, Outbus );
input [33:0] Inbus;
output [33:0] Outbus;
Buffer8 Buf34_0( Inbus[7:0], Outbus[7:0] ),
Buf34_1( Inbus[15:8], Outbus[15:8] ),
Buf34_2( Inbus[23:16], Outbus[23:16] ),
Buf34_3( Inbus[31:24], Outbus[31:24] );
buffer Buf34_4( .A(Inbus[32]), .Y(Outbus[32]) ),
Buf34_5( .A(Inbus[33]), .Y(Outbus[33]) );
endmodule // Buffer34
/******************************************************/
module Buffer8( Inbus, Outbus );
input [7:0] Inbus;
output [7:0] Outbus;
Buffer4 Buf8_0( Inbus[3:0], Outbus[3:0] ),
Buf8_1( Inbus[7:4], Outbus[7:4] );
endmodule // Buffer8
/******************************************************/
module Buffer4( Inbus, Outbus );
input [3:0] Inbus;
output [3:0] Outbus;
buffer Buf4_0( .A(Inbus[0]), .Y(Outbus[0]) ),
Buf4_1( .A(Inbus[1]), .Y(Outbus[1]) ),
Buf4_2( .A(Inbus[2]), .Y(Outbus[2]) ),
Buf4_3( .A(Inbus[3]), .Y(Outbus[3]) );
endmodule // Buffer4
/***************************************************************************
* Module: MiscLogic
*
* Function: just a random collection of a few gates.
*
***************************************************************************/
module MiscLogic( MiscInbus, MiscOutbus );
input [7:0] MiscInbus;
output [5:0] MiscOutbus;
buffer UM12_0( .A(MiscInbus[0]), .Y(MiscOutbus[0]) );
and2 UM12_1( .A(MiscInbus[0]), .B(MiscInbus[1]), .Y(MiscOutbus[1]) );
inv UM12_2( .A(MiscInbus[2]), .Y(MiscOutbus[2]) );
and2 UM12_3( .A(MiscInbus[4]), .B(MiscInbus[5]), .Y(line3) );
inv UM12_4( .A(MiscInbus[6]), .Y(line4) );
nand2 UM12_5( .A(line3), .B(line4), .Y(MiscOutbus[3]) );
nand2 UM12_6( .A(MiscInbus[3]), .B(line4), .Y(MiscOutbus[4]) );
inv UM12_7( .A(MiscInbus[7]), .Y(line7) );
nand2 UM12_8( .A(line7), .B(line4), .Y(MiscOutbus[5]) );
endmodule // MiscLogic
/***************************************************************************
* Description of some basic gates/modules
***************************************************************************/
module Mux2_1( In1, In2, ContIn, Out );
input In1, In2, ContIn;
output Out;
inv Mux0( .A(ContIn), .Y(Not_ContIn) );
and2 Mux1( .A(In1), .B(Not_ContIn), .Y(line1) ),
Mux2( .A(In2), .B(ContIn), .Y(line2) );
or2 Mux3( .A(line1), .B(line2), .Y(Out) );
endmodule // Mux2_1
/********************************************/
module AND_OR2( O, P, Q, YY);
input O, P, Q;
output YY;
and2 Ao2_0( .A(P), .B(Q), .Y(line0) );
or2 Ao2_1( .A(O), .B(line0), .Y(YY) );
endmodule // AND_OR2
/******************************************************/
module AND_OR3a( O, P, Q, R, S, YY);
input O, P, Q, R, S;
output YY;
and2 Ao3a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao3a_1( .A(P), .B(R), .C(S), .Y(line1) );
or3 Ao3a_2( .A(O), .B(line0), .C(line1), .Y(YY) );
endmodule // AND_OR3a
/******************************************************/
module AND_OR3b( O, P, Q, R, YY);
input O, P, Q, R;
output YY;
and2 Ao3a_0( .A(P), .B(Q), .Y(line0) );
and2 Ao3a_1( .A(P), .B(R), .Y(line1) );
or3 Ao3a_2( .A(O), .B(line0), .C(line1), .Y(YY) );
endmodule // AND_OR3b
/******************************************************/
module AND_OR4a( O, P, Q, R, S, T, U, YY);
input O, P, Q, R, S, T, U;
output YY;
and2 Ao4a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao4a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao4a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
or4 Ao4a_3( .A(O), .B(line0), .C(line1), .D(line2), .Y(YY) );
endmodule // AND_OR4a
/******************************************************/
module AND_OR4b( O, P, Q, R, S, T, YY);
input O, P, Q, R, S, T;
output YY;
and2 Ao4a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao4a_1( .A(P), .B(R), .C(S), .Y(line1) );
and3 Ao4a_2( .A(P), .B(R), .C(T), .Y(line2) );
or4 Ao4a_3( .A(O), .B(line0), .C(line1), .D(line2), .Y(YY) );
endmodule // AND_OR4a
/******************************************************/
module AND_OR5a( O, P, Q, R, S, T, U, V, W, YY);
input O, P, Q, R, S, T, U, V, W;
output YY;
and2 Ao5a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao5a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao5a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
and5 Ao5a_3( .A(P), .B(R), .C(T), .D(V), .E(W), .Y(line3) );
or5 Ao5a_4( .A(O), .B(line0), .C(line1), .D(line2), .E(line3), .Y(YY) );
endmodule // AND_OR5a
/******************************************************/
module AND_OR5b( O, P, Q, R, S, T, U, V, YY);
input O, P, Q, R, S, T, U, V;
output YY;
and2 Ao5a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao5a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao5a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
and4 Ao5a_3( .A(P), .B(R), .C(T), .D(V), .Y(line3) );
or5 Ao5a_4( .A(O), .B(line0), .C(line1), .D(line2), .E(line3), .Y(YY) );
endmodule // AND_OR5b
/******************************************************/
module AND_OR6a( O, P, Q, R, S, T, U, V, W, X, Y, YY);
input O, P, Q, R, S, T, U, V, W, X, Y;
output YY;
and2 Ao6a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao6a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao6a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
and5 Ao6a_3( .A(P), .B(R), .C(T), .D(V), .E(W), .Y(line3) );
and6 Ao6a_4( .A(P), .B(R), .C(T), .D(V), .E(X), .F(Y), .Y(line4) );
or6 Ao6a_5( .A(O), .B(line0), .C(line1), .D(line2), .E(line3),
.F(line4), .Y(YY) );
endmodule // AND_OR6a
/******************************************************/
module AND_OR6b( O, P, Q, R, S, T, U, V, W, X, YY);
input O, P, Q, R, S, T, U, V, W, X;
output YY;
and2 Ao6a_0( .A(P), .B(Q), .Y(line0) );
and3 Ao6a_1( .A(P), .B(R), .C(S), .Y(line1) );
and4 Ao6a_2( .A(P), .B(R), .C(T), .D(U), .Y(line2) );
and5 Ao6a_3( .A(P), .B(R), .C(T), .D(V), .E(W), .Y(line3) );
and5 Ao6a_4( .A(P), .B(R), .C(T), .D(V), .E(X), .Y(line4) );
or6 Ao6a_5( .A(O), .B(line0), .C(line1), .D(line2), .E(line3),
.F(line4), .Y(YY) );
endmodule // AND_OR6b
/********************************************/
module XOR2a ( A, B, Y );
input A, B;
output Y;
inv Xo0( .A(A), .Y(NotA) ),
Xo1( .A(B), .Y(NotB) );
nand2 Xo2( .A(NotA), .B(B), .Y(line2) ),
Xo3( .A(NotB), .B(A), .Y(line3) ),
Xo4( .A(line2), .B(line3), .Y(Y) );
endmodule // XOR2a
/********************************************/
module XOR3a( A, B, C, Y);
input A, B, C;
output Y;
inv Xo3_0( .A(A), .Y(NotA) ),
Xo3_1( .A(B), .Y(NotB) ),
Xo3_2( .A(C), .Y(NotC) );
and3 Xo3_3( .A(NotA), .B(NotB), .C(C), .Y(line3) ),
Xo3_4( .A(NotA), .B(B), .C(NotC), .Y(line4) ),
Xo3_5( .A(A), .B(NotB), .C(NotC), .Y(line5) ),
Xo3_6( .A(A), .B(B), .C(C), .Y(line6) );
nor2 Xo3_7( .A(line3), .B(line4), .Y(line7) ),
Xo3_8( .A(line5), .B(line6), .Y(line8) );
nand2 Xo3_9( .A(line7), .B(line8), .Y(Y) );
endmodule // XOR3a
|
Added c7552/flat7552.v.
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 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2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 | /**************************************************************************** * * * FLAT VERSION of HIGH-LEVEL MODEL for c7552 * * * * * * Generated by: Hakan Yalcin (hyalcin@cadence.com) * * Verified by: Jonathan David Hauke (jhauke@eecs.umich.edu) * * * * Oct 20, 1998 * * * ****************************************************************************/ // Flat Verilog File module c7552g ( in213, in214, in215, in216, in209, in153, in154, in155, in156, in157, in158, in159, in160, in151, in219, in220, in221, in222, in223, in224, in225, in226, in217, in231, in232, in233, in234, in235, in236, in237, in238, in135, in144, in138, in147, in66, in50, in32, in35, in47, in121, in94, in97, in118, in100, in124, in127, in130, in103, in23, in26, in29, in41, in1486, in1480, in106, in1469, in1462, in2256, in2253, in2247, in2239, in2236, in2230, in2224, in2218, in2211, in4437, in4432, in4427, in4420, in4415, in4410, in4405, in4400, in4394, in3749, in3743, in3737, in3729, in3723, in3717, in3711, in3705, in88, in112, in87, in111, in113, in110, in109, in86, in63, in64, in85, in84, in83, in65, in62, in61, in60, in79, in80, in81, in59, in78, in77, in56, in55, in54, in53, in73, in75, in76, in74, in166, in167, in168, in169, in173, in174, in175, in176, in177, in178, in179, in180, in171, in189, in190, in191, in192, in193, in194, in195, in196, in187, in200, in201, in202, in203, in204, in205, in206, in207, in18, in12, in9, in4526, in89, in38, in4528, in211, in212, in161, in227, in239, in229, in141, in115, in44, in1459, in1496, in1492, in2208, in4393, in3701, in3698, in114, in2204, in1455, in82, in58, in70, in69, in170, in164, in165, in181, in197, in208, in198, in199, in188, in172, in162, in186, in185, in182, in183, in230, in218, in152, in210, in240, in228, in184, in150, in1, in163, in15, in1197, in134, in133, in5, in57, in339, out469, out471, out327, out330, out333, out336, out324, out298, out301, out304, out307, out310, out313, out316, out319, out295, out347, out350, out353, out356, out359, out362, out365, out368, out344, out376, out379, out382, out385, out388, out391, out394, out397, out373, out419, out422, out270, out246, out273, out276, out258, out264, out249, out252, out338, out321, out370, out399, out416, out414, out412, out418, out410, out408, out406, out404, out440, out438, out442, out444, out446, out448, out436, out480, out482, out484, out486, out488, out490, out492, out494, out478, out524, out526, out528, out530, out532, out534, out536, out538, out522, out544, out546, out548, out550, out552, out554, out556, out558, out542, out450, out496, out540, out560, out402, out289, out292, out279, out278, out2, out3, out432, out453, out286, out341, out281, out284, out339); input in213, in214, in215, in216, in209, in153, in154, in155, in156, in157, in158, in159, in160, in151, in219, in220, in221, in222, in223, in224, in225, in226, in217, in231, in232, in233, in234, in235, in236, in237, in238, in135, in144, in138, in147, in66, in50, in32, in35, in47, in121, in94, in97, in118, in100, in124, in127, in130, in103, in23, in26, in29, in41, in1486, in1480, in106, in1469, in1462, in2256, in2253, in2247, in2239, in2236, in2230, in2224, in2218, in2211, in4437, in4432, in4427, in4420, in4415, in4410, in4405, in4400, in4394, in3749, in3743, in3737, in3729, in3723, in3717, in3711, in3705, in88, in112, in87, in111, in113, in110, in109, in86, in63, in64, in85, in84, in83, in65, in62, in61, in60, in79, in80, in81, in59, in78, in77, in56, in55, in54, in53, in73, in75, in76, in74, in166, in167, in168, in169, in173, in174, in175, in176, in177, in178, in179, in180, in171, in189, in190, in191, in192, in193, in194, in195, in196, in187, in200, in201, in202, in203, in204, in205, in206, in207, in18, in12, in9, in4526, in89, in38, in4528, in211, in212, in161, in227, in239, in229, in141, in115, in44, in1459, in1496, in1492, in2208, in4393, in3701, in3698, in114, in2204, in1455, in82, in58, in70, in69, in170, in164, in165, in181, in197, in208, in198, in199, in188, in172, in162, in186, in185, in182, in183, in230, in218, in152, in210, in240, in228, in184, in150, in1, in163, in15, in1197, in134, in133, in5, in57, in339; output out469, out471, out327, out330, out333, out336, out324, out298, out301, out304, out307, out310, out313, out316, out319, out295, out347, out350, out353, out356, out359, out362, out365, out368, out344, out376, out379, out382, out385, out388, out391, out394, out397, out373, out419, out422, out270, out246, out273, out276, out258, out264, out249, out252, out338, out321, out370, out399, out416, out414, out412, out418, out410, out408, out406, out404, out440, out438, out442, out444, out446, out448, out436, out480, out482, out484, out486, out488, out490, out492, out494, out478, out524, out526, out528, out530, out532, out534, out536, out538, out522, out544, out546, out548, out550, out552, out554, out556, out558, out542, out450, out496, out540, out560, out402, out289, out292, out279, out278, out2, out3, out432, out453, out286, out341, out281, out284, out339; nand2 M0(in12, in9, ContBusMask); inv M00(in18, MuxSel); inv M1_UM1_0_MM0_Mux32_0_Mux8_0_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_0_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_0_Mux8_0_Mux1(gnd, M1_UM1_0_MM0_Mux32_0_Mux8_0_Not_ContIn, M1_UM1_0_MM0_Mux32_0_Mux8_0_line1); and2 M1_UM1_0_MM0_Mux32_0_Mux8_0_Mux2(in41, MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_0_line2); or2 M1_UM1_0_MM0_Mux32_0_Mux8_0_Mux3(M1_UM1_0_MM0_Mux32_0_Mux8_0_line1, M1_UM1_0_MM0_Mux32_0_Mux8_0_line2, XAbus_0); inv M1_UM1_0_MM0_Mux32_0_Mux8_1_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_1_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_0_Mux8_1_Mux1(in238, M1_UM1_0_MM0_Mux32_0_Mux8_1_Not_ContIn, M1_UM1_0_MM0_Mux32_0_Mux8_1_line1); and2 M1_UM1_0_MM0_Mux32_0_Mux8_1_Mux2(in29, MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_1_line2); or2 M1_UM1_0_MM0_Mux32_0_Mux8_1_Mux3(M1_UM1_0_MM0_Mux32_0_Mux8_1_line1, M1_UM1_0_MM0_Mux32_0_Mux8_1_line2, XAbus_1); inv M1_UM1_0_MM0_Mux32_0_Mux8_2_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_2_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_0_Mux8_2_Mux1(in237, M1_UM1_0_MM0_Mux32_0_Mux8_2_Not_ContIn, M1_UM1_0_MM0_Mux32_0_Mux8_2_line1); and2 M1_UM1_0_MM0_Mux32_0_Mux8_2_Mux2(in26, MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_2_line2); or2 M1_UM1_0_MM0_Mux32_0_Mux8_2_Mux3(M1_UM1_0_MM0_Mux32_0_Mux8_2_line1, M1_UM1_0_MM0_Mux32_0_Mux8_2_line2, XAbus_2); inv M1_UM1_0_MM0_Mux32_0_Mux8_3_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_3_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_0_Mux8_3_Mux1(in236, M1_UM1_0_MM0_Mux32_0_Mux8_3_Not_ContIn, M1_UM1_0_MM0_Mux32_0_Mux8_3_line1); and2 M1_UM1_0_MM0_Mux32_0_Mux8_3_Mux2(in23, MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_3_line2); or2 M1_UM1_0_MM0_Mux32_0_Mux8_3_Mux3(M1_UM1_0_MM0_Mux32_0_Mux8_3_line1, M1_UM1_0_MM0_Mux32_0_Mux8_3_line2, XAbus_3); inv M1_UM1_0_MM0_Mux32_0_Mux8_4_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_4_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_0_Mux8_4_Mux1(in235, M1_UM1_0_MM0_Mux32_0_Mux8_4_Not_ContIn, M1_UM1_0_MM0_Mux32_0_Mux8_4_line1); and2 M1_UM1_0_MM0_Mux32_0_Mux8_4_Mux2(in103, MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_4_line2); or2 M1_UM1_0_MM0_Mux32_0_Mux8_4_Mux3(M1_UM1_0_MM0_Mux32_0_Mux8_4_line1, M1_UM1_0_MM0_Mux32_0_Mux8_4_line2, XAbus_4); inv M1_UM1_0_MM0_Mux32_0_Mux8_5_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_5_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_0_Mux8_5_Mux1(in234, M1_UM1_0_MM0_Mux32_0_Mux8_5_Not_ContIn, M1_UM1_0_MM0_Mux32_0_Mux8_5_line1); and2 M1_UM1_0_MM0_Mux32_0_Mux8_5_Mux2(in130, MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_5_line2); or2 M1_UM1_0_MM0_Mux32_0_Mux8_5_Mux3(M1_UM1_0_MM0_Mux32_0_Mux8_5_line1, M1_UM1_0_MM0_Mux32_0_Mux8_5_line2, XAbus_5); inv M1_UM1_0_MM0_Mux32_0_Mux8_6_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_6_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_0_Mux8_6_Mux1(in233, M1_UM1_0_MM0_Mux32_0_Mux8_6_Not_ContIn, M1_UM1_0_MM0_Mux32_0_Mux8_6_line1); and2 M1_UM1_0_MM0_Mux32_0_Mux8_6_Mux2(in127, MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_6_line2); or2 M1_UM1_0_MM0_Mux32_0_Mux8_6_Mux3(M1_UM1_0_MM0_Mux32_0_Mux8_6_line1, M1_UM1_0_MM0_Mux32_0_Mux8_6_line2, XAbus_6); inv M1_UM1_0_MM0_Mux32_0_Mux8_7_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_7_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_0_Mux8_7_Mux1(in232, M1_UM1_0_MM0_Mux32_0_Mux8_7_Not_ContIn, M1_UM1_0_MM0_Mux32_0_Mux8_7_line1); and2 M1_UM1_0_MM0_Mux32_0_Mux8_7_Mux2(in124, MuxSel, M1_UM1_0_MM0_Mux32_0_Mux8_7_line2); or2 M1_UM1_0_MM0_Mux32_0_Mux8_7_Mux3(M1_UM1_0_MM0_Mux32_0_Mux8_7_line1, M1_UM1_0_MM0_Mux32_0_Mux8_7_line2, XAbus_7); inv M1_UM1_0_MM0_Mux32_1_Mux8_0_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_0_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_1_Mux8_0_Mux1(in231, M1_UM1_0_MM0_Mux32_1_Mux8_0_Not_ContIn, M1_UM1_0_MM0_Mux32_1_Mux8_0_line1); and2 M1_UM1_0_MM0_Mux32_1_Mux8_0_Mux2(in100, MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_0_line2); or2 M1_UM1_0_MM0_Mux32_1_Mux8_0_Mux3(M1_UM1_0_MM0_Mux32_1_Mux8_0_line1, M1_UM1_0_MM0_Mux32_1_Mux8_0_line2, XAbus_8); inv M1_UM1_0_MM0_Mux32_1_Mux8_1_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_1_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_1_Mux8_1_Mux1(in217, M1_UM1_0_MM0_Mux32_1_Mux8_1_Not_ContIn, M1_UM1_0_MM0_Mux32_1_Mux8_1_line1); and2 M1_UM1_0_MM0_Mux32_1_Mux8_1_Mux2(in118, MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_1_line2); or2 M1_UM1_0_MM0_Mux32_1_Mux8_1_Mux3(M1_UM1_0_MM0_Mux32_1_Mux8_1_line1, M1_UM1_0_MM0_Mux32_1_Mux8_1_line2, XAbus_9); inv M1_UM1_0_MM0_Mux32_1_Mux8_2_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_2_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_1_Mux8_2_Mux1(in226, M1_UM1_0_MM0_Mux32_1_Mux8_2_Not_ContIn, M1_UM1_0_MM0_Mux32_1_Mux8_2_line1); and2 M1_UM1_0_MM0_Mux32_1_Mux8_2_Mux2(in97, MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_2_line2); or2 M1_UM1_0_MM0_Mux32_1_Mux8_2_Mux3(M1_UM1_0_MM0_Mux32_1_Mux8_2_line1, M1_UM1_0_MM0_Mux32_1_Mux8_2_line2, XAbus_10); inv M1_UM1_0_MM0_Mux32_1_Mux8_3_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_3_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_1_Mux8_3_Mux1(in225, M1_UM1_0_MM0_Mux32_1_Mux8_3_Not_ContIn, M1_UM1_0_MM0_Mux32_1_Mux8_3_line1); and2 M1_UM1_0_MM0_Mux32_1_Mux8_3_Mux2(in94, MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_3_line2); or2 M1_UM1_0_MM0_Mux32_1_Mux8_3_Mux3(M1_UM1_0_MM0_Mux32_1_Mux8_3_line1, M1_UM1_0_MM0_Mux32_1_Mux8_3_line2, XAbus_11); inv M1_UM1_0_MM0_Mux32_1_Mux8_4_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_4_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_1_Mux8_4_Mux1(in224, M1_UM1_0_MM0_Mux32_1_Mux8_4_Not_ContIn, M1_UM1_0_MM0_Mux32_1_Mux8_4_line1); and2 M1_UM1_0_MM0_Mux32_1_Mux8_4_Mux2(in121, MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_4_line2); or2 M1_UM1_0_MM0_Mux32_1_Mux8_4_Mux3(M1_UM1_0_MM0_Mux32_1_Mux8_4_line1, M1_UM1_0_MM0_Mux32_1_Mux8_4_line2, XAbus_12); inv M1_UM1_0_MM0_Mux32_1_Mux8_5_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_5_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_1_Mux8_5_Mux1(in223, M1_UM1_0_MM0_Mux32_1_Mux8_5_Not_ContIn, M1_UM1_0_MM0_Mux32_1_Mux8_5_line1); and2 M1_UM1_0_MM0_Mux32_1_Mux8_5_Mux2(in47, MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_5_line2); or2 M1_UM1_0_MM0_Mux32_1_Mux8_5_Mux3(M1_UM1_0_MM0_Mux32_1_Mux8_5_line1, M1_UM1_0_MM0_Mux32_1_Mux8_5_line2, XAbus_13); inv M1_UM1_0_MM0_Mux32_1_Mux8_6_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_6_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_1_Mux8_6_Mux1(in222, M1_UM1_0_MM0_Mux32_1_Mux8_6_Not_ContIn, M1_UM1_0_MM0_Mux32_1_Mux8_6_line1); and2 M1_UM1_0_MM0_Mux32_1_Mux8_6_Mux2(in35, MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_6_line2); or2 M1_UM1_0_MM0_Mux32_1_Mux8_6_Mux3(M1_UM1_0_MM0_Mux32_1_Mux8_6_line1, M1_UM1_0_MM0_Mux32_1_Mux8_6_line2, XAbus_14); inv M1_UM1_0_MM0_Mux32_1_Mux8_7_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_7_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_1_Mux8_7_Mux1(in221, M1_UM1_0_MM0_Mux32_1_Mux8_7_Not_ContIn, M1_UM1_0_MM0_Mux32_1_Mux8_7_line1); and2 M1_UM1_0_MM0_Mux32_1_Mux8_7_Mux2(in32, MuxSel, M1_UM1_0_MM0_Mux32_1_Mux8_7_line2); or2 M1_UM1_0_MM0_Mux32_1_Mux8_7_Mux3(M1_UM1_0_MM0_Mux32_1_Mux8_7_line1, M1_UM1_0_MM0_Mux32_1_Mux8_7_line2, XAbus_15); inv M1_UM1_0_MM0_Mux32_2_Mux8_0_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_0_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_2_Mux8_0_Mux1(in220, M1_UM1_0_MM0_Mux32_2_Mux8_0_Not_ContIn, M1_UM1_0_MM0_Mux32_2_Mux8_0_line1); and2 M1_UM1_0_MM0_Mux32_2_Mux8_0_Mux2(in50, MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_0_line2); or2 M1_UM1_0_MM0_Mux32_2_Mux8_0_Mux3(M1_UM1_0_MM0_Mux32_2_Mux8_0_line1, M1_UM1_0_MM0_Mux32_2_Mux8_0_line2, XAbus_16); inv M1_UM1_0_MM0_Mux32_2_Mux8_1_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_1_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_2_Mux8_1_Mux1(in219, M1_UM1_0_MM0_Mux32_2_Mux8_1_Not_ContIn, M1_UM1_0_MM0_Mux32_2_Mux8_1_line1); and2 M1_UM1_0_MM0_Mux32_2_Mux8_1_Mux2(in66, MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_1_line2); or2 M1_UM1_0_MM0_Mux32_2_Mux8_1_Mux3(M1_UM1_0_MM0_Mux32_2_Mux8_1_line1, M1_UM1_0_MM0_Mux32_2_Mux8_1_line2, XAbus_17); inv M1_UM1_0_MM0_Mux32_2_Mux8_2_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_2_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_2_Mux8_2_Mux1(in151, M1_UM1_0_MM0_Mux32_2_Mux8_2_Not_ContIn, M1_UM1_0_MM0_Mux32_2_Mux8_2_line1); and2 M1_UM1_0_MM0_Mux32_2_Mux8_2_Mux2(in147, MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_2_line2); or2 M1_UM1_0_MM0_Mux32_2_Mux8_2_Mux3(M1_UM1_0_MM0_Mux32_2_Mux8_2_line1, M1_UM1_0_MM0_Mux32_2_Mux8_2_line2, XAbus_18); inv M1_UM1_0_MM0_Mux32_2_Mux8_3_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_3_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_2_Mux8_3_Mux1(in160, M1_UM1_0_MM0_Mux32_2_Mux8_3_Not_ContIn, M1_UM1_0_MM0_Mux32_2_Mux8_3_line1); and2 M1_UM1_0_MM0_Mux32_2_Mux8_3_Mux2(in138, MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_3_line2); or2 M1_UM1_0_MM0_Mux32_2_Mux8_3_Mux3(M1_UM1_0_MM0_Mux32_2_Mux8_3_line1, M1_UM1_0_MM0_Mux32_2_Mux8_3_line2, XAbus_19); inv M1_UM1_0_MM0_Mux32_2_Mux8_4_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_4_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_2_Mux8_4_Mux1(in159, M1_UM1_0_MM0_Mux32_2_Mux8_4_Not_ContIn, M1_UM1_0_MM0_Mux32_2_Mux8_4_line1); and2 M1_UM1_0_MM0_Mux32_2_Mux8_4_Mux2(in144, MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_4_line2); or2 M1_UM1_0_MM0_Mux32_2_Mux8_4_Mux3(M1_UM1_0_MM0_Mux32_2_Mux8_4_line1, M1_UM1_0_MM0_Mux32_2_Mux8_4_line2, XAbus_20); inv M1_UM1_0_MM0_Mux32_2_Mux8_5_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_5_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_2_Mux8_5_Mux1(in158, M1_UM1_0_MM0_Mux32_2_Mux8_5_Not_ContIn, M1_UM1_0_MM0_Mux32_2_Mux8_5_line1); and2 M1_UM1_0_MM0_Mux32_2_Mux8_5_Mux2(in135, MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_5_line2); or2 M1_UM1_0_MM0_Mux32_2_Mux8_5_Mux3(M1_UM1_0_MM0_Mux32_2_Mux8_5_line1, M1_UM1_0_MM0_Mux32_2_Mux8_5_line2, XAbus_21); inv M1_UM1_0_MM0_Mux32_2_Mux8_6_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_6_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_2_Mux8_6_Mux1(in157, M1_UM1_0_MM0_Mux32_2_Mux8_6_Not_ContIn, M1_UM1_0_MM0_Mux32_2_Mux8_6_line1); and2 M1_UM1_0_MM0_Mux32_2_Mux8_6_Mux2(vdd, MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_6_line2); or2 M1_UM1_0_MM0_Mux32_2_Mux8_6_Mux3(M1_UM1_0_MM0_Mux32_2_Mux8_6_line1, M1_UM1_0_MM0_Mux32_2_Mux8_6_line2, M1_UM1_0_MuxOutbus_22); inv M1_UM1_0_MM0_Mux32_2_Mux8_7_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_7_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_2_Mux8_7_Mux1(in156, M1_UM1_0_MM0_Mux32_2_Mux8_7_Not_ContIn, M1_UM1_0_MM0_Mux32_2_Mux8_7_line1); and2 M1_UM1_0_MM0_Mux32_2_Mux8_7_Mux2(vdd, MuxSel, M1_UM1_0_MM0_Mux32_2_Mux8_7_line2); or2 M1_UM1_0_MM0_Mux32_2_Mux8_7_Mux3(M1_UM1_0_MM0_Mux32_2_Mux8_7_line1, M1_UM1_0_MM0_Mux32_2_Mux8_7_line2, M1_UM1_0_MuxOutbus_23); inv M1_UM1_0_MM0_Mux32_3_Mux8_0_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_0_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_3_Mux8_0_Mux1(in155, M1_UM1_0_MM0_Mux32_3_Mux8_0_Not_ContIn, M1_UM1_0_MM0_Mux32_3_Mux8_0_line1); and2 M1_UM1_0_MM0_Mux32_3_Mux8_0_Mux2(vdd, MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_0_line2); or2 M1_UM1_0_MM0_Mux32_3_Mux8_0_Mux3(M1_UM1_0_MM0_Mux32_3_Mux8_0_line1, M1_UM1_0_MM0_Mux32_3_Mux8_0_line2, M1_UM1_0_MuxOutbus_24); inv M1_UM1_0_MM0_Mux32_3_Mux8_1_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_1_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_3_Mux8_1_Mux1(in154, M1_UM1_0_MM0_Mux32_3_Mux8_1_Not_ContIn, M1_UM1_0_MM0_Mux32_3_Mux8_1_line1); and2 M1_UM1_0_MM0_Mux32_3_Mux8_1_Mux2(vdd, MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_1_line2); or2 M1_UM1_0_MM0_Mux32_3_Mux8_1_Mux3(M1_UM1_0_MM0_Mux32_3_Mux8_1_line1, M1_UM1_0_MM0_Mux32_3_Mux8_1_line2, M1_UM1_0_MuxOutbus_25); inv M1_UM1_0_MM0_Mux32_3_Mux8_2_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_2_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_3_Mux8_2_Mux1(in153, M1_UM1_0_MM0_Mux32_3_Mux8_2_Not_ContIn, M1_UM1_0_MM0_Mux32_3_Mux8_2_line1); and2 M1_UM1_0_MM0_Mux32_3_Mux8_2_Mux2(vdd, MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_2_line2); or2 M1_UM1_0_MM0_Mux32_3_Mux8_2_Mux3(M1_UM1_0_MM0_Mux32_3_Mux8_2_line1, M1_UM1_0_MM0_Mux32_3_Mux8_2_line2, M1_UM1_0_MuxOutbus_26); inv M1_UM1_0_MM0_Mux32_3_Mux8_3_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_3_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_3_Mux8_3_Mux1(in209, M1_UM1_0_MM0_Mux32_3_Mux8_3_Not_ContIn, M1_UM1_0_MM0_Mux32_3_Mux8_3_line1); and2 M1_UM1_0_MM0_Mux32_3_Mux8_3_Mux2(vdd, MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_3_line2); or2 M1_UM1_0_MM0_Mux32_3_Mux8_3_Mux3(M1_UM1_0_MM0_Mux32_3_Mux8_3_line1, M1_UM1_0_MM0_Mux32_3_Mux8_3_line2, M1_UM1_0_MuxOutbus_27); inv M1_UM1_0_MM0_Mux32_3_Mux8_4_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_4_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_3_Mux8_4_Mux1(in216, M1_UM1_0_MM0_Mux32_3_Mux8_4_Not_ContIn, M1_UM1_0_MM0_Mux32_3_Mux8_4_line1); and2 M1_UM1_0_MM0_Mux32_3_Mux8_4_Mux2(vdd, MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_4_line2); or2 M1_UM1_0_MM0_Mux32_3_Mux8_4_Mux3(M1_UM1_0_MM0_Mux32_3_Mux8_4_line1, M1_UM1_0_MM0_Mux32_3_Mux8_4_line2, M1_UM1_0_MuxOutbus_28); inv M1_UM1_0_MM0_Mux32_3_Mux8_5_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_5_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_3_Mux8_5_Mux1(in215, M1_UM1_0_MM0_Mux32_3_Mux8_5_Not_ContIn, M1_UM1_0_MM0_Mux32_3_Mux8_5_line1); and2 M1_UM1_0_MM0_Mux32_3_Mux8_5_Mux2(vdd, MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_5_line2); or2 M1_UM1_0_MM0_Mux32_3_Mux8_5_Mux3(M1_UM1_0_MM0_Mux32_3_Mux8_5_line1, M1_UM1_0_MM0_Mux32_3_Mux8_5_line2, M1_UM1_0_MuxOutbus_29); inv M1_UM1_0_MM0_Mux32_3_Mux8_6_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_6_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_3_Mux8_6_Mux1(in214, M1_UM1_0_MM0_Mux32_3_Mux8_6_Not_ContIn, M1_UM1_0_MM0_Mux32_3_Mux8_6_line1); and2 M1_UM1_0_MM0_Mux32_3_Mux8_6_Mux2(vdd, MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_6_line2); or2 M1_UM1_0_MM0_Mux32_3_Mux8_6_Mux3(M1_UM1_0_MM0_Mux32_3_Mux8_6_line1, M1_UM1_0_MM0_Mux32_3_Mux8_6_line2, M1_UM1_0_MuxOutbus_30); inv M1_UM1_0_MM0_Mux32_3_Mux8_7_Mux0(MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_7_Not_ContIn); and2 M1_UM1_0_MM0_Mux32_3_Mux8_7_Mux1(in213, M1_UM1_0_MM0_Mux32_3_Mux8_7_Not_ContIn, M1_UM1_0_MM0_Mux32_3_Mux8_7_line1); and2 M1_UM1_0_MM0_Mux32_3_Mux8_7_Mux2(vdd, MuxSel, M1_UM1_0_MM0_Mux32_3_Mux8_7_line2); or2 M1_UM1_0_MM0_Mux32_3_Mux8_7_Mux3(M1_UM1_0_MM0_Mux32_3_Mux8_7_line1, M1_UM1_0_MM0_Mux32_3_Mux8_7_line2, M1_UM1_0_MuxOutbus_31); and2 M1_UM1_0_MM1(M1_UM1_0_MuxOutbus_22, ContBusMask, XAbus_22); and2 M1_UM1_0_MM2(M1_UM1_0_MuxOutbus_23, ContBusMask, XAbus_23); and2 M1_UM1_0_MM3(M1_UM1_0_MuxOutbus_24, ContBusMask, XAbus_24); and2 M1_UM1_0_MM4(M1_UM1_0_MuxOutbus_25, ContBusMask, XAbus_25); and2 M1_UM1_0_MM5(M1_UM1_0_MuxOutbus_26, ContBusMask, XAbus_26); and2 M1_UM1_0_MM6(M1_UM1_0_MuxOutbus_27, ContBusMask, XAbus_27); and2 M1_UM1_0_MM7(M1_UM1_0_MuxOutbus_28, ContBusMask, XAbus_28); and2 M1_UM1_0_MM8(M1_UM1_0_MuxOutbus_29, ContBusMask, XAbus_29); and2 M1_UM1_0_MM9(M1_UM1_0_MuxOutbus_30, ContBusMask, XAbus_30); and2 M1_UM1_0_MM10(M1_UM1_0_MuxOutbus_31, ContBusMask, XAbus_31); inv M2_UM2_0_Mux0(MuxSel, M2_UM2_0_Not_ContIn); and2 M2_UM2_0_Mux1(gnd, M2_UM2_0_Not_ContIn, M2_UM2_0_line1); and2 M2_UM2_0_Mux2(in3701, MuxSel, M2_UM2_0_line2); or2 M2_UM2_0_Mux3(M2_UM2_0_line1, M2_UM2_0_line2, M2_AuxXBbus_0); and2 M2_UM2_1(in1492, in4528, M2_AuxXBbus_32); and2 M2_UM2_2(in1496, in4528, M2_AuxXBbus_33); inv M2_UM2_3_Inv34_0_Inv8_0(M2_AuxXBbus_0, Not_XBbus_0); inv M2_UM2_3_Inv34_0_Inv8_1(in3705, Not_XBbus_1); inv M2_UM2_3_Inv34_0_Inv8_2(in3711, Not_XBbus_2); inv M2_UM2_3_Inv34_0_Inv8_3(in3717, Not_XBbus_3); inv M2_UM2_3_Inv34_0_Inv8_4(in3723, Not_XBbus_4); inv M2_UM2_3_Inv34_0_Inv8_5(in3729, Not_XBbus_5); inv M2_UM2_3_Inv34_0_Inv8_6(in3737, Not_XBbus_6); inv M2_UM2_3_Inv34_0_Inv8_7(in3743, Not_XBbus_7); inv M2_UM2_3_Inv34_1_Inv8_0(in3749, Not_XBbus_8); inv M2_UM2_3_Inv34_1_Inv8_1(in4394, Not_XBbus_9); inv M2_UM2_3_Inv34_1_Inv8_2(in4400, Not_XBbus_10); inv M2_UM2_3_Inv34_1_Inv8_3(in4405, Not_XBbus_11); inv M2_UM2_3_Inv34_1_Inv8_4(in4410, Not_XBbus_12); inv M2_UM2_3_Inv34_1_Inv8_5(in4415, Not_XBbus_13); inv M2_UM2_3_Inv34_1_Inv8_6(in4420, Not_XBbus_14); inv M2_UM2_3_Inv34_1_Inv8_7(in4427, Not_XBbus_15); inv M2_UM2_3_Inv34_2_Inv8_0(in4432, Not_XBbus_16); inv M2_UM2_3_Inv34_2_Inv8_1(in4437, Not_XBbus_17); inv M2_UM2_3_Inv34_2_Inv8_2(in2211, Not_XBbus_18); inv M2_UM2_3_Inv34_2_Inv8_3(in2218, Not_XBbus_19); inv M2_UM2_3_Inv34_2_Inv8_4(in2224, Not_XBbus_20); inv M2_UM2_3_Inv34_2_Inv8_5(in2230, Not_XBbus_21); inv M2_UM2_3_Inv34_2_Inv8_6(in2236, Not_XBbus_22); inv M2_UM2_3_Inv34_2_Inv8_7(in2239, Not_XBbus_23); inv M2_UM2_3_Inv34_3_Inv8_0(in2247, Not_XBbus_24); inv M2_UM2_3_Inv34_3_Inv8_1(in2253, Not_XBbus_25); inv M2_UM2_3_Inv34_3_Inv8_2(in2256, Not_XBbus_26); inv M2_UM2_3_Inv34_3_Inv8_3(in1462, Not_XBbus_27); inv M2_UM2_3_Inv34_3_Inv8_4(in1469, Not_XBbus_28); inv M2_UM2_3_Inv34_3_Inv8_5(in106, Not_XBbus_29); inv M2_UM2_3_Inv34_3_Inv8_6(in1480, Not_XBbus_30); inv M2_UM2_3_Inv34_3_Inv8_7(in1486, Not_XBbus_31); inv M2_UM2_3_Inv34_4(M2_AuxXBbus_32, Not_XBbus_32); inv M2_UM2_3_Inv34_5(M2_AuxXBbus_33, Not_XBbus_33); inv M3_UM3_0_Mux32_0_Mux8_0_Mux0(MuxSel, M3_UM3_0_Mux32_0_Mux8_0_Not_ContIn); and2 M3_UM3_0_Mux32_0_Mux8_0_Mux1(vdd, M3_UM3_0_Mux32_0_Mux8_0_Not_ContIn, M3_UM3_0_Mux32_0_Mux8_0_line1); and2 M3_UM3_0_Mux32_0_Mux8_0_Mux2(in70, MuxSel, M3_UM3_0_Mux32_0_Mux8_0_line2); or2 M3_UM3_0_Mux32_0_Mux8_0_Mux3(M3_UM3_0_Mux32_0_Mux8_0_line1, M3_UM3_0_Mux32_0_Mux8_0_line2, YAbus_0); inv M3_UM3_0_Mux32_0_Mux8_1_Mux0(MuxSel, M3_UM3_0_Mux32_0_Mux8_1_Not_ContIn); and2 M3_UM3_0_Mux32_0_Mux8_1_Mux1(Not_XBbus_1, M3_UM3_0_Mux32_0_Mux8_1_Not_ContIn, M3_UM3_0_Mux32_0_Mux8_1_line1); and2 M3_UM3_0_Mux32_0_Mux8_1_Mux2(in74, MuxSel, M3_UM3_0_Mux32_0_Mux8_1_line2); or2 M3_UM3_0_Mux32_0_Mux8_1_Mux3(M3_UM3_0_Mux32_0_Mux8_1_line1, M3_UM3_0_Mux32_0_Mux8_1_line2, YAbus_1); inv M3_UM3_0_Mux32_0_Mux8_2_Mux0(MuxSel, M3_UM3_0_Mux32_0_Mux8_2_Not_ContIn); and2 M3_UM3_0_Mux32_0_Mux8_2_Mux1(Not_XBbus_2, M3_UM3_0_Mux32_0_Mux8_2_Not_ContIn, M3_UM3_0_Mux32_0_Mux8_2_line1); and2 M3_UM3_0_Mux32_0_Mux8_2_Mux2(in76, MuxSel, M3_UM3_0_Mux32_0_Mux8_2_line2); or2 M3_UM3_0_Mux32_0_Mux8_2_Mux3(M3_UM3_0_Mux32_0_Mux8_2_line1, M3_UM3_0_Mux32_0_Mux8_2_line2, YAbus_2); inv M3_UM3_0_Mux32_0_Mux8_3_Mux0(MuxSel, M3_UM3_0_Mux32_0_Mux8_3_Not_ContIn); and2 M3_UM3_0_Mux32_0_Mux8_3_Mux1(Not_XBbus_3, M3_UM3_0_Mux32_0_Mux8_3_Not_ContIn, M3_UM3_0_Mux32_0_Mux8_3_line1); and2 M3_UM3_0_Mux32_0_Mux8_3_Mux2(in75, MuxSel, M3_UM3_0_Mux32_0_Mux8_3_line2); or2 M3_UM3_0_Mux32_0_Mux8_3_Mux3(M3_UM3_0_Mux32_0_Mux8_3_line1, M3_UM3_0_Mux32_0_Mux8_3_line2, YAbus_3); inv M3_UM3_0_Mux32_0_Mux8_4_Mux0(MuxSel, M3_UM3_0_Mux32_0_Mux8_4_Not_ContIn); and2 M3_UM3_0_Mux32_0_Mux8_4_Mux1(Not_XBbus_4, M3_UM3_0_Mux32_0_Mux8_4_Not_ContIn, M3_UM3_0_Mux32_0_Mux8_4_line1); and2 M3_UM3_0_Mux32_0_Mux8_4_Mux2(in73, MuxSel, M3_UM3_0_Mux32_0_Mux8_4_line2); or2 M3_UM3_0_Mux32_0_Mux8_4_Mux3(M3_UM3_0_Mux32_0_Mux8_4_line1, M3_UM3_0_Mux32_0_Mux8_4_line2, YAbus_4); inv M3_UM3_0_Mux32_0_Mux8_5_Mux0(MuxSel, M3_UM3_0_Mux32_0_Mux8_5_Not_ContIn); and2 M3_UM3_0_Mux32_0_Mux8_5_Mux1(Not_XBbus_5, M3_UM3_0_Mux32_0_Mux8_5_Not_ContIn, M3_UM3_0_Mux32_0_Mux8_5_line1); and2 M3_UM3_0_Mux32_0_Mux8_5_Mux2(in53, MuxSel, M3_UM3_0_Mux32_0_Mux8_5_line2); or2 M3_UM3_0_Mux32_0_Mux8_5_Mux3(M3_UM3_0_Mux32_0_Mux8_5_line1, M3_UM3_0_Mux32_0_Mux8_5_line2, YAbus_5); inv M3_UM3_0_Mux32_0_Mux8_6_Mux0(MuxSel, M3_UM3_0_Mux32_0_Mux8_6_Not_ContIn); and2 M3_UM3_0_Mux32_0_Mux8_6_Mux1(Not_XBbus_6, M3_UM3_0_Mux32_0_Mux8_6_Not_ContIn, M3_UM3_0_Mux32_0_Mux8_6_line1); and2 M3_UM3_0_Mux32_0_Mux8_6_Mux2(in54, MuxSel, M3_UM3_0_Mux32_0_Mux8_6_line2); or2 M3_UM3_0_Mux32_0_Mux8_6_Mux3(M3_UM3_0_Mux32_0_Mux8_6_line1, M3_UM3_0_Mux32_0_Mux8_6_line2, YAbus_6); inv M3_UM3_0_Mux32_0_Mux8_7_Mux0(MuxSel, M3_UM3_0_Mux32_0_Mux8_7_Not_ContIn); and2 M3_UM3_0_Mux32_0_Mux8_7_Mux1(Not_XBbus_7, M3_UM3_0_Mux32_0_Mux8_7_Not_ContIn, M3_UM3_0_Mux32_0_Mux8_7_line1); and2 M3_UM3_0_Mux32_0_Mux8_7_Mux2(in55, MuxSel, M3_UM3_0_Mux32_0_Mux8_7_line2); or2 M3_UM3_0_Mux32_0_Mux8_7_Mux3(M3_UM3_0_Mux32_0_Mux8_7_line1, M3_UM3_0_Mux32_0_Mux8_7_line2, YAbus_7); inv M3_UM3_0_Mux32_1_Mux8_0_Mux0(MuxSel, M3_UM3_0_Mux32_1_Mux8_0_Not_ContIn); and2 M3_UM3_0_Mux32_1_Mux8_0_Mux1(Not_XBbus_8, M3_UM3_0_Mux32_1_Mux8_0_Not_ContIn, M3_UM3_0_Mux32_1_Mux8_0_line1); and2 M3_UM3_0_Mux32_1_Mux8_0_Mux2(in56, MuxSel, M3_UM3_0_Mux32_1_Mux8_0_line2); or2 M3_UM3_0_Mux32_1_Mux8_0_Mux3(M3_UM3_0_Mux32_1_Mux8_0_line1, M3_UM3_0_Mux32_1_Mux8_0_line2, YAbus_8); inv M3_UM3_0_Mux32_1_Mux8_1_Mux0(MuxSel, M3_UM3_0_Mux32_1_Mux8_1_Not_ContIn); and2 M3_UM3_0_Mux32_1_Mux8_1_Mux1(Not_XBbus_9, M3_UM3_0_Mux32_1_Mux8_1_Not_ContIn, M3_UM3_0_Mux32_1_Mux8_1_line1); and2 M3_UM3_0_Mux32_1_Mux8_1_Mux2(in77, MuxSel, M3_UM3_0_Mux32_1_Mux8_1_line2); or2 M3_UM3_0_Mux32_1_Mux8_1_Mux3(M3_UM3_0_Mux32_1_Mux8_1_line1, M3_UM3_0_Mux32_1_Mux8_1_line2, YAbus_9); inv M3_UM3_0_Mux32_1_Mux8_2_Mux0(MuxSel, M3_UM3_0_Mux32_1_Mux8_2_Not_ContIn); and2 M3_UM3_0_Mux32_1_Mux8_2_Mux1(Not_XBbus_10, M3_UM3_0_Mux32_1_Mux8_2_Not_ContIn, M3_UM3_0_Mux32_1_Mux8_2_line1); and2 M3_UM3_0_Mux32_1_Mux8_2_Mux2(in78, MuxSel, M3_UM3_0_Mux32_1_Mux8_2_line2); or2 M3_UM3_0_Mux32_1_Mux8_2_Mux3(M3_UM3_0_Mux32_1_Mux8_2_line1, M3_UM3_0_Mux32_1_Mux8_2_line2, YAbus_10); inv M3_UM3_0_Mux32_1_Mux8_3_Mux0(MuxSel, M3_UM3_0_Mux32_1_Mux8_3_Not_ContIn); and2 M3_UM3_0_Mux32_1_Mux8_3_Mux1(Not_XBbus_11, M3_UM3_0_Mux32_1_Mux8_3_Not_ContIn, M3_UM3_0_Mux32_1_Mux8_3_line1); and2 M3_UM3_0_Mux32_1_Mux8_3_Mux2(in59, MuxSel, M3_UM3_0_Mux32_1_Mux8_3_line2); or2 M3_UM3_0_Mux32_1_Mux8_3_Mux3(M3_UM3_0_Mux32_1_Mux8_3_line1, M3_UM3_0_Mux32_1_Mux8_3_line2, YAbus_11); inv M3_UM3_0_Mux32_1_Mux8_4_Mux0(MuxSel, M3_UM3_0_Mux32_1_Mux8_4_Not_ContIn); and2 M3_UM3_0_Mux32_1_Mux8_4_Mux1(Not_XBbus_12, M3_UM3_0_Mux32_1_Mux8_4_Not_ContIn, M3_UM3_0_Mux32_1_Mux8_4_line1); and2 M3_UM3_0_Mux32_1_Mux8_4_Mux2(in81, MuxSel, M3_UM3_0_Mux32_1_Mux8_4_line2); or2 M3_UM3_0_Mux32_1_Mux8_4_Mux3(M3_UM3_0_Mux32_1_Mux8_4_line1, M3_UM3_0_Mux32_1_Mux8_4_line2, YAbus_12); inv M3_UM3_0_Mux32_1_Mux8_5_Mux0(MuxSel, M3_UM3_0_Mux32_1_Mux8_5_Not_ContIn); and2 M3_UM3_0_Mux32_1_Mux8_5_Mux1(Not_XBbus_13, M3_UM3_0_Mux32_1_Mux8_5_Not_ContIn, M3_UM3_0_Mux32_1_Mux8_5_line1); and2 M3_UM3_0_Mux32_1_Mux8_5_Mux2(in80, MuxSel, M3_UM3_0_Mux32_1_Mux8_5_line2); or2 M3_UM3_0_Mux32_1_Mux8_5_Mux3(M3_UM3_0_Mux32_1_Mux8_5_line1, M3_UM3_0_Mux32_1_Mux8_5_line2, YAbus_13); inv M3_UM3_0_Mux32_1_Mux8_6_Mux0(MuxSel, M3_UM3_0_Mux32_1_Mux8_6_Not_ContIn); and2 M3_UM3_0_Mux32_1_Mux8_6_Mux1(Not_XBbus_14, M3_UM3_0_Mux32_1_Mux8_6_Not_ContIn, M3_UM3_0_Mux32_1_Mux8_6_line1); and2 M3_UM3_0_Mux32_1_Mux8_6_Mux2(in79, MuxSel, M3_UM3_0_Mux32_1_Mux8_6_line2); or2 M3_UM3_0_Mux32_1_Mux8_6_Mux3(M3_UM3_0_Mux32_1_Mux8_6_line1, M3_UM3_0_Mux32_1_Mux8_6_line2, YAbus_14); inv M3_UM3_0_Mux32_1_Mux8_7_Mux0(MuxSel, M3_UM3_0_Mux32_1_Mux8_7_Not_ContIn); and2 M3_UM3_0_Mux32_1_Mux8_7_Mux1(Not_XBbus_15, M3_UM3_0_Mux32_1_Mux8_7_Not_ContIn, M3_UM3_0_Mux32_1_Mux8_7_line1); and2 M3_UM3_0_Mux32_1_Mux8_7_Mux2(in60, MuxSel, M3_UM3_0_Mux32_1_Mux8_7_line2); or2 M3_UM3_0_Mux32_1_Mux8_7_Mux3(M3_UM3_0_Mux32_1_Mux8_7_line1, M3_UM3_0_Mux32_1_Mux8_7_line2, YAbus_15); inv M3_UM3_0_Mux32_2_Mux8_0_Mux0(MuxSel, M3_UM3_0_Mux32_2_Mux8_0_Not_ContIn); and2 M3_UM3_0_Mux32_2_Mux8_0_Mux1(Not_XBbus_16, M3_UM3_0_Mux32_2_Mux8_0_Not_ContIn, M3_UM3_0_Mux32_2_Mux8_0_line1); and2 M3_UM3_0_Mux32_2_Mux8_0_Mux2(in61, MuxSel, M3_UM3_0_Mux32_2_Mux8_0_line2); or2 M3_UM3_0_Mux32_2_Mux8_0_Mux3(M3_UM3_0_Mux32_2_Mux8_0_line1, M3_UM3_0_Mux32_2_Mux8_0_line2, YAbus_16); inv M3_UM3_0_Mux32_2_Mux8_1_Mux0(MuxSel, M3_UM3_0_Mux32_2_Mux8_1_Not_ContIn); and2 M3_UM3_0_Mux32_2_Mux8_1_Mux1(Not_XBbus_17, M3_UM3_0_Mux32_2_Mux8_1_Not_ContIn, M3_UM3_0_Mux32_2_Mux8_1_line1); and2 M3_UM3_0_Mux32_2_Mux8_1_Mux2(in62, MuxSel, M3_UM3_0_Mux32_2_Mux8_1_line2); or2 M3_UM3_0_Mux32_2_Mux8_1_Mux3(M3_UM3_0_Mux32_2_Mux8_1_line1, M3_UM3_0_Mux32_2_Mux8_1_line2, YAbus_17); inv M3_UM3_0_Mux32_2_Mux8_2_Mux0(MuxSel, M3_UM3_0_Mux32_2_Mux8_2_Not_ContIn); and2 M3_UM3_0_Mux32_2_Mux8_2_Mux1(Not_XBbus_18, M3_UM3_0_Mux32_2_Mux8_2_Not_ContIn, M3_UM3_0_Mux32_2_Mux8_2_line1); and2 M3_UM3_0_Mux32_2_Mux8_2_Mux2(in65, MuxSel, M3_UM3_0_Mux32_2_Mux8_2_line2); or2 M3_UM3_0_Mux32_2_Mux8_2_Mux3(M3_UM3_0_Mux32_2_Mux8_2_line1, M3_UM3_0_Mux32_2_Mux8_2_line2, YAbus_18); inv M3_UM3_0_Mux32_2_Mux8_3_Mux0(MuxSel, M3_UM3_0_Mux32_2_Mux8_3_Not_ContIn); and2 M3_UM3_0_Mux32_2_Mux8_3_Mux1(Not_XBbus_19, M3_UM3_0_Mux32_2_Mux8_3_Not_ContIn, M3_UM3_0_Mux32_2_Mux8_3_line1); and2 M3_UM3_0_Mux32_2_Mux8_3_Mux2(in83, MuxSel, M3_UM3_0_Mux32_2_Mux8_3_line2); or2 M3_UM3_0_Mux32_2_Mux8_3_Mux3(M3_UM3_0_Mux32_2_Mux8_3_line1, M3_UM3_0_Mux32_2_Mux8_3_line2, YAbus_19); inv M3_UM3_0_Mux32_2_Mux8_4_Mux0(MuxSel, M3_UM3_0_Mux32_2_Mux8_4_Not_ContIn); and2 M3_UM3_0_Mux32_2_Mux8_4_Mux1(Not_XBbus_20, M3_UM3_0_Mux32_2_Mux8_4_Not_ContIn, M3_UM3_0_Mux32_2_Mux8_4_line1); and2 M3_UM3_0_Mux32_2_Mux8_4_Mux2(in84, MuxSel, M3_UM3_0_Mux32_2_Mux8_4_line2); or2 M3_UM3_0_Mux32_2_Mux8_4_Mux3(M3_UM3_0_Mux32_2_Mux8_4_line1, M3_UM3_0_Mux32_2_Mux8_4_line2, YAbus_20); inv M3_UM3_0_Mux32_2_Mux8_5_Mux0(MuxSel, M3_UM3_0_Mux32_2_Mux8_5_Not_ContIn); and2 M3_UM3_0_Mux32_2_Mux8_5_Mux1(Not_XBbus_21, M3_UM3_0_Mux32_2_Mux8_5_Not_ContIn, M3_UM3_0_Mux32_2_Mux8_5_line1); and2 M3_UM3_0_Mux32_2_Mux8_5_Mux2(in85, MuxSel, M3_UM3_0_Mux32_2_Mux8_5_line2); or2 M3_UM3_0_Mux32_2_Mux8_5_Mux3(M3_UM3_0_Mux32_2_Mux8_5_line1, M3_UM3_0_Mux32_2_Mux8_5_line2, YAbus_21); inv M3_UM3_0_Mux32_2_Mux8_6_Mux0(MuxSel, M3_UM3_0_Mux32_2_Mux8_6_Not_ContIn); and2 M3_UM3_0_Mux32_2_Mux8_6_Mux1(Not_XBbus_22, M3_UM3_0_Mux32_2_Mux8_6_Not_ContIn, M3_UM3_0_Mux32_2_Mux8_6_line1); and2 M3_UM3_0_Mux32_2_Mux8_6_Mux2(in64, MuxSel, M3_UM3_0_Mux32_2_Mux8_6_line2); or2 M3_UM3_0_Mux32_2_Mux8_6_Mux3(M3_UM3_0_Mux32_2_Mux8_6_line1, M3_UM3_0_Mux32_2_Mux8_6_line2, YAbus_22); inv M3_UM3_0_Mux32_2_Mux8_7_Mux0(MuxSel, M3_UM3_0_Mux32_2_Mux8_7_Not_ContIn); and2 M3_UM3_0_Mux32_2_Mux8_7_Mux1(Not_XBbus_23, M3_UM3_0_Mux32_2_Mux8_7_Not_ContIn, M3_UM3_0_Mux32_2_Mux8_7_line1); and2 M3_UM3_0_Mux32_2_Mux8_7_Mux2(in63, MuxSel, M3_UM3_0_Mux32_2_Mux8_7_line2); or2 M3_UM3_0_Mux32_2_Mux8_7_Mux3(M3_UM3_0_Mux32_2_Mux8_7_line1, M3_UM3_0_Mux32_2_Mux8_7_line2, YAbus_23); inv M3_UM3_0_Mux32_3_Mux8_0_Mux0(MuxSel, M3_UM3_0_Mux32_3_Mux8_0_Not_ContIn); and2 M3_UM3_0_Mux32_3_Mux8_0_Mux1(Not_XBbus_24, M3_UM3_0_Mux32_3_Mux8_0_Not_ContIn, M3_UM3_0_Mux32_3_Mux8_0_line1); and2 M3_UM3_0_Mux32_3_Mux8_0_Mux2(in86, MuxSel, M3_UM3_0_Mux32_3_Mux8_0_line2); or2 M3_UM3_0_Mux32_3_Mux8_0_Mux3(M3_UM3_0_Mux32_3_Mux8_0_line1, M3_UM3_0_Mux32_3_Mux8_0_line2, YAbus_24); inv M3_UM3_0_Mux32_3_Mux8_1_Mux0(MuxSel, M3_UM3_0_Mux32_3_Mux8_1_Not_ContIn); and2 M3_UM3_0_Mux32_3_Mux8_1_Mux1(Not_XBbus_25, M3_UM3_0_Mux32_3_Mux8_1_Not_ContIn, M3_UM3_0_Mux32_3_Mux8_1_line1); and2 M3_UM3_0_Mux32_3_Mux8_1_Mux2(in109, MuxSel, M3_UM3_0_Mux32_3_Mux8_1_line2); or2 M3_UM3_0_Mux32_3_Mux8_1_Mux3(M3_UM3_0_Mux32_3_Mux8_1_line1, M3_UM3_0_Mux32_3_Mux8_1_line2, YAbus_25); inv M3_UM3_0_Mux32_3_Mux8_2_Mux0(MuxSel, M3_UM3_0_Mux32_3_Mux8_2_Not_ContIn); and2 M3_UM3_0_Mux32_3_Mux8_2_Mux1(Not_XBbus_26, M3_UM3_0_Mux32_3_Mux8_2_Not_ContIn, M3_UM3_0_Mux32_3_Mux8_2_line1); and2 M3_UM3_0_Mux32_3_Mux8_2_Mux2(in110, MuxSel, M3_UM3_0_Mux32_3_Mux8_2_line2); or2 M3_UM3_0_Mux32_3_Mux8_2_Mux3(M3_UM3_0_Mux32_3_Mux8_2_line1, M3_UM3_0_Mux32_3_Mux8_2_line2, YAbus_26); inv M3_UM3_0_Mux32_3_Mux8_3_Mux0(MuxSel, M3_UM3_0_Mux32_3_Mux8_3_Not_ContIn); and2 M3_UM3_0_Mux32_3_Mux8_3_Mux1(Not_XBbus_27, M3_UM3_0_Mux32_3_Mux8_3_Not_ContIn, M3_UM3_0_Mux32_3_Mux8_3_line1); and2 M3_UM3_0_Mux32_3_Mux8_3_Mux2(in113, MuxSel, M3_UM3_0_Mux32_3_Mux8_3_line2); or2 M3_UM3_0_Mux32_3_Mux8_3_Mux3(M3_UM3_0_Mux32_3_Mux8_3_line1, M3_UM3_0_Mux32_3_Mux8_3_line2, YAbus_27); inv M3_UM3_0_Mux32_3_Mux8_4_Mux0(MuxSel, M3_UM3_0_Mux32_3_Mux8_4_Not_ContIn); and2 M3_UM3_0_Mux32_3_Mux8_4_Mux1(Not_XBbus_28, M3_UM3_0_Mux32_3_Mux8_4_Not_ContIn, M3_UM3_0_Mux32_3_Mux8_4_line1); and2 M3_UM3_0_Mux32_3_Mux8_4_Mux2(in111, MuxSel, M3_UM3_0_Mux32_3_Mux8_4_line2); or2 M3_UM3_0_Mux32_3_Mux8_4_Mux3(M3_UM3_0_Mux32_3_Mux8_4_line1, M3_UM3_0_Mux32_3_Mux8_4_line2, YAbus_28); inv M3_UM3_0_Mux32_3_Mux8_5_Mux0(MuxSel, M3_UM3_0_Mux32_3_Mux8_5_Not_ContIn); and2 M3_UM3_0_Mux32_3_Mux8_5_Mux1(Not_XBbus_29, M3_UM3_0_Mux32_3_Mux8_5_Not_ContIn, M3_UM3_0_Mux32_3_Mux8_5_line1); and2 M3_UM3_0_Mux32_3_Mux8_5_Mux2(in87, MuxSel, M3_UM3_0_Mux32_3_Mux8_5_line2); or2 M3_UM3_0_Mux32_3_Mux8_5_Mux3(M3_UM3_0_Mux32_3_Mux8_5_line1, M3_UM3_0_Mux32_3_Mux8_5_line2, YAbus_29); inv M3_UM3_0_Mux32_3_Mux8_6_Mux0(MuxSel, M3_UM3_0_Mux32_3_Mux8_6_Not_ContIn); and2 M3_UM3_0_Mux32_3_Mux8_6_Mux1(Not_XBbus_30, M3_UM3_0_Mux32_3_Mux8_6_Not_ContIn, M3_UM3_0_Mux32_3_Mux8_6_line1); and2 M3_UM3_0_Mux32_3_Mux8_6_Mux2(in112, MuxSel, M3_UM3_0_Mux32_3_Mux8_6_line2); or2 M3_UM3_0_Mux32_3_Mux8_6_Mux3(M3_UM3_0_Mux32_3_Mux8_6_line1, M3_UM3_0_Mux32_3_Mux8_6_line2, YAbus_30); inv M3_UM3_0_Mux32_3_Mux8_7_Mux0(MuxSel, M3_UM3_0_Mux32_3_Mux8_7_Not_ContIn); and2 M3_UM3_0_Mux32_3_Mux8_7_Mux1(Not_XBbus_31, M3_UM3_0_Mux32_3_Mux8_7_Not_ContIn, M3_UM3_0_Mux32_3_Mux8_7_line1); and2 M3_UM3_0_Mux32_3_Mux8_7_Mux2(in88, MuxSel, M3_UM3_0_Mux32_3_Mux8_7_line2); or2 M3_UM3_0_Mux32_3_Mux8_7_Mux3(M3_UM3_0_Mux32_3_Mux8_7_line1, M3_UM3_0_Mux32_3_Mux8_7_line2, YAbus_31); inv M4_UM4_0_MM0_Mux32_0_Mux8_0_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_0_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_0_Mux8_0_Mux1(gnd, M4_UM4_0_MM0_Mux32_0_Mux8_0_Not_ContIn, M4_UM4_0_MM0_Mux32_0_Mux8_0_line1); and2 M4_UM4_0_MM0_Mux32_0_Mux8_0_Mux2(in41, MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_0_line2); or2 M4_UM4_0_MM0_Mux32_0_Mux8_0_Mux3(M4_UM4_0_MM0_Mux32_0_Mux8_0_line1, M4_UM4_0_MM0_Mux32_0_Mux8_0_line2, YBbus_0); inv M4_UM4_0_MM0_Mux32_0_Mux8_1_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_1_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_0_Mux8_1_Mux1(in207, M4_UM4_0_MM0_Mux32_0_Mux8_1_Not_ContIn, M4_UM4_0_MM0_Mux32_0_Mux8_1_line1); and2 M4_UM4_0_MM0_Mux32_0_Mux8_1_Mux2(in29, MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_1_line2); or2 M4_UM4_0_MM0_Mux32_0_Mux8_1_Mux3(M4_UM4_0_MM0_Mux32_0_Mux8_1_line1, M4_UM4_0_MM0_Mux32_0_Mux8_1_line2, YBbus_1); inv M4_UM4_0_MM0_Mux32_0_Mux8_2_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_2_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_0_Mux8_2_Mux1(in206, M4_UM4_0_MM0_Mux32_0_Mux8_2_Not_ContIn, M4_UM4_0_MM0_Mux32_0_Mux8_2_line1); and2 M4_UM4_0_MM0_Mux32_0_Mux8_2_Mux2(in26, MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_2_line2); or2 M4_UM4_0_MM0_Mux32_0_Mux8_2_Mux3(M4_UM4_0_MM0_Mux32_0_Mux8_2_line1, M4_UM4_0_MM0_Mux32_0_Mux8_2_line2, YBbus_2); inv M4_UM4_0_MM0_Mux32_0_Mux8_3_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_3_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_0_Mux8_3_Mux1(in205, M4_UM4_0_MM0_Mux32_0_Mux8_3_Not_ContIn, M4_UM4_0_MM0_Mux32_0_Mux8_3_line1); and2 M4_UM4_0_MM0_Mux32_0_Mux8_3_Mux2(in23, MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_3_line2); or2 M4_UM4_0_MM0_Mux32_0_Mux8_3_Mux3(M4_UM4_0_MM0_Mux32_0_Mux8_3_line1, M4_UM4_0_MM0_Mux32_0_Mux8_3_line2, YBbus_3); inv M4_UM4_0_MM0_Mux32_0_Mux8_4_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_4_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_0_Mux8_4_Mux1(in204, M4_UM4_0_MM0_Mux32_0_Mux8_4_Not_ContIn, M4_UM4_0_MM0_Mux32_0_Mux8_4_line1); and2 M4_UM4_0_MM0_Mux32_0_Mux8_4_Mux2(in103, MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_4_line2); or2 M4_UM4_0_MM0_Mux32_0_Mux8_4_Mux3(M4_UM4_0_MM0_Mux32_0_Mux8_4_line1, M4_UM4_0_MM0_Mux32_0_Mux8_4_line2, YBbus_4); inv M4_UM4_0_MM0_Mux32_0_Mux8_5_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_5_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_0_Mux8_5_Mux1(in203, M4_UM4_0_MM0_Mux32_0_Mux8_5_Not_ContIn, M4_UM4_0_MM0_Mux32_0_Mux8_5_line1); and2 M4_UM4_0_MM0_Mux32_0_Mux8_5_Mux2(in130, MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_5_line2); or2 M4_UM4_0_MM0_Mux32_0_Mux8_5_Mux3(M4_UM4_0_MM0_Mux32_0_Mux8_5_line1, M4_UM4_0_MM0_Mux32_0_Mux8_5_line2, YBbus_5); inv M4_UM4_0_MM0_Mux32_0_Mux8_6_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_6_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_0_Mux8_6_Mux1(in202, M4_UM4_0_MM0_Mux32_0_Mux8_6_Not_ContIn, M4_UM4_0_MM0_Mux32_0_Mux8_6_line1); and2 M4_UM4_0_MM0_Mux32_0_Mux8_6_Mux2(in127, MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_6_line2); or2 M4_UM4_0_MM0_Mux32_0_Mux8_6_Mux3(M4_UM4_0_MM0_Mux32_0_Mux8_6_line1, M4_UM4_0_MM0_Mux32_0_Mux8_6_line2, YBbus_6); inv M4_UM4_0_MM0_Mux32_0_Mux8_7_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_7_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_0_Mux8_7_Mux1(in201, M4_UM4_0_MM0_Mux32_0_Mux8_7_Not_ContIn, M4_UM4_0_MM0_Mux32_0_Mux8_7_line1); and2 M4_UM4_0_MM0_Mux32_0_Mux8_7_Mux2(in124, MuxSel, M4_UM4_0_MM0_Mux32_0_Mux8_7_line2); or2 M4_UM4_0_MM0_Mux32_0_Mux8_7_Mux3(M4_UM4_0_MM0_Mux32_0_Mux8_7_line1, M4_UM4_0_MM0_Mux32_0_Mux8_7_line2, YBbus_7); inv M4_UM4_0_MM0_Mux32_1_Mux8_0_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_0_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_1_Mux8_0_Mux1(in200, M4_UM4_0_MM0_Mux32_1_Mux8_0_Not_ContIn, M4_UM4_0_MM0_Mux32_1_Mux8_0_line1); and2 M4_UM4_0_MM0_Mux32_1_Mux8_0_Mux2(in100, MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_0_line2); or2 M4_UM4_0_MM0_Mux32_1_Mux8_0_Mux3(M4_UM4_0_MM0_Mux32_1_Mux8_0_line1, M4_UM4_0_MM0_Mux32_1_Mux8_0_line2, YBbus_8); inv M4_UM4_0_MM0_Mux32_1_Mux8_1_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_1_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_1_Mux8_1_Mux1(in187, M4_UM4_0_MM0_Mux32_1_Mux8_1_Not_ContIn, M4_UM4_0_MM0_Mux32_1_Mux8_1_line1); and2 M4_UM4_0_MM0_Mux32_1_Mux8_1_Mux2(in118, MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_1_line2); or2 M4_UM4_0_MM0_Mux32_1_Mux8_1_Mux3(M4_UM4_0_MM0_Mux32_1_Mux8_1_line1, M4_UM4_0_MM0_Mux32_1_Mux8_1_line2, YBbus_9); inv M4_UM4_0_MM0_Mux32_1_Mux8_2_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_2_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_1_Mux8_2_Mux1(in196, M4_UM4_0_MM0_Mux32_1_Mux8_2_Not_ContIn, M4_UM4_0_MM0_Mux32_1_Mux8_2_line1); and2 M4_UM4_0_MM0_Mux32_1_Mux8_2_Mux2(in97, MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_2_line2); or2 M4_UM4_0_MM0_Mux32_1_Mux8_2_Mux3(M4_UM4_0_MM0_Mux32_1_Mux8_2_line1, M4_UM4_0_MM0_Mux32_1_Mux8_2_line2, YBbus_10); inv M4_UM4_0_MM0_Mux32_1_Mux8_3_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_3_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_1_Mux8_3_Mux1(in195, M4_UM4_0_MM0_Mux32_1_Mux8_3_Not_ContIn, M4_UM4_0_MM0_Mux32_1_Mux8_3_line1); and2 M4_UM4_0_MM0_Mux32_1_Mux8_3_Mux2(in94, MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_3_line2); or2 M4_UM4_0_MM0_Mux32_1_Mux8_3_Mux3(M4_UM4_0_MM0_Mux32_1_Mux8_3_line1, M4_UM4_0_MM0_Mux32_1_Mux8_3_line2, YBbus_11); inv M4_UM4_0_MM0_Mux32_1_Mux8_4_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_4_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_1_Mux8_4_Mux1(in194, M4_UM4_0_MM0_Mux32_1_Mux8_4_Not_ContIn, M4_UM4_0_MM0_Mux32_1_Mux8_4_line1); and2 M4_UM4_0_MM0_Mux32_1_Mux8_4_Mux2(in121, MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_4_line2); or2 M4_UM4_0_MM0_Mux32_1_Mux8_4_Mux3(M4_UM4_0_MM0_Mux32_1_Mux8_4_line1, M4_UM4_0_MM0_Mux32_1_Mux8_4_line2, YBbus_12); inv M4_UM4_0_MM0_Mux32_1_Mux8_5_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_5_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_1_Mux8_5_Mux1(in193, M4_UM4_0_MM0_Mux32_1_Mux8_5_Not_ContIn, M4_UM4_0_MM0_Mux32_1_Mux8_5_line1); and2 M4_UM4_0_MM0_Mux32_1_Mux8_5_Mux2(in47, MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_5_line2); or2 M4_UM4_0_MM0_Mux32_1_Mux8_5_Mux3(M4_UM4_0_MM0_Mux32_1_Mux8_5_line1, M4_UM4_0_MM0_Mux32_1_Mux8_5_line2, YBbus_13); inv M4_UM4_0_MM0_Mux32_1_Mux8_6_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_6_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_1_Mux8_6_Mux1(in192, M4_UM4_0_MM0_Mux32_1_Mux8_6_Not_ContIn, M4_UM4_0_MM0_Mux32_1_Mux8_6_line1); and2 M4_UM4_0_MM0_Mux32_1_Mux8_6_Mux2(in35, MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_6_line2); or2 M4_UM4_0_MM0_Mux32_1_Mux8_6_Mux3(M4_UM4_0_MM0_Mux32_1_Mux8_6_line1, M4_UM4_0_MM0_Mux32_1_Mux8_6_line2, YBbus_14); inv M4_UM4_0_MM0_Mux32_1_Mux8_7_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_7_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_1_Mux8_7_Mux1(in191, M4_UM4_0_MM0_Mux32_1_Mux8_7_Not_ContIn, M4_UM4_0_MM0_Mux32_1_Mux8_7_line1); and2 M4_UM4_0_MM0_Mux32_1_Mux8_7_Mux2(in32, MuxSel, M4_UM4_0_MM0_Mux32_1_Mux8_7_line2); or2 M4_UM4_0_MM0_Mux32_1_Mux8_7_Mux3(M4_UM4_0_MM0_Mux32_1_Mux8_7_line1, M4_UM4_0_MM0_Mux32_1_Mux8_7_line2, YBbus_15); inv M4_UM4_0_MM0_Mux32_2_Mux8_0_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_0_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_2_Mux8_0_Mux1(in190, M4_UM4_0_MM0_Mux32_2_Mux8_0_Not_ContIn, M4_UM4_0_MM0_Mux32_2_Mux8_0_line1); and2 M4_UM4_0_MM0_Mux32_2_Mux8_0_Mux2(in50, MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_0_line2); or2 M4_UM4_0_MM0_Mux32_2_Mux8_0_Mux3(M4_UM4_0_MM0_Mux32_2_Mux8_0_line1, M4_UM4_0_MM0_Mux32_2_Mux8_0_line2, YBbus_16); inv M4_UM4_0_MM0_Mux32_2_Mux8_1_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_1_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_2_Mux8_1_Mux1(in189, M4_UM4_0_MM0_Mux32_2_Mux8_1_Not_ContIn, M4_UM4_0_MM0_Mux32_2_Mux8_1_line1); and2 M4_UM4_0_MM0_Mux32_2_Mux8_1_Mux2(in66, MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_1_line2); or2 M4_UM4_0_MM0_Mux32_2_Mux8_1_Mux3(M4_UM4_0_MM0_Mux32_2_Mux8_1_line1, M4_UM4_0_MM0_Mux32_2_Mux8_1_line2, YBbus_17); inv M4_UM4_0_MM0_Mux32_2_Mux8_2_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_2_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_2_Mux8_2_Mux1(in171, M4_UM4_0_MM0_Mux32_2_Mux8_2_Not_ContIn, M4_UM4_0_MM0_Mux32_2_Mux8_2_line1); and2 M4_UM4_0_MM0_Mux32_2_Mux8_2_Mux2(in147, MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_2_line2); or2 M4_UM4_0_MM0_Mux32_2_Mux8_2_Mux3(M4_UM4_0_MM0_Mux32_2_Mux8_2_line1, M4_UM4_0_MM0_Mux32_2_Mux8_2_line2, YBbus_18); inv M4_UM4_0_MM0_Mux32_2_Mux8_3_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_3_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_2_Mux8_3_Mux1(in180, M4_UM4_0_MM0_Mux32_2_Mux8_3_Not_ContIn, M4_UM4_0_MM0_Mux32_2_Mux8_3_line1); and2 M4_UM4_0_MM0_Mux32_2_Mux8_3_Mux2(in138, MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_3_line2); or2 M4_UM4_0_MM0_Mux32_2_Mux8_3_Mux3(M4_UM4_0_MM0_Mux32_2_Mux8_3_line1, M4_UM4_0_MM0_Mux32_2_Mux8_3_line2, YBbus_19); inv M4_UM4_0_MM0_Mux32_2_Mux8_4_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_4_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_2_Mux8_4_Mux1(in179, M4_UM4_0_MM0_Mux32_2_Mux8_4_Not_ContIn, M4_UM4_0_MM0_Mux32_2_Mux8_4_line1); and2 M4_UM4_0_MM0_Mux32_2_Mux8_4_Mux2(in144, MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_4_line2); or2 M4_UM4_0_MM0_Mux32_2_Mux8_4_Mux3(M4_UM4_0_MM0_Mux32_2_Mux8_4_line1, M4_UM4_0_MM0_Mux32_2_Mux8_4_line2, YBbus_20); inv M4_UM4_0_MM0_Mux32_2_Mux8_5_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_5_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_2_Mux8_5_Mux1(in178, M4_UM4_0_MM0_Mux32_2_Mux8_5_Not_ContIn, M4_UM4_0_MM0_Mux32_2_Mux8_5_line1); and2 M4_UM4_0_MM0_Mux32_2_Mux8_5_Mux2(in135, MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_5_line2); or2 M4_UM4_0_MM0_Mux32_2_Mux8_5_Mux3(M4_UM4_0_MM0_Mux32_2_Mux8_5_line1, M4_UM4_0_MM0_Mux32_2_Mux8_5_line2, YBbus_21); inv M4_UM4_0_MM0_Mux32_2_Mux8_6_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_6_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_2_Mux8_6_Mux1(in177, M4_UM4_0_MM0_Mux32_2_Mux8_6_Not_ContIn, M4_UM4_0_MM0_Mux32_2_Mux8_6_line1); and2 M4_UM4_0_MM0_Mux32_2_Mux8_6_Mux2(vdd, MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_6_line2); or2 M4_UM4_0_MM0_Mux32_2_Mux8_6_Mux3(M4_UM4_0_MM0_Mux32_2_Mux8_6_line1, M4_UM4_0_MM0_Mux32_2_Mux8_6_line2, M4_UM4_0_MuxOutbus_22); inv M4_UM4_0_MM0_Mux32_2_Mux8_7_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_7_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_2_Mux8_7_Mux1(in176, M4_UM4_0_MM0_Mux32_2_Mux8_7_Not_ContIn, M4_UM4_0_MM0_Mux32_2_Mux8_7_line1); and2 M4_UM4_0_MM0_Mux32_2_Mux8_7_Mux2(vdd, MuxSel, M4_UM4_0_MM0_Mux32_2_Mux8_7_line2); or2 M4_UM4_0_MM0_Mux32_2_Mux8_7_Mux3(M4_UM4_0_MM0_Mux32_2_Mux8_7_line1, M4_UM4_0_MM0_Mux32_2_Mux8_7_line2, M4_UM4_0_MuxOutbus_23); inv M4_UM4_0_MM0_Mux32_3_Mux8_0_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_0_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_3_Mux8_0_Mux1(in175, M4_UM4_0_MM0_Mux32_3_Mux8_0_Not_ContIn, M4_UM4_0_MM0_Mux32_3_Mux8_0_line1); and2 M4_UM4_0_MM0_Mux32_3_Mux8_0_Mux2(vdd, MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_0_line2); or2 M4_UM4_0_MM0_Mux32_3_Mux8_0_Mux3(M4_UM4_0_MM0_Mux32_3_Mux8_0_line1, M4_UM4_0_MM0_Mux32_3_Mux8_0_line2, M4_UM4_0_MuxOutbus_24); inv M4_UM4_0_MM0_Mux32_3_Mux8_1_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_1_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_3_Mux8_1_Mux1(in174, M4_UM4_0_MM0_Mux32_3_Mux8_1_Not_ContIn, M4_UM4_0_MM0_Mux32_3_Mux8_1_line1); and2 M4_UM4_0_MM0_Mux32_3_Mux8_1_Mux2(vdd, MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_1_line2); or2 M4_UM4_0_MM0_Mux32_3_Mux8_1_Mux3(M4_UM4_0_MM0_Mux32_3_Mux8_1_line1, M4_UM4_0_MM0_Mux32_3_Mux8_1_line2, M4_UM4_0_MuxOutbus_25); inv M4_UM4_0_MM0_Mux32_3_Mux8_2_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_2_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_3_Mux8_2_Mux1(in173, M4_UM4_0_MM0_Mux32_3_Mux8_2_Not_ContIn, M4_UM4_0_MM0_Mux32_3_Mux8_2_line1); and2 M4_UM4_0_MM0_Mux32_3_Mux8_2_Mux2(vdd, MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_2_line2); or2 M4_UM4_0_MM0_Mux32_3_Mux8_2_Mux3(M4_UM4_0_MM0_Mux32_3_Mux8_2_line1, M4_UM4_0_MM0_Mux32_3_Mux8_2_line2, M4_UM4_0_MuxOutbus_26); inv M4_UM4_0_MM0_Mux32_3_Mux8_3_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_3_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_3_Mux8_3_Mux1(vdd, M4_UM4_0_MM0_Mux32_3_Mux8_3_Not_ContIn, M4_UM4_0_MM0_Mux32_3_Mux8_3_line1); and2 M4_UM4_0_MM0_Mux32_3_Mux8_3_Mux2(vdd, MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_3_line2); or2 M4_UM4_0_MM0_Mux32_3_Mux8_3_Mux3(M4_UM4_0_MM0_Mux32_3_Mux8_3_line1, M4_UM4_0_MM0_Mux32_3_Mux8_3_line2, M4_UM4_0_MuxOutbus_27); inv M4_UM4_0_MM0_Mux32_3_Mux8_4_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_4_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_3_Mux8_4_Mux1(in169, M4_UM4_0_MM0_Mux32_3_Mux8_4_Not_ContIn, M4_UM4_0_MM0_Mux32_3_Mux8_4_line1); and2 M4_UM4_0_MM0_Mux32_3_Mux8_4_Mux2(vdd, MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_4_line2); or2 M4_UM4_0_MM0_Mux32_3_Mux8_4_Mux3(M4_UM4_0_MM0_Mux32_3_Mux8_4_line1, M4_UM4_0_MM0_Mux32_3_Mux8_4_line2, M4_UM4_0_MuxOutbus_28); inv M4_UM4_0_MM0_Mux32_3_Mux8_5_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_5_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_3_Mux8_5_Mux1(in168, M4_UM4_0_MM0_Mux32_3_Mux8_5_Not_ContIn, M4_UM4_0_MM0_Mux32_3_Mux8_5_line1); and2 M4_UM4_0_MM0_Mux32_3_Mux8_5_Mux2(vdd, MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_5_line2); or2 M4_UM4_0_MM0_Mux32_3_Mux8_5_Mux3(M4_UM4_0_MM0_Mux32_3_Mux8_5_line1, M4_UM4_0_MM0_Mux32_3_Mux8_5_line2, M4_UM4_0_MuxOutbus_29); inv M4_UM4_0_MM0_Mux32_3_Mux8_6_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_6_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_3_Mux8_6_Mux1(in167, M4_UM4_0_MM0_Mux32_3_Mux8_6_Not_ContIn, M4_UM4_0_MM0_Mux32_3_Mux8_6_line1); and2 M4_UM4_0_MM0_Mux32_3_Mux8_6_Mux2(vdd, MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_6_line2); or2 M4_UM4_0_MM0_Mux32_3_Mux8_6_Mux3(M4_UM4_0_MM0_Mux32_3_Mux8_6_line1, M4_UM4_0_MM0_Mux32_3_Mux8_6_line2, M4_UM4_0_MuxOutbus_30); inv M4_UM4_0_MM0_Mux32_3_Mux8_7_Mux0(MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_7_Not_ContIn); and2 M4_UM4_0_MM0_Mux32_3_Mux8_7_Mux1(in166, M4_UM4_0_MM0_Mux32_3_Mux8_7_Not_ContIn, M4_UM4_0_MM0_Mux32_3_Mux8_7_line1); and2 M4_UM4_0_MM0_Mux32_3_Mux8_7_Mux2(vdd, MuxSel, M4_UM4_0_MM0_Mux32_3_Mux8_7_line2); or2 M4_UM4_0_MM0_Mux32_3_Mux8_7_Mux3(M4_UM4_0_MM0_Mux32_3_Mux8_7_line1, M4_UM4_0_MM0_Mux32_3_Mux8_7_line2, M4_UM4_0_MuxOutbus_31); and2 M4_UM4_0_MM1(M4_UM4_0_MuxOutbus_22, ContBusMask, YBbus_22); and2 M4_UM4_0_MM2(M4_UM4_0_MuxOutbus_23, ContBusMask, YBbus_23); and2 M4_UM4_0_MM3(M4_UM4_0_MuxOutbus_24, ContBusMask, YBbus_24); and2 M4_UM4_0_MM4(M4_UM4_0_MuxOutbus_25, ContBusMask, YBbus_25); and2 M4_UM4_0_MM5(M4_UM4_0_MuxOutbus_26, ContBusMask, YBbus_26); and2 M4_UM4_0_MM6(M4_UM4_0_MuxOutbus_27, ContBusMask, YBbus_27); and2 M4_UM4_0_MM7(M4_UM4_0_MuxOutbus_28, ContBusMask, YBbus_28); and2 M4_UM4_0_MM8(M4_UM4_0_MuxOutbus_29, ContBusMask, YBbus_29); and2 M4_UM4_0_MM9(M4_UM4_0_MuxOutbus_30, ContBusMask, YBbus_30); and2 M4_UM4_0_MM10(M4_UM4_0_MuxOutbus_31, ContBusMask, YBbus_31); inv M4_UM4_1(in4528, M4_NotXYBext); or2 M4_UM4_2(M4_NotXYBext, in1455, YBbus_32); or2 M4_UM4_3(M4_NotXYBext, in2204, YBbus_33); and2 M5_UM5_0_GP34_0_GenProp8_0(XAbus_0, Not_XBbus_0, M5_GenXbus_0); and2 M5_UM5_0_GP34_0_GenProp8_1(XAbus_1, Not_XBbus_1, M5_GenXbus_1); and2 M5_UM5_0_GP34_0_GenProp8_2(XAbus_2, Not_XBbus_2, M5_GenXbus_2); and2 M5_UM5_0_GP34_0_GenProp8_3(XAbus_3, Not_XBbus_3, M5_GenXbus_3); and2 M5_UM5_0_GP34_0_GenProp8_4(XAbus_4, Not_XBbus_4, M5_GenXbus_4); and2 M5_UM5_0_GP34_0_GenProp8_5(XAbus_5, Not_XBbus_5, M5_GenXbus_5); and2 M5_UM5_0_GP34_0_GenProp8_6(XAbus_6, Not_XBbus_6, M5_GenXbus_6); and2 M5_UM5_0_GP34_0_GenProp8_7(XAbus_7, Not_XBbus_7, M5_GenXbus_7); inv M5_UM5_0_GP34_0_GenProp8_8_Xo0(XAbus_0, M5_UM5_0_GP34_0_GenProp8_8_NotA); inv M5_UM5_0_GP34_0_GenProp8_8_Xo1(Not_XBbus_0, M5_UM5_0_GP34_0_GenProp8_8_NotB); nand2 M5_UM5_0_GP34_0_GenProp8_8_Xo2(M5_UM5_0_GP34_0_GenProp8_8_NotA, Not_XBbus_0, M5_UM5_0_GP34_0_GenProp8_8_line2); nand2 M5_UM5_0_GP34_0_GenProp8_8_Xo3(M5_UM5_0_GP34_0_GenProp8_8_NotB, XAbus_0, M5_UM5_0_GP34_0_GenProp8_8_line3); nand2 M5_UM5_0_GP34_0_GenProp8_8_Xo4(M5_UM5_0_GP34_0_GenProp8_8_line2, M5_UM5_0_GP34_0_GenProp8_8_line3, PropXbus_0); inv M5_UM5_0_GP34_0_GenProp8_9_Xo0(XAbus_1, M5_UM5_0_GP34_0_GenProp8_9_NotA); inv M5_UM5_0_GP34_0_GenProp8_9_Xo1(Not_XBbus_1, M5_UM5_0_GP34_0_GenProp8_9_NotB); nand2 M5_UM5_0_GP34_0_GenProp8_9_Xo2(M5_UM5_0_GP34_0_GenProp8_9_NotA, Not_XBbus_1, M5_UM5_0_GP34_0_GenProp8_9_line2); nand2 M5_UM5_0_GP34_0_GenProp8_9_Xo3(M5_UM5_0_GP34_0_GenProp8_9_NotB, XAbus_1, M5_UM5_0_GP34_0_GenProp8_9_line3); nand2 M5_UM5_0_GP34_0_GenProp8_9_Xo4(M5_UM5_0_GP34_0_GenProp8_9_line2, M5_UM5_0_GP34_0_GenProp8_9_line3, PropXbus_1); inv M5_UM5_0_GP34_0_GenProp8_10_Xo0(XAbus_2, M5_UM5_0_GP34_0_GenProp8_10_NotA); inv M5_UM5_0_GP34_0_GenProp8_10_Xo1(Not_XBbus_2, M5_UM5_0_GP34_0_GenProp8_10_NotB); nand2 M5_UM5_0_GP34_0_GenProp8_10_Xo2(M5_UM5_0_GP34_0_GenProp8_10_NotA, Not_XBbus_2, M5_UM5_0_GP34_0_GenProp8_10_line2); nand2 M5_UM5_0_GP34_0_GenProp8_10_Xo3(M5_UM5_0_GP34_0_GenProp8_10_NotB, XAbus_2, M5_UM5_0_GP34_0_GenProp8_10_line3); nand2 M5_UM5_0_GP34_0_GenProp8_10_Xo4(M5_UM5_0_GP34_0_GenProp8_10_line2, M5_UM5_0_GP34_0_GenProp8_10_line3, PropXbus_2); inv M5_UM5_0_GP34_0_GenProp8_11_Xo0(XAbus_3, M5_UM5_0_GP34_0_GenProp8_11_NotA); inv M5_UM5_0_GP34_0_GenProp8_11_Xo1(Not_XBbus_3, M5_UM5_0_GP34_0_GenProp8_11_NotB); nand2 M5_UM5_0_GP34_0_GenProp8_11_Xo2(M5_UM5_0_GP34_0_GenProp8_11_NotA, Not_XBbus_3, M5_UM5_0_GP34_0_GenProp8_11_line2); nand2 M5_UM5_0_GP34_0_GenProp8_11_Xo3(M5_UM5_0_GP34_0_GenProp8_11_NotB, XAbus_3, M5_UM5_0_GP34_0_GenProp8_11_line3); nand2 M5_UM5_0_GP34_0_GenProp8_11_Xo4(M5_UM5_0_GP34_0_GenProp8_11_line2, M5_UM5_0_GP34_0_GenProp8_11_line3, PropXbus_3); inv M5_UM5_0_GP34_0_GenProp8_12_Xo0(XAbus_4, M5_UM5_0_GP34_0_GenProp8_12_NotA); inv M5_UM5_0_GP34_0_GenProp8_12_Xo1(Not_XBbus_4, M5_UM5_0_GP34_0_GenProp8_12_NotB); nand2 M5_UM5_0_GP34_0_GenProp8_12_Xo2(M5_UM5_0_GP34_0_GenProp8_12_NotA, Not_XBbus_4, M5_UM5_0_GP34_0_GenProp8_12_line2); nand2 M5_UM5_0_GP34_0_GenProp8_12_Xo3(M5_UM5_0_GP34_0_GenProp8_12_NotB, XAbus_4, M5_UM5_0_GP34_0_GenProp8_12_line3); nand2 M5_UM5_0_GP34_0_GenProp8_12_Xo4(M5_UM5_0_GP34_0_GenProp8_12_line2, M5_UM5_0_GP34_0_GenProp8_12_line3, PropXbus_4); inv M5_UM5_0_GP34_0_GenProp8_13_Xo0(XAbus_5, M5_UM5_0_GP34_0_GenProp8_13_NotA); inv M5_UM5_0_GP34_0_GenProp8_13_Xo1(Not_XBbus_5, M5_UM5_0_GP34_0_GenProp8_13_NotB); nand2 M5_UM5_0_GP34_0_GenProp8_13_Xo2(M5_UM5_0_GP34_0_GenProp8_13_NotA, Not_XBbus_5, M5_UM5_0_GP34_0_GenProp8_13_line2); nand2 M5_UM5_0_GP34_0_GenProp8_13_Xo3(M5_UM5_0_GP34_0_GenProp8_13_NotB, XAbus_5, M5_UM5_0_GP34_0_GenProp8_13_line3); nand2 M5_UM5_0_GP34_0_GenProp8_13_Xo4(M5_UM5_0_GP34_0_GenProp8_13_line2, M5_UM5_0_GP34_0_GenProp8_13_line3, PropXbus_5); inv M5_UM5_0_GP34_0_GenProp8_14_Xo0(XAbus_6, M5_UM5_0_GP34_0_GenProp8_14_NotA); inv M5_UM5_0_GP34_0_GenProp8_14_Xo1(Not_XBbus_6, M5_UM5_0_GP34_0_GenProp8_14_NotB); nand2 M5_UM5_0_GP34_0_GenProp8_14_Xo2(M5_UM5_0_GP34_0_GenProp8_14_NotA, Not_XBbus_6, M5_UM5_0_GP34_0_GenProp8_14_line2); nand2 M5_UM5_0_GP34_0_GenProp8_14_Xo3(M5_UM5_0_GP34_0_GenProp8_14_NotB, XAbus_6, M5_UM5_0_GP34_0_GenProp8_14_line3); nand2 M5_UM5_0_GP34_0_GenProp8_14_Xo4(M5_UM5_0_GP34_0_GenProp8_14_line2, M5_UM5_0_GP34_0_GenProp8_14_line3, PropXbus_6); inv M5_UM5_0_GP34_0_GenProp8_15_Xo0(XAbus_7, M5_UM5_0_GP34_0_GenProp8_15_NotA); inv M5_UM5_0_GP34_0_GenProp8_15_Xo1(Not_XBbus_7, M5_UM5_0_GP34_0_GenProp8_15_NotB); nand2 M5_UM5_0_GP34_0_GenProp8_15_Xo2(M5_UM5_0_GP34_0_GenProp8_15_NotA, Not_XBbus_7, M5_UM5_0_GP34_0_GenProp8_15_line2); nand2 M5_UM5_0_GP34_0_GenProp8_15_Xo3(M5_UM5_0_GP34_0_GenProp8_15_NotB, XAbus_7, M5_UM5_0_GP34_0_GenProp8_15_line3); nand2 M5_UM5_0_GP34_0_GenProp8_15_Xo4(M5_UM5_0_GP34_0_GenProp8_15_line2, M5_UM5_0_GP34_0_GenProp8_15_line3, PropXbus_7); and2 M5_UM5_0_GP34_1_GenProp8_0(XAbus_8, Not_XBbus_8, M5_GenXbus_8); and2 M5_UM5_0_GP34_1_GenProp8_1(XAbus_9, Not_XBbus_9, M5_GenXbus_9); and2 M5_UM5_0_GP34_1_GenProp8_2(XAbus_10, Not_XBbus_10, M5_GenXbus_10); and2 M5_UM5_0_GP34_1_GenProp8_3(XAbus_11, Not_XBbus_11, M5_GenXbus_11); and2 M5_UM5_0_GP34_1_GenProp8_4(XAbus_12, Not_XBbus_12, M5_GenXbus_12); and2 M5_UM5_0_GP34_1_GenProp8_5(XAbus_13, Not_XBbus_13, M5_GenXbus_13); and2 M5_UM5_0_GP34_1_GenProp8_6(XAbus_14, Not_XBbus_14, M5_GenXbus_14); and2 M5_UM5_0_GP34_1_GenProp8_7(XAbus_15, Not_XBbus_15, M5_GenXbus_15); inv M5_UM5_0_GP34_1_GenProp8_8_Xo0(XAbus_8, M5_UM5_0_GP34_1_GenProp8_8_NotA); inv M5_UM5_0_GP34_1_GenProp8_8_Xo1(Not_XBbus_8, M5_UM5_0_GP34_1_GenProp8_8_NotB); nand2 M5_UM5_0_GP34_1_GenProp8_8_Xo2(M5_UM5_0_GP34_1_GenProp8_8_NotA, Not_XBbus_8, M5_UM5_0_GP34_1_GenProp8_8_line2); nand2 M5_UM5_0_GP34_1_GenProp8_8_Xo3(M5_UM5_0_GP34_1_GenProp8_8_NotB, XAbus_8, M5_UM5_0_GP34_1_GenProp8_8_line3); nand2 M5_UM5_0_GP34_1_GenProp8_8_Xo4(M5_UM5_0_GP34_1_GenProp8_8_line2, M5_UM5_0_GP34_1_GenProp8_8_line3, PropXbus_8); inv M5_UM5_0_GP34_1_GenProp8_9_Xo0(XAbus_9, M5_UM5_0_GP34_1_GenProp8_9_NotA); inv M5_UM5_0_GP34_1_GenProp8_9_Xo1(Not_XBbus_9, M5_UM5_0_GP34_1_GenProp8_9_NotB); nand2 M5_UM5_0_GP34_1_GenProp8_9_Xo2(M5_UM5_0_GP34_1_GenProp8_9_NotA, Not_XBbus_9, M5_UM5_0_GP34_1_GenProp8_9_line2); nand2 M5_UM5_0_GP34_1_GenProp8_9_Xo3(M5_UM5_0_GP34_1_GenProp8_9_NotB, XAbus_9, M5_UM5_0_GP34_1_GenProp8_9_line3); nand2 M5_UM5_0_GP34_1_GenProp8_9_Xo4(M5_UM5_0_GP34_1_GenProp8_9_line2, M5_UM5_0_GP34_1_GenProp8_9_line3, PropXbus_9); inv M5_UM5_0_GP34_1_GenProp8_10_Xo0(XAbus_10, M5_UM5_0_GP34_1_GenProp8_10_NotA); inv M5_UM5_0_GP34_1_GenProp8_10_Xo1(Not_XBbus_10, M5_UM5_0_GP34_1_GenProp8_10_NotB); nand2 M5_UM5_0_GP34_1_GenProp8_10_Xo2(M5_UM5_0_GP34_1_GenProp8_10_NotA, Not_XBbus_10, M5_UM5_0_GP34_1_GenProp8_10_line2); nand2 M5_UM5_0_GP34_1_GenProp8_10_Xo3(M5_UM5_0_GP34_1_GenProp8_10_NotB, XAbus_10, M5_UM5_0_GP34_1_GenProp8_10_line3); nand2 M5_UM5_0_GP34_1_GenProp8_10_Xo4(M5_UM5_0_GP34_1_GenProp8_10_line2, M5_UM5_0_GP34_1_GenProp8_10_line3, PropXbus_10); inv M5_UM5_0_GP34_1_GenProp8_11_Xo0(XAbus_11, M5_UM5_0_GP34_1_GenProp8_11_NotA); inv M5_UM5_0_GP34_1_GenProp8_11_Xo1(Not_XBbus_11, M5_UM5_0_GP34_1_GenProp8_11_NotB); nand2 M5_UM5_0_GP34_1_GenProp8_11_Xo2(M5_UM5_0_GP34_1_GenProp8_11_NotA, Not_XBbus_11, M5_UM5_0_GP34_1_GenProp8_11_line2); nand2 M5_UM5_0_GP34_1_GenProp8_11_Xo3(M5_UM5_0_GP34_1_GenProp8_11_NotB, XAbus_11, M5_UM5_0_GP34_1_GenProp8_11_line3); nand2 M5_UM5_0_GP34_1_GenProp8_11_Xo4(M5_UM5_0_GP34_1_GenProp8_11_line2, M5_UM5_0_GP34_1_GenProp8_11_line3, PropXbus_11); inv M5_UM5_0_GP34_1_GenProp8_12_Xo0(XAbus_12, M5_UM5_0_GP34_1_GenProp8_12_NotA); inv M5_UM5_0_GP34_1_GenProp8_12_Xo1(Not_XBbus_12, M5_UM5_0_GP34_1_GenProp8_12_NotB); nand2 M5_UM5_0_GP34_1_GenProp8_12_Xo2(M5_UM5_0_GP34_1_GenProp8_12_NotA, Not_XBbus_12, M5_UM5_0_GP34_1_GenProp8_12_line2); nand2 M5_UM5_0_GP34_1_GenProp8_12_Xo3(M5_UM5_0_GP34_1_GenProp8_12_NotB, XAbus_12, M5_UM5_0_GP34_1_GenProp8_12_line3); nand2 M5_UM5_0_GP34_1_GenProp8_12_Xo4(M5_UM5_0_GP34_1_GenProp8_12_line2, M5_UM5_0_GP34_1_GenProp8_12_line3, PropXbus_12); inv M5_UM5_0_GP34_1_GenProp8_13_Xo0(XAbus_13, M5_UM5_0_GP34_1_GenProp8_13_NotA); inv M5_UM5_0_GP34_1_GenProp8_13_Xo1(Not_XBbus_13, M5_UM5_0_GP34_1_GenProp8_13_NotB); nand2 M5_UM5_0_GP34_1_GenProp8_13_Xo2(M5_UM5_0_GP34_1_GenProp8_13_NotA, Not_XBbus_13, M5_UM5_0_GP34_1_GenProp8_13_line2); nand2 M5_UM5_0_GP34_1_GenProp8_13_Xo3(M5_UM5_0_GP34_1_GenProp8_13_NotB, XAbus_13, M5_UM5_0_GP34_1_GenProp8_13_line3); nand2 M5_UM5_0_GP34_1_GenProp8_13_Xo4(M5_UM5_0_GP34_1_GenProp8_13_line2, M5_UM5_0_GP34_1_GenProp8_13_line3, PropXbus_13); inv M5_UM5_0_GP34_1_GenProp8_14_Xo0(XAbus_14, M5_UM5_0_GP34_1_GenProp8_14_NotA); inv M5_UM5_0_GP34_1_GenProp8_14_Xo1(Not_XBbus_14, M5_UM5_0_GP34_1_GenProp8_14_NotB); nand2 M5_UM5_0_GP34_1_GenProp8_14_Xo2(M5_UM5_0_GP34_1_GenProp8_14_NotA, Not_XBbus_14, M5_UM5_0_GP34_1_GenProp8_14_line2); nand2 M5_UM5_0_GP34_1_GenProp8_14_Xo3(M5_UM5_0_GP34_1_GenProp8_14_NotB, XAbus_14, M5_UM5_0_GP34_1_GenProp8_14_line3); nand2 M5_UM5_0_GP34_1_GenProp8_14_Xo4(M5_UM5_0_GP34_1_GenProp8_14_line2, M5_UM5_0_GP34_1_GenProp8_14_line3, PropXbus_14); inv M5_UM5_0_GP34_1_GenProp8_15_Xo0(XAbus_15, M5_UM5_0_GP34_1_GenProp8_15_NotA); inv M5_UM5_0_GP34_1_GenProp8_15_Xo1(Not_XBbus_15, M5_UM5_0_GP34_1_GenProp8_15_NotB); nand2 M5_UM5_0_GP34_1_GenProp8_15_Xo2(M5_UM5_0_GP34_1_GenProp8_15_NotA, Not_XBbus_15, M5_UM5_0_GP34_1_GenProp8_15_line2); nand2 M5_UM5_0_GP34_1_GenProp8_15_Xo3(M5_UM5_0_GP34_1_GenProp8_15_NotB, XAbus_15, M5_UM5_0_GP34_1_GenProp8_15_line3); nand2 M5_UM5_0_GP34_1_GenProp8_15_Xo4(M5_UM5_0_GP34_1_GenProp8_15_line2, M5_UM5_0_GP34_1_GenProp8_15_line3, PropXbus_15); and2 M5_UM5_0_GP34_2_GenProp8_0(XAbus_16, Not_XBbus_16, M5_GenXbus_16); and2 M5_UM5_0_GP34_2_GenProp8_1(XAbus_17, Not_XBbus_17, M5_GenXbus_17); and2 M5_UM5_0_GP34_2_GenProp8_2(XAbus_18, Not_XBbus_18, M5_GenXbus_18); and2 M5_UM5_0_GP34_2_GenProp8_3(XAbus_19, Not_XBbus_19, M5_GenXbus_19); and2 M5_UM5_0_GP34_2_GenProp8_4(XAbus_20, Not_XBbus_20, M5_GenXbus_20); and2 M5_UM5_0_GP34_2_GenProp8_5(XAbus_21, Not_XBbus_21, M5_GenXbus_21); and2 M5_UM5_0_GP34_2_GenProp8_6(XAbus_22, Not_XBbus_22, M5_GenXbus_22); and2 M5_UM5_0_GP34_2_GenProp8_7(XAbus_23, Not_XBbus_23, M5_GenXbus_23); inv M5_UM5_0_GP34_2_GenProp8_8_Xo0(XAbus_16, M5_UM5_0_GP34_2_GenProp8_8_NotA); inv M5_UM5_0_GP34_2_GenProp8_8_Xo1(Not_XBbus_16, M5_UM5_0_GP34_2_GenProp8_8_NotB); nand2 M5_UM5_0_GP34_2_GenProp8_8_Xo2(M5_UM5_0_GP34_2_GenProp8_8_NotA, Not_XBbus_16, M5_UM5_0_GP34_2_GenProp8_8_line2); nand2 M5_UM5_0_GP34_2_GenProp8_8_Xo3(M5_UM5_0_GP34_2_GenProp8_8_NotB, XAbus_16, M5_UM5_0_GP34_2_GenProp8_8_line3); nand2 M5_UM5_0_GP34_2_GenProp8_8_Xo4(M5_UM5_0_GP34_2_GenProp8_8_line2, M5_UM5_0_GP34_2_GenProp8_8_line3, PropXbus_16); inv M5_UM5_0_GP34_2_GenProp8_9_Xo0(XAbus_17, M5_UM5_0_GP34_2_GenProp8_9_NotA); inv M5_UM5_0_GP34_2_GenProp8_9_Xo1(Not_XBbus_17, M5_UM5_0_GP34_2_GenProp8_9_NotB); nand2 M5_UM5_0_GP34_2_GenProp8_9_Xo2(M5_UM5_0_GP34_2_GenProp8_9_NotA, Not_XBbus_17, M5_UM5_0_GP34_2_GenProp8_9_line2); nand2 M5_UM5_0_GP34_2_GenProp8_9_Xo3(M5_UM5_0_GP34_2_GenProp8_9_NotB, XAbus_17, M5_UM5_0_GP34_2_GenProp8_9_line3); nand2 M5_UM5_0_GP34_2_GenProp8_9_Xo4(M5_UM5_0_GP34_2_GenProp8_9_line2, M5_UM5_0_GP34_2_GenProp8_9_line3, PropXbus_17); inv M5_UM5_0_GP34_2_GenProp8_10_Xo0(XAbus_18, M5_UM5_0_GP34_2_GenProp8_10_NotA); inv M5_UM5_0_GP34_2_GenProp8_10_Xo1(Not_XBbus_18, M5_UM5_0_GP34_2_GenProp8_10_NotB); nand2 M5_UM5_0_GP34_2_GenProp8_10_Xo2(M5_UM5_0_GP34_2_GenProp8_10_NotA, Not_XBbus_18, M5_UM5_0_GP34_2_GenProp8_10_line2); nand2 M5_UM5_0_GP34_2_GenProp8_10_Xo3(M5_UM5_0_GP34_2_GenProp8_10_NotB, XAbus_18, M5_UM5_0_GP34_2_GenProp8_10_line3); nand2 M5_UM5_0_GP34_2_GenProp8_10_Xo4(M5_UM5_0_GP34_2_GenProp8_10_line2, M5_UM5_0_GP34_2_GenProp8_10_line3, PropXbus_18); inv M5_UM5_0_GP34_2_GenProp8_11_Xo0(XAbus_19, M5_UM5_0_GP34_2_GenProp8_11_NotA); inv M5_UM5_0_GP34_2_GenProp8_11_Xo1(Not_XBbus_19, M5_UM5_0_GP34_2_GenProp8_11_NotB); nand2 M5_UM5_0_GP34_2_GenProp8_11_Xo2(M5_UM5_0_GP34_2_GenProp8_11_NotA, Not_XBbus_19, M5_UM5_0_GP34_2_GenProp8_11_line2); nand2 M5_UM5_0_GP34_2_GenProp8_11_Xo3(M5_UM5_0_GP34_2_GenProp8_11_NotB, XAbus_19, M5_UM5_0_GP34_2_GenProp8_11_line3); nand2 M5_UM5_0_GP34_2_GenProp8_11_Xo4(M5_UM5_0_GP34_2_GenProp8_11_line2, M5_UM5_0_GP34_2_GenProp8_11_line3, PropXbus_19); inv M5_UM5_0_GP34_2_GenProp8_12_Xo0(XAbus_20, M5_UM5_0_GP34_2_GenProp8_12_NotA); inv M5_UM5_0_GP34_2_GenProp8_12_Xo1(Not_XBbus_20, M5_UM5_0_GP34_2_GenProp8_12_NotB); nand2 M5_UM5_0_GP34_2_GenProp8_12_Xo2(M5_UM5_0_GP34_2_GenProp8_12_NotA, Not_XBbus_20, M5_UM5_0_GP34_2_GenProp8_12_line2); nand2 M5_UM5_0_GP34_2_GenProp8_12_Xo3(M5_UM5_0_GP34_2_GenProp8_12_NotB, XAbus_20, M5_UM5_0_GP34_2_GenProp8_12_line3); nand2 M5_UM5_0_GP34_2_GenProp8_12_Xo4(M5_UM5_0_GP34_2_GenProp8_12_line2, M5_UM5_0_GP34_2_GenProp8_12_line3, PropXbus_20); inv M5_UM5_0_GP34_2_GenProp8_13_Xo0(XAbus_21, M5_UM5_0_GP34_2_GenProp8_13_NotA); inv M5_UM5_0_GP34_2_GenProp8_13_Xo1(Not_XBbus_21, M5_UM5_0_GP34_2_GenProp8_13_NotB); nand2 M5_UM5_0_GP34_2_GenProp8_13_Xo2(M5_UM5_0_GP34_2_GenProp8_13_NotA, Not_XBbus_21, M5_UM5_0_GP34_2_GenProp8_13_line2); nand2 M5_UM5_0_GP34_2_GenProp8_13_Xo3(M5_UM5_0_GP34_2_GenProp8_13_NotB, XAbus_21, M5_UM5_0_GP34_2_GenProp8_13_line3); nand2 M5_UM5_0_GP34_2_GenProp8_13_Xo4(M5_UM5_0_GP34_2_GenProp8_13_line2, M5_UM5_0_GP34_2_GenProp8_13_line3, PropXbus_21); inv M5_UM5_0_GP34_2_GenProp8_14_Xo0(XAbus_22, M5_UM5_0_GP34_2_GenProp8_14_NotA); inv M5_UM5_0_GP34_2_GenProp8_14_Xo1(Not_XBbus_22, M5_UM5_0_GP34_2_GenProp8_14_NotB); nand2 M5_UM5_0_GP34_2_GenProp8_14_Xo2(M5_UM5_0_GP34_2_GenProp8_14_NotA, Not_XBbus_22, M5_UM5_0_GP34_2_GenProp8_14_line2); nand2 M5_UM5_0_GP34_2_GenProp8_14_Xo3(M5_UM5_0_GP34_2_GenProp8_14_NotB, XAbus_22, M5_UM5_0_GP34_2_GenProp8_14_line3); nand2 M5_UM5_0_GP34_2_GenProp8_14_Xo4(M5_UM5_0_GP34_2_GenProp8_14_line2, M5_UM5_0_GP34_2_GenProp8_14_line3, PropXbus_22); inv M5_UM5_0_GP34_2_GenProp8_15_Xo0(XAbus_23, M5_UM5_0_GP34_2_GenProp8_15_NotA); inv M5_UM5_0_GP34_2_GenProp8_15_Xo1(Not_XBbus_23, M5_UM5_0_GP34_2_GenProp8_15_NotB); nand2 M5_UM5_0_GP34_2_GenProp8_15_Xo2(M5_UM5_0_GP34_2_GenProp8_15_NotA, Not_XBbus_23, M5_UM5_0_GP34_2_GenProp8_15_line2); nand2 M5_UM5_0_GP34_2_GenProp8_15_Xo3(M5_UM5_0_GP34_2_GenProp8_15_NotB, XAbus_23, M5_UM5_0_GP34_2_GenProp8_15_line3); nand2 M5_UM5_0_GP34_2_GenProp8_15_Xo4(M5_UM5_0_GP34_2_GenProp8_15_line2, M5_UM5_0_GP34_2_GenProp8_15_line3, PropXbus_23); and2 M5_UM5_0_GP34_3_GenProp8_0(XAbus_24, Not_XBbus_24, M5_GenXbus_24); and2 M5_UM5_0_GP34_3_GenProp8_1(XAbus_25, Not_XBbus_25, M5_GenXbus_25); and2 M5_UM5_0_GP34_3_GenProp8_2(XAbus_26, Not_XBbus_26, M5_GenXbus_26); and2 M5_UM5_0_GP34_3_GenProp8_3(XAbus_27, Not_XBbus_27, M5_GenXbus_27); and2 M5_UM5_0_GP34_3_GenProp8_4(XAbus_28, Not_XBbus_28, M5_GenXbus_28); and2 M5_UM5_0_GP34_3_GenProp8_5(XAbus_29, Not_XBbus_29, M5_GenXbus_29); and2 M5_UM5_0_GP34_3_GenProp8_6(XAbus_30, Not_XBbus_30, M5_GenXbus_30); and2 M5_UM5_0_GP34_3_GenProp8_7(XAbus_31, Not_XBbus_31, M5_GenXbus_31); inv M5_UM5_0_GP34_3_GenProp8_8_Xo0(XAbus_24, M5_UM5_0_GP34_3_GenProp8_8_NotA); inv M5_UM5_0_GP34_3_GenProp8_8_Xo1(Not_XBbus_24, M5_UM5_0_GP34_3_GenProp8_8_NotB); nand2 M5_UM5_0_GP34_3_GenProp8_8_Xo2(M5_UM5_0_GP34_3_GenProp8_8_NotA, Not_XBbus_24, M5_UM5_0_GP34_3_GenProp8_8_line2); nand2 M5_UM5_0_GP34_3_GenProp8_8_Xo3(M5_UM5_0_GP34_3_GenProp8_8_NotB, XAbus_24, M5_UM5_0_GP34_3_GenProp8_8_line3); nand2 M5_UM5_0_GP34_3_GenProp8_8_Xo4(M5_UM5_0_GP34_3_GenProp8_8_line2, M5_UM5_0_GP34_3_GenProp8_8_line3, PropXbus_24); inv M5_UM5_0_GP34_3_GenProp8_9_Xo0(XAbus_25, M5_UM5_0_GP34_3_GenProp8_9_NotA); inv M5_UM5_0_GP34_3_GenProp8_9_Xo1(Not_XBbus_25, M5_UM5_0_GP34_3_GenProp8_9_NotB); nand2 M5_UM5_0_GP34_3_GenProp8_9_Xo2(M5_UM5_0_GP34_3_GenProp8_9_NotA, Not_XBbus_25, M5_UM5_0_GP34_3_GenProp8_9_line2); nand2 M5_UM5_0_GP34_3_GenProp8_9_Xo3(M5_UM5_0_GP34_3_GenProp8_9_NotB, XAbus_25, M5_UM5_0_GP34_3_GenProp8_9_line3); nand2 M5_UM5_0_GP34_3_GenProp8_9_Xo4(M5_UM5_0_GP34_3_GenProp8_9_line2, M5_UM5_0_GP34_3_GenProp8_9_line3, PropXbus_25); inv M5_UM5_0_GP34_3_GenProp8_10_Xo0(XAbus_26, M5_UM5_0_GP34_3_GenProp8_10_NotA); inv M5_UM5_0_GP34_3_GenProp8_10_Xo1(Not_XBbus_26, M5_UM5_0_GP34_3_GenProp8_10_NotB); nand2 M5_UM5_0_GP34_3_GenProp8_10_Xo2(M5_UM5_0_GP34_3_GenProp8_10_NotA, Not_XBbus_26, M5_UM5_0_GP34_3_GenProp8_10_line2); nand2 M5_UM5_0_GP34_3_GenProp8_10_Xo3(M5_UM5_0_GP34_3_GenProp8_10_NotB, XAbus_26, M5_UM5_0_GP34_3_GenProp8_10_line3); nand2 M5_UM5_0_GP34_3_GenProp8_10_Xo4(M5_UM5_0_GP34_3_GenProp8_10_line2, M5_UM5_0_GP34_3_GenProp8_10_line3, PropXbus_26); inv M5_UM5_0_GP34_3_GenProp8_11_Xo0(XAbus_27, M5_UM5_0_GP34_3_GenProp8_11_NotA); inv M5_UM5_0_GP34_3_GenProp8_11_Xo1(Not_XBbus_27, M5_UM5_0_GP34_3_GenProp8_11_NotB); nand2 M5_UM5_0_GP34_3_GenProp8_11_Xo2(M5_UM5_0_GP34_3_GenProp8_11_NotA, Not_XBbus_27, M5_UM5_0_GP34_3_GenProp8_11_line2); nand2 M5_UM5_0_GP34_3_GenProp8_11_Xo3(M5_UM5_0_GP34_3_GenProp8_11_NotB, XAbus_27, M5_UM5_0_GP34_3_GenProp8_11_line3); nand2 M5_UM5_0_GP34_3_GenProp8_11_Xo4(M5_UM5_0_GP34_3_GenProp8_11_line2, M5_UM5_0_GP34_3_GenProp8_11_line3, PropXbus_27); inv M5_UM5_0_GP34_3_GenProp8_12_Xo0(XAbus_28, M5_UM5_0_GP34_3_GenProp8_12_NotA); inv M5_UM5_0_GP34_3_GenProp8_12_Xo1(Not_XBbus_28, M5_UM5_0_GP34_3_GenProp8_12_NotB); nand2 M5_UM5_0_GP34_3_GenProp8_12_Xo2(M5_UM5_0_GP34_3_GenProp8_12_NotA, Not_XBbus_28, M5_UM5_0_GP34_3_GenProp8_12_line2); nand2 M5_UM5_0_GP34_3_GenProp8_12_Xo3(M5_UM5_0_GP34_3_GenProp8_12_NotB, XAbus_28, M5_UM5_0_GP34_3_GenProp8_12_line3); nand2 M5_UM5_0_GP34_3_GenProp8_12_Xo4(M5_UM5_0_GP34_3_GenProp8_12_line2, M5_UM5_0_GP34_3_GenProp8_12_line3, PropXbus_28); inv M5_UM5_0_GP34_3_GenProp8_13_Xo0(XAbus_29, M5_UM5_0_GP34_3_GenProp8_13_NotA); inv M5_UM5_0_GP34_3_GenProp8_13_Xo1(Not_XBbus_29, M5_UM5_0_GP34_3_GenProp8_13_NotB); nand2 M5_UM5_0_GP34_3_GenProp8_13_Xo2(M5_UM5_0_GP34_3_GenProp8_13_NotA, Not_XBbus_29, M5_UM5_0_GP34_3_GenProp8_13_line2); nand2 M5_UM5_0_GP34_3_GenProp8_13_Xo3(M5_UM5_0_GP34_3_GenProp8_13_NotB, XAbus_29, M5_UM5_0_GP34_3_GenProp8_13_line3); nand2 M5_UM5_0_GP34_3_GenProp8_13_Xo4(M5_UM5_0_GP34_3_GenProp8_13_line2, M5_UM5_0_GP34_3_GenProp8_13_line3, PropXbus_29); inv M5_UM5_0_GP34_3_GenProp8_14_Xo0(XAbus_30, M5_UM5_0_GP34_3_GenProp8_14_NotA); inv M5_UM5_0_GP34_3_GenProp8_14_Xo1(Not_XBbus_30, M5_UM5_0_GP34_3_GenProp8_14_NotB); nand2 M5_UM5_0_GP34_3_GenProp8_14_Xo2(M5_UM5_0_GP34_3_GenProp8_14_NotA, Not_XBbus_30, M5_UM5_0_GP34_3_GenProp8_14_line2); nand2 M5_UM5_0_GP34_3_GenProp8_14_Xo3(M5_UM5_0_GP34_3_GenProp8_14_NotB, XAbus_30, M5_UM5_0_GP34_3_GenProp8_14_line3); nand2 M5_UM5_0_GP34_3_GenProp8_14_Xo4(M5_UM5_0_GP34_3_GenProp8_14_line2, M5_UM5_0_GP34_3_GenProp8_14_line3, PropXbus_30); inv M5_UM5_0_GP34_3_GenProp8_15_Xo0(XAbus_31, M5_UM5_0_GP34_3_GenProp8_15_NotA); inv M5_UM5_0_GP34_3_GenProp8_15_Xo1(Not_XBbus_31, M5_UM5_0_GP34_3_GenProp8_15_NotB); nand2 M5_UM5_0_GP34_3_GenProp8_15_Xo2(M5_UM5_0_GP34_3_GenProp8_15_NotA, Not_XBbus_31, M5_UM5_0_GP34_3_GenProp8_15_line2); nand2 M5_UM5_0_GP34_3_GenProp8_15_Xo3(M5_UM5_0_GP34_3_GenProp8_15_NotB, XAbus_31, M5_UM5_0_GP34_3_GenProp8_15_line3); nand2 M5_UM5_0_GP34_3_GenProp8_15_Xo4(M5_UM5_0_GP34_3_GenProp8_15_line2, M5_UM5_0_GP34_3_GenProp8_15_line3, PropXbus_31); and2 M5_UM5_0_GP34_4(in38, Not_XBbus_32, M5_GenXbus_32); and2 M5_UM5_0_GP34_5(in38, Not_XBbus_33, M5_GenXbus_33); inv M5_UM5_0_GP34_6_Xo0(in38, M5_UM5_0_GP34_6_NotA); inv M5_UM5_0_GP34_6_Xo1(Not_XBbus_32, M5_UM5_0_GP34_6_NotB); nand2 M5_UM5_0_GP34_6_Xo2(M5_UM5_0_GP34_6_NotA, Not_XBbus_32, M5_UM5_0_GP34_6_line2); nand2 M5_UM5_0_GP34_6_Xo3(M5_UM5_0_GP34_6_NotB, in38, M5_UM5_0_GP34_6_line3); nand2 M5_UM5_0_GP34_6_Xo4(M5_UM5_0_GP34_6_line2, M5_UM5_0_GP34_6_line3, PropXbus_32); inv M5_UM5_0_GP34_7_Xo0(in38, M5_UM5_0_GP34_7_NotA); inv M5_UM5_0_GP34_7_Xo1(Not_XBbus_33, M5_UM5_0_GP34_7_NotB); nand2 M5_UM5_0_GP34_7_Xo2(M5_UM5_0_GP34_7_NotA, Not_XBbus_33, M5_UM5_0_GP34_7_line2); nand2 M5_UM5_0_GP34_7_Xo3(M5_UM5_0_GP34_7_NotB, in38, M5_UM5_0_GP34_7_line3); nand2 M5_UM5_0_GP34_7_Xo4(M5_UM5_0_GP34_7_line2, M5_UM5_0_GP34_7_line3, PropXbus_33); or2 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_0(M5_GenXbus_0, PropXbus_0, LocalCarryXCin1_0); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_1_Ao2_0(PropXbus_1, M5_GenXbus_0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_1_line0); or2 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_1_Ao2_1(M5_GenXbus_1, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_1_line0, LocalCarryXCin0_1); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_Ao3a_0(PropXbus_1, M5_GenXbus_0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_line0); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_Ao3a_1(PropXbus_1, PropXbus_0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_line1); or3 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_Ao3a_2(M5_GenXbus_1, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_line0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_line1, LocalCarryXCin1_1); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_Ao3a_0(PropXbus_2, M5_GenXbus_1, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_line0); and3 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_Ao3a_1(PropXbus_2, PropXbus_1, M5_GenXbus_0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_line1); or3 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_Ao3a_2(M5_GenXbus_2, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_line0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_line1, LocalCarryXCin0_2); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_Ao4a_0(PropXbus_2, M5_GenXbus_1, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_line0); and3 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_Ao4a_1(PropXbus_2, PropXbus_1, M5_GenXbus_0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_line1); and3 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_Ao4a_2(PropXbus_2, PropXbus_1, PropXbus_0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_line2); or4 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_Ao4a_3(M5_GenXbus_2, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_line0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_line1, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_line2, LocalCarryXCin1_2); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_Ao4a_0(PropXbus_3, M5_GenXbus_2, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_line0); and3 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_Ao4a_1(PropXbus_3, PropXbus_2, M5_GenXbus_1, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_line1); and4 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_Ao4a_2(PropXbus_3, PropXbus_2, PropXbus_1, M5_GenXbus_0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_line2); or4 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_Ao4a_3(M5_GenXbus_3, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_line0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_line1, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_line2, LocalCarryXCin0_3); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_Ao5a_0(PropXbus_3, M5_GenXbus_2, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line0); and3 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_Ao5a_1(PropXbus_3, PropXbus_2, M5_GenXbus_1, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line1); and4 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_Ao5a_2(PropXbus_3, PropXbus_2, PropXbus_1, M5_GenXbus_0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line2); and4 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_Ao5a_3(PropXbus_3, PropXbus_2, PropXbus_1, PropXbus_0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line3); or5 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_Ao5a_4(M5_GenXbus_3, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line1, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line2, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line3, LocalCarryXCin1_3); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_1_Ao5a_0(PropXbus_4, M5_GenXbus_3, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line0); and3 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_1_Ao5a_1(PropXbus_4, PropXbus_3, M5_GenXbus_2, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line1); and4 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_1_Ao5a_2(PropXbus_4, PropXbus_3, PropXbus_2, M5_GenXbus_1, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line2); and5 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_1_Ao5a_3(PropXbus_4, PropXbus_3, PropXbus_2, PropXbus_1, M5_GenXbus_0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line3); or5 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_1_Ao5a_4(M5_GenXbus_4, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line1, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line2, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line3, LocalCarryXCin0_4); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_Ao6a_0(PropXbus_4, M5_GenXbus_3, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line0); and3 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_Ao6a_1(PropXbus_4, PropXbus_3, M5_GenXbus_2, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line1); and4 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_Ao6a_2(PropXbus_4, PropXbus_3, PropXbus_2, M5_GenXbus_1, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line2); and5 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_Ao6a_3(PropXbus_4, PropXbus_3, PropXbus_2, PropXbus_1, M5_GenXbus_0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line3); and5 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_Ao6a_4(PropXbus_4, PropXbus_3, PropXbus_2, PropXbus_1, PropXbus_0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line4); or6 M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_Ao6a_5(M5_GenXbus_4, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line0, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line1, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line2, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line3, M5_UM5_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line4, LocalCarryXCin1_4); or2 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_0(M5_GenXbus_5, PropXbus_5, LocalCarryXCin1_5); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_1_Ao2_0(PropXbus_6, M5_GenXbus_5, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_1_line0); or2 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_1_Ao2_1(M5_GenXbus_6, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_1_line0, LocalCarryXCin0_6); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_2_Ao3a_0(PropXbus_6, M5_GenXbus_5, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_2_line0); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_2_Ao3a_1(PropXbus_6, PropXbus_5, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_2_line1); or3 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_2_Ao3a_2(M5_GenXbus_6, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_2_line0, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_2_line1, LocalCarryXCin1_6); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_3_Ao3a_0(PropXbus_7, M5_GenXbus_6, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_3_line0); and3 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_3_Ao3a_1(PropXbus_7, PropXbus_6, M5_GenXbus_5, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_3_line1); or3 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_3_Ao3a_2(M5_GenXbus_7, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_3_line0, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_3_line1, LocalCarryXCin0_7); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_4_Ao4a_0(PropXbus_7, M5_GenXbus_6, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_4_line0); and3 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_4_Ao4a_1(PropXbus_7, PropXbus_6, M5_GenXbus_5, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_4_line1); and3 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_4_Ao4a_2(PropXbus_7, PropXbus_6, PropXbus_5, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_4_line2); or4 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_4_Ao4a_3(M5_GenXbus_7, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_4_line0, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_4_line1, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_4_line2, LocalCarryXCin1_7); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_5_Ao4a_0(PropXbus_8, M5_GenXbus_7, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_5_line0); and3 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_5_Ao4a_1(PropXbus_8, PropXbus_7, M5_GenXbus_6, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_5_line1); and4 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_5_Ao4a_2(PropXbus_8, PropXbus_7, PropXbus_6, M5_GenXbus_5, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_5_line2); or4 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_5_Ao4a_3(M5_GenXbus_8, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_5_line0, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_5_line1, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_5_line2, LocalCarryXCin0_8); and2 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_6_Ao5a_0(PropXbus_8, M5_GenXbus_7, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line0); and3 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_6_Ao5a_1(PropXbus_8, PropXbus_7, M5_GenXbus_6, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line1); and4 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_6_Ao5a_2(PropXbus_8, PropXbus_7, PropXbus_6, M5_GenXbus_5, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line2); and4 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_6_Ao5a_3(PropXbus_8, PropXbus_7, PropXbus_6, PropXbus_5, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line3); or5 M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_6_Ao5a_4(M5_GenXbus_8, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line0, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line1, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line2, M5_UM5_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line3, LocalCarryXCin1_8); or2 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_0(M5_GenXbus_9, PropXbus_9, LocalCarryXCin1_9); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_1_Ao2_0(PropXbus_10, M5_GenXbus_9, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_1_line0); or2 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_1_Ao2_1(M5_GenXbus_10, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_1_line0, LocalCarryXCin0_10); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_Ao3a_0(PropXbus_10, M5_GenXbus_9, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_line0); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_Ao3a_1(PropXbus_10, PropXbus_9, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_line1); or3 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_Ao3a_2(M5_GenXbus_10, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_line0, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_line1, LocalCarryXCin1_10); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_Ao3a_0(PropXbus_11, M5_GenXbus_10, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_line0); and3 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_Ao3a_1(PropXbus_11, PropXbus_10, M5_GenXbus_9, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_line1); or3 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_Ao3a_2(M5_GenXbus_11, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_line0, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_line1, LocalCarryXCin0_11); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_Ao4a_0(PropXbus_11, M5_GenXbus_10, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_line0); and3 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_Ao4a_1(PropXbus_11, PropXbus_10, M5_GenXbus_9, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_line1); and3 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_Ao4a_2(PropXbus_11, PropXbus_10, PropXbus_9, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_line2); or4 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_Ao4a_3(M5_GenXbus_11, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_line0, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_line1, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_line2, LocalCarryXCin1_11); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_Ao4a_0(PropXbus_12, M5_GenXbus_11, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_line0); and3 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_Ao4a_1(PropXbus_12, PropXbus_11, M5_GenXbus_10, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_line1); and4 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_Ao4a_2(PropXbus_12, PropXbus_11, PropXbus_10, M5_GenXbus_9, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_line2); or4 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_Ao4a_3(M5_GenXbus_12, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_line0, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_line1, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_line2, LocalCarryXCin0_12); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_Ao5a_0(PropXbus_12, M5_GenXbus_11, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line0); and3 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_Ao5a_1(PropXbus_12, PropXbus_11, M5_GenXbus_10, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line1); and4 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_Ao5a_2(PropXbus_12, PropXbus_11, PropXbus_10, M5_GenXbus_9, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line2); and4 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_Ao5a_3(PropXbus_12, PropXbus_11, PropXbus_10, PropXbus_9, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line3); or5 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_Ao5a_4(M5_GenXbus_12, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line0, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line1, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line2, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line3, LocalCarryXCin1_12); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_1_Ao5a_0(PropXbus_13, M5_GenXbus_12, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line0); and3 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_1_Ao5a_1(PropXbus_13, PropXbus_12, M5_GenXbus_11, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line1); and4 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_1_Ao5a_2(PropXbus_13, PropXbus_12, PropXbus_11, M5_GenXbus_10, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line2); and5 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_1_Ao5a_3(PropXbus_13, PropXbus_12, PropXbus_11, PropXbus_10, M5_GenXbus_9, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line3); or5 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_1_Ao5a_4(M5_GenXbus_13, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line0, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line1, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line2, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line3, LocalCarryXCin0_13); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_Ao6a_0(PropXbus_13, M5_GenXbus_12, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line0); and3 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_Ao6a_1(PropXbus_13, PropXbus_12, M5_GenXbus_11, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line1); and4 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_Ao6a_2(PropXbus_13, PropXbus_12, PropXbus_11, M5_GenXbus_10, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line2); and5 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_Ao6a_3(PropXbus_13, PropXbus_12, PropXbus_11, PropXbus_10, M5_GenXbus_9, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line3); and5 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_Ao6a_4(PropXbus_13, PropXbus_12, PropXbus_11, PropXbus_10, PropXbus_9, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line4); or6 M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_Ao6a_5(M5_GenXbus_13, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line0, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line1, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line2, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line3, M5_UM5_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line4, LocalCarryXCin1_13); or2 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_0(M5_GenXbus_14, PropXbus_14, LocalCarryXCin1_14); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_1_Ao2_0(PropXbus_15, M5_GenXbus_14, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_1_line0); or2 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_1_Ao2_1(M5_GenXbus_15, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_1_line0, LocalCarryXCin0_15); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_2_Ao3a_0(PropXbus_15, M5_GenXbus_14, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_2_line0); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_2_Ao3a_1(PropXbus_15, PropXbus_14, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_2_line1); or3 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_2_Ao3a_2(M5_GenXbus_15, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_2_line0, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_2_line1, LocalCarryXCin1_15); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_3_Ao3a_0(PropXbus_16, M5_GenXbus_15, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_3_line0); and3 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_3_Ao3a_1(PropXbus_16, PropXbus_15, M5_GenXbus_14, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_3_line1); or3 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_3_Ao3a_2(M5_GenXbus_16, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_3_line0, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_3_line1, LocalCarryXCin0_16); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_4_Ao4a_0(PropXbus_16, M5_GenXbus_15, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_4_line0); and3 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_4_Ao4a_1(PropXbus_16, PropXbus_15, M5_GenXbus_14, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_4_line1); and3 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_4_Ao4a_2(PropXbus_16, PropXbus_15, PropXbus_14, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_4_line2); or4 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_4_Ao4a_3(M5_GenXbus_16, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_4_line0, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_4_line1, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_4_line2, LocalCarryXCin1_16); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_5_Ao4a_0(PropXbus_17, M5_GenXbus_16, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_5_line0); and3 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_5_Ao4a_1(PropXbus_17, PropXbus_16, M5_GenXbus_15, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_5_line1); and4 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_5_Ao4a_2(PropXbus_17, PropXbus_16, PropXbus_15, M5_GenXbus_14, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_5_line2); or4 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_5_Ao4a_3(M5_GenXbus_17, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_5_line0, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_5_line1, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_5_line2, LocalCarryXCin0_17); and2 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_6_Ao5a_0(PropXbus_17, M5_GenXbus_16, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line0); and3 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_6_Ao5a_1(PropXbus_17, PropXbus_16, M5_GenXbus_15, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line1); and4 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_6_Ao5a_2(PropXbus_17, PropXbus_16, PropXbus_15, M5_GenXbus_14, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line2); and4 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_6_Ao5a_3(PropXbus_17, PropXbus_16, PropXbus_15, PropXbus_14, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line3); or5 M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_6_Ao5a_4(M5_GenXbus_17, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line0, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line1, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line2, M5_UM5_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line3, LocalCarryXCin1_17); or2 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_0(M5_GenXbus_18, PropXbus_18, LocalCarryXCin1_18); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_1_Ao2_0(PropXbus_19, M5_GenXbus_18, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_1_line0); or2 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_1_Ao2_1(M5_GenXbus_19, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_1_line0, LocalCarryXCin0_19); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_Ao3a_0(PropXbus_19, M5_GenXbus_18, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_line0); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_Ao3a_1(PropXbus_19, PropXbus_18, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_line1); or3 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_Ao3a_2(M5_GenXbus_19, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_line0, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_line1, LocalCarryXCin1_19); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_Ao3a_0(PropXbus_20, M5_GenXbus_19, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_line0); and3 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_Ao3a_1(PropXbus_20, PropXbus_19, M5_GenXbus_18, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_line1); or3 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_Ao3a_2(M5_GenXbus_20, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_line0, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_line1, LocalCarryXCin0_20); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_Ao4a_0(PropXbus_20, M5_GenXbus_19, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_line0); and3 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_Ao4a_1(PropXbus_20, PropXbus_19, M5_GenXbus_18, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_line1); and3 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_Ao4a_2(PropXbus_20, PropXbus_19, PropXbus_18, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_line2); or4 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_Ao4a_3(M5_GenXbus_20, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_line0, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_line1, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_line2, LocalCarryXCin1_20); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_Ao4a_0(PropXbus_21, M5_GenXbus_20, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_line0); and3 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_Ao4a_1(PropXbus_21, PropXbus_20, M5_GenXbus_19, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_line1); and4 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_Ao4a_2(PropXbus_21, PropXbus_20, PropXbus_19, M5_GenXbus_18, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_line2); or4 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_Ao4a_3(M5_GenXbus_21, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_line0, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_line1, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_line2, LocalCarryXCin0_21); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_Ao5a_0(PropXbus_21, M5_GenXbus_20, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line0); and3 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_Ao5a_1(PropXbus_21, PropXbus_20, M5_GenXbus_19, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line1); and4 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_Ao5a_2(PropXbus_21, PropXbus_20, PropXbus_19, M5_GenXbus_18, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line2); and4 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_Ao5a_3(PropXbus_21, PropXbus_20, PropXbus_19, PropXbus_18, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line3); or5 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_Ao5a_4(M5_GenXbus_21, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line0, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line1, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line2, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line3, LocalCarryXCin1_21); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_1_Ao5a_0(PropXbus_22, M5_GenXbus_21, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line0); and3 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_1_Ao5a_1(PropXbus_22, PropXbus_21, M5_GenXbus_20, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line1); and4 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_1_Ao5a_2(PropXbus_22, PropXbus_21, PropXbus_20, M5_GenXbus_19, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line2); and5 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_1_Ao5a_3(PropXbus_22, PropXbus_21, PropXbus_20, PropXbus_19, M5_GenXbus_18, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line3); or5 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_1_Ao5a_4(M5_GenXbus_22, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line0, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line1, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line2, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line3, LocalCarryXCin0_22); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_Ao6a_0(PropXbus_22, M5_GenXbus_21, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line0); and3 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_Ao6a_1(PropXbus_22, PropXbus_21, M5_GenXbus_20, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line1); and4 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_Ao6a_2(PropXbus_22, PropXbus_21, PropXbus_20, M5_GenXbus_19, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line2); and5 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_Ao6a_3(PropXbus_22, PropXbus_21, PropXbus_20, PropXbus_19, M5_GenXbus_18, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line3); and5 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_Ao6a_4(PropXbus_22, PropXbus_21, PropXbus_20, PropXbus_19, PropXbus_18, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line4); or6 M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_Ao6a_5(M5_GenXbus_22, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line0, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line1, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line2, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line3, M5_UM5_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line4, LocalCarryXCin1_22); or2 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_0(M5_GenXbus_23, PropXbus_23, LocalCarryXCin1_23); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_1_Ao2_0(PropXbus_24, M5_GenXbus_23, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_1_line0); or2 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_1_Ao2_1(M5_GenXbus_24, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_1_line0, LocalCarryXCin0_24); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_2_Ao3a_0(PropXbus_24, M5_GenXbus_23, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_2_line0); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_2_Ao3a_1(PropXbus_24, PropXbus_23, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_2_line1); or3 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_2_Ao3a_2(M5_GenXbus_24, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_2_line0, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_2_line1, LocalCarryXCin1_24); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_3_Ao3a_0(PropXbus_25, M5_GenXbus_24, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_3_line0); and3 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_3_Ao3a_1(PropXbus_25, PropXbus_24, M5_GenXbus_23, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_3_line1); or3 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_3_Ao3a_2(M5_GenXbus_25, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_3_line0, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_3_line1, LocalCarryXCin0_25); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_4_Ao4a_0(PropXbus_25, M5_GenXbus_24, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_4_line0); and3 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_4_Ao4a_1(PropXbus_25, PropXbus_24, M5_GenXbus_23, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_4_line1); and3 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_4_Ao4a_2(PropXbus_25, PropXbus_24, PropXbus_23, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_4_line2); or4 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_4_Ao4a_3(M5_GenXbus_25, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_4_line0, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_4_line1, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_4_line2, LocalCarryXCin1_25); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_5_Ao4a_0(PropXbus_26, M5_GenXbus_25, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_5_line0); and3 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_5_Ao4a_1(PropXbus_26, PropXbus_25, M5_GenXbus_24, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_5_line1); and4 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_5_Ao4a_2(PropXbus_26, PropXbus_25, PropXbus_24, M5_GenXbus_23, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_5_line2); or4 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_5_Ao4a_3(M5_GenXbus_26, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_5_line0, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_5_line1, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_5_line2, LocalCarryXCin0_26); and2 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_6_Ao5a_0(PropXbus_26, M5_GenXbus_25, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line0); and3 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_6_Ao5a_1(PropXbus_26, PropXbus_25, M5_GenXbus_24, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line1); and4 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_6_Ao5a_2(PropXbus_26, PropXbus_25, PropXbus_24, M5_GenXbus_23, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line2); and4 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_6_Ao5a_3(PropXbus_26, PropXbus_25, PropXbus_24, PropXbus_23, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line3); or5 M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_6_Ao5a_4(M5_GenXbus_26, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line0, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line1, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line2, M5_UM5_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line3, LocalCarryXCin1_26); or2 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_0(M5_GenXbus_27, PropXbus_27, LocalCarryXCin1_27); and2 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_1_Ao2_0(PropXbus_28, M5_GenXbus_27, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_1_line0); or2 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_1_Ao2_1(M5_GenXbus_28, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_1_line0, LocalCarryXCin0_28); and2 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_2_Ao3a_0(PropXbus_28, M5_GenXbus_27, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_2_line0); and2 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_2_Ao3a_1(PropXbus_28, PropXbus_27, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_2_line1); or3 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_2_Ao3a_2(M5_GenXbus_28, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_2_line0, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_2_line1, LocalCarryXCin1_28); and2 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_3_Ao3a_0(PropXbus_29, M5_GenXbus_28, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_3_line0); and3 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_3_Ao3a_1(PropXbus_29, PropXbus_28, M5_GenXbus_27, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_3_line1); or3 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_3_Ao3a_2(M5_GenXbus_29, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_3_line0, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_3_line1, LocalCarryXCin0_29); and2 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_4_Ao4a_0(PropXbus_29, M5_GenXbus_28, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_4_line0); and3 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_4_Ao4a_1(PropXbus_29, PropXbus_28, M5_GenXbus_27, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_4_line1); and3 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_4_Ao4a_2(PropXbus_29, PropXbus_28, PropXbus_27, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_4_line2); or4 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_4_Ao4a_3(M5_GenXbus_29, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_4_line0, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_4_line1, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_4_line2, LocalCarryXCin1_29); and2 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_5_Ao4a_0(PropXbus_30, M5_GenXbus_29, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_5_line0); and3 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_5_Ao4a_1(PropXbus_30, PropXbus_29, M5_GenXbus_28, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_5_line1); and4 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_5_Ao4a_2(PropXbus_30, PropXbus_29, PropXbus_28, M5_GenXbus_27, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_5_line2); or4 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_5_Ao4a_3(M5_GenXbus_30, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_5_line0, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_5_line1, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_5_line2, LocalCarryXCin0_30); and2 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_6_Ao5a_0(PropXbus_30, M5_GenXbus_29, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line0); and3 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_6_Ao5a_1(PropXbus_30, PropXbus_29, M5_GenXbus_28, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line1); and4 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_6_Ao5a_2(PropXbus_30, PropXbus_29, PropXbus_28, M5_GenXbus_27, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line2); and4 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_6_Ao5a_3(PropXbus_30, PropXbus_29, PropXbus_28, PropXbus_27, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line3); or5 M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_6_Ao5a_4(M5_GenXbus_30, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line0, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line1, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line2, M5_UM5_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line3, LocalCarryXCin1_30); and2 M5_UM5_1_CC_0_GLC34_3_GLC5_1_Ao5a_0(PropXbus_31, M5_GenXbus_30, M5_UM5_1_CC_0_GLC34_3_GLC5_1_line0); and3 M5_UM5_1_CC_0_GLC34_3_GLC5_1_Ao5a_1(PropXbus_31, PropXbus_30, M5_GenXbus_29, M5_UM5_1_CC_0_GLC34_3_GLC5_1_line1); and4 M5_UM5_1_CC_0_GLC34_3_GLC5_1_Ao5a_2(PropXbus_31, PropXbus_30, PropXbus_29, M5_GenXbus_28, M5_UM5_1_CC_0_GLC34_3_GLC5_1_line2); and5 M5_UM5_1_CC_0_GLC34_3_GLC5_1_Ao5a_3(PropXbus_31, PropXbus_30, PropXbus_29, PropXbus_28, M5_GenXbus_27, M5_UM5_1_CC_0_GLC34_3_GLC5_1_line3); or5 M5_UM5_1_CC_0_GLC34_3_GLC5_1_Ao5a_4(M5_GenXbus_31, M5_UM5_1_CC_0_GLC34_3_GLC5_1_line0, M5_UM5_1_CC_0_GLC34_3_GLC5_1_line1, M5_UM5_1_CC_0_GLC34_3_GLC5_1_line2, M5_UM5_1_CC_0_GLC34_3_GLC5_1_line3, LocalCarryXCin0_31); and2 M5_UM5_1_CC_0_GLC34_3_GLC5_2_Ao6a_0(PropXbus_31, M5_GenXbus_30, M5_UM5_1_CC_0_GLC34_3_GLC5_2_line0); and3 M5_UM5_1_CC_0_GLC34_3_GLC5_2_Ao6a_1(PropXbus_31, PropXbus_30, M5_GenXbus_29, M5_UM5_1_CC_0_GLC34_3_GLC5_2_line1); and4 M5_UM5_1_CC_0_GLC34_3_GLC5_2_Ao6a_2(PropXbus_31, PropXbus_30, PropXbus_29, M5_GenXbus_28, M5_UM5_1_CC_0_GLC34_3_GLC5_2_line2); and5 M5_UM5_1_CC_0_GLC34_3_GLC5_2_Ao6a_3(PropXbus_31, PropXbus_30, PropXbus_29, PropXbus_28, M5_GenXbus_27, M5_UM5_1_CC_0_GLC34_3_GLC5_2_line3); and5 M5_UM5_1_CC_0_GLC34_3_GLC5_2_Ao6a_4(PropXbus_31, PropXbus_30, PropXbus_29, PropXbus_28, PropXbus_27, M5_UM5_1_CC_0_GLC34_3_GLC5_2_line4); or6 M5_UM5_1_CC_0_GLC34_3_GLC5_2_Ao6a_5(M5_GenXbus_31, M5_UM5_1_CC_0_GLC34_3_GLC5_2_line0, M5_UM5_1_CC_0_GLC34_3_GLC5_2_line1, M5_UM5_1_CC_0_GLC34_3_GLC5_2_line2, M5_UM5_1_CC_0_GLC34_3_GLC5_2_line3, M5_UM5_1_CC_0_GLC34_3_GLC5_2_line4, LocalCarryXCin1_31); or2 M5_UM5_1_CC_0_GLC34_4_GLC2_0(M5_GenXbus_32, PropXbus_32, LocalCarryXCin1_32); and2 M5_UM5_1_CC_0_GLC34_4_GLC2_1_Ao2_0(PropXbus_33, M5_GenXbus_32, M5_UM5_1_CC_0_GLC34_4_GLC2_1_line0); or2 M5_UM5_1_CC_0_GLC34_4_GLC2_1_Ao2_1(M5_GenXbus_33, M5_UM5_1_CC_0_GLC34_4_GLC2_1_line0, LocalCarryXCin0_33); and2 M5_UM5_1_CC_0_GLC34_4_GLC2_2_Ao3a_0(PropXbus_33, M5_GenXbus_32, M5_UM5_1_CC_0_GLC34_4_GLC2_2_line0); and2 M5_UM5_1_CC_0_GLC34_4_GLC2_2_Ao3a_1(PropXbus_33, PropXbus_32, M5_UM5_1_CC_0_GLC34_4_GLC2_2_line1); or3 M5_UM5_1_CC_0_GLC34_4_GLC2_2_Ao3a_2(M5_GenXbus_33, M5_UM5_1_CC_0_GLC34_4_GLC2_2_line0, M5_UM5_1_CC_0_GLC34_4_GLC2_2_line1, LocalCarryXCin1_33); and5 M5_UM5_1_CC_1_CGC34_0_CBC0(PropXbus_0, PropXbus_1, PropXbus_2, PropXbus_3, PropXbus_4, M5_UM5_1_CC_1_CGC34_0_Prop4_0); and4 M5_UM5_1_CC_1_CGC34_0_CBC1(PropXbus_5, PropXbus_6, PropXbus_7, PropXbus_8, M5_UM5_1_CC_1_CGC34_0_Prop8_5); and5 M5_UM5_1_CC_1_CGC34_0_CBC2(PropXbus_9, PropXbus_10, PropXbus_11, PropXbus_12, PropXbus_13, M5_UM5_1_CC_1_CGC34_0_Prop13_9); and4 M5_UM5_1_CC_1_CGC34_0_CBC3(PropXbus_14, PropXbus_15, PropXbus_16, PropXbus_17, M5_UM5_1_CC_1_CGC34_0_Prop17_14); and5 M5_UM5_1_CC_1_CGC34_0_CBC4(PropXbus_18, PropXbus_19, PropXbus_20, PropXbus_21, PropXbus_22, M5_UM5_1_CC_1_CGC34_0_Prop22_18); and4 M5_UM5_1_CC_1_CGC34_0_CBC5(PropXbus_23, PropXbus_24, PropXbus_25, PropXbus_26, M5_UM5_1_CC_1_CGC34_0_Prop26_23); and5 M5_UM5_1_CC_1_CGC34_0_CBC6(PropXbus_27, PropXbus_28, PropXbus_29, PropXbus_30, PropXbus_31, M5_UM5_1_CC_1_CGC34_0_Prop31_27); and2 M5_UM5_1_CC_1_CGC34_0_CBC7(PropXbus_32, PropXbus_33, M5_UM5_1_CC_1_CGC34_0_Prop33_32); and2 M5_UM5_1_CC_1_CGC34_0_CBC8(M5_UM5_1_CC_1_CGC34_0_Prop4_0, M5_UM5_1_CC_1_CGC34_0_Prop8_5, M5_UM5_1_CC_1_CGC34_0_Prop8_0); and2 M5_UM5_1_CC_1_CGC34_0_CBC9(M5_UM5_1_CC_1_CGC34_0_Prop13_9, M5_UM5_1_CC_1_CGC34_0_Prop17_14, M5_UM5_1_CC_1_CGC34_0_Prop17_9); and2 M5_UM5_1_CC_1_CGC34_0_CBC10(M5_UM5_1_CC_1_CGC34_0_Prop22_18, M5_UM5_1_CC_1_CGC34_0_Prop26_23, M5_UM5_1_CC_1_CGC34_0_Prop26_18); and2 M5_UM5_1_CC_1_CGC34_0_CBC11(M5_UM5_1_CC_1_CGC34_0_Prop31_27, M5_UM5_1_CC_1_CGC34_0_Prop33_32, M5_UM5_1_CC_1_CGC34_0_Prop33_27); and2 M5_UM5_1_CC_1_CGC34_0_CBC12_Ao2_0(in4526, M5_UM5_1_CC_1_CGC34_0_Prop4_0, M5_UM5_1_CC_1_CGC34_0_CBC12_line0); or2 M5_UM5_1_CC_1_CGC34_0_CBC12_Ao2_1(LocalCarryXCin0_4, M5_UM5_1_CC_1_CGC34_0_CBC12_line0, CarryXbus_4); inv M5_UM5_1_CC_1_CGC34_0_CGC13_Mux0(CarryXbus_4, M5_UM5_1_CC_1_CGC34_0_CGC13_Not_ContIn); and2 M5_UM5_1_CC_1_CGC34_0_CGC13_Mux1(LocalCarryXCin0_8, M5_UM5_1_CC_1_CGC34_0_CGC13_Not_ContIn, M5_UM5_1_CC_1_CGC34_0_CGC13_line1); and2 M5_UM5_1_CC_1_CGC34_0_CGC13_Mux2(LocalCarryXCin1_8, CarryXbus_4, M5_UM5_1_CC_1_CGC34_0_CGC13_line2); or2 M5_UM5_1_CC_1_CGC34_0_CGC13_Mux3(M5_UM5_1_CC_1_CGC34_0_CGC13_line1, M5_UM5_1_CC_1_CGC34_0_CGC13_line2, CarryXbus_8); and2 M5_UM5_1_CC_1_CGC34_0_GGC14_Ao2_0(CarryXbus_8, M5_UM5_1_CC_1_CGC34_0_Prop13_9, M5_UM5_1_CC_1_CGC34_0_GGC14_line0); or2 M5_UM5_1_CC_1_CGC34_0_GGC14_Ao2_1(LocalCarryXCin0_13, M5_UM5_1_CC_1_CGC34_0_GGC14_line0, CarryXbus_13); and2 M5_UM5_1_CC_1_CGC34_0_CGC15_Ao2_0(LocalCarryXCin0_13, M5_UM5_1_CC_1_CGC34_0_Prop17_14, M5_UM5_1_CC_1_CGC34_0_CGC15_line0); or2 M5_UM5_1_CC_1_CGC34_0_CGC15_Ao2_1(LocalCarryXCin0_17, M5_UM5_1_CC_1_CGC34_0_CGC15_line0, M5_UM5_1_CC_1_CGC34_0_LocalCarry17_9); and2 M5_UM5_1_CC_1_CGC34_0_CGC16_Ao2_0(LocalCarryXCin0_4, M5_UM5_1_CC_1_CGC34_0_Prop8_5, M5_UM5_1_CC_1_CGC34_0_CGC16_line0); or2 M5_UM5_1_CC_1_CGC34_0_CGC16_Ao2_1(LocalCarryXCin0_8, M5_UM5_1_CC_1_CGC34_0_CGC16_line0, M5_UM5_1_CC_1_CGC34_0_LocalCarry8_0); and2 M5_UM5_1_CC_1_CGC34_0_CGC17_Ao3a_0(M5_UM5_1_CC_1_CGC34_0_Prop17_9, M5_UM5_1_CC_1_CGC34_0_LocalCarry8_0, M5_UM5_1_CC_1_CGC34_0_CGC17_line0); and3 M5_UM5_1_CC_1_CGC34_0_CGC17_Ao3a_1(M5_UM5_1_CC_1_CGC34_0_Prop17_9, M5_UM5_1_CC_1_CGC34_0_Prop8_0, in4526, M5_UM5_1_CC_1_CGC34_0_CGC17_line1); or3 M5_UM5_1_CC_1_CGC34_0_CGC17_Ao3a_2(M5_UM5_1_CC_1_CGC34_0_LocalCarry17_9, M5_UM5_1_CC_1_CGC34_0_CGC17_line0, M5_UM5_1_CC_1_CGC34_0_CGC17_line1, CarryXbus_17); and2 M5_UM5_1_CC_1_CGC34_0_CGC18_Ao2_0(CarryXbus_17, M5_UM5_1_CC_1_CGC34_0_Prop22_18, M5_UM5_1_CC_1_CGC34_0_CGC18_line0); or2 M5_UM5_1_CC_1_CGC34_0_CGC18_Ao2_1(LocalCarryXCin0_22, M5_UM5_1_CC_1_CGC34_0_CGC18_line0, CarryXbus_22); and2 M5_UM5_1_CC_1_CGC34_0_CGC19_Ao2_0(LocalCarryXCin0_22, M5_UM5_1_CC_1_CGC34_0_Prop26_23, M5_UM5_1_CC_1_CGC34_0_CGC19_line0); or2 M5_UM5_1_CC_1_CGC34_0_CGC19_Ao2_1(LocalCarryXCin0_26, M5_UM5_1_CC_1_CGC34_0_CGC19_line0, M5_UM5_1_CC_1_CGC34_0_LocalCarry26_18); and2 M5_UM5_1_CC_1_CGC34_0_CGC20_Ao4a_0(M5_UM5_1_CC_1_CGC34_0_Prop26_18, M5_UM5_1_CC_1_CGC34_0_LocalCarry17_9, M5_UM5_1_CC_1_CGC34_0_CGC20_line0); and3 M5_UM5_1_CC_1_CGC34_0_CGC20_Ao4a_1(M5_UM5_1_CC_1_CGC34_0_Prop26_18, M5_UM5_1_CC_1_CGC34_0_Prop17_9, M5_UM5_1_CC_1_CGC34_0_LocalCarry8_0, M5_UM5_1_CC_1_CGC34_0_CGC20_line1); and4 M5_UM5_1_CC_1_CGC34_0_CGC20_Ao4a_2(M5_UM5_1_CC_1_CGC34_0_Prop26_18, M5_UM5_1_CC_1_CGC34_0_Prop17_9, M5_UM5_1_CC_1_CGC34_0_Prop8_0, in4526, M5_UM5_1_CC_1_CGC34_0_CGC20_line2); or4 M5_UM5_1_CC_1_CGC34_0_CGC20_Ao4a_3(M5_UM5_1_CC_1_CGC34_0_LocalCarry26_18, M5_UM5_1_CC_1_CGC34_0_CGC20_line0, M5_UM5_1_CC_1_CGC34_0_CGC20_line1, M5_UM5_1_CC_1_CGC34_0_CGC20_line2, CarryXbus_26); and2 M5_UM5_1_CC_1_CGC34_0_CGC21_Ao2_0(CarryXbus_26, M5_UM5_1_CC_1_CGC34_0_Prop31_27, M5_UM5_1_CC_1_CGC34_0_CGC21_line0); or2 M5_UM5_1_CC_1_CGC34_0_CGC21_Ao2_1(LocalCarryXCin0_31, M5_UM5_1_CC_1_CGC34_0_CGC21_line0, CarryXbus_31); and2 M5_UM5_1_CC_1_CGC34_0_CGC22_Ao2_0(LocalCarryXCin0_31, M5_UM5_1_CC_1_CGC34_0_Prop33_32, M5_UM5_1_CC_1_CGC34_0_CGC22_line0); or2 M5_UM5_1_CC_1_CGC34_0_CGC22_Ao2_1(LocalCarryXCin0_33, M5_UM5_1_CC_1_CGC34_0_CGC22_line0, M5_UM5_1_CC_1_CGC34_0_LocalCarry33_27); and2 M5_UM5_1_CC_1_CGC34_0_CGC23_Ao5a_0(M5_UM5_1_CC_1_CGC34_0_Prop33_27, M5_UM5_1_CC_1_CGC34_0_LocalCarry26_18, M5_UM5_1_CC_1_CGC34_0_CGC23_line0); and3 M5_UM5_1_CC_1_CGC34_0_CGC23_Ao5a_1(M5_UM5_1_CC_1_CGC34_0_Prop33_27, M5_UM5_1_CC_1_CGC34_0_Prop26_18, M5_UM5_1_CC_1_CGC34_0_LocalCarry17_9, M5_UM5_1_CC_1_CGC34_0_CGC23_line1); and4 M5_UM5_1_CC_1_CGC34_0_CGC23_Ao5a_2(M5_UM5_1_CC_1_CGC34_0_Prop33_27, M5_UM5_1_CC_1_CGC34_0_Prop26_18, M5_UM5_1_CC_1_CGC34_0_Prop17_9, M5_UM5_1_CC_1_CGC34_0_LocalCarry8_0, M5_UM5_1_CC_1_CGC34_0_CGC23_line2); and5 M5_UM5_1_CC_1_CGC34_0_CGC23_Ao5a_3(M5_UM5_1_CC_1_CGC34_0_Prop33_27, M5_UM5_1_CC_1_CGC34_0_Prop26_18, M5_UM5_1_CC_1_CGC34_0_Prop17_9, M5_UM5_1_CC_1_CGC34_0_Prop8_0, in4526, M5_UM5_1_CC_1_CGC34_0_CGC23_line3); or5 M5_UM5_1_CC_1_CGC34_0_CGC23_Ao5a_4(M5_UM5_1_CC_1_CGC34_0_LocalCarry33_27, M5_UM5_1_CC_1_CGC34_0_CGC23_line0, M5_UM5_1_CC_1_CGC34_0_CGC23_line1, M5_UM5_1_CC_1_CGC34_0_CGC23_line2, M5_UM5_1_CC_1_CGC34_0_CGC23_line3, CarryXbus_33); and2 M5_UM5_1_CC_1_CGC34_1_CB5_0_Ao2_0(PropXbus_0, in4526, M5_UM5_1_CC_1_CGC34_1_CB5_0_line0); or2 M5_UM5_1_CC_1_CGC34_1_CB5_0_Ao2_1(M5_GenXbus_0, M5_UM5_1_CC_1_CGC34_1_CB5_0_line0, CarryXbus_0); and2 M5_UM5_1_CC_1_CGC34_1_CB5_1_Ao3a_0(PropXbus_1, M5_GenXbus_0, M5_UM5_1_CC_1_CGC34_1_CB5_1_line0); and3 M5_UM5_1_CC_1_CGC34_1_CB5_1_Ao3a_1(PropXbus_1, PropXbus_0, in4526, M5_UM5_1_CC_1_CGC34_1_CB5_1_line1); or3 M5_UM5_1_CC_1_CGC34_1_CB5_1_Ao3a_2(M5_GenXbus_1, M5_UM5_1_CC_1_CGC34_1_CB5_1_line0, M5_UM5_1_CC_1_CGC34_1_CB5_1_line1, CarryXbus_1); and2 M5_UM5_1_CC_1_CGC34_1_CB5_2_Ao4a_0(PropXbus_2, M5_GenXbus_1, M5_UM5_1_CC_1_CGC34_1_CB5_2_line0); and3 M5_UM5_1_CC_1_CGC34_1_CB5_2_Ao4a_1(PropXbus_2, PropXbus_1, M5_GenXbus_0, M5_UM5_1_CC_1_CGC34_1_CB5_2_line1); and4 M5_UM5_1_CC_1_CGC34_1_CB5_2_Ao4a_2(PropXbus_2, PropXbus_1, PropXbus_0, in4526, M5_UM5_1_CC_1_CGC34_1_CB5_2_line2); or4 M5_UM5_1_CC_1_CGC34_1_CB5_2_Ao4a_3(M5_GenXbus_2, M5_UM5_1_CC_1_CGC34_1_CB5_2_line0, M5_UM5_1_CC_1_CGC34_1_CB5_2_line1, M5_UM5_1_CC_1_CGC34_1_CB5_2_line2, CarryXbus_2); and2 M5_UM5_1_CC_1_CGC34_1_CB5_3_Ao5a_0(PropXbus_3, M5_GenXbus_2, M5_UM5_1_CC_1_CGC34_1_CB5_3_line0); and3 M5_UM5_1_CC_1_CGC34_1_CB5_3_Ao5a_1(PropXbus_3, PropXbus_2, M5_GenXbus_1, M5_UM5_1_CC_1_CGC34_1_CB5_3_line1); and4 M5_UM5_1_CC_1_CGC34_1_CB5_3_Ao5a_2(PropXbus_3, PropXbus_2, PropXbus_1, M5_GenXbus_0, M5_UM5_1_CC_1_CGC34_1_CB5_3_line2); and5 M5_UM5_1_CC_1_CGC34_1_CB5_3_Ao5a_3(PropXbus_3, PropXbus_2, PropXbus_1, PropXbus_0, in4526, M5_UM5_1_CC_1_CGC34_1_CB5_3_line3); or5 M5_UM5_1_CC_1_CGC34_1_CB5_3_Ao5a_4(M5_GenXbus_3, M5_UM5_1_CC_1_CGC34_1_CB5_3_line0, M5_UM5_1_CC_1_CGC34_1_CB5_3_line1, M5_UM5_1_CC_1_CGC34_1_CB5_3_line2, M5_UM5_1_CC_1_CGC34_1_CB5_3_line3, CarryXbus_3); and2 M5_UM5_1_CC_1_CGC34_2_CB5_0_Ao2_0(PropXbus_9, CarryXbus_8, M5_UM5_1_CC_1_CGC34_2_CB5_0_line0); or2 M5_UM5_1_CC_1_CGC34_2_CB5_0_Ao2_1(M5_GenXbus_9, M5_UM5_1_CC_1_CGC34_2_CB5_0_line0, CarryXbus_9); and2 M5_UM5_1_CC_1_CGC34_2_CB5_1_Ao3a_0(PropXbus_10, M5_GenXbus_9, M5_UM5_1_CC_1_CGC34_2_CB5_1_line0); and3 M5_UM5_1_CC_1_CGC34_2_CB5_1_Ao3a_1(PropXbus_10, PropXbus_9, CarryXbus_8, M5_UM5_1_CC_1_CGC34_2_CB5_1_line1); or3 M5_UM5_1_CC_1_CGC34_2_CB5_1_Ao3a_2(M5_GenXbus_10, M5_UM5_1_CC_1_CGC34_2_CB5_1_line0, M5_UM5_1_CC_1_CGC34_2_CB5_1_line1, CarryXbus_10); and2 M5_UM5_1_CC_1_CGC34_2_CB5_2_Ao4a_0(PropXbus_11, M5_GenXbus_10, M5_UM5_1_CC_1_CGC34_2_CB5_2_line0); and3 M5_UM5_1_CC_1_CGC34_2_CB5_2_Ao4a_1(PropXbus_11, PropXbus_10, M5_GenXbus_9, M5_UM5_1_CC_1_CGC34_2_CB5_2_line1); and4 M5_UM5_1_CC_1_CGC34_2_CB5_2_Ao4a_2(PropXbus_11, PropXbus_10, PropXbus_9, CarryXbus_8, M5_UM5_1_CC_1_CGC34_2_CB5_2_line2); or4 M5_UM5_1_CC_1_CGC34_2_CB5_2_Ao4a_3(M5_GenXbus_11, M5_UM5_1_CC_1_CGC34_2_CB5_2_line0, M5_UM5_1_CC_1_CGC34_2_CB5_2_line1, M5_UM5_1_CC_1_CGC34_2_CB5_2_line2, CarryXbus_11); and2 M5_UM5_1_CC_1_CGC34_2_CB5_3_Ao5a_0(PropXbus_12, M5_GenXbus_11, M5_UM5_1_CC_1_CGC34_2_CB5_3_line0); and3 M5_UM5_1_CC_1_CGC34_2_CB5_3_Ao5a_1(PropXbus_12, PropXbus_11, M5_GenXbus_10, M5_UM5_1_CC_1_CGC34_2_CB5_3_line1); and4 M5_UM5_1_CC_1_CGC34_2_CB5_3_Ao5a_2(PropXbus_12, PropXbus_11, PropXbus_10, M5_GenXbus_9, M5_UM5_1_CC_1_CGC34_2_CB5_3_line2); and5 M5_UM5_1_CC_1_CGC34_2_CB5_3_Ao5a_3(PropXbus_12, PropXbus_11, PropXbus_10, PropXbus_9, CarryXbus_8, M5_UM5_1_CC_1_CGC34_2_CB5_3_line3); or5 M5_UM5_1_CC_1_CGC34_2_CB5_3_Ao5a_4(M5_GenXbus_12, M5_UM5_1_CC_1_CGC34_2_CB5_3_line0, M5_UM5_1_CC_1_CGC34_2_CB5_3_line1, M5_UM5_1_CC_1_CGC34_2_CB5_3_line2, M5_UM5_1_CC_1_CGC34_2_CB5_3_line3, CarryXbus_12); and2 M5_UM5_1_CC_1_CGC34_3_CB5_0_Ao2_0(PropXbus_18, CarryXbus_17, M5_UM5_1_CC_1_CGC34_3_CB5_0_line0); or2 M5_UM5_1_CC_1_CGC34_3_CB5_0_Ao2_1(M5_GenXbus_18, M5_UM5_1_CC_1_CGC34_3_CB5_0_line0, CarryXbus_18); and2 M5_UM5_1_CC_1_CGC34_3_CB5_1_Ao3a_0(PropXbus_19, M5_GenXbus_18, M5_UM5_1_CC_1_CGC34_3_CB5_1_line0); and3 M5_UM5_1_CC_1_CGC34_3_CB5_1_Ao3a_1(PropXbus_19, PropXbus_18, CarryXbus_17, M5_UM5_1_CC_1_CGC34_3_CB5_1_line1); or3 M5_UM5_1_CC_1_CGC34_3_CB5_1_Ao3a_2(M5_GenXbus_19, M5_UM5_1_CC_1_CGC34_3_CB5_1_line0, M5_UM5_1_CC_1_CGC34_3_CB5_1_line1, CarryXbus_19); and2 M5_UM5_1_CC_1_CGC34_3_CB5_2_Ao4a_0(PropXbus_20, M5_GenXbus_19, M5_UM5_1_CC_1_CGC34_3_CB5_2_line0); and3 M5_UM5_1_CC_1_CGC34_3_CB5_2_Ao4a_1(PropXbus_20, PropXbus_19, M5_GenXbus_18, M5_UM5_1_CC_1_CGC34_3_CB5_2_line1); and4 M5_UM5_1_CC_1_CGC34_3_CB5_2_Ao4a_2(PropXbus_20, PropXbus_19, PropXbus_18, CarryXbus_17, M5_UM5_1_CC_1_CGC34_3_CB5_2_line2); or4 M5_UM5_1_CC_1_CGC34_3_CB5_2_Ao4a_3(M5_GenXbus_20, M5_UM5_1_CC_1_CGC34_3_CB5_2_line0, M5_UM5_1_CC_1_CGC34_3_CB5_2_line1, M5_UM5_1_CC_1_CGC34_3_CB5_2_line2, CarryXbus_20); and2 M5_UM5_1_CC_1_CGC34_3_CB5_3_Ao5a_0(PropXbus_21, M5_GenXbus_20, M5_UM5_1_CC_1_CGC34_3_CB5_3_line0); and3 M5_UM5_1_CC_1_CGC34_3_CB5_3_Ao5a_1(PropXbus_21, PropXbus_20, M5_GenXbus_19, M5_UM5_1_CC_1_CGC34_3_CB5_3_line1); and4 M5_UM5_1_CC_1_CGC34_3_CB5_3_Ao5a_2(PropXbus_21, PropXbus_20, PropXbus_19, M5_GenXbus_18, M5_UM5_1_CC_1_CGC34_3_CB5_3_line2); and5 M5_UM5_1_CC_1_CGC34_3_CB5_3_Ao5a_3(PropXbus_21, PropXbus_20, PropXbus_19, PropXbus_18, CarryXbus_17, M5_UM5_1_CC_1_CGC34_3_CB5_3_line3); or5 M5_UM5_1_CC_1_CGC34_3_CB5_3_Ao5a_4(M5_GenXbus_21, M5_UM5_1_CC_1_CGC34_3_CB5_3_line0, M5_UM5_1_CC_1_CGC34_3_CB5_3_line1, M5_UM5_1_CC_1_CGC34_3_CB5_3_line2, M5_UM5_1_CC_1_CGC34_3_CB5_3_line3, CarryXbus_21); and2 M5_UM5_1_CC_1_CGC34_4_CB5_0_Ao2_0(PropXbus_27, CarryXbus_26, M5_UM5_1_CC_1_CGC34_4_CB5_0_line0); or2 M5_UM5_1_CC_1_CGC34_4_CB5_0_Ao2_1(M5_GenXbus_27, M5_UM5_1_CC_1_CGC34_4_CB5_0_line0, CarryXbus_27); and2 M5_UM5_1_CC_1_CGC34_4_CB5_1_Ao3a_0(PropXbus_28, M5_GenXbus_27, M5_UM5_1_CC_1_CGC34_4_CB5_1_line0); and3 M5_UM5_1_CC_1_CGC34_4_CB5_1_Ao3a_1(PropXbus_28, PropXbus_27, CarryXbus_26, M5_UM5_1_CC_1_CGC34_4_CB5_1_line1); or3 M5_UM5_1_CC_1_CGC34_4_CB5_1_Ao3a_2(M5_GenXbus_28, M5_UM5_1_CC_1_CGC34_4_CB5_1_line0, M5_UM5_1_CC_1_CGC34_4_CB5_1_line1, CarryXbus_28); and2 M5_UM5_1_CC_1_CGC34_4_CB5_2_Ao4a_0(PropXbus_29, M5_GenXbus_28, M5_UM5_1_CC_1_CGC34_4_CB5_2_line0); and3 M5_UM5_1_CC_1_CGC34_4_CB5_2_Ao4a_1(PropXbus_29, PropXbus_28, M5_GenXbus_27, M5_UM5_1_CC_1_CGC34_4_CB5_2_line1); and4 M5_UM5_1_CC_1_CGC34_4_CB5_2_Ao4a_2(PropXbus_29, PropXbus_28, PropXbus_27, CarryXbus_26, M5_UM5_1_CC_1_CGC34_4_CB5_2_line2); or4 M5_UM5_1_CC_1_CGC34_4_CB5_2_Ao4a_3(M5_GenXbus_29, M5_UM5_1_CC_1_CGC34_4_CB5_2_line0, M5_UM5_1_CC_1_CGC34_4_CB5_2_line1, M5_UM5_1_CC_1_CGC34_4_CB5_2_line2, CarryXbus_29); and2 M5_UM5_1_CC_1_CGC34_4_CB5_3_Ao5a_0(PropXbus_30, M5_GenXbus_29, M5_UM5_1_CC_1_CGC34_4_CB5_3_line0); and3 M5_UM5_1_CC_1_CGC34_4_CB5_3_Ao5a_1(PropXbus_30, PropXbus_29, M5_GenXbus_28, M5_UM5_1_CC_1_CGC34_4_CB5_3_line1); and4 M5_UM5_1_CC_1_CGC34_4_CB5_3_Ao5a_2(PropXbus_30, PropXbus_29, PropXbus_28, M5_GenXbus_27, M5_UM5_1_CC_1_CGC34_4_CB5_3_line2); and5 M5_UM5_1_CC_1_CGC34_4_CB5_3_Ao5a_3(PropXbus_30, PropXbus_29, PropXbus_28, PropXbus_27, CarryXbus_26, M5_UM5_1_CC_1_CGC34_4_CB5_3_line3); or5 M5_UM5_1_CC_1_CGC34_4_CB5_3_Ao5a_4(M5_GenXbus_30, M5_UM5_1_CC_1_CGC34_4_CB5_3_line0, M5_UM5_1_CC_1_CGC34_4_CB5_3_line1, M5_UM5_1_CC_1_CGC34_4_CB5_3_line2, M5_UM5_1_CC_1_CGC34_4_CB5_3_line3, CarryXbus_30); inv M5_UM5_1_CC_2_Mux0(CarryXbus_31, M5_UM5_1_CC_2_Not_ContIn); and2 M5_UM5_1_CC_2_Mux1(LocalCarryXCin0_33, M5_UM5_1_CC_2_Not_ContIn, M5_UM5_1_CC_2_line1); and2 M5_UM5_1_CC_2_Mux2(LocalCarryXCin1_33, CarryXbus_31, M5_UM5_1_CC_2_line2); or2 M5_UM5_1_CC_2_Mux3(M5_UM5_1_CC_2_line1, M5_UM5_1_CC_2_line2, out273); inv M6_UM6_0_CSX6_0_Xo0(PropXbus_0, M6_UM6_0_CSX6_0_NotA); inv M6_UM6_0_CSX6_0_Xo1(in4526, M6_UM6_0_CSX6_0_NotB); nand2 M6_UM6_0_CSX6_0_Xo2(M6_UM6_0_CSX6_0_NotA, in4526, M6_UM6_0_CSX6_0_line2); nand2 M6_UM6_0_CSX6_0_Xo3(M6_UM6_0_CSX6_0_NotB, PropXbus_0, M6_UM6_0_CSX6_0_line3); nand2 M6_UM6_0_CSX6_0_Xo4(M6_UM6_0_CSX6_0_line2, M6_UM6_0_CSX6_0_line3, out373); inv M6_UM6_0_CSX6_1_Xo0(PropXbus_1, M6_UM6_0_CSX6_1_NotA); inv M6_UM6_0_CSX6_1_Xo1(CarryXbus_0, M6_UM6_0_CSX6_1_NotB); nand2 M6_UM6_0_CSX6_1_Xo2(M6_UM6_0_CSX6_1_NotA, CarryXbus_0, M6_UM6_0_CSX6_1_line2); nand2 M6_UM6_0_CSX6_1_Xo3(M6_UM6_0_CSX6_1_NotB, PropXbus_1, M6_UM6_0_CSX6_1_line3); nand2 M6_UM6_0_CSX6_1_Xo4(M6_UM6_0_CSX6_1_line2, M6_UM6_0_CSX6_1_line3, out397); inv M6_UM6_0_CSX6_2_Xo0(PropXbus_2, M6_UM6_0_CSX6_2_NotA); inv M6_UM6_0_CSX6_2_Xo1(CarryXbus_1, M6_UM6_0_CSX6_2_NotB); nand2 M6_UM6_0_CSX6_2_Xo2(M6_UM6_0_CSX6_2_NotA, CarryXbus_1, M6_UM6_0_CSX6_2_line2); nand2 M6_UM6_0_CSX6_2_Xo3(M6_UM6_0_CSX6_2_NotB, PropXbus_2, M6_UM6_0_CSX6_2_line3); nand2 M6_UM6_0_CSX6_2_Xo4(M6_UM6_0_CSX6_2_line2, M6_UM6_0_CSX6_2_line3, out394); inv M6_UM6_0_CSX6_3_Xo0(PropXbus_3, M6_UM6_0_CSX6_3_NotA); inv M6_UM6_0_CSX6_3_Xo1(CarryXbus_2, M6_UM6_0_CSX6_3_NotB); nand2 M6_UM6_0_CSX6_3_Xo2(M6_UM6_0_CSX6_3_NotA, CarryXbus_2, M6_UM6_0_CSX6_3_line2); nand2 M6_UM6_0_CSX6_3_Xo3(M6_UM6_0_CSX6_3_NotB, PropXbus_3, M6_UM6_0_CSX6_3_line3); nand2 M6_UM6_0_CSX6_3_Xo4(M6_UM6_0_CSX6_3_line2, M6_UM6_0_CSX6_3_line3, out391); inv M6_UM6_0_CSX6_4_Xo0(PropXbus_4, M6_UM6_0_CSX6_4_NotA); inv M6_UM6_0_CSX6_4_Xo1(CarryXbus_3, M6_UM6_0_CSX6_4_NotB); nand2 M6_UM6_0_CSX6_4_Xo2(M6_UM6_0_CSX6_4_NotA, CarryXbus_3, M6_UM6_0_CSX6_4_line2); nand2 M6_UM6_0_CSX6_4_Xo3(M6_UM6_0_CSX6_4_NotB, PropXbus_4, M6_UM6_0_CSX6_4_line3); nand2 M6_UM6_0_CSX6_4_Xo4(M6_UM6_0_CSX6_4_line2, M6_UM6_0_CSX6_4_line3, out388); inv M6_UM6_0_CSX6_5_Xo0(PropXbus_5, M6_UM6_0_CSX6_5_NotA); inv M6_UM6_0_CSX6_5_Xo1(CarryXbus_4, M6_UM6_0_CSX6_5_NotB); nand2 M6_UM6_0_CSX6_5_Xo2(M6_UM6_0_CSX6_5_NotA, CarryXbus_4, M6_UM6_0_CSX6_5_line2); nand2 M6_UM6_0_CSX6_5_Xo3(M6_UM6_0_CSX6_5_NotB, PropXbus_5, M6_UM6_0_CSX6_5_line3); nand2 M6_UM6_0_CSX6_5_Xo4(M6_UM6_0_CSX6_5_line2, M6_UM6_0_CSX6_5_line3, out385); inv M6_UM6_1_CSM4_0_Xo0(PropXbus_6, M6_UM6_1_CSM4_0_NotA); inv M6_UM6_1_CSM4_0_Xo1(M5_GenXbus_5, M6_UM6_1_CSM4_0_NotB); nand2 M6_UM6_1_CSM4_0_Xo2(M6_UM6_1_CSM4_0_NotA, M5_GenXbus_5, M6_UM6_1_CSM4_0_line2); nand2 M6_UM6_1_CSM4_0_Xo3(M6_UM6_1_CSM4_0_NotB, PropXbus_6, M6_UM6_1_CSM4_0_line3); nand2 M6_UM6_1_CSM4_0_Xo4(M6_UM6_1_CSM4_0_line2, M6_UM6_1_CSM4_0_line3, M6_UM6_1_Sum0_0); inv M6_UM6_1_CSM4_1_Xo0(PropXbus_7, M6_UM6_1_CSM4_1_NotA); inv M6_UM6_1_CSM4_1_Xo1(LocalCarryXCin0_6, M6_UM6_1_CSM4_1_NotB); nand2 M6_UM6_1_CSM4_1_Xo2(M6_UM6_1_CSM4_1_NotA, LocalCarryXCin0_6, M6_UM6_1_CSM4_1_line2); nand2 M6_UM6_1_CSM4_1_Xo3(M6_UM6_1_CSM4_1_NotB, PropXbus_7, M6_UM6_1_CSM4_1_line3); nand2 M6_UM6_1_CSM4_1_Xo4(M6_UM6_1_CSM4_1_line2, M6_UM6_1_CSM4_1_line3, M6_UM6_1_Sum0_1); inv M6_UM6_1_CSM4_2_Xo0(PropXbus_8, M6_UM6_1_CSM4_2_NotA); inv M6_UM6_1_CSM4_2_Xo1(LocalCarryXCin0_7, M6_UM6_1_CSM4_2_NotB); nand2 M6_UM6_1_CSM4_2_Xo2(M6_UM6_1_CSM4_2_NotA, LocalCarryXCin0_7, M6_UM6_1_CSM4_2_line2); nand2 M6_UM6_1_CSM4_2_Xo3(M6_UM6_1_CSM4_2_NotB, PropXbus_8, M6_UM6_1_CSM4_2_line3); nand2 M6_UM6_1_CSM4_2_Xo4(M6_UM6_1_CSM4_2_line2, M6_UM6_1_CSM4_2_line3, M6_UM6_1_Sum0_2); inv M6_UM6_1_CSM4_3_Xo0(PropXbus_6, M6_UM6_1_CSM4_3_NotA); inv M6_UM6_1_CSM4_3_Xo1(LocalCarryXCin1_5, M6_UM6_1_CSM4_3_NotB); nand2 M6_UM6_1_CSM4_3_Xo2(M6_UM6_1_CSM4_3_NotA, LocalCarryXCin1_5, M6_UM6_1_CSM4_3_line2); nand2 M6_UM6_1_CSM4_3_Xo3(M6_UM6_1_CSM4_3_NotB, PropXbus_6, M6_UM6_1_CSM4_3_line3); nand2 M6_UM6_1_CSM4_3_Xo4(M6_UM6_1_CSM4_3_line2, M6_UM6_1_CSM4_3_line3, M6_UM6_1_Sum1_0); inv M6_UM6_1_CSM4_4_Xo0(PropXbus_7, M6_UM6_1_CSM4_4_NotA); inv M6_UM6_1_CSM4_4_Xo1(LocalCarryXCin1_6, M6_UM6_1_CSM4_4_NotB); nand2 M6_UM6_1_CSM4_4_Xo2(M6_UM6_1_CSM4_4_NotA, LocalCarryXCin1_6, M6_UM6_1_CSM4_4_line2); nand2 M6_UM6_1_CSM4_4_Xo3(M6_UM6_1_CSM4_4_NotB, PropXbus_7, M6_UM6_1_CSM4_4_line3); nand2 M6_UM6_1_CSM4_4_Xo4(M6_UM6_1_CSM4_4_line2, M6_UM6_1_CSM4_4_line3, M6_UM6_1_Sum1_1); inv M6_UM6_1_CSM4_5_Xo0(PropXbus_8, M6_UM6_1_CSM4_5_NotA); inv M6_UM6_1_CSM4_5_Xo1(LocalCarryXCin1_7, M6_UM6_1_CSM4_5_NotB); nand2 M6_UM6_1_CSM4_5_Xo2(M6_UM6_1_CSM4_5_NotA, LocalCarryXCin1_7, M6_UM6_1_CSM4_5_line2); nand2 M6_UM6_1_CSM4_5_Xo3(M6_UM6_1_CSM4_5_NotB, PropXbus_8, M6_UM6_1_CSM4_5_line3); nand2 M6_UM6_1_CSM4_5_Xo4(M6_UM6_1_CSM4_5_line2, M6_UM6_1_CSM4_5_line3, M6_UM6_1_Sum1_2); inv M6_UM6_1_CSM4_6_Mux0(CarryXbus_4, M6_UM6_1_CSM4_6_Not_ContIn); and2 M6_UM6_1_CSM4_6_Mux1(M6_UM6_1_Sum0_0, M6_UM6_1_CSM4_6_Not_ContIn, M6_UM6_1_CSM4_6_line1); and2 M6_UM6_1_CSM4_6_Mux2(M6_UM6_1_Sum1_0, CarryXbus_4, M6_UM6_1_CSM4_6_line2); or2 M6_UM6_1_CSM4_6_Mux3(M6_UM6_1_CSM4_6_line1, M6_UM6_1_CSM4_6_line2, out382); inv M6_UM6_1_CSM4_7_Mux0(CarryXbus_4, M6_UM6_1_CSM4_7_Not_ContIn); and2 M6_UM6_1_CSM4_7_Mux1(M6_UM6_1_Sum0_1, M6_UM6_1_CSM4_7_Not_ContIn, M6_UM6_1_CSM4_7_line1); and2 M6_UM6_1_CSM4_7_Mux2(M6_UM6_1_Sum1_1, CarryXbus_4, M6_UM6_1_CSM4_7_line2); or2 M6_UM6_1_CSM4_7_Mux3(M6_UM6_1_CSM4_7_line1, M6_UM6_1_CSM4_7_line2, out379); inv M6_UM6_1_CSM4_8_Mux0(CarryXbus_4, M6_UM6_1_CSM4_8_Not_ContIn); and2 M6_UM6_1_CSM4_8_Mux1(M6_UM6_1_Sum0_2, M6_UM6_1_CSM4_8_Not_ContIn, M6_UM6_1_CSM4_8_line1); and2 M6_UM6_1_CSM4_8_Mux2(M6_UM6_1_Sum1_2, CarryXbus_4, M6_UM6_1_CSM4_8_line2); or2 M6_UM6_1_CSM4_8_Mux3(M6_UM6_1_CSM4_8_line1, M6_UM6_1_CSM4_8_line2, out376); inv M6_UM6_2_CSX6_0_Xo0(PropXbus_9, M6_UM6_2_CSX6_0_NotA); inv M6_UM6_2_CSX6_0_Xo1(CarryXbus_8, M6_UM6_2_CSX6_0_NotB); nand2 M6_UM6_2_CSX6_0_Xo2(M6_UM6_2_CSX6_0_NotA, CarryXbus_8, M6_UM6_2_CSX6_0_line2); nand2 M6_UM6_2_CSX6_0_Xo3(M6_UM6_2_CSX6_0_NotB, PropXbus_9, M6_UM6_2_CSX6_0_line3); nand2 M6_UM6_2_CSX6_0_Xo4(M6_UM6_2_CSX6_0_line2, M6_UM6_2_CSX6_0_line3, out344); inv M6_UM6_2_CSX6_1_Xo0(PropXbus_10, M6_UM6_2_CSX6_1_NotA); inv M6_UM6_2_CSX6_1_Xo1(CarryXbus_9, M6_UM6_2_CSX6_1_NotB); nand2 M6_UM6_2_CSX6_1_Xo2(M6_UM6_2_CSX6_1_NotA, CarryXbus_9, M6_UM6_2_CSX6_1_line2); nand2 M6_UM6_2_CSX6_1_Xo3(M6_UM6_2_CSX6_1_NotB, PropXbus_10, M6_UM6_2_CSX6_1_line3); nand2 M6_UM6_2_CSX6_1_Xo4(M6_UM6_2_CSX6_1_line2, M6_UM6_2_CSX6_1_line3, out368); inv M6_UM6_2_CSX6_2_Xo0(PropXbus_11, M6_UM6_2_CSX6_2_NotA); inv M6_UM6_2_CSX6_2_Xo1(CarryXbus_10, M6_UM6_2_CSX6_2_NotB); nand2 M6_UM6_2_CSX6_2_Xo2(M6_UM6_2_CSX6_2_NotA, CarryXbus_10, M6_UM6_2_CSX6_2_line2); nand2 M6_UM6_2_CSX6_2_Xo3(M6_UM6_2_CSX6_2_NotB, PropXbus_11, M6_UM6_2_CSX6_2_line3); nand2 M6_UM6_2_CSX6_2_Xo4(M6_UM6_2_CSX6_2_line2, M6_UM6_2_CSX6_2_line3, out365); inv M6_UM6_2_CSX6_3_Xo0(PropXbus_12, M6_UM6_2_CSX6_3_NotA); inv M6_UM6_2_CSX6_3_Xo1(CarryXbus_11, M6_UM6_2_CSX6_3_NotB); nand2 M6_UM6_2_CSX6_3_Xo2(M6_UM6_2_CSX6_3_NotA, CarryXbus_11, M6_UM6_2_CSX6_3_line2); nand2 M6_UM6_2_CSX6_3_Xo3(M6_UM6_2_CSX6_3_NotB, PropXbus_12, M6_UM6_2_CSX6_3_line3); nand2 M6_UM6_2_CSX6_3_Xo4(M6_UM6_2_CSX6_3_line2, M6_UM6_2_CSX6_3_line3, out362); inv M6_UM6_2_CSX6_4_Xo0(PropXbus_13, M6_UM6_2_CSX6_4_NotA); inv M6_UM6_2_CSX6_4_Xo1(CarryXbus_12, M6_UM6_2_CSX6_4_NotB); nand2 M6_UM6_2_CSX6_4_Xo2(M6_UM6_2_CSX6_4_NotA, CarryXbus_12, M6_UM6_2_CSX6_4_line2); nand2 M6_UM6_2_CSX6_4_Xo3(M6_UM6_2_CSX6_4_NotB, PropXbus_13, M6_UM6_2_CSX6_4_line3); nand2 M6_UM6_2_CSX6_4_Xo4(M6_UM6_2_CSX6_4_line2, M6_UM6_2_CSX6_4_line3, out359); inv M6_UM6_2_CSX6_5_Xo0(PropXbus_14, M6_UM6_2_CSX6_5_NotA); inv M6_UM6_2_CSX6_5_Xo1(CarryXbus_13, M6_UM6_2_CSX6_5_NotB); nand2 M6_UM6_2_CSX6_5_Xo2(M6_UM6_2_CSX6_5_NotA, CarryXbus_13, M6_UM6_2_CSX6_5_line2); nand2 M6_UM6_2_CSX6_5_Xo3(M6_UM6_2_CSX6_5_NotB, PropXbus_14, M6_UM6_2_CSX6_5_line3); nand2 M6_UM6_2_CSX6_5_Xo4(M6_UM6_2_CSX6_5_line2, M6_UM6_2_CSX6_5_line3, out356); inv M6_UM6_3_CSM4_0_Xo0(PropXbus_15, M6_UM6_3_CSM4_0_NotA); inv M6_UM6_3_CSM4_0_Xo1(M5_GenXbus_14, M6_UM6_3_CSM4_0_NotB); nand2 M6_UM6_3_CSM4_0_Xo2(M6_UM6_3_CSM4_0_NotA, M5_GenXbus_14, M6_UM6_3_CSM4_0_line2); nand2 M6_UM6_3_CSM4_0_Xo3(M6_UM6_3_CSM4_0_NotB, PropXbus_15, M6_UM6_3_CSM4_0_line3); nand2 M6_UM6_3_CSM4_0_Xo4(M6_UM6_3_CSM4_0_line2, M6_UM6_3_CSM4_0_line3, M6_UM6_3_Sum0_0); inv M6_UM6_3_CSM4_1_Xo0(PropXbus_16, M6_UM6_3_CSM4_1_NotA); inv M6_UM6_3_CSM4_1_Xo1(LocalCarryXCin0_15, M6_UM6_3_CSM4_1_NotB); nand2 M6_UM6_3_CSM4_1_Xo2(M6_UM6_3_CSM4_1_NotA, LocalCarryXCin0_15, M6_UM6_3_CSM4_1_line2); nand2 M6_UM6_3_CSM4_1_Xo3(M6_UM6_3_CSM4_1_NotB, PropXbus_16, M6_UM6_3_CSM4_1_line3); nand2 M6_UM6_3_CSM4_1_Xo4(M6_UM6_3_CSM4_1_line2, M6_UM6_3_CSM4_1_line3, M6_UM6_3_Sum0_1); inv M6_UM6_3_CSM4_2_Xo0(PropXbus_17, M6_UM6_3_CSM4_2_NotA); inv M6_UM6_3_CSM4_2_Xo1(LocalCarryXCin0_16, M6_UM6_3_CSM4_2_NotB); nand2 M6_UM6_3_CSM4_2_Xo2(M6_UM6_3_CSM4_2_NotA, LocalCarryXCin0_16, M6_UM6_3_CSM4_2_line2); nand2 M6_UM6_3_CSM4_2_Xo3(M6_UM6_3_CSM4_2_NotB, PropXbus_17, M6_UM6_3_CSM4_2_line3); nand2 M6_UM6_3_CSM4_2_Xo4(M6_UM6_3_CSM4_2_line2, M6_UM6_3_CSM4_2_line3, M6_UM6_3_Sum0_2); inv M6_UM6_3_CSM4_3_Xo0(PropXbus_15, M6_UM6_3_CSM4_3_NotA); inv M6_UM6_3_CSM4_3_Xo1(LocalCarryXCin1_14, M6_UM6_3_CSM4_3_NotB); nand2 M6_UM6_3_CSM4_3_Xo2(M6_UM6_3_CSM4_3_NotA, LocalCarryXCin1_14, M6_UM6_3_CSM4_3_line2); nand2 M6_UM6_3_CSM4_3_Xo3(M6_UM6_3_CSM4_3_NotB, PropXbus_15, M6_UM6_3_CSM4_3_line3); nand2 M6_UM6_3_CSM4_3_Xo4(M6_UM6_3_CSM4_3_line2, M6_UM6_3_CSM4_3_line3, M6_UM6_3_Sum1_0); inv M6_UM6_3_CSM4_4_Xo0(PropXbus_16, M6_UM6_3_CSM4_4_NotA); inv M6_UM6_3_CSM4_4_Xo1(LocalCarryXCin1_15, M6_UM6_3_CSM4_4_NotB); nand2 M6_UM6_3_CSM4_4_Xo2(M6_UM6_3_CSM4_4_NotA, LocalCarryXCin1_15, M6_UM6_3_CSM4_4_line2); nand2 M6_UM6_3_CSM4_4_Xo3(M6_UM6_3_CSM4_4_NotB, PropXbus_16, M6_UM6_3_CSM4_4_line3); nand2 M6_UM6_3_CSM4_4_Xo4(M6_UM6_3_CSM4_4_line2, M6_UM6_3_CSM4_4_line3, M6_UM6_3_Sum1_1); inv M6_UM6_3_CSM4_5_Xo0(PropXbus_17, M6_UM6_3_CSM4_5_NotA); inv M6_UM6_3_CSM4_5_Xo1(LocalCarryXCin1_16, M6_UM6_3_CSM4_5_NotB); nand2 M6_UM6_3_CSM4_5_Xo2(M6_UM6_3_CSM4_5_NotA, LocalCarryXCin1_16, M6_UM6_3_CSM4_5_line2); nand2 M6_UM6_3_CSM4_5_Xo3(M6_UM6_3_CSM4_5_NotB, PropXbus_17, M6_UM6_3_CSM4_5_line3); nand2 M6_UM6_3_CSM4_5_Xo4(M6_UM6_3_CSM4_5_line2, M6_UM6_3_CSM4_5_line3, M6_UM6_3_Sum1_2); inv M6_UM6_3_CSM4_6_Mux0(CarryXbus_13, M6_UM6_3_CSM4_6_Not_ContIn); and2 M6_UM6_3_CSM4_6_Mux1(M6_UM6_3_Sum0_0, M6_UM6_3_CSM4_6_Not_ContIn, M6_UM6_3_CSM4_6_line1); and2 M6_UM6_3_CSM4_6_Mux2(M6_UM6_3_Sum1_0, CarryXbus_13, M6_UM6_3_CSM4_6_line2); or2 M6_UM6_3_CSM4_6_Mux3(M6_UM6_3_CSM4_6_line1, M6_UM6_3_CSM4_6_line2, out353); inv M6_UM6_3_CSM4_7_Mux0(CarryXbus_13, M6_UM6_3_CSM4_7_Not_ContIn); and2 M6_UM6_3_CSM4_7_Mux1(M6_UM6_3_Sum0_1, M6_UM6_3_CSM4_7_Not_ContIn, M6_UM6_3_CSM4_7_line1); and2 M6_UM6_3_CSM4_7_Mux2(M6_UM6_3_Sum1_1, CarryXbus_13, M6_UM6_3_CSM4_7_line2); or2 M6_UM6_3_CSM4_7_Mux3(M6_UM6_3_CSM4_7_line1, M6_UM6_3_CSM4_7_line2, out350); inv M6_UM6_3_CSM4_8_Mux0(CarryXbus_13, M6_UM6_3_CSM4_8_Not_ContIn); and2 M6_UM6_3_CSM4_8_Mux1(M6_UM6_3_Sum0_2, M6_UM6_3_CSM4_8_Not_ContIn, M6_UM6_3_CSM4_8_line1); and2 M6_UM6_3_CSM4_8_Mux2(M6_UM6_3_Sum1_2, CarryXbus_13, M6_UM6_3_CSM4_8_line2); or2 M6_UM6_3_CSM4_8_Mux3(M6_UM6_3_CSM4_8_line1, M6_UM6_3_CSM4_8_line2, out347); inv M6_UM6_4_CSX6_0_Xo0(PropXbus_18, M6_UM6_4_CSX6_0_NotA); inv M6_UM6_4_CSX6_0_Xo1(CarryXbus_17, M6_UM6_4_CSX6_0_NotB); nand2 M6_UM6_4_CSX6_0_Xo2(M6_UM6_4_CSX6_0_NotA, CarryXbus_17, M6_UM6_4_CSX6_0_line2); nand2 M6_UM6_4_CSX6_0_Xo3(M6_UM6_4_CSX6_0_NotB, PropXbus_18, M6_UM6_4_CSX6_0_line3); nand2 M6_UM6_4_CSX6_0_Xo4(M6_UM6_4_CSX6_0_line2, M6_UM6_4_CSX6_0_line3, out295); inv M6_UM6_4_CSX6_1_Xo0(PropXbus_19, M6_UM6_4_CSX6_1_NotA); inv M6_UM6_4_CSX6_1_Xo1(CarryXbus_18, M6_UM6_4_CSX6_1_NotB); nand2 M6_UM6_4_CSX6_1_Xo2(M6_UM6_4_CSX6_1_NotA, CarryXbus_18, M6_UM6_4_CSX6_1_line2); nand2 M6_UM6_4_CSX6_1_Xo3(M6_UM6_4_CSX6_1_NotB, PropXbus_19, M6_UM6_4_CSX6_1_line3); nand2 M6_UM6_4_CSX6_1_Xo4(M6_UM6_4_CSX6_1_line2, M6_UM6_4_CSX6_1_line3, out319); inv M6_UM6_4_CSX6_2_Xo0(PropXbus_20, M6_UM6_4_CSX6_2_NotA); inv M6_UM6_4_CSX6_2_Xo1(CarryXbus_19, M6_UM6_4_CSX6_2_NotB); nand2 M6_UM6_4_CSX6_2_Xo2(M6_UM6_4_CSX6_2_NotA, CarryXbus_19, M6_UM6_4_CSX6_2_line2); nand2 M6_UM6_4_CSX6_2_Xo3(M6_UM6_4_CSX6_2_NotB, PropXbus_20, M6_UM6_4_CSX6_2_line3); nand2 M6_UM6_4_CSX6_2_Xo4(M6_UM6_4_CSX6_2_line2, M6_UM6_4_CSX6_2_line3, out316); inv M6_UM6_4_CSX6_3_Xo0(PropXbus_21, M6_UM6_4_CSX6_3_NotA); inv M6_UM6_4_CSX6_3_Xo1(CarryXbus_20, M6_UM6_4_CSX6_3_NotB); nand2 M6_UM6_4_CSX6_3_Xo2(M6_UM6_4_CSX6_3_NotA, CarryXbus_20, M6_UM6_4_CSX6_3_line2); nand2 M6_UM6_4_CSX6_3_Xo3(M6_UM6_4_CSX6_3_NotB, PropXbus_21, M6_UM6_4_CSX6_3_line3); nand2 M6_UM6_4_CSX6_3_Xo4(M6_UM6_4_CSX6_3_line2, M6_UM6_4_CSX6_3_line3, out313); inv M6_UM6_4_CSX6_4_Xo0(PropXbus_22, M6_UM6_4_CSX6_4_NotA); inv M6_UM6_4_CSX6_4_Xo1(CarryXbus_21, M6_UM6_4_CSX6_4_NotB); nand2 M6_UM6_4_CSX6_4_Xo2(M6_UM6_4_CSX6_4_NotA, CarryXbus_21, M6_UM6_4_CSX6_4_line2); nand2 M6_UM6_4_CSX6_4_Xo3(M6_UM6_4_CSX6_4_NotB, PropXbus_22, M6_UM6_4_CSX6_4_line3); nand2 M6_UM6_4_CSX6_4_Xo4(M6_UM6_4_CSX6_4_line2, M6_UM6_4_CSX6_4_line3, out310); inv M6_UM6_4_CSX6_5_Xo0(PropXbus_23, M6_UM6_4_CSX6_5_NotA); inv M6_UM6_4_CSX6_5_Xo1(CarryXbus_22, M6_UM6_4_CSX6_5_NotB); nand2 M6_UM6_4_CSX6_5_Xo2(M6_UM6_4_CSX6_5_NotA, CarryXbus_22, M6_UM6_4_CSX6_5_line2); nand2 M6_UM6_4_CSX6_5_Xo3(M6_UM6_4_CSX6_5_NotB, PropXbus_23, M6_UM6_4_CSX6_5_line3); nand2 M6_UM6_4_CSX6_5_Xo4(M6_UM6_4_CSX6_5_line2, M6_UM6_4_CSX6_5_line3, out307); inv M6_UM6_5_CSM4_0_Xo0(PropXbus_24, M6_UM6_5_CSM4_0_NotA); inv M6_UM6_5_CSM4_0_Xo1(M5_GenXbus_23, M6_UM6_5_CSM4_0_NotB); nand2 M6_UM6_5_CSM4_0_Xo2(M6_UM6_5_CSM4_0_NotA, M5_GenXbus_23, M6_UM6_5_CSM4_0_line2); nand2 M6_UM6_5_CSM4_0_Xo3(M6_UM6_5_CSM4_0_NotB, PropXbus_24, M6_UM6_5_CSM4_0_line3); nand2 M6_UM6_5_CSM4_0_Xo4(M6_UM6_5_CSM4_0_line2, M6_UM6_5_CSM4_0_line3, M6_UM6_5_Sum0_0); inv M6_UM6_5_CSM4_1_Xo0(PropXbus_25, M6_UM6_5_CSM4_1_NotA); inv M6_UM6_5_CSM4_1_Xo1(LocalCarryXCin0_24, M6_UM6_5_CSM4_1_NotB); nand2 M6_UM6_5_CSM4_1_Xo2(M6_UM6_5_CSM4_1_NotA, LocalCarryXCin0_24, M6_UM6_5_CSM4_1_line2); nand2 M6_UM6_5_CSM4_1_Xo3(M6_UM6_5_CSM4_1_NotB, PropXbus_25, M6_UM6_5_CSM4_1_line3); nand2 M6_UM6_5_CSM4_1_Xo4(M6_UM6_5_CSM4_1_line2, M6_UM6_5_CSM4_1_line3, M6_UM6_5_Sum0_1); inv M6_UM6_5_CSM4_2_Xo0(PropXbus_26, M6_UM6_5_CSM4_2_NotA); inv M6_UM6_5_CSM4_2_Xo1(LocalCarryXCin0_25, M6_UM6_5_CSM4_2_NotB); nand2 M6_UM6_5_CSM4_2_Xo2(M6_UM6_5_CSM4_2_NotA, LocalCarryXCin0_25, M6_UM6_5_CSM4_2_line2); nand2 M6_UM6_5_CSM4_2_Xo3(M6_UM6_5_CSM4_2_NotB, PropXbus_26, M6_UM6_5_CSM4_2_line3); nand2 M6_UM6_5_CSM4_2_Xo4(M6_UM6_5_CSM4_2_line2, M6_UM6_5_CSM4_2_line3, M6_UM6_5_Sum0_2); inv M6_UM6_5_CSM4_3_Xo0(PropXbus_24, M6_UM6_5_CSM4_3_NotA); inv M6_UM6_5_CSM4_3_Xo1(LocalCarryXCin1_23, M6_UM6_5_CSM4_3_NotB); nand2 M6_UM6_5_CSM4_3_Xo2(M6_UM6_5_CSM4_3_NotA, LocalCarryXCin1_23, M6_UM6_5_CSM4_3_line2); nand2 M6_UM6_5_CSM4_3_Xo3(M6_UM6_5_CSM4_3_NotB, PropXbus_24, M6_UM6_5_CSM4_3_line3); nand2 M6_UM6_5_CSM4_3_Xo4(M6_UM6_5_CSM4_3_line2, M6_UM6_5_CSM4_3_line3, M6_UM6_5_Sum1_0); inv M6_UM6_5_CSM4_4_Xo0(PropXbus_25, M6_UM6_5_CSM4_4_NotA); inv M6_UM6_5_CSM4_4_Xo1(LocalCarryXCin1_24, M6_UM6_5_CSM4_4_NotB); nand2 M6_UM6_5_CSM4_4_Xo2(M6_UM6_5_CSM4_4_NotA, LocalCarryXCin1_24, M6_UM6_5_CSM4_4_line2); nand2 M6_UM6_5_CSM4_4_Xo3(M6_UM6_5_CSM4_4_NotB, PropXbus_25, M6_UM6_5_CSM4_4_line3); nand2 M6_UM6_5_CSM4_4_Xo4(M6_UM6_5_CSM4_4_line2, M6_UM6_5_CSM4_4_line3, M6_UM6_5_Sum1_1); inv M6_UM6_5_CSM4_5_Xo0(PropXbus_26, M6_UM6_5_CSM4_5_NotA); inv M6_UM6_5_CSM4_5_Xo1(LocalCarryXCin1_25, M6_UM6_5_CSM4_5_NotB); nand2 M6_UM6_5_CSM4_5_Xo2(M6_UM6_5_CSM4_5_NotA, LocalCarryXCin1_25, M6_UM6_5_CSM4_5_line2); nand2 M6_UM6_5_CSM4_5_Xo3(M6_UM6_5_CSM4_5_NotB, PropXbus_26, M6_UM6_5_CSM4_5_line3); nand2 M6_UM6_5_CSM4_5_Xo4(M6_UM6_5_CSM4_5_line2, M6_UM6_5_CSM4_5_line3, M6_UM6_5_Sum1_2); inv M6_UM6_5_CSM4_6_Mux0(CarryXbus_22, M6_UM6_5_CSM4_6_Not_ContIn); and2 M6_UM6_5_CSM4_6_Mux1(M6_UM6_5_Sum0_0, M6_UM6_5_CSM4_6_Not_ContIn, M6_UM6_5_CSM4_6_line1); and2 M6_UM6_5_CSM4_6_Mux2(M6_UM6_5_Sum1_0, CarryXbus_22, M6_UM6_5_CSM4_6_line2); or2 M6_UM6_5_CSM4_6_Mux3(M6_UM6_5_CSM4_6_line1, M6_UM6_5_CSM4_6_line2, out304); inv M6_UM6_5_CSM4_7_Mux0(CarryXbus_22, M6_UM6_5_CSM4_7_Not_ContIn); and2 M6_UM6_5_CSM4_7_Mux1(M6_UM6_5_Sum0_1, M6_UM6_5_CSM4_7_Not_ContIn, M6_UM6_5_CSM4_7_line1); and2 M6_UM6_5_CSM4_7_Mux2(M6_UM6_5_Sum1_1, CarryXbus_22, M6_UM6_5_CSM4_7_line2); or2 M6_UM6_5_CSM4_7_Mux3(M6_UM6_5_CSM4_7_line1, M6_UM6_5_CSM4_7_line2, out301); inv M6_UM6_5_CSM4_8_Mux0(CarryXbus_22, M6_UM6_5_CSM4_8_Not_ContIn); and2 M6_UM6_5_CSM4_8_Mux1(M6_UM6_5_Sum0_2, M6_UM6_5_CSM4_8_Not_ContIn, M6_UM6_5_CSM4_8_line1); and2 M6_UM6_5_CSM4_8_Mux2(M6_UM6_5_Sum1_2, CarryXbus_22, M6_UM6_5_CSM4_8_line2); or2 M6_UM6_5_CSM4_8_Mux3(M6_UM6_5_CSM4_8_line1, M6_UM6_5_CSM4_8_line2, out298); inv M6_UM6_6_CSX6_0_Xo0(PropXbus_27, M6_UM6_6_CSX6_0_NotA); inv M6_UM6_6_CSX6_0_Xo1(CarryXbus_26, M6_UM6_6_CSX6_0_NotB); nand2 M6_UM6_6_CSX6_0_Xo2(M6_UM6_6_CSX6_0_NotA, CarryXbus_26, M6_UM6_6_CSX6_0_line2); nand2 M6_UM6_6_CSX6_0_Xo3(M6_UM6_6_CSX6_0_NotB, PropXbus_27, M6_UM6_6_CSX6_0_line3); nand2 M6_UM6_6_CSX6_0_Xo4(M6_UM6_6_CSX6_0_line2, M6_UM6_6_CSX6_0_line3, out324); inv M6_UM6_6_CSX6_1_Xo0(PropXbus_28, M6_UM6_6_CSX6_1_NotA); inv M6_UM6_6_CSX6_1_Xo1(CarryXbus_27, M6_UM6_6_CSX6_1_NotB); nand2 M6_UM6_6_CSX6_1_Xo2(M6_UM6_6_CSX6_1_NotA, CarryXbus_27, M6_UM6_6_CSX6_1_line2); nand2 M6_UM6_6_CSX6_1_Xo3(M6_UM6_6_CSX6_1_NotB, PropXbus_28, M6_UM6_6_CSX6_1_line3); nand2 M6_UM6_6_CSX6_1_Xo4(M6_UM6_6_CSX6_1_line2, M6_UM6_6_CSX6_1_line3, out336); inv M6_UM6_6_CSX6_2_Xo0(PropXbus_29, M6_UM6_6_CSX6_2_NotA); inv M6_UM6_6_CSX6_2_Xo1(CarryXbus_28, M6_UM6_6_CSX6_2_NotB); nand2 M6_UM6_6_CSX6_2_Xo2(M6_UM6_6_CSX6_2_NotA, CarryXbus_28, M6_UM6_6_CSX6_2_line2); nand2 M6_UM6_6_CSX6_2_Xo3(M6_UM6_6_CSX6_2_NotB, PropXbus_29, M6_UM6_6_CSX6_2_line3); nand2 M6_UM6_6_CSX6_2_Xo4(M6_UM6_6_CSX6_2_line2, M6_UM6_6_CSX6_2_line3, out333); inv M6_UM6_6_CSX6_3_Xo0(PropXbus_30, M6_UM6_6_CSX6_3_NotA); inv M6_UM6_6_CSX6_3_Xo1(CarryXbus_29, M6_UM6_6_CSX6_3_NotB); nand2 M6_UM6_6_CSX6_3_Xo2(M6_UM6_6_CSX6_3_NotA, CarryXbus_29, M6_UM6_6_CSX6_3_line2); nand2 M6_UM6_6_CSX6_3_Xo3(M6_UM6_6_CSX6_3_NotB, PropXbus_30, M6_UM6_6_CSX6_3_line3); nand2 M6_UM6_6_CSX6_3_Xo4(M6_UM6_6_CSX6_3_line2, M6_UM6_6_CSX6_3_line3, out330); inv M6_UM6_6_CSX6_4_Xo0(PropXbus_31, M6_UM6_6_CSX6_4_NotA); inv M6_UM6_6_CSX6_4_Xo1(CarryXbus_30, M6_UM6_6_CSX6_4_NotB); nand2 M6_UM6_6_CSX6_4_Xo2(M6_UM6_6_CSX6_4_NotA, CarryXbus_30, M6_UM6_6_CSX6_4_line2); nand2 M6_UM6_6_CSX6_4_Xo3(M6_UM6_6_CSX6_4_NotB, PropXbus_31, M6_UM6_6_CSX6_4_line3); nand2 M6_UM6_6_CSX6_4_Xo4(M6_UM6_6_CSX6_4_line2, M6_UM6_6_CSX6_4_line3, out327); inv M6_UM6_6_CSX6_5_Xo0(PropXbus_32, M6_UM6_6_CSX6_5_NotA); inv M6_UM6_6_CSX6_5_Xo1(CarryXbus_31, M6_UM6_6_CSX6_5_NotB); nand2 M6_UM6_6_CSX6_5_Xo2(M6_UM6_6_CSX6_5_NotA, CarryXbus_31, M6_UM6_6_CSX6_5_line2); nand2 M6_UM6_6_CSX6_5_Xo3(M6_UM6_6_CSX6_5_NotB, PropXbus_32, M6_UM6_6_CSX6_5_line3); nand2 M6_UM6_6_CSX6_5_Xo4(M6_UM6_6_CSX6_5_line2, M6_UM6_6_CSX6_5_line3, out471); inv M6_UM6_7_Xo0(PropXbus_33, M6_UM6_7_NotA); inv M6_UM6_7_Xo1(M5_GenXbus_32, M6_UM6_7_NotB); nand2 M6_UM6_7_Xo2(M6_UM6_7_NotA, M5_GenXbus_32, M6_UM6_7_line2); nand2 M6_UM6_7_Xo3(M6_UM6_7_NotB, PropXbus_33, M6_UM6_7_line3); nand2 M6_UM6_7_Xo4(M6_UM6_7_line2, M6_UM6_7_line3, M6_Sum33_0); inv M6_UM6_8_Xo0(PropXbus_33, M6_UM6_8_NotA); inv M6_UM6_8_Xo1(LocalCarryXCin1_32, M6_UM6_8_NotB); nand2 M6_UM6_8_Xo2(M6_UM6_8_NotA, LocalCarryXCin1_32, M6_UM6_8_line2); nand2 M6_UM6_8_Xo3(M6_UM6_8_NotB, PropXbus_33, M6_UM6_8_line3); nand2 M6_UM6_8_Xo4(M6_UM6_8_line2, M6_UM6_8_line3, M6_Sum33_1); inv M6_UM6_9_Mux0(CarryXbus_31, M6_UM6_9_Not_ContIn); and2 M6_UM6_9_Mux1(M6_Sum33_0, M6_UM6_9_Not_ContIn, M6_UM6_9_line1); and2 M6_UM6_9_Mux2(M6_Sum33_1, CarryXbus_31, M6_UM6_9_line2); or2 M6_UM6_9_Mux3(M6_UM6_9_line1, M6_UM6_9_line2, out469); inv M7_GSP0_SP9nc0_SP7nc0_Xo0(M5_GenXbus_0, M7_GSP0_SP9nc0_SP7nc0_NotA); inv M7_GSP0_SP9nc0_SP7nc0_Xo1(LocalCarryXCin0_1, M7_GSP0_SP9nc0_SP7nc0_NotB); nand2 M7_GSP0_SP9nc0_SP7nc0_Xo2(M7_GSP0_SP9nc0_SP7nc0_NotA, LocalCarryXCin0_1, M7_GSP0_SP9nc0_SP7nc0_line2); nand2 M7_GSP0_SP9nc0_SP7nc0_Xo3(M7_GSP0_SP9nc0_SP7nc0_NotB, M5_GenXbus_0, M7_GSP0_SP9nc0_SP7nc0_line3); nand2 M7_GSP0_SP9nc0_SP7nc0_Xo4(M7_GSP0_SP9nc0_SP7nc0_line2, M7_GSP0_SP9nc0_SP7nc0_line3, M7_GSP0_SP9nc0_line0); inv M7_GSP0_SP9nc0_SP7nc1_Xo0(LocalCarryXCin0_2, M7_GSP0_SP9nc0_SP7nc1_NotA); inv M7_GSP0_SP9nc0_SP7nc1_Xo1(M7_GSP0_SP9nc0_line0, M7_GSP0_SP9nc0_SP7nc1_NotB); nand2 M7_GSP0_SP9nc0_SP7nc1_Xo2(M7_GSP0_SP9nc0_SP7nc1_NotA, M7_GSP0_SP9nc0_line0, M7_GSP0_SP9nc0_SP7nc1_line2); nand2 M7_GSP0_SP9nc0_SP7nc1_Xo3(M7_GSP0_SP9nc0_SP7nc1_NotB, LocalCarryXCin0_2, M7_GSP0_SP9nc0_SP7nc1_line3); nand2 M7_GSP0_SP9nc0_SP7nc1_Xo4(M7_GSP0_SP9nc0_SP7nc1_line2, M7_GSP0_SP9nc0_SP7nc1_line3, M7_GSP0_SP9nc0_line1); inv M7_GSP0_SP9nc0_SP7nc2_Xo0(LocalCarryXCin0_3, M7_GSP0_SP9nc0_SP7nc2_NotA); inv M7_GSP0_SP9nc0_SP7nc2_Xo1(M7_GSP0_SP9nc0_line1, M7_GSP0_SP9nc0_SP7nc2_NotB); nand2 M7_GSP0_SP9nc0_SP7nc2_Xo2(M7_GSP0_SP9nc0_SP7nc2_NotA, M7_GSP0_SP9nc0_line1, M7_GSP0_SP9nc0_SP7nc2_line2); nand2 M7_GSP0_SP9nc0_SP7nc2_Xo3(M7_GSP0_SP9nc0_SP7nc2_NotB, LocalCarryXCin0_3, M7_GSP0_SP9nc0_SP7nc2_line3); nand2 M7_GSP0_SP9nc0_SP7nc2_Xo4(M7_GSP0_SP9nc0_SP7nc2_line2, M7_GSP0_SP9nc0_SP7nc2_line3, M7_GSP0_SP9nc0_line2); inv M7_GSP0_SP9nc0_SP7nc3_Xo0(PropXbus_0, M7_GSP0_SP9nc0_SP7nc3_NotA); inv M7_GSP0_SP9nc0_SP7nc3_Xo1(M7_GSP0_SP9nc0_line2, M7_GSP0_SP9nc0_SP7nc3_NotB); nand2 M7_GSP0_SP9nc0_SP7nc3_Xo2(M7_GSP0_SP9nc0_SP7nc3_NotA, M7_GSP0_SP9nc0_line2, M7_GSP0_SP9nc0_SP7nc3_line2); nand2 M7_GSP0_SP9nc0_SP7nc3_Xo3(M7_GSP0_SP9nc0_SP7nc3_NotB, PropXbus_0, M7_GSP0_SP9nc0_SP7nc3_line3); nand2 M7_GSP0_SP9nc0_SP7nc3_Xo4(M7_GSP0_SP9nc0_SP7nc3_line2, M7_GSP0_SP9nc0_SP7nc3_line3, M7_GSP0_SP9nc0_line3); inv M7_GSP0_SP9nc0_SP7nc4_Xo0(PropXbus_1, M7_GSP0_SP9nc0_SP7nc4_NotA); inv M7_GSP0_SP9nc0_SP7nc4_Xo1(M7_GSP0_SP9nc0_line3, M7_GSP0_SP9nc0_SP7nc4_NotB); nand2 M7_GSP0_SP9nc0_SP7nc4_Xo2(M7_GSP0_SP9nc0_SP7nc4_NotA, M7_GSP0_SP9nc0_line3, M7_GSP0_SP9nc0_SP7nc4_line2); nand2 M7_GSP0_SP9nc0_SP7nc4_Xo3(M7_GSP0_SP9nc0_SP7nc4_NotB, PropXbus_1, M7_GSP0_SP9nc0_SP7nc4_line3); nand2 M7_GSP0_SP9nc0_SP7nc4_Xo4(M7_GSP0_SP9nc0_SP7nc4_line2, M7_GSP0_SP9nc0_SP7nc4_line3, M7_GSP0_SP9nc0_line4); inv M7_GSP0_SP9nc0_SP7nc5_Xo0(PropXbus_2, M7_GSP0_SP9nc0_SP7nc5_NotA); inv M7_GSP0_SP9nc0_SP7nc5_Xo1(M7_GSP0_SP9nc0_line4, M7_GSP0_SP9nc0_SP7nc5_NotB); nand2 M7_GSP0_SP9nc0_SP7nc5_Xo2(M7_GSP0_SP9nc0_SP7nc5_NotA, M7_GSP0_SP9nc0_line4, M7_GSP0_SP9nc0_SP7nc5_line2); nand2 M7_GSP0_SP9nc0_SP7nc5_Xo3(M7_GSP0_SP9nc0_SP7nc5_NotB, PropXbus_2, M7_GSP0_SP9nc0_SP7nc5_line3); nand2 M7_GSP0_SP9nc0_SP7nc5_Xo4(M7_GSP0_SP9nc0_SP7nc5_line2, M7_GSP0_SP9nc0_SP7nc5_line3, M7_GSP0_line0); inv M7_GSP0_SP9nc1_Xo0(PropXbus_3, M7_GSP0_SP9nc1_NotA); inv M7_GSP0_SP9nc1_Xo1(M7_GSP0_line0, M7_GSP0_SP9nc1_NotB); nand2 M7_GSP0_SP9nc1_Xo2(M7_GSP0_SP9nc1_NotA, M7_GSP0_line0, M7_GSP0_SP9nc1_line2); nand2 M7_GSP0_SP9nc1_Xo3(M7_GSP0_SP9nc1_NotB, PropXbus_3, M7_GSP0_SP9nc1_line3); nand2 M7_GSP0_SP9nc1_Xo4(M7_GSP0_SP9nc1_line2, M7_GSP0_SP9nc1_line3, M7_GSP0_line1); inv M7_GSP0_SP9nc2_Xo0(PropXbus_4, M7_GSP0_SP9nc2_NotA); inv M7_GSP0_SP9nc2_Xo1(M7_GSP0_line1, M7_GSP0_SP9nc2_NotB); nand2 M7_GSP0_SP9nc2_Xo2(M7_GSP0_SP9nc2_NotA, M7_GSP0_line1, M7_GSP0_SP9nc2_line2); nand2 M7_GSP0_SP9nc2_Xo3(M7_GSP0_SP9nc2_NotB, PropXbus_4, M7_GSP0_SP9nc2_line3); nand2 M7_GSP0_SP9nc2_Xo4(M7_GSP0_SP9nc2_line2, M7_GSP0_SP9nc2_line3, M7_ParCin0b4_0); inv M7_GSP1_SP9nc0_SP7c0(PropXbus_2, M7_GSP1_SP9nc0_NewInbus_6); inv M7_GSP1_SP9nc0_SP7c2_SP7nc0_Xo0(LocalCarryXCin1_0, M7_GSP1_SP9nc0_SP7c2_SP7nc0_NotA); inv M7_GSP1_SP9nc0_SP7c2_SP7nc0_Xo1(LocalCarryXCin1_1, M7_GSP1_SP9nc0_SP7c2_SP7nc0_NotB); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc0_Xo2(M7_GSP1_SP9nc0_SP7c2_SP7nc0_NotA, LocalCarryXCin1_1, M7_GSP1_SP9nc0_SP7c2_SP7nc0_line2); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc0_Xo3(M7_GSP1_SP9nc0_SP7c2_SP7nc0_NotB, LocalCarryXCin1_0, M7_GSP1_SP9nc0_SP7c2_SP7nc0_line3); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc0_Xo4(M7_GSP1_SP9nc0_SP7c2_SP7nc0_line2, M7_GSP1_SP9nc0_SP7c2_SP7nc0_line3, M7_GSP1_SP9nc0_SP7c2_line0); inv M7_GSP1_SP9nc0_SP7c2_SP7nc1_Xo0(LocalCarryXCin1_2, M7_GSP1_SP9nc0_SP7c2_SP7nc1_NotA); inv M7_GSP1_SP9nc0_SP7c2_SP7nc1_Xo1(M7_GSP1_SP9nc0_SP7c2_line0, M7_GSP1_SP9nc0_SP7c2_SP7nc1_NotB); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc1_Xo2(M7_GSP1_SP9nc0_SP7c2_SP7nc1_NotA, M7_GSP1_SP9nc0_SP7c2_line0, M7_GSP1_SP9nc0_SP7c2_SP7nc1_line2); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc1_Xo3(M7_GSP1_SP9nc0_SP7c2_SP7nc1_NotB, LocalCarryXCin1_2, M7_GSP1_SP9nc0_SP7c2_SP7nc1_line3); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc1_Xo4(M7_GSP1_SP9nc0_SP7c2_SP7nc1_line2, M7_GSP1_SP9nc0_SP7c2_SP7nc1_line3, M7_GSP1_SP9nc0_SP7c2_line1); inv M7_GSP1_SP9nc0_SP7c2_SP7nc2_Xo0(LocalCarryXCin1_3, M7_GSP1_SP9nc0_SP7c2_SP7nc2_NotA); inv M7_GSP1_SP9nc0_SP7c2_SP7nc2_Xo1(M7_GSP1_SP9nc0_SP7c2_line1, M7_GSP1_SP9nc0_SP7c2_SP7nc2_NotB); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc2_Xo2(M7_GSP1_SP9nc0_SP7c2_SP7nc2_NotA, M7_GSP1_SP9nc0_SP7c2_line1, M7_GSP1_SP9nc0_SP7c2_SP7nc2_line2); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc2_Xo3(M7_GSP1_SP9nc0_SP7c2_SP7nc2_NotB, LocalCarryXCin1_3, M7_GSP1_SP9nc0_SP7c2_SP7nc2_line3); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc2_Xo4(M7_GSP1_SP9nc0_SP7c2_SP7nc2_line2, M7_GSP1_SP9nc0_SP7c2_SP7nc2_line3, M7_GSP1_SP9nc0_SP7c2_line2); inv M7_GSP1_SP9nc0_SP7c2_SP7nc3_Xo0(PropXbus_0, M7_GSP1_SP9nc0_SP7c2_SP7nc3_NotA); inv M7_GSP1_SP9nc0_SP7c2_SP7nc3_Xo1(M7_GSP1_SP9nc0_SP7c2_line2, M7_GSP1_SP9nc0_SP7c2_SP7nc3_NotB); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc3_Xo2(M7_GSP1_SP9nc0_SP7c2_SP7nc3_NotA, M7_GSP1_SP9nc0_SP7c2_line2, M7_GSP1_SP9nc0_SP7c2_SP7nc3_line2); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc3_Xo3(M7_GSP1_SP9nc0_SP7c2_SP7nc3_NotB, PropXbus_0, M7_GSP1_SP9nc0_SP7c2_SP7nc3_line3); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc3_Xo4(M7_GSP1_SP9nc0_SP7c2_SP7nc3_line2, M7_GSP1_SP9nc0_SP7c2_SP7nc3_line3, M7_GSP1_SP9nc0_SP7c2_line3); inv M7_GSP1_SP9nc0_SP7c2_SP7nc4_Xo0(PropXbus_1, M7_GSP1_SP9nc0_SP7c2_SP7nc4_NotA); inv M7_GSP1_SP9nc0_SP7c2_SP7nc4_Xo1(M7_GSP1_SP9nc0_SP7c2_line3, M7_GSP1_SP9nc0_SP7c2_SP7nc4_NotB); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc4_Xo2(M7_GSP1_SP9nc0_SP7c2_SP7nc4_NotA, M7_GSP1_SP9nc0_SP7c2_line3, M7_GSP1_SP9nc0_SP7c2_SP7nc4_line2); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc4_Xo3(M7_GSP1_SP9nc0_SP7c2_SP7nc4_NotB, PropXbus_1, M7_GSP1_SP9nc0_SP7c2_SP7nc4_line3); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc4_Xo4(M7_GSP1_SP9nc0_SP7c2_SP7nc4_line2, M7_GSP1_SP9nc0_SP7c2_SP7nc4_line3, M7_GSP1_SP9nc0_SP7c2_line4); inv M7_GSP1_SP9nc0_SP7c2_SP7nc5_Xo0(M7_GSP1_SP9nc0_NewInbus_6, M7_GSP1_SP9nc0_SP7c2_SP7nc5_NotA); inv M7_GSP1_SP9nc0_SP7c2_SP7nc5_Xo1(M7_GSP1_SP9nc0_SP7c2_line4, M7_GSP1_SP9nc0_SP7c2_SP7nc5_NotB); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc5_Xo2(M7_GSP1_SP9nc0_SP7c2_SP7nc5_NotA, M7_GSP1_SP9nc0_SP7c2_line4, M7_GSP1_SP9nc0_SP7c2_SP7nc5_line2); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc5_Xo3(M7_GSP1_SP9nc0_SP7c2_SP7nc5_NotB, M7_GSP1_SP9nc0_NewInbus_6, M7_GSP1_SP9nc0_SP7c2_SP7nc5_line3); nand2 M7_GSP1_SP9nc0_SP7c2_SP7nc5_Xo4(M7_GSP1_SP9nc0_SP7c2_SP7nc5_line2, M7_GSP1_SP9nc0_SP7c2_SP7nc5_line3, M7_GSP1_line0); inv M7_GSP1_SP9nc1_Xo0(PropXbus_3, M7_GSP1_SP9nc1_NotA); inv M7_GSP1_SP9nc1_Xo1(M7_GSP1_line0, M7_GSP1_SP9nc1_NotB); nand2 M7_GSP1_SP9nc1_Xo2(M7_GSP1_SP9nc1_NotA, M7_GSP1_line0, M7_GSP1_SP9nc1_line2); nand2 M7_GSP1_SP9nc1_Xo3(M7_GSP1_SP9nc1_NotB, PropXbus_3, M7_GSP1_SP9nc1_line3); nand2 M7_GSP1_SP9nc1_Xo4(M7_GSP1_SP9nc1_line2, M7_GSP1_SP9nc1_line3, M7_GSP1_line1); inv M7_GSP1_SP9nc2_Xo0(PropXbus_4, M7_GSP1_SP9nc2_NotA); inv M7_GSP1_SP9nc2_Xo1(M7_GSP1_line1, M7_GSP1_SP9nc2_NotB); nand2 M7_GSP1_SP9nc2_Xo2(M7_GSP1_SP9nc2_NotA, M7_GSP1_line1, M7_GSP1_SP9nc2_line2); nand2 M7_GSP1_SP9nc2_Xo3(M7_GSP1_SP9nc2_NotB, PropXbus_4, M7_GSP1_SP9nc2_line3); nand2 M7_GSP1_SP9nc2_Xo4(M7_GSP1_SP9nc2_line2, M7_GSP1_SP9nc2_line3, M7_ParCin1b4_0); inv M7_GSP2_SP7nc0_Xo0(M5_GenXbus_5, M7_GSP2_SP7nc0_NotA); inv M7_GSP2_SP7nc0_Xo1(LocalCarryXCin0_6, M7_GSP2_SP7nc0_NotB); nand2 M7_GSP2_SP7nc0_Xo2(M7_GSP2_SP7nc0_NotA, LocalCarryXCin0_6, M7_GSP2_SP7nc0_line2); nand2 M7_GSP2_SP7nc0_Xo3(M7_GSP2_SP7nc0_NotB, M5_GenXbus_5, M7_GSP2_SP7nc0_line3); nand2 M7_GSP2_SP7nc0_Xo4(M7_GSP2_SP7nc0_line2, M7_GSP2_SP7nc0_line3, M7_GSP2_line0); inv M7_GSP2_SP7nc1_Xo0(LocalCarryXCin0_7, M7_GSP2_SP7nc1_NotA); inv M7_GSP2_SP7nc1_Xo1(M7_GSP2_line0, M7_GSP2_SP7nc1_NotB); nand2 M7_GSP2_SP7nc1_Xo2(M7_GSP2_SP7nc1_NotA, M7_GSP2_line0, M7_GSP2_SP7nc1_line2); nand2 M7_GSP2_SP7nc1_Xo3(M7_GSP2_SP7nc1_NotB, LocalCarryXCin0_7, M7_GSP2_SP7nc1_line3); nand2 M7_GSP2_SP7nc1_Xo4(M7_GSP2_SP7nc1_line2, M7_GSP2_SP7nc1_line3, M7_GSP2_line1); inv M7_GSP2_SP7nc2_Xo0(PropXbus_5, M7_GSP2_SP7nc2_NotA); inv M7_GSP2_SP7nc2_Xo1(M7_GSP2_line1, M7_GSP2_SP7nc2_NotB); nand2 M7_GSP2_SP7nc2_Xo2(M7_GSP2_SP7nc2_NotA, M7_GSP2_line1, M7_GSP2_SP7nc2_line2); nand2 M7_GSP2_SP7nc2_Xo3(M7_GSP2_SP7nc2_NotB, PropXbus_5, M7_GSP2_SP7nc2_line3); nand2 M7_GSP2_SP7nc2_Xo4(M7_GSP2_SP7nc2_line2, M7_GSP2_SP7nc2_line3, M7_GSP2_line2); inv M7_GSP2_SP7nc3_Xo0(PropXbus_6, M7_GSP2_SP7nc3_NotA); inv M7_GSP2_SP7nc3_Xo1(M7_GSP2_line2, M7_GSP2_SP7nc3_NotB); nand2 M7_GSP2_SP7nc3_Xo2(M7_GSP2_SP7nc3_NotA, M7_GSP2_line2, M7_GSP2_SP7nc3_line2); nand2 M7_GSP2_SP7nc3_Xo3(M7_GSP2_SP7nc3_NotB, PropXbus_6, M7_GSP2_SP7nc3_line3); nand2 M7_GSP2_SP7nc3_Xo4(M7_GSP2_SP7nc3_line2, M7_GSP2_SP7nc3_line3, M7_GSP2_line3); inv M7_GSP2_SP7nc4_Xo0(PropXbus_7, M7_GSP2_SP7nc4_NotA); inv M7_GSP2_SP7nc4_Xo1(M7_GSP2_line3, M7_GSP2_SP7nc4_NotB); nand2 M7_GSP2_SP7nc4_Xo2(M7_GSP2_SP7nc4_NotA, M7_GSP2_line3, M7_GSP2_SP7nc4_line2); nand2 M7_GSP2_SP7nc4_Xo3(M7_GSP2_SP7nc4_NotB, PropXbus_7, M7_GSP2_SP7nc4_line3); nand2 M7_GSP2_SP7nc4_Xo4(M7_GSP2_SP7nc4_line2, M7_GSP2_SP7nc4_line3, M7_GSP2_line4); inv M7_GSP2_SP7nc5_Xo0(PropXbus_8, M7_GSP2_SP7nc5_NotA); inv M7_GSP2_SP7nc5_Xo1(M7_GSP2_line4, M7_GSP2_SP7nc5_NotB); nand2 M7_GSP2_SP7nc5_Xo2(M7_GSP2_SP7nc5_NotA, M7_GSP2_line4, M7_GSP2_SP7nc5_line2); nand2 M7_GSP2_SP7nc5_Xo3(M7_GSP2_SP7nc5_NotB, PropXbus_8, M7_GSP2_SP7nc5_line3); nand2 M7_GSP2_SP7nc5_Xo4(M7_GSP2_SP7nc5_line2, M7_GSP2_SP7nc5_line3, M7_ParCin0b8_5); inv M7_GSP3_SP7c0(PropXbus_8, M7_GSP3_NewInbus_6); inv M7_GSP3_SP7c2_SP7nc0_Xo0(LocalCarryXCin1_5, M7_GSP3_SP7c2_SP7nc0_NotA); inv M7_GSP3_SP7c2_SP7nc0_Xo1(LocalCarryXCin1_6, M7_GSP3_SP7c2_SP7nc0_NotB); nand2 M7_GSP3_SP7c2_SP7nc0_Xo2(M7_GSP3_SP7c2_SP7nc0_NotA, LocalCarryXCin1_6, M7_GSP3_SP7c2_SP7nc0_line2); nand2 M7_GSP3_SP7c2_SP7nc0_Xo3(M7_GSP3_SP7c2_SP7nc0_NotB, LocalCarryXCin1_5, M7_GSP3_SP7c2_SP7nc0_line3); nand2 M7_GSP3_SP7c2_SP7nc0_Xo4(M7_GSP3_SP7c2_SP7nc0_line2, M7_GSP3_SP7c2_SP7nc0_line3, M7_GSP3_SP7c2_line0); inv M7_GSP3_SP7c2_SP7nc1_Xo0(LocalCarryXCin1_7, M7_GSP3_SP7c2_SP7nc1_NotA); inv M7_GSP3_SP7c2_SP7nc1_Xo1(M7_GSP3_SP7c2_line0, M7_GSP3_SP7c2_SP7nc1_NotB); nand2 M7_GSP3_SP7c2_SP7nc1_Xo2(M7_GSP3_SP7c2_SP7nc1_NotA, M7_GSP3_SP7c2_line0, M7_GSP3_SP7c2_SP7nc1_line2); nand2 M7_GSP3_SP7c2_SP7nc1_Xo3(M7_GSP3_SP7c2_SP7nc1_NotB, LocalCarryXCin1_7, M7_GSP3_SP7c2_SP7nc1_line3); nand2 M7_GSP3_SP7c2_SP7nc1_Xo4(M7_GSP3_SP7c2_SP7nc1_line2, M7_GSP3_SP7c2_SP7nc1_line3, M7_GSP3_SP7c2_line1); inv M7_GSP3_SP7c2_SP7nc2_Xo0(PropXbus_5, M7_GSP3_SP7c2_SP7nc2_NotA); inv M7_GSP3_SP7c2_SP7nc2_Xo1(M7_GSP3_SP7c2_line1, M7_GSP3_SP7c2_SP7nc2_NotB); nand2 M7_GSP3_SP7c2_SP7nc2_Xo2(M7_GSP3_SP7c2_SP7nc2_NotA, M7_GSP3_SP7c2_line1, M7_GSP3_SP7c2_SP7nc2_line2); nand2 M7_GSP3_SP7c2_SP7nc2_Xo3(M7_GSP3_SP7c2_SP7nc2_NotB, PropXbus_5, M7_GSP3_SP7c2_SP7nc2_line3); nand2 M7_GSP3_SP7c2_SP7nc2_Xo4(M7_GSP3_SP7c2_SP7nc2_line2, M7_GSP3_SP7c2_SP7nc2_line3, M7_GSP3_SP7c2_line2); inv M7_GSP3_SP7c2_SP7nc3_Xo0(PropXbus_6, M7_GSP3_SP7c2_SP7nc3_NotA); inv M7_GSP3_SP7c2_SP7nc3_Xo1(M7_GSP3_SP7c2_line2, M7_GSP3_SP7c2_SP7nc3_NotB); nand2 M7_GSP3_SP7c2_SP7nc3_Xo2(M7_GSP3_SP7c2_SP7nc3_NotA, M7_GSP3_SP7c2_line2, M7_GSP3_SP7c2_SP7nc3_line2); nand2 M7_GSP3_SP7c2_SP7nc3_Xo3(M7_GSP3_SP7c2_SP7nc3_NotB, PropXbus_6, M7_GSP3_SP7c2_SP7nc3_line3); nand2 M7_GSP3_SP7c2_SP7nc3_Xo4(M7_GSP3_SP7c2_SP7nc3_line2, M7_GSP3_SP7c2_SP7nc3_line3, M7_GSP3_SP7c2_line3); inv M7_GSP3_SP7c2_SP7nc4_Xo0(PropXbus_7, M7_GSP3_SP7c2_SP7nc4_NotA); inv M7_GSP3_SP7c2_SP7nc4_Xo1(M7_GSP3_SP7c2_line3, M7_GSP3_SP7c2_SP7nc4_NotB); nand2 M7_GSP3_SP7c2_SP7nc4_Xo2(M7_GSP3_SP7c2_SP7nc4_NotA, M7_GSP3_SP7c2_line3, M7_GSP3_SP7c2_SP7nc4_line2); nand2 M7_GSP3_SP7c2_SP7nc4_Xo3(M7_GSP3_SP7c2_SP7nc4_NotB, PropXbus_7, M7_GSP3_SP7c2_SP7nc4_line3); nand2 M7_GSP3_SP7c2_SP7nc4_Xo4(M7_GSP3_SP7c2_SP7nc4_line2, M7_GSP3_SP7c2_SP7nc4_line3, M7_GSP3_SP7c2_line4); inv M7_GSP3_SP7c2_SP7nc5_Xo0(M7_GSP3_NewInbus_6, M7_GSP3_SP7c2_SP7nc5_NotA); inv M7_GSP3_SP7c2_SP7nc5_Xo1(M7_GSP3_SP7c2_line4, M7_GSP3_SP7c2_SP7nc5_NotB); nand2 M7_GSP3_SP7c2_SP7nc5_Xo2(M7_GSP3_SP7c2_SP7nc5_NotA, M7_GSP3_SP7c2_line4, M7_GSP3_SP7c2_SP7nc5_line2); nand2 M7_GSP3_SP7c2_SP7nc5_Xo3(M7_GSP3_SP7c2_SP7nc5_NotB, M7_GSP3_NewInbus_6, M7_GSP3_SP7c2_SP7nc5_line3); nand2 M7_GSP3_SP7c2_SP7nc5_Xo4(M7_GSP3_SP7c2_SP7nc5_line2, M7_GSP3_SP7c2_SP7nc5_line3, M7_ParCin1b8_5); inv M7_GSP4_SP9nc0_SP7nc0_Xo0(M5_GenXbus_9, M7_GSP4_SP9nc0_SP7nc0_NotA); inv M7_GSP4_SP9nc0_SP7nc0_Xo1(LocalCarryXCin0_10, M7_GSP4_SP9nc0_SP7nc0_NotB); nand2 M7_GSP4_SP9nc0_SP7nc0_Xo2(M7_GSP4_SP9nc0_SP7nc0_NotA, LocalCarryXCin0_10, M7_GSP4_SP9nc0_SP7nc0_line2); nand2 M7_GSP4_SP9nc0_SP7nc0_Xo3(M7_GSP4_SP9nc0_SP7nc0_NotB, M5_GenXbus_9, M7_GSP4_SP9nc0_SP7nc0_line3); nand2 M7_GSP4_SP9nc0_SP7nc0_Xo4(M7_GSP4_SP9nc0_SP7nc0_line2, M7_GSP4_SP9nc0_SP7nc0_line3, M7_GSP4_SP9nc0_line0); inv M7_GSP4_SP9nc0_SP7nc1_Xo0(LocalCarryXCin0_11, M7_GSP4_SP9nc0_SP7nc1_NotA); inv M7_GSP4_SP9nc0_SP7nc1_Xo1(M7_GSP4_SP9nc0_line0, M7_GSP4_SP9nc0_SP7nc1_NotB); nand2 M7_GSP4_SP9nc0_SP7nc1_Xo2(M7_GSP4_SP9nc0_SP7nc1_NotA, M7_GSP4_SP9nc0_line0, M7_GSP4_SP9nc0_SP7nc1_line2); nand2 M7_GSP4_SP9nc0_SP7nc1_Xo3(M7_GSP4_SP9nc0_SP7nc1_NotB, LocalCarryXCin0_11, M7_GSP4_SP9nc0_SP7nc1_line3); nand2 M7_GSP4_SP9nc0_SP7nc1_Xo4(M7_GSP4_SP9nc0_SP7nc1_line2, M7_GSP4_SP9nc0_SP7nc1_line3, M7_GSP4_SP9nc0_line1); inv M7_GSP4_SP9nc0_SP7nc2_Xo0(LocalCarryXCin0_12, M7_GSP4_SP9nc0_SP7nc2_NotA); inv M7_GSP4_SP9nc0_SP7nc2_Xo1(M7_GSP4_SP9nc0_line1, M7_GSP4_SP9nc0_SP7nc2_NotB); nand2 M7_GSP4_SP9nc0_SP7nc2_Xo2(M7_GSP4_SP9nc0_SP7nc2_NotA, M7_GSP4_SP9nc0_line1, M7_GSP4_SP9nc0_SP7nc2_line2); nand2 M7_GSP4_SP9nc0_SP7nc2_Xo3(M7_GSP4_SP9nc0_SP7nc2_NotB, LocalCarryXCin0_12, M7_GSP4_SP9nc0_SP7nc2_line3); nand2 M7_GSP4_SP9nc0_SP7nc2_Xo4(M7_GSP4_SP9nc0_SP7nc2_line2, M7_GSP4_SP9nc0_SP7nc2_line3, M7_GSP4_SP9nc0_line2); inv M7_GSP4_SP9nc0_SP7nc3_Xo0(PropXbus_9, M7_GSP4_SP9nc0_SP7nc3_NotA); inv M7_GSP4_SP9nc0_SP7nc3_Xo1(M7_GSP4_SP9nc0_line2, M7_GSP4_SP9nc0_SP7nc3_NotB); nand2 M7_GSP4_SP9nc0_SP7nc3_Xo2(M7_GSP4_SP9nc0_SP7nc3_NotA, M7_GSP4_SP9nc0_line2, M7_GSP4_SP9nc0_SP7nc3_line2); nand2 M7_GSP4_SP9nc0_SP7nc3_Xo3(M7_GSP4_SP9nc0_SP7nc3_NotB, PropXbus_9, M7_GSP4_SP9nc0_SP7nc3_line3); nand2 M7_GSP4_SP9nc0_SP7nc3_Xo4(M7_GSP4_SP9nc0_SP7nc3_line2, M7_GSP4_SP9nc0_SP7nc3_line3, M7_GSP4_SP9nc0_line3); inv M7_GSP4_SP9nc0_SP7nc4_Xo0(PropXbus_10, M7_GSP4_SP9nc0_SP7nc4_NotA); inv M7_GSP4_SP9nc0_SP7nc4_Xo1(M7_GSP4_SP9nc0_line3, M7_GSP4_SP9nc0_SP7nc4_NotB); nand2 M7_GSP4_SP9nc0_SP7nc4_Xo2(M7_GSP4_SP9nc0_SP7nc4_NotA, M7_GSP4_SP9nc0_line3, M7_GSP4_SP9nc0_SP7nc4_line2); nand2 M7_GSP4_SP9nc0_SP7nc4_Xo3(M7_GSP4_SP9nc0_SP7nc4_NotB, PropXbus_10, M7_GSP4_SP9nc0_SP7nc4_line3); nand2 M7_GSP4_SP9nc0_SP7nc4_Xo4(M7_GSP4_SP9nc0_SP7nc4_line2, M7_GSP4_SP9nc0_SP7nc4_line3, M7_GSP4_SP9nc0_line4); inv M7_GSP4_SP9nc0_SP7nc5_Xo0(PropXbus_11, M7_GSP4_SP9nc0_SP7nc5_NotA); inv M7_GSP4_SP9nc0_SP7nc5_Xo1(M7_GSP4_SP9nc0_line4, M7_GSP4_SP9nc0_SP7nc5_NotB); nand2 M7_GSP4_SP9nc0_SP7nc5_Xo2(M7_GSP4_SP9nc0_SP7nc5_NotA, M7_GSP4_SP9nc0_line4, M7_GSP4_SP9nc0_SP7nc5_line2); nand2 M7_GSP4_SP9nc0_SP7nc5_Xo3(M7_GSP4_SP9nc0_SP7nc5_NotB, PropXbus_11, M7_GSP4_SP9nc0_SP7nc5_line3); nand2 M7_GSP4_SP9nc0_SP7nc5_Xo4(M7_GSP4_SP9nc0_SP7nc5_line2, M7_GSP4_SP9nc0_SP7nc5_line3, M7_GSP4_line0); inv M7_GSP4_SP9nc1_Xo0(PropXbus_12, M7_GSP4_SP9nc1_NotA); inv M7_GSP4_SP9nc1_Xo1(M7_GSP4_line0, M7_GSP4_SP9nc1_NotB); nand2 M7_GSP4_SP9nc1_Xo2(M7_GSP4_SP9nc1_NotA, M7_GSP4_line0, M7_GSP4_SP9nc1_line2); nand2 M7_GSP4_SP9nc1_Xo3(M7_GSP4_SP9nc1_NotB, PropXbus_12, M7_GSP4_SP9nc1_line3); nand2 M7_GSP4_SP9nc1_Xo4(M7_GSP4_SP9nc1_line2, M7_GSP4_SP9nc1_line3, M7_GSP4_line1); inv M7_GSP4_SP9nc2_Xo0(PropXbus_13, M7_GSP4_SP9nc2_NotA); inv M7_GSP4_SP9nc2_Xo1(M7_GSP4_line1, M7_GSP4_SP9nc2_NotB); nand2 M7_GSP4_SP9nc2_Xo2(M7_GSP4_SP9nc2_NotA, M7_GSP4_line1, M7_GSP4_SP9nc2_line2); nand2 M7_GSP4_SP9nc2_Xo3(M7_GSP4_SP9nc2_NotB, PropXbus_13, M7_GSP4_SP9nc2_line3); nand2 M7_GSP4_SP9nc2_Xo4(M7_GSP4_SP9nc2_line2, M7_GSP4_SP9nc2_line3, M7_ParCin0b13_9); inv M7_GSP5_SP9nc0_SP7c0(PropXbus_11, M7_GSP5_SP9nc0_NewInbus_6); inv M7_GSP5_SP9nc0_SP7c2_SP7nc0_Xo0(LocalCarryXCin1_9, M7_GSP5_SP9nc0_SP7c2_SP7nc0_NotA); inv M7_GSP5_SP9nc0_SP7c2_SP7nc0_Xo1(LocalCarryXCin1_10, M7_GSP5_SP9nc0_SP7c2_SP7nc0_NotB); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc0_Xo2(M7_GSP5_SP9nc0_SP7c2_SP7nc0_NotA, LocalCarryXCin1_10, M7_GSP5_SP9nc0_SP7c2_SP7nc0_line2); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc0_Xo3(M7_GSP5_SP9nc0_SP7c2_SP7nc0_NotB, LocalCarryXCin1_9, M7_GSP5_SP9nc0_SP7c2_SP7nc0_line3); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc0_Xo4(M7_GSP5_SP9nc0_SP7c2_SP7nc0_line2, M7_GSP5_SP9nc0_SP7c2_SP7nc0_line3, M7_GSP5_SP9nc0_SP7c2_line0); inv M7_GSP5_SP9nc0_SP7c2_SP7nc1_Xo0(LocalCarryXCin1_11, M7_GSP5_SP9nc0_SP7c2_SP7nc1_NotA); inv M7_GSP5_SP9nc0_SP7c2_SP7nc1_Xo1(M7_GSP5_SP9nc0_SP7c2_line0, M7_GSP5_SP9nc0_SP7c2_SP7nc1_NotB); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc1_Xo2(M7_GSP5_SP9nc0_SP7c2_SP7nc1_NotA, M7_GSP5_SP9nc0_SP7c2_line0, M7_GSP5_SP9nc0_SP7c2_SP7nc1_line2); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc1_Xo3(M7_GSP5_SP9nc0_SP7c2_SP7nc1_NotB, LocalCarryXCin1_11, M7_GSP5_SP9nc0_SP7c2_SP7nc1_line3); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc1_Xo4(M7_GSP5_SP9nc0_SP7c2_SP7nc1_line2, M7_GSP5_SP9nc0_SP7c2_SP7nc1_line3, M7_GSP5_SP9nc0_SP7c2_line1); inv M7_GSP5_SP9nc0_SP7c2_SP7nc2_Xo0(LocalCarryXCin1_12, M7_GSP5_SP9nc0_SP7c2_SP7nc2_NotA); inv M7_GSP5_SP9nc0_SP7c2_SP7nc2_Xo1(M7_GSP5_SP9nc0_SP7c2_line1, M7_GSP5_SP9nc0_SP7c2_SP7nc2_NotB); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc2_Xo2(M7_GSP5_SP9nc0_SP7c2_SP7nc2_NotA, M7_GSP5_SP9nc0_SP7c2_line1, M7_GSP5_SP9nc0_SP7c2_SP7nc2_line2); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc2_Xo3(M7_GSP5_SP9nc0_SP7c2_SP7nc2_NotB, LocalCarryXCin1_12, M7_GSP5_SP9nc0_SP7c2_SP7nc2_line3); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc2_Xo4(M7_GSP5_SP9nc0_SP7c2_SP7nc2_line2, M7_GSP5_SP9nc0_SP7c2_SP7nc2_line3, M7_GSP5_SP9nc0_SP7c2_line2); inv M7_GSP5_SP9nc0_SP7c2_SP7nc3_Xo0(PropXbus_9, M7_GSP5_SP9nc0_SP7c2_SP7nc3_NotA); inv M7_GSP5_SP9nc0_SP7c2_SP7nc3_Xo1(M7_GSP5_SP9nc0_SP7c2_line2, M7_GSP5_SP9nc0_SP7c2_SP7nc3_NotB); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc3_Xo2(M7_GSP5_SP9nc0_SP7c2_SP7nc3_NotA, M7_GSP5_SP9nc0_SP7c2_line2, M7_GSP5_SP9nc0_SP7c2_SP7nc3_line2); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc3_Xo3(M7_GSP5_SP9nc0_SP7c2_SP7nc3_NotB, PropXbus_9, M7_GSP5_SP9nc0_SP7c2_SP7nc3_line3); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc3_Xo4(M7_GSP5_SP9nc0_SP7c2_SP7nc3_line2, M7_GSP5_SP9nc0_SP7c2_SP7nc3_line3, M7_GSP5_SP9nc0_SP7c2_line3); inv M7_GSP5_SP9nc0_SP7c2_SP7nc4_Xo0(PropXbus_10, M7_GSP5_SP9nc0_SP7c2_SP7nc4_NotA); inv M7_GSP5_SP9nc0_SP7c2_SP7nc4_Xo1(M7_GSP5_SP9nc0_SP7c2_line3, M7_GSP5_SP9nc0_SP7c2_SP7nc4_NotB); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc4_Xo2(M7_GSP5_SP9nc0_SP7c2_SP7nc4_NotA, M7_GSP5_SP9nc0_SP7c2_line3, M7_GSP5_SP9nc0_SP7c2_SP7nc4_line2); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc4_Xo3(M7_GSP5_SP9nc0_SP7c2_SP7nc4_NotB, PropXbus_10, M7_GSP5_SP9nc0_SP7c2_SP7nc4_line3); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc4_Xo4(M7_GSP5_SP9nc0_SP7c2_SP7nc4_line2, M7_GSP5_SP9nc0_SP7c2_SP7nc4_line3, M7_GSP5_SP9nc0_SP7c2_line4); inv M7_GSP5_SP9nc0_SP7c2_SP7nc5_Xo0(M7_GSP5_SP9nc0_NewInbus_6, M7_GSP5_SP9nc0_SP7c2_SP7nc5_NotA); inv M7_GSP5_SP9nc0_SP7c2_SP7nc5_Xo1(M7_GSP5_SP9nc0_SP7c2_line4, M7_GSP5_SP9nc0_SP7c2_SP7nc5_NotB); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc5_Xo2(M7_GSP5_SP9nc0_SP7c2_SP7nc5_NotA, M7_GSP5_SP9nc0_SP7c2_line4, M7_GSP5_SP9nc0_SP7c2_SP7nc5_line2); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc5_Xo3(M7_GSP5_SP9nc0_SP7c2_SP7nc5_NotB, M7_GSP5_SP9nc0_NewInbus_6, M7_GSP5_SP9nc0_SP7c2_SP7nc5_line3); nand2 M7_GSP5_SP9nc0_SP7c2_SP7nc5_Xo4(M7_GSP5_SP9nc0_SP7c2_SP7nc5_line2, M7_GSP5_SP9nc0_SP7c2_SP7nc5_line3, M7_GSP5_line0); inv M7_GSP5_SP9nc1_Xo0(PropXbus_12, M7_GSP5_SP9nc1_NotA); inv M7_GSP5_SP9nc1_Xo1(M7_GSP5_line0, M7_GSP5_SP9nc1_NotB); nand2 M7_GSP5_SP9nc1_Xo2(M7_GSP5_SP9nc1_NotA, M7_GSP5_line0, M7_GSP5_SP9nc1_line2); nand2 M7_GSP5_SP9nc1_Xo3(M7_GSP5_SP9nc1_NotB, PropXbus_12, M7_GSP5_SP9nc1_line3); nand2 M7_GSP5_SP9nc1_Xo4(M7_GSP5_SP9nc1_line2, M7_GSP5_SP9nc1_line3, M7_GSP5_line1); inv M7_GSP5_SP9nc2_Xo0(PropXbus_13, M7_GSP5_SP9nc2_NotA); inv M7_GSP5_SP9nc2_Xo1(M7_GSP5_line1, M7_GSP5_SP9nc2_NotB); nand2 M7_GSP5_SP9nc2_Xo2(M7_GSP5_SP9nc2_NotA, M7_GSP5_line1, M7_GSP5_SP9nc2_line2); nand2 M7_GSP5_SP9nc2_Xo3(M7_GSP5_SP9nc2_NotB, PropXbus_13, M7_GSP5_SP9nc2_line3); nand2 M7_GSP5_SP9nc2_Xo4(M7_GSP5_SP9nc2_line2, M7_GSP5_SP9nc2_line3, M7_ParCin1b13_9); inv M7_GSP6_SP7nc0_Xo0(M5_GenXbus_14, M7_GSP6_SP7nc0_NotA); inv M7_GSP6_SP7nc0_Xo1(LocalCarryXCin0_15, M7_GSP6_SP7nc0_NotB); nand2 M7_GSP6_SP7nc0_Xo2(M7_GSP6_SP7nc0_NotA, LocalCarryXCin0_15, M7_GSP6_SP7nc0_line2); nand2 M7_GSP6_SP7nc0_Xo3(M7_GSP6_SP7nc0_NotB, M5_GenXbus_14, M7_GSP6_SP7nc0_line3); nand2 M7_GSP6_SP7nc0_Xo4(M7_GSP6_SP7nc0_line2, M7_GSP6_SP7nc0_line3, M7_GSP6_line0); inv M7_GSP6_SP7nc1_Xo0(LocalCarryXCin0_16, M7_GSP6_SP7nc1_NotA); inv M7_GSP6_SP7nc1_Xo1(M7_GSP6_line0, M7_GSP6_SP7nc1_NotB); nand2 M7_GSP6_SP7nc1_Xo2(M7_GSP6_SP7nc1_NotA, M7_GSP6_line0, M7_GSP6_SP7nc1_line2); nand2 M7_GSP6_SP7nc1_Xo3(M7_GSP6_SP7nc1_NotB, LocalCarryXCin0_16, M7_GSP6_SP7nc1_line3); nand2 M7_GSP6_SP7nc1_Xo4(M7_GSP6_SP7nc1_line2, M7_GSP6_SP7nc1_line3, M7_GSP6_line1); inv M7_GSP6_SP7nc2_Xo0(PropXbus_14, M7_GSP6_SP7nc2_NotA); inv M7_GSP6_SP7nc2_Xo1(M7_GSP6_line1, M7_GSP6_SP7nc2_NotB); nand2 M7_GSP6_SP7nc2_Xo2(M7_GSP6_SP7nc2_NotA, M7_GSP6_line1, M7_GSP6_SP7nc2_line2); nand2 M7_GSP6_SP7nc2_Xo3(M7_GSP6_SP7nc2_NotB, PropXbus_14, M7_GSP6_SP7nc2_line3); nand2 M7_GSP6_SP7nc2_Xo4(M7_GSP6_SP7nc2_line2, M7_GSP6_SP7nc2_line3, M7_GSP6_line2); inv M7_GSP6_SP7nc3_Xo0(PropXbus_15, M7_GSP6_SP7nc3_NotA); inv M7_GSP6_SP7nc3_Xo1(M7_GSP6_line2, M7_GSP6_SP7nc3_NotB); nand2 M7_GSP6_SP7nc3_Xo2(M7_GSP6_SP7nc3_NotA, M7_GSP6_line2, M7_GSP6_SP7nc3_line2); nand2 M7_GSP6_SP7nc3_Xo3(M7_GSP6_SP7nc3_NotB, PropXbus_15, M7_GSP6_SP7nc3_line3); nand2 M7_GSP6_SP7nc3_Xo4(M7_GSP6_SP7nc3_line2, M7_GSP6_SP7nc3_line3, M7_GSP6_line3); inv M7_GSP6_SP7nc4_Xo0(PropXbus_16, M7_GSP6_SP7nc4_NotA); inv M7_GSP6_SP7nc4_Xo1(M7_GSP6_line3, M7_GSP6_SP7nc4_NotB); nand2 M7_GSP6_SP7nc4_Xo2(M7_GSP6_SP7nc4_NotA, M7_GSP6_line3, M7_GSP6_SP7nc4_line2); nand2 M7_GSP6_SP7nc4_Xo3(M7_GSP6_SP7nc4_NotB, PropXbus_16, M7_GSP6_SP7nc4_line3); nand2 M7_GSP6_SP7nc4_Xo4(M7_GSP6_SP7nc4_line2, M7_GSP6_SP7nc4_line3, M7_GSP6_line4); inv M7_GSP6_SP7nc5_Xo0(PropXbus_17, M7_GSP6_SP7nc5_NotA); inv M7_GSP6_SP7nc5_Xo1(M7_GSP6_line4, M7_GSP6_SP7nc5_NotB); nand2 M7_GSP6_SP7nc5_Xo2(M7_GSP6_SP7nc5_NotA, M7_GSP6_line4, M7_GSP6_SP7nc5_line2); nand2 M7_GSP6_SP7nc5_Xo3(M7_GSP6_SP7nc5_NotB, PropXbus_17, M7_GSP6_SP7nc5_line3); nand2 M7_GSP6_SP7nc5_Xo4(M7_GSP6_SP7nc5_line2, M7_GSP6_SP7nc5_line3, M7_ParCin0b17_14); inv M7_GSP7_SP7c0(PropXbus_17, M7_GSP7_NewInbus_6); inv M7_GSP7_SP7c2_SP7nc0_Xo0(LocalCarryXCin1_14, M7_GSP7_SP7c2_SP7nc0_NotA); inv M7_GSP7_SP7c2_SP7nc0_Xo1(LocalCarryXCin1_15, M7_GSP7_SP7c2_SP7nc0_NotB); nand2 M7_GSP7_SP7c2_SP7nc0_Xo2(M7_GSP7_SP7c2_SP7nc0_NotA, LocalCarryXCin1_15, M7_GSP7_SP7c2_SP7nc0_line2); nand2 M7_GSP7_SP7c2_SP7nc0_Xo3(M7_GSP7_SP7c2_SP7nc0_NotB, LocalCarryXCin1_14, M7_GSP7_SP7c2_SP7nc0_line3); nand2 M7_GSP7_SP7c2_SP7nc0_Xo4(M7_GSP7_SP7c2_SP7nc0_line2, M7_GSP7_SP7c2_SP7nc0_line3, M7_GSP7_SP7c2_line0); inv M7_GSP7_SP7c2_SP7nc1_Xo0(LocalCarryXCin1_16, M7_GSP7_SP7c2_SP7nc1_NotA); inv M7_GSP7_SP7c2_SP7nc1_Xo1(M7_GSP7_SP7c2_line0, M7_GSP7_SP7c2_SP7nc1_NotB); nand2 M7_GSP7_SP7c2_SP7nc1_Xo2(M7_GSP7_SP7c2_SP7nc1_NotA, M7_GSP7_SP7c2_line0, M7_GSP7_SP7c2_SP7nc1_line2); nand2 M7_GSP7_SP7c2_SP7nc1_Xo3(M7_GSP7_SP7c2_SP7nc1_NotB, LocalCarryXCin1_16, M7_GSP7_SP7c2_SP7nc1_line3); nand2 M7_GSP7_SP7c2_SP7nc1_Xo4(M7_GSP7_SP7c2_SP7nc1_line2, M7_GSP7_SP7c2_SP7nc1_line3, M7_GSP7_SP7c2_line1); inv M7_GSP7_SP7c2_SP7nc2_Xo0(PropXbus_14, M7_GSP7_SP7c2_SP7nc2_NotA); inv M7_GSP7_SP7c2_SP7nc2_Xo1(M7_GSP7_SP7c2_line1, M7_GSP7_SP7c2_SP7nc2_NotB); nand2 M7_GSP7_SP7c2_SP7nc2_Xo2(M7_GSP7_SP7c2_SP7nc2_NotA, M7_GSP7_SP7c2_line1, M7_GSP7_SP7c2_SP7nc2_line2); nand2 M7_GSP7_SP7c2_SP7nc2_Xo3(M7_GSP7_SP7c2_SP7nc2_NotB, PropXbus_14, M7_GSP7_SP7c2_SP7nc2_line3); nand2 M7_GSP7_SP7c2_SP7nc2_Xo4(M7_GSP7_SP7c2_SP7nc2_line2, M7_GSP7_SP7c2_SP7nc2_line3, M7_GSP7_SP7c2_line2); inv M7_GSP7_SP7c2_SP7nc3_Xo0(PropXbus_15, M7_GSP7_SP7c2_SP7nc3_NotA); inv M7_GSP7_SP7c2_SP7nc3_Xo1(M7_GSP7_SP7c2_line2, M7_GSP7_SP7c2_SP7nc3_NotB); nand2 M7_GSP7_SP7c2_SP7nc3_Xo2(M7_GSP7_SP7c2_SP7nc3_NotA, M7_GSP7_SP7c2_line2, M7_GSP7_SP7c2_SP7nc3_line2); nand2 M7_GSP7_SP7c2_SP7nc3_Xo3(M7_GSP7_SP7c2_SP7nc3_NotB, PropXbus_15, M7_GSP7_SP7c2_SP7nc3_line3); nand2 M7_GSP7_SP7c2_SP7nc3_Xo4(M7_GSP7_SP7c2_SP7nc3_line2, M7_GSP7_SP7c2_SP7nc3_line3, M7_GSP7_SP7c2_line3); inv M7_GSP7_SP7c2_SP7nc4_Xo0(PropXbus_16, M7_GSP7_SP7c2_SP7nc4_NotA); inv M7_GSP7_SP7c2_SP7nc4_Xo1(M7_GSP7_SP7c2_line3, M7_GSP7_SP7c2_SP7nc4_NotB); nand2 M7_GSP7_SP7c2_SP7nc4_Xo2(M7_GSP7_SP7c2_SP7nc4_NotA, M7_GSP7_SP7c2_line3, M7_GSP7_SP7c2_SP7nc4_line2); nand2 M7_GSP7_SP7c2_SP7nc4_Xo3(M7_GSP7_SP7c2_SP7nc4_NotB, PropXbus_16, M7_GSP7_SP7c2_SP7nc4_line3); nand2 M7_GSP7_SP7c2_SP7nc4_Xo4(M7_GSP7_SP7c2_SP7nc4_line2, M7_GSP7_SP7c2_SP7nc4_line3, M7_GSP7_SP7c2_line4); inv M7_GSP7_SP7c2_SP7nc5_Xo0(M7_GSP7_NewInbus_6, M7_GSP7_SP7c2_SP7nc5_NotA); inv M7_GSP7_SP7c2_SP7nc5_Xo1(M7_GSP7_SP7c2_line4, M7_GSP7_SP7c2_SP7nc5_NotB); nand2 M7_GSP7_SP7c2_SP7nc5_Xo2(M7_GSP7_SP7c2_SP7nc5_NotA, M7_GSP7_SP7c2_line4, M7_GSP7_SP7c2_SP7nc5_line2); nand2 M7_GSP7_SP7c2_SP7nc5_Xo3(M7_GSP7_SP7c2_SP7nc5_NotB, M7_GSP7_NewInbus_6, M7_GSP7_SP7c2_SP7nc5_line3); nand2 M7_GSP7_SP7c2_SP7nc5_Xo4(M7_GSP7_SP7c2_SP7nc5_line2, M7_GSP7_SP7c2_SP7nc5_line3, M7_ParCin1b17_14); inv M7_GSP8_SP9nc0_SP7nc0_Xo0(M5_GenXbus_18, M7_GSP8_SP9nc0_SP7nc0_NotA); inv M7_GSP8_SP9nc0_SP7nc0_Xo1(LocalCarryXCin0_19, M7_GSP8_SP9nc0_SP7nc0_NotB); nand2 M7_GSP8_SP9nc0_SP7nc0_Xo2(M7_GSP8_SP9nc0_SP7nc0_NotA, LocalCarryXCin0_19, M7_GSP8_SP9nc0_SP7nc0_line2); nand2 M7_GSP8_SP9nc0_SP7nc0_Xo3(M7_GSP8_SP9nc0_SP7nc0_NotB, M5_GenXbus_18, M7_GSP8_SP9nc0_SP7nc0_line3); nand2 M7_GSP8_SP9nc0_SP7nc0_Xo4(M7_GSP8_SP9nc0_SP7nc0_line2, M7_GSP8_SP9nc0_SP7nc0_line3, M7_GSP8_SP9nc0_line0); inv M7_GSP8_SP9nc0_SP7nc1_Xo0(LocalCarryXCin0_20, M7_GSP8_SP9nc0_SP7nc1_NotA); inv M7_GSP8_SP9nc0_SP7nc1_Xo1(M7_GSP8_SP9nc0_line0, M7_GSP8_SP9nc0_SP7nc1_NotB); nand2 M7_GSP8_SP9nc0_SP7nc1_Xo2(M7_GSP8_SP9nc0_SP7nc1_NotA, M7_GSP8_SP9nc0_line0, M7_GSP8_SP9nc0_SP7nc1_line2); nand2 M7_GSP8_SP9nc0_SP7nc1_Xo3(M7_GSP8_SP9nc0_SP7nc1_NotB, LocalCarryXCin0_20, M7_GSP8_SP9nc0_SP7nc1_line3); nand2 M7_GSP8_SP9nc0_SP7nc1_Xo4(M7_GSP8_SP9nc0_SP7nc1_line2, M7_GSP8_SP9nc0_SP7nc1_line3, M7_GSP8_SP9nc0_line1); inv M7_GSP8_SP9nc0_SP7nc2_Xo0(LocalCarryXCin0_21, M7_GSP8_SP9nc0_SP7nc2_NotA); inv M7_GSP8_SP9nc0_SP7nc2_Xo1(M7_GSP8_SP9nc0_line1, M7_GSP8_SP9nc0_SP7nc2_NotB); nand2 M7_GSP8_SP9nc0_SP7nc2_Xo2(M7_GSP8_SP9nc0_SP7nc2_NotA, M7_GSP8_SP9nc0_line1, M7_GSP8_SP9nc0_SP7nc2_line2); nand2 M7_GSP8_SP9nc0_SP7nc2_Xo3(M7_GSP8_SP9nc0_SP7nc2_NotB, LocalCarryXCin0_21, M7_GSP8_SP9nc0_SP7nc2_line3); nand2 M7_GSP8_SP9nc0_SP7nc2_Xo4(M7_GSP8_SP9nc0_SP7nc2_line2, M7_GSP8_SP9nc0_SP7nc2_line3, M7_GSP8_SP9nc0_line2); inv M7_GSP8_SP9nc0_SP7nc3_Xo0(PropXbus_18, M7_GSP8_SP9nc0_SP7nc3_NotA); inv M7_GSP8_SP9nc0_SP7nc3_Xo1(M7_GSP8_SP9nc0_line2, M7_GSP8_SP9nc0_SP7nc3_NotB); nand2 M7_GSP8_SP9nc0_SP7nc3_Xo2(M7_GSP8_SP9nc0_SP7nc3_NotA, M7_GSP8_SP9nc0_line2, M7_GSP8_SP9nc0_SP7nc3_line2); nand2 M7_GSP8_SP9nc0_SP7nc3_Xo3(M7_GSP8_SP9nc0_SP7nc3_NotB, PropXbus_18, M7_GSP8_SP9nc0_SP7nc3_line3); nand2 M7_GSP8_SP9nc0_SP7nc3_Xo4(M7_GSP8_SP9nc0_SP7nc3_line2, M7_GSP8_SP9nc0_SP7nc3_line3, M7_GSP8_SP9nc0_line3); inv M7_GSP8_SP9nc0_SP7nc4_Xo0(PropXbus_19, M7_GSP8_SP9nc0_SP7nc4_NotA); inv M7_GSP8_SP9nc0_SP7nc4_Xo1(M7_GSP8_SP9nc0_line3, M7_GSP8_SP9nc0_SP7nc4_NotB); nand2 M7_GSP8_SP9nc0_SP7nc4_Xo2(M7_GSP8_SP9nc0_SP7nc4_NotA, M7_GSP8_SP9nc0_line3, M7_GSP8_SP9nc0_SP7nc4_line2); nand2 M7_GSP8_SP9nc0_SP7nc4_Xo3(M7_GSP8_SP9nc0_SP7nc4_NotB, PropXbus_19, M7_GSP8_SP9nc0_SP7nc4_line3); nand2 M7_GSP8_SP9nc0_SP7nc4_Xo4(M7_GSP8_SP9nc0_SP7nc4_line2, M7_GSP8_SP9nc0_SP7nc4_line3, M7_GSP8_SP9nc0_line4); inv M7_GSP8_SP9nc0_SP7nc5_Xo0(PropXbus_20, M7_GSP8_SP9nc0_SP7nc5_NotA); inv M7_GSP8_SP9nc0_SP7nc5_Xo1(M7_GSP8_SP9nc0_line4, M7_GSP8_SP9nc0_SP7nc5_NotB); nand2 M7_GSP8_SP9nc0_SP7nc5_Xo2(M7_GSP8_SP9nc0_SP7nc5_NotA, M7_GSP8_SP9nc0_line4, M7_GSP8_SP9nc0_SP7nc5_line2); nand2 M7_GSP8_SP9nc0_SP7nc5_Xo3(M7_GSP8_SP9nc0_SP7nc5_NotB, PropXbus_20, M7_GSP8_SP9nc0_SP7nc5_line3); nand2 M7_GSP8_SP9nc0_SP7nc5_Xo4(M7_GSP8_SP9nc0_SP7nc5_line2, M7_GSP8_SP9nc0_SP7nc5_line3, M7_GSP8_line0); inv M7_GSP8_SP9nc1_Xo0(PropXbus_21, M7_GSP8_SP9nc1_NotA); inv M7_GSP8_SP9nc1_Xo1(M7_GSP8_line0, M7_GSP8_SP9nc1_NotB); nand2 M7_GSP8_SP9nc1_Xo2(M7_GSP8_SP9nc1_NotA, M7_GSP8_line0, M7_GSP8_SP9nc1_line2); nand2 M7_GSP8_SP9nc1_Xo3(M7_GSP8_SP9nc1_NotB, PropXbus_21, M7_GSP8_SP9nc1_line3); nand2 M7_GSP8_SP9nc1_Xo4(M7_GSP8_SP9nc1_line2, M7_GSP8_SP9nc1_line3, M7_GSP8_line1); inv M7_GSP8_SP9nc2_Xo0(PropXbus_22, M7_GSP8_SP9nc2_NotA); inv M7_GSP8_SP9nc2_Xo1(M7_GSP8_line1, M7_GSP8_SP9nc2_NotB); nand2 M7_GSP8_SP9nc2_Xo2(M7_GSP8_SP9nc2_NotA, M7_GSP8_line1, M7_GSP8_SP9nc2_line2); nand2 M7_GSP8_SP9nc2_Xo3(M7_GSP8_SP9nc2_NotB, PropXbus_22, M7_GSP8_SP9nc2_line3); nand2 M7_GSP8_SP9nc2_Xo4(M7_GSP8_SP9nc2_line2, M7_GSP8_SP9nc2_line3, M7_ParCin0b22_18); inv M7_GSP9_SP9nc0_SP7c0(PropXbus_20, M7_GSP9_SP9nc0_NewInbus_6); inv M7_GSP9_SP9nc0_SP7c2_SP7nc0_Xo0(LocalCarryXCin1_18, M7_GSP9_SP9nc0_SP7c2_SP7nc0_NotA); inv M7_GSP9_SP9nc0_SP7c2_SP7nc0_Xo1(LocalCarryXCin1_19, M7_GSP9_SP9nc0_SP7c2_SP7nc0_NotB); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc0_Xo2(M7_GSP9_SP9nc0_SP7c2_SP7nc0_NotA, LocalCarryXCin1_19, M7_GSP9_SP9nc0_SP7c2_SP7nc0_line2); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc0_Xo3(M7_GSP9_SP9nc0_SP7c2_SP7nc0_NotB, LocalCarryXCin1_18, M7_GSP9_SP9nc0_SP7c2_SP7nc0_line3); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc0_Xo4(M7_GSP9_SP9nc0_SP7c2_SP7nc0_line2, M7_GSP9_SP9nc0_SP7c2_SP7nc0_line3, M7_GSP9_SP9nc0_SP7c2_line0); inv M7_GSP9_SP9nc0_SP7c2_SP7nc1_Xo0(LocalCarryXCin1_20, M7_GSP9_SP9nc0_SP7c2_SP7nc1_NotA); inv M7_GSP9_SP9nc0_SP7c2_SP7nc1_Xo1(M7_GSP9_SP9nc0_SP7c2_line0, M7_GSP9_SP9nc0_SP7c2_SP7nc1_NotB); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc1_Xo2(M7_GSP9_SP9nc0_SP7c2_SP7nc1_NotA, M7_GSP9_SP9nc0_SP7c2_line0, M7_GSP9_SP9nc0_SP7c2_SP7nc1_line2); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc1_Xo3(M7_GSP9_SP9nc0_SP7c2_SP7nc1_NotB, LocalCarryXCin1_20, M7_GSP9_SP9nc0_SP7c2_SP7nc1_line3); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc1_Xo4(M7_GSP9_SP9nc0_SP7c2_SP7nc1_line2, M7_GSP9_SP9nc0_SP7c2_SP7nc1_line3, M7_GSP9_SP9nc0_SP7c2_line1); inv M7_GSP9_SP9nc0_SP7c2_SP7nc2_Xo0(LocalCarryXCin1_21, M7_GSP9_SP9nc0_SP7c2_SP7nc2_NotA); inv M7_GSP9_SP9nc0_SP7c2_SP7nc2_Xo1(M7_GSP9_SP9nc0_SP7c2_line1, M7_GSP9_SP9nc0_SP7c2_SP7nc2_NotB); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc2_Xo2(M7_GSP9_SP9nc0_SP7c2_SP7nc2_NotA, M7_GSP9_SP9nc0_SP7c2_line1, M7_GSP9_SP9nc0_SP7c2_SP7nc2_line2); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc2_Xo3(M7_GSP9_SP9nc0_SP7c2_SP7nc2_NotB, LocalCarryXCin1_21, M7_GSP9_SP9nc0_SP7c2_SP7nc2_line3); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc2_Xo4(M7_GSP9_SP9nc0_SP7c2_SP7nc2_line2, M7_GSP9_SP9nc0_SP7c2_SP7nc2_line3, M7_GSP9_SP9nc0_SP7c2_line2); inv M7_GSP9_SP9nc0_SP7c2_SP7nc3_Xo0(PropXbus_18, M7_GSP9_SP9nc0_SP7c2_SP7nc3_NotA); inv M7_GSP9_SP9nc0_SP7c2_SP7nc3_Xo1(M7_GSP9_SP9nc0_SP7c2_line2, M7_GSP9_SP9nc0_SP7c2_SP7nc3_NotB); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc3_Xo2(M7_GSP9_SP9nc0_SP7c2_SP7nc3_NotA, M7_GSP9_SP9nc0_SP7c2_line2, M7_GSP9_SP9nc0_SP7c2_SP7nc3_line2); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc3_Xo3(M7_GSP9_SP9nc0_SP7c2_SP7nc3_NotB, PropXbus_18, M7_GSP9_SP9nc0_SP7c2_SP7nc3_line3); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc3_Xo4(M7_GSP9_SP9nc0_SP7c2_SP7nc3_line2, M7_GSP9_SP9nc0_SP7c2_SP7nc3_line3, M7_GSP9_SP9nc0_SP7c2_line3); inv M7_GSP9_SP9nc0_SP7c2_SP7nc4_Xo0(PropXbus_19, M7_GSP9_SP9nc0_SP7c2_SP7nc4_NotA); inv M7_GSP9_SP9nc0_SP7c2_SP7nc4_Xo1(M7_GSP9_SP9nc0_SP7c2_line3, M7_GSP9_SP9nc0_SP7c2_SP7nc4_NotB); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc4_Xo2(M7_GSP9_SP9nc0_SP7c2_SP7nc4_NotA, M7_GSP9_SP9nc0_SP7c2_line3, M7_GSP9_SP9nc0_SP7c2_SP7nc4_line2); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc4_Xo3(M7_GSP9_SP9nc0_SP7c2_SP7nc4_NotB, PropXbus_19, M7_GSP9_SP9nc0_SP7c2_SP7nc4_line3); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc4_Xo4(M7_GSP9_SP9nc0_SP7c2_SP7nc4_line2, M7_GSP9_SP9nc0_SP7c2_SP7nc4_line3, M7_GSP9_SP9nc0_SP7c2_line4); inv M7_GSP9_SP9nc0_SP7c2_SP7nc5_Xo0(M7_GSP9_SP9nc0_NewInbus_6, M7_GSP9_SP9nc0_SP7c2_SP7nc5_NotA); inv M7_GSP9_SP9nc0_SP7c2_SP7nc5_Xo1(M7_GSP9_SP9nc0_SP7c2_line4, M7_GSP9_SP9nc0_SP7c2_SP7nc5_NotB); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc5_Xo2(M7_GSP9_SP9nc0_SP7c2_SP7nc5_NotA, M7_GSP9_SP9nc0_SP7c2_line4, M7_GSP9_SP9nc0_SP7c2_SP7nc5_line2); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc5_Xo3(M7_GSP9_SP9nc0_SP7c2_SP7nc5_NotB, M7_GSP9_SP9nc0_NewInbus_6, M7_GSP9_SP9nc0_SP7c2_SP7nc5_line3); nand2 M7_GSP9_SP9nc0_SP7c2_SP7nc5_Xo4(M7_GSP9_SP9nc0_SP7c2_SP7nc5_line2, M7_GSP9_SP9nc0_SP7c2_SP7nc5_line3, M7_GSP9_line0); inv M7_GSP9_SP9nc1_Xo0(PropXbus_21, M7_GSP9_SP9nc1_NotA); inv M7_GSP9_SP9nc1_Xo1(M7_GSP9_line0, M7_GSP9_SP9nc1_NotB); nand2 M7_GSP9_SP9nc1_Xo2(M7_GSP9_SP9nc1_NotA, M7_GSP9_line0, M7_GSP9_SP9nc1_line2); nand2 M7_GSP9_SP9nc1_Xo3(M7_GSP9_SP9nc1_NotB, PropXbus_21, M7_GSP9_SP9nc1_line3); nand2 M7_GSP9_SP9nc1_Xo4(M7_GSP9_SP9nc1_line2, M7_GSP9_SP9nc1_line3, M7_GSP9_line1); inv M7_GSP9_SP9nc2_Xo0(PropXbus_22, M7_GSP9_SP9nc2_NotA); inv M7_GSP9_SP9nc2_Xo1(M7_GSP9_line1, M7_GSP9_SP9nc2_NotB); nand2 M7_GSP9_SP9nc2_Xo2(M7_GSP9_SP9nc2_NotA, M7_GSP9_line1, M7_GSP9_SP9nc2_line2); nand2 M7_GSP9_SP9nc2_Xo3(M7_GSP9_SP9nc2_NotB, PropXbus_22, M7_GSP9_SP9nc2_line3); nand2 M7_GSP9_SP9nc2_Xo4(M7_GSP9_SP9nc2_line2, M7_GSP9_SP9nc2_line3, M7_ParCin1b22_18); inv M7_GSP10_SP7nc0_Xo0(M5_GenXbus_23, M7_GSP10_SP7nc0_NotA); inv M7_GSP10_SP7nc0_Xo1(LocalCarryXCin0_24, M7_GSP10_SP7nc0_NotB); nand2 M7_GSP10_SP7nc0_Xo2(M7_GSP10_SP7nc0_NotA, LocalCarryXCin0_24, M7_GSP10_SP7nc0_line2); nand2 M7_GSP10_SP7nc0_Xo3(M7_GSP10_SP7nc0_NotB, M5_GenXbus_23, M7_GSP10_SP7nc0_line3); nand2 M7_GSP10_SP7nc0_Xo4(M7_GSP10_SP7nc0_line2, M7_GSP10_SP7nc0_line3, M7_GSP10_line0); inv M7_GSP10_SP7nc1_Xo0(LocalCarryXCin0_25, M7_GSP10_SP7nc1_NotA); inv M7_GSP10_SP7nc1_Xo1(M7_GSP10_line0, M7_GSP10_SP7nc1_NotB); nand2 M7_GSP10_SP7nc1_Xo2(M7_GSP10_SP7nc1_NotA, M7_GSP10_line0, M7_GSP10_SP7nc1_line2); nand2 M7_GSP10_SP7nc1_Xo3(M7_GSP10_SP7nc1_NotB, LocalCarryXCin0_25, M7_GSP10_SP7nc1_line3); nand2 M7_GSP10_SP7nc1_Xo4(M7_GSP10_SP7nc1_line2, M7_GSP10_SP7nc1_line3, M7_GSP10_line1); inv M7_GSP10_SP7nc2_Xo0(PropXbus_23, M7_GSP10_SP7nc2_NotA); inv M7_GSP10_SP7nc2_Xo1(M7_GSP10_line1, M7_GSP10_SP7nc2_NotB); nand2 M7_GSP10_SP7nc2_Xo2(M7_GSP10_SP7nc2_NotA, M7_GSP10_line1, M7_GSP10_SP7nc2_line2); nand2 M7_GSP10_SP7nc2_Xo3(M7_GSP10_SP7nc2_NotB, PropXbus_23, M7_GSP10_SP7nc2_line3); nand2 M7_GSP10_SP7nc2_Xo4(M7_GSP10_SP7nc2_line2, M7_GSP10_SP7nc2_line3, M7_GSP10_line2); inv M7_GSP10_SP7nc3_Xo0(PropXbus_24, M7_GSP10_SP7nc3_NotA); inv M7_GSP10_SP7nc3_Xo1(M7_GSP10_line2, M7_GSP10_SP7nc3_NotB); nand2 M7_GSP10_SP7nc3_Xo2(M7_GSP10_SP7nc3_NotA, M7_GSP10_line2, M7_GSP10_SP7nc3_line2); nand2 M7_GSP10_SP7nc3_Xo3(M7_GSP10_SP7nc3_NotB, PropXbus_24, M7_GSP10_SP7nc3_line3); nand2 M7_GSP10_SP7nc3_Xo4(M7_GSP10_SP7nc3_line2, M7_GSP10_SP7nc3_line3, M7_GSP10_line3); inv M7_GSP10_SP7nc4_Xo0(PropXbus_25, M7_GSP10_SP7nc4_NotA); inv M7_GSP10_SP7nc4_Xo1(M7_GSP10_line3, M7_GSP10_SP7nc4_NotB); nand2 M7_GSP10_SP7nc4_Xo2(M7_GSP10_SP7nc4_NotA, M7_GSP10_line3, M7_GSP10_SP7nc4_line2); nand2 M7_GSP10_SP7nc4_Xo3(M7_GSP10_SP7nc4_NotB, PropXbus_25, M7_GSP10_SP7nc4_line3); nand2 M7_GSP10_SP7nc4_Xo4(M7_GSP10_SP7nc4_line2, M7_GSP10_SP7nc4_line3, M7_GSP10_line4); inv M7_GSP10_SP7nc5_Xo0(PropXbus_26, M7_GSP10_SP7nc5_NotA); inv M7_GSP10_SP7nc5_Xo1(M7_GSP10_line4, M7_GSP10_SP7nc5_NotB); nand2 M7_GSP10_SP7nc5_Xo2(M7_GSP10_SP7nc5_NotA, M7_GSP10_line4, M7_GSP10_SP7nc5_line2); nand2 M7_GSP10_SP7nc5_Xo3(M7_GSP10_SP7nc5_NotB, PropXbus_26, M7_GSP10_SP7nc5_line3); nand2 M7_GSP10_SP7nc5_Xo4(M7_GSP10_SP7nc5_line2, M7_GSP10_SP7nc5_line3, M7_ParCin0b26_23); inv M7_GSP11_SP7c0(PropXbus_26, M7_GSP11_NewInbus_6); inv M7_GSP11_SP7c2_SP7nc0_Xo0(LocalCarryXCin1_23, M7_GSP11_SP7c2_SP7nc0_NotA); inv M7_GSP11_SP7c2_SP7nc0_Xo1(LocalCarryXCin1_24, M7_GSP11_SP7c2_SP7nc0_NotB); nand2 M7_GSP11_SP7c2_SP7nc0_Xo2(M7_GSP11_SP7c2_SP7nc0_NotA, LocalCarryXCin1_24, M7_GSP11_SP7c2_SP7nc0_line2); nand2 M7_GSP11_SP7c2_SP7nc0_Xo3(M7_GSP11_SP7c2_SP7nc0_NotB, LocalCarryXCin1_23, M7_GSP11_SP7c2_SP7nc0_line3); nand2 M7_GSP11_SP7c2_SP7nc0_Xo4(M7_GSP11_SP7c2_SP7nc0_line2, M7_GSP11_SP7c2_SP7nc0_line3, M7_GSP11_SP7c2_line0); inv M7_GSP11_SP7c2_SP7nc1_Xo0(LocalCarryXCin1_25, M7_GSP11_SP7c2_SP7nc1_NotA); inv M7_GSP11_SP7c2_SP7nc1_Xo1(M7_GSP11_SP7c2_line0, M7_GSP11_SP7c2_SP7nc1_NotB); nand2 M7_GSP11_SP7c2_SP7nc1_Xo2(M7_GSP11_SP7c2_SP7nc1_NotA, M7_GSP11_SP7c2_line0, M7_GSP11_SP7c2_SP7nc1_line2); nand2 M7_GSP11_SP7c2_SP7nc1_Xo3(M7_GSP11_SP7c2_SP7nc1_NotB, LocalCarryXCin1_25, M7_GSP11_SP7c2_SP7nc1_line3); nand2 M7_GSP11_SP7c2_SP7nc1_Xo4(M7_GSP11_SP7c2_SP7nc1_line2, M7_GSP11_SP7c2_SP7nc1_line3, M7_GSP11_SP7c2_line1); inv M7_GSP11_SP7c2_SP7nc2_Xo0(PropXbus_23, M7_GSP11_SP7c2_SP7nc2_NotA); inv M7_GSP11_SP7c2_SP7nc2_Xo1(M7_GSP11_SP7c2_line1, M7_GSP11_SP7c2_SP7nc2_NotB); nand2 M7_GSP11_SP7c2_SP7nc2_Xo2(M7_GSP11_SP7c2_SP7nc2_NotA, M7_GSP11_SP7c2_line1, M7_GSP11_SP7c2_SP7nc2_line2); nand2 M7_GSP11_SP7c2_SP7nc2_Xo3(M7_GSP11_SP7c2_SP7nc2_NotB, PropXbus_23, M7_GSP11_SP7c2_SP7nc2_line3); nand2 M7_GSP11_SP7c2_SP7nc2_Xo4(M7_GSP11_SP7c2_SP7nc2_line2, M7_GSP11_SP7c2_SP7nc2_line3, M7_GSP11_SP7c2_line2); inv M7_GSP11_SP7c2_SP7nc3_Xo0(PropXbus_24, M7_GSP11_SP7c2_SP7nc3_NotA); inv M7_GSP11_SP7c2_SP7nc3_Xo1(M7_GSP11_SP7c2_line2, M7_GSP11_SP7c2_SP7nc3_NotB); nand2 M7_GSP11_SP7c2_SP7nc3_Xo2(M7_GSP11_SP7c2_SP7nc3_NotA, M7_GSP11_SP7c2_line2, M7_GSP11_SP7c2_SP7nc3_line2); nand2 M7_GSP11_SP7c2_SP7nc3_Xo3(M7_GSP11_SP7c2_SP7nc3_NotB, PropXbus_24, M7_GSP11_SP7c2_SP7nc3_line3); nand2 M7_GSP11_SP7c2_SP7nc3_Xo4(M7_GSP11_SP7c2_SP7nc3_line2, M7_GSP11_SP7c2_SP7nc3_line3, M7_GSP11_SP7c2_line3); inv M7_GSP11_SP7c2_SP7nc4_Xo0(PropXbus_25, M7_GSP11_SP7c2_SP7nc4_NotA); inv M7_GSP11_SP7c2_SP7nc4_Xo1(M7_GSP11_SP7c2_line3, M7_GSP11_SP7c2_SP7nc4_NotB); nand2 M7_GSP11_SP7c2_SP7nc4_Xo2(M7_GSP11_SP7c2_SP7nc4_NotA, M7_GSP11_SP7c2_line3, M7_GSP11_SP7c2_SP7nc4_line2); nand2 M7_GSP11_SP7c2_SP7nc4_Xo3(M7_GSP11_SP7c2_SP7nc4_NotB, PropXbus_25, M7_GSP11_SP7c2_SP7nc4_line3); nand2 M7_GSP11_SP7c2_SP7nc4_Xo4(M7_GSP11_SP7c2_SP7nc4_line2, M7_GSP11_SP7c2_SP7nc4_line3, M7_GSP11_SP7c2_line4); inv M7_GSP11_SP7c2_SP7nc5_Xo0(M7_GSP11_NewInbus_6, M7_GSP11_SP7c2_SP7nc5_NotA); inv M7_GSP11_SP7c2_SP7nc5_Xo1(M7_GSP11_SP7c2_line4, M7_GSP11_SP7c2_SP7nc5_NotB); nand2 M7_GSP11_SP7c2_SP7nc5_Xo2(M7_GSP11_SP7c2_SP7nc5_NotA, M7_GSP11_SP7c2_line4, M7_GSP11_SP7c2_SP7nc5_line2); nand2 M7_GSP11_SP7c2_SP7nc5_Xo3(M7_GSP11_SP7c2_SP7nc5_NotB, M7_GSP11_NewInbus_6, M7_GSP11_SP7c2_SP7nc5_line3); nand2 M7_GSP11_SP7c2_SP7nc5_Xo4(M7_GSP11_SP7c2_SP7nc5_line2, M7_GSP11_SP7c2_SP7nc5_line3, M7_ParCin1b26_23); inv M7_GSP12_SP9nc0_SP7nc0_Xo0(M5_GenXbus_27, M7_GSP12_SP9nc0_SP7nc0_NotA); inv M7_GSP12_SP9nc0_SP7nc0_Xo1(LocalCarryXCin0_28, M7_GSP12_SP9nc0_SP7nc0_NotB); nand2 M7_GSP12_SP9nc0_SP7nc0_Xo2(M7_GSP12_SP9nc0_SP7nc0_NotA, LocalCarryXCin0_28, M7_GSP12_SP9nc0_SP7nc0_line2); nand2 M7_GSP12_SP9nc0_SP7nc0_Xo3(M7_GSP12_SP9nc0_SP7nc0_NotB, M5_GenXbus_27, M7_GSP12_SP9nc0_SP7nc0_line3); nand2 M7_GSP12_SP9nc0_SP7nc0_Xo4(M7_GSP12_SP9nc0_SP7nc0_line2, M7_GSP12_SP9nc0_SP7nc0_line3, M7_GSP12_SP9nc0_line0); inv M7_GSP12_SP9nc0_SP7nc1_Xo0(LocalCarryXCin0_29, M7_GSP12_SP9nc0_SP7nc1_NotA); inv M7_GSP12_SP9nc0_SP7nc1_Xo1(M7_GSP12_SP9nc0_line0, M7_GSP12_SP9nc0_SP7nc1_NotB); nand2 M7_GSP12_SP9nc0_SP7nc1_Xo2(M7_GSP12_SP9nc0_SP7nc1_NotA, M7_GSP12_SP9nc0_line0, M7_GSP12_SP9nc0_SP7nc1_line2); nand2 M7_GSP12_SP9nc0_SP7nc1_Xo3(M7_GSP12_SP9nc0_SP7nc1_NotB, LocalCarryXCin0_29, M7_GSP12_SP9nc0_SP7nc1_line3); nand2 M7_GSP12_SP9nc0_SP7nc1_Xo4(M7_GSP12_SP9nc0_SP7nc1_line2, M7_GSP12_SP9nc0_SP7nc1_line3, M7_GSP12_SP9nc0_line1); inv M7_GSP12_SP9nc0_SP7nc2_Xo0(LocalCarryXCin0_30, M7_GSP12_SP9nc0_SP7nc2_NotA); inv M7_GSP12_SP9nc0_SP7nc2_Xo1(M7_GSP12_SP9nc0_line1, M7_GSP12_SP9nc0_SP7nc2_NotB); nand2 M7_GSP12_SP9nc0_SP7nc2_Xo2(M7_GSP12_SP9nc0_SP7nc2_NotA, M7_GSP12_SP9nc0_line1, M7_GSP12_SP9nc0_SP7nc2_line2); nand2 M7_GSP12_SP9nc0_SP7nc2_Xo3(M7_GSP12_SP9nc0_SP7nc2_NotB, LocalCarryXCin0_30, M7_GSP12_SP9nc0_SP7nc2_line3); nand2 M7_GSP12_SP9nc0_SP7nc2_Xo4(M7_GSP12_SP9nc0_SP7nc2_line2, M7_GSP12_SP9nc0_SP7nc2_line3, M7_GSP12_SP9nc0_line2); inv M7_GSP12_SP9nc0_SP7nc3_Xo0(PropXbus_27, M7_GSP12_SP9nc0_SP7nc3_NotA); inv M7_GSP12_SP9nc0_SP7nc3_Xo1(M7_GSP12_SP9nc0_line2, M7_GSP12_SP9nc0_SP7nc3_NotB); nand2 M7_GSP12_SP9nc0_SP7nc3_Xo2(M7_GSP12_SP9nc0_SP7nc3_NotA, M7_GSP12_SP9nc0_line2, M7_GSP12_SP9nc0_SP7nc3_line2); nand2 M7_GSP12_SP9nc0_SP7nc3_Xo3(M7_GSP12_SP9nc0_SP7nc3_NotB, PropXbus_27, M7_GSP12_SP9nc0_SP7nc3_line3); nand2 M7_GSP12_SP9nc0_SP7nc3_Xo4(M7_GSP12_SP9nc0_SP7nc3_line2, M7_GSP12_SP9nc0_SP7nc3_line3, M7_GSP12_SP9nc0_line3); inv M7_GSP12_SP9nc0_SP7nc4_Xo0(PropXbus_28, M7_GSP12_SP9nc0_SP7nc4_NotA); inv M7_GSP12_SP9nc0_SP7nc4_Xo1(M7_GSP12_SP9nc0_line3, M7_GSP12_SP9nc0_SP7nc4_NotB); nand2 M7_GSP12_SP9nc0_SP7nc4_Xo2(M7_GSP12_SP9nc0_SP7nc4_NotA, M7_GSP12_SP9nc0_line3, M7_GSP12_SP9nc0_SP7nc4_line2); nand2 M7_GSP12_SP9nc0_SP7nc4_Xo3(M7_GSP12_SP9nc0_SP7nc4_NotB, PropXbus_28, M7_GSP12_SP9nc0_SP7nc4_line3); nand2 M7_GSP12_SP9nc0_SP7nc4_Xo4(M7_GSP12_SP9nc0_SP7nc4_line2, M7_GSP12_SP9nc0_SP7nc4_line3, M7_GSP12_SP9nc0_line4); inv M7_GSP12_SP9nc0_SP7nc5_Xo0(PropXbus_29, M7_GSP12_SP9nc0_SP7nc5_NotA); inv M7_GSP12_SP9nc0_SP7nc5_Xo1(M7_GSP12_SP9nc0_line4, M7_GSP12_SP9nc0_SP7nc5_NotB); nand2 M7_GSP12_SP9nc0_SP7nc5_Xo2(M7_GSP12_SP9nc0_SP7nc5_NotA, M7_GSP12_SP9nc0_line4, M7_GSP12_SP9nc0_SP7nc5_line2); nand2 M7_GSP12_SP9nc0_SP7nc5_Xo3(M7_GSP12_SP9nc0_SP7nc5_NotB, PropXbus_29, M7_GSP12_SP9nc0_SP7nc5_line3); nand2 M7_GSP12_SP9nc0_SP7nc5_Xo4(M7_GSP12_SP9nc0_SP7nc5_line2, M7_GSP12_SP9nc0_SP7nc5_line3, M7_GSP12_line0); inv M7_GSP12_SP9nc1_Xo0(PropXbus_30, M7_GSP12_SP9nc1_NotA); inv M7_GSP12_SP9nc1_Xo1(M7_GSP12_line0, M7_GSP12_SP9nc1_NotB); nand2 M7_GSP12_SP9nc1_Xo2(M7_GSP12_SP9nc1_NotA, M7_GSP12_line0, M7_GSP12_SP9nc1_line2); nand2 M7_GSP12_SP9nc1_Xo3(M7_GSP12_SP9nc1_NotB, PropXbus_30, M7_GSP12_SP9nc1_line3); nand2 M7_GSP12_SP9nc1_Xo4(M7_GSP12_SP9nc1_line2, M7_GSP12_SP9nc1_line3, M7_GSP12_line1); inv M7_GSP12_SP9nc2_Xo0(PropXbus_31, M7_GSP12_SP9nc2_NotA); inv M7_GSP12_SP9nc2_Xo1(M7_GSP12_line1, M7_GSP12_SP9nc2_NotB); nand2 M7_GSP12_SP9nc2_Xo2(M7_GSP12_SP9nc2_NotA, M7_GSP12_line1, M7_GSP12_SP9nc2_line2); nand2 M7_GSP12_SP9nc2_Xo3(M7_GSP12_SP9nc2_NotB, PropXbus_31, M7_GSP12_SP9nc2_line3); nand2 M7_GSP12_SP9nc2_Xo4(M7_GSP12_SP9nc2_line2, M7_GSP12_SP9nc2_line3, M7_ParCin0b31_27); inv M7_GSP13_SP9nc0_SP7c0(PropXbus_29, M7_GSP13_SP9nc0_NewInbus_6); inv M7_GSP13_SP9nc0_SP7c2_SP7nc0_Xo0(LocalCarryXCin1_27, M7_GSP13_SP9nc0_SP7c2_SP7nc0_NotA); inv M7_GSP13_SP9nc0_SP7c2_SP7nc0_Xo1(LocalCarryXCin1_28, M7_GSP13_SP9nc0_SP7c2_SP7nc0_NotB); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc0_Xo2(M7_GSP13_SP9nc0_SP7c2_SP7nc0_NotA, LocalCarryXCin1_28, M7_GSP13_SP9nc0_SP7c2_SP7nc0_line2); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc0_Xo3(M7_GSP13_SP9nc0_SP7c2_SP7nc0_NotB, LocalCarryXCin1_27, M7_GSP13_SP9nc0_SP7c2_SP7nc0_line3); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc0_Xo4(M7_GSP13_SP9nc0_SP7c2_SP7nc0_line2, M7_GSP13_SP9nc0_SP7c2_SP7nc0_line3, M7_GSP13_SP9nc0_SP7c2_line0); inv M7_GSP13_SP9nc0_SP7c2_SP7nc1_Xo0(LocalCarryXCin1_29, M7_GSP13_SP9nc0_SP7c2_SP7nc1_NotA); inv M7_GSP13_SP9nc0_SP7c2_SP7nc1_Xo1(M7_GSP13_SP9nc0_SP7c2_line0, M7_GSP13_SP9nc0_SP7c2_SP7nc1_NotB); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc1_Xo2(M7_GSP13_SP9nc0_SP7c2_SP7nc1_NotA, M7_GSP13_SP9nc0_SP7c2_line0, M7_GSP13_SP9nc0_SP7c2_SP7nc1_line2); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc1_Xo3(M7_GSP13_SP9nc0_SP7c2_SP7nc1_NotB, LocalCarryXCin1_29, M7_GSP13_SP9nc0_SP7c2_SP7nc1_line3); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc1_Xo4(M7_GSP13_SP9nc0_SP7c2_SP7nc1_line2, M7_GSP13_SP9nc0_SP7c2_SP7nc1_line3, M7_GSP13_SP9nc0_SP7c2_line1); inv M7_GSP13_SP9nc0_SP7c2_SP7nc2_Xo0(LocalCarryXCin1_30, M7_GSP13_SP9nc0_SP7c2_SP7nc2_NotA); inv M7_GSP13_SP9nc0_SP7c2_SP7nc2_Xo1(M7_GSP13_SP9nc0_SP7c2_line1, M7_GSP13_SP9nc0_SP7c2_SP7nc2_NotB); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc2_Xo2(M7_GSP13_SP9nc0_SP7c2_SP7nc2_NotA, M7_GSP13_SP9nc0_SP7c2_line1, M7_GSP13_SP9nc0_SP7c2_SP7nc2_line2); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc2_Xo3(M7_GSP13_SP9nc0_SP7c2_SP7nc2_NotB, LocalCarryXCin1_30, M7_GSP13_SP9nc0_SP7c2_SP7nc2_line3); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc2_Xo4(M7_GSP13_SP9nc0_SP7c2_SP7nc2_line2, M7_GSP13_SP9nc0_SP7c2_SP7nc2_line3, M7_GSP13_SP9nc0_SP7c2_line2); inv M7_GSP13_SP9nc0_SP7c2_SP7nc3_Xo0(PropXbus_27, M7_GSP13_SP9nc0_SP7c2_SP7nc3_NotA); inv M7_GSP13_SP9nc0_SP7c2_SP7nc3_Xo1(M7_GSP13_SP9nc0_SP7c2_line2, M7_GSP13_SP9nc0_SP7c2_SP7nc3_NotB); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc3_Xo2(M7_GSP13_SP9nc0_SP7c2_SP7nc3_NotA, M7_GSP13_SP9nc0_SP7c2_line2, M7_GSP13_SP9nc0_SP7c2_SP7nc3_line2); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc3_Xo3(M7_GSP13_SP9nc0_SP7c2_SP7nc3_NotB, PropXbus_27, M7_GSP13_SP9nc0_SP7c2_SP7nc3_line3); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc3_Xo4(M7_GSP13_SP9nc0_SP7c2_SP7nc3_line2, M7_GSP13_SP9nc0_SP7c2_SP7nc3_line3, M7_GSP13_SP9nc0_SP7c2_line3); inv M7_GSP13_SP9nc0_SP7c2_SP7nc4_Xo0(PropXbus_28, M7_GSP13_SP9nc0_SP7c2_SP7nc4_NotA); inv M7_GSP13_SP9nc0_SP7c2_SP7nc4_Xo1(M7_GSP13_SP9nc0_SP7c2_line3, M7_GSP13_SP9nc0_SP7c2_SP7nc4_NotB); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc4_Xo2(M7_GSP13_SP9nc0_SP7c2_SP7nc4_NotA, M7_GSP13_SP9nc0_SP7c2_line3, M7_GSP13_SP9nc0_SP7c2_SP7nc4_line2); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc4_Xo3(M7_GSP13_SP9nc0_SP7c2_SP7nc4_NotB, PropXbus_28, M7_GSP13_SP9nc0_SP7c2_SP7nc4_line3); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc4_Xo4(M7_GSP13_SP9nc0_SP7c2_SP7nc4_line2, M7_GSP13_SP9nc0_SP7c2_SP7nc4_line3, M7_GSP13_SP9nc0_SP7c2_line4); inv M7_GSP13_SP9nc0_SP7c2_SP7nc5_Xo0(M7_GSP13_SP9nc0_NewInbus_6, M7_GSP13_SP9nc0_SP7c2_SP7nc5_NotA); inv M7_GSP13_SP9nc0_SP7c2_SP7nc5_Xo1(M7_GSP13_SP9nc0_SP7c2_line4, M7_GSP13_SP9nc0_SP7c2_SP7nc5_NotB); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc5_Xo2(M7_GSP13_SP9nc0_SP7c2_SP7nc5_NotA, M7_GSP13_SP9nc0_SP7c2_line4, M7_GSP13_SP9nc0_SP7c2_SP7nc5_line2); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc5_Xo3(M7_GSP13_SP9nc0_SP7c2_SP7nc5_NotB, M7_GSP13_SP9nc0_NewInbus_6, M7_GSP13_SP9nc0_SP7c2_SP7nc5_line3); nand2 M7_GSP13_SP9nc0_SP7c2_SP7nc5_Xo4(M7_GSP13_SP9nc0_SP7c2_SP7nc5_line2, M7_GSP13_SP9nc0_SP7c2_SP7nc5_line3, M7_GSP13_line0); inv M7_GSP13_SP9nc1_Xo0(PropXbus_30, M7_GSP13_SP9nc1_NotA); inv M7_GSP13_SP9nc1_Xo1(M7_GSP13_line0, M7_GSP13_SP9nc1_NotB); nand2 M7_GSP13_SP9nc1_Xo2(M7_GSP13_SP9nc1_NotA, M7_GSP13_line0, M7_GSP13_SP9nc1_line2); nand2 M7_GSP13_SP9nc1_Xo3(M7_GSP13_SP9nc1_NotB, PropXbus_30, M7_GSP13_SP9nc1_line3); nand2 M7_GSP13_SP9nc1_Xo4(M7_GSP13_SP9nc1_line2, M7_GSP13_SP9nc1_line3, M7_GSP13_line1); inv M7_GSP13_SP9nc2_Xo0(PropXbus_31, M7_GSP13_SP9nc2_NotA); inv M7_GSP13_SP9nc2_Xo1(M7_GSP13_line1, M7_GSP13_SP9nc2_NotB); nand2 M7_GSP13_SP9nc2_Xo2(M7_GSP13_SP9nc2_NotA, M7_GSP13_line1, M7_GSP13_SP9nc2_line2); nand2 M7_GSP13_SP9nc2_Xo3(M7_GSP13_SP9nc2_NotB, PropXbus_31, M7_GSP13_SP9nc2_line3); nand2 M7_GSP13_SP9nc2_Xo4(M7_GSP13_SP9nc2_line2, M7_GSP13_SP9nc2_line3, M7_ParCin1b31_27); inv M7_GSP14_SP3nc0_Xo0(M5_GenXbus_32, M7_GSP14_SP3nc0_NotA); inv M7_GSP14_SP3nc0_Xo1(PropXbus_32, M7_GSP14_SP3nc0_NotB); nand2 M7_GSP14_SP3nc0_Xo2(M7_GSP14_SP3nc0_NotA, PropXbus_32, M7_GSP14_SP3nc0_line2); nand2 M7_GSP14_SP3nc0_Xo3(M7_GSP14_SP3nc0_NotB, M5_GenXbus_32, M7_GSP14_SP3nc0_line3); nand2 M7_GSP14_SP3nc0_Xo4(M7_GSP14_SP3nc0_line2, M7_GSP14_SP3nc0_line3, M7_GSP14_line0); inv M7_GSP14_SP3nc1_Xo0(PropXbus_33, M7_GSP14_SP3nc1_NotA); inv M7_GSP14_SP3nc1_Xo1(M7_GSP14_line0, M7_GSP14_SP3nc1_NotB); nand2 M7_GSP14_SP3nc1_Xo2(M7_GSP14_SP3nc1_NotA, M7_GSP14_line0, M7_GSP14_SP3nc1_line2); nand2 M7_GSP14_SP3nc1_Xo3(M7_GSP14_SP3nc1_NotB, PropXbus_33, M7_GSP14_SP3nc1_line3); nand2 M7_GSP14_SP3nc1_Xo4(M7_GSP14_SP3nc1_line2, M7_GSP14_SP3nc1_line3, M7_ParCin0b33_32); inv M7_GSP15_SP3c0(PropXbus_33, M7_GSP15_NotIn2); inv M7_GSP15_SP3c1_Xo0(LocalCarryXCin1_32, M7_GSP15_SP3c1_NotA); inv M7_GSP15_SP3c1_Xo1(PropXbus_32, M7_GSP15_SP3c1_NotB); nand2 M7_GSP15_SP3c1_Xo2(M7_GSP15_SP3c1_NotA, PropXbus_32, M7_GSP15_SP3c1_line2); nand2 M7_GSP15_SP3c1_Xo3(M7_GSP15_SP3c1_NotB, LocalCarryXCin1_32, M7_GSP15_SP3c1_line3); nand2 M7_GSP15_SP3c1_Xo4(M7_GSP15_SP3c1_line2, M7_GSP15_SP3c1_line3, M7_GSP15_line1); inv M7_GSP15_SP3c2_Xo0(M7_GSP15_NotIn2, M7_GSP15_SP3c2_NotA); inv M7_GSP15_SP3c2_Xo1(M7_GSP15_line1, M7_GSP15_SP3c2_NotB); nand2 M7_GSP15_SP3c2_Xo2(M7_GSP15_SP3c2_NotA, M7_GSP15_line1, M7_GSP15_SP3c2_line2); nand2 M7_GSP15_SP3c2_Xo3(M7_GSP15_SP3c2_NotB, M7_GSP15_NotIn2, M7_GSP15_SP3c2_line3); nand2 M7_GSP15_SP3c2_Xo4(M7_GSP15_SP3c2_line2, M7_GSP15_SP3c2_line3, M7_ParCin1b33_32armut); inv M7_GSP16_SPar0_Mux0(in4526, M7_GSP16_SPar0_Not_ContIn); and2 M7_GSP16_SPar0_Mux1(M7_ParCin0b4_0, M7_GSP16_SPar0_Not_ContIn, M7_GSP16_SPar0_line1); and2 M7_GSP16_SPar0_Mux2(M7_ParCin1b4_0, in4526, M7_GSP16_SPar0_line2); or2 M7_GSP16_SPar0_Mux3(M7_GSP16_SPar0_line1, M7_GSP16_SPar0_line2, M7_GSP16_line0); inv M7_GSP16_SPar1_Mux0(LocalCarryXCin0_4, M7_GSP16_SPar1_Not_ContIn); and2 M7_GSP16_SPar1_Mux1(M7_ParCin0b8_5, M7_GSP16_SPar1_Not_ContIn, M7_GSP16_SPar1_line1); and2 M7_GSP16_SPar1_Mux2(M7_ParCin1b8_5, LocalCarryXCin0_4, M7_GSP16_SPar1_line2); or2 M7_GSP16_SPar1_Mux3(M7_GSP16_SPar1_line1, M7_GSP16_SPar1_line2, M7_GSP16_line1); inv M7_GSP16_SPar2_Mux0(LocalCarryXCin1_4, M7_GSP16_SPar2_Not_ContIn); and2 M7_GSP16_SPar2_Mux1(M7_ParCin0b8_5, M7_GSP16_SPar2_Not_ContIn, M7_GSP16_SPar2_line1); and2 M7_GSP16_SPar2_Mux2(M7_ParCin1b8_5, LocalCarryXCin1_4, M7_GSP16_SPar2_line2); or2 M7_GSP16_SPar2_Mux3(M7_GSP16_SPar2_line1, M7_GSP16_SPar2_line2, M7_GSP16_line2); inv M7_GSP16_SPar3_Mux0(in4526, M7_GSP16_SPar3_Not_ContIn); and2 M7_GSP16_SPar3_Mux1(M7_GSP16_line1, M7_GSP16_SPar3_Not_ContIn, M7_GSP16_SPar3_line1); and2 M7_GSP16_SPar3_Mux2(M7_GSP16_line2, in4526, M7_GSP16_SPar3_line2); or2 M7_GSP16_SPar3_Mux3(M7_GSP16_SPar3_line1, M7_GSP16_SPar3_line2, M7_GSP16_line3); inv M7_GSP16_SPar4_Xo0(M7_GSP16_line0, M7_GSP16_SPar4_NotA); inv M7_GSP16_SPar4_Xo1(M7_GSP16_line3, M7_GSP16_SPar4_NotB); nand2 M7_GSP16_SPar4_Xo2(M7_GSP16_SPar4_NotA, M7_GSP16_line3, M7_GSP16_SPar4_line2); nand2 M7_GSP16_SPar4_Xo3(M7_GSP16_SPar4_NotB, M7_GSP16_line0, M7_GSP16_SPar4_line3); nand2 M7_GSP16_SPar4_Xo4(M7_GSP16_SPar4_line2, M7_GSP16_SPar4_line3, M7_GSP16_line4); inv M7_GSP16_SPar5(M7_GSP16_line4, out399); inv M7_GSP17_SPar0_Mux0(CarryXbus_8, M7_GSP17_SPar0_Not_ContIn); and2 M7_GSP17_SPar0_Mux1(M7_ParCin0b13_9, M7_GSP17_SPar0_Not_ContIn, M7_GSP17_SPar0_line1); and2 M7_GSP17_SPar0_Mux2(M7_ParCin1b13_9, CarryXbus_8, M7_GSP17_SPar0_line2); or2 M7_GSP17_SPar0_Mux3(M7_GSP17_SPar0_line1, M7_GSP17_SPar0_line2, M7_GSP17_line0); inv M7_GSP17_SPar1_Mux0(LocalCarryXCin0_13, M7_GSP17_SPar1_Not_ContIn); and2 M7_GSP17_SPar1_Mux1(M7_ParCin0b17_14, M7_GSP17_SPar1_Not_ContIn, M7_GSP17_SPar1_line1); and2 M7_GSP17_SPar1_Mux2(M7_ParCin1b17_14, LocalCarryXCin0_13, M7_GSP17_SPar1_line2); or2 M7_GSP17_SPar1_Mux3(M7_GSP17_SPar1_line1, M7_GSP17_SPar1_line2, M7_GSP17_line1); inv M7_GSP17_SPar2_Mux0(LocalCarryXCin1_13, M7_GSP17_SPar2_Not_ContIn); and2 M7_GSP17_SPar2_Mux1(M7_ParCin0b17_14, M7_GSP17_SPar2_Not_ContIn, M7_GSP17_SPar2_line1); and2 M7_GSP17_SPar2_Mux2(M7_ParCin1b17_14, LocalCarryXCin1_13, M7_GSP17_SPar2_line2); or2 M7_GSP17_SPar2_Mux3(M7_GSP17_SPar2_line1, M7_GSP17_SPar2_line2, M7_GSP17_line2); inv M7_GSP17_SPar3_Mux0(CarryXbus_8, M7_GSP17_SPar3_Not_ContIn); and2 M7_GSP17_SPar3_Mux1(M7_GSP17_line1, M7_GSP17_SPar3_Not_ContIn, M7_GSP17_SPar3_line1); and2 M7_GSP17_SPar3_Mux2(M7_GSP17_line2, CarryXbus_8, M7_GSP17_SPar3_line2); or2 M7_GSP17_SPar3_Mux3(M7_GSP17_SPar3_line1, M7_GSP17_SPar3_line2, M7_GSP17_line3); inv M7_GSP17_SPar4_Xo0(M7_GSP17_line0, M7_GSP17_SPar4_NotA); inv M7_GSP17_SPar4_Xo1(M7_GSP17_line3, M7_GSP17_SPar4_NotB); nand2 M7_GSP17_SPar4_Xo2(M7_GSP17_SPar4_NotA, M7_GSP17_line3, M7_GSP17_SPar4_line2); nand2 M7_GSP17_SPar4_Xo3(M7_GSP17_SPar4_NotB, M7_GSP17_line0, M7_GSP17_SPar4_line3); nand2 M7_GSP17_SPar4_Xo4(M7_GSP17_SPar4_line2, M7_GSP17_SPar4_line3, M7_GSP17_line4); inv M7_GSP17_SPar5(M7_GSP17_line4, out370); inv M7_GSP18_SPar0_Mux0(CarryXbus_17, M7_GSP18_SPar0_Not_ContIn); and2 M7_GSP18_SPar0_Mux1(M7_ParCin0b22_18, M7_GSP18_SPar0_Not_ContIn, M7_GSP18_SPar0_line1); and2 M7_GSP18_SPar0_Mux2(M7_ParCin1b22_18, CarryXbus_17, M7_GSP18_SPar0_line2); or2 M7_GSP18_SPar0_Mux3(M7_GSP18_SPar0_line1, M7_GSP18_SPar0_line2, M7_GSP18_line0); inv M7_GSP18_SPar1_Mux0(LocalCarryXCin0_22, M7_GSP18_SPar1_Not_ContIn); and2 M7_GSP18_SPar1_Mux1(M7_ParCin0b26_23, M7_GSP18_SPar1_Not_ContIn, M7_GSP18_SPar1_line1); and2 M7_GSP18_SPar1_Mux2(M7_ParCin1b26_23, LocalCarryXCin0_22, M7_GSP18_SPar1_line2); or2 M7_GSP18_SPar1_Mux3(M7_GSP18_SPar1_line1, M7_GSP18_SPar1_line2, M7_GSP18_line1); inv M7_GSP18_SPar2_Mux0(LocalCarryXCin1_22, M7_GSP18_SPar2_Not_ContIn); and2 M7_GSP18_SPar2_Mux1(M7_ParCin0b26_23, M7_GSP18_SPar2_Not_ContIn, M7_GSP18_SPar2_line1); and2 M7_GSP18_SPar2_Mux2(M7_ParCin1b26_23, LocalCarryXCin1_22, M7_GSP18_SPar2_line2); or2 M7_GSP18_SPar2_Mux3(M7_GSP18_SPar2_line1, M7_GSP18_SPar2_line2, M7_GSP18_line2); inv M7_GSP18_SPar3_Mux0(CarryXbus_17, M7_GSP18_SPar3_Not_ContIn); and2 M7_GSP18_SPar3_Mux1(M7_GSP18_line1, M7_GSP18_SPar3_Not_ContIn, M7_GSP18_SPar3_line1); and2 M7_GSP18_SPar3_Mux2(M7_GSP18_line2, CarryXbus_17, M7_GSP18_SPar3_line2); or2 M7_GSP18_SPar3_Mux3(M7_GSP18_SPar3_line1, M7_GSP18_SPar3_line2, M7_GSP18_line3); inv M7_GSP18_SPar4_Xo0(M7_GSP18_line0, M7_GSP18_SPar4_NotA); inv M7_GSP18_SPar4_Xo1(M7_GSP18_line3, M7_GSP18_SPar4_NotB); nand2 M7_GSP18_SPar4_Xo2(M7_GSP18_SPar4_NotA, M7_GSP18_line3, M7_GSP18_SPar4_line2); nand2 M7_GSP18_SPar4_Xo3(M7_GSP18_SPar4_NotB, M7_GSP18_line0, M7_GSP18_SPar4_line3); nand2 M7_GSP18_SPar4_Xo4(M7_GSP18_SPar4_line2, M7_GSP18_SPar4_line3, M7_GSP18_line4); inv M7_GSP18_SPar5(M7_GSP18_line4, out321); inv M7_GSP19_SPar0_Mux0(CarryXbus_26, M7_GSP19_SPar0_Not_ContIn); and2 M7_GSP19_SPar0_Mux1(M7_ParCin0b31_27, M7_GSP19_SPar0_Not_ContIn, M7_GSP19_SPar0_line1); and2 M7_GSP19_SPar0_Mux2(M7_ParCin1b31_27, CarryXbus_26, M7_GSP19_SPar0_line2); or2 M7_GSP19_SPar0_Mux3(M7_GSP19_SPar0_line1, M7_GSP19_SPar0_line2, M7_GSP19_line0); inv M7_GSP19_SPar1_Mux0(LocalCarryXCin0_31, M7_GSP19_SPar1_Not_ContIn); and2 M7_GSP19_SPar1_Mux1(M7_ParCin0b33_32, M7_GSP19_SPar1_Not_ContIn, M7_GSP19_SPar1_line1); and2 M7_GSP19_SPar1_Mux2(M7_ParCin1b33_32armut, LocalCarryXCin0_31, M7_GSP19_SPar1_line2); or2 M7_GSP19_SPar1_Mux3(M7_GSP19_SPar1_line1, M7_GSP19_SPar1_line2, M7_GSP19_line1); inv M7_GSP19_SPar2_Mux0(LocalCarryXCin1_31, M7_GSP19_SPar2_Not_ContIn); and2 M7_GSP19_SPar2_Mux1(M7_ParCin0b33_32, M7_GSP19_SPar2_Not_ContIn, M7_GSP19_SPar2_line1); and2 M7_GSP19_SPar2_Mux2(M7_ParCin1b33_32armut, LocalCarryXCin1_31, M7_GSP19_SPar2_line2); or2 M7_GSP19_SPar2_Mux3(M7_GSP19_SPar2_line1, M7_GSP19_SPar2_line2, M7_GSP19_line2); inv M7_GSP19_SPar3_Mux0(CarryXbus_26, M7_GSP19_SPar3_Not_ContIn); and2 M7_GSP19_SPar3_Mux1(M7_GSP19_line1, M7_GSP19_SPar3_Not_ContIn, M7_GSP19_SPar3_line1); and2 M7_GSP19_SPar3_Mux2(M7_GSP19_line2, CarryXbus_26, M7_GSP19_SPar3_line2); or2 M7_GSP19_SPar3_Mux3(M7_GSP19_SPar3_line1, M7_GSP19_SPar3_line2, M7_GSP19_line3); inv M7_GSP19_SPar4_Xo0(M7_GSP19_line0, M7_GSP19_SPar4_NotA); inv M7_GSP19_SPar4_Xo1(M7_GSP19_line3, M7_GSP19_SPar4_NotB); nand2 M7_GSP19_SPar4_Xo2(M7_GSP19_SPar4_NotA, M7_GSP19_line3, M7_GSP19_SPar4_line2); nand2 M7_GSP19_SPar4_Xo3(M7_GSP19_SPar4_NotB, M7_GSP19_line0, M7_GSP19_SPar4_line3); nand2 M7_GSP19_SPar4_Xo4(M7_GSP19_SPar4_line2, M7_GSP19_SPar4_line3, M7_GSP19_line4); inv M7_GSP19_SPar5(M7_GSP19_line4, out338); and2 M8_UM8_0_GP34_0_GenProp8_0(YAbus_0, YBbus_0, M8_GenYbus_0); and2 M8_UM8_0_GP34_0_GenProp8_1(YAbus_1, YBbus_1, M8_GenYbus_1); and2 M8_UM8_0_GP34_0_GenProp8_2(YAbus_2, YBbus_2, M8_GenYbus_2); and2 M8_UM8_0_GP34_0_GenProp8_3(YAbus_3, YBbus_3, M8_GenYbus_3); and2 M8_UM8_0_GP34_0_GenProp8_4(YAbus_4, YBbus_4, M8_GenYbus_4); and2 M8_UM8_0_GP34_0_GenProp8_5(YAbus_5, YBbus_5, M8_GenYbus_5); and2 M8_UM8_0_GP34_0_GenProp8_6(YAbus_6, YBbus_6, M8_GenYbus_6); and2 M8_UM8_0_GP34_0_GenProp8_7(YAbus_7, YBbus_7, M8_GenYbus_7); inv M8_UM8_0_GP34_0_GenProp8_8_Xo0(YAbus_0, M8_UM8_0_GP34_0_GenProp8_8_NotA); inv M8_UM8_0_GP34_0_GenProp8_8_Xo1(YBbus_0, M8_UM8_0_GP34_0_GenProp8_8_NotB); nand2 M8_UM8_0_GP34_0_GenProp8_8_Xo2(M8_UM8_0_GP34_0_GenProp8_8_NotA, YBbus_0, M8_UM8_0_GP34_0_GenProp8_8_line2); nand2 M8_UM8_0_GP34_0_GenProp8_8_Xo3(M8_UM8_0_GP34_0_GenProp8_8_NotB, YAbus_0, M8_UM8_0_GP34_0_GenProp8_8_line3); nand2 M8_UM8_0_GP34_0_GenProp8_8_Xo4(M8_UM8_0_GP34_0_GenProp8_8_line2, M8_UM8_0_GP34_0_GenProp8_8_line3, M8_PropYbus_0); inv M8_UM8_0_GP34_0_GenProp8_9_Xo0(YAbus_1, M8_UM8_0_GP34_0_GenProp8_9_NotA); inv M8_UM8_0_GP34_0_GenProp8_9_Xo1(YBbus_1, M8_UM8_0_GP34_0_GenProp8_9_NotB); nand2 M8_UM8_0_GP34_0_GenProp8_9_Xo2(M8_UM8_0_GP34_0_GenProp8_9_NotA, YBbus_1, M8_UM8_0_GP34_0_GenProp8_9_line2); nand2 M8_UM8_0_GP34_0_GenProp8_9_Xo3(M8_UM8_0_GP34_0_GenProp8_9_NotB, YAbus_1, M8_UM8_0_GP34_0_GenProp8_9_line3); nand2 M8_UM8_0_GP34_0_GenProp8_9_Xo4(M8_UM8_0_GP34_0_GenProp8_9_line2, M8_UM8_0_GP34_0_GenProp8_9_line3, M8_PropYbus_1); inv M8_UM8_0_GP34_0_GenProp8_10_Xo0(YAbus_2, M8_UM8_0_GP34_0_GenProp8_10_NotA); inv M8_UM8_0_GP34_0_GenProp8_10_Xo1(YBbus_2, M8_UM8_0_GP34_0_GenProp8_10_NotB); nand2 M8_UM8_0_GP34_0_GenProp8_10_Xo2(M8_UM8_0_GP34_0_GenProp8_10_NotA, YBbus_2, M8_UM8_0_GP34_0_GenProp8_10_line2); nand2 M8_UM8_0_GP34_0_GenProp8_10_Xo3(M8_UM8_0_GP34_0_GenProp8_10_NotB, YAbus_2, M8_UM8_0_GP34_0_GenProp8_10_line3); nand2 M8_UM8_0_GP34_0_GenProp8_10_Xo4(M8_UM8_0_GP34_0_GenProp8_10_line2, M8_UM8_0_GP34_0_GenProp8_10_line3, M8_PropYbus_2); inv M8_UM8_0_GP34_0_GenProp8_11_Xo0(YAbus_3, M8_UM8_0_GP34_0_GenProp8_11_NotA); inv M8_UM8_0_GP34_0_GenProp8_11_Xo1(YBbus_3, M8_UM8_0_GP34_0_GenProp8_11_NotB); nand2 M8_UM8_0_GP34_0_GenProp8_11_Xo2(M8_UM8_0_GP34_0_GenProp8_11_NotA, YBbus_3, M8_UM8_0_GP34_0_GenProp8_11_line2); nand2 M8_UM8_0_GP34_0_GenProp8_11_Xo3(M8_UM8_0_GP34_0_GenProp8_11_NotB, YAbus_3, M8_UM8_0_GP34_0_GenProp8_11_line3); nand2 M8_UM8_0_GP34_0_GenProp8_11_Xo4(M8_UM8_0_GP34_0_GenProp8_11_line2, M8_UM8_0_GP34_0_GenProp8_11_line3, M8_PropYbus_3); inv M8_UM8_0_GP34_0_GenProp8_12_Xo0(YAbus_4, M8_UM8_0_GP34_0_GenProp8_12_NotA); inv M8_UM8_0_GP34_0_GenProp8_12_Xo1(YBbus_4, M8_UM8_0_GP34_0_GenProp8_12_NotB); nand2 M8_UM8_0_GP34_0_GenProp8_12_Xo2(M8_UM8_0_GP34_0_GenProp8_12_NotA, YBbus_4, M8_UM8_0_GP34_0_GenProp8_12_line2); nand2 M8_UM8_0_GP34_0_GenProp8_12_Xo3(M8_UM8_0_GP34_0_GenProp8_12_NotB, YAbus_4, M8_UM8_0_GP34_0_GenProp8_12_line3); nand2 M8_UM8_0_GP34_0_GenProp8_12_Xo4(M8_UM8_0_GP34_0_GenProp8_12_line2, M8_UM8_0_GP34_0_GenProp8_12_line3, M8_PropYbus_4); inv M8_UM8_0_GP34_0_GenProp8_13_Xo0(YAbus_5, M8_UM8_0_GP34_0_GenProp8_13_NotA); inv M8_UM8_0_GP34_0_GenProp8_13_Xo1(YBbus_5, M8_UM8_0_GP34_0_GenProp8_13_NotB); nand2 M8_UM8_0_GP34_0_GenProp8_13_Xo2(M8_UM8_0_GP34_0_GenProp8_13_NotA, YBbus_5, M8_UM8_0_GP34_0_GenProp8_13_line2); nand2 M8_UM8_0_GP34_0_GenProp8_13_Xo3(M8_UM8_0_GP34_0_GenProp8_13_NotB, YAbus_5, M8_UM8_0_GP34_0_GenProp8_13_line3); nand2 M8_UM8_0_GP34_0_GenProp8_13_Xo4(M8_UM8_0_GP34_0_GenProp8_13_line2, M8_UM8_0_GP34_0_GenProp8_13_line3, M8_PropYbus_5); inv M8_UM8_0_GP34_0_GenProp8_14_Xo0(YAbus_6, M8_UM8_0_GP34_0_GenProp8_14_NotA); inv M8_UM8_0_GP34_0_GenProp8_14_Xo1(YBbus_6, M8_UM8_0_GP34_0_GenProp8_14_NotB); nand2 M8_UM8_0_GP34_0_GenProp8_14_Xo2(M8_UM8_0_GP34_0_GenProp8_14_NotA, YBbus_6, M8_UM8_0_GP34_0_GenProp8_14_line2); nand2 M8_UM8_0_GP34_0_GenProp8_14_Xo3(M8_UM8_0_GP34_0_GenProp8_14_NotB, YAbus_6, M8_UM8_0_GP34_0_GenProp8_14_line3); nand2 M8_UM8_0_GP34_0_GenProp8_14_Xo4(M8_UM8_0_GP34_0_GenProp8_14_line2, M8_UM8_0_GP34_0_GenProp8_14_line3, M8_PropYbus_6); inv M8_UM8_0_GP34_0_GenProp8_15_Xo0(YAbus_7, M8_UM8_0_GP34_0_GenProp8_15_NotA); inv M8_UM8_0_GP34_0_GenProp8_15_Xo1(YBbus_7, M8_UM8_0_GP34_0_GenProp8_15_NotB); nand2 M8_UM8_0_GP34_0_GenProp8_15_Xo2(M8_UM8_0_GP34_0_GenProp8_15_NotA, YBbus_7, M8_UM8_0_GP34_0_GenProp8_15_line2); nand2 M8_UM8_0_GP34_0_GenProp8_15_Xo3(M8_UM8_0_GP34_0_GenProp8_15_NotB, YAbus_7, M8_UM8_0_GP34_0_GenProp8_15_line3); nand2 M8_UM8_0_GP34_0_GenProp8_15_Xo4(M8_UM8_0_GP34_0_GenProp8_15_line2, M8_UM8_0_GP34_0_GenProp8_15_line3, M8_PropYbus_7); and2 M8_UM8_0_GP34_1_GenProp8_0(YAbus_8, YBbus_8, M8_GenYbus_8); and2 M8_UM8_0_GP34_1_GenProp8_1(YAbus_9, YBbus_9, M8_GenYbus_9); and2 M8_UM8_0_GP34_1_GenProp8_2(YAbus_10, YBbus_10, M8_GenYbus_10); and2 M8_UM8_0_GP34_1_GenProp8_3(YAbus_11, YBbus_11, M8_GenYbus_11); and2 M8_UM8_0_GP34_1_GenProp8_4(YAbus_12, YBbus_12, M8_GenYbus_12); and2 M8_UM8_0_GP34_1_GenProp8_5(YAbus_13, YBbus_13, M8_GenYbus_13); and2 M8_UM8_0_GP34_1_GenProp8_6(YAbus_14, YBbus_14, M8_GenYbus_14); and2 M8_UM8_0_GP34_1_GenProp8_7(YAbus_15, YBbus_15, M8_GenYbus_15); inv M8_UM8_0_GP34_1_GenProp8_8_Xo0(YAbus_8, M8_UM8_0_GP34_1_GenProp8_8_NotA); inv M8_UM8_0_GP34_1_GenProp8_8_Xo1(YBbus_8, M8_UM8_0_GP34_1_GenProp8_8_NotB); nand2 M8_UM8_0_GP34_1_GenProp8_8_Xo2(M8_UM8_0_GP34_1_GenProp8_8_NotA, YBbus_8, M8_UM8_0_GP34_1_GenProp8_8_line2); nand2 M8_UM8_0_GP34_1_GenProp8_8_Xo3(M8_UM8_0_GP34_1_GenProp8_8_NotB, YAbus_8, M8_UM8_0_GP34_1_GenProp8_8_line3); nand2 M8_UM8_0_GP34_1_GenProp8_8_Xo4(M8_UM8_0_GP34_1_GenProp8_8_line2, M8_UM8_0_GP34_1_GenProp8_8_line3, M8_PropYbus_8); inv M8_UM8_0_GP34_1_GenProp8_9_Xo0(YAbus_9, M8_UM8_0_GP34_1_GenProp8_9_NotA); inv M8_UM8_0_GP34_1_GenProp8_9_Xo1(YBbus_9, M8_UM8_0_GP34_1_GenProp8_9_NotB); nand2 M8_UM8_0_GP34_1_GenProp8_9_Xo2(M8_UM8_0_GP34_1_GenProp8_9_NotA, YBbus_9, M8_UM8_0_GP34_1_GenProp8_9_line2); nand2 M8_UM8_0_GP34_1_GenProp8_9_Xo3(M8_UM8_0_GP34_1_GenProp8_9_NotB, YAbus_9, M8_UM8_0_GP34_1_GenProp8_9_line3); nand2 M8_UM8_0_GP34_1_GenProp8_9_Xo4(M8_UM8_0_GP34_1_GenProp8_9_line2, M8_UM8_0_GP34_1_GenProp8_9_line3, M8_PropYbus_9); inv M8_UM8_0_GP34_1_GenProp8_10_Xo0(YAbus_10, M8_UM8_0_GP34_1_GenProp8_10_NotA); inv M8_UM8_0_GP34_1_GenProp8_10_Xo1(YBbus_10, M8_UM8_0_GP34_1_GenProp8_10_NotB); nand2 M8_UM8_0_GP34_1_GenProp8_10_Xo2(M8_UM8_0_GP34_1_GenProp8_10_NotA, YBbus_10, M8_UM8_0_GP34_1_GenProp8_10_line2); nand2 M8_UM8_0_GP34_1_GenProp8_10_Xo3(M8_UM8_0_GP34_1_GenProp8_10_NotB, YAbus_10, M8_UM8_0_GP34_1_GenProp8_10_line3); nand2 M8_UM8_0_GP34_1_GenProp8_10_Xo4(M8_UM8_0_GP34_1_GenProp8_10_line2, M8_UM8_0_GP34_1_GenProp8_10_line3, M8_PropYbus_10); inv M8_UM8_0_GP34_1_GenProp8_11_Xo0(YAbus_11, M8_UM8_0_GP34_1_GenProp8_11_NotA); inv M8_UM8_0_GP34_1_GenProp8_11_Xo1(YBbus_11, M8_UM8_0_GP34_1_GenProp8_11_NotB); nand2 M8_UM8_0_GP34_1_GenProp8_11_Xo2(M8_UM8_0_GP34_1_GenProp8_11_NotA, YBbus_11, M8_UM8_0_GP34_1_GenProp8_11_line2); nand2 M8_UM8_0_GP34_1_GenProp8_11_Xo3(M8_UM8_0_GP34_1_GenProp8_11_NotB, YAbus_11, M8_UM8_0_GP34_1_GenProp8_11_line3); nand2 M8_UM8_0_GP34_1_GenProp8_11_Xo4(M8_UM8_0_GP34_1_GenProp8_11_line2, M8_UM8_0_GP34_1_GenProp8_11_line3, M8_PropYbus_11); inv M8_UM8_0_GP34_1_GenProp8_12_Xo0(YAbus_12, M8_UM8_0_GP34_1_GenProp8_12_NotA); inv M8_UM8_0_GP34_1_GenProp8_12_Xo1(YBbus_12, M8_UM8_0_GP34_1_GenProp8_12_NotB); nand2 M8_UM8_0_GP34_1_GenProp8_12_Xo2(M8_UM8_0_GP34_1_GenProp8_12_NotA, YBbus_12, M8_UM8_0_GP34_1_GenProp8_12_line2); nand2 M8_UM8_0_GP34_1_GenProp8_12_Xo3(M8_UM8_0_GP34_1_GenProp8_12_NotB, YAbus_12, M8_UM8_0_GP34_1_GenProp8_12_line3); nand2 M8_UM8_0_GP34_1_GenProp8_12_Xo4(M8_UM8_0_GP34_1_GenProp8_12_line2, M8_UM8_0_GP34_1_GenProp8_12_line3, M8_PropYbus_12); inv M8_UM8_0_GP34_1_GenProp8_13_Xo0(YAbus_13, M8_UM8_0_GP34_1_GenProp8_13_NotA); inv M8_UM8_0_GP34_1_GenProp8_13_Xo1(YBbus_13, M8_UM8_0_GP34_1_GenProp8_13_NotB); nand2 M8_UM8_0_GP34_1_GenProp8_13_Xo2(M8_UM8_0_GP34_1_GenProp8_13_NotA, YBbus_13, M8_UM8_0_GP34_1_GenProp8_13_line2); nand2 M8_UM8_0_GP34_1_GenProp8_13_Xo3(M8_UM8_0_GP34_1_GenProp8_13_NotB, YAbus_13, M8_UM8_0_GP34_1_GenProp8_13_line3); nand2 M8_UM8_0_GP34_1_GenProp8_13_Xo4(M8_UM8_0_GP34_1_GenProp8_13_line2, M8_UM8_0_GP34_1_GenProp8_13_line3, M8_PropYbus_13); inv M8_UM8_0_GP34_1_GenProp8_14_Xo0(YAbus_14, M8_UM8_0_GP34_1_GenProp8_14_NotA); inv M8_UM8_0_GP34_1_GenProp8_14_Xo1(YBbus_14, M8_UM8_0_GP34_1_GenProp8_14_NotB); nand2 M8_UM8_0_GP34_1_GenProp8_14_Xo2(M8_UM8_0_GP34_1_GenProp8_14_NotA, YBbus_14, M8_UM8_0_GP34_1_GenProp8_14_line2); nand2 M8_UM8_0_GP34_1_GenProp8_14_Xo3(M8_UM8_0_GP34_1_GenProp8_14_NotB, YAbus_14, M8_UM8_0_GP34_1_GenProp8_14_line3); nand2 M8_UM8_0_GP34_1_GenProp8_14_Xo4(M8_UM8_0_GP34_1_GenProp8_14_line2, M8_UM8_0_GP34_1_GenProp8_14_line3, M8_PropYbus_14); inv M8_UM8_0_GP34_1_GenProp8_15_Xo0(YAbus_15, M8_UM8_0_GP34_1_GenProp8_15_NotA); inv M8_UM8_0_GP34_1_GenProp8_15_Xo1(YBbus_15, M8_UM8_0_GP34_1_GenProp8_15_NotB); nand2 M8_UM8_0_GP34_1_GenProp8_15_Xo2(M8_UM8_0_GP34_1_GenProp8_15_NotA, YBbus_15, M8_UM8_0_GP34_1_GenProp8_15_line2); nand2 M8_UM8_0_GP34_1_GenProp8_15_Xo3(M8_UM8_0_GP34_1_GenProp8_15_NotB, YAbus_15, M8_UM8_0_GP34_1_GenProp8_15_line3); nand2 M8_UM8_0_GP34_1_GenProp8_15_Xo4(M8_UM8_0_GP34_1_GenProp8_15_line2, M8_UM8_0_GP34_1_GenProp8_15_line3, M8_PropYbus_15); and2 M8_UM8_0_GP34_2_GenProp8_0(YAbus_16, YBbus_16, M8_GenYbus_16); and2 M8_UM8_0_GP34_2_GenProp8_1(YAbus_17, YBbus_17, M8_GenYbus_17); and2 M8_UM8_0_GP34_2_GenProp8_2(YAbus_18, YBbus_18, M8_GenYbus_18); and2 M8_UM8_0_GP34_2_GenProp8_3(YAbus_19, YBbus_19, M8_GenYbus_19); and2 M8_UM8_0_GP34_2_GenProp8_4(YAbus_20, YBbus_20, M8_GenYbus_20); and2 M8_UM8_0_GP34_2_GenProp8_5(YAbus_21, YBbus_21, M8_GenYbus_21); and2 M8_UM8_0_GP34_2_GenProp8_6(YAbus_22, YBbus_22, M8_GenYbus_22); and2 M8_UM8_0_GP34_2_GenProp8_7(YAbus_23, YBbus_23, M8_GenYbus_23); inv M8_UM8_0_GP34_2_GenProp8_8_Xo0(YAbus_16, M8_UM8_0_GP34_2_GenProp8_8_NotA); inv M8_UM8_0_GP34_2_GenProp8_8_Xo1(YBbus_16, M8_UM8_0_GP34_2_GenProp8_8_NotB); nand2 M8_UM8_0_GP34_2_GenProp8_8_Xo2(M8_UM8_0_GP34_2_GenProp8_8_NotA, YBbus_16, M8_UM8_0_GP34_2_GenProp8_8_line2); nand2 M8_UM8_0_GP34_2_GenProp8_8_Xo3(M8_UM8_0_GP34_2_GenProp8_8_NotB, YAbus_16, M8_UM8_0_GP34_2_GenProp8_8_line3); nand2 M8_UM8_0_GP34_2_GenProp8_8_Xo4(M8_UM8_0_GP34_2_GenProp8_8_line2, M8_UM8_0_GP34_2_GenProp8_8_line3, M8_PropYbus_16); inv M8_UM8_0_GP34_2_GenProp8_9_Xo0(YAbus_17, M8_UM8_0_GP34_2_GenProp8_9_NotA); inv M8_UM8_0_GP34_2_GenProp8_9_Xo1(YBbus_17, M8_UM8_0_GP34_2_GenProp8_9_NotB); nand2 M8_UM8_0_GP34_2_GenProp8_9_Xo2(M8_UM8_0_GP34_2_GenProp8_9_NotA, YBbus_17, M8_UM8_0_GP34_2_GenProp8_9_line2); nand2 M8_UM8_0_GP34_2_GenProp8_9_Xo3(M8_UM8_0_GP34_2_GenProp8_9_NotB, YAbus_17, M8_UM8_0_GP34_2_GenProp8_9_line3); nand2 M8_UM8_0_GP34_2_GenProp8_9_Xo4(M8_UM8_0_GP34_2_GenProp8_9_line2, M8_UM8_0_GP34_2_GenProp8_9_line3, M8_PropYbus_17); inv M8_UM8_0_GP34_2_GenProp8_10_Xo0(YAbus_18, M8_UM8_0_GP34_2_GenProp8_10_NotA); inv M8_UM8_0_GP34_2_GenProp8_10_Xo1(YBbus_18, M8_UM8_0_GP34_2_GenProp8_10_NotB); nand2 M8_UM8_0_GP34_2_GenProp8_10_Xo2(M8_UM8_0_GP34_2_GenProp8_10_NotA, YBbus_18, M8_UM8_0_GP34_2_GenProp8_10_line2); nand2 M8_UM8_0_GP34_2_GenProp8_10_Xo3(M8_UM8_0_GP34_2_GenProp8_10_NotB, YAbus_18, M8_UM8_0_GP34_2_GenProp8_10_line3); nand2 M8_UM8_0_GP34_2_GenProp8_10_Xo4(M8_UM8_0_GP34_2_GenProp8_10_line2, M8_UM8_0_GP34_2_GenProp8_10_line3, M8_PropYbus_18); inv M8_UM8_0_GP34_2_GenProp8_11_Xo0(YAbus_19, M8_UM8_0_GP34_2_GenProp8_11_NotA); inv M8_UM8_0_GP34_2_GenProp8_11_Xo1(YBbus_19, M8_UM8_0_GP34_2_GenProp8_11_NotB); nand2 M8_UM8_0_GP34_2_GenProp8_11_Xo2(M8_UM8_0_GP34_2_GenProp8_11_NotA, YBbus_19, M8_UM8_0_GP34_2_GenProp8_11_line2); nand2 M8_UM8_0_GP34_2_GenProp8_11_Xo3(M8_UM8_0_GP34_2_GenProp8_11_NotB, YAbus_19, M8_UM8_0_GP34_2_GenProp8_11_line3); nand2 M8_UM8_0_GP34_2_GenProp8_11_Xo4(M8_UM8_0_GP34_2_GenProp8_11_line2, M8_UM8_0_GP34_2_GenProp8_11_line3, M8_PropYbus_19); inv M8_UM8_0_GP34_2_GenProp8_12_Xo0(YAbus_20, M8_UM8_0_GP34_2_GenProp8_12_NotA); inv M8_UM8_0_GP34_2_GenProp8_12_Xo1(YBbus_20, M8_UM8_0_GP34_2_GenProp8_12_NotB); nand2 M8_UM8_0_GP34_2_GenProp8_12_Xo2(M8_UM8_0_GP34_2_GenProp8_12_NotA, YBbus_20, M8_UM8_0_GP34_2_GenProp8_12_line2); nand2 M8_UM8_0_GP34_2_GenProp8_12_Xo3(M8_UM8_0_GP34_2_GenProp8_12_NotB, YAbus_20, M8_UM8_0_GP34_2_GenProp8_12_line3); nand2 M8_UM8_0_GP34_2_GenProp8_12_Xo4(M8_UM8_0_GP34_2_GenProp8_12_line2, M8_UM8_0_GP34_2_GenProp8_12_line3, M8_PropYbus_20); inv M8_UM8_0_GP34_2_GenProp8_13_Xo0(YAbus_21, M8_UM8_0_GP34_2_GenProp8_13_NotA); inv M8_UM8_0_GP34_2_GenProp8_13_Xo1(YBbus_21, M8_UM8_0_GP34_2_GenProp8_13_NotB); nand2 M8_UM8_0_GP34_2_GenProp8_13_Xo2(M8_UM8_0_GP34_2_GenProp8_13_NotA, YBbus_21, M8_UM8_0_GP34_2_GenProp8_13_line2); nand2 M8_UM8_0_GP34_2_GenProp8_13_Xo3(M8_UM8_0_GP34_2_GenProp8_13_NotB, YAbus_21, M8_UM8_0_GP34_2_GenProp8_13_line3); nand2 M8_UM8_0_GP34_2_GenProp8_13_Xo4(M8_UM8_0_GP34_2_GenProp8_13_line2, M8_UM8_0_GP34_2_GenProp8_13_line3, M8_PropYbus_21); inv M8_UM8_0_GP34_2_GenProp8_14_Xo0(YAbus_22, M8_UM8_0_GP34_2_GenProp8_14_NotA); inv M8_UM8_0_GP34_2_GenProp8_14_Xo1(YBbus_22, M8_UM8_0_GP34_2_GenProp8_14_NotB); nand2 M8_UM8_0_GP34_2_GenProp8_14_Xo2(M8_UM8_0_GP34_2_GenProp8_14_NotA, YBbus_22, M8_UM8_0_GP34_2_GenProp8_14_line2); nand2 M8_UM8_0_GP34_2_GenProp8_14_Xo3(M8_UM8_0_GP34_2_GenProp8_14_NotB, YAbus_22, M8_UM8_0_GP34_2_GenProp8_14_line3); nand2 M8_UM8_0_GP34_2_GenProp8_14_Xo4(M8_UM8_0_GP34_2_GenProp8_14_line2, M8_UM8_0_GP34_2_GenProp8_14_line3, M8_PropYbus_22); inv M8_UM8_0_GP34_2_GenProp8_15_Xo0(YAbus_23, M8_UM8_0_GP34_2_GenProp8_15_NotA); inv M8_UM8_0_GP34_2_GenProp8_15_Xo1(YBbus_23, M8_UM8_0_GP34_2_GenProp8_15_NotB); nand2 M8_UM8_0_GP34_2_GenProp8_15_Xo2(M8_UM8_0_GP34_2_GenProp8_15_NotA, YBbus_23, M8_UM8_0_GP34_2_GenProp8_15_line2); nand2 M8_UM8_0_GP34_2_GenProp8_15_Xo3(M8_UM8_0_GP34_2_GenProp8_15_NotB, YAbus_23, M8_UM8_0_GP34_2_GenProp8_15_line3); nand2 M8_UM8_0_GP34_2_GenProp8_15_Xo4(M8_UM8_0_GP34_2_GenProp8_15_line2, M8_UM8_0_GP34_2_GenProp8_15_line3, M8_PropYbus_23); and2 M8_UM8_0_GP34_3_GenProp8_0(YAbus_24, YBbus_24, M8_GenYbus_24); and2 M8_UM8_0_GP34_3_GenProp8_1(YAbus_25, YBbus_25, M8_GenYbus_25); and2 M8_UM8_0_GP34_3_GenProp8_2(YAbus_26, YBbus_26, M8_GenYbus_26); and2 M8_UM8_0_GP34_3_GenProp8_3(YAbus_27, YBbus_27, M8_GenYbus_27); and2 M8_UM8_0_GP34_3_GenProp8_4(YAbus_28, YBbus_28, M8_GenYbus_28); and2 M8_UM8_0_GP34_3_GenProp8_5(YAbus_29, YBbus_29, M8_GenYbus_29); and2 M8_UM8_0_GP34_3_GenProp8_6(YAbus_30, YBbus_30, M8_GenYbus_30); and2 M8_UM8_0_GP34_3_GenProp8_7(YAbus_31, YBbus_31, M8_GenYbus_31); inv M8_UM8_0_GP34_3_GenProp8_8_Xo0(YAbus_24, M8_UM8_0_GP34_3_GenProp8_8_NotA); inv M8_UM8_0_GP34_3_GenProp8_8_Xo1(YBbus_24, M8_UM8_0_GP34_3_GenProp8_8_NotB); nand2 M8_UM8_0_GP34_3_GenProp8_8_Xo2(M8_UM8_0_GP34_3_GenProp8_8_NotA, YBbus_24, M8_UM8_0_GP34_3_GenProp8_8_line2); nand2 M8_UM8_0_GP34_3_GenProp8_8_Xo3(M8_UM8_0_GP34_3_GenProp8_8_NotB, YAbus_24, M8_UM8_0_GP34_3_GenProp8_8_line3); nand2 M8_UM8_0_GP34_3_GenProp8_8_Xo4(M8_UM8_0_GP34_3_GenProp8_8_line2, M8_UM8_0_GP34_3_GenProp8_8_line3, M8_PropYbus_24); inv M8_UM8_0_GP34_3_GenProp8_9_Xo0(YAbus_25, M8_UM8_0_GP34_3_GenProp8_9_NotA); inv M8_UM8_0_GP34_3_GenProp8_9_Xo1(YBbus_25, M8_UM8_0_GP34_3_GenProp8_9_NotB); nand2 M8_UM8_0_GP34_3_GenProp8_9_Xo2(M8_UM8_0_GP34_3_GenProp8_9_NotA, YBbus_25, M8_UM8_0_GP34_3_GenProp8_9_line2); nand2 M8_UM8_0_GP34_3_GenProp8_9_Xo3(M8_UM8_0_GP34_3_GenProp8_9_NotB, YAbus_25, M8_UM8_0_GP34_3_GenProp8_9_line3); nand2 M8_UM8_0_GP34_3_GenProp8_9_Xo4(M8_UM8_0_GP34_3_GenProp8_9_line2, M8_UM8_0_GP34_3_GenProp8_9_line3, M8_PropYbus_25); inv M8_UM8_0_GP34_3_GenProp8_10_Xo0(YAbus_26, M8_UM8_0_GP34_3_GenProp8_10_NotA); inv M8_UM8_0_GP34_3_GenProp8_10_Xo1(YBbus_26, M8_UM8_0_GP34_3_GenProp8_10_NotB); nand2 M8_UM8_0_GP34_3_GenProp8_10_Xo2(M8_UM8_0_GP34_3_GenProp8_10_NotA, YBbus_26, M8_UM8_0_GP34_3_GenProp8_10_line2); nand2 M8_UM8_0_GP34_3_GenProp8_10_Xo3(M8_UM8_0_GP34_3_GenProp8_10_NotB, YAbus_26, M8_UM8_0_GP34_3_GenProp8_10_line3); nand2 M8_UM8_0_GP34_3_GenProp8_10_Xo4(M8_UM8_0_GP34_3_GenProp8_10_line2, M8_UM8_0_GP34_3_GenProp8_10_line3, M8_PropYbus_26); inv M8_UM8_0_GP34_3_GenProp8_11_Xo0(YAbus_27, M8_UM8_0_GP34_3_GenProp8_11_NotA); inv M8_UM8_0_GP34_3_GenProp8_11_Xo1(YBbus_27, M8_UM8_0_GP34_3_GenProp8_11_NotB); nand2 M8_UM8_0_GP34_3_GenProp8_11_Xo2(M8_UM8_0_GP34_3_GenProp8_11_NotA, YBbus_27, M8_UM8_0_GP34_3_GenProp8_11_line2); nand2 M8_UM8_0_GP34_3_GenProp8_11_Xo3(M8_UM8_0_GP34_3_GenProp8_11_NotB, YAbus_27, M8_UM8_0_GP34_3_GenProp8_11_line3); nand2 M8_UM8_0_GP34_3_GenProp8_11_Xo4(M8_UM8_0_GP34_3_GenProp8_11_line2, M8_UM8_0_GP34_3_GenProp8_11_line3, M8_PropYbus_27); inv M8_UM8_0_GP34_3_GenProp8_12_Xo0(YAbus_28, M8_UM8_0_GP34_3_GenProp8_12_NotA); inv M8_UM8_0_GP34_3_GenProp8_12_Xo1(YBbus_28, M8_UM8_0_GP34_3_GenProp8_12_NotB); nand2 M8_UM8_0_GP34_3_GenProp8_12_Xo2(M8_UM8_0_GP34_3_GenProp8_12_NotA, YBbus_28, M8_UM8_0_GP34_3_GenProp8_12_line2); nand2 M8_UM8_0_GP34_3_GenProp8_12_Xo3(M8_UM8_0_GP34_3_GenProp8_12_NotB, YAbus_28, M8_UM8_0_GP34_3_GenProp8_12_line3); nand2 M8_UM8_0_GP34_3_GenProp8_12_Xo4(M8_UM8_0_GP34_3_GenProp8_12_line2, M8_UM8_0_GP34_3_GenProp8_12_line3, M8_PropYbus_28); inv M8_UM8_0_GP34_3_GenProp8_13_Xo0(YAbus_29, M8_UM8_0_GP34_3_GenProp8_13_NotA); inv M8_UM8_0_GP34_3_GenProp8_13_Xo1(YBbus_29, M8_UM8_0_GP34_3_GenProp8_13_NotB); nand2 M8_UM8_0_GP34_3_GenProp8_13_Xo2(M8_UM8_0_GP34_3_GenProp8_13_NotA, YBbus_29, M8_UM8_0_GP34_3_GenProp8_13_line2); nand2 M8_UM8_0_GP34_3_GenProp8_13_Xo3(M8_UM8_0_GP34_3_GenProp8_13_NotB, YAbus_29, M8_UM8_0_GP34_3_GenProp8_13_line3); nand2 M8_UM8_0_GP34_3_GenProp8_13_Xo4(M8_UM8_0_GP34_3_GenProp8_13_line2, M8_UM8_0_GP34_3_GenProp8_13_line3, M8_PropYbus_29); inv M8_UM8_0_GP34_3_GenProp8_14_Xo0(YAbus_30, M8_UM8_0_GP34_3_GenProp8_14_NotA); inv M8_UM8_0_GP34_3_GenProp8_14_Xo1(YBbus_30, M8_UM8_0_GP34_3_GenProp8_14_NotB); nand2 M8_UM8_0_GP34_3_GenProp8_14_Xo2(M8_UM8_0_GP34_3_GenProp8_14_NotA, YBbus_30, M8_UM8_0_GP34_3_GenProp8_14_line2); nand2 M8_UM8_0_GP34_3_GenProp8_14_Xo3(M8_UM8_0_GP34_3_GenProp8_14_NotB, YAbus_30, M8_UM8_0_GP34_3_GenProp8_14_line3); nand2 M8_UM8_0_GP34_3_GenProp8_14_Xo4(M8_UM8_0_GP34_3_GenProp8_14_line2, M8_UM8_0_GP34_3_GenProp8_14_line3, M8_PropYbus_30); inv M8_UM8_0_GP34_3_GenProp8_15_Xo0(YAbus_31, M8_UM8_0_GP34_3_GenProp8_15_NotA); inv M8_UM8_0_GP34_3_GenProp8_15_Xo1(YBbus_31, M8_UM8_0_GP34_3_GenProp8_15_NotB); nand2 M8_UM8_0_GP34_3_GenProp8_15_Xo2(M8_UM8_0_GP34_3_GenProp8_15_NotA, YBbus_31, M8_UM8_0_GP34_3_GenProp8_15_line2); nand2 M8_UM8_0_GP34_3_GenProp8_15_Xo3(M8_UM8_0_GP34_3_GenProp8_15_NotB, YAbus_31, M8_UM8_0_GP34_3_GenProp8_15_line3); nand2 M8_UM8_0_GP34_3_GenProp8_15_Xo4(M8_UM8_0_GP34_3_GenProp8_15_line2, M8_UM8_0_GP34_3_GenProp8_15_line3, M8_PropYbus_31); and2 M8_UM8_0_GP34_4(in38, YBbus_32, M8_GenYbus_32); and2 M8_UM8_0_GP34_5(in38, YBbus_33, M8_GenYbus_33); inv M8_UM8_0_GP34_6_Xo0(in38, M8_UM8_0_GP34_6_NotA); inv M8_UM8_0_GP34_6_Xo1(YBbus_32, M8_UM8_0_GP34_6_NotB); nand2 M8_UM8_0_GP34_6_Xo2(M8_UM8_0_GP34_6_NotA, YBbus_32, M8_UM8_0_GP34_6_line2); nand2 M8_UM8_0_GP34_6_Xo3(M8_UM8_0_GP34_6_NotB, in38, M8_UM8_0_GP34_6_line3); nand2 M8_UM8_0_GP34_6_Xo4(M8_UM8_0_GP34_6_line2, M8_UM8_0_GP34_6_line3, M8_PropYbus_32); inv M8_UM8_0_GP34_7_Xo0(in38, M8_UM8_0_GP34_7_NotA); inv M8_UM8_0_GP34_7_Xo1(YBbus_33, M8_UM8_0_GP34_7_NotB); nand2 M8_UM8_0_GP34_7_Xo2(M8_UM8_0_GP34_7_NotA, YBbus_33, M8_UM8_0_GP34_7_line2); nand2 M8_UM8_0_GP34_7_Xo3(M8_UM8_0_GP34_7_NotB, in38, M8_UM8_0_GP34_7_line3); nand2 M8_UM8_0_GP34_7_Xo4(M8_UM8_0_GP34_7_line2, M8_UM8_0_GP34_7_line3, M8_PropYbus_33); or2 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_0(M8_GenYbus_0, M8_PropYbus_0, M8_dummy1_0); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_1_Ao2_0(M8_PropYbus_1, M8_GenYbus_0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_1_line0); or2 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_1_Ao2_1(M8_GenYbus_1, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_1_line0, M8_dummy0_1); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_Ao3a_0(M8_PropYbus_1, M8_GenYbus_0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_line0); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_Ao3a_1(M8_PropYbus_1, M8_PropYbus_0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_line1); or3 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_Ao3a_2(M8_GenYbus_1, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_line0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_2_line1, M8_dummy1_1); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_Ao3a_0(M8_PropYbus_2, M8_GenYbus_1, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_line0); and3 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_Ao3a_1(M8_PropYbus_2, M8_PropYbus_1, M8_GenYbus_0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_line1); or3 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_Ao3a_2(M8_GenYbus_2, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_line0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_3_line1, M8_dummy0_2); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_Ao4a_0(M8_PropYbus_2, M8_GenYbus_1, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_line0); and3 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_Ao4a_1(M8_PropYbus_2, M8_PropYbus_1, M8_GenYbus_0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_line1); and3 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_Ao4a_2(M8_PropYbus_2, M8_PropYbus_1, M8_PropYbus_0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_line2); or4 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_Ao4a_3(M8_GenYbus_2, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_line0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_line1, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_4_line2, M8_dummy1_2); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_Ao4a_0(M8_PropYbus_3, M8_GenYbus_2, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_line0); and3 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_Ao4a_1(M8_PropYbus_3, M8_PropYbus_2, M8_GenYbus_1, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_line1); and4 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_Ao4a_2(M8_PropYbus_3, M8_PropYbus_2, M8_PropYbus_1, M8_GenYbus_0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_line2); or4 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_Ao4a_3(M8_GenYbus_3, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_line0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_line1, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_5_line2, M8_dummy0_3); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_Ao5a_0(M8_PropYbus_3, M8_GenYbus_2, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line0); and3 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_Ao5a_1(M8_PropYbus_3, M8_PropYbus_2, M8_GenYbus_1, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line1); and4 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_Ao5a_2(M8_PropYbus_3, M8_PropYbus_2, M8_PropYbus_1, M8_GenYbus_0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line2); and4 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_Ao5a_3(M8_PropYbus_3, M8_PropYbus_2, M8_PropYbus_1, M8_PropYbus_0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line3); or5 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_Ao5a_4(M8_GenYbus_3, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line1, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line2, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_0_GLC4_6_line3, M8_dummy1_3); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_1_Ao5a_0(M8_PropYbus_4, M8_GenYbus_3, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line0); and3 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_1_Ao5a_1(M8_PropYbus_4, M8_PropYbus_3, M8_GenYbus_2, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line1); and4 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_1_Ao5a_2(M8_PropYbus_4, M8_PropYbus_3, M8_PropYbus_2, M8_GenYbus_1, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line2); and5 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_1_Ao5a_3(M8_PropYbus_4, M8_PropYbus_3, M8_PropYbus_2, M8_PropYbus_1, M8_GenYbus_0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line3); or5 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_1_Ao5a_4(M8_GenYbus_4, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line1, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line2, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_1_line3, M8_dummy0_4); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_Ao6a_0(M8_PropYbus_4, M8_GenYbus_3, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line0); and3 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_Ao6a_1(M8_PropYbus_4, M8_PropYbus_3, M8_GenYbus_2, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line1); and4 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_Ao6a_2(M8_PropYbus_4, M8_PropYbus_3, M8_PropYbus_2, M8_GenYbus_1, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line2); and5 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_Ao6a_3(M8_PropYbus_4, M8_PropYbus_3, M8_PropYbus_2, M8_PropYbus_1, M8_GenYbus_0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line3); and5 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_Ao6a_4(M8_PropYbus_4, M8_PropYbus_3, M8_PropYbus_2, M8_PropYbus_1, M8_PropYbus_0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line4); or6 M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_Ao6a_5(M8_GenYbus_4, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line0, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line1, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line2, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line3, M8_UM8_1_CC_0_GLC34_0_GLC9_0_GLC5_2_line4, M8_dummy1_4); or2 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_0(M8_GenYbus_5, M8_PropYbus_5, M8_dummy1_5); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_1_Ao2_0(M8_PropYbus_6, M8_GenYbus_5, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_1_line0); or2 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_1_Ao2_1(M8_GenYbus_6, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_1_line0, M8_dummy0_6); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_2_Ao3a_0(M8_PropYbus_6, M8_GenYbus_5, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_2_line0); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_2_Ao3a_1(M8_PropYbus_6, M8_PropYbus_5, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_2_line1); or3 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_2_Ao3a_2(M8_GenYbus_6, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_2_line0, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_2_line1, M8_dummy1_6); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_3_Ao3a_0(M8_PropYbus_7, M8_GenYbus_6, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_3_line0); and3 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_3_Ao3a_1(M8_PropYbus_7, M8_PropYbus_6, M8_GenYbus_5, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_3_line1); or3 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_3_Ao3a_2(M8_GenYbus_7, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_3_line0, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_3_line1, M8_dummy0_7); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_4_Ao4a_0(M8_PropYbus_7, M8_GenYbus_6, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_4_line0); and3 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_4_Ao4a_1(M8_PropYbus_7, M8_PropYbus_6, M8_GenYbus_5, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_4_line1); and3 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_4_Ao4a_2(M8_PropYbus_7, M8_PropYbus_6, M8_PropYbus_5, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_4_line2); or4 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_4_Ao4a_3(M8_GenYbus_7, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_4_line0, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_4_line1, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_4_line2, M8_dummy1_7); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_5_Ao4a_0(M8_PropYbus_8, M8_GenYbus_7, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_5_line0); and3 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_5_Ao4a_1(M8_PropYbus_8, M8_PropYbus_7, M8_GenYbus_6, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_5_line1); and4 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_5_Ao4a_2(M8_PropYbus_8, M8_PropYbus_7, M8_PropYbus_6, M8_GenYbus_5, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_5_line2); or4 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_5_Ao4a_3(M8_GenYbus_8, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_5_line0, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_5_line1, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_5_line2, M8_dummy0_8); and2 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_6_Ao5a_0(M8_PropYbus_8, M8_GenYbus_7, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line0); and3 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_6_Ao5a_1(M8_PropYbus_8, M8_PropYbus_7, M8_GenYbus_6, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line1); and4 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_6_Ao5a_2(M8_PropYbus_8, M8_PropYbus_7, M8_PropYbus_6, M8_GenYbus_5, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line2); and4 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_6_Ao5a_3(M8_PropYbus_8, M8_PropYbus_7, M8_PropYbus_6, M8_PropYbus_5, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line3); or5 M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_6_Ao5a_4(M8_GenYbus_8, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line0, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line1, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line2, M8_UM8_1_CC_0_GLC34_0_GLC9_4_GLC4_6_line3, M8_dummy1_8); or2 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_0(M8_GenYbus_9, M8_PropYbus_9, M8_dummy1_9); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_1_Ao2_0(M8_PropYbus_10, M8_GenYbus_9, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_1_line0); or2 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_1_Ao2_1(M8_GenYbus_10, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_1_line0, M8_dummy0_10); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_Ao3a_0(M8_PropYbus_10, M8_GenYbus_9, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_line0); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_Ao3a_1(M8_PropYbus_10, M8_PropYbus_9, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_line1); or3 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_Ao3a_2(M8_GenYbus_10, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_line0, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_2_line1, M8_dummy1_10); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_Ao3a_0(M8_PropYbus_11, M8_GenYbus_10, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_line0); and3 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_Ao3a_1(M8_PropYbus_11, M8_PropYbus_10, M8_GenYbus_9, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_line1); or3 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_Ao3a_2(M8_GenYbus_11, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_line0, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_3_line1, M8_dummy0_11); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_Ao4a_0(M8_PropYbus_11, M8_GenYbus_10, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_line0); and3 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_Ao4a_1(M8_PropYbus_11, M8_PropYbus_10, M8_GenYbus_9, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_line1); and3 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_Ao4a_2(M8_PropYbus_11, M8_PropYbus_10, M8_PropYbus_9, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_line2); or4 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_Ao4a_3(M8_GenYbus_11, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_line0, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_line1, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_4_line2, M8_dummy1_11); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_Ao4a_0(M8_PropYbus_12, M8_GenYbus_11, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_line0); and3 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_Ao4a_1(M8_PropYbus_12, M8_PropYbus_11, M8_GenYbus_10, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_line1); and4 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_Ao4a_2(M8_PropYbus_12, M8_PropYbus_11, M8_PropYbus_10, M8_GenYbus_9, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_line2); or4 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_Ao4a_3(M8_GenYbus_12, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_line0, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_line1, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_5_line2, M8_dummy0_12); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_Ao5a_0(M8_PropYbus_12, M8_GenYbus_11, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line0); and3 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_Ao5a_1(M8_PropYbus_12, M8_PropYbus_11, M8_GenYbus_10, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line1); and4 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_Ao5a_2(M8_PropYbus_12, M8_PropYbus_11, M8_PropYbus_10, M8_GenYbus_9, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line2); and4 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_Ao5a_3(M8_PropYbus_12, M8_PropYbus_11, M8_PropYbus_10, M8_PropYbus_9, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line3); or5 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_Ao5a_4(M8_GenYbus_12, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line0, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line1, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line2, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_0_GLC4_6_line3, M8_dummy1_12); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_1_Ao5a_0(M8_PropYbus_13, M8_GenYbus_12, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line0); and3 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_1_Ao5a_1(M8_PropYbus_13, M8_PropYbus_12, M8_GenYbus_11, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line1); and4 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_1_Ao5a_2(M8_PropYbus_13, M8_PropYbus_12, M8_PropYbus_11, M8_GenYbus_10, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line2); and5 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_1_Ao5a_3(M8_PropYbus_13, M8_PropYbus_12, M8_PropYbus_11, M8_PropYbus_10, M8_GenYbus_9, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line3); or5 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_1_Ao5a_4(M8_GenYbus_13, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line0, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line1, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line2, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_1_line3, M8_dummy0_13); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_Ao6a_0(M8_PropYbus_13, M8_GenYbus_12, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line0); and3 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_Ao6a_1(M8_PropYbus_13, M8_PropYbus_12, M8_GenYbus_11, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line1); and4 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_Ao6a_2(M8_PropYbus_13, M8_PropYbus_12, M8_PropYbus_11, M8_GenYbus_10, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line2); and5 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_Ao6a_3(M8_PropYbus_13, M8_PropYbus_12, M8_PropYbus_11, M8_PropYbus_10, M8_GenYbus_9, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line3); and5 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_Ao6a_4(M8_PropYbus_13, M8_PropYbus_12, M8_PropYbus_11, M8_PropYbus_10, M8_PropYbus_9, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line4); or6 M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_Ao6a_5(M8_GenYbus_13, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line0, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line1, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line2, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line3, M8_UM8_1_CC_0_GLC34_1_GLC9_0_GLC5_2_line4, M8_dummy1_13); or2 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_0(M8_GenYbus_14, M8_PropYbus_14, M8_dummy1_14); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_1_Ao2_0(M8_PropYbus_15, M8_GenYbus_14, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_1_line0); or2 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_1_Ao2_1(M8_GenYbus_15, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_1_line0, M8_dummy0_15); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_2_Ao3a_0(M8_PropYbus_15, M8_GenYbus_14, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_2_line0); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_2_Ao3a_1(M8_PropYbus_15, M8_PropYbus_14, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_2_line1); or3 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_2_Ao3a_2(M8_GenYbus_15, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_2_line0, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_2_line1, M8_dummy1_15); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_3_Ao3a_0(M8_PropYbus_16, M8_GenYbus_15, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_3_line0); and3 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_3_Ao3a_1(M8_PropYbus_16, M8_PropYbus_15, M8_GenYbus_14, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_3_line1); or3 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_3_Ao3a_2(M8_GenYbus_16, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_3_line0, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_3_line1, M8_dummy0_16); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_4_Ao4a_0(M8_PropYbus_16, M8_GenYbus_15, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_4_line0); and3 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_4_Ao4a_1(M8_PropYbus_16, M8_PropYbus_15, M8_GenYbus_14, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_4_line1); and3 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_4_Ao4a_2(M8_PropYbus_16, M8_PropYbus_15, M8_PropYbus_14, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_4_line2); or4 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_4_Ao4a_3(M8_GenYbus_16, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_4_line0, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_4_line1, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_4_line2, M8_dummy1_16); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_5_Ao4a_0(M8_PropYbus_17, M8_GenYbus_16, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_5_line0); and3 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_5_Ao4a_1(M8_PropYbus_17, M8_PropYbus_16, M8_GenYbus_15, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_5_line1); and4 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_5_Ao4a_2(M8_PropYbus_17, M8_PropYbus_16, M8_PropYbus_15, M8_GenYbus_14, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_5_line2); or4 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_5_Ao4a_3(M8_GenYbus_17, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_5_line0, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_5_line1, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_5_line2, M8_dummy0_17); and2 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_6_Ao5a_0(M8_PropYbus_17, M8_GenYbus_16, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line0); and3 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_6_Ao5a_1(M8_PropYbus_17, M8_PropYbus_16, M8_GenYbus_15, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line1); and4 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_6_Ao5a_2(M8_PropYbus_17, M8_PropYbus_16, M8_PropYbus_15, M8_GenYbus_14, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line2); and4 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_6_Ao5a_3(M8_PropYbus_17, M8_PropYbus_16, M8_PropYbus_15, M8_PropYbus_14, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line3); or5 M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_6_Ao5a_4(M8_GenYbus_17, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line0, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line1, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line2, M8_UM8_1_CC_0_GLC34_1_GLC9_4_GLC4_6_line3, M8_dummy1_17); or2 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_0(M8_GenYbus_18, M8_PropYbus_18, M8_dummy1_18); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_1_Ao2_0(M8_PropYbus_19, M8_GenYbus_18, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_1_line0); or2 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_1_Ao2_1(M8_GenYbus_19, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_1_line0, M8_dummy0_19); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_Ao3a_0(M8_PropYbus_19, M8_GenYbus_18, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_line0); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_Ao3a_1(M8_PropYbus_19, M8_PropYbus_18, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_line1); or3 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_Ao3a_2(M8_GenYbus_19, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_line0, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_2_line1, M8_dummy1_19); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_Ao3a_0(M8_PropYbus_20, M8_GenYbus_19, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_line0); and3 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_Ao3a_1(M8_PropYbus_20, M8_PropYbus_19, M8_GenYbus_18, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_line1); or3 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_Ao3a_2(M8_GenYbus_20, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_line0, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_3_line1, M8_dummy0_20); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_Ao4a_0(M8_PropYbus_20, M8_GenYbus_19, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_line0); and3 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_Ao4a_1(M8_PropYbus_20, M8_PropYbus_19, M8_GenYbus_18, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_line1); and3 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_Ao4a_2(M8_PropYbus_20, M8_PropYbus_19, M8_PropYbus_18, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_line2); or4 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_Ao4a_3(M8_GenYbus_20, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_line0, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_line1, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_4_line2, M8_dummy1_20); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_Ao4a_0(M8_PropYbus_21, M8_GenYbus_20, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_line0); and3 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_Ao4a_1(M8_PropYbus_21, M8_PropYbus_20, M8_GenYbus_19, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_line1); and4 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_Ao4a_2(M8_PropYbus_21, M8_PropYbus_20, M8_PropYbus_19, M8_GenYbus_18, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_line2); or4 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_Ao4a_3(M8_GenYbus_21, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_line0, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_line1, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_5_line2, M8_dummy0_21); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_Ao5a_0(M8_PropYbus_21, M8_GenYbus_20, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line0); and3 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_Ao5a_1(M8_PropYbus_21, M8_PropYbus_20, M8_GenYbus_19, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line1); and4 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_Ao5a_2(M8_PropYbus_21, M8_PropYbus_20, M8_PropYbus_19, M8_GenYbus_18, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line2); and4 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_Ao5a_3(M8_PropYbus_21, M8_PropYbus_20, M8_PropYbus_19, M8_PropYbus_18, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line3); or5 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_Ao5a_4(M8_GenYbus_21, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line0, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line1, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line2, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_0_GLC4_6_line3, M8_dummy1_21); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_1_Ao5a_0(M8_PropYbus_22, M8_GenYbus_21, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line0); and3 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_1_Ao5a_1(M8_PropYbus_22, M8_PropYbus_21, M8_GenYbus_20, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line1); and4 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_1_Ao5a_2(M8_PropYbus_22, M8_PropYbus_21, M8_PropYbus_20, M8_GenYbus_19, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line2); and5 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_1_Ao5a_3(M8_PropYbus_22, M8_PropYbus_21, M8_PropYbus_20, M8_PropYbus_19, M8_GenYbus_18, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line3); or5 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_1_Ao5a_4(M8_GenYbus_22, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line0, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line1, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line2, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_1_line3, M8_dummy0_22); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_Ao6a_0(M8_PropYbus_22, M8_GenYbus_21, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line0); and3 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_Ao6a_1(M8_PropYbus_22, M8_PropYbus_21, M8_GenYbus_20, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line1); and4 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_Ao6a_2(M8_PropYbus_22, M8_PropYbus_21, M8_PropYbus_20, M8_GenYbus_19, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line2); and5 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_Ao6a_3(M8_PropYbus_22, M8_PropYbus_21, M8_PropYbus_20, M8_PropYbus_19, M8_GenYbus_18, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line3); and5 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_Ao6a_4(M8_PropYbus_22, M8_PropYbus_21, M8_PropYbus_20, M8_PropYbus_19, M8_PropYbus_18, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line4); or6 M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_Ao6a_5(M8_GenYbus_22, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line0, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line1, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line2, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line3, M8_UM8_1_CC_0_GLC34_2_GLC9_0_GLC5_2_line4, M8_dummy1_22); or2 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_0(M8_GenYbus_23, M8_PropYbus_23, M8_dummy1_23); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_1_Ao2_0(M8_PropYbus_24, M8_GenYbus_23, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_1_line0); or2 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_1_Ao2_1(M8_GenYbus_24, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_1_line0, M8_dummy0_24); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_2_Ao3a_0(M8_PropYbus_24, M8_GenYbus_23, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_2_line0); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_2_Ao3a_1(M8_PropYbus_24, M8_PropYbus_23, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_2_line1); or3 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_2_Ao3a_2(M8_GenYbus_24, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_2_line0, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_2_line1, M8_dummy1_24); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_3_Ao3a_0(M8_PropYbus_25, M8_GenYbus_24, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_3_line0); and3 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_3_Ao3a_1(M8_PropYbus_25, M8_PropYbus_24, M8_GenYbus_23, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_3_line1); or3 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_3_Ao3a_2(M8_GenYbus_25, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_3_line0, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_3_line1, M8_dummy0_25); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_4_Ao4a_0(M8_PropYbus_25, M8_GenYbus_24, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_4_line0); and3 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_4_Ao4a_1(M8_PropYbus_25, M8_PropYbus_24, M8_GenYbus_23, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_4_line1); and3 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_4_Ao4a_2(M8_PropYbus_25, M8_PropYbus_24, M8_PropYbus_23, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_4_line2); or4 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_4_Ao4a_3(M8_GenYbus_25, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_4_line0, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_4_line1, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_4_line2, M8_dummy1_25); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_5_Ao4a_0(M8_PropYbus_26, M8_GenYbus_25, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_5_line0); and3 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_5_Ao4a_1(M8_PropYbus_26, M8_PropYbus_25, M8_GenYbus_24, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_5_line1); and4 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_5_Ao4a_2(M8_PropYbus_26, M8_PropYbus_25, M8_PropYbus_24, M8_GenYbus_23, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_5_line2); or4 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_5_Ao4a_3(M8_GenYbus_26, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_5_line0, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_5_line1, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_5_line2, M8_dummy0_26); and2 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_6_Ao5a_0(M8_PropYbus_26, M8_GenYbus_25, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line0); and3 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_6_Ao5a_1(M8_PropYbus_26, M8_PropYbus_25, M8_GenYbus_24, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line1); and4 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_6_Ao5a_2(M8_PropYbus_26, M8_PropYbus_25, M8_PropYbus_24, M8_GenYbus_23, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line2); and4 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_6_Ao5a_3(M8_PropYbus_26, M8_PropYbus_25, M8_PropYbus_24, M8_PropYbus_23, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line3); or5 M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_6_Ao5a_4(M8_GenYbus_26, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line0, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line1, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line2, M8_UM8_1_CC_0_GLC34_2_GLC9_4_GLC4_6_line3, M8_dummy1_26); or2 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_0(M8_GenYbus_27, M8_PropYbus_27, M8_dummy1_27); and2 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_1_Ao2_0(M8_PropYbus_28, M8_GenYbus_27, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_1_line0); or2 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_1_Ao2_1(M8_GenYbus_28, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_1_line0, M8_dummy0_28); and2 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_2_Ao3a_0(M8_PropYbus_28, M8_GenYbus_27, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_2_line0); and2 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_2_Ao3a_1(M8_PropYbus_28, M8_PropYbus_27, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_2_line1); or3 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_2_Ao3a_2(M8_GenYbus_28, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_2_line0, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_2_line1, M8_dummy1_28); and2 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_3_Ao3a_0(M8_PropYbus_29, M8_GenYbus_28, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_3_line0); and3 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_3_Ao3a_1(M8_PropYbus_29, M8_PropYbus_28, M8_GenYbus_27, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_3_line1); or3 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_3_Ao3a_2(M8_GenYbus_29, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_3_line0, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_3_line1, M8_dummy0_29); and2 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_4_Ao4a_0(M8_PropYbus_29, M8_GenYbus_28, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_4_line0); and3 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_4_Ao4a_1(M8_PropYbus_29, M8_PropYbus_28, M8_GenYbus_27, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_4_line1); and3 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_4_Ao4a_2(M8_PropYbus_29, M8_PropYbus_28, M8_PropYbus_27, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_4_line2); or4 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_4_Ao4a_3(M8_GenYbus_29, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_4_line0, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_4_line1, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_4_line2, M8_dummy1_29); and2 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_5_Ao4a_0(M8_PropYbus_30, M8_GenYbus_29, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_5_line0); and3 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_5_Ao4a_1(M8_PropYbus_30, M8_PropYbus_29, M8_GenYbus_28, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_5_line1); and4 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_5_Ao4a_2(M8_PropYbus_30, M8_PropYbus_29, M8_PropYbus_28, M8_GenYbus_27, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_5_line2); or4 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_5_Ao4a_3(M8_GenYbus_30, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_5_line0, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_5_line1, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_5_line2, M8_dummy0_30); and2 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_6_Ao5a_0(M8_PropYbus_30, M8_GenYbus_29, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line0); and3 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_6_Ao5a_1(M8_PropYbus_30, M8_PropYbus_29, M8_GenYbus_28, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line1); and4 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_6_Ao5a_2(M8_PropYbus_30, M8_PropYbus_29, M8_PropYbus_28, M8_GenYbus_27, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line2); and4 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_6_Ao5a_3(M8_PropYbus_30, M8_PropYbus_29, M8_PropYbus_28, M8_PropYbus_27, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line3); or5 M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_6_Ao5a_4(M8_GenYbus_30, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line0, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line1, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line2, M8_UM8_1_CC_0_GLC34_3_GLC5_0_GLC4_6_line3, M8_dummy1_30); and2 M8_UM8_1_CC_0_GLC34_3_GLC5_1_Ao5a_0(M8_PropYbus_31, M8_GenYbus_30, M8_UM8_1_CC_0_GLC34_3_GLC5_1_line0); and3 M8_UM8_1_CC_0_GLC34_3_GLC5_1_Ao5a_1(M8_PropYbus_31, M8_PropYbus_30, M8_GenYbus_29, M8_UM8_1_CC_0_GLC34_3_GLC5_1_line1); and4 M8_UM8_1_CC_0_GLC34_3_GLC5_1_Ao5a_2(M8_PropYbus_31, M8_PropYbus_30, M8_PropYbus_29, M8_GenYbus_28, M8_UM8_1_CC_0_GLC34_3_GLC5_1_line2); and5 M8_UM8_1_CC_0_GLC34_3_GLC5_1_Ao5a_3(M8_PropYbus_31, M8_PropYbus_30, M8_PropYbus_29, M8_PropYbus_28, M8_GenYbus_27, M8_UM8_1_CC_0_GLC34_3_GLC5_1_line3); or5 M8_UM8_1_CC_0_GLC34_3_GLC5_1_Ao5a_4(M8_GenYbus_31, M8_UM8_1_CC_0_GLC34_3_GLC5_1_line0, M8_UM8_1_CC_0_GLC34_3_GLC5_1_line1, M8_UM8_1_CC_0_GLC34_3_GLC5_1_line2, M8_UM8_1_CC_0_GLC34_3_GLC5_1_line3, M8_dummy0_31); and2 M8_UM8_1_CC_0_GLC34_3_GLC5_2_Ao6a_0(M8_PropYbus_31, M8_GenYbus_30, M8_UM8_1_CC_0_GLC34_3_GLC5_2_line0); and3 M8_UM8_1_CC_0_GLC34_3_GLC5_2_Ao6a_1(M8_PropYbus_31, M8_PropYbus_30, M8_GenYbus_29, M8_UM8_1_CC_0_GLC34_3_GLC5_2_line1); and4 M8_UM8_1_CC_0_GLC34_3_GLC5_2_Ao6a_2(M8_PropYbus_31, M8_PropYbus_30, M8_PropYbus_29, M8_GenYbus_28, M8_UM8_1_CC_0_GLC34_3_GLC5_2_line2); and5 M8_UM8_1_CC_0_GLC34_3_GLC5_2_Ao6a_3(M8_PropYbus_31, M8_PropYbus_30, M8_PropYbus_29, M8_PropYbus_28, M8_GenYbus_27, M8_UM8_1_CC_0_GLC34_3_GLC5_2_line3); and5 M8_UM8_1_CC_0_GLC34_3_GLC5_2_Ao6a_4(M8_PropYbus_31, M8_PropYbus_30, M8_PropYbus_29, M8_PropYbus_28, M8_PropYbus_27, M8_UM8_1_CC_0_GLC34_3_GLC5_2_line4); or6 M8_UM8_1_CC_0_GLC34_3_GLC5_2_Ao6a_5(M8_GenYbus_31, M8_UM8_1_CC_0_GLC34_3_GLC5_2_line0, M8_UM8_1_CC_0_GLC34_3_GLC5_2_line1, M8_UM8_1_CC_0_GLC34_3_GLC5_2_line2, M8_UM8_1_CC_0_GLC34_3_GLC5_2_line3, M8_UM8_1_CC_0_GLC34_3_GLC5_2_line4, M8_dummy1_31); or2 M8_UM8_1_CC_0_GLC34_4_GLC2_0(M8_GenYbus_32, M8_PropYbus_32, M8_dummy1_32); and2 M8_UM8_1_CC_0_GLC34_4_GLC2_1_Ao2_0(M8_PropYbus_33, M8_GenYbus_32, M8_UM8_1_CC_0_GLC34_4_GLC2_1_line0); or2 M8_UM8_1_CC_0_GLC34_4_GLC2_1_Ao2_1(M8_GenYbus_33, M8_UM8_1_CC_0_GLC34_4_GLC2_1_line0, M8_dummy0_33); and2 M8_UM8_1_CC_0_GLC34_4_GLC2_2_Ao3a_0(M8_PropYbus_33, M8_GenYbus_32, M8_UM8_1_CC_0_GLC34_4_GLC2_2_line0); and2 M8_UM8_1_CC_0_GLC34_4_GLC2_2_Ao3a_1(M8_PropYbus_33, M8_PropYbus_32, M8_UM8_1_CC_0_GLC34_4_GLC2_2_line1); or3 M8_UM8_1_CC_0_GLC34_4_GLC2_2_Ao3a_2(M8_GenYbus_33, M8_UM8_1_CC_0_GLC34_4_GLC2_2_line0, M8_UM8_1_CC_0_GLC34_4_GLC2_2_line1, M8_dummy1_33); and5 M8_UM8_1_CC_1_CGC34_0_CBC0(M8_PropYbus_0, M8_PropYbus_1, M8_PropYbus_2, M8_PropYbus_3, M8_PropYbus_4, M8_UM8_1_CC_1_CGC34_0_Prop4_0); and4 M8_UM8_1_CC_1_CGC34_0_CBC1(M8_PropYbus_5, M8_PropYbus_6, M8_PropYbus_7, M8_PropYbus_8, M8_UM8_1_CC_1_CGC34_0_Prop8_5); and5 M8_UM8_1_CC_1_CGC34_0_CBC2(M8_PropYbus_9, M8_PropYbus_10, M8_PropYbus_11, M8_PropYbus_12, M8_PropYbus_13, M8_UM8_1_CC_1_CGC34_0_Prop13_9); and4 M8_UM8_1_CC_1_CGC34_0_CBC3(M8_PropYbus_14, M8_PropYbus_15, M8_PropYbus_16, M8_PropYbus_17, M8_UM8_1_CC_1_CGC34_0_Prop17_14); and5 M8_UM8_1_CC_1_CGC34_0_CBC4(M8_PropYbus_18, M8_PropYbus_19, M8_PropYbus_20, M8_PropYbus_21, M8_PropYbus_22, M8_UM8_1_CC_1_CGC34_0_Prop22_18); and4 M8_UM8_1_CC_1_CGC34_0_CBC5(M8_PropYbus_23, M8_PropYbus_24, M8_PropYbus_25, M8_PropYbus_26, M8_UM8_1_CC_1_CGC34_0_Prop26_23); and5 M8_UM8_1_CC_1_CGC34_0_CBC6(M8_PropYbus_27, M8_PropYbus_28, M8_PropYbus_29, M8_PropYbus_30, M8_PropYbus_31, M8_UM8_1_CC_1_CGC34_0_Prop31_27); and2 M8_UM8_1_CC_1_CGC34_0_CBC7(M8_PropYbus_32, M8_PropYbus_33, M8_UM8_1_CC_1_CGC34_0_Prop33_32); and2 M8_UM8_1_CC_1_CGC34_0_CBC8(M8_UM8_1_CC_1_CGC34_0_Prop4_0, M8_UM8_1_CC_1_CGC34_0_Prop8_5, M8_UM8_1_CC_1_CGC34_0_Prop8_0); and2 M8_UM8_1_CC_1_CGC34_0_CBC9(M8_UM8_1_CC_1_CGC34_0_Prop13_9, M8_UM8_1_CC_1_CGC34_0_Prop17_14, M8_UM8_1_CC_1_CGC34_0_Prop17_9); and2 M8_UM8_1_CC_1_CGC34_0_CBC10(M8_UM8_1_CC_1_CGC34_0_Prop22_18, M8_UM8_1_CC_1_CGC34_0_Prop26_23, M8_UM8_1_CC_1_CGC34_0_Prop26_18); and2 M8_UM8_1_CC_1_CGC34_0_CBC11(M8_UM8_1_CC_1_CGC34_0_Prop31_27, M8_UM8_1_CC_1_CGC34_0_Prop33_32, M8_UM8_1_CC_1_CGC34_0_Prop33_27); and2 M8_UM8_1_CC_1_CGC34_0_CBC12_Ao2_0(in89, M8_UM8_1_CC_1_CGC34_0_Prop4_0, M8_UM8_1_CC_1_CGC34_0_CBC12_line0); or2 M8_UM8_1_CC_1_CGC34_0_CBC12_Ao2_1(M8_dummy0_4, M8_UM8_1_CC_1_CGC34_0_CBC12_line0, M8_CarryOutYbus_4); inv M8_UM8_1_CC_1_CGC34_0_CGC13_Mux0(M8_CarryOutYbus_4, M8_UM8_1_CC_1_CGC34_0_CGC13_Not_ContIn); and2 M8_UM8_1_CC_1_CGC34_0_CGC13_Mux1(M8_dummy0_8, M8_UM8_1_CC_1_CGC34_0_CGC13_Not_ContIn, M8_UM8_1_CC_1_CGC34_0_CGC13_line1); and2 M8_UM8_1_CC_1_CGC34_0_CGC13_Mux2(M8_dummy1_8, M8_CarryOutYbus_4, M8_UM8_1_CC_1_CGC34_0_CGC13_line2); or2 M8_UM8_1_CC_1_CGC34_0_CGC13_Mux3(M8_UM8_1_CC_1_CGC34_0_CGC13_line1, M8_UM8_1_CC_1_CGC34_0_CGC13_line2, M8_CarryOutYbus_8); and2 M8_UM8_1_CC_1_CGC34_0_GGC14_Ao2_0(M8_CarryOutYbus_8, M8_UM8_1_CC_1_CGC34_0_Prop13_9, M8_UM8_1_CC_1_CGC34_0_GGC14_line0); or2 M8_UM8_1_CC_1_CGC34_0_GGC14_Ao2_1(M8_dummy0_13, M8_UM8_1_CC_1_CGC34_0_GGC14_line0, M8_CarryOutYbus_13); and2 M8_UM8_1_CC_1_CGC34_0_CGC15_Ao2_0(M8_dummy0_13, M8_UM8_1_CC_1_CGC34_0_Prop17_14, M8_UM8_1_CC_1_CGC34_0_CGC15_line0); or2 M8_UM8_1_CC_1_CGC34_0_CGC15_Ao2_1(M8_dummy0_17, M8_UM8_1_CC_1_CGC34_0_CGC15_line0, M8_UM8_1_CC_1_CGC34_0_LocalCarry17_9); and2 M8_UM8_1_CC_1_CGC34_0_CGC16_Ao2_0(M8_dummy0_4, M8_UM8_1_CC_1_CGC34_0_Prop8_5, M8_UM8_1_CC_1_CGC34_0_CGC16_line0); or2 M8_UM8_1_CC_1_CGC34_0_CGC16_Ao2_1(M8_dummy0_8, M8_UM8_1_CC_1_CGC34_0_CGC16_line0, M8_UM8_1_CC_1_CGC34_0_LocalCarry8_0); and2 M8_UM8_1_CC_1_CGC34_0_CGC17_Ao3a_0(M8_UM8_1_CC_1_CGC34_0_Prop17_9, M8_UM8_1_CC_1_CGC34_0_LocalCarry8_0, M8_UM8_1_CC_1_CGC34_0_CGC17_line0); and3 M8_UM8_1_CC_1_CGC34_0_CGC17_Ao3a_1(M8_UM8_1_CC_1_CGC34_0_Prop17_9, M8_UM8_1_CC_1_CGC34_0_Prop8_0, in89, M8_UM8_1_CC_1_CGC34_0_CGC17_line1); or3 M8_UM8_1_CC_1_CGC34_0_CGC17_Ao3a_2(M8_UM8_1_CC_1_CGC34_0_LocalCarry17_9, M8_UM8_1_CC_1_CGC34_0_CGC17_line0, M8_UM8_1_CC_1_CGC34_0_CGC17_line1, out252); and2 M8_UM8_1_CC_1_CGC34_0_CGC18_Ao2_0(out252, M8_UM8_1_CC_1_CGC34_0_Prop22_18, M8_UM8_1_CC_1_CGC34_0_CGC18_line0); or2 M8_UM8_1_CC_1_CGC34_0_CGC18_Ao2_1(M8_dummy0_22, M8_UM8_1_CC_1_CGC34_0_CGC18_line0, M8_CarryOutYbus_22); and2 M8_UM8_1_CC_1_CGC34_0_CGC19_Ao2_0(M8_dummy0_22, M8_UM8_1_CC_1_CGC34_0_Prop26_23, M8_UM8_1_CC_1_CGC34_0_CGC19_line0); or2 M8_UM8_1_CC_1_CGC34_0_CGC19_Ao2_1(M8_dummy0_26, M8_UM8_1_CC_1_CGC34_0_CGC19_line0, M8_UM8_1_CC_1_CGC34_0_LocalCarry26_18); and2 M8_UM8_1_CC_1_CGC34_0_CGC20_Ao4a_0(M8_UM8_1_CC_1_CGC34_0_Prop26_18, M8_UM8_1_CC_1_CGC34_0_LocalCarry17_9, M8_UM8_1_CC_1_CGC34_0_CGC20_line0); and3 M8_UM8_1_CC_1_CGC34_0_CGC20_Ao4a_1(M8_UM8_1_CC_1_CGC34_0_Prop26_18, M8_UM8_1_CC_1_CGC34_0_Prop17_9, M8_UM8_1_CC_1_CGC34_0_LocalCarry8_0, M8_UM8_1_CC_1_CGC34_0_CGC20_line1); and4 M8_UM8_1_CC_1_CGC34_0_CGC20_Ao4a_2(M8_UM8_1_CC_1_CGC34_0_Prop26_18, M8_UM8_1_CC_1_CGC34_0_Prop17_9, M8_UM8_1_CC_1_CGC34_0_Prop8_0, in89, M8_UM8_1_CC_1_CGC34_0_CGC20_line2); or4 M8_UM8_1_CC_1_CGC34_0_CGC20_Ao4a_3(M8_UM8_1_CC_1_CGC34_0_LocalCarry26_18, M8_UM8_1_CC_1_CGC34_0_CGC20_line0, M8_UM8_1_CC_1_CGC34_0_CGC20_line1, M8_UM8_1_CC_1_CGC34_0_CGC20_line2, M8_CarryOutYbus_26); and2 M8_UM8_1_CC_1_CGC34_0_CGC21_Ao2_0(M8_CarryOutYbus_26, M8_UM8_1_CC_1_CGC34_0_Prop31_27, M8_UM8_1_CC_1_CGC34_0_CGC21_line0); or2 M8_UM8_1_CC_1_CGC34_0_CGC21_Ao2_1(M8_dummy0_31, M8_UM8_1_CC_1_CGC34_0_CGC21_line0, M8_CarryOutYbus_31); and2 M8_UM8_1_CC_1_CGC34_0_CGC22_Ao2_0(M8_dummy0_31, M8_UM8_1_CC_1_CGC34_0_Prop33_32, M8_UM8_1_CC_1_CGC34_0_CGC22_line0); or2 M8_UM8_1_CC_1_CGC34_0_CGC22_Ao2_1(M8_dummy0_33, M8_UM8_1_CC_1_CGC34_0_CGC22_line0, M8_UM8_1_CC_1_CGC34_0_LocalCarry33_27); and2 M8_UM8_1_CC_1_CGC34_0_CGC23_Ao5a_0(M8_UM8_1_CC_1_CGC34_0_Prop33_27, M8_UM8_1_CC_1_CGC34_0_LocalCarry26_18, M8_UM8_1_CC_1_CGC34_0_CGC23_line0); and3 M8_UM8_1_CC_1_CGC34_0_CGC23_Ao5a_1(M8_UM8_1_CC_1_CGC34_0_Prop33_27, M8_UM8_1_CC_1_CGC34_0_Prop26_18, M8_UM8_1_CC_1_CGC34_0_LocalCarry17_9, M8_UM8_1_CC_1_CGC34_0_CGC23_line1); and4 M8_UM8_1_CC_1_CGC34_0_CGC23_Ao5a_2(M8_UM8_1_CC_1_CGC34_0_Prop33_27, M8_UM8_1_CC_1_CGC34_0_Prop26_18, M8_UM8_1_CC_1_CGC34_0_Prop17_9, M8_UM8_1_CC_1_CGC34_0_LocalCarry8_0, M8_UM8_1_CC_1_CGC34_0_CGC23_line2); and5 M8_UM8_1_CC_1_CGC34_0_CGC23_Ao5a_3(M8_UM8_1_CC_1_CGC34_0_Prop33_27, M8_UM8_1_CC_1_CGC34_0_Prop26_18, M8_UM8_1_CC_1_CGC34_0_Prop17_9, M8_UM8_1_CC_1_CGC34_0_Prop8_0, in89, M8_UM8_1_CC_1_CGC34_0_CGC23_line3); or5 M8_UM8_1_CC_1_CGC34_0_CGC23_Ao5a_4(M8_UM8_1_CC_1_CGC34_0_LocalCarry33_27, M8_UM8_1_CC_1_CGC34_0_CGC23_line0, M8_UM8_1_CC_1_CGC34_0_CGC23_line1, M8_UM8_1_CC_1_CGC34_0_CGC23_line2, M8_UM8_1_CC_1_CGC34_0_CGC23_line3, M8_CarryOutYbus_33); and2 M8_UM8_1_CC_1_CGC34_1_CB5_0_Ao2_0(M8_PropYbus_0, in89, M8_UM8_1_CC_1_CGC34_1_CB5_0_line0); or2 M8_UM8_1_CC_1_CGC34_1_CB5_0_Ao2_1(M8_GenYbus_0, M8_UM8_1_CC_1_CGC34_1_CB5_0_line0, M8_CarryOutYbus_0); and2 M8_UM8_1_CC_1_CGC34_1_CB5_1_Ao3a_0(M8_PropYbus_1, M8_GenYbus_0, M8_UM8_1_CC_1_CGC34_1_CB5_1_line0); and3 M8_UM8_1_CC_1_CGC34_1_CB5_1_Ao3a_1(M8_PropYbus_1, M8_PropYbus_0, in89, M8_UM8_1_CC_1_CGC34_1_CB5_1_line1); or3 M8_UM8_1_CC_1_CGC34_1_CB5_1_Ao3a_2(M8_GenYbus_1, M8_UM8_1_CC_1_CGC34_1_CB5_1_line0, M8_UM8_1_CC_1_CGC34_1_CB5_1_line1, M8_CarryOutYbus_1); and2 M8_UM8_1_CC_1_CGC34_1_CB5_2_Ao4a_0(M8_PropYbus_2, M8_GenYbus_1, M8_UM8_1_CC_1_CGC34_1_CB5_2_line0); and3 M8_UM8_1_CC_1_CGC34_1_CB5_2_Ao4a_1(M8_PropYbus_2, M8_PropYbus_1, M8_GenYbus_0, M8_UM8_1_CC_1_CGC34_1_CB5_2_line1); and4 M8_UM8_1_CC_1_CGC34_1_CB5_2_Ao4a_2(M8_PropYbus_2, M8_PropYbus_1, M8_PropYbus_0, in89, M8_UM8_1_CC_1_CGC34_1_CB5_2_line2); or4 M8_UM8_1_CC_1_CGC34_1_CB5_2_Ao4a_3(M8_GenYbus_2, M8_UM8_1_CC_1_CGC34_1_CB5_2_line0, M8_UM8_1_CC_1_CGC34_1_CB5_2_line1, M8_UM8_1_CC_1_CGC34_1_CB5_2_line2, M8_CarryOutYbus_2); and2 M8_UM8_1_CC_1_CGC34_1_CB5_3_Ao5a_0(M8_PropYbus_3, M8_GenYbus_2, M8_UM8_1_CC_1_CGC34_1_CB5_3_line0); and3 M8_UM8_1_CC_1_CGC34_1_CB5_3_Ao5a_1(M8_PropYbus_3, M8_PropYbus_2, M8_GenYbus_1, M8_UM8_1_CC_1_CGC34_1_CB5_3_line1); and4 M8_UM8_1_CC_1_CGC34_1_CB5_3_Ao5a_2(M8_PropYbus_3, M8_PropYbus_2, M8_PropYbus_1, M8_GenYbus_0, M8_UM8_1_CC_1_CGC34_1_CB5_3_line2); and5 M8_UM8_1_CC_1_CGC34_1_CB5_3_Ao5a_3(M8_PropYbus_3, M8_PropYbus_2, M8_PropYbus_1, M8_PropYbus_0, in89, M8_UM8_1_CC_1_CGC34_1_CB5_3_line3); or5 M8_UM8_1_CC_1_CGC34_1_CB5_3_Ao5a_4(M8_GenYbus_3, M8_UM8_1_CC_1_CGC34_1_CB5_3_line0, M8_UM8_1_CC_1_CGC34_1_CB5_3_line1, M8_UM8_1_CC_1_CGC34_1_CB5_3_line2, M8_UM8_1_CC_1_CGC34_1_CB5_3_line3, M8_CarryOutYbus_3); and2 M8_UM8_1_CC_1_CGC34_2_CB5_0_Ao2_0(M8_PropYbus_9, M8_CarryOutYbus_8, M8_UM8_1_CC_1_CGC34_2_CB5_0_line0); or2 M8_UM8_1_CC_1_CGC34_2_CB5_0_Ao2_1(M8_GenYbus_9, M8_UM8_1_CC_1_CGC34_2_CB5_0_line0, M8_CarryOutYbus_9); and2 M8_UM8_1_CC_1_CGC34_2_CB5_1_Ao3a_0(M8_PropYbus_10, M8_GenYbus_9, M8_UM8_1_CC_1_CGC34_2_CB5_1_line0); and3 M8_UM8_1_CC_1_CGC34_2_CB5_1_Ao3a_1(M8_PropYbus_10, M8_PropYbus_9, M8_CarryOutYbus_8, M8_UM8_1_CC_1_CGC34_2_CB5_1_line1); or3 M8_UM8_1_CC_1_CGC34_2_CB5_1_Ao3a_2(M8_GenYbus_10, M8_UM8_1_CC_1_CGC34_2_CB5_1_line0, M8_UM8_1_CC_1_CGC34_2_CB5_1_line1, M8_CarryOutYbus_10); and2 M8_UM8_1_CC_1_CGC34_2_CB5_2_Ao4a_0(M8_PropYbus_11, M8_GenYbus_10, M8_UM8_1_CC_1_CGC34_2_CB5_2_line0); and3 M8_UM8_1_CC_1_CGC34_2_CB5_2_Ao4a_1(M8_PropYbus_11, M8_PropYbus_10, M8_GenYbus_9, M8_UM8_1_CC_1_CGC34_2_CB5_2_line1); and4 M8_UM8_1_CC_1_CGC34_2_CB5_2_Ao4a_2(M8_PropYbus_11, M8_PropYbus_10, M8_PropYbus_9, M8_CarryOutYbus_8, M8_UM8_1_CC_1_CGC34_2_CB5_2_line2); or4 M8_UM8_1_CC_1_CGC34_2_CB5_2_Ao4a_3(M8_GenYbus_11, M8_UM8_1_CC_1_CGC34_2_CB5_2_line0, M8_UM8_1_CC_1_CGC34_2_CB5_2_line1, M8_UM8_1_CC_1_CGC34_2_CB5_2_line2, M8_CarryOutYbus_11); and2 M8_UM8_1_CC_1_CGC34_2_CB5_3_Ao5a_0(M8_PropYbus_12, M8_GenYbus_11, M8_UM8_1_CC_1_CGC34_2_CB5_3_line0); and3 M8_UM8_1_CC_1_CGC34_2_CB5_3_Ao5a_1(M8_PropYbus_12, M8_PropYbus_11, M8_GenYbus_10, M8_UM8_1_CC_1_CGC34_2_CB5_3_line1); and4 M8_UM8_1_CC_1_CGC34_2_CB5_3_Ao5a_2(M8_PropYbus_12, M8_PropYbus_11, M8_PropYbus_10, M8_GenYbus_9, M8_UM8_1_CC_1_CGC34_2_CB5_3_line2); and5 M8_UM8_1_CC_1_CGC34_2_CB5_3_Ao5a_3(M8_PropYbus_12, M8_PropYbus_11, M8_PropYbus_10, M8_PropYbus_9, M8_CarryOutYbus_8, M8_UM8_1_CC_1_CGC34_2_CB5_3_line3); or5 M8_UM8_1_CC_1_CGC34_2_CB5_3_Ao5a_4(M8_GenYbus_12, M8_UM8_1_CC_1_CGC34_2_CB5_3_line0, M8_UM8_1_CC_1_CGC34_2_CB5_3_line1, M8_UM8_1_CC_1_CGC34_2_CB5_3_line2, M8_UM8_1_CC_1_CGC34_2_CB5_3_line3, M8_CarryOutYbus_12); and2 M8_UM8_1_CC_1_CGC34_3_CB5_0_Ao2_0(M8_PropYbus_18, out252, M8_UM8_1_CC_1_CGC34_3_CB5_0_line0); or2 M8_UM8_1_CC_1_CGC34_3_CB5_0_Ao2_1(M8_GenYbus_18, M8_UM8_1_CC_1_CGC34_3_CB5_0_line0, M8_CarryOutYbus_18); and2 M8_UM8_1_CC_1_CGC34_3_CB5_1_Ao3a_0(M8_PropYbus_19, M8_GenYbus_18, M8_UM8_1_CC_1_CGC34_3_CB5_1_line0); and3 M8_UM8_1_CC_1_CGC34_3_CB5_1_Ao3a_1(M8_PropYbus_19, M8_PropYbus_18, out252, M8_UM8_1_CC_1_CGC34_3_CB5_1_line1); or3 M8_UM8_1_CC_1_CGC34_3_CB5_1_Ao3a_2(M8_GenYbus_19, M8_UM8_1_CC_1_CGC34_3_CB5_1_line0, M8_UM8_1_CC_1_CGC34_3_CB5_1_line1, M8_CarryOutYbus_19); and2 M8_UM8_1_CC_1_CGC34_3_CB5_2_Ao4a_0(M8_PropYbus_20, M8_GenYbus_19, M8_UM8_1_CC_1_CGC34_3_CB5_2_line0); and3 M8_UM8_1_CC_1_CGC34_3_CB5_2_Ao4a_1(M8_PropYbus_20, M8_PropYbus_19, M8_GenYbus_18, M8_UM8_1_CC_1_CGC34_3_CB5_2_line1); and4 M8_UM8_1_CC_1_CGC34_3_CB5_2_Ao4a_2(M8_PropYbus_20, M8_PropYbus_19, M8_PropYbus_18, out252, M8_UM8_1_CC_1_CGC34_3_CB5_2_line2); or4 M8_UM8_1_CC_1_CGC34_3_CB5_2_Ao4a_3(M8_GenYbus_20, M8_UM8_1_CC_1_CGC34_3_CB5_2_line0, M8_UM8_1_CC_1_CGC34_3_CB5_2_line1, M8_UM8_1_CC_1_CGC34_3_CB5_2_line2, M8_CarryOutYbus_20); and2 M8_UM8_1_CC_1_CGC34_3_CB5_3_Ao5a_0(M8_PropYbus_21, M8_GenYbus_20, M8_UM8_1_CC_1_CGC34_3_CB5_3_line0); and3 M8_UM8_1_CC_1_CGC34_3_CB5_3_Ao5a_1(M8_PropYbus_21, M8_PropYbus_20, M8_GenYbus_19, M8_UM8_1_CC_1_CGC34_3_CB5_3_line1); and4 M8_UM8_1_CC_1_CGC34_3_CB5_3_Ao5a_2(M8_PropYbus_21, M8_PropYbus_20, M8_PropYbus_19, M8_GenYbus_18, M8_UM8_1_CC_1_CGC34_3_CB5_3_line2); and5 M8_UM8_1_CC_1_CGC34_3_CB5_3_Ao5a_3(M8_PropYbus_21, M8_PropYbus_20, M8_PropYbus_19, M8_PropYbus_18, out252, M8_UM8_1_CC_1_CGC34_3_CB5_3_line3); or5 M8_UM8_1_CC_1_CGC34_3_CB5_3_Ao5a_4(M8_GenYbus_21, M8_UM8_1_CC_1_CGC34_3_CB5_3_line0, M8_UM8_1_CC_1_CGC34_3_CB5_3_line1, M8_UM8_1_CC_1_CGC34_3_CB5_3_line2, M8_UM8_1_CC_1_CGC34_3_CB5_3_line3, M8_CarryOutYbus_21); and2 M8_UM8_1_CC_1_CGC34_4_CB5_0_Ao2_0(M8_PropYbus_27, M8_CarryOutYbus_26, M8_UM8_1_CC_1_CGC34_4_CB5_0_line0); or2 M8_UM8_1_CC_1_CGC34_4_CB5_0_Ao2_1(M8_GenYbus_27, M8_UM8_1_CC_1_CGC34_4_CB5_0_line0, M8_CarryOutYbus_27); and2 M8_UM8_1_CC_1_CGC34_4_CB5_1_Ao3a_0(M8_PropYbus_28, M8_GenYbus_27, M8_UM8_1_CC_1_CGC34_4_CB5_1_line0); and3 M8_UM8_1_CC_1_CGC34_4_CB5_1_Ao3a_1(M8_PropYbus_28, M8_PropYbus_27, M8_CarryOutYbus_26, M8_UM8_1_CC_1_CGC34_4_CB5_1_line1); or3 M8_UM8_1_CC_1_CGC34_4_CB5_1_Ao3a_2(M8_GenYbus_28, M8_UM8_1_CC_1_CGC34_4_CB5_1_line0, M8_UM8_1_CC_1_CGC34_4_CB5_1_line1, M8_CarryOutYbus_28); and2 M8_UM8_1_CC_1_CGC34_4_CB5_2_Ao4a_0(M8_PropYbus_29, M8_GenYbus_28, M8_UM8_1_CC_1_CGC34_4_CB5_2_line0); and3 M8_UM8_1_CC_1_CGC34_4_CB5_2_Ao4a_1(M8_PropYbus_29, M8_PropYbus_28, M8_GenYbus_27, M8_UM8_1_CC_1_CGC34_4_CB5_2_line1); and4 M8_UM8_1_CC_1_CGC34_4_CB5_2_Ao4a_2(M8_PropYbus_29, M8_PropYbus_28, M8_PropYbus_27, M8_CarryOutYbus_26, M8_UM8_1_CC_1_CGC34_4_CB5_2_line2); or4 M8_UM8_1_CC_1_CGC34_4_CB5_2_Ao4a_3(M8_GenYbus_29, M8_UM8_1_CC_1_CGC34_4_CB5_2_line0, M8_UM8_1_CC_1_CGC34_4_CB5_2_line1, M8_UM8_1_CC_1_CGC34_4_CB5_2_line2, M8_CarryOutYbus_29); and2 M8_UM8_1_CC_1_CGC34_4_CB5_3_Ao5a_0(M8_PropYbus_30, M8_GenYbus_29, M8_UM8_1_CC_1_CGC34_4_CB5_3_line0); and3 M8_UM8_1_CC_1_CGC34_4_CB5_3_Ao5a_1(M8_PropYbus_30, M8_PropYbus_29, M8_GenYbus_28, M8_UM8_1_CC_1_CGC34_4_CB5_3_line1); and4 M8_UM8_1_CC_1_CGC34_4_CB5_3_Ao5a_2(M8_PropYbus_30, M8_PropYbus_29, M8_PropYbus_28, M8_GenYbus_27, M8_UM8_1_CC_1_CGC34_4_CB5_3_line2); and5 M8_UM8_1_CC_1_CGC34_4_CB5_3_Ao5a_3(M8_PropYbus_30, M8_PropYbus_29, M8_PropYbus_28, M8_PropYbus_27, M8_CarryOutYbus_26, M8_UM8_1_CC_1_CGC34_4_CB5_3_line3); or5 M8_UM8_1_CC_1_CGC34_4_CB5_3_Ao5a_4(M8_GenYbus_30, M8_UM8_1_CC_1_CGC34_4_CB5_3_line0, M8_UM8_1_CC_1_CGC34_4_CB5_3_line1, M8_UM8_1_CC_1_CGC34_4_CB5_3_line2, M8_UM8_1_CC_1_CGC34_4_CB5_3_line3, M8_CarryOutYbus_30); inv M8_UM8_1_CC_2_Mux0(M8_CarryOutYbus_31, M8_UM8_1_CC_2_Not_ContIn); and2 M8_UM8_1_CC_2_Mux1(M8_dummy0_33, M8_UM8_1_CC_2_Not_ContIn, M8_UM8_1_CC_2_line1); and2 M8_UM8_1_CC_2_Mux2(M8_dummy1_33, M8_CarryOutYbus_31, M8_UM8_1_CC_2_line2); or2 M8_UM8_1_CC_2_Mux3(M8_UM8_1_CC_2_line1, M8_UM8_1_CC_2_line2, out249); and4 M9_UM9_0_GS0(in150, in184, in228, in240, M9_UM9_0_K0); and4 M9_UM9_0_GS1(in210, in152, in218, in230, M9_UM9_0_K1); and4 M9_UM9_0_GS2(in183, in182, in185, in186, M9_UM9_0_K2); and4 M9_UM9_0_GS3(in162, in172, in188, in199, M9_UM9_0_K3); and2 M9_UM9_0_GS4(M9_UM9_0_K0, M9_UM9_0_K1, M9_StrobeK0_1); and2 M9_UM9_0_GS5(M9_UM9_0_K2, M9_UM9_0_K3, M9_StrobeK2_3); inv M9_UM9_0_GS6(M9_UM9_0_K0, out404); inv M9_UM9_0_GS7(M9_UM9_0_K1, out406); inv M9_UM9_0_GS8(M9_UM9_0_K2, out408); inv M9_UM9_0_GS9(M9_UM9_0_K3, out410); inv M9_UM9_1_PCB0_Inv7_0(in3698, M9_UM9_1_Not_PCYA0bus_0); inv M9_UM9_1_PCB0_Inv7_1(in3701, M9_UM9_1_Not_PCYA0bus_1); inv M9_UM9_1_PCB0_Inv7_2(in4393, M9_UM9_1_Not_PCYA0bus_2); inv M9_UM9_1_PCB0_Inv7_3(in2208, M9_UM9_1_Not_PCYA0bus_3); inv M9_UM9_1_PCB0_Inv7_4(in1492, M9_UM9_1_Not_PCYA0bus_4); inv M9_UM9_1_PCB0_Inv7_5(in1496, M9_UM9_1_Not_PCYA0bus_5); inv M9_UM9_1_PCB0_Inv7_6(in1459, M9_UM9_1_Not_PCYA0bus_6); inv M9_UM9_1_PCB1_Mux7_0_Mux0(MuxSel, M9_UM9_1_PCB1_Mux7_0_Not_ContIn); and2 M9_UM9_1_PCB1_Mux7_0_Mux1(in229, M9_UM9_1_PCB1_Mux7_0_Not_ContIn, M9_UM9_1_PCB1_Mux7_0_line1); and2 M9_UM9_1_PCB1_Mux7_0_Mux2(in41, MuxSel, M9_UM9_1_PCB1_Mux7_0_line2); or2 M9_UM9_1_PCB1_Mux7_0_Mux3(M9_UM9_1_PCB1_Mux7_0_line1, M9_UM9_1_PCB1_Mux7_0_line2, M9_UM9_1_PCXAtempbus_0); inv M9_UM9_1_PCB1_Mux7_1_Mux0(MuxSel, M9_UM9_1_PCB1_Mux7_1_Not_ContIn); and2 M9_UM9_1_PCB1_Mux7_1_Mux1(in239, M9_UM9_1_PCB1_Mux7_1_Not_ContIn, M9_UM9_1_PCB1_Mux7_1_line1); and2 M9_UM9_1_PCB1_Mux7_1_Mux2(in44, MuxSel, M9_UM9_1_PCB1_Mux7_1_line2); or2 M9_UM9_1_PCB1_Mux7_1_Mux3(M9_UM9_1_PCB1_Mux7_1_line1, M9_UM9_1_PCB1_Mux7_1_line2, M9_UM9_1_PCXAtempbus_1); inv M9_UM9_1_PCB1_Mux7_2_Mux0(MuxSel, M9_UM9_1_PCB1_Mux7_2_Not_ContIn); and2 M9_UM9_1_PCB1_Mux7_2_Mux1(in227, M9_UM9_1_PCB1_Mux7_2_Not_ContIn, M9_UM9_1_PCB1_Mux7_2_line1); and2 M9_UM9_1_PCB1_Mux7_2_Mux2(in115, MuxSel, M9_UM9_1_PCB1_Mux7_2_line2); or2 M9_UM9_1_PCB1_Mux7_2_Mux3(M9_UM9_1_PCB1_Mux7_2_line1, M9_UM9_1_PCB1_Mux7_2_line2, M9_UM9_1_PCXAtempbus_2); inv M9_UM9_1_PCB1_Mux7_3_Mux0(MuxSel, M9_UM9_1_PCB1_Mux7_3_Not_ContIn); and2 M9_UM9_1_PCB1_Mux7_3_Mux1(in161, M9_UM9_1_PCB1_Mux7_3_Not_ContIn, M9_UM9_1_PCB1_Mux7_3_line1); and2 M9_UM9_1_PCB1_Mux7_3_Mux2(in141, MuxSel, M9_UM9_1_PCB1_Mux7_3_line2); or2 M9_UM9_1_PCB1_Mux7_3_Mux3(M9_UM9_1_PCB1_Mux7_3_line1, M9_UM9_1_PCB1_Mux7_3_line2, M9_UM9_1_PCXAtempbus_3); inv M9_UM9_1_PCB1_Mux7_4_Mux0(MuxSel, M9_UM9_1_PCB1_Mux7_4_Not_ContIn); and2 M9_UM9_1_PCB1_Mux7_4_Mux1(in212, M9_UM9_1_PCB1_Mux7_4_Not_ContIn, M9_UM9_1_PCB1_Mux7_4_line1); and2 M9_UM9_1_PCB1_Mux7_4_Mux2(vdd, MuxSel, M9_UM9_1_PCB1_Mux7_4_line2); or2 M9_UM9_1_PCB1_Mux7_4_Mux3(M9_UM9_1_PCB1_Mux7_4_line1, M9_UM9_1_PCB1_Mux7_4_line2, M9_UM9_1_PCXAtempbus_4); inv M9_UM9_1_PCB1_Mux7_5_Mux0(MuxSel, M9_UM9_1_PCB1_Mux7_5_Not_ContIn); and2 M9_UM9_1_PCB1_Mux7_5_Mux1(in211, M9_UM9_1_PCB1_Mux7_5_Not_ContIn, M9_UM9_1_PCB1_Mux7_5_line1); and2 M9_UM9_1_PCB1_Mux7_5_Mux2(vdd, MuxSel, M9_UM9_1_PCB1_Mux7_5_line2); or2 M9_UM9_1_PCB1_Mux7_5_Mux3(M9_UM9_1_PCB1_Mux7_5_line1, M9_UM9_1_PCB1_Mux7_5_line2, M9_UM9_1_PCXAtempbus_5); inv M9_UM9_1_PCB1_Mux7_6_Mux0(MuxSel, M9_UM9_1_PCB1_Mux7_6_Not_ContIn); and2 M9_UM9_1_PCB1_Mux7_6_Mux1(vdd, M9_UM9_1_PCB1_Mux7_6_Not_ContIn, M9_UM9_1_PCB1_Mux7_6_line1); and2 M9_UM9_1_PCB1_Mux7_6_Mux2(vdd, MuxSel, M9_UM9_1_PCB1_Mux7_6_line2); or2 M9_UM9_1_PCB1_Mux7_6_Mux3(M9_UM9_1_PCB1_Mux7_6_line1, M9_UM9_1_PCB1_Mux7_6_line2, M9_UM9_1_PCXAtempbus_6); inv M9_UM9_1_PCB2_Mux7_0_Mux0(MuxSel, M9_UM9_1_PCB2_Mux7_0_Not_ContIn); and2 M9_UM9_1_PCB2_Mux7_0_Mux1(M9_UM9_1_Not_PCYA0bus_0, M9_UM9_1_PCB2_Mux7_0_Not_ContIn, M9_UM9_1_PCB2_Mux7_0_line1); and2 M9_UM9_1_PCB2_Mux7_0_Mux2(in69, MuxSel, M9_UM9_1_PCB2_Mux7_0_line2); or2 M9_UM9_1_PCB2_Mux7_0_Mux3(M9_UM9_1_PCB2_Mux7_0_line1, M9_UM9_1_PCB2_Mux7_0_line2, M9_PCYAbus_0); inv M9_UM9_1_PCB2_Mux7_1_Mux0(MuxSel, M9_UM9_1_PCB2_Mux7_1_Not_ContIn); and2 M9_UM9_1_PCB2_Mux7_1_Mux1(M9_UM9_1_Not_PCYA0bus_1, M9_UM9_1_PCB2_Mux7_1_Not_ContIn, M9_UM9_1_PCB2_Mux7_1_line1); and2 M9_UM9_1_PCB2_Mux7_1_Mux2(in70, MuxSel, M9_UM9_1_PCB2_Mux7_1_line2); or2 M9_UM9_1_PCB2_Mux7_1_Mux3(M9_UM9_1_PCB2_Mux7_1_line1, M9_UM9_1_PCB2_Mux7_1_line2, M9_PCYAbus_1); inv M9_UM9_1_PCB2_Mux7_2_Mux0(MuxSel, M9_UM9_1_PCB2_Mux7_2_Not_ContIn); and2 M9_UM9_1_PCB2_Mux7_2_Mux1(M9_UM9_1_Not_PCYA0bus_2, M9_UM9_1_PCB2_Mux7_2_Not_ContIn, M9_UM9_1_PCB2_Mux7_2_line1); and2 M9_UM9_1_PCB2_Mux7_2_Mux2(in58, MuxSel, M9_UM9_1_PCB2_Mux7_2_line2); or2 M9_UM9_1_PCB2_Mux7_2_Mux3(M9_UM9_1_PCB2_Mux7_2_line1, M9_UM9_1_PCB2_Mux7_2_line2, M9_PCYAbus_2); inv M9_UM9_1_PCB2_Mux7_3_Mux0(MuxSel, M9_UM9_1_PCB2_Mux7_3_Not_ContIn); and2 M9_UM9_1_PCB2_Mux7_3_Mux1(M9_UM9_1_Not_PCYA0bus_3, M9_UM9_1_PCB2_Mux7_3_Not_ContIn, M9_UM9_1_PCB2_Mux7_3_line1); and2 M9_UM9_1_PCB2_Mux7_3_Mux2(in82, MuxSel, M9_UM9_1_PCB2_Mux7_3_line2); or2 M9_UM9_1_PCB2_Mux7_3_Mux3(M9_UM9_1_PCB2_Mux7_3_line1, M9_UM9_1_PCB2_Mux7_3_line2, M9_PCYAbus_3); inv M9_UM9_1_PCB2_Mux7_4_Mux0(MuxSel, M9_UM9_1_PCB2_Mux7_4_Not_ContIn); and2 M9_UM9_1_PCB2_Mux7_4_Mux1(M9_UM9_1_Not_PCYA0bus_4, M9_UM9_1_PCB2_Mux7_4_Not_ContIn, M9_UM9_1_PCB2_Mux7_4_line1); and2 M9_UM9_1_PCB2_Mux7_4_Mux2(in1455, MuxSel, M9_UM9_1_PCB2_Mux7_4_line2); or2 M9_UM9_1_PCB2_Mux7_4_Mux3(M9_UM9_1_PCB2_Mux7_4_line1, M9_UM9_1_PCB2_Mux7_4_line2, M9_PCYAbus_4); inv M9_UM9_1_PCB2_Mux7_5_Mux0(MuxSel, M9_UM9_1_PCB2_Mux7_5_Not_ContIn); and2 M9_UM9_1_PCB2_Mux7_5_Mux1(M9_UM9_1_Not_PCYA0bus_5, M9_UM9_1_PCB2_Mux7_5_Not_ContIn, M9_UM9_1_PCB2_Mux7_5_line1); and2 M9_UM9_1_PCB2_Mux7_5_Mux2(in2204, MuxSel, M9_UM9_1_PCB2_Mux7_5_line2); or2 M9_UM9_1_PCB2_Mux7_5_Mux3(M9_UM9_1_PCB2_Mux7_5_line1, M9_UM9_1_PCB2_Mux7_5_line2, M9_PCYAbus_5); inv M9_UM9_1_PCB2_Mux7_6_Mux0(MuxSel, M9_UM9_1_PCB2_Mux7_6_Not_ContIn); and2 M9_UM9_1_PCB2_Mux7_6_Mux1(M9_UM9_1_Not_PCYA0bus_6, M9_UM9_1_PCB2_Mux7_6_Not_ContIn, M9_UM9_1_PCB2_Mux7_6_line1); and2 M9_UM9_1_PCB2_Mux7_6_Mux2(in114, MuxSel, M9_UM9_1_PCB2_Mux7_6_line2); or2 M9_UM9_1_PCB2_Mux7_6_Mux3(M9_UM9_1_PCB2_Mux7_6_line1, M9_UM9_1_PCB2_Mux7_6_line2, M9_PCYAbus_6); inv M9_UM9_1_PCB3_Mux7_0_Mux0(MuxSel, M9_UM9_1_PCB3_Mux7_0_Not_ContIn); and2 M9_UM9_1_PCB3_Mux7_0_Mux1(in198, M9_UM9_1_PCB3_Mux7_0_Not_ContIn, M9_UM9_1_PCB3_Mux7_0_line1); and2 M9_UM9_1_PCB3_Mux7_0_Mux2(in41, MuxSel, M9_UM9_1_PCB3_Mux7_0_line2); or2 M9_UM9_1_PCB3_Mux7_0_Mux3(M9_UM9_1_PCB3_Mux7_0_line1, M9_UM9_1_PCB3_Mux7_0_line2, M9_UM9_1_PCYBtempbus_0); inv M9_UM9_1_PCB3_Mux7_1_Mux0(MuxSel, M9_UM9_1_PCB3_Mux7_1_Not_ContIn); and2 M9_UM9_1_PCB3_Mux7_1_Mux1(in208, M9_UM9_1_PCB3_Mux7_1_Not_ContIn, M9_UM9_1_PCB3_Mux7_1_line1); and2 M9_UM9_1_PCB3_Mux7_1_Mux2(in44, MuxSel, M9_UM9_1_PCB3_Mux7_1_line2); or2 M9_UM9_1_PCB3_Mux7_1_Mux3(M9_UM9_1_PCB3_Mux7_1_line1, M9_UM9_1_PCB3_Mux7_1_line2, M9_UM9_1_PCYBtempbus_1); inv M9_UM9_1_PCB3_Mux7_2_Mux0(MuxSel, M9_UM9_1_PCB3_Mux7_2_Not_ContIn); and2 M9_UM9_1_PCB3_Mux7_2_Mux1(in197, M9_UM9_1_PCB3_Mux7_2_Not_ContIn, M9_UM9_1_PCB3_Mux7_2_line1); and2 M9_UM9_1_PCB3_Mux7_2_Mux2(in115, MuxSel, M9_UM9_1_PCB3_Mux7_2_line2); or2 M9_UM9_1_PCB3_Mux7_2_Mux3(M9_UM9_1_PCB3_Mux7_2_line1, M9_UM9_1_PCB3_Mux7_2_line2, M9_UM9_1_PCYBtempbus_2); inv M9_UM9_1_PCB3_Mux7_3_Mux0(MuxSel, M9_UM9_1_PCB3_Mux7_3_Not_ContIn); and2 M9_UM9_1_PCB3_Mux7_3_Mux1(in181, M9_UM9_1_PCB3_Mux7_3_Not_ContIn, M9_UM9_1_PCB3_Mux7_3_line1); and2 M9_UM9_1_PCB3_Mux7_3_Mux2(in141, MuxSel, M9_UM9_1_PCB3_Mux7_3_line2); or2 M9_UM9_1_PCB3_Mux7_3_Mux3(M9_UM9_1_PCB3_Mux7_3_line1, M9_UM9_1_PCB3_Mux7_3_line2, M9_UM9_1_PCYBtempbus_3); inv M9_UM9_1_PCB3_Mux7_4_Mux0(MuxSel, M9_UM9_1_PCB3_Mux7_4_Not_ContIn); and2 M9_UM9_1_PCB3_Mux7_4_Mux1(in165, M9_UM9_1_PCB3_Mux7_4_Not_ContIn, M9_UM9_1_PCB3_Mux7_4_line1); and2 M9_UM9_1_PCB3_Mux7_4_Mux2(vdd, MuxSel, M9_UM9_1_PCB3_Mux7_4_line2); or2 M9_UM9_1_PCB3_Mux7_4_Mux3(M9_UM9_1_PCB3_Mux7_4_line1, M9_UM9_1_PCB3_Mux7_4_line2, M9_UM9_1_PCYBtempbus_4); inv M9_UM9_1_PCB3_Mux7_5_Mux0(MuxSel, M9_UM9_1_PCB3_Mux7_5_Not_ContIn); and2 M9_UM9_1_PCB3_Mux7_5_Mux1(in164, M9_UM9_1_PCB3_Mux7_5_Not_ContIn, M9_UM9_1_PCB3_Mux7_5_line1); and2 M9_UM9_1_PCB3_Mux7_5_Mux2(vdd, MuxSel, M9_UM9_1_PCB3_Mux7_5_line2); or2 M9_UM9_1_PCB3_Mux7_5_Mux3(M9_UM9_1_PCB3_Mux7_5_line1, M9_UM9_1_PCB3_Mux7_5_line2, M9_UM9_1_PCYBtempbus_5); inv M9_UM9_1_PCB3_Mux7_6_Mux0(MuxSel, M9_UM9_1_PCB3_Mux7_6_Not_ContIn); and2 M9_UM9_1_PCB3_Mux7_6_Mux1(in170, M9_UM9_1_PCB3_Mux7_6_Not_ContIn, M9_UM9_1_PCB3_Mux7_6_line1); and2 M9_UM9_1_PCB3_Mux7_6_Mux2(vdd, MuxSel, M9_UM9_1_PCB3_Mux7_6_line2); or2 M9_UM9_1_PCB3_Mux7_6_Mux3(M9_UM9_1_PCB3_Mux7_6_line1, M9_UM9_1_PCB3_Mux7_6_line2, M9_UM9_1_PCYBtempbus_6); and2 M9_UM9_1_PCB4_MN0(M9_UM9_1_PCXAtempbus_4, ContBusMask, M9_PCXAbus_4); and2 M9_UM9_1_PCB4_MN1(M9_UM9_1_PCXAtempbus_5, ContBusMask, M9_PCXAbus_5); and2 M9_UM9_1_PCB4_MN2(M9_UM9_1_PCXAtempbus_6, ContBusMask, M9_UM9_1_PCB4_line2); inv M9_UM9_1_PCB4_MN3(M9_UM9_1_PCB4_line2, M9_PCXAbus_6); and2 M9_UM9_1_PCB5_MN0(M9_UM9_1_PCYBtempbus_4, ContBusMask, M9_PCYBbus_4); and2 M9_UM9_1_PCB5_MN1(M9_UM9_1_PCYBtempbus_5, ContBusMask, M9_PCYBbus_5); and2 M9_UM9_1_PCB5_MN2(M9_UM9_1_PCYBtempbus_6, ContBusMask, M9_UM9_1_PCB5_line2); inv M9_UM9_1_PCB5_MN3(M9_UM9_1_PCB5_line2, M9_PCYBbus_6); inv M9_UM9_2_ParC0_PT0_Xo0(XAbus_5, M9_UM9_2_ParC0_PT0_NotA); inv M9_UM9_2_ParC0_PT0_Xo1(XAbus_6, M9_UM9_2_ParC0_PT0_NotB); nand2 M9_UM9_2_ParC0_PT0_Xo2(M9_UM9_2_ParC0_PT0_NotA, XAbus_6, M9_UM9_2_ParC0_PT0_line2); nand2 M9_UM9_2_ParC0_PT0_Xo3(M9_UM9_2_ParC0_PT0_NotB, XAbus_5, M9_UM9_2_ParC0_PT0_line3); nand2 M9_UM9_2_ParC0_PT0_Xo4(M9_UM9_2_ParC0_PT0_line2, M9_UM9_2_ParC0_PT0_line3, M9_UM9_2_ParC0_line0); inv M9_UM9_2_ParC0_PT1_Xo0(XAbus_7, M9_UM9_2_ParC0_PT1_NotA); inv M9_UM9_2_ParC0_PT1_Xo1(XAbus_8, M9_UM9_2_ParC0_PT1_NotB); nand2 M9_UM9_2_ParC0_PT1_Xo2(M9_UM9_2_ParC0_PT1_NotA, XAbus_8, M9_UM9_2_ParC0_PT1_line2); nand2 M9_UM9_2_ParC0_PT1_Xo3(M9_UM9_2_ParC0_PT1_NotB, XAbus_7, M9_UM9_2_ParC0_PT1_line3); nand2 M9_UM9_2_ParC0_PT1_Xo4(M9_UM9_2_ParC0_PT1_line2, M9_UM9_2_ParC0_PT1_line3, M9_UM9_2_ParC0_line1); inv M9_UM9_2_ParC0_PT2_Xo0(XAbus_1, M9_UM9_2_ParC0_PT2_NotA); inv M9_UM9_2_ParC0_PT2_Xo1(XAbus_2, M9_UM9_2_ParC0_PT2_NotB); nand2 M9_UM9_2_ParC0_PT2_Xo2(M9_UM9_2_ParC0_PT2_NotA, XAbus_2, M9_UM9_2_ParC0_PT2_line2); nand2 M9_UM9_2_ParC0_PT2_Xo3(M9_UM9_2_ParC0_PT2_NotB, XAbus_1, M9_UM9_2_ParC0_PT2_line3); nand2 M9_UM9_2_ParC0_PT2_Xo4(M9_UM9_2_ParC0_PT2_line2, M9_UM9_2_ParC0_PT2_line3, M9_UM9_2_ParC0_line2); inv M9_UM9_2_ParC0_PT3_Xo0(M9_UM9_1_PCXAtempbus_0, M9_UM9_2_ParC0_PT3_NotA); inv M9_UM9_2_ParC0_PT3_Xo1(M9_UM9_1_PCXAtempbus_1, M9_UM9_2_ParC0_PT3_NotB); nand2 M9_UM9_2_ParC0_PT3_Xo2(M9_UM9_2_ParC0_PT3_NotA, M9_UM9_1_PCXAtempbus_1, M9_UM9_2_ParC0_PT3_line2); nand2 M9_UM9_2_ParC0_PT3_Xo3(M9_UM9_2_ParC0_PT3_NotB, M9_UM9_1_PCXAtempbus_0, M9_UM9_2_ParC0_PT3_line3); nand2 M9_UM9_2_ParC0_PT3_Xo4(M9_UM9_2_ParC0_PT3_line2, M9_UM9_2_ParC0_PT3_line3, M9_UM9_2_ParC0_line3); inv M9_UM9_2_ParC0_PT4_Xo0(XAbus_3, M9_UM9_2_ParC0_PT4_NotA); inv M9_UM9_2_ParC0_PT4_Xo1(XAbus_4, M9_UM9_2_ParC0_PT4_NotB); nand2 M9_UM9_2_ParC0_PT4_Xo2(M9_UM9_2_ParC0_PT4_NotA, XAbus_4, M9_UM9_2_ParC0_PT4_line2); nand2 M9_UM9_2_ParC0_PT4_Xo3(M9_UM9_2_ParC0_PT4_NotB, XAbus_3, M9_UM9_2_ParC0_PT4_line3); nand2 M9_UM9_2_ParC0_PT4_Xo4(M9_UM9_2_ParC0_PT4_line2, M9_UM9_2_ParC0_PT4_line3, M9_UM9_2_ParC0_line4); inv M9_UM9_2_ParC0_PT5_Xo0(M9_UM9_2_ParC0_line0, M9_UM9_2_ParC0_PT5_NotA); inv M9_UM9_2_ParC0_PT5_Xo1(M9_UM9_2_ParC0_line1, M9_UM9_2_ParC0_PT5_NotB); nand2 M9_UM9_2_ParC0_PT5_Xo2(M9_UM9_2_ParC0_PT5_NotA, M9_UM9_2_ParC0_line1, M9_UM9_2_ParC0_PT5_line2); nand2 M9_UM9_2_ParC0_PT5_Xo3(M9_UM9_2_ParC0_PT5_NotB, M9_UM9_2_ParC0_line0, M9_UM9_2_ParC0_PT5_line3); nand2 M9_UM9_2_ParC0_PT5_Xo4(M9_UM9_2_ParC0_PT5_line2, M9_UM9_2_ParC0_PT5_line3, M9_UM9_2_ParC0_line5); inv M9_UM9_2_ParC0_PT6_Xo3_0(M9_UM9_2_ParC0_line2, M9_UM9_2_ParC0_PT6_NotA); inv M9_UM9_2_ParC0_PT6_Xo3_1(M9_UM9_2_ParC0_line3, M9_UM9_2_ParC0_PT6_NotB); inv M9_UM9_2_ParC0_PT6_Xo3_2(M9_UM9_2_ParC0_line4, M9_UM9_2_ParC0_PT6_NotC); and3 M9_UM9_2_ParC0_PT6_Xo3_3(M9_UM9_2_ParC0_PT6_NotA, M9_UM9_2_ParC0_PT6_NotB, M9_UM9_2_ParC0_line4, M9_UM9_2_ParC0_PT6_line3); and3 M9_UM9_2_ParC0_PT6_Xo3_4(M9_UM9_2_ParC0_PT6_NotA, M9_UM9_2_ParC0_line3, M9_UM9_2_ParC0_PT6_NotC, M9_UM9_2_ParC0_PT6_line4); and3 M9_UM9_2_ParC0_PT6_Xo3_5(M9_UM9_2_ParC0_line2, M9_UM9_2_ParC0_PT6_NotB, M9_UM9_2_ParC0_PT6_NotC, M9_UM9_2_ParC0_PT6_line5); and3 M9_UM9_2_ParC0_PT6_Xo3_6(M9_UM9_2_ParC0_line2, M9_UM9_2_ParC0_line3, M9_UM9_2_ParC0_line4, M9_UM9_2_ParC0_PT6_line6); nor2 M9_UM9_2_ParC0_PT6_Xo3_7(M9_UM9_2_ParC0_PT6_line3, M9_UM9_2_ParC0_PT6_line4, M9_UM9_2_ParC0_PT6_line7); nor2 M9_UM9_2_ParC0_PT6_Xo3_8(M9_UM9_2_ParC0_PT6_line5, M9_UM9_2_ParC0_PT6_line6, M9_UM9_2_ParC0_PT6_line8); nand2 M9_UM9_2_ParC0_PT6_Xo3_9(M9_UM9_2_ParC0_PT6_line7, M9_UM9_2_ParC0_PT6_line8, M9_UM9_2_ParC0_line6); inv M9_UM9_2_ParC0_PT7_Xo0(M9_UM9_2_ParC0_line5, M9_UM9_2_ParC0_PT7_NotA); inv M9_UM9_2_ParC0_PT7_Xo1(M9_UM9_2_ParC0_line6, M9_UM9_2_ParC0_PT7_NotB); nand2 M9_UM9_2_ParC0_PT7_Xo2(M9_UM9_2_ParC0_PT7_NotA, M9_UM9_2_ParC0_line6, M9_UM9_2_ParC0_PT7_line2); nand2 M9_UM9_2_ParC0_PT7_Xo3(M9_UM9_2_ParC0_PT7_NotB, M9_UM9_2_ParC0_line5, M9_UM9_2_ParC0_PT7_line3); nand2 M9_UM9_2_ParC0_PT7_Xo4(M9_UM9_2_ParC0_PT7_line2, M9_UM9_2_ParC0_PT7_line3, M9_UM9_2_XaP0); inv M9_UM9_2_ParC1_PT0_Xo0(XAbus_14, M9_UM9_2_ParC1_PT0_NotA); inv M9_UM9_2_ParC1_PT0_Xo1(XAbus_15, M9_UM9_2_ParC1_PT0_NotB); nand2 M9_UM9_2_ParC1_PT0_Xo2(M9_UM9_2_ParC1_PT0_NotA, XAbus_15, M9_UM9_2_ParC1_PT0_line2); nand2 M9_UM9_2_ParC1_PT0_Xo3(M9_UM9_2_ParC1_PT0_NotB, XAbus_14, M9_UM9_2_ParC1_PT0_line3); nand2 M9_UM9_2_ParC1_PT0_Xo4(M9_UM9_2_ParC1_PT0_line2, M9_UM9_2_ParC1_PT0_line3, M9_UM9_2_ParC1_line0); inv M9_UM9_2_ParC1_PT1_Xo0(XAbus_16, M9_UM9_2_ParC1_PT1_NotA); inv M9_UM9_2_ParC1_PT1_Xo1(XAbus_17, M9_UM9_2_ParC1_PT1_NotB); nand2 M9_UM9_2_ParC1_PT1_Xo2(M9_UM9_2_ParC1_PT1_NotA, XAbus_17, M9_UM9_2_ParC1_PT1_line2); nand2 M9_UM9_2_ParC1_PT1_Xo3(M9_UM9_2_ParC1_PT1_NotB, XAbus_16, M9_UM9_2_ParC1_PT1_line3); nand2 M9_UM9_2_ParC1_PT1_Xo4(M9_UM9_2_ParC1_PT1_line2, M9_UM9_2_ParC1_PT1_line3, M9_UM9_2_ParC1_line1); inv M9_UM9_2_ParC1_PT2_Xo0(XAbus_10, M9_UM9_2_ParC1_PT2_NotA); inv M9_UM9_2_ParC1_PT2_Xo1(XAbus_11, M9_UM9_2_ParC1_PT2_NotB); nand2 M9_UM9_2_ParC1_PT2_Xo2(M9_UM9_2_ParC1_PT2_NotA, XAbus_11, M9_UM9_2_ParC1_PT2_line2); nand2 M9_UM9_2_ParC1_PT2_Xo3(M9_UM9_2_ParC1_PT2_NotB, XAbus_10, M9_UM9_2_ParC1_PT2_line3); nand2 M9_UM9_2_ParC1_PT2_Xo4(M9_UM9_2_ParC1_PT2_line2, M9_UM9_2_ParC1_PT2_line3, M9_UM9_2_ParC1_line2); inv M9_UM9_2_ParC1_PT3_Xo0(M9_UM9_1_PCXAtempbus_2, M9_UM9_2_ParC1_PT3_NotA); inv M9_UM9_2_ParC1_PT3_Xo1(XAbus_9, M9_UM9_2_ParC1_PT3_NotB); nand2 M9_UM9_2_ParC1_PT3_Xo2(M9_UM9_2_ParC1_PT3_NotA, XAbus_9, M9_UM9_2_ParC1_PT3_line2); nand2 M9_UM9_2_ParC1_PT3_Xo3(M9_UM9_2_ParC1_PT3_NotB, M9_UM9_1_PCXAtempbus_2, M9_UM9_2_ParC1_PT3_line3); nand2 M9_UM9_2_ParC1_PT3_Xo4(M9_UM9_2_ParC1_PT3_line2, M9_UM9_2_ParC1_PT3_line3, M9_UM9_2_ParC1_line3); inv M9_UM9_2_ParC1_PT4_Xo0(XAbus_12, M9_UM9_2_ParC1_PT4_NotA); inv M9_UM9_2_ParC1_PT4_Xo1(XAbus_13, M9_UM9_2_ParC1_PT4_NotB); nand2 M9_UM9_2_ParC1_PT4_Xo2(M9_UM9_2_ParC1_PT4_NotA, XAbus_13, M9_UM9_2_ParC1_PT4_line2); nand2 M9_UM9_2_ParC1_PT4_Xo3(M9_UM9_2_ParC1_PT4_NotB, XAbus_12, M9_UM9_2_ParC1_PT4_line3); nand2 M9_UM9_2_ParC1_PT4_Xo4(M9_UM9_2_ParC1_PT4_line2, M9_UM9_2_ParC1_PT4_line3, M9_UM9_2_ParC1_line4); inv M9_UM9_2_ParC1_PT5_Xo0(M9_UM9_2_ParC1_line0, M9_UM9_2_ParC1_PT5_NotA); inv M9_UM9_2_ParC1_PT5_Xo1(M9_UM9_2_ParC1_line1, M9_UM9_2_ParC1_PT5_NotB); nand2 M9_UM9_2_ParC1_PT5_Xo2(M9_UM9_2_ParC1_PT5_NotA, M9_UM9_2_ParC1_line1, M9_UM9_2_ParC1_PT5_line2); nand2 M9_UM9_2_ParC1_PT5_Xo3(M9_UM9_2_ParC1_PT5_NotB, M9_UM9_2_ParC1_line0, M9_UM9_2_ParC1_PT5_line3); nand2 M9_UM9_2_ParC1_PT5_Xo4(M9_UM9_2_ParC1_PT5_line2, M9_UM9_2_ParC1_PT5_line3, M9_UM9_2_ParC1_line5); inv M9_UM9_2_ParC1_PT6_Xo3_0(M9_UM9_2_ParC1_line2, M9_UM9_2_ParC1_PT6_NotA); inv M9_UM9_2_ParC1_PT6_Xo3_1(M9_UM9_2_ParC1_line3, M9_UM9_2_ParC1_PT6_NotB); inv M9_UM9_2_ParC1_PT6_Xo3_2(M9_UM9_2_ParC1_line4, M9_UM9_2_ParC1_PT6_NotC); and3 M9_UM9_2_ParC1_PT6_Xo3_3(M9_UM9_2_ParC1_PT6_NotA, M9_UM9_2_ParC1_PT6_NotB, M9_UM9_2_ParC1_line4, M9_UM9_2_ParC1_PT6_line3); and3 M9_UM9_2_ParC1_PT6_Xo3_4(M9_UM9_2_ParC1_PT6_NotA, M9_UM9_2_ParC1_line3, M9_UM9_2_ParC1_PT6_NotC, M9_UM9_2_ParC1_PT6_line4); and3 M9_UM9_2_ParC1_PT6_Xo3_5(M9_UM9_2_ParC1_line2, M9_UM9_2_ParC1_PT6_NotB, M9_UM9_2_ParC1_PT6_NotC, M9_UM9_2_ParC1_PT6_line5); and3 M9_UM9_2_ParC1_PT6_Xo3_6(M9_UM9_2_ParC1_line2, M9_UM9_2_ParC1_line3, M9_UM9_2_ParC1_line4, M9_UM9_2_ParC1_PT6_line6); nor2 M9_UM9_2_ParC1_PT6_Xo3_7(M9_UM9_2_ParC1_PT6_line3, M9_UM9_2_ParC1_PT6_line4, M9_UM9_2_ParC1_PT6_line7); nor2 M9_UM9_2_ParC1_PT6_Xo3_8(M9_UM9_2_ParC1_PT6_line5, M9_UM9_2_ParC1_PT6_line6, M9_UM9_2_ParC1_PT6_line8); nand2 M9_UM9_2_ParC1_PT6_Xo3_9(M9_UM9_2_ParC1_PT6_line7, M9_UM9_2_ParC1_PT6_line8, M9_UM9_2_ParC1_line6); inv M9_UM9_2_ParC1_PT7_Xo0(M9_UM9_2_ParC1_line5, M9_UM9_2_ParC1_PT7_NotA); inv M9_UM9_2_ParC1_PT7_Xo1(M9_UM9_2_ParC1_line6, M9_UM9_2_ParC1_PT7_NotB); nand2 M9_UM9_2_ParC1_PT7_Xo2(M9_UM9_2_ParC1_PT7_NotA, M9_UM9_2_ParC1_line6, M9_UM9_2_ParC1_PT7_line2); nand2 M9_UM9_2_ParC1_PT7_Xo3(M9_UM9_2_ParC1_PT7_NotB, M9_UM9_2_ParC1_line5, M9_UM9_2_ParC1_PT7_line3); nand2 M9_UM9_2_ParC1_PT7_Xo4(M9_UM9_2_ParC1_PT7_line2, M9_UM9_2_ParC1_PT7_line3, M9_UM9_2_XaP1); inv M9_UM9_2_ParC2_PT0_Xo0(XAbus_23, M9_UM9_2_ParC2_PT0_NotA); inv M9_UM9_2_ParC2_PT0_Xo1(XAbus_24, M9_UM9_2_ParC2_PT0_NotB); nand2 M9_UM9_2_ParC2_PT0_Xo2(M9_UM9_2_ParC2_PT0_NotA, XAbus_24, M9_UM9_2_ParC2_PT0_line2); nand2 M9_UM9_2_ParC2_PT0_Xo3(M9_UM9_2_ParC2_PT0_NotB, XAbus_23, M9_UM9_2_ParC2_PT0_line3); nand2 M9_UM9_2_ParC2_PT0_Xo4(M9_UM9_2_ParC2_PT0_line2, M9_UM9_2_ParC2_PT0_line3, M9_UM9_2_ParC2_line0); inv M9_UM9_2_ParC2_PT1_Xo0(XAbus_25, M9_UM9_2_ParC2_PT1_NotA); inv M9_UM9_2_ParC2_PT1_Xo1(XAbus_26, M9_UM9_2_ParC2_PT1_NotB); nand2 M9_UM9_2_ParC2_PT1_Xo2(M9_UM9_2_ParC2_PT1_NotA, XAbus_26, M9_UM9_2_ParC2_PT1_line2); nand2 M9_UM9_2_ParC2_PT1_Xo3(M9_UM9_2_ParC2_PT1_NotB, XAbus_25, M9_UM9_2_ParC2_PT1_line3); nand2 M9_UM9_2_ParC2_PT1_Xo4(M9_UM9_2_ParC2_PT1_line2, M9_UM9_2_ParC2_PT1_line3, M9_UM9_2_ParC2_line1); inv M9_UM9_2_ParC2_PT2_Xo0(XAbus_19, M9_UM9_2_ParC2_PT2_NotA); inv M9_UM9_2_ParC2_PT2_Xo1(XAbus_20, M9_UM9_2_ParC2_PT2_NotB); nand2 M9_UM9_2_ParC2_PT2_Xo2(M9_UM9_2_ParC2_PT2_NotA, XAbus_20, M9_UM9_2_ParC2_PT2_line2); nand2 M9_UM9_2_ParC2_PT2_Xo3(M9_UM9_2_ParC2_PT2_NotB, XAbus_19, M9_UM9_2_ParC2_PT2_line3); nand2 M9_UM9_2_ParC2_PT2_Xo4(M9_UM9_2_ParC2_PT2_line2, M9_UM9_2_ParC2_PT2_line3, M9_UM9_2_ParC2_line2); inv M9_UM9_2_ParC2_PT3_Xo0(M9_UM9_1_PCXAtempbus_3, M9_UM9_2_ParC2_PT3_NotA); inv M9_UM9_2_ParC2_PT3_Xo1(XAbus_18, M9_UM9_2_ParC2_PT3_NotB); nand2 M9_UM9_2_ParC2_PT3_Xo2(M9_UM9_2_ParC2_PT3_NotA, XAbus_18, M9_UM9_2_ParC2_PT3_line2); nand2 M9_UM9_2_ParC2_PT3_Xo3(M9_UM9_2_ParC2_PT3_NotB, M9_UM9_1_PCXAtempbus_3, M9_UM9_2_ParC2_PT3_line3); nand2 M9_UM9_2_ParC2_PT3_Xo4(M9_UM9_2_ParC2_PT3_line2, M9_UM9_2_ParC2_PT3_line3, M9_UM9_2_ParC2_line3); inv M9_UM9_2_ParC2_PT4_Xo0(XAbus_21, M9_UM9_2_ParC2_PT4_NotA); inv M9_UM9_2_ParC2_PT4_Xo1(XAbus_22, M9_UM9_2_ParC2_PT4_NotB); nand2 M9_UM9_2_ParC2_PT4_Xo2(M9_UM9_2_ParC2_PT4_NotA, XAbus_22, M9_UM9_2_ParC2_PT4_line2); nand2 M9_UM9_2_ParC2_PT4_Xo3(M9_UM9_2_ParC2_PT4_NotB, XAbus_21, M9_UM9_2_ParC2_PT4_line3); nand2 M9_UM9_2_ParC2_PT4_Xo4(M9_UM9_2_ParC2_PT4_line2, M9_UM9_2_ParC2_PT4_line3, M9_UM9_2_ParC2_line4); inv M9_UM9_2_ParC2_PT5_Xo0(M9_UM9_2_ParC2_line0, M9_UM9_2_ParC2_PT5_NotA); inv M9_UM9_2_ParC2_PT5_Xo1(M9_UM9_2_ParC2_line1, M9_UM9_2_ParC2_PT5_NotB); nand2 M9_UM9_2_ParC2_PT5_Xo2(M9_UM9_2_ParC2_PT5_NotA, M9_UM9_2_ParC2_line1, M9_UM9_2_ParC2_PT5_line2); nand2 M9_UM9_2_ParC2_PT5_Xo3(M9_UM9_2_ParC2_PT5_NotB, M9_UM9_2_ParC2_line0, M9_UM9_2_ParC2_PT5_line3); nand2 M9_UM9_2_ParC2_PT5_Xo4(M9_UM9_2_ParC2_PT5_line2, M9_UM9_2_ParC2_PT5_line3, M9_UM9_2_ParC2_line5); inv M9_UM9_2_ParC2_PT6_Xo3_0(M9_UM9_2_ParC2_line2, M9_UM9_2_ParC2_PT6_NotA); inv M9_UM9_2_ParC2_PT6_Xo3_1(M9_UM9_2_ParC2_line3, M9_UM9_2_ParC2_PT6_NotB); inv M9_UM9_2_ParC2_PT6_Xo3_2(M9_UM9_2_ParC2_line4, M9_UM9_2_ParC2_PT6_NotC); and3 M9_UM9_2_ParC2_PT6_Xo3_3(M9_UM9_2_ParC2_PT6_NotA, M9_UM9_2_ParC2_PT6_NotB, M9_UM9_2_ParC2_line4, M9_UM9_2_ParC2_PT6_line3); and3 M9_UM9_2_ParC2_PT6_Xo3_4(M9_UM9_2_ParC2_PT6_NotA, M9_UM9_2_ParC2_line3, M9_UM9_2_ParC2_PT6_NotC, M9_UM9_2_ParC2_PT6_line4); and3 M9_UM9_2_ParC2_PT6_Xo3_5(M9_UM9_2_ParC2_line2, M9_UM9_2_ParC2_PT6_NotB, M9_UM9_2_ParC2_PT6_NotC, M9_UM9_2_ParC2_PT6_line5); and3 M9_UM9_2_ParC2_PT6_Xo3_6(M9_UM9_2_ParC2_line2, M9_UM9_2_ParC2_line3, M9_UM9_2_ParC2_line4, M9_UM9_2_ParC2_PT6_line6); nor2 M9_UM9_2_ParC2_PT6_Xo3_7(M9_UM9_2_ParC2_PT6_line3, M9_UM9_2_ParC2_PT6_line4, M9_UM9_2_ParC2_PT6_line7); nor2 M9_UM9_2_ParC2_PT6_Xo3_8(M9_UM9_2_ParC2_PT6_line5, M9_UM9_2_ParC2_PT6_line6, M9_UM9_2_ParC2_PT6_line8); nand2 M9_UM9_2_ParC2_PT6_Xo3_9(M9_UM9_2_ParC2_PT6_line7, M9_UM9_2_ParC2_PT6_line8, M9_UM9_2_ParC2_line6); inv M9_UM9_2_ParC2_PT7_Xo0(M9_UM9_2_ParC2_line5, M9_UM9_2_ParC2_PT7_NotA); inv M9_UM9_2_ParC2_PT7_Xo1(M9_UM9_2_ParC2_line6, M9_UM9_2_ParC2_PT7_NotB); nand2 M9_UM9_2_ParC2_PT7_Xo2(M9_UM9_2_ParC2_PT7_NotA, M9_UM9_2_ParC2_line6, M9_UM9_2_ParC2_PT7_line2); nand2 M9_UM9_2_ParC2_PT7_Xo3(M9_UM9_2_ParC2_PT7_NotB, M9_UM9_2_ParC2_line5, M9_UM9_2_ParC2_PT7_line3); nand2 M9_UM9_2_ParC2_PT7_Xo4(M9_UM9_2_ParC2_PT7_line2, M9_UM9_2_ParC2_PT7_line3, M9_UM9_2_XaP2); inv M9_UM9_2_ParC3_PT0_Xo0(M9_PCXAbus_4, M9_UM9_2_ParC3_PT0_NotA); inv M9_UM9_2_ParC3_PT0_Xo1(M9_PCXAbus_5, M9_UM9_2_ParC3_PT0_NotB); nand2 M9_UM9_2_ParC3_PT0_Xo2(M9_UM9_2_ParC3_PT0_NotA, M9_PCXAbus_5, M9_UM9_2_ParC3_PT0_line2); nand2 M9_UM9_2_ParC3_PT0_Xo3(M9_UM9_2_ParC3_PT0_NotB, M9_PCXAbus_4, M9_UM9_2_ParC3_PT0_line3); nand2 M9_UM9_2_ParC3_PT0_Xo4(M9_UM9_2_ParC3_PT0_line2, M9_UM9_2_ParC3_PT0_line3, M9_UM9_2_ParC3_line0); inv M9_UM9_2_ParC3_PT1_Xo0(M9_PCXAbus_6, M9_UM9_2_ParC3_PT1_NotA); inv M9_UM9_2_ParC3_PT1_Xo1(XAbus_27, M9_UM9_2_ParC3_PT1_NotB); nand2 M9_UM9_2_ParC3_PT1_Xo2(M9_UM9_2_ParC3_PT1_NotA, XAbus_27, M9_UM9_2_ParC3_PT1_line2); nand2 M9_UM9_2_ParC3_PT1_Xo3(M9_UM9_2_ParC3_PT1_NotB, M9_PCXAbus_6, M9_UM9_2_ParC3_PT1_line3); nand2 M9_UM9_2_ParC3_PT1_Xo4(M9_UM9_2_ParC3_PT1_line2, M9_UM9_2_ParC3_PT1_line3, M9_UM9_2_ParC3_line1); inv M9_UM9_2_ParC3_PT2_Xo0(XAbus_28, M9_UM9_2_ParC3_PT2_NotA); inv M9_UM9_2_ParC3_PT2_Xo1(XAbus_29, M9_UM9_2_ParC3_PT2_NotB); nand2 M9_UM9_2_ParC3_PT2_Xo2(M9_UM9_2_ParC3_PT2_NotA, XAbus_29, M9_UM9_2_ParC3_PT2_line2); nand2 M9_UM9_2_ParC3_PT2_Xo3(M9_UM9_2_ParC3_PT2_NotB, XAbus_28, M9_UM9_2_ParC3_PT2_line3); nand2 M9_UM9_2_ParC3_PT2_Xo4(M9_UM9_2_ParC3_PT2_line2, M9_UM9_2_ParC3_PT2_line3, M9_UM9_2_ParC3_line2); inv M9_UM9_2_ParC3_PT3_Xo0(XAbus_30, M9_UM9_2_ParC3_PT3_NotA); inv M9_UM9_2_ParC3_PT3_Xo1(XAbus_31, M9_UM9_2_ParC3_PT3_NotB); nand2 M9_UM9_2_ParC3_PT3_Xo2(M9_UM9_2_ParC3_PT3_NotA, XAbus_31, M9_UM9_2_ParC3_PT3_line2); nand2 M9_UM9_2_ParC3_PT3_Xo3(M9_UM9_2_ParC3_PT3_NotB, XAbus_30, M9_UM9_2_ParC3_PT3_line3); nand2 M9_UM9_2_ParC3_PT3_Xo4(M9_UM9_2_ParC3_PT3_line2, M9_UM9_2_ParC3_PT3_line3, M9_UM9_2_ParC3_line3); inv M9_UM9_2_ParC3_PT4_Xo3_0(M9_UM9_2_ParC3_line1, M9_UM9_2_ParC3_PT4_NotA); inv M9_UM9_2_ParC3_PT4_Xo3_1(M9_UM9_2_ParC3_line2, M9_UM9_2_ParC3_PT4_NotB); inv M9_UM9_2_ParC3_PT4_Xo3_2(M9_UM9_2_ParC3_line3, M9_UM9_2_ParC3_PT4_NotC); and3 M9_UM9_2_ParC3_PT4_Xo3_3(M9_UM9_2_ParC3_PT4_NotA, M9_UM9_2_ParC3_PT4_NotB, M9_UM9_2_ParC3_line3, M9_UM9_2_ParC3_PT4_line3); and3 M9_UM9_2_ParC3_PT4_Xo3_4(M9_UM9_2_ParC3_PT4_NotA, M9_UM9_2_ParC3_line2, M9_UM9_2_ParC3_PT4_NotC, M9_UM9_2_ParC3_PT4_line4); and3 M9_UM9_2_ParC3_PT4_Xo3_5(M9_UM9_2_ParC3_line1, M9_UM9_2_ParC3_PT4_NotB, M9_UM9_2_ParC3_PT4_NotC, M9_UM9_2_ParC3_PT4_line5); and3 M9_UM9_2_ParC3_PT4_Xo3_6(M9_UM9_2_ParC3_line1, M9_UM9_2_ParC3_line2, M9_UM9_2_ParC3_line3, M9_UM9_2_ParC3_PT4_line6); nor2 M9_UM9_2_ParC3_PT4_Xo3_7(M9_UM9_2_ParC3_PT4_line3, M9_UM9_2_ParC3_PT4_line4, M9_UM9_2_ParC3_PT4_line7); nor2 M9_UM9_2_ParC3_PT4_Xo3_8(M9_UM9_2_ParC3_PT4_line5, M9_UM9_2_ParC3_PT4_line6, M9_UM9_2_ParC3_PT4_line8); nand2 M9_UM9_2_ParC3_PT4_Xo3_9(M9_UM9_2_ParC3_PT4_line7, M9_UM9_2_ParC3_PT4_line8, M9_UM9_2_ParC3_line4); inv M9_UM9_2_ParC3_PT5_Xo0(M9_UM9_2_ParC3_line0, M9_UM9_2_ParC3_PT5_NotA); inv M9_UM9_2_ParC3_PT5_Xo1(M9_UM9_2_ParC3_line4, M9_UM9_2_ParC3_PT5_NotB); nand2 M9_UM9_2_ParC3_PT5_Xo2(M9_UM9_2_ParC3_PT5_NotA, M9_UM9_2_ParC3_line4, M9_UM9_2_ParC3_PT5_line2); nand2 M9_UM9_2_ParC3_PT5_Xo3(M9_UM9_2_ParC3_PT5_NotB, M9_UM9_2_ParC3_line0, M9_UM9_2_ParC3_PT5_line3); nand2 M9_UM9_2_ParC3_PT5_Xo4(M9_UM9_2_ParC3_PT5_line2, M9_UM9_2_ParC3_PT5_line3, M9_UM9_2_XaP3); inv M9_UM9_2_ParC4_PT0_Xo0(YAbus_5, M9_UM9_2_ParC4_PT0_NotA); inv M9_UM9_2_ParC4_PT0_Xo1(YAbus_6, M9_UM9_2_ParC4_PT0_NotB); nand2 M9_UM9_2_ParC4_PT0_Xo2(M9_UM9_2_ParC4_PT0_NotA, YAbus_6, M9_UM9_2_ParC4_PT0_line2); nand2 M9_UM9_2_ParC4_PT0_Xo3(M9_UM9_2_ParC4_PT0_NotB, YAbus_5, M9_UM9_2_ParC4_PT0_line3); nand2 M9_UM9_2_ParC4_PT0_Xo4(M9_UM9_2_ParC4_PT0_line2, M9_UM9_2_ParC4_PT0_line3, M9_UM9_2_ParC4_line0); inv M9_UM9_2_ParC4_PT1_Xo0(YAbus_7, M9_UM9_2_ParC4_PT1_NotA); inv M9_UM9_2_ParC4_PT1_Xo1(YAbus_8, M9_UM9_2_ParC4_PT1_NotB); nand2 M9_UM9_2_ParC4_PT1_Xo2(M9_UM9_2_ParC4_PT1_NotA, YAbus_8, M9_UM9_2_ParC4_PT1_line2); nand2 M9_UM9_2_ParC4_PT1_Xo3(M9_UM9_2_ParC4_PT1_NotB, YAbus_7, M9_UM9_2_ParC4_PT1_line3); nand2 M9_UM9_2_ParC4_PT1_Xo4(M9_UM9_2_ParC4_PT1_line2, M9_UM9_2_ParC4_PT1_line3, M9_UM9_2_ParC4_line1); inv M9_UM9_2_ParC4_PT2_Xo0(YAbus_1, M9_UM9_2_ParC4_PT2_NotA); inv M9_UM9_2_ParC4_PT2_Xo1(YAbus_2, M9_UM9_2_ParC4_PT2_NotB); nand2 M9_UM9_2_ParC4_PT2_Xo2(M9_UM9_2_ParC4_PT2_NotA, YAbus_2, M9_UM9_2_ParC4_PT2_line2); nand2 M9_UM9_2_ParC4_PT2_Xo3(M9_UM9_2_ParC4_PT2_NotB, YAbus_1, M9_UM9_2_ParC4_PT2_line3); nand2 M9_UM9_2_ParC4_PT2_Xo4(M9_UM9_2_ParC4_PT2_line2, M9_UM9_2_ParC4_PT2_line3, M9_UM9_2_ParC4_line2); inv M9_UM9_2_ParC4_PT3_Xo0(M9_PCYAbus_0, M9_UM9_2_ParC4_PT3_NotA); inv M9_UM9_2_ParC4_PT3_Xo1(M9_PCYAbus_1, M9_UM9_2_ParC4_PT3_NotB); nand2 M9_UM9_2_ParC4_PT3_Xo2(M9_UM9_2_ParC4_PT3_NotA, M9_PCYAbus_1, M9_UM9_2_ParC4_PT3_line2); nand2 M9_UM9_2_ParC4_PT3_Xo3(M9_UM9_2_ParC4_PT3_NotB, M9_PCYAbus_0, M9_UM9_2_ParC4_PT3_line3); nand2 M9_UM9_2_ParC4_PT3_Xo4(M9_UM9_2_ParC4_PT3_line2, M9_UM9_2_ParC4_PT3_line3, M9_UM9_2_ParC4_line3); inv M9_UM9_2_ParC4_PT4_Xo0(YAbus_3, M9_UM9_2_ParC4_PT4_NotA); inv M9_UM9_2_ParC4_PT4_Xo1(YAbus_4, M9_UM9_2_ParC4_PT4_NotB); nand2 M9_UM9_2_ParC4_PT4_Xo2(M9_UM9_2_ParC4_PT4_NotA, YAbus_4, M9_UM9_2_ParC4_PT4_line2); nand2 M9_UM9_2_ParC4_PT4_Xo3(M9_UM9_2_ParC4_PT4_NotB, YAbus_3, M9_UM9_2_ParC4_PT4_line3); nand2 M9_UM9_2_ParC4_PT4_Xo4(M9_UM9_2_ParC4_PT4_line2, M9_UM9_2_ParC4_PT4_line3, M9_UM9_2_ParC4_line4); inv M9_UM9_2_ParC4_PT5_Xo0(M9_UM9_2_ParC4_line0, M9_UM9_2_ParC4_PT5_NotA); inv M9_UM9_2_ParC4_PT5_Xo1(M9_UM9_2_ParC4_line1, M9_UM9_2_ParC4_PT5_NotB); nand2 M9_UM9_2_ParC4_PT5_Xo2(M9_UM9_2_ParC4_PT5_NotA, M9_UM9_2_ParC4_line1, M9_UM9_2_ParC4_PT5_line2); nand2 M9_UM9_2_ParC4_PT5_Xo3(M9_UM9_2_ParC4_PT5_NotB, M9_UM9_2_ParC4_line0, M9_UM9_2_ParC4_PT5_line3); nand2 M9_UM9_2_ParC4_PT5_Xo4(M9_UM9_2_ParC4_PT5_line2, M9_UM9_2_ParC4_PT5_line3, M9_UM9_2_ParC4_line5); inv M9_UM9_2_ParC4_PT6_Xo3_0(M9_UM9_2_ParC4_line2, M9_UM9_2_ParC4_PT6_NotA); inv M9_UM9_2_ParC4_PT6_Xo3_1(M9_UM9_2_ParC4_line3, M9_UM9_2_ParC4_PT6_NotB); inv M9_UM9_2_ParC4_PT6_Xo3_2(M9_UM9_2_ParC4_line4, M9_UM9_2_ParC4_PT6_NotC); and3 M9_UM9_2_ParC4_PT6_Xo3_3(M9_UM9_2_ParC4_PT6_NotA, M9_UM9_2_ParC4_PT6_NotB, M9_UM9_2_ParC4_line4, M9_UM9_2_ParC4_PT6_line3); and3 M9_UM9_2_ParC4_PT6_Xo3_4(M9_UM9_2_ParC4_PT6_NotA, M9_UM9_2_ParC4_line3, M9_UM9_2_ParC4_PT6_NotC, M9_UM9_2_ParC4_PT6_line4); and3 M9_UM9_2_ParC4_PT6_Xo3_5(M9_UM9_2_ParC4_line2, M9_UM9_2_ParC4_PT6_NotB, M9_UM9_2_ParC4_PT6_NotC, M9_UM9_2_ParC4_PT6_line5); and3 M9_UM9_2_ParC4_PT6_Xo3_6(M9_UM9_2_ParC4_line2, M9_UM9_2_ParC4_line3, M9_UM9_2_ParC4_line4, M9_UM9_2_ParC4_PT6_line6); nor2 M9_UM9_2_ParC4_PT6_Xo3_7(M9_UM9_2_ParC4_PT6_line3, M9_UM9_2_ParC4_PT6_line4, M9_UM9_2_ParC4_PT6_line7); nor2 M9_UM9_2_ParC4_PT6_Xo3_8(M9_UM9_2_ParC4_PT6_line5, M9_UM9_2_ParC4_PT6_line6, M9_UM9_2_ParC4_PT6_line8); nand2 M9_UM9_2_ParC4_PT6_Xo3_9(M9_UM9_2_ParC4_PT6_line7, M9_UM9_2_ParC4_PT6_line8, M9_UM9_2_ParC4_line6); inv M9_UM9_2_ParC4_PT7_Xo0(M9_UM9_2_ParC4_line5, M9_UM9_2_ParC4_PT7_NotA); inv M9_UM9_2_ParC4_PT7_Xo1(M9_UM9_2_ParC4_line6, M9_UM9_2_ParC4_PT7_NotB); nand2 M9_UM9_2_ParC4_PT7_Xo2(M9_UM9_2_ParC4_PT7_NotA, M9_UM9_2_ParC4_line6, M9_UM9_2_ParC4_PT7_line2); nand2 M9_UM9_2_ParC4_PT7_Xo3(M9_UM9_2_ParC4_PT7_NotB, M9_UM9_2_ParC4_line5, M9_UM9_2_ParC4_PT7_line3); nand2 M9_UM9_2_ParC4_PT7_Xo4(M9_UM9_2_ParC4_PT7_line2, M9_UM9_2_ParC4_PT7_line3, M9_UM9_2_YaP0); inv M9_UM9_2_ParC5_PT0_Xo0(YAbus_14, M9_UM9_2_ParC5_PT0_NotA); inv M9_UM9_2_ParC5_PT0_Xo1(YAbus_15, M9_UM9_2_ParC5_PT0_NotB); nand2 M9_UM9_2_ParC5_PT0_Xo2(M9_UM9_2_ParC5_PT0_NotA, YAbus_15, M9_UM9_2_ParC5_PT0_line2); nand2 M9_UM9_2_ParC5_PT0_Xo3(M9_UM9_2_ParC5_PT0_NotB, YAbus_14, M9_UM9_2_ParC5_PT0_line3); nand2 M9_UM9_2_ParC5_PT0_Xo4(M9_UM9_2_ParC5_PT0_line2, M9_UM9_2_ParC5_PT0_line3, M9_UM9_2_ParC5_line0); inv M9_UM9_2_ParC5_PT1_Xo0(YAbus_16, M9_UM9_2_ParC5_PT1_NotA); inv M9_UM9_2_ParC5_PT1_Xo1(YAbus_17, M9_UM9_2_ParC5_PT1_NotB); nand2 M9_UM9_2_ParC5_PT1_Xo2(M9_UM9_2_ParC5_PT1_NotA, YAbus_17, M9_UM9_2_ParC5_PT1_line2); nand2 M9_UM9_2_ParC5_PT1_Xo3(M9_UM9_2_ParC5_PT1_NotB, YAbus_16, M9_UM9_2_ParC5_PT1_line3); nand2 M9_UM9_2_ParC5_PT1_Xo4(M9_UM9_2_ParC5_PT1_line2, M9_UM9_2_ParC5_PT1_line3, M9_UM9_2_ParC5_line1); inv M9_UM9_2_ParC5_PT2_Xo0(YAbus_10, M9_UM9_2_ParC5_PT2_NotA); inv M9_UM9_2_ParC5_PT2_Xo1(YAbus_11, M9_UM9_2_ParC5_PT2_NotB); nand2 M9_UM9_2_ParC5_PT2_Xo2(M9_UM9_2_ParC5_PT2_NotA, YAbus_11, M9_UM9_2_ParC5_PT2_line2); nand2 M9_UM9_2_ParC5_PT2_Xo3(M9_UM9_2_ParC5_PT2_NotB, YAbus_10, M9_UM9_2_ParC5_PT2_line3); nand2 M9_UM9_2_ParC5_PT2_Xo4(M9_UM9_2_ParC5_PT2_line2, M9_UM9_2_ParC5_PT2_line3, M9_UM9_2_ParC5_line2); inv M9_UM9_2_ParC5_PT3_Xo0(M9_PCYAbus_2, M9_UM9_2_ParC5_PT3_NotA); inv M9_UM9_2_ParC5_PT3_Xo1(YAbus_9, M9_UM9_2_ParC5_PT3_NotB); nand2 M9_UM9_2_ParC5_PT3_Xo2(M9_UM9_2_ParC5_PT3_NotA, YAbus_9, M9_UM9_2_ParC5_PT3_line2); nand2 M9_UM9_2_ParC5_PT3_Xo3(M9_UM9_2_ParC5_PT3_NotB, M9_PCYAbus_2, M9_UM9_2_ParC5_PT3_line3); nand2 M9_UM9_2_ParC5_PT3_Xo4(M9_UM9_2_ParC5_PT3_line2, M9_UM9_2_ParC5_PT3_line3, M9_UM9_2_ParC5_line3); inv M9_UM9_2_ParC5_PT4_Xo0(YAbus_12, M9_UM9_2_ParC5_PT4_NotA); inv M9_UM9_2_ParC5_PT4_Xo1(YAbus_13, M9_UM9_2_ParC5_PT4_NotB); nand2 M9_UM9_2_ParC5_PT4_Xo2(M9_UM9_2_ParC5_PT4_NotA, YAbus_13, M9_UM9_2_ParC5_PT4_line2); nand2 M9_UM9_2_ParC5_PT4_Xo3(M9_UM9_2_ParC5_PT4_NotB, YAbus_12, M9_UM9_2_ParC5_PT4_line3); nand2 M9_UM9_2_ParC5_PT4_Xo4(M9_UM9_2_ParC5_PT4_line2, M9_UM9_2_ParC5_PT4_line3, M9_UM9_2_ParC5_line4); inv M9_UM9_2_ParC5_PT5_Xo0(M9_UM9_2_ParC5_line0, M9_UM9_2_ParC5_PT5_NotA); inv M9_UM9_2_ParC5_PT5_Xo1(M9_UM9_2_ParC5_line1, M9_UM9_2_ParC5_PT5_NotB); nand2 M9_UM9_2_ParC5_PT5_Xo2(M9_UM9_2_ParC5_PT5_NotA, M9_UM9_2_ParC5_line1, M9_UM9_2_ParC5_PT5_line2); nand2 M9_UM9_2_ParC5_PT5_Xo3(M9_UM9_2_ParC5_PT5_NotB, M9_UM9_2_ParC5_line0, M9_UM9_2_ParC5_PT5_line3); nand2 M9_UM9_2_ParC5_PT5_Xo4(M9_UM9_2_ParC5_PT5_line2, M9_UM9_2_ParC5_PT5_line3, M9_UM9_2_ParC5_line5); inv M9_UM9_2_ParC5_PT6_Xo3_0(M9_UM9_2_ParC5_line2, M9_UM9_2_ParC5_PT6_NotA); inv M9_UM9_2_ParC5_PT6_Xo3_1(M9_UM9_2_ParC5_line3, M9_UM9_2_ParC5_PT6_NotB); inv M9_UM9_2_ParC5_PT6_Xo3_2(M9_UM9_2_ParC5_line4, M9_UM9_2_ParC5_PT6_NotC); and3 M9_UM9_2_ParC5_PT6_Xo3_3(M9_UM9_2_ParC5_PT6_NotA, M9_UM9_2_ParC5_PT6_NotB, M9_UM9_2_ParC5_line4, M9_UM9_2_ParC5_PT6_line3); and3 M9_UM9_2_ParC5_PT6_Xo3_4(M9_UM9_2_ParC5_PT6_NotA, M9_UM9_2_ParC5_line3, M9_UM9_2_ParC5_PT6_NotC, M9_UM9_2_ParC5_PT6_line4); and3 M9_UM9_2_ParC5_PT6_Xo3_5(M9_UM9_2_ParC5_line2, M9_UM9_2_ParC5_PT6_NotB, M9_UM9_2_ParC5_PT6_NotC, M9_UM9_2_ParC5_PT6_line5); and3 M9_UM9_2_ParC5_PT6_Xo3_6(M9_UM9_2_ParC5_line2, M9_UM9_2_ParC5_line3, M9_UM9_2_ParC5_line4, M9_UM9_2_ParC5_PT6_line6); nor2 M9_UM9_2_ParC5_PT6_Xo3_7(M9_UM9_2_ParC5_PT6_line3, M9_UM9_2_ParC5_PT6_line4, M9_UM9_2_ParC5_PT6_line7); nor2 M9_UM9_2_ParC5_PT6_Xo3_8(M9_UM9_2_ParC5_PT6_line5, M9_UM9_2_ParC5_PT6_line6, M9_UM9_2_ParC5_PT6_line8); nand2 M9_UM9_2_ParC5_PT6_Xo3_9(M9_UM9_2_ParC5_PT6_line7, M9_UM9_2_ParC5_PT6_line8, M9_UM9_2_ParC5_line6); inv M9_UM9_2_ParC5_PT7_Xo0(M9_UM9_2_ParC5_line5, M9_UM9_2_ParC5_PT7_NotA); inv M9_UM9_2_ParC5_PT7_Xo1(M9_UM9_2_ParC5_line6, M9_UM9_2_ParC5_PT7_NotB); nand2 M9_UM9_2_ParC5_PT7_Xo2(M9_UM9_2_ParC5_PT7_NotA, M9_UM9_2_ParC5_line6, M9_UM9_2_ParC5_PT7_line2); nand2 M9_UM9_2_ParC5_PT7_Xo3(M9_UM9_2_ParC5_PT7_NotB, M9_UM9_2_ParC5_line5, M9_UM9_2_ParC5_PT7_line3); nand2 M9_UM9_2_ParC5_PT7_Xo4(M9_UM9_2_ParC5_PT7_line2, M9_UM9_2_ParC5_PT7_line3, M9_UM9_2_YaP1); inv M9_UM9_2_ParC6_PT0_Xo0(YAbus_23, M9_UM9_2_ParC6_PT0_NotA); inv M9_UM9_2_ParC6_PT0_Xo1(YAbus_24, M9_UM9_2_ParC6_PT0_NotB); nand2 M9_UM9_2_ParC6_PT0_Xo2(M9_UM9_2_ParC6_PT0_NotA, YAbus_24, M9_UM9_2_ParC6_PT0_line2); nand2 M9_UM9_2_ParC6_PT0_Xo3(M9_UM9_2_ParC6_PT0_NotB, YAbus_23, M9_UM9_2_ParC6_PT0_line3); nand2 M9_UM9_2_ParC6_PT0_Xo4(M9_UM9_2_ParC6_PT0_line2, M9_UM9_2_ParC6_PT0_line3, M9_UM9_2_ParC6_line0); inv M9_UM9_2_ParC6_PT1_Xo0(YAbus_25, M9_UM9_2_ParC6_PT1_NotA); inv M9_UM9_2_ParC6_PT1_Xo1(YAbus_26, M9_UM9_2_ParC6_PT1_NotB); nand2 M9_UM9_2_ParC6_PT1_Xo2(M9_UM9_2_ParC6_PT1_NotA, YAbus_26, M9_UM9_2_ParC6_PT1_line2); nand2 M9_UM9_2_ParC6_PT1_Xo3(M9_UM9_2_ParC6_PT1_NotB, YAbus_25, M9_UM9_2_ParC6_PT1_line3); nand2 M9_UM9_2_ParC6_PT1_Xo4(M9_UM9_2_ParC6_PT1_line2, M9_UM9_2_ParC6_PT1_line3, M9_UM9_2_ParC6_line1); inv M9_UM9_2_ParC6_PT2_Xo0(YAbus_19, M9_UM9_2_ParC6_PT2_NotA); inv M9_UM9_2_ParC6_PT2_Xo1(YAbus_20, M9_UM9_2_ParC6_PT2_NotB); nand2 M9_UM9_2_ParC6_PT2_Xo2(M9_UM9_2_ParC6_PT2_NotA, YAbus_20, M9_UM9_2_ParC6_PT2_line2); nand2 M9_UM9_2_ParC6_PT2_Xo3(M9_UM9_2_ParC6_PT2_NotB, YAbus_19, M9_UM9_2_ParC6_PT2_line3); nand2 M9_UM9_2_ParC6_PT2_Xo4(M9_UM9_2_ParC6_PT2_line2, M9_UM9_2_ParC6_PT2_line3, M9_UM9_2_ParC6_line2); inv M9_UM9_2_ParC6_PT3_Xo0(M9_PCYAbus_3, M9_UM9_2_ParC6_PT3_NotA); inv M9_UM9_2_ParC6_PT3_Xo1(YAbus_18, M9_UM9_2_ParC6_PT3_NotB); nand2 M9_UM9_2_ParC6_PT3_Xo2(M9_UM9_2_ParC6_PT3_NotA, YAbus_18, M9_UM9_2_ParC6_PT3_line2); nand2 M9_UM9_2_ParC6_PT3_Xo3(M9_UM9_2_ParC6_PT3_NotB, M9_PCYAbus_3, M9_UM9_2_ParC6_PT3_line3); nand2 M9_UM9_2_ParC6_PT3_Xo4(M9_UM9_2_ParC6_PT3_line2, M9_UM9_2_ParC6_PT3_line3, M9_UM9_2_ParC6_line3); inv M9_UM9_2_ParC6_PT4_Xo0(YAbus_21, M9_UM9_2_ParC6_PT4_NotA); inv M9_UM9_2_ParC6_PT4_Xo1(YAbus_22, M9_UM9_2_ParC6_PT4_NotB); nand2 M9_UM9_2_ParC6_PT4_Xo2(M9_UM9_2_ParC6_PT4_NotA, YAbus_22, M9_UM9_2_ParC6_PT4_line2); nand2 M9_UM9_2_ParC6_PT4_Xo3(M9_UM9_2_ParC6_PT4_NotB, YAbus_21, M9_UM9_2_ParC6_PT4_line3); nand2 M9_UM9_2_ParC6_PT4_Xo4(M9_UM9_2_ParC6_PT4_line2, M9_UM9_2_ParC6_PT4_line3, M9_UM9_2_ParC6_line4); inv M9_UM9_2_ParC6_PT5_Xo0(M9_UM9_2_ParC6_line0, M9_UM9_2_ParC6_PT5_NotA); inv M9_UM9_2_ParC6_PT5_Xo1(M9_UM9_2_ParC6_line1, M9_UM9_2_ParC6_PT5_NotB); nand2 M9_UM9_2_ParC6_PT5_Xo2(M9_UM9_2_ParC6_PT5_NotA, M9_UM9_2_ParC6_line1, M9_UM9_2_ParC6_PT5_line2); nand2 M9_UM9_2_ParC6_PT5_Xo3(M9_UM9_2_ParC6_PT5_NotB, M9_UM9_2_ParC6_line0, M9_UM9_2_ParC6_PT5_line3); nand2 M9_UM9_2_ParC6_PT5_Xo4(M9_UM9_2_ParC6_PT5_line2, M9_UM9_2_ParC6_PT5_line3, M9_UM9_2_ParC6_line5); inv M9_UM9_2_ParC6_PT6_Xo3_0(M9_UM9_2_ParC6_line2, M9_UM9_2_ParC6_PT6_NotA); inv M9_UM9_2_ParC6_PT6_Xo3_1(M9_UM9_2_ParC6_line3, M9_UM9_2_ParC6_PT6_NotB); inv M9_UM9_2_ParC6_PT6_Xo3_2(M9_UM9_2_ParC6_line4, M9_UM9_2_ParC6_PT6_NotC); and3 M9_UM9_2_ParC6_PT6_Xo3_3(M9_UM9_2_ParC6_PT6_NotA, M9_UM9_2_ParC6_PT6_NotB, M9_UM9_2_ParC6_line4, M9_UM9_2_ParC6_PT6_line3); and3 M9_UM9_2_ParC6_PT6_Xo3_4(M9_UM9_2_ParC6_PT6_NotA, M9_UM9_2_ParC6_line3, M9_UM9_2_ParC6_PT6_NotC, M9_UM9_2_ParC6_PT6_line4); and3 M9_UM9_2_ParC6_PT6_Xo3_5(M9_UM9_2_ParC6_line2, M9_UM9_2_ParC6_PT6_NotB, M9_UM9_2_ParC6_PT6_NotC, M9_UM9_2_ParC6_PT6_line5); and3 M9_UM9_2_ParC6_PT6_Xo3_6(M9_UM9_2_ParC6_line2, M9_UM9_2_ParC6_line3, M9_UM9_2_ParC6_line4, M9_UM9_2_ParC6_PT6_line6); nor2 M9_UM9_2_ParC6_PT6_Xo3_7(M9_UM9_2_ParC6_PT6_line3, M9_UM9_2_ParC6_PT6_line4, M9_UM9_2_ParC6_PT6_line7); nor2 M9_UM9_2_ParC6_PT6_Xo3_8(M9_UM9_2_ParC6_PT6_line5, M9_UM9_2_ParC6_PT6_line6, M9_UM9_2_ParC6_PT6_line8); nand2 M9_UM9_2_ParC6_PT6_Xo3_9(M9_UM9_2_ParC6_PT6_line7, M9_UM9_2_ParC6_PT6_line8, M9_UM9_2_ParC6_line6); inv M9_UM9_2_ParC6_PT7_Xo0(M9_UM9_2_ParC6_line5, M9_UM9_2_ParC6_PT7_NotA); inv M9_UM9_2_ParC6_PT7_Xo1(M9_UM9_2_ParC6_line6, M9_UM9_2_ParC6_PT7_NotB); nand2 M9_UM9_2_ParC6_PT7_Xo2(M9_UM9_2_ParC6_PT7_NotA, M9_UM9_2_ParC6_line6, M9_UM9_2_ParC6_PT7_line2); nand2 M9_UM9_2_ParC6_PT7_Xo3(M9_UM9_2_ParC6_PT7_NotB, M9_UM9_2_ParC6_line5, M9_UM9_2_ParC6_PT7_line3); nand2 M9_UM9_2_ParC6_PT7_Xo4(M9_UM9_2_ParC6_PT7_line2, M9_UM9_2_ParC6_PT7_line3, M9_UM9_2_YaP2); inv M9_UM9_2_ParC7_PT0_Xo0(M9_PCYAbus_4, M9_UM9_2_ParC7_PT0_NotA); inv M9_UM9_2_ParC7_PT0_Xo1(M9_PCYAbus_5, M9_UM9_2_ParC7_PT0_NotB); nand2 M9_UM9_2_ParC7_PT0_Xo2(M9_UM9_2_ParC7_PT0_NotA, M9_PCYAbus_5, M9_UM9_2_ParC7_PT0_line2); nand2 M9_UM9_2_ParC7_PT0_Xo3(M9_UM9_2_ParC7_PT0_NotB, M9_PCYAbus_4, M9_UM9_2_ParC7_PT0_line3); nand2 M9_UM9_2_ParC7_PT0_Xo4(M9_UM9_2_ParC7_PT0_line2, M9_UM9_2_ParC7_PT0_line3, M9_UM9_2_ParC7_line0); inv M9_UM9_2_ParC7_PT1_Xo0(M9_PCYAbus_6, M9_UM9_2_ParC7_PT1_NotA); inv M9_UM9_2_ParC7_PT1_Xo1(YAbus_27, M9_UM9_2_ParC7_PT1_NotB); nand2 M9_UM9_2_ParC7_PT1_Xo2(M9_UM9_2_ParC7_PT1_NotA, YAbus_27, M9_UM9_2_ParC7_PT1_line2); nand2 M9_UM9_2_ParC7_PT1_Xo3(M9_UM9_2_ParC7_PT1_NotB, M9_PCYAbus_6, M9_UM9_2_ParC7_PT1_line3); nand2 M9_UM9_2_ParC7_PT1_Xo4(M9_UM9_2_ParC7_PT1_line2, M9_UM9_2_ParC7_PT1_line3, M9_UM9_2_ParC7_line1); inv M9_UM9_2_ParC7_PT2_Xo0(YAbus_28, M9_UM9_2_ParC7_PT2_NotA); inv M9_UM9_2_ParC7_PT2_Xo1(YAbus_29, M9_UM9_2_ParC7_PT2_NotB); nand2 M9_UM9_2_ParC7_PT2_Xo2(M9_UM9_2_ParC7_PT2_NotA, YAbus_29, M9_UM9_2_ParC7_PT2_line2); nand2 M9_UM9_2_ParC7_PT2_Xo3(M9_UM9_2_ParC7_PT2_NotB, YAbus_28, M9_UM9_2_ParC7_PT2_line3); nand2 M9_UM9_2_ParC7_PT2_Xo4(M9_UM9_2_ParC7_PT2_line2, M9_UM9_2_ParC7_PT2_line3, M9_UM9_2_ParC7_line2); inv M9_UM9_2_ParC7_PT3_Xo0(YAbus_30, M9_UM9_2_ParC7_PT3_NotA); inv M9_UM9_2_ParC7_PT3_Xo1(YAbus_31, M9_UM9_2_ParC7_PT3_NotB); nand2 M9_UM9_2_ParC7_PT3_Xo2(M9_UM9_2_ParC7_PT3_NotA, YAbus_31, M9_UM9_2_ParC7_PT3_line2); nand2 M9_UM9_2_ParC7_PT3_Xo3(M9_UM9_2_ParC7_PT3_NotB, YAbus_30, M9_UM9_2_ParC7_PT3_line3); nand2 M9_UM9_2_ParC7_PT3_Xo4(M9_UM9_2_ParC7_PT3_line2, M9_UM9_2_ParC7_PT3_line3, M9_UM9_2_ParC7_line3); inv M9_UM9_2_ParC7_PT4_Xo3_0(M9_UM9_2_ParC7_line1, M9_UM9_2_ParC7_PT4_NotA); inv M9_UM9_2_ParC7_PT4_Xo3_1(M9_UM9_2_ParC7_line2, M9_UM9_2_ParC7_PT4_NotB); inv M9_UM9_2_ParC7_PT4_Xo3_2(M9_UM9_2_ParC7_line3, M9_UM9_2_ParC7_PT4_NotC); and3 M9_UM9_2_ParC7_PT4_Xo3_3(M9_UM9_2_ParC7_PT4_NotA, M9_UM9_2_ParC7_PT4_NotB, M9_UM9_2_ParC7_line3, M9_UM9_2_ParC7_PT4_line3); and3 M9_UM9_2_ParC7_PT4_Xo3_4(M9_UM9_2_ParC7_PT4_NotA, M9_UM9_2_ParC7_line2, M9_UM9_2_ParC7_PT4_NotC, M9_UM9_2_ParC7_PT4_line4); and3 M9_UM9_2_ParC7_PT4_Xo3_5(M9_UM9_2_ParC7_line1, M9_UM9_2_ParC7_PT4_NotB, M9_UM9_2_ParC7_PT4_NotC, M9_UM9_2_ParC7_PT4_line5); and3 M9_UM9_2_ParC7_PT4_Xo3_6(M9_UM9_2_ParC7_line1, M9_UM9_2_ParC7_line2, M9_UM9_2_ParC7_line3, M9_UM9_2_ParC7_PT4_line6); nor2 M9_UM9_2_ParC7_PT4_Xo3_7(M9_UM9_2_ParC7_PT4_line3, M9_UM9_2_ParC7_PT4_line4, M9_UM9_2_ParC7_PT4_line7); nor2 M9_UM9_2_ParC7_PT4_Xo3_8(M9_UM9_2_ParC7_PT4_line5, M9_UM9_2_ParC7_PT4_line6, M9_UM9_2_ParC7_PT4_line8); nand2 M9_UM9_2_ParC7_PT4_Xo3_9(M9_UM9_2_ParC7_PT4_line7, M9_UM9_2_ParC7_PT4_line8, M9_UM9_2_ParC7_line4); inv M9_UM9_2_ParC7_PT5_Xo0(M9_UM9_2_ParC7_line0, M9_UM9_2_ParC7_PT5_NotA); inv M9_UM9_2_ParC7_PT5_Xo1(M9_UM9_2_ParC7_line4, M9_UM9_2_ParC7_PT5_NotB); nand2 M9_UM9_2_ParC7_PT5_Xo2(M9_UM9_2_ParC7_PT5_NotA, M9_UM9_2_ParC7_line4, M9_UM9_2_ParC7_PT5_line2); nand2 M9_UM9_2_ParC7_PT5_Xo3(M9_UM9_2_ParC7_PT5_NotB, M9_UM9_2_ParC7_line0, M9_UM9_2_ParC7_PT5_line3); nand2 M9_UM9_2_ParC7_PT5_Xo4(M9_UM9_2_ParC7_PT5_line2, M9_UM9_2_ParC7_PT5_line3, M9_UM9_2_YaP3); inv M9_UM9_2_ParC8_PT0_Xo0(YBbus_5, M9_UM9_2_ParC8_PT0_NotA); inv M9_UM9_2_ParC8_PT0_Xo1(YBbus_6, M9_UM9_2_ParC8_PT0_NotB); nand2 M9_UM9_2_ParC8_PT0_Xo2(M9_UM9_2_ParC8_PT0_NotA, YBbus_6, M9_UM9_2_ParC8_PT0_line2); nand2 M9_UM9_2_ParC8_PT0_Xo3(M9_UM9_2_ParC8_PT0_NotB, YBbus_5, M9_UM9_2_ParC8_PT0_line3); nand2 M9_UM9_2_ParC8_PT0_Xo4(M9_UM9_2_ParC8_PT0_line2, M9_UM9_2_ParC8_PT0_line3, M9_UM9_2_ParC8_line0); inv M9_UM9_2_ParC8_PT1_Xo0(YBbus_7, M9_UM9_2_ParC8_PT1_NotA); inv M9_UM9_2_ParC8_PT1_Xo1(YBbus_8, M9_UM9_2_ParC8_PT1_NotB); nand2 M9_UM9_2_ParC8_PT1_Xo2(M9_UM9_2_ParC8_PT1_NotA, YBbus_8, M9_UM9_2_ParC8_PT1_line2); nand2 M9_UM9_2_ParC8_PT1_Xo3(M9_UM9_2_ParC8_PT1_NotB, YBbus_7, M9_UM9_2_ParC8_PT1_line3); nand2 M9_UM9_2_ParC8_PT1_Xo4(M9_UM9_2_ParC8_PT1_line2, M9_UM9_2_ParC8_PT1_line3, M9_UM9_2_ParC8_line1); inv M9_UM9_2_ParC8_PT2_Xo0(YBbus_1, M9_UM9_2_ParC8_PT2_NotA); inv M9_UM9_2_ParC8_PT2_Xo1(YBbus_2, M9_UM9_2_ParC8_PT2_NotB); nand2 M9_UM9_2_ParC8_PT2_Xo2(M9_UM9_2_ParC8_PT2_NotA, YBbus_2, M9_UM9_2_ParC8_PT2_line2); nand2 M9_UM9_2_ParC8_PT2_Xo3(M9_UM9_2_ParC8_PT2_NotB, YBbus_1, M9_UM9_2_ParC8_PT2_line3); nand2 M9_UM9_2_ParC8_PT2_Xo4(M9_UM9_2_ParC8_PT2_line2, M9_UM9_2_ParC8_PT2_line3, M9_UM9_2_ParC8_line2); inv M9_UM9_2_ParC8_PT3_Xo0(M9_UM9_1_PCYBtempbus_0, M9_UM9_2_ParC8_PT3_NotA); inv M9_UM9_2_ParC8_PT3_Xo1(M9_UM9_1_PCYBtempbus_1, M9_UM9_2_ParC8_PT3_NotB); nand2 M9_UM9_2_ParC8_PT3_Xo2(M9_UM9_2_ParC8_PT3_NotA, M9_UM9_1_PCYBtempbus_1, M9_UM9_2_ParC8_PT3_line2); nand2 M9_UM9_2_ParC8_PT3_Xo3(M9_UM9_2_ParC8_PT3_NotB, M9_UM9_1_PCYBtempbus_0, M9_UM9_2_ParC8_PT3_line3); nand2 M9_UM9_2_ParC8_PT3_Xo4(M9_UM9_2_ParC8_PT3_line2, M9_UM9_2_ParC8_PT3_line3, M9_UM9_2_ParC8_line3); inv M9_UM9_2_ParC8_PT4_Xo0(YBbus_3, M9_UM9_2_ParC8_PT4_NotA); inv M9_UM9_2_ParC8_PT4_Xo1(YBbus_4, M9_UM9_2_ParC8_PT4_NotB); nand2 M9_UM9_2_ParC8_PT4_Xo2(M9_UM9_2_ParC8_PT4_NotA, YBbus_4, M9_UM9_2_ParC8_PT4_line2); nand2 M9_UM9_2_ParC8_PT4_Xo3(M9_UM9_2_ParC8_PT4_NotB, YBbus_3, M9_UM9_2_ParC8_PT4_line3); nand2 M9_UM9_2_ParC8_PT4_Xo4(M9_UM9_2_ParC8_PT4_line2, M9_UM9_2_ParC8_PT4_line3, M9_UM9_2_ParC8_line4); inv M9_UM9_2_ParC8_PT5_Xo0(M9_UM9_2_ParC8_line0, M9_UM9_2_ParC8_PT5_NotA); inv M9_UM9_2_ParC8_PT5_Xo1(M9_UM9_2_ParC8_line1, M9_UM9_2_ParC8_PT5_NotB); nand2 M9_UM9_2_ParC8_PT5_Xo2(M9_UM9_2_ParC8_PT5_NotA, M9_UM9_2_ParC8_line1, M9_UM9_2_ParC8_PT5_line2); nand2 M9_UM9_2_ParC8_PT5_Xo3(M9_UM9_2_ParC8_PT5_NotB, M9_UM9_2_ParC8_line0, M9_UM9_2_ParC8_PT5_line3); nand2 M9_UM9_2_ParC8_PT5_Xo4(M9_UM9_2_ParC8_PT5_line2, M9_UM9_2_ParC8_PT5_line3, M9_UM9_2_ParC8_line5); inv M9_UM9_2_ParC8_PT6_Xo3_0(M9_UM9_2_ParC8_line2, M9_UM9_2_ParC8_PT6_NotA); inv M9_UM9_2_ParC8_PT6_Xo3_1(M9_UM9_2_ParC8_line3, M9_UM9_2_ParC8_PT6_NotB); inv M9_UM9_2_ParC8_PT6_Xo3_2(M9_UM9_2_ParC8_line4, M9_UM9_2_ParC8_PT6_NotC); and3 M9_UM9_2_ParC8_PT6_Xo3_3(M9_UM9_2_ParC8_PT6_NotA, M9_UM9_2_ParC8_PT6_NotB, M9_UM9_2_ParC8_line4, M9_UM9_2_ParC8_PT6_line3); and3 M9_UM9_2_ParC8_PT6_Xo3_4(M9_UM9_2_ParC8_PT6_NotA, M9_UM9_2_ParC8_line3, M9_UM9_2_ParC8_PT6_NotC, M9_UM9_2_ParC8_PT6_line4); and3 M9_UM9_2_ParC8_PT6_Xo3_5(M9_UM9_2_ParC8_line2, M9_UM9_2_ParC8_PT6_NotB, M9_UM9_2_ParC8_PT6_NotC, M9_UM9_2_ParC8_PT6_line5); and3 M9_UM9_2_ParC8_PT6_Xo3_6(M9_UM9_2_ParC8_line2, M9_UM9_2_ParC8_line3, M9_UM9_2_ParC8_line4, M9_UM9_2_ParC8_PT6_line6); nor2 M9_UM9_2_ParC8_PT6_Xo3_7(M9_UM9_2_ParC8_PT6_line3, M9_UM9_2_ParC8_PT6_line4, M9_UM9_2_ParC8_PT6_line7); nor2 M9_UM9_2_ParC8_PT6_Xo3_8(M9_UM9_2_ParC8_PT6_line5, M9_UM9_2_ParC8_PT6_line6, M9_UM9_2_ParC8_PT6_line8); nand2 M9_UM9_2_ParC8_PT6_Xo3_9(M9_UM9_2_ParC8_PT6_line7, M9_UM9_2_ParC8_PT6_line8, M9_UM9_2_ParC8_line6); inv M9_UM9_2_ParC8_PT7_Xo0(M9_UM9_2_ParC8_line5, M9_UM9_2_ParC8_PT7_NotA); inv M9_UM9_2_ParC8_PT7_Xo1(M9_UM9_2_ParC8_line6, M9_UM9_2_ParC8_PT7_NotB); nand2 M9_UM9_2_ParC8_PT7_Xo2(M9_UM9_2_ParC8_PT7_NotA, M9_UM9_2_ParC8_line6, M9_UM9_2_ParC8_PT7_line2); nand2 M9_UM9_2_ParC8_PT7_Xo3(M9_UM9_2_ParC8_PT7_NotB, M9_UM9_2_ParC8_line5, M9_UM9_2_ParC8_PT7_line3); nand2 M9_UM9_2_ParC8_PT7_Xo4(M9_UM9_2_ParC8_PT7_line2, M9_UM9_2_ParC8_PT7_line3, M9_UM9_2_YbP0); inv M9_UM9_2_ParC9_PT0_Xo0(YBbus_14, M9_UM9_2_ParC9_PT0_NotA); inv M9_UM9_2_ParC9_PT0_Xo1(YBbus_15, M9_UM9_2_ParC9_PT0_NotB); nand2 M9_UM9_2_ParC9_PT0_Xo2(M9_UM9_2_ParC9_PT0_NotA, YBbus_15, M9_UM9_2_ParC9_PT0_line2); nand2 M9_UM9_2_ParC9_PT0_Xo3(M9_UM9_2_ParC9_PT0_NotB, YBbus_14, M9_UM9_2_ParC9_PT0_line3); nand2 M9_UM9_2_ParC9_PT0_Xo4(M9_UM9_2_ParC9_PT0_line2, M9_UM9_2_ParC9_PT0_line3, M9_UM9_2_ParC9_line0); inv M9_UM9_2_ParC9_PT1_Xo0(YBbus_16, M9_UM9_2_ParC9_PT1_NotA); inv M9_UM9_2_ParC9_PT1_Xo1(YBbus_17, M9_UM9_2_ParC9_PT1_NotB); nand2 M9_UM9_2_ParC9_PT1_Xo2(M9_UM9_2_ParC9_PT1_NotA, YBbus_17, M9_UM9_2_ParC9_PT1_line2); nand2 M9_UM9_2_ParC9_PT1_Xo3(M9_UM9_2_ParC9_PT1_NotB, YBbus_16, M9_UM9_2_ParC9_PT1_line3); nand2 M9_UM9_2_ParC9_PT1_Xo4(M9_UM9_2_ParC9_PT1_line2, M9_UM9_2_ParC9_PT1_line3, M9_UM9_2_ParC9_line1); inv M9_UM9_2_ParC9_PT2_Xo0(YBbus_10, M9_UM9_2_ParC9_PT2_NotA); inv M9_UM9_2_ParC9_PT2_Xo1(YBbus_11, M9_UM9_2_ParC9_PT2_NotB); nand2 M9_UM9_2_ParC9_PT2_Xo2(M9_UM9_2_ParC9_PT2_NotA, YBbus_11, M9_UM9_2_ParC9_PT2_line2); nand2 M9_UM9_2_ParC9_PT2_Xo3(M9_UM9_2_ParC9_PT2_NotB, YBbus_10, M9_UM9_2_ParC9_PT2_line3); nand2 M9_UM9_2_ParC9_PT2_Xo4(M9_UM9_2_ParC9_PT2_line2, M9_UM9_2_ParC9_PT2_line3, M9_UM9_2_ParC9_line2); inv M9_UM9_2_ParC9_PT3_Xo0(M9_UM9_1_PCYBtempbus_2, M9_UM9_2_ParC9_PT3_NotA); inv M9_UM9_2_ParC9_PT3_Xo1(YBbus_9, M9_UM9_2_ParC9_PT3_NotB); nand2 M9_UM9_2_ParC9_PT3_Xo2(M9_UM9_2_ParC9_PT3_NotA, YBbus_9, M9_UM9_2_ParC9_PT3_line2); nand2 M9_UM9_2_ParC9_PT3_Xo3(M9_UM9_2_ParC9_PT3_NotB, M9_UM9_1_PCYBtempbus_2, M9_UM9_2_ParC9_PT3_line3); nand2 M9_UM9_2_ParC9_PT3_Xo4(M9_UM9_2_ParC9_PT3_line2, M9_UM9_2_ParC9_PT3_line3, M9_UM9_2_ParC9_line3); inv M9_UM9_2_ParC9_PT4_Xo0(YBbus_12, M9_UM9_2_ParC9_PT4_NotA); inv M9_UM9_2_ParC9_PT4_Xo1(YBbus_13, M9_UM9_2_ParC9_PT4_NotB); nand2 M9_UM9_2_ParC9_PT4_Xo2(M9_UM9_2_ParC9_PT4_NotA, YBbus_13, M9_UM9_2_ParC9_PT4_line2); nand2 M9_UM9_2_ParC9_PT4_Xo3(M9_UM9_2_ParC9_PT4_NotB, YBbus_12, M9_UM9_2_ParC9_PT4_line3); nand2 M9_UM9_2_ParC9_PT4_Xo4(M9_UM9_2_ParC9_PT4_line2, M9_UM9_2_ParC9_PT4_line3, M9_UM9_2_ParC9_line4); inv M9_UM9_2_ParC9_PT5_Xo0(M9_UM9_2_ParC9_line0, M9_UM9_2_ParC9_PT5_NotA); inv M9_UM9_2_ParC9_PT5_Xo1(M9_UM9_2_ParC9_line1, M9_UM9_2_ParC9_PT5_NotB); nand2 M9_UM9_2_ParC9_PT5_Xo2(M9_UM9_2_ParC9_PT5_NotA, M9_UM9_2_ParC9_line1, M9_UM9_2_ParC9_PT5_line2); nand2 M9_UM9_2_ParC9_PT5_Xo3(M9_UM9_2_ParC9_PT5_NotB, M9_UM9_2_ParC9_line0, M9_UM9_2_ParC9_PT5_line3); nand2 M9_UM9_2_ParC9_PT5_Xo4(M9_UM9_2_ParC9_PT5_line2, M9_UM9_2_ParC9_PT5_line3, M9_UM9_2_ParC9_line5); inv M9_UM9_2_ParC9_PT6_Xo3_0(M9_UM9_2_ParC9_line2, M9_UM9_2_ParC9_PT6_NotA); inv M9_UM9_2_ParC9_PT6_Xo3_1(M9_UM9_2_ParC9_line3, M9_UM9_2_ParC9_PT6_NotB); inv M9_UM9_2_ParC9_PT6_Xo3_2(M9_UM9_2_ParC9_line4, M9_UM9_2_ParC9_PT6_NotC); and3 M9_UM9_2_ParC9_PT6_Xo3_3(M9_UM9_2_ParC9_PT6_NotA, M9_UM9_2_ParC9_PT6_NotB, M9_UM9_2_ParC9_line4, M9_UM9_2_ParC9_PT6_line3); and3 M9_UM9_2_ParC9_PT6_Xo3_4(M9_UM9_2_ParC9_PT6_NotA, M9_UM9_2_ParC9_line3, M9_UM9_2_ParC9_PT6_NotC, M9_UM9_2_ParC9_PT6_line4); and3 M9_UM9_2_ParC9_PT6_Xo3_5(M9_UM9_2_ParC9_line2, M9_UM9_2_ParC9_PT6_NotB, M9_UM9_2_ParC9_PT6_NotC, M9_UM9_2_ParC9_PT6_line5); and3 M9_UM9_2_ParC9_PT6_Xo3_6(M9_UM9_2_ParC9_line2, M9_UM9_2_ParC9_line3, M9_UM9_2_ParC9_line4, M9_UM9_2_ParC9_PT6_line6); nor2 M9_UM9_2_ParC9_PT6_Xo3_7(M9_UM9_2_ParC9_PT6_line3, M9_UM9_2_ParC9_PT6_line4, M9_UM9_2_ParC9_PT6_line7); nor2 M9_UM9_2_ParC9_PT6_Xo3_8(M9_UM9_2_ParC9_PT6_line5, M9_UM9_2_ParC9_PT6_line6, M9_UM9_2_ParC9_PT6_line8); nand2 M9_UM9_2_ParC9_PT6_Xo3_9(M9_UM9_2_ParC9_PT6_line7, M9_UM9_2_ParC9_PT6_line8, M9_UM9_2_ParC9_line6); inv M9_UM9_2_ParC9_PT7_Xo0(M9_UM9_2_ParC9_line5, M9_UM9_2_ParC9_PT7_NotA); inv M9_UM9_2_ParC9_PT7_Xo1(M9_UM9_2_ParC9_line6, M9_UM9_2_ParC9_PT7_NotB); nand2 M9_UM9_2_ParC9_PT7_Xo2(M9_UM9_2_ParC9_PT7_NotA, M9_UM9_2_ParC9_line6, M9_UM9_2_ParC9_PT7_line2); nand2 M9_UM9_2_ParC9_PT7_Xo3(M9_UM9_2_ParC9_PT7_NotB, M9_UM9_2_ParC9_line5, M9_UM9_2_ParC9_PT7_line3); nand2 M9_UM9_2_ParC9_PT7_Xo4(M9_UM9_2_ParC9_PT7_line2, M9_UM9_2_ParC9_PT7_line3, M9_UM9_2_YbP1); inv M9_UM9_2_ParC10_PT0_Xo0(YBbus_23, M9_UM9_2_ParC10_PT0_NotA); inv M9_UM9_2_ParC10_PT0_Xo1(YBbus_24, M9_UM9_2_ParC10_PT0_NotB); nand2 M9_UM9_2_ParC10_PT0_Xo2(M9_UM9_2_ParC10_PT0_NotA, YBbus_24, M9_UM9_2_ParC10_PT0_line2); nand2 M9_UM9_2_ParC10_PT0_Xo3(M9_UM9_2_ParC10_PT0_NotB, YBbus_23, M9_UM9_2_ParC10_PT0_line3); nand2 M9_UM9_2_ParC10_PT0_Xo4(M9_UM9_2_ParC10_PT0_line2, M9_UM9_2_ParC10_PT0_line3, M9_UM9_2_ParC10_line0); inv M9_UM9_2_ParC10_PT1_Xo0(YBbus_25, M9_UM9_2_ParC10_PT1_NotA); inv M9_UM9_2_ParC10_PT1_Xo1(YBbus_26, M9_UM9_2_ParC10_PT1_NotB); nand2 M9_UM9_2_ParC10_PT1_Xo2(M9_UM9_2_ParC10_PT1_NotA, YBbus_26, M9_UM9_2_ParC10_PT1_line2); nand2 M9_UM9_2_ParC10_PT1_Xo3(M9_UM9_2_ParC10_PT1_NotB, YBbus_25, M9_UM9_2_ParC10_PT1_line3); nand2 M9_UM9_2_ParC10_PT1_Xo4(M9_UM9_2_ParC10_PT1_line2, M9_UM9_2_ParC10_PT1_line3, M9_UM9_2_ParC10_line1); inv M9_UM9_2_ParC10_PT2_Xo0(YBbus_19, M9_UM9_2_ParC10_PT2_NotA); inv M9_UM9_2_ParC10_PT2_Xo1(YBbus_20, M9_UM9_2_ParC10_PT2_NotB); nand2 M9_UM9_2_ParC10_PT2_Xo2(M9_UM9_2_ParC10_PT2_NotA, YBbus_20, M9_UM9_2_ParC10_PT2_line2); nand2 M9_UM9_2_ParC10_PT2_Xo3(M9_UM9_2_ParC10_PT2_NotB, YBbus_19, M9_UM9_2_ParC10_PT2_line3); nand2 M9_UM9_2_ParC10_PT2_Xo4(M9_UM9_2_ParC10_PT2_line2, M9_UM9_2_ParC10_PT2_line3, M9_UM9_2_ParC10_line2); inv M9_UM9_2_ParC10_PT3_Xo0(M9_UM9_1_PCYBtempbus_3, M9_UM9_2_ParC10_PT3_NotA); inv M9_UM9_2_ParC10_PT3_Xo1(YBbus_18, M9_UM9_2_ParC10_PT3_NotB); nand2 M9_UM9_2_ParC10_PT3_Xo2(M9_UM9_2_ParC10_PT3_NotA, YBbus_18, M9_UM9_2_ParC10_PT3_line2); nand2 M9_UM9_2_ParC10_PT3_Xo3(M9_UM9_2_ParC10_PT3_NotB, M9_UM9_1_PCYBtempbus_3, M9_UM9_2_ParC10_PT3_line3); nand2 M9_UM9_2_ParC10_PT3_Xo4(M9_UM9_2_ParC10_PT3_line2, M9_UM9_2_ParC10_PT3_line3, M9_UM9_2_ParC10_line3); inv M9_UM9_2_ParC10_PT4_Xo0(YBbus_21, M9_UM9_2_ParC10_PT4_NotA); inv M9_UM9_2_ParC10_PT4_Xo1(YBbus_22, M9_UM9_2_ParC10_PT4_NotB); nand2 M9_UM9_2_ParC10_PT4_Xo2(M9_UM9_2_ParC10_PT4_NotA, YBbus_22, M9_UM9_2_ParC10_PT4_line2); nand2 M9_UM9_2_ParC10_PT4_Xo3(M9_UM9_2_ParC10_PT4_NotB, YBbus_21, M9_UM9_2_ParC10_PT4_line3); nand2 M9_UM9_2_ParC10_PT4_Xo4(M9_UM9_2_ParC10_PT4_line2, M9_UM9_2_ParC10_PT4_line3, M9_UM9_2_ParC10_line4); inv M9_UM9_2_ParC10_PT5_Xo0(M9_UM9_2_ParC10_line0, M9_UM9_2_ParC10_PT5_NotA); inv M9_UM9_2_ParC10_PT5_Xo1(M9_UM9_2_ParC10_line1, M9_UM9_2_ParC10_PT5_NotB); nand2 M9_UM9_2_ParC10_PT5_Xo2(M9_UM9_2_ParC10_PT5_NotA, M9_UM9_2_ParC10_line1, M9_UM9_2_ParC10_PT5_line2); nand2 M9_UM9_2_ParC10_PT5_Xo3(M9_UM9_2_ParC10_PT5_NotB, M9_UM9_2_ParC10_line0, M9_UM9_2_ParC10_PT5_line3); nand2 M9_UM9_2_ParC10_PT5_Xo4(M9_UM9_2_ParC10_PT5_line2, M9_UM9_2_ParC10_PT5_line3, M9_UM9_2_ParC10_line5); inv M9_UM9_2_ParC10_PT6_Xo3_0(M9_UM9_2_ParC10_line2, M9_UM9_2_ParC10_PT6_NotA); inv M9_UM9_2_ParC10_PT6_Xo3_1(M9_UM9_2_ParC10_line3, M9_UM9_2_ParC10_PT6_NotB); inv M9_UM9_2_ParC10_PT6_Xo3_2(M9_UM9_2_ParC10_line4, M9_UM9_2_ParC10_PT6_NotC); and3 M9_UM9_2_ParC10_PT6_Xo3_3(M9_UM9_2_ParC10_PT6_NotA, M9_UM9_2_ParC10_PT6_NotB, M9_UM9_2_ParC10_line4, M9_UM9_2_ParC10_PT6_line3); and3 M9_UM9_2_ParC10_PT6_Xo3_4(M9_UM9_2_ParC10_PT6_NotA, M9_UM9_2_ParC10_line3, M9_UM9_2_ParC10_PT6_NotC, M9_UM9_2_ParC10_PT6_line4); and3 M9_UM9_2_ParC10_PT6_Xo3_5(M9_UM9_2_ParC10_line2, M9_UM9_2_ParC10_PT6_NotB, M9_UM9_2_ParC10_PT6_NotC, M9_UM9_2_ParC10_PT6_line5); and3 M9_UM9_2_ParC10_PT6_Xo3_6(M9_UM9_2_ParC10_line2, M9_UM9_2_ParC10_line3, M9_UM9_2_ParC10_line4, M9_UM9_2_ParC10_PT6_line6); nor2 M9_UM9_2_ParC10_PT6_Xo3_7(M9_UM9_2_ParC10_PT6_line3, M9_UM9_2_ParC10_PT6_line4, M9_UM9_2_ParC10_PT6_line7); nor2 M9_UM9_2_ParC10_PT6_Xo3_8(M9_UM9_2_ParC10_PT6_line5, M9_UM9_2_ParC10_PT6_line6, M9_UM9_2_ParC10_PT6_line8); nand2 M9_UM9_2_ParC10_PT6_Xo3_9(M9_UM9_2_ParC10_PT6_line7, M9_UM9_2_ParC10_PT6_line8, M9_UM9_2_ParC10_line6); inv M9_UM9_2_ParC10_PT7_Xo0(M9_UM9_2_ParC10_line5, M9_UM9_2_ParC10_PT7_NotA); inv M9_UM9_2_ParC10_PT7_Xo1(M9_UM9_2_ParC10_line6, M9_UM9_2_ParC10_PT7_NotB); nand2 M9_UM9_2_ParC10_PT7_Xo2(M9_UM9_2_ParC10_PT7_NotA, M9_UM9_2_ParC10_line6, M9_UM9_2_ParC10_PT7_line2); nand2 M9_UM9_2_ParC10_PT7_Xo3(M9_UM9_2_ParC10_PT7_NotB, M9_UM9_2_ParC10_line5, M9_UM9_2_ParC10_PT7_line3); nand2 M9_UM9_2_ParC10_PT7_Xo4(M9_UM9_2_ParC10_PT7_line2, M9_UM9_2_ParC10_PT7_line3, M9_UM9_2_YbP2); inv M9_UM9_2_ParC11_PT0_Xo0(M9_PCYBbus_4, M9_UM9_2_ParC11_PT0_NotA); inv M9_UM9_2_ParC11_PT0_Xo1(M9_PCYBbus_5, M9_UM9_2_ParC11_PT0_NotB); nand2 M9_UM9_2_ParC11_PT0_Xo2(M9_UM9_2_ParC11_PT0_NotA, M9_PCYBbus_5, M9_UM9_2_ParC11_PT0_line2); nand2 M9_UM9_2_ParC11_PT0_Xo3(M9_UM9_2_ParC11_PT0_NotB, M9_PCYBbus_4, M9_UM9_2_ParC11_PT0_line3); nand2 M9_UM9_2_ParC11_PT0_Xo4(M9_UM9_2_ParC11_PT0_line2, M9_UM9_2_ParC11_PT0_line3, M9_UM9_2_ParC11_line0); inv M9_UM9_2_ParC11_PT1_Xo0(M9_PCYBbus_6, M9_UM9_2_ParC11_PT1_NotA); inv M9_UM9_2_ParC11_PT1_Xo1(YBbus_27, M9_UM9_2_ParC11_PT1_NotB); nand2 M9_UM9_2_ParC11_PT1_Xo2(M9_UM9_2_ParC11_PT1_NotA, YBbus_27, M9_UM9_2_ParC11_PT1_line2); nand2 M9_UM9_2_ParC11_PT1_Xo3(M9_UM9_2_ParC11_PT1_NotB, M9_PCYBbus_6, M9_UM9_2_ParC11_PT1_line3); nand2 M9_UM9_2_ParC11_PT1_Xo4(M9_UM9_2_ParC11_PT1_line2, M9_UM9_2_ParC11_PT1_line3, M9_UM9_2_ParC11_line1); inv M9_UM9_2_ParC11_PT2_Xo0(YBbus_28, M9_UM9_2_ParC11_PT2_NotA); inv M9_UM9_2_ParC11_PT2_Xo1(YBbus_29, M9_UM9_2_ParC11_PT2_NotB); nand2 M9_UM9_2_ParC11_PT2_Xo2(M9_UM9_2_ParC11_PT2_NotA, YBbus_29, M9_UM9_2_ParC11_PT2_line2); nand2 M9_UM9_2_ParC11_PT2_Xo3(M9_UM9_2_ParC11_PT2_NotB, YBbus_28, M9_UM9_2_ParC11_PT2_line3); nand2 M9_UM9_2_ParC11_PT2_Xo4(M9_UM9_2_ParC11_PT2_line2, M9_UM9_2_ParC11_PT2_line3, M9_UM9_2_ParC11_line2); inv M9_UM9_2_ParC11_PT3_Xo0(YBbus_30, M9_UM9_2_ParC11_PT3_NotA); inv M9_UM9_2_ParC11_PT3_Xo1(YBbus_31, M9_UM9_2_ParC11_PT3_NotB); nand2 M9_UM9_2_ParC11_PT3_Xo2(M9_UM9_2_ParC11_PT3_NotA, YBbus_31, M9_UM9_2_ParC11_PT3_line2); nand2 M9_UM9_2_ParC11_PT3_Xo3(M9_UM9_2_ParC11_PT3_NotB, YBbus_30, M9_UM9_2_ParC11_PT3_line3); nand2 M9_UM9_2_ParC11_PT3_Xo4(M9_UM9_2_ParC11_PT3_line2, M9_UM9_2_ParC11_PT3_line3, M9_UM9_2_ParC11_line3); inv M9_UM9_2_ParC11_PT4_Xo3_0(M9_UM9_2_ParC11_line1, M9_UM9_2_ParC11_PT4_NotA); inv M9_UM9_2_ParC11_PT4_Xo3_1(M9_UM9_2_ParC11_line2, M9_UM9_2_ParC11_PT4_NotB); inv M9_UM9_2_ParC11_PT4_Xo3_2(M9_UM9_2_ParC11_line3, M9_UM9_2_ParC11_PT4_NotC); and3 M9_UM9_2_ParC11_PT4_Xo3_3(M9_UM9_2_ParC11_PT4_NotA, M9_UM9_2_ParC11_PT4_NotB, M9_UM9_2_ParC11_line3, M9_UM9_2_ParC11_PT4_line3); and3 M9_UM9_2_ParC11_PT4_Xo3_4(M9_UM9_2_ParC11_PT4_NotA, M9_UM9_2_ParC11_line2, M9_UM9_2_ParC11_PT4_NotC, M9_UM9_2_ParC11_PT4_line4); and3 M9_UM9_2_ParC11_PT4_Xo3_5(M9_UM9_2_ParC11_line1, M9_UM9_2_ParC11_PT4_NotB, M9_UM9_2_ParC11_PT4_NotC, M9_UM9_2_ParC11_PT4_line5); and3 M9_UM9_2_ParC11_PT4_Xo3_6(M9_UM9_2_ParC11_line1, M9_UM9_2_ParC11_line2, M9_UM9_2_ParC11_line3, M9_UM9_2_ParC11_PT4_line6); nor2 M9_UM9_2_ParC11_PT4_Xo3_7(M9_UM9_2_ParC11_PT4_line3, M9_UM9_2_ParC11_PT4_line4, M9_UM9_2_ParC11_PT4_line7); nor2 M9_UM9_2_ParC11_PT4_Xo3_8(M9_UM9_2_ParC11_PT4_line5, M9_UM9_2_ParC11_PT4_line6, M9_UM9_2_ParC11_PT4_line8); nand2 M9_UM9_2_ParC11_PT4_Xo3_9(M9_UM9_2_ParC11_PT4_line7, M9_UM9_2_ParC11_PT4_line8, M9_UM9_2_ParC11_line4); inv M9_UM9_2_ParC11_PT5_Xo0(M9_UM9_2_ParC11_line0, M9_UM9_2_ParC11_PT5_NotA); inv M9_UM9_2_ParC11_PT5_Xo1(M9_UM9_2_ParC11_line4, M9_UM9_2_ParC11_PT5_NotB); nand2 M9_UM9_2_ParC11_PT5_Xo2(M9_UM9_2_ParC11_PT5_NotA, M9_UM9_2_ParC11_line4, M9_UM9_2_ParC11_PT5_line2); nand2 M9_UM9_2_ParC11_PT5_Xo3(M9_UM9_2_ParC11_PT5_NotB, M9_UM9_2_ParC11_line0, M9_UM9_2_ParC11_PT5_line3); nand2 M9_UM9_2_ParC11_PT5_Xo4(M9_UM9_2_ParC11_PT5_line2, M9_UM9_2_ParC11_PT5_line3, M9_UM9_2_YbP3); and4 M9_UM9_2_ParC12(M9_UM9_2_XaP0, M9_UM9_2_XaP1, M9_UM9_2_XaP2, M9_UM9_2_XaP3, M9_UM9_2_XaP); and4 M9_UM9_2_ParC13(M9_UM9_2_YaP0, M9_UM9_2_YaP1, M9_UM9_2_YaP2, M9_UM9_2_YaP3, M9_UM9_2_YaP); and4 M9_UM9_2_ParC14(M9_UM9_2_YbP0, M9_UM9_2_YbP1, M9_UM9_2_YbP2, M9_UM9_2_YbP3, M9_UM9_2_YbP); and3 M9_UM9_2_ParC15(M9_UM9_2_XaP, M9_UM9_2_YaP, M9_UM9_2_YbP, M9_UM9_2_XYabP); and3 M9_UM9_2_ParC16(M9_StrobeK0_1, M9_StrobeK2_3, M9_UM9_2_XYabP, M9_UM9_2_NotPar0); inv M9_UM9_2_ParC17(M9_UM9_2_NotPar0, out418); inv M9_UM9_2_ParC18(M9_UM9_2_XaP, out412); inv M9_UM9_2_ParC19(M9_UM9_2_YaP, out414); inv M9_UM9_2_ParC20(M9_UM9_2_YbP, out416); buffer M10_Buf34_0_Buf8_0_Buf4_0(in3701, out542); buffer M10_Buf34_0_Buf8_0_Buf4_1(in3705, out558); buffer M10_Buf34_0_Buf8_0_Buf4_2(in3711, out556); buffer M10_Buf34_0_Buf8_0_Buf4_3(in3717, out554); buffer M10_Buf34_0_Buf8_1_Buf4_0(in3723, out552); buffer M10_Buf34_0_Buf8_1_Buf4_1(in3729, out550); buffer M10_Buf34_0_Buf8_1_Buf4_2(in3737, out548); buffer M10_Buf34_0_Buf8_1_Buf4_3(in3743, out546); buffer M10_Buf34_1_Buf8_0_Buf4_0(in3749, out544); buffer M10_Buf34_1_Buf8_0_Buf4_1(in4394, out522); buffer M10_Buf34_1_Buf8_0_Buf4_2(in4400, out538); buffer M10_Buf34_1_Buf8_0_Buf4_3(in4405, out536); buffer M10_Buf34_1_Buf8_1_Buf4_0(in4410, out534); buffer M10_Buf34_1_Buf8_1_Buf4_1(in4415, out532); buffer M10_Buf34_1_Buf8_1_Buf4_2(in4420, out530); buffer M10_Buf34_1_Buf8_1_Buf4_3(in4427, out528); buffer M10_Buf34_2_Buf8_0_Buf4_0(in4432, out526); buffer M10_Buf34_2_Buf8_0_Buf4_1(in4437, out524); buffer M10_Buf34_2_Buf8_0_Buf4_2(in2211, out478); buffer M10_Buf34_2_Buf8_0_Buf4_3(in2218, out494); buffer M10_Buf34_2_Buf8_1_Buf4_0(in2224, out492); buffer M10_Buf34_2_Buf8_1_Buf4_1(in2230, out490); buffer M10_Buf34_2_Buf8_1_Buf4_2(in2236, out488); buffer M10_Buf34_2_Buf8_1_Buf4_3(in2239, out486); buffer M10_Buf34_3_Buf8_0_Buf4_0(in2247, out484); buffer M10_Buf34_3_Buf8_0_Buf4_1(in2253, out482); buffer M10_Buf34_3_Buf8_0_Buf4_2(in2256, out480); buffer M10_Buf34_3_Buf8_0_Buf4_3(in1462, out436); buffer M10_Buf34_3_Buf8_1_Buf4_0(in1469, out448); buffer M10_Buf34_3_Buf8_1_Buf4_1(in106, out446); buffer M10_Buf34_3_Buf8_1_Buf4_2(in1480, out444); buffer M10_Buf34_3_Buf8_1_Buf4_3(in1486, out442); buffer M10_Buf34_4(in1492, out440); buffer M10_Buf34_5(in1496, out438); buffer M11_Buf4_0(in3698, out560); buffer M11_Buf4_1(in4393, out540); buffer M11_Buf4_2(in2208, out496); buffer M11_Buf4_3(in1459, out450); buffer M12_UM12_0(in1, out2); and2 M12_UM12_1(in1, in163, out278); inv M12_UM12_2(in15, out279); and2 M12_UM12_3(in134, in133, M12_line3); inv M12_UM12_4(in5, M12_line4); nand2 M12_UM12_5(M12_line3, M12_line4, out292); nand2 M12_UM12_6(in1197, M12_line4, out289); inv M12_UM12_7(in57, M12_line7); nand2 M12_UM12_8(M12_line7, M12_line4, out402); assign out419 = out471; assign out422 = out469; assign out270 = CarryXbus_33; assign out246 = CarryXbus_33; assign out276 = out273; assign out258 = M8_CarryOutYbus_33; assign out264 = M8_CarryOutYbus_33; assign out3 = out2; assign out432 = out2; assign out453 = out2; assign out286 = out279; assign out341 = out279; assign out281 = out292; assign out284 = out289; assign out339 = in339; assign vdd = 1'b1; assign gnd = 1'b0; endmodule |
Added c880.gif.
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> > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c880</TITLE> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C880 8-Bit ALU</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="c880.gif" WIDTH=638 HEIGHT=331></P> <B><P>Statistics: </B>60 inputs; 26 outputs; 383 gates; <A HREF="c880bus.html">bus translations</A></P> <B><P>Function: </B>c880 is an 8-bit ALU with the high-level model shown in above. Given the presence of a CLA module in the <A HREF="74181.html">74181</A> ALU, it is not surprising to find a similar module in c880. The core of this 8-bit ALU is an 8-bit 74283-style adder. The multiplexers M1 and M6 are both controlled by module M2 in a fashion reminiscent of horizontal microcode; i.e., an external source must ensure that no more than one function is activated at a time on C(25:0). </P> <B><P>Models:</P> <UL> </B><LI><A HREF="c880.isc">c880 ISCAS-85 netlist</A><B> </LI> </B><LI><A HREF="c880.v">c880 Verilog hierarchical structural model</A><B> </LI> </B><LI><A HREF="c880b.v">c880 Verilog hierarchical behavioral model</A> </LI> <LI><A HREF="c880.tests">c880 complete gate-level tests</A></LI></UL> <FONT SIZE=2><P> </P></FONT></BODY> </HTML> |
Added c880.isc.
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 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* combinational logic example "c880"
*-------------------------------------------------------------
*
*
* total number of lines in the netlist .............. 880
* simplistically reduced equivalent fault set size = 942
* lines from primary input gates ....... 60
* lines from primary output gates ....... 26
* lines from interior gate outputs ...... 357
* lines from ** 125 ** fanout stems ... 437
*
* avg_fanin = 1.90, max_fanin = 4
* avg_fanout = 3.50, max_fanout = 8
*
*
*
*
*
1 1gat inpt 6 0 >sa0 >sa1
2 1f01 from 1gat >sa1
3 1f02 from 1gat >sa1
4 1f03 from 1gat >sa1
5 1f04 from 1gat >sa1
6 1f05 from 1gat >sa1
7 1f06 from 1gat >sa1
8 8gat inpt 4 0 >sa0 >sa1
9 8f01 from 8gat >sa1
10 8f02 from 8gat >sa1
11 8f03 from 8gat >sa1
12 8f04 from 8gat >sa1
13 13gat inpt 3 0 >sa0 >sa1
14 13f01 from 13gat >sa1
15 13f02 from 13gat >sa1
16 13f03 from 13gat >sa1
17 17gat inpt 8 0 >sa0 >sa1
18 17f01 from 17gat >sa1
19 17f02 from 17gat >sa1
20 17f03 from 17gat >sa1
21 17f04 from 17gat >sa1
22 17f05 from 17gat >sa0
23 17f06 from 17gat >sa1
24 17f07 from 17gat >sa1
25 17f08 from 17gat >sa1
26 26gat inpt 2 0 >sa0 >sa1
27 26f01 from 26gat >sa1
28 26f02 from 26gat >sa1
29 29gat inpt 6 0 >sa0 >sa1
30 29f01 from 29gat >sa1
31 29f02 from 29gat >sa1
32 29f03 from 29gat >sa1
33 29f04 from 29gat >sa1
34 29f05 from 29gat >sa1
35 29f06 from 29gat >sa1
36 36gat inpt 5 0 >sa0 >sa1
37 36f01 from 36gat >sa1
38 36f02 from 36gat >sa1
39 36f03 from 36gat >sa1
40 36f04 from 36gat >sa1
41 36f05 from 36gat >sa1
42 42gat inpt 8 0 >sa0 >sa1
43 42f01 from 42gat >sa1
44 42f02 from 42gat >sa1
45 42f03 from 42gat >sa1
46 42f04 from 42gat >sa1
47 42f05 from 42gat >sa1
48 42f06 from 42gat >sa1
49 42f07 from 42gat >sa0
50 42f08 from 42gat >sa1
51 51gat inpt 3 0 >sa0 >sa1
52 51f01 from 51gat >sa1
53 51f02 from 51gat >sa1
54 51f03 from 51gat >sa1
55 55gat inpt 3 0 >sa0 >sa1
56 55f01 from 55gat >sa1
57 55f02 from 55gat >sa1
58 55f03 from 55gat >sa1
59 59gat inpt 8 0 >sa0 >sa1
60 59f01 from 59gat >sa1
61 59f02 from 59gat >sa1
62 59f03 from 59gat >sa1
63 59f04 from 59gat >sa1
64 59f05 from 59gat >sa1
65 59f06 from 59gat >sa1
66 59f07 from 59gat >sa1
67 59f08 from 59gat >sa1
68 68gat inpt 3 0 >sa0 >sa1
69 68f01 from 68gat >sa1
70 68f02 from 68gat >sa1
71 68f03 from 68gat >sa1
72 72gat inpt 1 0 >sa1
73 73gat inpt 1 0 >sa1
74 74gat inpt 1 0 >sa1
75 75gat inpt 4 0 >sa0 >sa1
76 75f01 from 75gat >sa1
77 75f02 from 75gat >sa1
78 75f03 from 75gat >sa1
79 75f04 from 75gat >sa1
80 80gat inpt 4 0 >sa0 >sa1
81 80f01 from 80gat >sa1
82 80f02 from 80gat >sa1
83 80f03 from 80gat >sa1
84 80f04 from 80gat >sa1
85 85gat inpt 1 0 >sa1
86 86gat inpt 1 0 >sa1
87 87gat inpt 1 0 >sa0
88 88gat inpt 1 0 >sa0
89 89gat inpt 1 0 >sa1
90 90gat inpt 1 0 >sa1
91 91gat inpt 4 0 >sa0 >sa1
92 91f01 from 91gat >sa1
93 91f02 from 91gat >sa0
94 91f03 from 91gat >sa1
95 91f04 from 91gat >sa1
96 96gat inpt 4 0 >sa0 >sa1
97 96f01 from 96gat >sa1
98 96f02 from 96gat >sa0
99 96f03 from 96gat >sa1
100 96f04 from 96gat >sa1
101 101gat inpt 4 0 >sa0 >sa1
102 101f01 from 101gat >sa1
103 101f02 from 101gat >sa0
104 101f03 from 101gat >sa1
105 101f04 from 101gat >sa1
106 106gat inpt 4 0 >sa0 >sa1
107 106f01 from 106gat >sa1
108 106f02 from 106gat >sa0
109 106f03 from 106gat >sa1
110 106f04 from 106gat >sa1
111 111gat inpt 4 0 >sa0 >sa1
112 111f01 from 111gat >sa1
113 111f02 from 111gat >sa0
114 111f03 from 111gat >sa1
115 111f04 from 111gat >sa1
116 116gat inpt 4 0 >sa0 >sa1
117 116f01 from 116gat >sa1
118 116f02 from 116gat >sa0
119 116f03 from 116gat >sa1
120 116f04 from 116gat >sa1
121 121gat inpt 4 0 >sa0 >sa1
122 121f01 from 121gat >sa1
123 121f02 from 121gat >sa0
124 121f03 from 121gat >sa1
125 121f04 from 121gat >sa1
126 126gat inpt 3 0 >sa0 >sa1
127 126f01 from 126gat >sa1
128 126f02 from 126gat >sa0
129 126f03 from 126gat >sa1
130 130gat inpt 4 0 >sa0 >sa1
131 130f01 from 130gat >sa1
132 130f02 from 130gat >sa0
133 130f03 from 130gat >sa1
134 130f04 from 130gat >sa0
135 135gat inpt 2 0 >sa0 >sa1
136 135f01 from 135gat >sa1
137 135f02 from 135gat >sa0
138 138gat inpt 4 0 >sa0 >sa1
139 138f01 from 138gat >sa1
140 138f02 from 138gat >sa1
141 138f03 from 138gat >sa1
142 138f04 from 138gat >sa1
143 143gat inpt 2 0 >sa0 >sa1
144 143f01 from 143gat >sa1
145 143f02 from 143gat >sa1
146 146gat inpt 2 0 >sa0 >sa1
147 146f01 from 146gat >sa1
148 146f02 from 146gat >sa1
149 149gat inpt 2 0 >sa0 >sa1
150 149f01 from 149gat >sa1
151 149f02 from 149gat >sa1
152 152gat inpt 1 0 >sa1
153 153gat inpt 2 0 >sa0 >sa1
154 153f01 from 153gat >sa1
155 153f02 from 153gat >sa1
156 156gat inpt 2 0 >sa0 >sa1
157 156f01 from 156gat >sa1
158 156f02 from 156gat >sa1
159 159gat inpt 5 0 >sa0 >sa1
160 159f01 from 159gat >sa1
161 159f02 from 159gat >sa0
162 159f03 from 159gat >sa1
163 159f04 from 159gat >sa1
164 159f05 from 159gat >sa0
165 165gat inpt 5 0 >sa0 >sa1
166 165f01 from 165gat >sa1
167 165f02 from 165gat >sa0
168 165f03 from 165gat >sa1
169 165f04 from 165gat >sa1
170 165f05 from 165gat >sa0
171 171gat inpt 5 0 >sa0 >sa1
172 171f01 from 171gat >sa1
173 171f02 from 171gat >sa0
174 171f03 from 171gat >sa1
175 171f04 from 171gat >sa1
176 171f05 from 171gat >sa0
177 177gat inpt 5 0 >sa0 >sa1
178 177f01 from 177gat >sa1
179 177f02 from 177gat >sa0
180 177f03 from 177gat >sa1
181 177f04 from 177gat >sa1
182 177f05 from 177gat >sa0
183 183gat inpt 5 0 >sa0 >sa1
184 183f01 from 183gat >sa1
185 183f02 from 183gat >sa0
186 183f03 from 183gat >sa1
187 183f04 from 183gat >sa1
188 183f05 from 183gat >sa0
189 189gat inpt 5 0 >sa0 >sa1
190 189f01 from 189gat >sa1
191 189f02 from 189gat >sa0
192 189f03 from 189gat >sa1
193 189f04 from 189gat >sa1
194 189f05 from 189gat >sa0
195 195gat inpt 5 0 >sa0 >sa1
196 195f01 from 195gat >sa1
197 195f02 from 195gat >sa0
198 195f03 from 195gat >sa1
199 195f04 from 195gat >sa1
200 195f05 from 195gat >sa0
201 201gat inpt 5 0 >sa0 >sa1
202 201f01 from 201gat >sa1
203 201f02 from 201gat >sa0
204 201f03 from 201gat >sa1
205 201f04 from 201gat >sa1
206 201f05 from 201gat >sa0
207 207gat inpt 2 0 >sa0 >sa1
208 207f01 from 207gat >sa1
209 207f02 from 207gat >sa0
210 210gat inpt 8 0 >sa0 >sa1
211 210f01 from 210gat >sa1
212 210f02 from 210gat >sa1
213 210f03 from 210gat >sa1
214 210f04 from 210gat >sa1
215 210f05 from 210gat >sa1
216 210f06 from 210gat >sa1
217 210f07 from 210gat >sa1
218 210f08 from 210gat >sa1
219 219gat inpt 8 0 >sa0 >sa1
220 219f01 from 219gat >sa1
221 219f02 from 219gat >sa1
222 219f03 from 219gat >sa1
223 219f04 from 219gat >sa1
224 219f05 from 219gat >sa1
225 219f06 from 219gat >sa1
226 219f07 from 219gat >sa1
227 219f08 from 219gat >sa1
228 228gat inpt 8 0 >sa0 >sa1
229 228f01 from 228gat >sa1
230 228f02 from 228gat >sa1
231 228f03 from 228gat >sa1
232 228f04 from 228gat >sa1
233 228f05 from 228gat >sa1
234 228f06 from 228gat >sa1
235 228f07 from 228gat >sa1
236 228f08 from 228gat >sa1
237 237gat inpt 8 0 >sa0 >sa1
238 237f01 from 237gat >sa1
239 237f02 from 237gat >sa1
240 237f03 from 237gat >sa1
241 237f04 from 237gat >sa1
242 237f05 from 237gat >sa1
243 237f06 from 237gat >sa1
244 237f07 from 237gat >sa1
245 237f08 from 237gat >sa1
246 246gat inpt 8 0 >sa0 >sa1
247 246f01 from 246gat >sa1
248 246f02 from 246gat >sa1
249 246f03 from 246gat >sa1
250 246f04 from 246gat >sa1
251 246f05 from 246gat >sa1
252 246f06 from 246gat >sa1
253 246f07 from 246gat >sa1
254 246f08 from 246gat >sa1
255 255gat inpt 3 0 >sa0 >sa1
256 255f01 from 255gat >sa1
257 255f02 from 255gat >sa1
258 255f03 from 255gat >sa1
259 259gat inpt 1 0 >sa1
260 260gat inpt 1 0 >sa1
261 261gat inpt 5 0 >sa0 >sa1
262 261f01 from 261gat >sa1
263 261f02 from 261gat >sa1
264 261f03 from 261gat >sa1
265 261f04 from 261gat >sa0
266 261f05 from 261gat >sa1
267 267gat inpt 1 0 >sa1
268 268gat inpt 1 0
269 269gat nand 1 4
2 9 14 18
270 270gat nand 2 4 >sa0 >sa1
3 27 15 19
271 270f01 from 270gat >sa0
272 270f02 from 270gat >sa0
273 273gat and 2 3 >sa0 >sa1
30 37 43
274 273f01 from 273gat
275 273f02 from 273gat >sa0
276 276gat and 2 3 >sa0 >sa1
4 28 52
277 276f01 from 276gat
278 276f02 from 276gat
279 279gat nand 1 4
5 10 53 20
280 280gat nand 3 4 >sa0 >sa1
6 11 16 56
281 280f01 from 280gat >sa0
282 280f02 from 280gat >sa0
283 280f03 from 280gat >sa0
284 284gat nand 1 4 >sa0
60 44 69 72
285 285gat nand 1 2 >sa0
31 70
286 286gat nand 1 3 >sa0
61 71 74
287 287gat and 2 3 >sa0 >sa1
32 76 81
288 287f01 from 287gat >sa1
289 287f02 from 287gat >sa1
290 290gat and 1 3
33 77 45
291 291gat and 1 3
34 38 82
292 292gat and 1 3
35 39 46
293 293gat and 1 3
62 78 83
294 294gat and 1 3
63 79 47
295 295gat and 1 3
64 40 84
296 296gat and 1 3
65 41 48
297 297gat and 1 2
85 86
298 298gat or 2 2 >sa0 >sa1
87 88
299 298f01 from 298gat >sa1
300 298f02 from 298gat >sa1
301 301gat nand 1 2 >sa1
92 97
302 302gat or 1 2 >sa1
93 98
303 303gat nand 1 2 >sa1
102 107
304 304gat or 1 2 >sa1
103 108
305 305gat nand 1 2 >sa1
112 117
306 306gat or 1 2 >sa1
113 118
307 307gat nand 1 2 >sa1
122 127
308 308gat or 1 2 >sa1
123 128
309 309gat and 1 2 >sa0
12 139
310 310gat not 5 1 >sa0 >sa1
268
311 310f01 from 310gat
312 310f02 from 310gat >sa1
313 310f03 from 310gat >sa1
314 310f04 from 310gat >sa1
315 310f05 from 310gat >sa1
316 316gat and 1 2 >sa0
54 140
317 317gat and 1 2 >sa0
21 141
318 318gat and 1 2 >sa0
152 142
319 319gat nand 2 2 >sa0 >sa1
66 157
320 319f01 from 319gat >sa1
321 319f02 from 319gat >sa1
322 322gat nor 1 2 >sa0
22 49
323 323gat and 1 2 >sa0
23 50
324 324gat nand 1 2 >sa1
160 166
325 325gat or 1 2 >sa1
161 167
326 326gat nand 1 2 >sa1
172 178
327 327gat or 1 2 >sa1
173 179
328 328gat nand 1 2 >sa1
184 190
329 329gat or 1 2 >sa1
185 191
330 330gat nand 1 2 >sa1
196 202
331 331gat or 1 2 >sa1
197 203
332 332gat and 1 2 >sa0
211 94
333 333gat and 1 2 >sa0
212 99
334 334gat and 1 2 >sa0
213 104
335 335gat and 1 2 >sa0
214 109
336 336gat and 1 2 >sa0
215 114
337 337gat and 1 2 >sa0
256 259
338 338gat and 1 2 >sa0
216 119
339 339gat and 1 2 >sa0
257 260
340 340gat and 1 2 >sa0
217 124
341 341gat and 1 2 >sa0
258 267
342 342gat not 1 1
269
343 343gat not 1 1 >sa0
274
344 344gat or 1 2
271 275
345 345gat not 1 1
277
346 346gat not 1 1
278
347 347gat not 1 1 >sa1
279
348 348gat nor 1 2 >sa1
281 284
349 349gat or 1 2
282 285
350 350gat or 1 2
283 286
351 351gat not 1 1
293
352 352gat not 1 1 >sa1
294
353 353gat not 1 1
295
354 354gat not 1 1
296
355 355gat nand 1 2
89 299
356 356gat and 1 2
90 300
357 357gat nand 2 2 >sa0 >sa1
301 302
358 357f01 from 357gat
359 357f02 from 357gat >sa1
360 360gat nand 2 2 >sa0 >sa1
303 304
361 360f01 from 360gat
362 360f02 from 360gat >sa1
363 363gat nand 2 2 >sa0 >sa1
305 306
364 363f01 from 363gat
365 363f02 from 363gat >sa1
366 366gat nand 2 2 >sa0 >sa1
307 308
367 366f01 from 366gat
368 366f02 from 366gat >sa1
369 369gat not 5 1 >sa0 >sa1
311
370 369f01 from 369gat >sa1
371 369f02 from 369gat >sa0
372 369f03 from 369gat >sa0
373 369f04 from 369gat >sa0
374 369f05 from 369gat >sa0
375 375gat nor 1 2 >sa1
322 323
376 376gat nand 2 2 >sa0 >sa1
324 325
377 376f01 from 376gat
378 376f02 from 376gat >sa1
379 379gat nand 2 2 >sa0 >sa1
326 327
380 379f01 from 379gat
381 379f02 from 379gat >sa1
382 382gat nand 2 2 >sa0 >sa1
328 329
383 382f01 from 382gat
384 382f02 from 382gat >sa1
385 385gat nand 2 2 >sa0 >sa1
330 331
386 385f01 from 385gat
387 385f02 from 385gat >sa1
388 388gat buff 0 1 >sa0 >sa1
290
389 389gat buff 0 1 >sa0 >sa1
291
390 390gat buff 0 1 >sa0 >sa1
292
391 391gat buff 0 1 >sa0 >sa1
297
392 392gat or 1 2
272 343
393 393gat not 5 1 >sa0 >sa1
345
394 393f01 from 393gat >sa1
395 393f02 from 393gat >sa1
396 393f03 from 393gat >sa1
397 393f04 from 393gat >sa1
398 393f05 from 393gat >sa1
399 399gat not 1 1
346
400 400gat and 1 2
348 73
401 401gat not 1 1
349
402 402gat not 1 1
350
403 403gat not 1 1
355
404 404gat not 1 1 >sa1
358
405 405gat not 1 1 >sa1
361
406 406gat and 1 2 >sa0
359 362
407 407gat not 1 1 >sa1
364
408 408gat not 1 1 >sa1
367
409 409gat and 1 2 >sa0
365 368
410 410gat nand 1 2 >sa1
347 352
411 411gat not 1 1 >sa1
377
412 412gat not 1 1 >sa1
380
413 413gat and 1 2 >sa0
378 381
414 414gat not 1 1 >sa1
383
415 415gat not 1 1 >sa1
386
416 416gat and 1 2 >sa0
384 387
417 417gat and 1 2 >sa0
218 370
418 418gat buff 0 1 >sa0 >sa1
342
419 419gat buff 0 1 >sa0 >sa1
344
420 420gat buff 0 1 >sa0 >sa1
351
421 421gat buff 0 1 >sa0 >sa1
353
422 422gat buff 0 1 >sa0 >sa1
354
423 423gat buff 0 1 >sa0 >sa1
356
424 424gat not 1 1
400
425 425gat and 1 2 >sa0
404 405
426 426gat and 1 2 >sa0
407 408
427 427gat and 4 3 >sa0 >sa1
320 394 57
428 427f01 from 427gat >sa1
429 427f02 from 427gat >sa1
430 427f03 from 427gat >sa1
431 427f04 from 427gat >sa1
432 432gat and 4 3 >sa0 >sa1
395 24 288
433 432f01 from 432gat >sa1
434 432f02 from 432gat >sa1
435 432f03 from 432gat >sa1
436 432f04 from 432gat >sa1
437 437gat nand 4 3 >sa0 >sa1
396 289 58
438 437f01 from 437gat >sa0
439 437f02 from 437gat >sa0
440 437f03 from 437gat >sa0
441 437f04 from 437gat >sa0
442 442gat nand 1 4 >sa1
375 67 158 397
443 443gat nand 1 3 >sa1
398 321 25
444 444gat and 1 2 >sa0
411 412
445 445gat and 1 2 >sa0
414 415
446 446gat buff 0 1 >sa0 >sa1
392
447 447gat buff 0 1 >sa0 >sa1
399
448 448gat buff 0 1 >sa0 >sa1
401
449 449gat buff 0 1 >sa0 >sa1
402
450 450gat buff 0 1 >sa0 >sa1
403
451 451gat not 8 1 >sa0 >sa1
424
452 451f01 from 451gat >sa1
453 451f02 from 451gat >sa1
454 451f03 from 451gat >sa1
455 451f04 from 451gat >sa1
456 451f05 from 451gat >sa1
457 451f06 from 451gat >sa1
458 451f07 from 451gat >sa1
459 451f08 from 451gat >sa1
460 460gat nor 2 2 >sa0 >sa1
406 425
461 460f01 from 460gat >sa1
462 460f02 from 460gat >sa0
463 463gat nor 2 2 >sa0 >sa1
409 426
464 463f01 from 463gat >sa1
465 463f02 from 463gat >sa0
466 466gat nand 8 2 >sa0 >sa1
442 410
467 466f01 from 466gat >sa1
468 466f02 from 466gat >sa1
469 466f03 from 466gat >sa1
470 466f04 from 466gat >sa1
471 466f05 from 466gat >sa1
472 466f06 from 466gat >sa1
473 466f07 from 466gat >sa1
474 466f08 from 466gat >sa1
475 475gat and 1 2 >sa0
144 428
476 476gat and 1 2 >sa0
312 433
477 477gat and 1 2 >sa0
147 429
478 478gat and 1 2 >sa0
313 434
479 479gat and 1 2 >sa0
150 430
480 480gat and 1 2 >sa0
314 435
481 481gat and 1 2 >sa0
154 431
482 482gat and 1 2 >sa0
315 436
483 483gat nand 4 2 >sa0 >sa1
443 7
484 483f01 from 483gat >sa1
485 483f02 from 483gat >sa1
486 483f03 from 483gat >sa1
487 483f04 from 483gat >sa1
488 488gat or 1 2 >sa1
371 438
489 489gat or 1 2 >sa1
372 439
490 490gat or 1 2 >sa1
373 440
491 491gat or 1 2 >sa1
374 441
492 492gat nor 2 2 >sa0 >sa1
413 444
493 492f01 from 492gat >sa1
494 492f02 from 492gat >sa0
495 495gat nor 2 2 >sa0 >sa1
416 445
496 495f01 from 495gat >sa1
497 495f02 from 495gat >sa0
498 498gat nand 1 2 >sa1
131 461
499 499gat or 1 2 >sa1
132 462
500 500gat nand 1 2 >sa1
464 136
501 501gat or 1 2 >sa1
465 137
502 502gat and 1 2 >sa0
95 467
503 503gat nor 1 2 >sa1
475 476
504 504gat and 1 2 >sa0
100 468
505 505gat nor 1 2 >sa1
477 478
506 506gat and 1 2 >sa0
105 469
507 507gat nor 1 2 >sa1
479 480
508 508gat and 1 2 >sa0
110 470
509 509gat nor 1 2 >sa1
481 482
510 510gat and 1 2 >sa0
145 484
511 511gat and 1 2 >sa0
115 471
512 512gat and 1 2 >sa0
148 485
513 513gat and 1 2 >sa0
120 472
514 514gat and 1 2 >sa0
151 486
515 515gat and 1 2 >sa0
125 473
516 516gat and 1 2 >sa0
155 487
517 517gat and 1 2 >sa0
129 474
518 518gat nand 1 2 >sa1
133 493
519 519gat or 1 2 >sa1
134 494
520 520gat nand 1 2 >sa1
496 208
521 521gat or 1 2 >sa1
497 209
522 522gat and 1 2 >sa0
452 162
523 523gat and 1 2 >sa0
453 168
524 524gat and 1 2 >sa0
454 174
525 525gat and 1 2 >sa0
455 180
526 526gat and 1 2 >sa0
456 186
527 527gat nand 1 2 >sa1
457 192
528 528gat nand 1 2 >sa1
458 198
529 529gat nand 1 2 >sa1
459 204
530 530gat nand 2 2 >sa0 >sa1
498 499
531 530f01 from 530gat
532 530f02 from 530gat >sa1
533 533gat nand 2 2 >sa0 >sa1
500 501
534 533f01 from 533gat
535 533f02 from 533gat >sa1
536 536gat nor 1 2 >sa1
309 502
537 537gat nor 1 2 >sa1
316 504
538 538gat nor 1 2 >sa1
317 506
539 539gat nor 1 2 >sa1
318 508
540 540gat nor 1 2 >sa1
510 511
541 541gat nor 1 2 >sa1
512 513
542 542gat nor 1 2 >sa1
514 515
543 543gat nor 1 2 >sa1
516 517
544 544gat nand 2 2 >sa0 >sa1
518 519
545 544f01 from 544gat
546 544f02 from 544gat >sa1
547 547gat nand 2 2 >sa0 >sa1
520 521
548 547f01 from 547gat
549 547f02 from 547gat >sa1
550 550gat not 1 1 >sa1
531
551 551gat not 1 1 >sa1
534
552 552gat and 1 2 >sa0
532 535
553 553gat nand 3 2 >sa0 >sa1
536 503
554 553f01 from 553gat >sa1
555 553f02 from 553gat >sa0
556 553f03 from 553gat >sa1
557 557gat nand 3 2 >sa0 >sa1
537 505
558 557f01 from 557gat >sa1
559 557f02 from 557gat >sa0
560 557f03 from 557gat >sa1
561 561gat nand 3 2 >sa0 >sa1
538 507
562 561f01 from 561gat >sa1
563 561f02 from 561gat >sa0
564 561f03 from 561gat >sa1
565 565gat nand 3 2 >sa0 >sa1
539 509
566 565f01 from 565gat >sa1
567 565f02 from 565gat >sa0
568 565f03 from 565gat >sa1
569 569gat nand 3 2 >sa0 >sa1
488 540
570 569f01 from 569gat >sa1
571 569f02 from 569gat >sa0
572 569f03 from 569gat >sa1
573 573gat nand 3 2 >sa0 >sa1
489 541
574 573f01 from 573gat >sa1
575 573f02 from 573gat >sa0
576 573f03 from 573gat >sa1
577 577gat nand 3 2 >sa0 >sa1
490 542
578 577f01 from 577gat >sa1
579 577f02 from 577gat >sa0
580 577f03 from 577gat >sa1
581 581gat nand 3 2 >sa0 >sa1
491 543
582 581f01 from 581gat >sa1
583 581f02 from 581gat >sa0
584 581f03 from 581gat >sa1
585 585gat not 1 1 >sa1
545
586 586gat not 1 1 >sa1
548
587 587gat and 1 2 >sa0
546 549
588 588gat and 1 2 >sa0
550 551
589 589gat and 1 2 >sa0
585 586
590 590gat nand 2 2 >sa0 >sa1
554 163
591 590f01 from 590gat
592 590f02 from 590gat >sa1
593 593gat or 2 2 >sa0 >sa1
555 164
594 593f01 from 593gat >sa1
595 593f02 from 593gat >sa1
596 596gat and 1 2 >sa0
247 556
597 597gat nand 2 2 >sa0 >sa1
558 169
598 597f01 from 597gat
599 597f02 from 597gat >sa1
600 600gat or 4 2 >sa0 >sa1
559 170
601 600f01 from 600gat >sa1
602 600f02 from 600gat >sa1
603 600f03 from 600gat >sa1
604 600f04 from 600gat >sa1
605 605gat and 1 2 >sa0
248 560
606 606gat nand 2 2 >sa0 >sa1
562 175
607 606f01 from 606gat
608 606f02 from 606gat >sa1
609 609gat or 5 2 >sa0 >sa1
563 176
610 609f01 from 609gat >sa1
611 609f02 from 609gat >sa1
612 609f03 from 609gat >sa1
613 609f04 from 609gat >sa1
614 609f05 from 609gat >sa1
615 615gat and 1 2 >sa0
249 564
616 616gat nand 2 2 >sa0 >sa1
566 181
617 616f01 from 616gat
618 616f02 from 616gat >sa1
619 619gat or 4 2 >sa0 >sa1
567 182
620 619f01 from 619gat >sa1
621 619f02 from 619gat >sa1
622 619f03 from 619gat >sa1
623 619f04 from 619gat >sa1
624 624gat and 1 2 >sa0
250 568
625 625gat nand 2 2 >sa0 >sa1
570 187
626 625f01 from 625gat
627 625f02 from 625gat >sa1
628 628gat or 2 2 >sa0 >sa1
571 188
629 628f01 from 628gat >sa1
630 628f02 from 628gat >sa1
631 631gat and 1 2 >sa0
251 572
632 632gat nand 2 2 >sa0 >sa1
574 193
633 632f01 from 632gat
634 632f02 from 632gat >sa1
635 635gat or 4 2 >sa0 >sa1
575 194
636 635f01 from 635gat >sa1
637 635f02 from 635gat >sa1
638 635f03 from 635gat >sa1
639 635f04 from 635gat >sa1
640 640gat and 1 2 >sa0
252 576
641 641gat nand 2 2 >sa0 >sa1
578 199
642 641f01 from 641gat
643 641f02 from 641gat >sa1
644 644gat or 5 2 >sa0 >sa1
579 200
645 644f01 from 644gat >sa1
646 644f02 from 644gat >sa1
647 644f03 from 644gat >sa1
648 644f04 from 644gat >sa1
649 644f05 from 644gat >sa1
650 650gat and 1 2 >sa0
253 580
651 651gat nand 2 2 >sa0 >sa1
582 205
652 651f01 from 651gat
653 651f02 from 651gat >sa1
654 654gat or 4 2 >sa0 >sa1
583 206
655 654f01 from 654gat >sa1
656 654f02 from 654gat >sa1
657 654f03 from 654gat >sa1
658 654f04 from 654gat >sa1
659 659gat and 1 2 >sa0
254 584
660 660gat nor 1 2
552 588
661 661gat nor 1 2
587 589
662 662gat not 2 1 >sa0 >sa1
591
663 662f01 from 662gat
664 662f02 from 662gat >sa1
665 665gat and 3 2 >sa0 >sa1
594 592
666 665f01 from 665gat >sa1
667 665f02 from 665gat >sa0
668 665f03 from 665gat >sa1
669 669gat nor 1 2 >sa1
596 522
670 670gat not 2 1 >sa0 >sa1
598
671 670f01 from 670gat
672 670f02 from 670gat >sa1
673 673gat and 3 2 >sa0 >sa1
601 599
674 673f01 from 673gat >sa1
675 673f02 from 673gat >sa0
676 673f03 from 673gat >sa1
677 677gat nor 1 2 >sa1
605 523
678 678gat not 3 1 >sa0 >sa1
607
679 678f01 from 678gat
680 678f02 from 678gat >sa1
681 678f03 from 678gat >sa1
682 682gat and 3 2 >sa0 >sa1
610 608
683 682f01 from 682gat >sa1
684 682f02 from 682gat >sa0
685 682f03 from 682gat >sa1
686 686gat nor 1 2 >sa1
615 524
687 687gat not 4 1 >sa0 >sa1
617
688 687f01 from 687gat
689 687f02 from 687gat >sa1
690 687f03 from 687gat >sa1
691 687f04 from 687gat >sa1
692 692gat and 3 2 >sa0 >sa1
620 618
693 692f01 from 692gat >sa1
694 692f02 from 692gat >sa0
695 692f03 from 692gat >sa1
696 696gat nor 1 2 >sa1
624 525
697 697gat not 2 1 >sa0 >sa1
626
698 697f01 from 697gat
699 697f02 from 697gat >sa1
700 700gat and 3 2 >sa0 >sa1
629 627
701 700f01 from 700gat >sa1
702 700f02 from 700gat >sa0
703 700f03 from 700gat >sa1
704 704gat nor 1 2 >sa1
631 526
705 705gat not 2 1 >sa0 >sa1
633
706 705f01 from 705gat
707 705f02 from 705gat >sa1
708 708gat and 3 2 >sa0 >sa1
636 634
709 708f01 from 708gat >sa1
710 708f02 from 708gat >sa0
711 708f03 from 708gat >sa1
712 712gat nor 1 2 >sa1
337 640
713 713gat not 3 1 >sa0 >sa1
642
714 713f01 from 713gat
715 713f02 from 713gat >sa1
716 713f03 from 713gat >sa1
717 717gat and 3 2 >sa0 >sa1
645 643
718 717f01 from 717gat >sa1
719 717f02 from 717gat >sa0
720 717f03 from 717gat >sa1
721 721gat nor 1 2 >sa1
339 650
722 722gat not 4 1 >sa0 >sa1
652
723 722f01 from 722gat
724 722f02 from 722gat >sa1
725 722f03 from 722gat >sa1
726 722f04 from 722gat >sa1
727 727gat and 3 2 >sa0 >sa1
655 653
728 727f01 from 727gat >sa0
729 727f02 from 727gat >sa1
730 727f03 from 727gat >sa1
731 731gat nor 1 2 >sa1
341 659
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736 736gat and 1 2 >sa0
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679
742 742gat and 1 2 >sa0
231 683
743 743gat and 1 2 >sa0
240 680
744 744gat not 1 1 >sa1
688
745 745gat and 1 2 >sa0
232 693
746 746gat and 1 2 >sa0
241 689
747 747gat not 1 1 >sa1
698
748 748gat and 1 2 >sa0
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749 749gat and 1 2 >sa0
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750 750gat not 1 1 >sa1
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234 709
752 752gat and 1 2 >sa0
243 707
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235 718
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758 758gat and 1 2 >sa0
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236 730
760 760gat and 1 2 >sa0
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768 768gat buff 0 1 >sa0 >sa1
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769 769gat nor 1 2 >sa1
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774 773f01 from 773gat >sa0
775 773f02 from 773gat >sa1
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777 777gat nor 1 2 >sa1
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778 778gat nand 2 3 >sa0 >sa1
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779 778f01 from 778gat >sa0
780 778f02 from 778gat >sa1
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783 782f01 from 782gat >sa0
784 782f02 from 782gat >sa1
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795 747
797 796f01 from 796gat >sa0
798 796f02 from 796gat >sa1
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800 796f04 from 796gat >sa1
801 796f05 from 796gat >sa1
802 802gat nor 1 2 >sa1
788 789
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221 802
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222 803
810 810gat and 1 2 >sa0
223 804
811 811gat nand 1 4
805 787 731 529
812 812gat nand 1 2 >sa1
621 799
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613 622 800
814 814gat nand 1 4 >sa1
604 614 623 801
815 815gat nand 3 4 >sa0 >sa1
738 765 766 814
816 815f01 from 815gat >sa0
817 815f02 from 815gat >sa1
818 815f03 from 815gat >sa1
819 819gat nand 2 3 >sa0 >sa1
741 764 813
820 819f01 from 819gat >sa0
821 819f02 from 819gat >sa1
822 822gat nand 2 2 >sa0 >sa1
744 812
823 822f01 from 822gat >sa0
824 822f02 from 822gat >sa1
825 825gat nor 1 2 >sa1
806 807
826 826gat nor 1 2 >sa1
335 808
827 827gat nor 1 2 >sa1
336 809
828 828gat nor 1 2 >sa1
338 810
829 829gat not 1 1
811
830 830gat nor 1 2 >sa0
667 816
831 831gat and 1 2 >sa0
668 817
832 832gat nor 1 2 >sa0
675 820
833 833gat and 1 2 >sa0
676 821
834 834gat nor 1 2 >sa0
684 823
835 835gat and 1 2 >sa0
685 824
836 836gat and 1 2 >sa0
224 825
837 837gat nand 1 3
826 777 704
838 838gat nand 1 4
827 781 712 527
839 839gat nand 1 4
828 785 721 528
840 840gat not 1 1
829
841 841gat nand 1 2 >sa1
818 595
842 842gat nor 1 2 >sa1
830 831
843 843gat nor 1 2 >sa1
832 833
844 844gat nor 1 2 >sa1
834 835
845 845gat nor 1 2 >sa1
334 836
846 846gat not 1 1
837
847 847gat not 1 1
838
848 848gat not 1 1
839
849 849gat and 1 2
735 841
850 850gat buff 0 1 >sa0 >sa1
840
851 851gat and 1 2 >sa0
225 842
852 852gat and 1 2 >sa0
226 843
853 853gat and 1 2 >sa0
227 844
854 854gat nand 1 3
845 772 696
855 855gat not 1 1
846
856 856gat not 1 1
847
857 857gat not 1 1
848
858 858gat not 1 1
849
859 859gat nor 1 2 >sa1
417 851
860 860gat nor 1 2 >sa1
332 852
861 861gat nor 1 2 >sa1
333 853
862 862gat not 1 1
854
863 863gat buff 0 1 >sa0 >sa1
855
864 864gat buff 0 1 >sa0 >sa1
856
865 865gat buff 0 1 >sa0 >sa1
857
866 866gat buff 0 1 >sa0 >sa1
858
867 867gat nand 1 3
859 769 669
868 868gat nand 1 3
860 770 677
869 869gat nand 1 3
861 771 686
870 870gat not 1 1
862
871 871gat not 1 1
867
872 872gat not 1 1
868
873 873gat not 1 1
869
874 874gat buff 0 1 >sa0 >sa1
870
875 875gat not 1 1
871
876 876gat not 1 1
872
877 877gat not 1 1
873
878 878gat buff 0 1 >sa0 >sa1
875
879 879gat buff 0 1 >sa0 >sa1
876
880 880gat buff 0 1 >sa0 >sa1
877
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> > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 | 110111101111001101101111111111100000010000000000001000000001 011111001111001111010111111111101000000111111111101011100100 111100011101111110100110111011100011101000010001001000011011 101111101101000010010001111111100001100100100010001000000000 111101111111011000000000100010000000010101000100001000000000 111111011110111010000001000100000000000111101110001000000100 100110001110000000000001111111100010001011011101001000000100 111011111111100100000001011101100000000110111011001000000100 111111111111001110000000001000111000000100010001100001000000 100111101010000100000001101111100100000111111111000010000000 100111111110000110000001111111100011101111111111010000000001 111011011011110110000000000000000011101011111111000100000000 111110111111110110000001111111100011101111111111000000000000 111010001111110000000000010100000100011110001000000001111010 100010110100000000000000000000000111101011111111010000000010 111111110111110000000000000000100000000000000000000100000000 011111110111110000000001010101010000001010101010000001000001 |
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>c880bus</TITLE> <META NAME="Version" CONTENT="8.0.3410"> <META NAME="Date" CONTENT="10/11/96"> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY TEXT="#000000" LINK="#0000ff" VLINK="#800080" BGCOLOR="#ffffff"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-85 C880 8-Bit ALU</P> <P ALIGN="CENTER">Bus Translations</P> </B></FONT><P> </P> <TABLE BORDER CELLSPACING=1 WIDTH=778> <TR><TD WIDTH="13%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997489"></A><B>I/O buses</B></TD> <TD WIDTH="19%" VALIGN="MIDDLE"> <B><P ALIGN="CENTER"><A NAME="pgfId_997491"></A>Function</B></TD> <TD WIDTH="68%" VALIGN="MIDDLE"> <B><P ALIGN="CENTER"><A NAME="pgfId_997496"></A>ISCAS-85 Netlist numbers </B></TD> </TR> <TR><TD WIDTH="13%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997498"></A>A[8:0]</TD> <TD WIDTH="19%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997500"></A>Main A bus</TD> <TD WIDTH="68%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997502"></A>268,91, 96, 101, 106, 111, 116, 121, 126</TD> </TR> <TR><TD WIDTH="13%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997504"></A>B[7:0]</TD> <TD WIDTH="19%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997506"></A>Main B bus</TD> <TD WIDTH="68%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997508"></A>159, 165, 171, 177, 183, 189, 195, 201</TD> </TR> <TR><TD WIDTH="13%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997510"></A>C[25:0]</TD> <TD WIDTH="19%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997512"></A>Control bus</TD> <TD WIDTH="68%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997514"></A>207, 135, 156, 90, 89, 88, 87, 86, 85, 80, 75, 74, 73,</P> <P ALIGN="CENTER"><A NAME="pgfId_997515"></A>72, 68, 59, 55, 51, 42, 36, 29, 26, 17, 13, 8, 1</TD> </TR> <TR><TD WIDTH="13%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997517"></A>D[3:0]</TD> <TD WIDTH="19%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997519"></A>4-bit bus</TD> <TD WIDTH="68%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997521"></A>143, 146, 149, 153</TD> </TR> <TR><TD WIDTH="13%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997523"></A>F[7:0]</TD> <TD WIDTH="19%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997525"></A>Output function</TD> <TD WIDTH="68%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997527"></A>878,879,880,874,863,864,865,850</TD> </TR> <TR><TD WIDTH="13%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997529"></A>G[3:0]</TD> <TD WIDTH="19%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997531"></A>4-bit bus</TD> <TD WIDTH="68%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997533"></A>8, 51, 17, 152</TD> </TR> <TR><TD WIDTH="13%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997535"></A>C in</TD> <TD WIDTH="19%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997537"></A>Carry in</TD> <TD WIDTH="68%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997539"></A>261</TD> </TR> <TR><TD WIDTH="13%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997541"></A>C8</TD> <TD WIDTH="19%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997543"></A>Carry out</TD> <TD WIDTH="68%" VALIGN="MIDDLE"> <P ALIGN="CENTER"><A NAME="pgfId_997545"></A>866</TD> </TR> </TABLE> <P><A NAME="pgfId_997547"></A> </P></BODY> </HTML> |
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 |
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<TITLE>ISCAS_HLM</TITLE>
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<br><B><FONT SIZE=5>ISCAS High-Level Models
<p></font></b>These pages contain high-level models for all ISCAS-85, several of the smaller ISCAS-89, and several 74X-series circuits. These models may be freely copied and used for research purposes.</P>
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<P> </B></FONT>
<b> Recent Publication:</b>
<ul><li>M. Hansen, H. Yalcin, and J. P. Hayes, "Unveiling the ISCAS-85
Benchmarks: A Case Study in Reverse Engineering," IEEE Design and Test,
vol. 16, no. 3, pp. 72-80, July-Sept. 1999.
<P>Abstract: Digital designers normally proceed from behavioral specification to logic circuit; rarely do they need
to go in the reverse direction. One such situation is examined here: recovering the high-level specifications of a
popular set of benchmark logic circuits. The authors present their methodology and experience in reverse
engineering the ISCAS-85 circuits. They also discuss a few of the practical uses of the resulting high-level
benchmarks, and make them available for other researchers to use.
<p>The high-level ISCAS-85 benchmarks discussed in this paper are available below, and we invite other researchers to use them. The models, of which we have constructed both structural and
behavioral versions, partition the original gate-level netlists into standard RTL blocks and identify the functions of
these blocks. Together, the gate-level and high-level models form a set of hierarchicical benchmark circuits that
have proven to be useful research tools in several areas of digital design, including test generation, timing
analysis, and technology mapping. The web documentation for each model consists of annotated circuit schematic
diagrams, and executable (simulatable) descriptions written in structural Verilog. The structural models are
intended to express the specific high-level structure implicit in the original gate-level designs. In most cases, we
also provide behavioral Verilog models, which define high-level blocks in the form of logical equations that can
readily be synthesized into gates.
</ul>
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<P> <B>ISCAS-85 Circuits:</P>
<UL>
<UL>
</B><LI><A HREF="c432.html">c432</A><FONT SIZE=2> </FONT>:<FONT SIZE=2> </FONT>27-channel interrupt controller </LI>
<LI><A HREF="c499.html">c499/c1355</A><FONT SIZE=2> </FONT>: 32-bit SEC circuit</LI>
<LI><A HREF="c880.html">c880</A><FONT SIZE=2> </FONT>: 8-bit ALU </LI>
<LI><A HREF="c1908/c1908.html">c1908</A> : 16-bit SEC/DED circuit </LI>
<LI><A HREF="c2670/c2670.html">c2670</A> : 12-bit ALU and controller </LI>
<LI><A HREF="c3540/c3540.html">c3540</A> : 8-bit ALU </LI>
<LI><A HREF="c5315/c5315.html">c5315</A> : 9-bit ALU </LI>
<LI><A HREF="c6288.html">c6288</A><FONT SIZE=2> </FONT>: 16x16 multiplier </LI>
<LI><A HREF="c7552/c7552.html">c7552</A> : 32-bit adder/comparator</LI></UL>
</UL>
<FONT SIZE=2><P> </FONT><B>ISCAS-89 Circuits:</P>
<UL>
<UL>
</B><LI><A HREF="s208_1.html">s208.1</A> : fractional multiplier </LI>
<LI><A HREF="s298.html">s298</A><FONT SIZE=2> </FONT>: traffic light controller </LI>
<LI><A HREF="s344.html">s344/s349</A><FONT SIZE=2> </FONT>: 4x4 add-shift multiplier</LI></UL>
</UL>
<B><P> 74X-Series Circuits:</P>
<UL>
<UL>
</B><LI><A HREF="74182.html">74182</A> : 4-bit carry-lookahead generator </LI>
<LI><A HREF="74283.html">74283</A> : 4-bit adder </LI>
<LI><A HREF="74181.html">74181</A> : 4-bit ALU </LI>
<LI><A HREF="74L85.html">74L85</A> : 4-bit magnitude comparator</LI></UL>
</UL>
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<p>Acknowledgement: The reverse engineering work was carried out
at the University of Michigan by Mark Hansen, Hakan Yalcin,
and John Hayes. They would like to thank Hyungwon Kim
for his assistance in constructing some of the Verilog models, as
well as Hussain Al-Asaad and Jonathan Hauke for checking the models.
Thanks are also due to Delphi Delco Electronics Systems, the National
Science Foundation (under Grant No. MIP-9503463), and the
Semiconductor Research Corporation for supporting various
portions of the research contributing to this effort.<p>
<FONT SIZE=2><P> </P>
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> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 | # 10 inputs # 1 outputs # 8 D-type flipflops # 38 inverters # 66 gates (21 ANDs + 15 NANDs + 14 ORs + 16 NORs) INPUT(P.0) INPUT(C.8) INPUT(C.7) INPUT(C.6) INPUT(C.5) INPUT(C.4) INPUT(C.3) INPUT(C.2) INPUT(C.1) INPUT(C.0) OUTPUT(Z) X.4 = DFF(I12) X.3 = DFF(I13) X.2 = DFF(I14) X.1 = DFF(I15) X.8 = DFF(I110) X.7 = DFF(I111) X.6 = DFF(I112) X.5 = DFF(I113) I73.1 = NOT(I69) I73.2 = NOT(X.3) I7.1 = NOT(I66) I7.2 = NOT(X.2) I88.1 = NOT(X.1) I88.2 = NOT(P.0) I48 = NOT(P.0) I49 = NOT(X.4) I50 = NOT(X.3) I68 = NOT(I69) I105.1 = NOT(I163) I105.2 = NOT(X.6) I182.1 = NOT(X.5) I182.2 = NOT(I1.2) I148 = NOT(X.7) I149 = NOT(X.6) I161 = NOT(I162) I164 = NOT(I163) I212 = NOT(P.0) I213 = NOT(X.1) I214 = NOT(X.2) I215 = NOT(X.3) I216 = NOT(X.4) I225 = NOT(I224) I240 = NOT(P.0) I241 = NOT(X.5) I242 = NOT(X.6) I243 = NOT(X.7) I244 = NOT(X.8) I252 = NOT(I251) I282 = NOT(P.2) I283 = NOT(P.3) I286 = NOT(C.2) I287 = NOT(C.3) I306 = NOT(P.6) I307 = NOT(P.7) I310 = NOT(C.6) I311 = NOT(C.7) I73.3 = AND(I69, I73.2) I73.4 = AND(X.3, I73.1) I7.3 = AND(I66, I7.2) I7.4 = AND(X.2, I7.1) I88.3 = AND(X.1, I88.2) I88.4 = AND(P.0, I88.1) I105.3 = AND(I163, I105.2) I105.4 = AND(X.6, I105.1) I182.3 = AND(X.5, I182.2) I182.4 = AND(I1.2, I182.1) I191.1 = AND(I164, X.6) I1.2 = AND(I2.1, P.0) P.5 = AND(I209.1, I205.2) P.6 = AND(I209.1, I206.2) P.7 = AND(I209.1, I207.2) P.8 = AND(I209.1, I208.2) I295.1 = AND(P.1, C.1) I295.2 = AND(P.0, C.0) I319.1 = AND(P.5, C.5) I319.2 = AND(P.4, C.4) I270.3 = AND(P.8, C.8) I70.1 = OR(I68, X.4, I50) I13 = OR(I73.3, I73.4) I15 = OR(I88.3, I88.4) I95.1 = OR(I64, I50, I48) I167.1 = OR(I165, X.8, I148) I170.1 = OR(I165, X.7) I113 = OR(I182.3, I182.4) I188.1 = OR(I163, I149, I148) I291.1 = OR(I283, I287) I291.2 = OR(I282, I286) I315.1 = OR(I307, I311) I315.2 = OR(I306, I310) I270.2 = OR(I269.1, I269.2) Z = OR(I270.2, I270.3) I12 = NAND(I70.1, I62) I62 = NAND(I95.1, X.4) I64 = NAND(X.1, X.2) I66 = NAND(X.1, P.0) I110 = NAND(I167.1, I159) I111 = NAND(I170.1, I161) I159 = NAND(I188.1, X.8) I163 = NAND(X.5, I1.2) I165 = NAND(I164, X.6) I222 = NAND(I225, I214) I224 = NAND(I213, P.0) I249 = NAND(I252, I242) I251 = NAND(I241, P.0) I269.1 = NAND(I291.1, I291.2, I290) I269.2 = NAND(I315.1, I315.2, I314) I14 = NOR(I7.3, I7.4) I2.1 = NOR(I64, I49, I50) I69 = NOR(I64, I48) I112 = NOR(I105.3, I105.4) I162 = NOR(I148, I191.1) P.1 = NOR(I212, I213) P.2 = NOR(I214, I224) P.3 = NOR(I215, I222) P.4 = NOR(X.3, I222, I216) I209.1 = NOR(X.4, X.2, X.3, X.1) I205.2 = NOR(I240, I241) I206.2 = NOR(I242, I251) I207.2 = NOR(I243, I249) I208.2 = NOR(X.7, I249, I244) I290 = NOR(I295.1, I295.2) I314 = NOR(I319.1, I319.2) |
Added s208.1.tests.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 | 0 000000000 11 t1 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 01 (extra for tst->m1b) 1 100000000 00 0 000000000 11 t2 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 1 010000000 00 0 000000000 11 t3 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 1 001000000 00 0 000000000 11 t4 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 1 000100000 00 0 000000000 11 t5 0 000000000 10 0 000000000 10 0 000000000 10 1 000010000 00 0 000000000 11 t6 0 000000000 10 0 000000000 10 1 000001000 00 0 000000000 11 t7 0 000000000 10 1 000000100 00 1 000000010 00 t8 1 000000001 00 t9 0 000000000 10 t10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 1 111111110 00 0 000000000 10 t11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 1 000000000 00 1 011111110 00 0 000000000 10 t12 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 1 000000000 00 1 101111110 00 0 000000000 11 t13 0 000000000 10 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 1 000000000 00 1 110111110 00 0 000000000 11 t14 0 000000000 11 0 000000000 10 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 1 000000000 00 1 111011110 00 0 000000000 11 t15 0 000000000 11 0 000000000 11 0 000000000 10 0 000000000 11 0 000000000 11 0 000000000 11 1 000000000 00 1 111101110 00 0 000000000 11 t16 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 10 0 000000000 11 0 000000000 11 1 000000000 00 1 111110110 00 0 000000000 11 t17 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 10 0 000000000 11 1 000000000 00 1 111111010 00 1 111111100 00 t18 0 000000000 11 t19 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 11 0 000000000 10 0 000000000 10 1 100000000 00 0 000000000 10 t20 0 000000000 11 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 11 0 000000000 10 1 010000000 00 0 000000000 10 t21 0 000000000 10 0 000000000 11 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 11 1 001000000 00 0 000000000 11 t22 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 100000000 00 0 000000000 11 t23 0 000000000 10 0 000000000 10 0 000000000 10 0 000000000 10 0 000100000 00 0 000000000 11 t24 0 000000000 10 0 000000000 10 0 000000000 10 0 000010000 00 0 000000000 11 t25 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000011 00 1 000000000 00 toggle all 1 000000010 01 0 000000000 10 t12 w/ f8=0 0 000000000 10 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 1 000000000 00 1 000000000 00 0 000000000 10 t13 w/ f7=0 0 000000000 10 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 1 000000000 00 1 000000000 00 0 000000000 10 t16 w/ f4=0 0 000000000 10 0 000000000 11 0 000000000 11 1 000000000 00 1 000000000 00 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 0 000000000 11 |
Added s208_1.html.
> > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>s208_1</TITLE> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080"> <B><FONT SIZE=5><P ALIGN="CENTER"><A NAME="pgfId_105045"></A>ISCAS-89 s208.1 Frequency Divider</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="s208.1.gif" WIDTH=433 HEIGHT=190></P> <B><P>Statistics: </B>10 inputs; 1 output; 112 gates;</P> <B><P>Function: </B>The functional model for the s208.1 frequency divider (also called a fractional multiplier) is shown in above. The control lines C determine if the P input pulse train is passed to the output Z, or if a frequency-divided version is passed. For every N input pulses on P, there are N*C/256 pulses on Z. If C equals 256, all pulses on P are passed to Z. </P> <B><P>Models:</P> <UL> </B><LI><A HREF="s208.1.isc">s208.1 ISCAS-89 netlist</A><B> </LI> </B><LI><A HREF="s208.1.v">s208.1 Verilog hierarchical structural model</A><B> </LI> </B><LI><A HREF="s208.1b.v">s208.1 Verilog hierarchical behavioral model</A> </LI> <LI><A HREF="s208.1.tests">s208.1 complete gate-level tests</A></LI></UL> <FONT SIZE=2><P> </P> </FONT><P> </P> <P><DIV></DIV></P> <FONT SIZE=2><P> </P></FONT></BODY> </HTML> |
Added s298.gif.
cannot compute difference between binary files
Added s298.html.
> > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>s298</TITLE> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-89 s298 Traffic Light Controller</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="s298.gif" WIDTH=433 HEIGHT=331></P> <B><P>Statistics: </B>3 inputs; 6 outputs; 133 gates;</P> <B><P>Function: </B>The high-level model of the s298 traffic light controller is shown above. After being reset by activating input I0, the controller has a repeating green-yellow-red light sequence that is 20 clock cycles in length. For the main direction of travel, the sequence is: 14 green, two yellow, and four red; for the opposing direction: 16 red, two green and two yellow. When the I1 input is pulsed, the controller changes to a repeating light pattern that is twice as fast, that is 10 clock cycles in length. If the I2 input is pulsed, the controller enters a blinking red/blinking yellow mode. M1-M6 are simple "random" combinational logic blocks that generate the six light values; M7 is a status logic block; M8 is a modulo-10 counter; and M9 controls the two mode lines.<DIV></DIV></P> <B><P>Models:</P> <UL> </B><LI><A HREF="s298.isc">s298 ISCAS-89 netlist</A><B> </LI> </B><LI><A HREF="s298.v">s298 Verilog hierarchical structural model</A><B> </LI> </B><LI><A HREF="s298b.v">s298 Verilog hierarchical behavioral model</A> </LI> <LI><A HREF="s298.tests">s298 complete gate-level tests</A></LI></UL> <FONT SIZE=2><P> </P> <P> </P></FONT></BODY> </HTML> |
Added s298.isc.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 | # 3 inputs # 6 outputs # 14 D-type flipflops # 44 inverters # 75 gates (31 ANDs + 9 NANDs + 16 ORs + 19 NORs) INPUT(G0) INPUT(G1) INPUT(G2) OUTPUT(G117) OUTPUT(G132) OUTPUT(G66) OUTPUT(G118) OUTPUT(G133) OUTPUT(G67) G10 = DFF(G29) G11 = DFF(G30) G12 = DFF(G34) G13 = DFF(G39) G14 = DFF(G44) G15 = DFF(G56) G16 = DFF(G86) G17 = DFF(G92) G18 = DFF(G98) G19 = DFF(G102) G20 = DFF(G107) G21 = DFF(G113) G22 = DFF(G119) G23 = DFF(G125) G28 = NOT(G130) G38 = NOT(G10) G40 = NOT(G13) G45 = NOT(G12) G46 = NOT(G11) G50 = NOT(G14) G51 = NOT(G23) G54 = NOT(G11) G55 = NOT(G13) G59 = NOT(G12) G60 = NOT(G22) G64 = NOT(G15) I155 = NOT(G16) G66 = NOT(I155) I158 = NOT(G17) G67 = NOT(I158) G76 = NOT(G10) G82 = NOT(G11) G87 = NOT(G16) G91 = NOT(G12) G93 = NOT(G17) G96 = NOT(G14) G99 = NOT(G18) G103 = NOT(G13) G108 = NOT(G112) G114 = NOT(G21) I210 = NOT(G18) G117 = NOT(I210) I213 = NOT(G19) G118 = NOT(I213) G120 = NOT(G124) G121 = NOT(G22) I221 = NOT(G2) G124 = NOT(I221) G126 = NOT(G131) G127 = NOT(G23) I229 = NOT(G0) G130 = NOT(I229) I232 = NOT(G1) G131 = NOT(I232) I235 = NOT(G20) G132 = NOT(I235) I238 = NOT(G21) G133 = NOT(I238) G26 = AND(G28, G50) G27 = AND(G51, G28) G31 = AND(G10, G45, G13) G32 = AND(G10, G11) G33 = AND(G38, G46) G35 = AND(G10, G11, G12) G36 = AND(G38, G45) G37 = AND(G46, G45) G42 = AND(G40, G41) G48 = AND(G45, G46, G10, G47) G49 = AND(G50, G51, G52) G57 = AND(G59, G11, G60, G61) G58 = AND(G64, G65) G62 = AND(G59, G11, G60, G61) G63 = AND(G64, G65) G74 = AND(G12, G14, G19) G75 = AND(G82, G91, G14) G88 = AND(G14, G87) G89 = AND(G103, G96) G90 = AND(G91, G103) G94 = AND(G93, G13) G95 = AND(G96, G13) G100 = AND(G99, G14, G12) G105 = AND(G103, G108, G104) G110 = AND(G108, G109) G111 = AND(G10, G112) G115 = AND(G114, G14) G122 = AND(G120, G121) G123 = AND(G124, G22) G128 = AND(G126, G127) G129 = AND(G131, G23) G24 = OR(G38, G46, G45, G40) G25 = OR(G38, G11, G12) G68 = OR(G11, G12, G13, G96) G69 = OR(G103, G18) G70 = OR(G103, G14) G71 = OR(G82, G12, G13) G72 = OR(G91, G20) G73 = OR(G103, G20) G77 = OR(G112, G103, G96, G19) G78 = OR(G108, G76) G79 = OR(G103, G14) G80 = OR(G11, G14) G81 = OR(G12, G13) G83 = OR(G11, G12, G13, G96) G84 = OR(G82, G91, G14) G85 = OR(G91, G96, G17) G41 = NAND(G12, G11, G10) G43 = NAND(G24, G25, G28) G52 = NAND(G13, G45, G46, G10) G65 = NAND(G59, G54, G22, G61) G97 = NAND(G83, G84, G85, G108) G101 = NAND(G68, G69, G70, G108) G106 = NAND(G77, G78) G109 = NAND(G71, G72, G73, G14) G116 = NAND(G79, G80, G81, G108) G29 = NOR(G10, G130) G30 = NOR(G31, G32, G33, G130) G34 = NOR(G35, G36, G37, G130) G39 = NOR(G42, G43) G44 = NOR(G48, G49, G53) G47 = NOR(G50, G40) G53 = NOR(G26, G27) G56 = NOR(G57, G58, G130) G61 = NOR(G14, G55) G86 = NOR(G88, G89, G90, G112) G92 = NOR(G94, G95, G97) G98 = NOR(G100, G101) G102 = NOR(G105, G106) G104 = NOR(G74, G75) G107 = NOR(G110, G111) G112 = NOR(G62, G63) G113 = NOR(G115, G116) G119 = NOR(G122, G123, G130) G125 = NOR(G128, G129, G130) |
Added s298.tests.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 | 000 000 000 001 001 001 001 001 001 001 001 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 001 001 001 001 001 000 100 100 100 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 |
Added s298.v.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 |
/****************************************************************************
* *
* VERILOG HIGH-LEVEL DESCRIPTION OF THE ISCAS-89 BENCHMARK CIRCUIT s298 *
* *
* Function: Traffic Light Controller *
* *
* Written by: Mark C. Hansen *
* *
* Last modified: Dec 05, 1997 *
* *
* Structural variation from gate level netlist only in that buffers are
* removed on primary I/O and inverters are minimized *
* *
****************************************************************************/
module Circuit298 (g0, g1, g2, g117, g132, g66, g118, g133, g67);
input g0, g1, g2;
output g117, g132, g66, g118, g133, g67;
wire [2:0] I;
wire [1:0] R, Y, G;
wire Clock;
assign
I[2:0] = {g2, g1, g0},
R[1:0] = {g118, g117},
Y[1:0] = {g133, g132},
G[1:0] = {g67, g66};
/* I[0] = Reset */
/* I[1] = Faster Cycle */
/* I[2] = Blink */
/* R[1:0] = Primary:Secondary Red Light */
/* Y[1:0] = Primary:Secondary Yellow Light */
/* G[1:0] = Primary:Secondary Green Light */
TopLevel298 Ckt298 (Clock, I, R, Y, G);
endmodule /* Circuit298 */
/*************************************************************************/
module TopLevel298 (Clock, I, R, Y, G);
input Clock;
input[2:0] I;
output[1:0] R, Y, G;
wire[13:0] Ff, FfB;
wire Blink, BlinkB;
wire I0B;
assign R[1] = Ff[8], R[0] = Ff[9], Y[1] = Ff[10], Y[0] = Ff[11],
G[1] = Ff[6], G[0] = Ff[7];
RedPrimary M1(Clock, Ff, FfB, BlinkB);
YellowPrimary M2(Clock, Ff, FfB, Blink, BlinkB);
GreenPrimary M3(Clock, Ff, FfB, Blink);
RedSecondary M4(Clock, Ff, FfB, Blink, BlinkB);
YellowSecondary M5(Clock, Ff, FfB, BlinkB);
GreenSecondary M6(Clock, Ff, FfB, BlinkB);
Status M7(Clock, I, I0B, Ff, FfB, Blink, BlinkB);
Counter M8(Clock, I, I0B, Ff, FfB);
Mode M9(Clock, I, Ff, FfB);
endmodule /* TopLevel298 */
/*************************************************************************/
module RedPrimary (Clock, Ff, FfB, BlinkB);
input Clock;
inout[13:0] Ff, FfB;
input BlinkB;
wire L116, L117, L118, L132, L103, L26;
or L116g(L116, Ff[1], Ff[2], Ff[3], FfB[4]);
or L117g(L117, FfB[3], Ff[8]);
or L118g(L118, FfB[3], Ff[4]);
nand L132g(L132, BlinkB, L116, L117, L118);
and L103g(L103, Ff[2], Ff[4], FfB[8]);
nor L26g(L26, L103, L132);
DFF DFFRP(L26, Clock, Ff[8], FfB[8]);
endmodule /* RedPrimary */
/*************************************************************************/
module YellowPrimary (Clock, Ff, FfB, Blink, BlinkB);
input Clock;
inout[13:0] Ff, FfB;
input Blink, BlinkB;
wire L30, L106, L107, L108, L119, L120, L121;
or L119g(L119, FfB[1], Ff[2], Ff[3]);
or L120g(L120, FfB[2], Ff[10]);
or L121g(L121, FfB[3], Ff[10]);
nand L107g(L107, L119, L120, L121, Ff[4]);
and L106g(L106, BlinkB, L107);
and L108g(L108, Blink, Ff[0]);
nor L30g(L30, L106, L108);
DFF DFFYP(L30, Clock, Ff[10], FfB[10]);
endmodule /* YellowPrimary */
/*************************************************************************/
/*************************************************************************/
module GreenPrimary (Clock, Ff, FfB, Blink);
input Clock;
inout[13:0] Ff, FfB;
input Blink;
wire L22, L98, L99, L100;
and L98g(L98, Ff[4], FfB[6]);
and L99g(L99, FfB[3], FfB[4]);
and L100g(L100, FfB[2], FfB[3]);
nor L22g(L22, Blink, L98, L99, L100);
DFF DFFRP(L22, Clock, Ff[6], FfB[6]);
endmodule /* GreenPrimary */
/*************************************************************************/
/*************************************************************************/
module RedSecondary (Clock, Ff, FfB, Blink, BlinkB);
input Clock;
inout[13:0] Ff, FfB;
input Blink, BlinkB;
wire L28, L96, L97, L104, L105, L122, L123, L133;
and L96g(L96, Ff[2], Ff[4], Ff[9]);
and L97g(L97, FfB[1], FfB[2], Ff[4]);
nor L105g(L105, L96, L97);
and L104g(L104, BlinkB, L105, FfB[3]);
or L122g(L122, FfB[3], FfB[4], Ff[9], Blink);
or L123g(L123, BlinkB, FfB[0]);
nand L133g(L133, L122, L123);
nor L28g(L28, L104, L133);
DFF DFFRS(L28, Clock, Ff[9], FfB[9]);
endmodule /* RedSecondary */
/*************************************************************************/
/*************************************************************************/
module YellowSecondary (Clock, Ff, FfB, BlinkB);
input Clock;
inout[13:0] Ff, FfB;
input BlinkB;
wire L32, L109, L124, L125, L126, L134;
or L124g(L124, FfB[3], Ff[4]);
or L125g(L125, Ff[1], Ff[4]);
or L126g(L126, Ff[2], Ff[3]);
nand L134g(L134, BlinkB, L124, L125, L126);
and L109g(L109, Ff[4], FfB[11]);
nor L32g(L32, L109, L134);
DFF DFFYS(L32, Clock, Ff[11], FfB[11]);
endmodule /* YellowSecondary */
/*************************************************************************/
/*************************************************************************/
module GreenSecondary (Clock, Ff, FfB, BlinkB);
input Clock;
inout[13:0] Ff, FfB;
input BlinkB;
wire L24, L101, L102, L127, L128, L129, L131;
or L127g(L127, Ff[1], Ff[2], Ff[3], FfB[4]);
or L128g(L128, FfB[1], FfB[2], Ff[4]);
or L129g(L129, FfB[2], FfB[4], Ff[7]);
nand L131g(L131, BlinkB, L127, L128, L129);
and L101g(L101, Ff[3], FfB[7]);
and L102g(L102, Ff[3], FfB[4]);
nor L24g(L24, L101, L102, L131);
DFF DFFGS(L24, Clock, Ff[7], FfB[7]);
endmodule /* GreenSecondary */
/*************************************************************************/
/*************************************************************************/
module Status (Clock, I, I0B, Ff, FfB, Blink, BlinkB);
input Clock;
input[2:0] I;
output I0B;
inout[13:0] Ff, FfB;
output Blink, BlinkB;
wire L18, L20, L76, L77, L86, L87, L88;
wire L90, L91, L92, L93, L94, L95, L135;
not I0Bg(I0B, I[0]);
nor L87g(L87, FfB[3], FfB[4]);
and L86g(L86, L87, Ff[0], FfB[1], FfB[2]);
nand L89g(L89, Ff[0], FfB[1], FfB[2], Ff[3]);
and L88g(L88, L89, FfB[4], FfB[13]);
and L76g(L76, I0B, FfB[4]);
and L77g(L77, I0B, FfB[13]);
nor L135g(L135, L76, L77);
nor L18g(L18, L86, L88, L135);
DFF DFFS1(L18, Clock, Ff[4], FfB[4]);
nor L91g(L91, FfB[3], Ff[4]);
nand L93g(L93, L91, FfB[1], FfB[2], Ff[12]);
and L90g(L90, L91, Ff[1], FfB[2], FfB[12]);
and L92g(L92, L93, FfB[5]);
nor L20g(L20, I[0], L90, L92);
DFF DFFS2(L20, Clock, Ff[5], FfB[5]);
and L94g(L94, L91, Ff[1], FfB[2], FfB[12]);
and L95g(L95, L93, FfB[5]);
nor Blinkg(Blink, L94, L95);
not BlinkBg(BlinkB, Blink);
endmodule /* Status */
/*************************************************************************/
/*************************************************************************/
module Counter (Clock, I, I0B, Ff, FfB);
/* Mod 10 Counter 0000-1001; Reset by I[0]/I0B */
input Clock;
input[2:0] I;
input I0B;
inout[13:0] Ff, FfB;
wire L10, L12, L14, L16, L78, L79, L80, L81, L82, L83, L84, L85;
wire L114, L115, L130;
/*bit 0 */
nor L10g(L10, I[0], Ff[0]);
DFF DFFC0(L10, Clock, Ff[0], FfB[0]);
/*bit 1 */
and L78g(L78, Ff[0], FfB[2], Ff[3]);
and L79g(L79, Ff[0], Ff[1]);
and L80g(L80, FfB[0], FfB[1]);
nor L12g(L12, I[0], L78, L79, L80);
DFF DFFC1(L12, Clock, Ff[1], FfB[1]);
/*bit 2 */
and L81g(L81, Ff[0], Ff[1], Ff[2]);
and L82g(L82, FfB[0], FfB[2]);
and L83g(L83, FfB[1], FfB[2]);
nor L14g(L14, I[0], L81, L82, L83);
DFF DFFC2(L14, Clock, Ff[2], FfB[2]);
/*bit 3 */
nand L85g(L85, Ff[0], Ff[1], Ff[2]);
and L84g(L84, L85, FfB[3]);
or L114g(L114, FfB[0], FfB[1], FfB[2], FfB[3]);
or L115g(L115, FfB[0], Ff[1], Ff[2]);
nand L130g(L130, I0B, L114, L115);
nor L16g(L16, L84, L130);
DFF DFFC3(L16, Clock, Ff[3], FfB[3]);
endmodule /* Counter */
/*************************************************************************/
/*************************************************************************/
module Mode (Clock, I, Ff, FfB);
input Clock;
input[2:0] I;
inout[13:0] Ff, FfB;
wire I1B, I2B, L34, L36, L110, L111, L112, L113;
/* Cycle Short/Long */
not I2Bg(I2B, I[2]);
and L110g(L110, I2B, FfB[12]);
and L111g(L111, I[2], Ff[12]);
nor L34g(L34, I[0], L110, L111);
DFF DFFSpeed(L34, Clock, Ff[12], FfB[12]);
/* Blink */
not I1Bg(I1B, I[1]);
and L112g(L112, I1B, FfB[13]);
and L113g(L113, I[1], Ff[13]);
nor L36g(L36, I[0], L112, L113);
DFF DFFBlink(L36, Clock, Ff[13], FfB[13]);
endmodule /* Mode */
/*************************************************************************/
module DFF (D, Clock, Q, QB);
input D, Clock;
output Q, QB;
reg Q, QB;
always @(posedge Clock) begin
#10 Q = D;
#10 QB = ~Q;
end
endmodule /* DFF */
/*************************************************************************/
|
Added s344.gif.
cannot compute difference between binary files
Added s344.html.
> > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 | <HTML> <HEAD> <META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=windows-1252"> <META NAME="Generator" CONTENT="Microsoft Word 97"> <TITLE>s344</TITLE> <META NAME="Template" CONTENT="C:\PROGRAM FILES\MICROSOFT OFFICE\OFFICE\html.dot"> </HEAD> <BODY LINK="#0000ff" VLINK="#800080"> <B><FONT SIZE=5><P ALIGN="CENTER">ISCAS-89 s344/s349 4x4 Add-Shift Multiplier</P> </B></FONT><P ALIGN="CENTER"><IMG SRC="s344.gif" WIDTH=704 HEIGHT=448></P> <B><P>Statistics: </B>9 inputs; 11 outputs; 175/176 gates;</P> <B><P>Function: </B>The high-level functional model for the s344/s349 4-bit multiplier is shown above. It consists of 16 multiplexers, eight D-type flip-flops, four D-type flip-flops with reset, three T -type flip-flops, one 4-bit full adder, and one 4-bit AND. The circuit is controlled by a 3-bit counter, that when reset by the Start input, counts from 0 to 5. During a count of 0, the A input is loaded; between the counts 1-4, an add and shift procedure forms the multiplication product; and at a count of 5, the Ready line goes to 1, and holds the counter state fixed.<FONT SIZE=2> </P> </FONT><P>s344 and s349 have the same function, but have slightly different implementations.</P> <B><P>Models:</P> <UL> </B><LI><A HREF="s344.isc">s344 ISCAS-89 netlist</A><B> </LI> </B><LI><A HREF="s349.isc">s349 ISCAS-89 netlist</A> </LI> <LI><A HREF="s349.v">s349 Verilog hierarchical structural model</A><B> </LI> </B><LI><A HREF="s344b.v">s344/s349 Verilog hierarchical behavioral model</A> </LI> <LI><A HREF="s344.tests">s344/s349 complete gate-level tests</A></LI></UL> <FONT SIZE=2><P> </P> <P> </P></FONT></BODY> </HTML> |
Added s344.isc.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 | # 9 inputs # 11 outputs # 15 D-type flipflops # 59 inverters # 101 gates (44 ANDs + 18 NANDs + 9 ORs + 30 NORs) INPUT(START) INPUT(B0) INPUT(B1) INPUT(B2) INPUT(B3) INPUT(A0) INPUT(A1) INPUT(A2) INPUT(A3) OUTPUT(P4) OUTPUT(P5) OUTPUT(P6) OUTPUT(P7) OUTPUT(P0) OUTPUT(P1) OUTPUT(P2) OUTPUT(P3) OUTPUT(CNTVCON2) OUTPUT(CNTVCO2) OUTPUT(READY) CT2 = DFF(CNTVG3VD) CT1 = DFF(CNTVG2VD) CT0 = DFF(CNTVG1VD) ACVQN3 = DFF(ACVG4VD1) ACVQN2 = DFF(ACVG3VD1) ACVQN1 = DFF(ACVG2VD1) ACVQN0 = DFF(ACVG1VD1) MRVQN3 = DFF(MRVG4VD) MRVQN2 = DFF(MRVG3VD) MRVQN1 = DFF(MRVG2VD) MRVQN0 = DFF(MRVG1VD) AX3 = DFF(AM3) AX2 = DFF(AM2) AX1 = DFF(AM1) AX0 = DFF(AM0) CNTVG3VQN = NOT(CT2) CNTVG2VQN = NOT(CT1) CNTVG1VQN = NOT(CT0) P7 = NOT(ACVQN3) P6 = NOT(ACVQN2) P5 = NOT(ACVQN1) P4 = NOT(ACVQN0) P3 = NOT(MRVQN3) P2 = NOT(MRVQN2) P1 = NOT(MRVQN1) P0 = NOT(MRVQN0) CNTVCON0 = NOT(CT0) CT1N = NOT(CT1) ACVPCN = NOT(START) CNTVCO0 = NOT(CNTVG1VQN) AMVS0N = NOT(INIT) READY = NOT(READYN) BMVS0N = NOT(READYN) AMVG5VS0P = NOT(AMVS0N) AMVG4VS0P = NOT(AMVS0N) AMVG3VS0P = NOT(AMVS0N) AMVG2VS0P = NOT(AMVS0N) AD0 = NOT(AD0N) AD1 = NOT(AD1N) AD2 = NOT(AD2N) AD3 = NOT(AD3N) CNTVG3VD1 = NOT(CNTVCON1) CNTVG1VD1 = NOT(READY) BMVG5VS0P = NOT(BMVS0N) BMVG4VS0P = NOT(BMVS0N) BMVG3VS0P = NOT(BMVS0N) BMVG2VS0P = NOT(BMVS0N) SMVS0N = NOT(ADSH) MRVSHLDN = NOT(ADSH) ADDVC1 = NOT(ADDVG1VCN) SMVG5VS0P = NOT(SMVS0N) SMVG4VS0P = NOT(SMVS0N) SMVG3VS0P = NOT(SMVS0N) SMVG2VS0P = NOT(SMVS0N) CNTVG1VZ = NOT(CNTVG1VZ1) AM3 = NOT(AMVG5VX) AM2 = NOT(AMVG4VX) AM1 = NOT(AMVG3VX) AM0 = NOT(AMVG2VX) S0 = NOT(ADDVG1VP) BM3 = NOT(BMVG5VX) BM2 = NOT(BMVG4VX) BM1 = NOT(BMVG3VX) BM0 = NOT(BMVG2VX) ADDVC2 = NOT(ADDVG2VCN) S1 = NOT(ADDVG2VSN) ADDVC3 = NOT(ADDVG3VCN) S2 = NOT(ADDVG3VSN) SM0 = NOT(SMVG2VX) CO = NOT(ADDVG4VCN) S3 = NOT(ADDVG4VSN) SM1 = NOT(SMVG3VX) SM3 = NOT(SMVG5VX) SM2 = NOT(SMVG4VX) AMVG5VG1VAD1NF = AND(AMVS0N, AX3) AMVG4VG1VAD1NF = AND(AMVS0N, AX2) AMVG3VG1VAD1NF = AND(AMVS0N, AX1) AMVG2VG1VAD1NF = AND(AMVS0N, AX0) BMVG5VG1VAD1NF = AND(BMVS0N, P3) BMVG4VG1VAD1NF = AND(BMVS0N, P2) BMVG3VG1VAD1NF = AND(BMVS0N, P1) BMVG2VG1VAD1NF = AND(BMVS0N, P0) AMVG5VG1VAD2NF = AND(AMVG5VS0P, A3) AMVG4VG1VAD2NF = AND(AMVG4VS0P, A2) AMVG3VG1VAD2NF = AND(AMVG3VS0P, A1) AMVG2VG1VAD2NF = AND(AMVG2VS0P, A0) ADDVG2VCNVAD1NF = AND(AD1, P5) ADDVG3VCNVAD1NF = AND(AD2, P6) ADDVG4VCNVAD1NF = AND(AD3, P7) MRVG3VDVAD1NF = AND(ADSH, P3) MRVG2VDVAD1NF = AND(ADSH, P2) MRVG1VDVAD1NF = AND(ADSH, P1) BMVG5VG1VAD2NF = AND(BMVG5VS0P, B3) BMVG4VG1VAD2NF = AND(BMVG4VS0P, B2) BMVG3VG1VAD2NF = AND(BMVG3VS0P, B1) BMVG2VG1VAD2NF = AND(BMVG2VS0P, B0) SMVG5VG1VAD1NF = AND(SMVS0N, P7) SMVG4VG1VAD1NF = AND(SMVS0N, P6) SMVG3VG1VAD1NF = AND(SMVS0N, P5) SMVG2VG1VAD1NF = AND(SMVS0N, P4) ADDVG2VCNVAD4NF = AND(ADDVC1, AD1, P5) ADDVG2VCNVAD2NF = AND(ADDVC1, ADDVG2VCNVOR1NF) MRVG4VDVAD1NF = AND(ADSH, S0) MRVG4VDVAD2NF = AND(MRVSHLDN, BM3) MRVG3VDVAD2NF = AND(MRVSHLDN, BM2) MRVG2VDVAD2NF = AND(MRVSHLDN, BM1) MRVG1VDVAD2NF = AND(MRVSHLDN, BM0) ADDVG2VCNVAD3NF = AND(ADDVG2VCNVOR2NF, ADDVG2VCN) ADDVG3VCNVAD4NF = AND(ADDVC2, AD2, P6) ADDVG3VCNVAD2NF = AND(ADDVC2, ADDVG3VCNVOR1NF) ADDVG3VCNVAD3NF = AND(ADDVG3VCNVOR2NF, ADDVG3VCN) SMVG2VG1VAD2NF = AND(SMVG2VS0P, S1) ADDVG4VCNVAD4NF = AND(ADDVC3, AD3, P7) ADDVG4VCNVAD2NF = AND(ADDVC3, ADDVG4VCNVOR1NF) ADDVG4VCNVAD3NF = AND(ADDVG4VCNVOR2NF, ADDVG4VCN) SMVG3VG1VAD2NF = AND(SMVG3VS0P, S2) SMVG5VG1VAD2NF = AND(SMVG5VS0P, CO) SMVG4VG1VAD2NF = AND(SMVG4VS0P, S3) ADDVG1VPVOR1NF = OR(AD0, P4) ADDVG2VCNVOR1NF = OR(AD1, P5) ADDVG3VCNVOR1NF = OR(AD2, P6) ADDVG4VCNVOR1NF = OR(AD3, P7) CNTVG3VG2VOR1NF = OR(CT2, CNTVG3VD1) CNTVG2VG2VOR1NF = OR(CT1, CNTVG2VD1) ADDVG2VCNVOR2NF = OR(ADDVC1, AD1, P5) ADDVG3VCNVOR2NF = OR(ADDVC2, AD2, P6) ADDVG4VCNVOR2NF = OR(ADDVC3, AD3, P7) READYN = NAND(CT0, CT1N, CT2) AD0N = NAND(P0, AX0) AD1N = NAND(P0, AX1) AD2N = NAND(P0, AX2) AD3N = NAND(P0, AX3) CNTVCON1 = NAND(CT1, CNTVCO0) CNTVCON2 = NAND(CT2, CNTVCO1) ADDVG1VCN = NAND(AD0, P4) CNTVG3VZ1 = NAND(CT2, CNTVG3VD1) CNTVG2VZ1 = NAND(CT1, CNTVG2VD1) CNTVG1VZ1 = NAND(CT0, CNTVG1VD1) ADDVG1VP = NAND(ADDVG1VPVOR1NF, ADDVG1VCN) CNTVG3VZ = NAND(CNTVG3VG2VOR1NF, CNTVG3VZ1) CNTVG2VZ = NAND(CNTVG2VG2VOR1NF, CNTVG2VZ1) ACVG1VD1 = NAND(ACVPCN, SM0) ACVG2VD1 = NAND(ACVPCN, SM1) ACVG4VD1 = NAND(ACVPCN, SM3) ACVG3VD1 = NAND(ACVPCN, SM2) INIT = NOR(CT0, CT1, CT2) CNTVCO1 = NOR(CNTVG2VQN, CNTVCON0) CNTVCO2 = NOR(CNTVG3VQN, CNTVCON1) ADSH = NOR(READY, INIT) CNTVG2VD1 = NOR(READY, CNTVCON0) AMVG5VX = NOR(AMVG5VG1VAD2NF, AMVG5VG1VAD1NF) AMVG4VX = NOR(AMVG4VG1VAD2NF, AMVG4VG1VAD1NF) AMVG3VX = NOR(AMVG3VG1VAD2NF, AMVG3VG1VAD1NF) AMVG2VX = NOR(AMVG2VG1VAD2NF, AMVG2VG1VAD1NF) BMVG5VX = NOR(BMVG5VG1VAD2NF, BMVG5VG1VAD1NF) BMVG4VX = NOR(BMVG4VG1VAD2NF, BMVG4VG1VAD1NF) BMVG3VX = NOR(BMVG3VG1VAD2NF, BMVG3VG1VAD1NF) BMVG2VX = NOR(BMVG2VG1VAD2NF, BMVG2VG1VAD1NF) CNTVG3VD = NOR(CNTVG3VZ, START) CNTVG2VD = NOR(CNTVG2VZ, START) CNTVG1VD = NOR(CNTVG1VZ, START) ADDVG2VCN = NOR(ADDVG2VCNVAD2NF, ADDVG2VCNVAD1NF) MRVG4VD = NOR(MRVG4VDVAD2NF, MRVG4VDVAD1NF) MRVG3VD = NOR(MRVG3VDVAD2NF, MRVG3VDVAD1NF) MRVG2VD = NOR(MRVG2VDVAD2NF, MRVG2VDVAD1NF) MRVG1VD = NOR(MRVG1VDVAD2NF, MRVG1VDVAD1NF) ADDVG2VSN = NOR(ADDVG2VCNVAD4NF, ADDVG2VCNVAD3NF) ADDVG3VCN = NOR(ADDVG3VCNVAD2NF, ADDVG3VCNVAD1NF) ADDVG3VSN = NOR(ADDVG3VCNVAD4NF, ADDVG3VCNVAD3NF) SMVG2VX = NOR(SMVG2VG1VAD2NF, SMVG2VG1VAD1NF) ADDVG4VCN = NOR(ADDVG4VCNVAD2NF, ADDVG4VCNVAD1NF) ADDVG4VSN = NOR(ADDVG4VCNVAD4NF, ADDVG4VCNVAD3NF) SMVG3VX = NOR(SMVG3VG1VAD2NF, SMVG3VG1VAD1NF) SMVG5VX = NOR(SMVG5VG1VAD2NF, SMVG5VG1VAD1NF) SMVG4VX = NOR(SMVG4VG1VAD2NF, SMVG4VG1VAD1NF) |
Added s344.tests.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 | 1:111111111 2:011111111 3:011111111 4:011111111 5:011111111 6:011111111 7:111111111 8:010111101 9:011111111 10:011111111 11:011111111 12:011111111 13:011111111 14:111111111 15:000000000 16:111111111 17:000010111 18:011111111 19:011111111 20:011111111 21:011111111 22:011111111 23:111111111 24:011111011 25:011111111 26:011111111 27:011111111 28:011111111 29:111111111 30:011111110 31:011111111 32:011111111 33:111111111 34:011011111 35:011111111 36:011111111 37:011111111 38:111111111 39:011101111 40:011111111 41:011111111 42:011111111 43:011111111 44:011111111 45:011111111 |
Added s349.isc.
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 | # 9 inputs # 11 outputs # 15 D-type flipflops # 57 inverters # 104 gates (44 ANDs + 19 NANDs + 10 ORs + 31 NORs) INPUT(START) INPUT(B0) INPUT(B1) INPUT(B2) INPUT(B3) INPUT(A0) INPUT(A1) INPUT(A2) INPUT(A3) OUTPUT(CNTVCO2) OUTPUT(CNTVCON2) OUTPUT(READY) OUTPUT(P0) OUTPUT(P1) OUTPUT(P2) OUTPUT(P3) OUTPUT(P4) OUTPUT(P5) OUTPUT(P6) OUTPUT(P7) CT2 = DFF(CNTVG3VD) CT1 = DFF(CNTVG2VD) CT0 = DFF(CNTVG1VD) ACVQN3 = DFF(ACVG4VD1) ACVQN2 = DFF(ACVG3VD1) ACVQN1 = DFF(ACVG2VD1) ACVQN0 = DFF(ACVG1VD1) MRVQN3 = DFF(MRVG4VD) MRVQN2 = DFF(MRVG3VD) MRVQN1 = DFF(MRVG2VD) MRVQN0 = DFF(MRVG1VD) AX3 = DFF(AM3) AX2 = DFF(AM2) AX1 = DFF(AM1) AX0 = DFF(AM0) READY = NOT(READYN) CT1N = NOT(CT1) CNTVG3VQN = NOT(CT2) CNTVG2VQN = NOT(CT1) CNTVCO0 = NOT(CNTVG1VQN) CNTVCON0 = NOT(CT0) CNTVG1VQN = NOT(CT0) CNTVG1VD1 = NOT(READY) S3 = NOT(ADDVG4VSN) CO = NOT(ADDVG4VCN) S2 = NOT(ADDVG3VSN) ADDVC3 = NOT(ADDVG3VCN) S1 = NOT(ADDVG2VSN) ADDVC2 = NOT(ADDVG2VCN) ADDVC1 = NOT(ADDVG1VCN) S0 = NOT(ADDVG1VP) AD0 = NOT(AD0N) AD1 = NOT(AD1N) AD2 = NOT(AD2N) AD3 = NOT(AD3N) ACVPCN = NOT(START) P7 = NOT(ACVQN3) P6 = NOT(ACVQN2) P5 = NOT(ACVQN1) P4 = NOT(ACVQN0) SMVG5VS0P = NOT(SMVS0N) SM3 = NOT(SMVG5VX) SMVG4VS0P = NOT(SMVS0N) SM2 = NOT(SMVG4VX) SMVG3VS0P = NOT(SMVS0N) SM1 = NOT(SMVG3VX) SMVG2VS0P = NOT(SMVS0N) SM0 = NOT(SMVG2VX) SMVS0N = NOT(ADSH) MRVSHLDN = NOT(ADSH) P3 = NOT(MRVQN3) P2 = NOT(MRVQN2) P1 = NOT(MRVQN1) P0 = NOT(MRVQN0) BMVG5VS0P = NOT(BMVS0N) BM3 = NOT(BMVG5VX) BMVG4VS0P = NOT(BMVS0N) BM2 = NOT(BMVG4VX) BMVG3VS0P = NOT(BMVS0N) BM1 = NOT(BMVG3VX) BMVG2VS0P = NOT(BMVS0N) BM0 = NOT(BMVG2VX) BMVS0N = NOT(READYN) AMVG5VS0P = NOT(AMVS0N) AM3 = NOT(AMVG5VX) AMVG4VS0P = NOT(AMVS0N) AM2 = NOT(AMVG4VX) AMVG3VS0P = NOT(AMVS0N) AM1 = NOT(AMVG3VX) AMVG2VS0P = NOT(AMVS0N) AM0 = NOT(AMVG2VX) AMVS0N = NOT(INIT) ADDVG4VCNVAD4NF = AND(ADDVC3, AD3, P7) ADDVG4VCNVAD3NF = AND(ADDVG4VCNVOR2NF, ADDVG4VCN) ADDVG4VCNVAD2NF = AND(ADDVC3, ADDVG4VCNVOR1NF) ADDVG4VCNVAD1NF = AND(AD3, P7) ADDVG3VCNVAD4NF = AND(ADDVC2, AD2, P6) ADDVG3VCNVAD3NF = AND(ADDVG3VCNVOR2NF, ADDVG3VCN) ADDVG3VCNVAD2NF = AND(ADDVC2, ADDVG3VCNVOR1NF) ADDVG3VCNVAD1NF = AND(AD2, P6) ADDVG2VCNVAD4NF = AND(ADDVC1, AD1, P5) ADDVG2VCNVAD3NF = AND(ADDVG2VCNVOR2NF, ADDVG2VCN) ADDVG2VCNVAD2NF = AND(ADDVC1, ADDVG2VCNVOR1NF) ADDVG2VCNVAD1NF = AND(AD1, P5) SMVG5VG1VAD2NF = AND(SMVG5VS0P, CO) SMVG5VG1VAD1NF = AND(SMVS0N, P7) SMVG4VG1VAD2NF = AND(SMVG4VS0P, S3) SMVG4VG1VAD1NF = AND(SMVS0N, P6) SMVG3VG1VAD2NF = AND(SMVG3VS0P, S2) SMVG3VG1VAD1NF = AND(SMVS0N, P5) SMVG2VG1VAD2NF = AND(SMVG2VS0P, S1) SMVG2VG1VAD1NF = AND(SMVS0N, P4) MRVG4VDVAD2NF = AND(MRVSHLDN, BM3) MRVG4VDVAD1NF = AND(ADSH, S0) MRVG3VDVAD2NF = AND(MRVSHLDN, BM2) MRVG3VDVAD1NF = AND(ADSH, P3) MRVG2VDVAD2NF = AND(MRVSHLDN, BM1) MRVG2VDVAD1NF = AND(ADSH, P2) MRVG1VDVAD2NF = AND(MRVSHLDN, BM0) MRVG1VDVAD1NF = AND(ADSH, P1) BMVG5VG1VAD2NF = AND(BMVG5VS0P, B3) BMVG5VG1VAD1NF = AND(BMVS0N, P3) BMVG4VG1VAD2NF = AND(BMVG4VS0P, B2) BMVG4VG1VAD1NF = AND(BMVS0N, P2) BMVG3VG1VAD2NF = AND(BMVG3VS0P, B1) BMVG3VG1VAD1NF = AND(BMVS0N, P1) BMVG2VG1VAD2NF = AND(BMVG2VS0P, B0) BMVG2VG1VAD1NF = AND(BMVS0N, P0) AMVG5VG1VAD2NF = AND(AMVG5VS0P, A3) AMVG5VG1VAD1NF = AND(AMVS0N, AX3) AMVG4VG1VAD2NF = AND(AMVG4VS0P, A2) AMVG4VG1VAD1NF = AND(AMVS0N, AX2) AMVG3VG1VAD2NF = AND(AMVG3VS0P, A1) AMVG3VG1VAD1NF = AND(AMVS0N, AX1) AMVG2VG1VAD2NF = AND(AMVG2VS0P, A0) AMVG2VG1VAD1NF = AND(AMVS0N, AX0) CNTVG3VG2VOR1NF = OR(CT2, CNTVG3VD1) CNTVG2VG2VOR1NF = OR(CT1, CNTVG2VD1) CNTVG1VG2VOR1NF = OR(CT0, CNTVG1VD1) ADDVG4VCNVOR2NF = OR(ADDVC3, AD3, P7) ADDVG4VCNVOR1NF = OR(AD3, P7) ADDVG3VCNVOR2NF = OR(ADDVC2, AD2, P6) ADDVG3VCNVOR1NF = OR(AD2, P6) ADDVG2VCNVOR2NF = OR(ADDVC1, AD1, P5) ADDVG2VCNVOR1NF = OR(AD1, P5) ADDVG1VPVOR1NF = OR(AD0, P4) READYN = NAND(CT0, CT1N, CT2) CNTVCON2 = NAND(CT2, CNTVCO1) CNTVG3VZ = NAND(CNTVG3VG2VOR1NF, CNTVG3VZ1) CNTVG3VZ1 = NAND(CT2, CNTVG3VD1) CNTVCON1 = NAND(CT1, CNTVCO0) CNTVG2VZ = NAND(CNTVG2VG2VOR1NF, CNTVG2VZ1) CNTVG2VZ1 = NAND(CT1, CNTVG2VD1) CNTVG1VZ = NAND(CNTVG1VG2VOR1NF, CNTVG1VZ1) CNTVG1VZ1 = NAND(CT0, CNTVG1VD1) ADDVG1VP = NAND(ADDVG1VPVOR1NF, ADDVG1VCN) ADDVG1VCN = NAND(AD0, P4) AD0N = NAND(P0, AX0) AD1N = NAND(P0, AX1) AD2N = NAND(P0, AX2) AD3N = NAND(P0, AX3) ACVG4VD1 = NAND(ACVPCN, SM3) ACVG3VD1 = NAND(ACVPCN, SM2) ACVG2VD1 = NAND(ACVPCN, SM1) ACVG1VD1 = NAND(ACVPCN, SM0) ADSH = NOR(READY, INIT) INIT = NOR(CT0, CT1, CT2) CNTVCO2 = NOR(CNTVG3VQN, CNTVCON1) CNTVG3VD = NOR(CNTVG3VZ, START) CNTVG3VD1 = NOR(READY, CNTVCON1) CNTVCO1 = NOR(CNTVG2VQN, CNTVCON0) CNTVG2VD = NOR(CNTVG2VZ, START) CNTVG2VD1 = NOR(READY, CNTVCON0) CNTVG1VD = NOR(CNTVG1VZ, START) ADDVG4VSN = NOR(ADDVG4VCNVAD4NF, ADDVG4VCNVAD3NF) ADDVG4VCN = NOR(ADDVG4VCNVAD2NF, ADDVG4VCNVAD1NF) ADDVG3VSN = NOR(ADDVG3VCNVAD4NF, ADDVG3VCNVAD3NF) ADDVG3VCN = NOR(ADDVG3VCNVAD2NF, ADDVG3VCNVAD1NF) ADDVG2VSN = NOR(ADDVG2VCNVAD4NF, ADDVG2VCNVAD3NF) ADDVG2VCN = NOR(ADDVG2VCNVAD2NF, ADDVG2VCNVAD1NF) SMVG5VX = NOR(SMVG5VG1VAD2NF, SMVG5VG1VAD1NF) SMVG4VX = NOR(SMVG4VG1VAD2NF, SMVG4VG1VAD1NF) SMVG3VX = NOR(SMVG3VG1VAD2NF, SMVG3VG1VAD1NF) SMVG2VX = NOR(SMVG2VG1VAD2NF, SMVG2VG1VAD1NF) MRVG4VD = NOR(MRVG4VDVAD2NF, MRVG4VDVAD1NF) MRVG3VD = NOR(MRVG3VDVAD2NF, MRVG3VDVAD1NF) MRVG2VD = NOR(MRVG2VDVAD2NF, MRVG2VDVAD1NF) MRVG1VD = NOR(MRVG1VDVAD2NF, MRVG1VDVAD1NF) BMVG5VX = NOR(BMVG5VG1VAD2NF, BMVG5VG1VAD1NF) BMVG4VX = NOR(BMVG4VG1VAD2NF, BMVG4VG1VAD1NF) BMVG3VX = NOR(BMVG3VG1VAD2NF, BMVG3VG1VAD1NF) BMVG2VX = NOR(BMVG2VG1VAD2NF, BMVG2VG1VAD1NF) AMVG5VX = NOR(AMVG5VG1VAD2NF, AMVG5VG1VAD1NF) AMVG4VX = NOR(AMVG4VG1VAD2NF, AMVG4VG1VAD1NF) AMVG3VX = NOR(AMVG3VG1VAD2NF, AMVG3VG1VAD1NF) AMVG2VX = NOR(AMVG2VG1VAD2NF, AMVG2VG1VAD1NF) |