ISCAS High-Level Models These pages contain high-level models for all ISCAS-85, several of the smaller ISCAS-89, and several 74X-series circuits. These models may be freely copied and used for research purposes.
- M. Hansen, H. Yalcin, and J. P. Hayes, "Unveiling the ISCAS-85
Benchmarks: A Case Study in Reverse Engineering," IEEE Design and Test,
vol. 16, no. 3, pp. 72-80, July-Sept. 1999.
Abstract: Digital designers normally proceed from behavioral specification to logic circuit; rarely do they need to go in the reverse direction. One such situation is examined here: recovering the high-level specifications of a popular set of benchmark logic circuits. The authors present their methodology and experience in reverse engineering the ISCAS-85 circuits. They also discuss a few of the practical uses of the resulting high-level benchmarks, and make them available for other researchers to use.
The high-level ISCAS-85 benchmarks discussed in this paper are available below, and we invite other researchers to use them. The models, of which we have constructed both structural and behavioral versions, partition the original gate-level netlists into standard RTL blocks and identify the functions of these blocks. Together, the gate-level and high-level models form a set of hierarchicical benchmark circuits that have proven to be useful research tools in several areas of digital design, including test generation, timing analysis, and technology mapping. The web documentation for each model consists of annotated circuit schematic diagrams, and executable (simulatable) descriptions written in structural Verilog. The structural models are intended to express the specific high-level structure implicit in the original gate-level designs. In most cases, we also provide behavioral Verilog models, which define high-level blocks in the form of logical equations that can readily be synthesized into gates.
Acknowledgement: The reverse engineering work was carried out at the University of Michigan by Mark Hansen, Hakan Yalcin, and John Hayes. They would like to thank Hyungwon Kim for his assistance in constructing some of the Verilog models, as well as Hussain Al-Asaad and Jonathan Hauke for checking the models. Thanks are also due to Delphi Delco Electronics Systems, the National Science Foundation (under Grant No. MIP-9503463), and the Semiconductor Research Corporation for supporting various portions of the research contributing to this effort.